Science.gov

Sample records for 1-v 90-nm cmos

  1. Design and implementation of a 1-V transformer magnetic feedback low-noise amplifier (LNA) at 5-6 GHz, in a 90 nm complementary metal-oxide-semiconductor (CMOS) process

    NASA Astrophysics Data System (ADS)

    Kytonaki, Eleni-Sotiria; Simitsakis, Paschalis; Bazigos, Antonios; Papananos, Yannis

    2011-02-01

    In this study, a low-noise amplifier (LNA) suitable for low-voltage operation is presented. The LNA operates at a frequency range between 5 and 6 GHz. Its topology exploits magnetic feedback to achieve high reverse isolation and low noise performance without a significant degradation of the gain and linearity of the circuit. The design has been fabricated, considering full electrostatic discharge protection, in a modern 90 nm complementary metal-oxide-semiconductor process. The measured performance, at 5.4 GHz, shows a reverse isolation of -17.3 dB, a gain of 10.4 dB, a noise figure of 0.98 dB and an input intercept point of 1.4 dBm. The circuit dissipates 12.5 mW from a 1 V supply, while it occupies 0.162 mm2 of the die area.

  2. Radiation Performance of 1 Gbit DDR SDRAMs Fabricated in the 90 nm CMOS Technology Node

    NASA Technical Reports Server (NTRS)

    Ladbury, Raymond L.; Gorelick, Jerry L.; Berg, M. D.; Kim, H.; LaBel, K.; Friendlich, M.; Koga, R.; George, J.; Crain, S.; Yu, P.; Reed, R. A.

    2006-01-01

    We present Single Event Effect (SEE) and Total Ionizing Dose (TID) data for 1 Gbit DDR SDRAMs (90 nm CMOS technology) as well as comparing this data with earlier technology nodes from the same manufacturer.

  3. IC design of low power, wide tuning range VCO in 90 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Zhu, Li; Zhigong, Wang; Zhiqun, Li; Qin, Li; Faen, Liu

    2014-12-01

    A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET (IMOS) varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27-32.5 GHz, exhibiting a frequency tuning range (FTR) of 18.4% and a phase noise of -101.38 dBc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of -185 dBc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 mA DC current.

  4. 0.1 V 13 GHz Transformer-Based Quadrature Voltage-Controlled Oscillator with a Capacitor Coupling Technique in 90 nm Complementary Metal Oxide Semiconductor

    NASA Astrophysics Data System (ADS)

    Kamimura, Tatsuya; Lee, Sang-yeop; Tanoi, Satoru; Ito, Hiroyuki; Ishihara, Noboru; Masu, Kazuya

    2012-04-01

    A low power-supply voltage and high-frequency quadrature voltage-controlled oscillator (QVCO) using a combination of capacitor coupling and transformer feedback techniques is presented. The capacitor coupling technique can boost the transconductance of the LC-VCO core and coupling transconductance of QVCO at high frequency. Also, this technique can improve the quality factor of the QVCO at high frequency with low power-supply voltage, compared with the conventional QVCO. In addition, the capacitor coupling QVCO with transformer feedback can improve the quality factor of QVCO. Using this topology, the QVCO is able to operate at over 10 GHz with lower power-supply voltage. Implemented in the 90 nm complementary metal oxide semiconductor (CMOS) process, the proposed QVCO measures 1-MHz-offset phase noise of -94 dBc/Hz at 13 GHz while consuming 0.68 mW from a 0.1 V power-supply.

  5. 25Gb/s 1V-driving CMOS ring modulator with integrated thermal tuning.

    PubMed

    Li, Guoliang; Zheng, Xuezhe; Yao, Jin; Thacker, Hiren; Shubin, Ivan; Luo, Ying; Raj, Kannan; Cunningham, John E; Krishnamoorthy, Ashok V

    2011-10-10

    We report a high-speed ring modulator that fits many of the ideal qualities for optical interconnect in future exascale supercomputers. The device was fabricated in a 130 nm SOI CMOS process, with 7.5 μm ring radius. Its high-speed section, employing PN junction that works at carrier-depletion mode, enables 25 Gb/s modulation and an extinction ratio >5 dB with only 1V peak-to-peak driving. Its thermal tuning section allows the device to work in broad wavelength range, with a tuning efficiency of 0.19 nm/mW. Based on microwave characterization and circuit modeling, the modulation energy is estimated ~7 fJ/bit. The whole device fits in a compact 400 μm2 footprint. PMID:21997052

  6. A 1-V TSPC Dual Modulus Prescaler with Speed Scalability Using Forward Body Biasing in 0.18µm CMOS

    NASA Astrophysics Data System (ADS)

    Shin, Hyunchol

    The operating speed scalability is demonstrated by using the forward body biasing method for a 1-V 0.18-µm CMOS true single-phase clocking (TSPC) dual-modulus prescaler. With the forward body bias voltage varying between 0 and 0.4V, the maximum operating speed changes by about 40-50% and the maximum input sensitivity frequency changes by about 400%. This speed scalability is achieved with less than 0.5-dB phase noise degradation. This demonstration indicates that the forward body biasing method is instrumental to build a cost-saving power-efficient 1-V 0.18-µm CMOS radio for low-power WBAN and WSN applications.

  7. Improved overlay metrology device correlation on 90-nm logic processes

    NASA Astrophysics Data System (ADS)

    Ueno, Atsushi; Tsujita, Kouichirou; Kurita, Hiroyuki; Iwata, Yasuhisa; Ghinovker, Mark; Poplawski, Jorge M.; Kassel, Elyakim; Adel, Mike E.

    2004-05-01

    Isolated and dense patterns were formed at process layers from gate through to back-end on wafers using a 90 nm logic device process utilizing ArF lithography under various lithography conditions. Pattern placement errors (PPE) between AIM grating and BiB marks were characterized for line widths varying from 1000nm to 140nm. As pattern size was reduced, overlay discrepancies became larger, a tendency which was confirmed by optical simulation with simple coma aberration. Furthermore, incorporating such small patterns into conventional marks resulted in significant degradation in metrology performance while performance on small pattern segmented grating marks was excellent. Finally, the data also show good correlation between the grating mark and specialized design rule feature SEM marks, with poorer correlation between conventional mark and SEM mark confirming that new grating mark significantly improves overlay metrology correlation with device patterns.

  8. A low power 20 GHz comparator in 90 nm COMS technology

    NASA Astrophysics Data System (ADS)

    Kai, Tang; Qiao, Meng; Zhigong, Wang; Ting, Guo

    2014-05-01

    A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters (ADCs) is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic (SCL) topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second (GSps) with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications.

  9. Practicality of Evaluating Soft Errors in Commercial sub-90 nm CMOS for Space Applications

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan A.; LaBel, Kenneth A.

    2010-01-01

    The purpose of this presentation is to: Highlight space memory evaluation evolution, Review recent developments regarding low-energy proton direct ionization soft errors, Assess current space memory evaluation challenges, including increase of non-volatile technology choices, and Discuss related testing and evaluation complexities.

  10. A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process

    NASA Astrophysics Data System (ADS)

    Mingyuan, Yu; Ting, Li; Jiaqi, Yang; Shuangshuang, Zhang; Fujiang, Lin; Lin, He

    2016-07-01

    This paper presents a 10-bit 50-MS/s subrange successive-approximation register (SAR) analog-to-digital converter (ADC) composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi-comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1P8M 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes 186 μW at 50 MS/s with a 1-V supply, resulting in a figure of merit (FOM) of 12 fJ/conversion-step. The core area is only 0.045 mm2. Project supported by the National Natural Science Foundation of China (Nos. 61204033, 61331015), the Fundamental Research Funds for the Central Universities (No. WK2100230015), and the Funds of Science and Technology on Analog Integrated Circuit Laboratory (No. 9140C090111150C09041).

  11. Achieving CDU requirement for 90-nm technology node and beyond with advanced mask making process technology

    NASA Astrophysics Data System (ADS)

    Tzu, San-De; Chang, Chung-Hsing; Chen, Wen-Chi; Kliem, Karl-Heinz; Hudek, Peter; Beyer, Dirk

    2005-01-01

    For 90nm node and beyond technology generations, one of the most critical challenges is how to meet the local CD uniformity (proximity) and global CD uniformity (GCDU) requirements within the exposure field. Both of them must be well controlled in the mask making process: (1) proximity effect and, (2) exposure pattern loading effect, or the so-called e-beam "fogging effect". In this paper, we report a method to improve our global CDU by means of a long range fogging compensation together with the Leica SB350 MW. This exposure tool is operated at 50keV and 1nm design grid. The proximity correction is done by the software - package "PROXECCO" from PDF Solutions. We have developed a unique correction method to reduce the fogging effect in dependency of the pattern density of the mask. This allows us to meet our customers" CDU specifications for the 90nm node and beyond.

  12. FPGA chip performance improvement with gate shrink through alternating PSM 90nm process

    NASA Astrophysics Data System (ADS)

    Yu, Chun-Chi; Shieh, Ming-Feng; Liu, Erick; Lin, Benjamin; Ho, Jonathan; Wu, Xin; Panaite, Petrisor; Chacko, Manoj; Zhang, Yunqiang; Lei, Wen-Kang

    2005-11-01

    In the post-physical verification space called 'Mask Synthesis' a key component of design-for-manufacturing (DFM), double-exposure based, dark-field, alternating PSM (Alt-PSM) is being increasingly applied at the 90nm node in addition with other mature resolution enhancement techniques (RETs) such as optical proximity correction (OPC) and sub-resolution assist features (SRAF). Several high-performance IC manufacturers already use alt-PSM technology in 65nm production. At 90nm having strong control over the lithography process is a critical component in meeting targeted yield goals. However, implementing alt-PSM in production has been challenging due to several factors such as phase conflict errors, mask manufacturing, and the increased production cost due to the need for two masks in the process. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a mature, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. With minimum design changes, design houses usually are motivated by higher product performance for the existing designs. What follows is an in-depth review of the motivation to apply alt-PSM on a production FPGA, the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.

  13. Monolithic integration of high bandwidth waveguide coupled Ge photodiode in a photonic BiCMOS process

    NASA Astrophysics Data System (ADS)

    Lischke, S.; Knoll, D.; Zimmermann, L.

    2015-03-01

    Monolithic integration of photonic functionality in the frontend-of-line (FEOL) of an advanced microelectronics technology is a key step towards future communication applications. This combines photonic components such as waveguides, couplers, modulators, and photo detectors with high-speed electronics plus shortest possible interconnects crucial for high-speed performance. Integration of photonics into CMOS FEOL is therefore in development for quite some time reaching 90nm node recently [1]. However, an alternative to CMOS is high-performance BiCMOS, offering significant advantages for integrated photonics-electronics applications with regard to cost and RF performance. We already presented results of FEOL integration of photonic components in a high-performance SiGe:C BiCMOS baseline to establish a novel, photonic BiCMOS process. Process cornerstone is a local-SOI approach which allows us to fabricate SOI-based, thus low-loss photonic components in a bulk BiCMOS environment [2]. A monolithically integrated 10Gbit/sec Silicon modulator with driver was shown here [3]. A monolithically integrated 25Gbps receiver was presented in [4], consisting of 200GHz bipolar transistors and CMOS devices, low-loss waveguides, couplers, and highspeed Ge photo diodes showing 3-dB bandwidth of 35GHz, internal responsivity of more than 0.6A/W at λ= 1.55μm, and ~ 50nA dark current at 1V. However, the BiCMOS-given thermal steps cause a significant smearing of the Germanium photo diodes doping profile, limiting the photo diode performance. Therefore, we introduced implantation of non-doping elements to overcome such limiting factors, resulting in photo diode bandwidths of more than 50GHz even under the effect of thermal steps necessary when the diodes are integrated in a high performance BiCMOS process.

  14. Resolution of 90 nm (lambda/5) in an optical transmission microscope with an annular condenser.

    PubMed

    Vainrub, Arnold; Pustovyy, Oleg; Vodyanoy, Vitaly

    2006-10-01

    Resolution of 90 nm was achieved with a research microscope simply by replacing the standard bright-field condenser with a homebuilt illumination system with a cardioid annular condenser. Diffraction gratings with 100 nm width lines as well as less than 100 nm size features of different-shaped objects were clearly visible on a calibrated microscope test slide. The resolution increase results from a known narrower diffraction pattern in coherent illumination for the annular aperture compared with the circular aperture. This explanation is supported by an excellent accord of calculated and measured diffraction patterns for a 50 nm radius disk. PMID:16969401

  15. Resolution of 90 nm (λ/5) in an optical transmission microscope with an annular condenser

    NASA Astrophysics Data System (ADS)

    Vainrub, Arnold; Pustovyy, Oleg; Vodyanoy, Vitaly

    2006-10-01

    Resolution of 90 nm was achieved with a research microscope simply by replacing the standard bright-field condenser with a homebuilt illumination system with a cardioid annular condenser. Diffraction gratings with 100 nm width lines as well as less than 100 nm size features of different-shaped objects were clearly visible on a calibrated microscope test slide. The resolution increase results from a known narrower diffraction pattern in coherent illumination for the annular aperture compared with the circular aperture. This explanation is supported by an excellent accord of calculated and measured diffraction patterns for a 50 nm radius disk.

  16. A 1V low power second-order delta-sigma modulator for biomedical signal application.

    PubMed

    Hsu, Chih-Han; Tang, Kea-Tiong

    2013-01-01

    This paper presents the design and implementation of a low-power delta-sigma modulator for biomedical application with a standard 90 nm CMOS technology. The delta-sigma architecture is implemented as 2nd order feedforward architecture. A low quiescent current operational transconductance amplifier (OTA) is utilized to reduce power consumption. This delta-sigma modulator operated in 1V power supply, and achieved 64.87 dB signal to noise distortion ratio (SNDR) at 10 KHz bandwidth with an oversampling ratio (OSR) of 64. The power consumption is 17.14 µW, and the figure-of-merit (FOM) is 0.60 pJ/conv. PMID:24110111

  17. Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

    NASA Astrophysics Data System (ADS)

    Yin, Lan; Bozler, Carl; Harburg, Daniel V.; Omenetto, Fiorenzo; Rogers, John A.

    2015-01-01

    Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

  18. ArF processing of 90-nm design rule lithography achieved through enhanced thermal processing

    NASA Astrophysics Data System (ADS)

    Kagerer, Markus; Miller, Daniel; Chang, Wayne; Williams, Daniel J.

    2006-03-01

    As the lithography community has moved to ArF processing on 300 mm wafers for 90 nm design rules the process characterization of the components of variance continues to highlight the thermal requirements for the post exposure bake (PEB) processing step. In particular as the thermal systems have become increasingly uniform, the transient behavior of the thermal processing system has received the focus of attention. This paper demonstrates how a newly designed and patented thermal processing system was optimized for delivering improved thermal uniformity during a typical 90 second PEB processing cycle, rather than being optimized for steady state performance. This was accomplished with the aid of a wireless temperature measurement wafer system for obtaining real time temperature data and by using a response surface model (RSM) experimental design for optimizing parameters of the temperature controller of the thermal processing system. The new units were field retrofitted seamlessly in <2 days at customer sites without disruption to process recipes or flows. After evaluating certain resist parameters such as PEB temperature sensitivity and post exposure delay (PED) - stability of the baseline process, the new units were benchmarked against the previous PEB plates by processing a split lot experiment. Additional hardware characterization included environmental factors such as air velocity in the vicinity of the PEB plates and transient time between PEB and chill plate. At the completion of the optimization process, the within wafer CD uniformity displayed a significant improvement when compared to the previous hardware. The demonstrated within wafer CD uniformity improved by 27% compared to the initial hardware and baseline process. ITRS requirements for the 90 nm node were exceeded.

  19. Optimum PEC Conditions Under Resist Heating Effect Reduction for 90nm Node Mask Writing

    NASA Astrophysics Data System (ADS)

    Park, Eu Sang; Lee, Jong Hwa; Park, Dong Il; Jeong, Woo Gun; Seo, Soon Kyu; Kim, Jin Min; Choi, Sang-Soo; Jeong, Soo-Hong

    2002-12-01

    For high-voltage vector e-beam writing systems, solving the resist heating effect problem is one of the highest priorities because it is a major factor affecting localized critical dimension (CD) uniformity. In order to write patterns for 90nm node devices, the utilization of proximity effect correction (PEC) is essential for e-beam mask writers to achieve high CD performance. In this study, the dependence of CD variation on e-beam write conditions was investigated under optimum PEC parameter conditions. Writing conditions such as current density, shot size, number of writing passes, and settling time were tested to see their affects on resist heating. Industry-standard Nippon Zeon ZEP 7000 resist was written by a Toshiba EBM-3500B 50KeV vector e-beam writer using patterns found in sub-130nm node devices. Results indicated that the main factor affecting resist heating CD variation for ZEP 7000 was in fact the e-beam writer shot size selected. Multi-pass writing was effective in reducing the CD variation, and the settling time of each shot in the EBM-3500B had very little influence.

  20. In-line 90 nm Technology Gate Oxide Nitrogen Monitoring With Non-Contact Electrical Technique

    NASA Astrophysics Data System (ADS)

    Pic, Nicolas; Polisski, Gennadi; Paire, Emmanuel; Rizzo, Véronique; Grosjean, Catherine; Bortolotti, Benjamin; D'Amico, John; Cabuil, Nicolas

    2009-09-01

    The continuous race to reduce the dimensions of IC components has lead to the introduction of Nitrogen in the thin gate oxide layer in order to increase the dielectric constant and to improve the gate dielectric properties. It is mandatory to apply in-line monitoring to control the amount of Nitrogen to ensure that electrical behavior is correct over time. Historically, this monitoring was performed by measuring the delay to reoxidation (D2R) with an ellipsometer. But, this method is not suitable in production as it is depending on both initial oxidation and reoxidation reproducibility, which implies implementing dedicated Statistical Process Control (SPC) monitoring at these two specific processing steps. We are here presenting an alternative method to D2R for 90 nm Technology gate oxide grown by Rapid Thermal Process (RTP). Applying a non-contact Metrology technique, which couples Kelvin probe surface voltage measurement with surface Corona deposition, directly after the nitridation step, the interface trapped charge (QIT) is obtained by integration of the interface state density over the space charge region. In summary, this electrical non-contact monitoring is more sensitive to the Nitrogen content compared to ellipsometer measurement after nitridation or after D2R, less sensitive compared to D2R to any initial oxide variation, and it allows simplification of the qualification procedure at this process step by skipping the reoxidation.

  1. Asymmetric MQW semiconductor optical amplifier with low-polarization sensitivity of over 90-nm bandwidth

    NASA Astrophysics Data System (ADS)

    Nkanta, Julie E.; Maldonado-Basilio, Ramón; Abdul-Majid, Sawsan; Zhang, Jessica; Hall, Trevor J.

    2013-12-01

    An exhausted capacity of current Passive Optical Networks has been anticipated as bandwidth-hungry applications such as HDTV and 3D video become available to end-users. To enhance their performance, the next generation optical access networks have been proposed, using optical carriers allocated within the E-band (1360-1460 nm). It is partly motivated by the low-water peak fiber being manufactured by Corning. At these wavelengths, choices for low cost optical amplifiers, with compact size, low energy consumption and feasibility for integration with other optoelectronic components are limited, making the semiconductor optical amplifiers (SOA) a realistic solution. An experimental characterization of a broadband and low polarization sensitive asymmetric multi quantum well (MQW) SOA operating in the E-band is reported. The SOA device is composed of nine 6 nm In1-xGaxAsyP1-y 0.2% tensile strained asymmetric MQW layers sandwiched between nine latticed matched 6 nm InGaAsP barrier layers. The active region is grown on an n-doped InP substrate and buried by p-doped InGaAsP layers. The SOA devices have 7-degrees tilt anti-reflected coated facets, with 2 μm ridge width, and a cavity length of 900 μm. For input powers of -10 dBm and -20 dBm, a maximum gain of 20 dB at 1360 nm with a polarization insensitivity under 3 dB for over 90 nm bandwidth is measured. Polarization sensitivity of less than 0.5 dB is observed for some wavelengths. Obtained results indicate a promising SOA with broadband amplification, polarization insensitivity and high gain. These SOAs were designed and characterized at the Photonics Technology Laboratory, University of Ottawa, Canada.

  2. DOE experiment for scattering bars optimization at the 90nm node

    NASA Astrophysics Data System (ADS)

    Bouton, G.; Connolly, B.; Courboin, D.; Di Giacomo, A.; Gasnier, F.; Lallement, R.; Parker, D.; Pindo, M.; Richoilley, J. C.; Royere, F.; Rameau-Savio, A.; Tissier, M.

    2011-03-01

    Scattering bars (SB) are sub-resolution lines added to the original database during Resolution Enhancement Techniques (RET) treatments. Their goal is stabilizing the CD of the adjacent polygons (by suppressing or reducing secondary diffraction waves). SB increase the process window in the litho process by lowering the first derivative of the CD. Moreover, the detailed knowledge of SB behavior around the fab working point is a must for future shrinks and for preparing the next technology nodes. SB are inserted in the generation of critical levels for STMicroelectronics 90 nm technology embedded memories before invoking the Model for Optical Proximity Corrections (MBOPC). This allows the software to calculate their contribution to the intensity in the aerial image and integrate their effects in Edge Proximity Error (EPE) corrections. However the Rule-Based insertion of these assist features still leaves behind occurrences of conflicting priorities as in the image below. (See manuscript PDF)Detection of Hot Spots in 2D simulations for die treatment validation (done on BRION equipment on each critical level before mask making) is in most cases correlated with SB singularities, at least for CD non-uniformity, bridging issues and necking in correspondence with OPC fragmentation effects. Within the framework of the MaXSSIMM project, we established a joint STMicroelectronics and Toppan Photomasks team to explore the influence of assist features (CD, distance), convex and concave corner rounding and CD uniformity by means of specific test patterns. The proposed study concerns the algorithms used to define the mask shop input as well as the physical mask etching. A set of test cases, based on elementary test patterns, each one including a list of geometrical variations, has been defined. As the number of configurations becomes rapidly very large (tens of thousands) we had to apply Design of Experiments (DOE) algorithms in order to reduce the number of measurements to a

  3. Phase-change memory technology with self-aligned μTrench cell architecture for 90 nm node and beyond

    NASA Astrophysics Data System (ADS)

    Pirovano, A.; Pellizzer, F.; Tortorelli, I.; Riganó, A.; Harrigan, R.; Magistretti, M.; Petruzza, P.; Varesi, E.; Redaelli, A.; Erbetta, D.; Marangon, T.; Bedeschi, F.; Fackenthal, R.; Atwood, G.; Bez, R.

    2008-09-01

    A novel self-aligned μTrench-based cell architecture for phase change memory (PCM) process is presented. The low programming current and the good dimensional control of the sub-lithographic features achieved with the μTrench structure are combined with a self-aligned patterning strategy that simplify the integration process in term of alignment tolerances and of number of critical masks. The proposed architecture has been integrated in a 90 nm 128 Mb vehicle based on a pnp bipolar junction transistor for the array selection. The good active and leakage currents achieved by the purposely optimized selecting transistors combined with programming currents of 300 μA of the storage element and good distributions measured on the 128 Mb array demonstrate the suitability of the proposed architecture for the production of high-density PCM arrays at 90 nm and beyond.

  4. Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodes

    NASA Astrophysics Data System (ADS)

    Nogami, T.; Lane, S.; Fukasawa, M.; Ida, K.; Angyal, M.; Chanda, K.; Chen, F.; Christiansen, C.; Cohen, S.; Cullinan, M.; Dziobkowski, C.; Fitzsimmons, J.; Flaitz, P.; Grill, A.; Gill, J.; Inoue, K.; Klymko, N.; Kumar, K.; Labelle, C.; Lane, M.; Li, B.; Liniger, E.; Madon, A.; Malone, K.; Martin, J.; McGahay, V.; McLaughlin, P.; Melville, I.; Minami, M.; Molis, S.; Nguyen, S.; Penny, C.; Restaino, D.; Sakamoto, A.; Sankar, M.; Sherwood, M.; Simonyi, E.; Shimooka, Y.; Tai, L.; Widodo, J.; Wildman, H.; Ono, M.; McHerron, D.; Nye, H.; Davis, C.; Sankaran, S.; Edelstein, D.; Ivers, T.

    2005-11-01

    This paper discusses low-k/copper integration schemes which has been in production in the 90 nm node, have been developed in the 65 nm node, and should be taken in the 45 nm node. While our baseline 65 nm BEOL process has been developed by extension and simple shrinkage of our PECVD SiCOH integration which has been in production in the 90 nm node with our SiCOH film having k=3.0, the 65 nm SiCOH integration has two other options to go to extend to lower capacitance. One is to add porosity to become ultra low-k (ULK). The other is to stay with low-k SiCOH, which is modified to have a "lower-k". The effective k- value attained with the lower-k (k=2.8) SiCOH processed in the "Direct CMP" scheme is very close to that with an ULK (k=2.5) SiCOH film built with the "Hard Mask Retention" scheme. This paper first describes consideration of these two damascene schemes, whose comparison leads to the conclusion that the lower-k SiCOH integration can have more advantages in terms of process simplicity and extendibility of our 90 nm scheme under certain assumptions. Then describing the k=2.8 SiCOH film development and its successful integration, damascene schemes for 45nm nodes are discussed based on our learning from development of the lower-k 65nm scheme. Capability of modern dry etchers to define the finer patterns, non-uniformity of CMP, and susceptibility to plasma and mechanical strength and adhesion of ULK are discussed as factors to hamper the applicability of ULK.

  5. Evaluation of soft error rates using nuclear probes in bulk and SOI SRAMs with a technology node of 90 nm

    NASA Astrophysics Data System (ADS)

    Abo, Satoshi; Masuda, Naoyuki; Wakaya, Fujio; Onoda, Shinobu; Hirao, Toshio; Ohshima, Takeshi; Iwamatsu, Toshiaki; Takai, Mikio

    2010-06-01

    The difference of soft error rates (SERs) in conventional bulk Si and silicon-on-insulator (SOI) static random access memories (SRAMs) with a technology node of 90 nm has been investigated by helium ion probes with energies ranging from 0.8 to 6.0 MeV and a dose of 75 ions/μm 2. The SERs in the SOI SRAM were also investigated by oxygen ion probes with energies ranging from 9.0 to 18.0 MeV and doses of 0.14-0.76 ions/μm 2. The soft error in the bulk and SOI SRAMs occurred by helium ion irradiation with energies at and above 1.95 and 2.10 MeV, respectively. The SER in the bulk SRAM saturated with ion energies at and above 2.5 MeV. The SER in the SOI SRAM became the highest by helium ion irradiation at 2.5 MeV and drastically decreased with increasing the ion energies above 2.5 MeV, in which helium ions at this energy range generated the maximum amount of excess charge carriers in a SOI body. The soft errors occurred by helium ions were induced by a floating body effect due to generated excess charge carriers in the channel regions. The soft error occurred by oxygen ion irradiation with energies at and above 10.5 MeV in the SOI SRAM. The SER in the SOI SRAM gradually increased with energies from 10.5 to 13.5 MeV and saturated at 18 MeV, in which the amount of charge carriers induced by oxygen ions in this energy range gradually increased. The computer calculation indicated that the oxygen ions with energies above 13.0 MeV generated more excess charge carriers than the critical charge of the 90 nm node SOI SRAM with the designed over-layer thickness. The soft errors, occurred by oxygen ions with energies at and below 12.5 MeV, were induced by a floating body effect due to the generated excess charge carriers in the channel regions and those with energies at and above 13.0 MeV were induced by both the floating body effect and generated excess carriers. The difference of the threshold energy of the oxygen ions between the experiment and the computer calculation might

  6. Ion traps fabricated in a CMOS foundry

    SciTech Connect

    Mehta, K. K.; Ram, R. J.; Eltony, A. M.; Chuang, I. L.; Bruzewicz, C. D.; Sage, J. M. Chiaverini, J.

    2014-07-28

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  7. Nanoscale dimensional focused ion beam repair of quartz defects on 90-nm node alternating aperture phase shift masks

    NASA Astrophysics Data System (ADS)

    Robinson, Tod E.; Graupera, Anthony; Morrison, Troy B.; Ramstein, Marcus

    2004-08-01

    The effort to produce perfect dimension repairs of quartz bump defects on Alternating-Aperture Phase Shift Masks (AAPSM) has been brought to a new level with process developments to meet 90 nm technology node specifications. Decreasing photomask line and space dimensions pushes performance requirements for a mask repair system in terms of fine control in difficult to access structures on the mask surface. New repair strategies using a recently improved focused ion beam mask repair system for different defect types are discussed, along with their relative effectiveness. These strategies are then applied to the repair of full height extension and bridging defects in a line and space array. The role of quartz topography and its optical effects, Cr edge bias, and the combination of both strategies in a quartz bump repair are discussed. Additionally, effective process controls in repair are also discussed, along with analysis of metrology data received from a stylus nano-profilometer (SNP) system, and their relationship to potential imaging on the wafer by examination of AIMS data at a high numerical aperture. Several possible mask repair process flows are also reviewed in light of this work.

  8. Improved Programming Efficiency through Additional Boron Implantation at the Active Area Edge in 90 nm Localized Charge-Trapping Non-volatile Memory

    NASA Astrophysics Data System (ADS)

    Xu, Yue; Yan, Feng; Chen, Dun-Jun; Shi, Yi; Wang, Yong-Gang; Li, Zhi-Guo; Yang, Fan; Wang, Jos-Hua; Lin, Peter; Chang, Jian-Guang

    2010-06-01

    As the scaling-down of non-volatile memory (NVM) cells continues, the impact of shallow trench isolation (STI) on NVM cells becomes more severe. It has been observed in the 90 nm localized charge-trapping non-volatile memory (NROM™) that the programming efficiency of edge cells adjacent to STI is remarkably lower than that of other cells when channel hot electron injection is applied. Boron segregation is found to be mainly responsible for the low programming efficiency of edge cells. Meanwhile, an additional boron implantation of 10° tilt at the active area edge as a new solution to solve this problem is developed.

  9. Advanced mask technique to improve bit line CD uniformity of 90 nm node flash memory in low-k1 lithography

    NASA Astrophysics Data System (ADS)

    Kim, Jong-doo; Choi, Jae-young; Kim, Jea-hee; Han, Jae-won

    2008-10-01

    As devices size move toward 90nm technology node or below, defining uniform bit line CD of flash devices is one of the most challenging features to print in KrF lithography. There are two principal difficulties in defining bit line on wafer. One is insufficient process margin besides poor resolution compared with ArF lithography. The other is that asymmetric bit line should be made for OPC(Optical Proximity Correction) modeling. Therefore advanced ArF lithography scanner should be used for define bit line with RETs (Resolution Enhancement Techniques) such as immersion lithography, OPC, PSM(Phase Shift Mask), high NA(Numerical Aperture), OAI(Off-Axis Illumination), SRAF(Sub-resolution Assistant Feature), and mask biasing.. Like this, ArF lithography propose the method of enhancing resolution, however, we must spend an enormous amount of CoC(cost of ownership) to utilize ArF photolithography process than KrF. In this paper, we suggest method to improve of bit line CD uniformity, patterned by KrF lithographic process in 90nm sFlash(stand alone Flash) devices. We applied new scheme of mask manufacturing, which is able to realize 2 different types of mask, binary and phase-shift, into one plate. Finally, we could get the more uniform bit lines and we expect to get more stable properties then before applying this technique.

  10. Yb:CaGdAlO4 thin-disk laser with 70% slope efficiency and 90 nm wavelength tuning range.

    PubMed

    Beil, Kolja; Deppe, Bastian; Kränkel, Christian

    2013-06-01

    Thin-disk laser experiments with Yb:CaGdAlO(4) (Yb:CALGO) have been performed. A slope efficiency of 70% and an optical-to-optical efficiency of 57% could be achieved with a maximum output power of 30.7 W. These are so far the highest efficiencies obtained with this material. Furthermore, tuning experiments were carried out leading to a tuning range of 90 nm in total and 50 nm with more than 20 W of output power. This is to the best of our knowledge the widest wavelength tuning range of any material demonstrated at this power level. For all experiments the thermal evolution of the crystal surface temperature during laser operation was investigated. PMID:23722805

  11. A novel colour-sensitive CMOS detector

    NASA Astrophysics Data System (ADS)

    Langfelder, G.; Longoni, A.; Zaraga, F.

    2009-10-01

    A novel colour-sensitive semiconductor detector is proposed. The device (named Transverse Field Detector (TFD)) can be used to measure the colour of the incident light without any colour filter. The device is completely compatible with standard CMOS processes and is suitable to be integrated in a pixel array for imaging purposes. The working principle is based on the capability of this device to collect at different superficial junctions the carriers, generated at different depths, by means of suitable transverse electric fields. The transverse components of the electric field are generated inside the depleted region by a suitable bias of the superficial junctions. Thanks to the differences in the light absorption coefficients at different wavelengths, the device performs colour separation. Among the advantages of this approach are the capability of an active tuning of the pixel colour response, which can be obtained just by changing the biasing values of collecting junctions, and foreseen higher colour fidelity, thanks to the easy extension to four colour pixels. First test structures of three colours TFD pixels were designed and built in a standard CMOS 90 nm technology. Operative principles of the device and first experimental results are presented.

  12. A scalable neural chip with synaptic electronics using CMOS integrated memristors

    NASA Astrophysics Data System (ADS)

    Cruz-Albrecht, Jose M.; Derosier, Timothy; Srinivasa, Narayan

    2013-09-01

    The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

  13. CAOS-CMOS camera.

    PubMed

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems. PMID:27410361

  14. DFM in practice: results of a three way partnership between a leading fabless design house, foundry, and EDA company to implement alternating-phase shift mask (Alt-PSM) on a 90-nm FPGA chip

    NASA Astrophysics Data System (ADS)

    Yu, Chun-Chi; Shieh, Ming-Feng; Liu, Erick; Lin, Benjamin; Lin, Henry; Chacko, Manoj; Li, Xiaoyang; Lei, Wen-Kang; Ho, Jonathan; Wu, Xin

    2005-05-01

    At the sub 90nm nodes, resolution enhancement techniques (RETs) such as optical proximity correction (OPC), phase-shifting masks (PSM), sub-resolution assist features (SRAF) have become essential steps in the post-physical verification 'Mask Synthesis' process and a key component of design for manufacturing (DFM). Several studies have been conducted and the results have been published on the implication and application of the different types of RETs on mask printability and costs. More specifically, double-exposure-based, dark-field, alternating PSM (Alt-PSM) technology has received lot of attention with respect to the mask manufacturing challenges and its implementation into a production flow, despite its yield and critical dimension (CD) control superiority. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a matured, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. What follows is an in-depth review of the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.

  15. Further developments on a novel color sensitive CMOS detector

    NASA Astrophysics Data System (ADS)

    Langfelder, G.; Longoni, A.; Zaraga, F.

    2009-05-01

    The Transverse Field Detector (TFD) is a recently proposed Silicon pixel device designed to perform color imaging without the use of color filters. The color detection principle is based on the dependence of the Silicon absorption coefficient from the wavelength and relies on the generation of a suitable transverse electric field configuration, within the semiconductor active layer, to drive photocarriers generated at different depths towards different collecting electrodes. Each electrode has in this way a different spectral response with respect to the incoming wavelength. Pixels with three or four different spectral responses can be implemented within ~ 6 μm of pixel dimension. Thanks to the compatibility with standard triple well CMOS processes, the TFD can be used in an Active Pixel Sensor exploiting a dedicated readout topology, based on a single transistor charge amplifier. The overall APS electronics includes five transistors (5T) and a feedback capacitance, with a resulting overall fill factor around 50%. In this work the three colors and four colors TFD pixel simulations and implementations in a 90 nm standard CMOS triple well technology are described. Details on the design of a TFD APS mini matrix are provided and preliminary experimental results on four colors pixels are presented.

  16. Implantable CMOS Biomedical Devices

    PubMed Central

    Ohta, Jun; Tokuda, Takashi; Sasagawa, Kiyotaka; Noda, Toshihiko

    2009-01-01

    The results of recent research on our implantable CMOS biomedical devices are reviewed. Topics include retinal prosthesis devices and deep-brain implantation devices for small animals. Fundamental device structures and characteristics as well as in vivo experiments are presented. PMID:22291554

  17. CCD and CMOS sensors

    NASA Astrophysics Data System (ADS)

    Waltham, Nick

    The charge-coupled device (CCD) has been developed primarily as a compact image sensor for consumer and industrial markets, but is now also the preeminent visible and ultraviolet wavelength image sensor in many fields of scientific research including space-science and both Earth and planetary remote sensing. Today"s scientific or science-grade CCD will strive to maximise pixel count, focal plane coverage, photon detection efficiency over the broadest spectral range and signal dynamic range whilst maintaining the lowest possible readout noise. The relatively recent emergence of complementary metal oxide semiconductor (CMOS) image sensor technology is arguably the most important development in solid-state imaging since the invention of the CCD. CMOS technology enables the integration on a single silicon chip of a large array of photodiode pixels alongside all of the ancillary electronics needed to address the array and digitise the resulting analogue video signal. Compared to the CCD, CMOS promises a more compact, lower mass, lower power and potentially more radiation tolerant camera.

  18. Regenerative switching CMOS system

    DOEpatents

    Welch, J.D.

    1998-06-02

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

  19. Regenerative switching CMOS system

    DOEpatents

    Welch, James D.

    1998-01-01

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

  20. Automation of CMOS technology migration illustrated by RGB to YCrCb analogue converter

    NASA Astrophysics Data System (ADS)

    Naumowicz, M.; Melosik, M.; Katarzynski, P.; Handkiewicz, A.

    2013-09-01

    The paper illustrates a practical example of technology migration applied to the colour space converter realized in CMOS technology. The element has analogue excitation and response signals expressed in current mode. Such converter may be incorporated into an integrated vision sensor for preconditioning acquired image data. The idea of a computer software tool supporting the automated migration and design reuse is presented as the major contribution. The mentioned tools implement the Hooke-Jeeves direct search method for performing the multivariable optimization. Our purpose is to ensure transferring the circuit between usable fabrication technologies and preserving its functional properties. The colour space converter is treated as the case study for performance evaluation of the proposed tool in cooperation with HSPICE simulation software. The original CMOS technology files for Taiwan semiconductor (TSMC) plant were utilized for the research. The automated design migration from 180 nm into 90 nm resulted with obtaining compact IC layout characterized by a smaller area and lower power consumption. The paper is concluded with a brief summary that proves the usability of the proposed tool in designing CMOS cells dedicated for low power image processing.

  1. Large area CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; Guerrini, N.; Sedgwick, I.

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  2. CMOS Integrated Carbon Nanotube Sensor

    SciTech Connect

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

    2009-05-23

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  3. Neutron diffusion in graphite poisoned with 1/v and non-1/v absorbers

    SciTech Connect

    Malik, U.; Kothari, L.S.; Kumar, A.

    1982-05-01

    Neutron diffusion in graphite containing 1/v and non-1/v absorbers has been studied in the diffusion theory approximation using a multigroup (30-group) approach and the neutron scattering kernel proposed earlier by the authors. It is observed that, in this case as in the case of water investigated earlier, the behavior of neutrons in graphite poisoned with gadolinium is different from that in graphite poisoned with samarium or cadmium. To explain the reason for this difference, a hypothetical model for the energy variation of the absorption cross section has been constructed that closely resembles samarium in one limit and goes over to gadolinium in the other. The effect of varying the concentration of non-1/v absorbers on the flux of sub-Bragg and epicold neutrons has been studied for this model, and some interesting results are obtained.

  4. High-voltage CMOS detectors

    NASA Astrophysics Data System (ADS)

    Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

    2016-07-01

    High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented.

  5. CMOS output buffer wave shaper

    NASA Technical Reports Server (NTRS)

    Albertson, L.; Whitaker, S.; Merrell, R.

    1990-01-01

    As the switching speeds and densities of Digital CMOS integrated circuits continue to increase, output switching noise becomes more of a problem. A design technique which aids in the reduction of switching noise is reported. The output driver stage is analyzed through the use of an equivalent RLC circuit. The results of the analysis are used in the design of an output driver stage. A test circuit based on these techniques is being submitted to MOSIS for fabrication.

  6. Fabrication of CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Malinovich, Yacov; Koltin, Ephie; Choen, David; Shkuri, Moshe; Ben-Simon, Meir

    1999-04-01

    In order to provide its customers with sub-micron CMOS fabrication solutions for imaging applications, Tower Semiconductor initiated a project to characterize the optical parameters of Tower's 0.5-micron process. A special characterization test chip was processed using the TS50 process. The results confirmed a high quality process for optical applications. Perhaps the most important result is the process' very low dark current, of 30-50 pA/cm2, using the entire window of process. This very low dark current characteristic was confirmed for a variety of pixel architectures. Additionally, we have succeeded to reduce and virtually eliminate the white spots on large sensor arrays. As a foundry Tower needs to support fabrication of many different imaging products. Therefore we have developed a fabrication methodology that is adjusted to the special needs of optical applications. In order to establish in-line process monitoring of the optical parameters, Tower places a scribe line optical test chip that enables wafer level measurements of the most important parameters, ensuring the optical quality and repeatability of the process. We have developed complementary capabilities like in house deposition of color filter and fabrication of very large are dice using sub-micron CMOS technologies. Shellcase and Tower are currently developing a new CMOS image sensor optical package.

  7. CMOS downsizing toward sub-10 nm

    NASA Astrophysics Data System (ADS)

    Iwai, Hiroshi

    2004-04-01

    Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 6 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing such small-geometry MOSFETs into large scale integrated circuits, and it is still questionable whether we can successfully introduce sub-10 nm CMOS LSIs into the market or not. In this paper, limitation and its possible causes for the downscaling of CMOS towards sub-10 nm are discussed with consideration of past CMOS predictions for the limitation.

  8. Nanosecond monolithic CMOS readout cell

    DOEpatents

    Souchkov, Vitali V.

    2004-08-24

    A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

  9. CMOS foveal image sensor chip

    NASA Technical Reports Server (NTRS)

    Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

    2002-01-01

    A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

  10. Accelerated life testing effects on CMOS microcircuit characteristics

    NASA Technical Reports Server (NTRS)

    1977-01-01

    Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

  11. Polarization- and wavelength-sensitive sub-wavelength structures fabricated in the metal layers of deep submicron CMOS processes

    NASA Astrophysics Data System (ADS)

    Junger, Stephan; Tschekalinskij, Wladimir; Verwaal, Nanko; Weber, Norbert

    2010-05-01

    Sub-wavelength structures in metal films have interesting optical properties that can be implemented for sensing applications: gratings act as wire grid polarizer, hole arrays with enhanced transmission can be used as spectral filters. This paper demonstrates the feasibility of these nanostructures using 180 nm and 90 nm complementary metal-oxide semiconductor (CMOS) processes. The metal layers of the process can be used for optical nanostructures with feature sizes down to 100 nm. We describe the design and simulation of these metal structures using the finite-difference timedomain (FDTD) method. The spectral response of the test structures was measured for different polarizations, where the gratings showed typical features of wire grid polarizers. Using a 180 nm CMOS image sensor process, an image sensor with 6 μm pixel size was designed and fabricated with different polarization selective structures allowing for polarization imaging. A polarization camera using this image sensor is demonstrated, visualizing stress birefringence as an application example. Finally, first results on the fabrication of hole arrays with a period of 320 nm are presented, showing color filters with enhanced transmission.

  12. Carbon Nanotube Integration with a CMOS Process

    PubMed Central

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  13. A CMOS low power, process/temperature variation tolerant RSSI with an integrated AGC loop

    NASA Astrophysics Data System (ADS)

    Qianqian, Lei; Min, Lin; Yin, Shi

    2013-03-01

    A low voltage low power CMOS limiter and received signal strength indicator (RSSI) with an integrated automatic gain control (AGC) loop for a short-distance receiver are implemented in SMIC 0.13 μm CMOS technology. The RSSI has a dynamic range of more than 60 dB and the RSSI linearity error is within ±0.5 dB for an input power from -65 to -8 dBm. The RSSI output voltage is from 0.15 to 1 V and the slope of the curve is 14.17 mV/dB while consuming 1.5 mA (I and Q paths) from a 1.2 V supply. Auto LNA gain mode selection with a combined RSSI function is also presented. Furthermore, with the compensation circuit, the proposed RSSI shows good temperature-independent and good robustness against process variation characteristics.

  14. Biosensing with integrated CMOS nanopores

    NASA Astrophysics Data System (ADS)

    Uddin, Ashfaque; Yemenicioglu, Sukru; Chen, Chin-Hsuan; Corgliano, Ellie; Milaninia, Kaveh; Xia, Fan; Plaxco, Kevin; Theogarajan, Luke

    2012-10-01

    This paper outlines our recent efforts in using solid-state nanopores as a biosensing platform. Traditionally biosensors concentrate mainly on the detection platform and not on signal processing. This decoupling can lead to inferior sensors and is exacerbated in nanoscale devices, where device noise is large and large dynamic range is required. This paper outlines a novel platform that integrates the nano, micro and macroscales in a closely coupled manner that mitigates many of these problems. We discuss our initial results of DNA translocation through the nanopore. We also briefly discuss the use of molecular recognition properties of aptamers with the versatility of the nanopore detector to design a new class of biosensors in a CMOS compatible platform.

  15. Yield enhancement methodologies for 90-nm technology and beyond

    NASA Astrophysics Data System (ADS)

    Allgair, John; Carey, Todd; Dougan, James; Etnyre, Tony; Langdon, Nate; Murray, Brooke

    2006-03-01

    In order to stay competitive in the rapidly advancing international semiconductor industry, a manufacturing company needs to continually focus on several areas including rapid yield learning, manufacturing cost, statistical process control limits, process yield, equipment availability, cycle time, turns per direct labor hour, customer on time delivery and zero customer defects. To hold a competitive position in the semiconductor market, performance to these measurable factors mut be maintained regardless of the technology generation. In this presentation, the methodology applied by Freescale Semiconductor to achieve the fastest yield learning curve in the industry, as cited by Dr. Robert Leachman of UC Berkley in 2003, will be discussed.

  16. Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs

    NASA Astrophysics Data System (ADS)

    Sharma, Devendra Kumar; Kaushik, Brajesh Kumar; Sharma, R. K.

    2014-05-01

    This article analyses the effect of coupling parasitics and CMOS gate driver width on transition time delay of coupled interconnects driven by dynamically switching inputs. Propagation delay through an interconnect is dependent not only on the technology/topology but also on many other factors such as input transition time, load characteristic, driving gate dimensions and so on. The delay is affected by rise/fall time of the signal, which in turn is dependent on the driving gate and the load presented to it. The signal transition time is also a strong function of wire parasitics. This article addresses the different issues of signal transition time. The impact of inter-wire parasitics and driver width on signal transition time are presented in this article. Furthermore, the effect of unequal transition time of the inputs to interconnect lines on crosstalk noise and delay is analysed. To demonstrate these effects, two distributed RLC lines coupled capacitively and inductively are taken into consideration. The simulations are run at three different technology nodes, viz. 65 nm, 90 nm and 130 nm.

  17. Optical hybrid package with an 8-channel 18GT/s CMOS transceiver for chip-to-chip optical interconnect

    NASA Astrophysics Data System (ADS)

    Mohammed, E.; Liao, J.; Kern, A.; Lu, D.; Braunisch, H.; Thomas, T.; Hyvonen, S.; Palermo, S.; Young, I. A.

    2008-02-01

    We describe the design and development of a high-speed 8-channel hybrid integrated optical transceiver package with Clock and Data Recovery (CDR) circuits. The package concept has been developed to be compatible with microprocessor package technology and at the same time allow the integration of low cost, high-performance optical components. A 90nm CMOS optical transceiver chip, 850nm 10Gb/s GaAs based vertical cavity surface emitting laser (VCSEL) array and PIN photodiode array are flip-chip mounted on a standard microprocessor Land Grid Array (LGA) package substrate. The CMOS drivers and receivers on the transceiver chip and the optical components (VCSEL and Photodiode arrays) are electrically coupled using a short transmission line routed on the top surface of the package. VCSEL and photodiode arrays are optically coupled to on-package integrated polymer waveguide arrays with metallized 45° mirrors. The waveguides, which are terminated with multi-terminal (MT) fiber optic connectors, couple out/in high-speed optical signals to/from the chip. The CMOS transceiver chip fully integrates all analog optical circuits such as VCSEL drivers, transimpedance amplifiers and clock and data recovery (CDR) retiming circuit with a low jitter LC-PLL. Digital circuits for pseudorandom bit-pattern sequence generators (PRBS) and bit-error rate test (BERT) are fully integrated. 20Gb/s electrical and 18Gb/s optical eye diagrams for the transmitter were measured out of the package. A fully packaged transmitter and receiver including clock data recovery at 10Gb/s have also been measured.

  18. Electroabsorption modulators for CMOS compatible optical interconnects in III-V and group IV materials

    NASA Astrophysics Data System (ADS)

    Roth, Jonathan Edgar

    While electrical systems excel at information processing, photonics is useful in systems for high-bandwidth, low-loss signal transmission. As photonics technology has become increasingly widespread and has been deployed at shorter distance scales than traditional long-haul networks, it has become important to efficiently integrate photonics components with electrical integrated circuits. Optoelectronic modulators used as transmitters are an important class of device for use in optical interconnects. Many optoelectronic modulator designs use waveguides. Coupling light into waveguides requires a difficult alignment step. This dissertation will describe a number of optoelectronic modulators that do not have the tight alignment constraints associated with waveguide-based modulators. The eased alignment constraints may be important for the practical manufacturing and packaging of systems using optical interconnects. Most currently deployed photonics technologies also use substrates other than silicon and materials incompatible with CMOS manufacturing. Recently we discovered a strong quantum-confined Stark effect in Ge/SiGe quantum well structures that can be used to create efficient optoelectronic modulators on silicon substrates. Optoelectronic modulators using this technology can be fabricated with conventional CMOS foundry processes, possibly on the same chips as CMOS circuits. In this dissertation, an optical interconnect operating in the C-band will be presented. We believe this is the first such device employing an optical transmitter flip-chip bonded to silicon CMOS. A number of novel modulators will be presented, which are fabricated on silicon substrates, and employ Ge/SiGe quantum well structures. These modulators include a novel architecture known as the side-entry modulator, which is designed for monolithic integration with electronics. One side-entry modulator achieved over 3 dB of contrast in the telecommunications C-band for a voltage swing of 1V. Such a

  19. Flexible packaging and integration of CMOS IC with elastomeric microfluidics

    NASA Astrophysics Data System (ADS)

    Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

    2013-05-01

    We have demonstrated flexible packaging and integration of CMOS IC chips with PDMS microfluidics. Microfluidic channels are used to deliver both liquid samples and liquid metals to the CMOS die. The liquid metals are used to realize electrical interconnects to the CMOS chip. As a demonstration we integrated a CMOS magnetic sensor die and matched PDMS microfluidic channels in a flexible package. The packaged system is fully functional under 3cm bending radius. The flexible integration of CMOS ICs with microfluidics enables previously unavailable flexible CMOS electronic systems with fluidic manipulation capabilities, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing.

  20. Nanopore-CMOS Interfaces for DNA Sequencing.

    PubMed

    Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

    2016-01-01

    DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces. PMID:27509529

  1. Characterization and reliability of CMOS microstructures

    NASA Astrophysics Data System (ADS)

    Fedder, Gary K.; Blanton, Ronald D. S.

    1999-08-01

    This paper provides an overview of high-aspect-ratio CMOS micromachining, focusing on materials characterization, reliability, and fault analysis. Composite microstrutural beam widths and gaps down to 1.2 micrometers are etched out of conventional CMOS dielectric, aluminum, and gate-polysilicon thin films using post-CMOS dry etching for both structural sidewall definition and for release from the substrate. Differences in stress between the multiple metal and dielectric layers cause vertical stress gradients and curl, while misalignment between layers causes lateral stress gradients and curl. Cracking is induced in a resonant fatigue structures at 620 MPa of repetitive stress after over 50 million cycles. Beams have withstood over 1.3 billion cycles at 124 MPa stress levels induced by electrostatic actuation. Failures due to process defects are classified according to the geometrical features of the defective structures. Relative probability of occurrence of each defect type is extracted from the process simulation results.

  2. Resistor Extends Life Of Battery In Clocked CMOS Circuit

    NASA Technical Reports Server (NTRS)

    Wells, George H., Jr.

    1991-01-01

    Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

  3. Low power, CMOS digital autocorrelator spectrometer for spaceborne applications

    NASA Technical Reports Server (NTRS)

    Chandra, Kumar; Wilson, William J.

    1992-01-01

    A 128-channel digital autocorrelator spectrometer using four 32 channel low power CMOS correlator chips was built and tested. The CMOS correlator chip uses a 2-bit multiplication algorithm and a full-custom CMOS VLSI design to achieve low DC power consumption. The digital autocorrelator spectrometer has a 20 MHz band width, and the total DC power requirement is 6 Watts.

  4. High-temperature Complementary Metal Oxide Semiconductors (CMOS)

    NASA Technical Reports Server (NTRS)

    Mcbrayer, J. D.

    1981-01-01

    The results of an investigation into the possibility of using complementary metal oxide semiconductor (CMOS) technology for high temperature electronics are presented. A CMOS test chip was specifically developed as the test bed. This test chip incorporates CMOS transistors that have no gate protection diodes; these diodes are the major cause of leakage in commercial devices.

  5. End-of-fabrication CMOS process monitor

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

    1990-01-01

    A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

  6. Low power SEU immune CMOS memory circuits

    NASA Technical Reports Server (NTRS)

    Liu, M. N.; Whitaker, Sterling

    1992-01-01

    The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.

  7. Fully CMOS-compatible titanium nitride nanoantennas

    NASA Astrophysics Data System (ADS)

    Briggs, Justin A.; Naik, Gururaj V.; Petach, Trevor A.; Baum, Brian K.; Goldhaber-Gordon, David; Dionne, Jennifer A.

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  8. A fail-safe CMOS logic gate

    NASA Technical Reports Server (NTRS)

    Bobin, V.; Whitaker, S.

    1990-01-01

    This paper reports a design technique to make Complex CMOS Gates fail-safe for a class of faults. Two classes of faults are defined. The fail-safe design presented has limited fault-tolerance capability. Multiple faults are also covered.

  9. Radiation Tolerance of 65nm CMOS Transistors

    DOE PAGESBeta

    Krohn, M.; Bentele, B.; Christian, D. C.; Cumalat, J. P.; Deptuch, G.; Fahim, F.; Hoff, J.; Shenai, A.; Wagner, S. R.

    2015-12-11

    We report on the effects of ionizing radiation on 65 nm CMOS transistors held at approximately -20°C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

  10. SEU hardening of CMOS memory circuit

    NASA Technical Reports Server (NTRS)

    Whitaker, S.; Canaris, J.; Liu, K.

    1990-01-01

    This paper reports a design technique to harden CMOS memory circuits against Single Event Upset (SEU) in the space environment. A RAM cell and Flip Flop design are presented to demonstrate the method. The Flip Flop was used in the control circuitry for a Reed Solomon encoder designed for the Space Station.

  11. Low energy CMOS for space applications

    NASA Technical Reports Server (NTRS)

    Panwar, Ramesh; Alkalaj, Leon

    1992-01-01

    The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

  12. CMOS preamplifiers for detectors large and small

    SciTech Connect

    O`Connor, P.

    1997-12-31

    We describe four CMOS preamplifiers developed for multiwire proportional chambers (MWPC) and silicon drift detectors (SDD) covering a capacitance range from 150 pF to 0.15 pF. Circuit techniques to optimize noise performance, particularly in the low-capacitance regime, are discussed.

  13. Low energy CMOS for space applications

    NASA Astrophysics Data System (ADS)

    Panwar, Ramesh; Alkalaj, Leon

    The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

  14. Low-Power SOI CMOS Transceiver

    NASA Technical Reports Server (NTRS)

    Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

    2003-01-01

    The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS

  15. FLASH_SSF_Terra-FM1_V3B

    Atmospheric Science Data Center

    2016-07-22

    ... FLASH_SSF_Terra-FM1_V3B Project Title:  CERES Discipline:  Clouds Radiation Budget ...   Reverb Tutorial Subset/Visualization Tool:  CERES Order Tool CERES Search and Subset Tool (HDF4 & netCDF) ...

  16. 200-Mbps optical integrated circuit design and first iteration realizations in 1.2- and 0.8-micron Bi-CMOS technology

    NASA Astrophysics Data System (ADS)

    Snyman, Lukas W.; Chaing, C.-T.; Bogalecki, Alfons; Du Plessis, Monuko; Aharoni, Herzl

    2004-07-01

    A prototype Silicon CMOS Optical Integrated Circuit (Si CMOS OEIC) was designed and simulated using standard 0.8 micron Bi-CMOS silicon integrated circuit technology. The circuit consisted of an integrated silicon light emitting source, an optical wave-guiding structure, two integrated optical detectors and two high-gain CMOS transimpedance analogue amplifiers. Simulations with MicroSim PSpice software predict a utilizable bandwidth capability of up to 220 MHz for the trans-impedance amplifier for detected photo-currents at the input of the amplifier in the range of 1 nA to 100 nA and driving a 10mV to 1 V signal into a 100 kΩ load. First iteration OEIC structures were realised in 1.2 micron CMOS technology for various source-waveguide-detector arrangements. Current signal ranging from 1nA to 1 micro-amp was detected at detectors. The technology seems favorable for first-iteration implementation for digital communications on chip up to 200Mbps.

  17. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

    PubMed

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-01

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system. PMID:26840316

  18. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement

    PubMed Central

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-01

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of −20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system. PMID:26840316

  19. A novel loss compensation technique analysis and design for 60 GHz CMOS SPDT switch

    NASA Astrophysics Data System (ADS)

    Zonghua, Zheng; Lingling, Sun; Jun, Liu; Shengzhou, Zhang

    2016-01-01

    A novel loss compensation technique for a series-shunt single-pole double-throw (SPDT) switch is presented operating in the 60 GHz. The feed-forward compensation network which is composed of an NMOS, a couple capacitance and a shunt inductance can reduce the impact of the feed forward capacitance to reduce the insertion loss and improve the isolation of the SPDT switch. The measured insertion loss and isolation characteristics of the switch somewhat deviating from the 60 GHz are analyzed revealing that the inaccuracy of the MOS model can greatly degrade the performance of the switch. The switch is implemented in TSMC 90-nm CMOS process and exhibits an isolation of above 27 dB at transmitter mode, and the insertion loss of 1.8-3 dB at 30-65 GHz by layout simulation. The measured insertion loss is 2.45 dB at 52 GHz and keeps < 4 dB at 30-64 GHz. The measured isolation is better than 25 dB at 30-64 GHz and the measured return loss is better than 10 dB at 30-65 GHz. A measured input 1 dB gain compression point of the switch is 13 dBm at 52 GHz and 15 dBm at 60 GHz. The simulated switching speed with rise time and fall time are 720 and 520 ps, respectively. The active chip size of the proposed switch is 0.5 × 0.95 mm2. Project supported by the National Natural Science Foundation of China (Nos. 61331006, 61372021).

  20. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    PubMed Central

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-01-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

  1. Spectrum acquisition of detonation based on CMOS

    NASA Astrophysics Data System (ADS)

    Li, Yan; Bai, Yonglin; Wang, Bo; Liu, Baiyu; Xue, Yingdong; Zhang, Wei; Gou, Yongsheng; Bai, Xiaohong; Qin, Junjun; Xian, Ouyang

    2010-10-01

    The detection of high-speed dynamic spectrum is the main method to acquire transient information. In order to obtain the large amount spectral data in real-time during the process of detonation, a CMOS-based system with high-speed spectrum data acquisition is designed. The hardware platform of the system is based on FPGA, and the unique characteristic of CMOS image sensors in the rolling shutter model is used simultaneously. Using FPGA as the master control chip of the system, not only provides the time sequence for CIS, but also controls the storage and transmission of the spectral data. In the experiment of spectral data acquisition, the acquired information is transmitted to the host computer through the CameraLink bus. The dynamic spectral curve is obtained after the subsequent processing. The experimental results demonstrate that this system is feasible in the acquisition and storage of high-speed dynamic spectrum information during the process of detonation.

  2. Ultralow-Loss CMOS Copper Plasmonic Waveguides.

    PubMed

    Fedyanin, Dmitry Yu; Yakubovsky, Dmitry I; Kirtaev, Roman V; Volkov, Valentyn S

    2016-01-13

    Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which can outperform gold plasmonic waveguides simultaneously providing long (>40 μm) propagation length and deep subwavelength (∼λ(2)/50, where λ is the free-space wavelength) mode confinement in the telecommunication spectral range. These results create the backbone for the development of a CMOS plasmonic platform and its integration in future electronic chips. PMID:26654281

  3. Noise in a CMOS digital pixel sensor

    NASA Astrophysics Data System (ADS)

    Chi, Zhang; Suying, Yao; Jiangtao, Xu

    2011-11-01

    Based on the study of noise performance in CMOS digital pixel sensor (DPS), a mathematical model of noise is established with the pulse-width-modulation (PWM) principle. Compared with traditional CMOS image sensors, the integration time is different and A/D conversion is implemented in each PWM DPS pixel. Then, the quantitative calculating formula of system noise is derived. It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region. In this model, photodiode shot noise does not vary with luminance, but dark current shot noise does. According to increasing photodiode capacitance and the comparator's reference voltage or optimizing the mismatch in the comparator, the total noise can be reduced. These results serve as a guideline for the design of PWM DPS.

  4. Cmos spdt switch for wlan applications

    NASA Astrophysics Data System (ADS)

    Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

    2015-04-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

  5. IR CMOS: infrared enhanced silicon imaging

    NASA Astrophysics Data System (ADS)

    Pralle, M. U.; Carey, J. E.; Haddad, Homayoon; Vineis, C.; Sickler, J.; Li, X.; Jiang, J.; Sahebi, F.; Palsule, C.; McKee, J.

    2013-06-01

    SiOnyx has developed visible and infrared CMOS image sensors leveraging a proprietary ultrafast laser semiconductor process technology. This technology demonstrates 10 fold improvements in infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Furthermore, these sensitivity enhancements are achieved on a focal plane with state of the art noise performance of 2 electrons/pixel. By capturing light in the visible regime as well as infrared light from the night glow, this sensor technology provides imaging in daytime through twilight and into nighttime conditions. The measured 10x quantum efficiency at the critical 1064 nm laser node enables see spot imaging capabilities in a variety of ambient conditions. The spectral sensitivity is from 400 to 1200 nm.

  6. CMOS-array design-automation techniques

    NASA Technical Reports Server (NTRS)

    Feller, A.; Lombardt, T.

    1979-01-01

    Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

  7. Advanced CMOS Radiation Effects Testing Analysis

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, Kenneth P.; Gordon, Michael S.; LaBel, Kenneth A.; Schwank, James R.; Dodds, Nathaniel A.; Castaneda, Carlos M.; Berg, Melanie D.; Kim, Hak S.; Phan, Anthony M.; Seidleck, Christina M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  8. Advanced CMOS Radiation Effects Testing and Analysis

    NASA Technical Reports Server (NTRS)

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  9. Radiation effects on scientific CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Yuanfu, Zhao; Liyan, Liu; Xiaohui, Liu; Xiaofeng, Jin; Xiang, Li

    2015-11-01

    A systemic solution for radiation hardened design is presented. Besides, a series of experiments have been carried out on the samples, and then the photoelectric response characteristic and spectral characteristic before and after the experiments have been comprehensively analyzed. The performance of the CMOS image sensor with the radiation hardened design technique realized total-dose resilience up to 300 krad(Si) and resilience to single-event latch up for LET up to 110 MeV·cm2/mg.

  10. CMOS Camera Array With Onboard Memory

    NASA Technical Reports Server (NTRS)

    Gat, Nahum

    2009-01-01

    A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

  11. Radiation characteristics of scintillator coupled CMOS APS for radiography conditions

    NASA Astrophysics Data System (ADS)

    Kim, Kwang Hyun; Kim, Soongpyung; Kang, Dong-Won; Kim, Dong-Kie

    2006-11-01

    Under industrial radiography conditions, we analyzed short-term radiation characteristics of scintillator coupled CMOS APS (hereinafter SC CMOS APS). By means of experimentation, the contribution of the transmitted X-ray through the scintillator to the properties of the CMOS APS and the afterimage, generated in the acquired image even at low dose condition, were investigated. To see the transmitted X-ray effects on the CMOS APS, Fein focus™ X-ray machine, two scintillators of Lanex™ Fine and Regular, and two CMOS APS array of RadEye™ were used under the conditions of 50 kV p/1 mAs and 100 kV p/1 mAs. By measuring the transmitted X-ray on signal and Noise Power Spectrum, we analytically examined the generation mechanism of the afterimage, based on dark signal or dark current increase in the sensor, and explained the afterimage in the SC CMOS APS.

  12. CMOS-controlled rapidly tunable photodetectors

    NASA Astrophysics Data System (ADS)

    Chen, Ray

    With rapidly increasing data bandwidth demands, wavelength-division-multiplexing (WDM) optical access networks seem unavoidable in the near future. To operate WDM optical networks in an efficient scheme, wavelength reconfigurability and scalability of the network are crucial. Unfortunately, most of the existing wavelength tunable technologies are neither rapidly tunable nor spectrally programmable. This dissertation presents a tunable photodetector that is designed for dynamic-wavelength allocation WDM network environments. The wavelength tuning mechanism is completely different from existing technologies. The spectrum of this detector is programmable through low-voltage digital patterns. Since the wavelength selection is achieved by electronic means, the device wavelength reconfiguration time is as fast as the electronic switching time. In this dissertation work, we have demonstrated a tunable detector that is hybridly integrated with its customized CMOS driver and receiver with nanosecond wavelength reconfiguration time. In addition to its nanosecond wavelength reconfiguration time, the spectrum of this detector is digitally programmable, which means that it can adapt to system changes without re-fabrication. We have theoretically developed and experimentally demonstrated two device operating algorithms based on the same orthogonal device-optics basis. Both the rapid wavelength tuning time and the scalability make this novel device very viable for new reconfigurable WDM networks. By taking advantage of CMOS circuit design, this detector concept can be further extended for simultaneous multiple wavelength detection. We have developed one possible chip architecture and have designed a CMOS tunable optical demux for simultaneous controllable two-wavelength detection.

  13. Efficient design of CMOS TSC checkers

    NASA Technical Reports Server (NTRS)

    Biddappa, Anita; Shamanna, Manjunath K.; Maki, Gary; Whitaker, Sterling

    1990-01-01

    This paper considers the design of an efficient, robustly testable, CMOS Totally Self-Checking (TSC) Checker for k-out-of-2k codes. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers under the stuck-open fault model due to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented. This design retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (greater than 70 percent) in gate count, gate inputs, and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed one is better than Kundu's in all respects for k-out-of-2k codes.

  14. Quantitative optical metrology with CMOS cameras

    NASA Astrophysics Data System (ADS)

    Furlong, Cosme; Kolenovic, Ervin; Ferguson, Curtis F.

    2004-08-01

    Recent advances in laser technology, optical sensing, and computer processing of data, have lead to the development of advanced quantitative optical metrology techniques for high accuracy measurements of absolute shapes and deformations of objects. These techniques provide noninvasive, remote, and full field of view information about the objects of interest. The information obtained relates to changes in shape and/or size of the objects, characterizes anomalies, and provides tools to enhance fabrication processes. Factors that influence selection and applicability of an optical technique include the required sensitivity, accuracy, and precision that are necessary for a particular application. In this paper, sensitivity, accuracy, and precision characteristics in quantitative optical metrology techniques, and specifically in optoelectronic holography (OEH) based on CMOS cameras, are discussed. Sensitivity, accuracy, and precision are investigated with the aid of National Institute of Standards and Technology (NIST) traceable gauges, demonstrating the applicability of CMOS cameras in quantitative optical metrology techniques. It is shown that the advanced nature of CMOS technology can be applied to challenging engineering applications, including the study of rapidly evolving phenomena occurring in MEMS and micromechatronics.

  15. Correct CMOS IC defect models for quality testing

    NASA Technical Reports Server (NTRS)

    Soden, Jerry M.; Hawkins, Charles F.

    1993-01-01

    Leading edge, high reliability, and low escape CMOS IC test practices have now virtually removed the stuck-at fault model and replaced it with more defect-orientated models. Quiescent power supply current testing (I(sub DDQ)) combined with strategic use of high speed test patterns is the recommended approach to zero defect and high reliability testing goals. This paper reviews the reasons for the change in CMOS IC test practices and outlines an improved CMOS IC test methodology.

  16. A Standard CMOS Humidity Sensor without Post-Processing

    PubMed Central

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2011-01-01

    A 2 μW power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023–10 humidity-sensitive layer, and a CMOS capacitance to voltage converter. PMID:22163949

  17. Behavior of faulty double BJT BiCMOS logic gates

    NASA Technical Reports Server (NTRS)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1992-01-01

    Logic Behavior of a Double BJT BiCMOS device under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS, to bring out the testability differences.

  18. Interferometric comparison of the performance of a CMOS and sCMOS detector

    NASA Astrophysics Data System (ADS)

    Flores-Moreno, J. M.; De la Torre I., Manuel H.; Hernández-Montes, M. S.; Pérez-López, Carlos; Mendoza S., Fernando

    2015-08-01

    We present an analysis of the imaging performance of two state-of-the-art sensors widely used in the nondestructive- testing area (NDT). The analysis is based on the quantification of the signal-to-noise (SNR) ratio from an optical phase image. The calculation of the SNR is based on the relation of the median (average) and standard deviation measurements over specific areas of interest in the phase images of both sensors. This retrieved phase is coming from the vibrational behavior of a large object by means of an out-of-plane holographic interferometer. The SNR is used as a figure-of-merit to evaluate and compare the performance of the CMOS and scientific CMOS (sCMOS) camera as part of the experimental set-up. One of the cameras has a high speed CMOS sensor while the other has a high resolution sCMOS sensor. The object under study is a metallically framed table with a Formica cover with an observable area of 1.1 m2. The vibration induced to the sample is performed by a linear step motor with an attached tip in the motion stage. Each camera is used once at the time to record the deformation keeping the same experimental conditions for each case. These measurements may complement the conventional procedures or technical information commonly used to evaluate a camerás performance such as: quantum efficiency, spatial resolution and others. Results present post processed images from both cameras, but showing a smoother and easy to unwrap optical phase coming from those recorded with the sCMOS camera.

  19. Ideals generated by traces in the algebra of symplectic reflections {H_{1,{v_{1,}}{v_2}}}( {{I_2}( {2m} )} )

    NASA Astrophysics Data System (ADS)

    Konstein, S. E.; Tyutin, I. V.

    2016-05-01

    The associative algebra of symplectic reflections H: = {H_{1,{v_{1,}}{v_2}}}( {{I_2}( {2m} )} ) based on the group generated by the root system I 2(2m) depends on two parameters, ν 1 and ν 2. For each value of these parameters, the algebra admits an m-dimensional space of traces. A trace tr is said to be degenerate if the corresponding symmetric bilinear form B tr( x, y) = tr( xy) is degenerate. We find all values of the parameters ν 1 and ν 2 for which the space of traces contains degenerate traces and the algebra H consequently has a two-sided ideal. It turns out that a linear combination of degenerate traces is also a degenerate trace. For the ν 1 and ν 2 values corresponding to degenerate traces, we find the dimensions of the space of degenerate traces.

  20. Current-mode CMOS hybrid image sensor

    NASA Astrophysics Data System (ADS)

    Benyhesan, Mohammad Kassim

    Digital imaging is growing rapidly making Complimentary Metal-Oxide-Semi conductor (CMOS) image sensor-based cameras indispensable in many modern life devices like cell phones, surveillance devices, personal computers, and tablets. For various purposes wireless portable image systems are widely deployed in many indoor and outdoor places such as hospitals, urban areas, streets, highways, forests, mountains, and towers. However, the increased demand on high-resolution image sensors and improved processing features is expected to increase the power consumption of the CMOS sensor-based camera systems. Increased power consumption translates into a reduced battery life-time. The increased power consumption might not be a problem if there is access to a nearby charging station. On the other hand, the problem arises if the image sensor is located in widely spread areas, unfavorable to human intervention, and difficult to reach. Given the limitation of energy sources available for wireless CMOS image sensor, an energy harvesting technique presents a viable solution to extend the sensor life-time. Energy can be harvested from the sun light or the artificial light surrounding the sensor itself. In this thesis, we propose a current-mode CMOS hybrid image sensor capable of energy harvesting and image capture. The proposed sensor is based on a hybrid pixel that can be programmed to perform the task of an image sensor and the task of a solar cell to harvest energy. The basic idea is to design a pixel that can be configured to exploit its internal photodiode to perform two functions: image sensing and energy harvesting. As a proof of concept a 40 x 40 array of hybrid pixels has been designed and fabricated in a standard 0.5 microm CMOS process. Measurement results show that up to 39 microW of power can be harvested from the array under 130 Klux condition with an energy efficiency of 220 nJ /pixel /frame. The proposed image sensor is a current-mode image sensor which has several

  1. Envelope tracking CMOS power amplifier with high-speed CMOS envelope amplifier for mobile handsets

    NASA Astrophysics Data System (ADS)

    Yoshida, Eiji; Sakai, Yasufumi; Oishi, Kazuaki; Yamazaki, Hiroshi; Mori, Toshihiko; Yamaura, Shinji; Suto, Kazuo; Tanaka, Tetsu

    2014-01-01

    A high-efficiency CMOS power amplifier (PA) based on envelope tracking (ET) has been reported for a wideband code division multiple access (W-CDMA) and long term evolution (LTE) application. By adopting a high-speed CMOS envelope amplifier with current direction sensing, a 5% improvement in total power-added efficiency (PAE) and a 11 dB decrease in adjacent channel leakage ratio (ACLR) are achieved with a W-CDMA signal. Moreover, the proposed PA achieves a PAE of 25.4% for a 10 MHz LTE signal at an output power (Pout) of 25.6 dBm and a gain of 24 dB.

  2. Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

    PubMed Central

    Huang, Yue; Mason, Andrew J.

    2013-01-01

    This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

  3. High responsivity CMOS imager pixel implemented in SOI technology

    NASA Technical Reports Server (NTRS)

    Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

    2000-01-01

    Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

  4. An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability

    PubMed Central

    Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U.

    2015-01-01

    An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle. PMID:25756863

  5. CMOS-compatible RF MEMS switch

    NASA Astrophysics Data System (ADS)

    Lakamraju, Narendra V.; Kim, Bruce; Phillips, Stephen M.

    2004-08-01

    Mobile technologies have relied on RF switches for a long time. Though the basic function of the switch has remained the same, the way they have been made has changed in the recent past. In the past few years work has been done to use MEMS technologies in designing and fabricating an RF switch that would in many ways replace the electronic and mechanical switches that have been used for so long. The work that is described here is an attempt to design and fabricate an RF MEMS switch that can handle higher RF power and have CMOS compatible operating voltages.

  6. Monolithic CMOS imaging x-ray spectrometers

    NASA Astrophysics Data System (ADS)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

    2014-07-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

  7. Vertical Isolation for Photodiodes in CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2008-01-01

    In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

  8. A CMOS high speed imaging system design based on FPGA

    NASA Astrophysics Data System (ADS)

    Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

    2015-10-01

    CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

  9. Theoretical performance analysis for CMOS based high resolution detectors.

    PubMed

    Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2013-03-01

    High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive. PMID:24353390

  10. Modulated CMOS camera for fluorescence lifetime microscopy.

    PubMed

    Chen, Hongtao; Holst, Gerhard; Gratton, Enrico

    2015-12-01

    Widefield frequency-domain fluorescence lifetime imaging microscopy (FD-FLIM) is a fast and accurate method to measure the fluorescence lifetime of entire images. However, the complexity and high costs involved in construction of such a system limit the extensive use of this technique. PCO AG recently released the first luminescence lifetime imaging camera based on a high frequency modulated CMOS image sensor, QMFLIM2. Here we tested and provide operational procedures to calibrate the camera and to improve the accuracy using corrections necessary for image analysis. With its flexible input/output options, we are able to use a modulated laser diode or a 20 MHz pulsed white supercontinuum laser as the light source. The output of the camera consists of a stack of modulated images that can be analyzed by the SimFCS software using the phasor approach. The nonuniform system response across the image sensor must be calibrated at the pixel level. This pixel calibration is crucial and needed for every camera settings, e.g. modulation frequency and exposure time. A significant dependency of the modulation signal on the intensity was also observed and hence an additional calibration is needed for each pixel depending on the pixel intensity level. These corrections are important not only for the fundamental frequency, but also for the higher harmonics when using the pulsed supercontinuum laser. With these post data acquisition corrections, the PCO CMOS-FLIM camera can be used for various biomedical applications requiring a large frame and high speed acquisition. PMID:26500051

  11. Challenges of nickel silicidation in CMOS technologies

    SciTech Connect

    Breil, Nicolas; Lavoie, Christian; Ozcan, Ahmet; Baumann, Frieder; Klymko, Nancy; Nummy, Karen; Sun, Bing; Jordan-Sweet, Jean; Yu, Jian; Zhu, Frank; Narasimha, Shreesh; Chudzik, Michael

    2015-04-01

    In our paper, we review some of the key challenges associated with the Ni silicidation process in the most recent CMOS technologies. The introduction of new materials (e.g.SiGe), and of non-planar architectures bring some important changes that require fundamental investigation from a material engineering perspective. Following a discussion of the device architecture and silicide evolution through the last CMOS generations, we focus our study on a very peculiar defect, termed NiSi-Fangs. We describe a mechanism for the defect formation, and present a detailed material analysis that supports this mechanism. We highlight some of the possible metal enrichment processes of the nickel monosilicide such as oxidation or various RIE (Reactive Ion Etching) plasma process, leading to a metal source available for defect formation. Furthermore, we investigate the NiSi formation and re-formation silicidation differences between Si and SiGe materials, and between (1 0 0) and (1 1 1) orientations. Finally, we show that the thermal budgets post silicidation can lead to the formation of NiSi-Fangs if the structure and the processes are not optimized. Beyond the understanding of the defect and the discussion on the engineering solutions used to prevent its formation, the interest of this investigation also lies in the fundamental learning within the Ni–Pt–Si–Ge system and some additional perspective on Ni-based contacts to advanced microelectronic devices.

  12. All-CMOS night vision viewer with integrated microdisplay

    NASA Astrophysics Data System (ADS)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

    2014-02-01

    The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

  13. Ink-Jet Printed CMOS Electronics from Oxide Semiconductors.

    PubMed

    Garlapati, Suresh Kumar; Baby, Tessy Theres; Dehm, Simone; Hammad, Mohammed; Chakravadhanula, Venkata Sai Kiran; Kruk, Robert; Hahn, Horst; Dasgupta, Subho

    2015-08-01

    Complementary metal oxide semiconductor (CMOS) technology with high transconductance and signal gain is mandatory for practicable digital/analog logic electronics. However, high performance all-oxide CMOS logics are scarcely reported in the literature; specifically, not at all for solution-processed/printed transistors. As a major step toward solution-processed all-oxide electronics, here it is shown that using a highly efficient electrolyte-gating approach one can obtain printed and low-voltage operated oxide CMOS logics with high signal gain (≈21 at a supply voltage of only 1.5 V) and low static power dissipation. PMID:25867029

  14. Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

    2008-01-01

    Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

  15. CMOS digital pixel sensors: technology and applications

    NASA Astrophysics Data System (ADS)

    Skorka, Orit; Joseph, Dileepan

    2014-04-01

    CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

  16. Latchup in CMOS devices from heavy ions

    NASA Technical Reports Server (NTRS)

    Soliman, K.; Nichols, D. K.

    1983-01-01

    It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

  17. CMOS imager for pointing and tracking applications

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

    2006-01-01

    Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

  18. CMOS image sensor with contour enhancement

    NASA Astrophysics Data System (ADS)

    Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

    2010-10-01

    Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5μm DPTM CMOS process.

  19. Depleted CMOS pixels for LHC proton-proton experiments

    NASA Astrophysics Data System (ADS)

    Wermes, N.

    2016-07-01

    While so far monolithic pixel detectors have remained in the realm of comparatively low rate and radiation applications outside LHC, new developments exploiting high resistivity substrates with three or four well CMOS process options allow reasonably large depletion depths and full CMOS circuitry in a monolithic structure. This opens up the possibility to target CMOS pixel detectors also for high radiation pp-experiments at the LHC upgrade, either in a hybrid-type fashion or even fully monolithic. Several pixel matrices have been prototyped with high ohmic substrates, high voltage options, and full CMOS electronics. They were characterized in the lab and in test beams. An overview of the necessary development steps and different approaches as well as prototype results are presented in this paper.

  20. A safety monitoring system for taxi based on CMOS imager

    NASA Astrophysics Data System (ADS)

    Liu, Zhi

    2005-01-01

    CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

  1. Tests of commercial colour CMOS cameras for astronomical applications

    NASA Astrophysics Data System (ADS)

    Pokhvala, S. M.; Reshetnyk, V. M.; Zhilyaev, B. E.

    2013-12-01

    We present some results of testing commercial colour CMOS cameras for astronomical applications. Colour CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in colour CMOS sensors is close to the astronomical Johnson BVR system. The basic camera characteristics: read noise (e^{-}/pix), thermal noise (e^{-}/pix/sec) and electronic gain (e^{-}/ADU) for the commercial digital camera Canon 5D MarkIII are presented. We give the same characteristics for the scientific high performance cooled CCD camera system ALTA E47. Comparing results for tests of Canon 5D MarkIII and CCD ALTA E47 show that present-day commercial colour CMOS cameras can seriously compete with the scientific CCD cameras in deep astronomical imaging.

  2. High-speed multicolour photometry with CMOS cameras

    NASA Astrophysics Data System (ADS)

    Pokhvala, S. M.; Zhilyaev, B. E.; Reshetnyk, V. M.

    2012-11-01

    We present the results of testing the commercial digital camera Nikon D90 with a CMOS sensor for high-speed photometry with a small telescope Celestron 11'' at the Peak Terskol Observatory. CMOS sensor allows to perform photometry in 3 filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system of CMOS sensors is close to the Johnson BVR system. The results of testing show that one can carry out photometric measurements with CMOS cameras for stars with the V-magnitude up to ≃14^{m} with the precision of 0.01^{m}. Stars with the V-magnitude up to ˜10 can be shot at 24 frames per second in the video mode.

  3. CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

    NASA Technical Reports Server (NTRS)

    Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

    2006-01-01

    This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

  4. OLED-on-CMOS integration for optoelectronic sensor applications

    NASA Astrophysics Data System (ADS)

    Vogel, Uwe; Kreye, Daniel; Reckziegel, Sven; Törker, Michael; Grillberger, Christiane; Amelung, Jörg

    2007-02-01

    Highly-efficient, low-voltage organic light emitting diodes (OLEDs) are well suitable for post-processing integration onto the top metal layer of CMOS devices. This has been proven for OLED microdisplays so far. Moreover, OLEDon- CMOS technology may also be excellently suitable for various optoelectronic sensor applications by combining highly efficient emitters, use of low-cost materials and cost-effective manufacturing together with silicon-inherent photodetectors and CMOS circuitry. The use of OLEDs on CMOS substrates requires a top-emitting, low-voltage and highly efficient OLED structure. By reducing the operating voltage for the OLED below 5V, the costs for the CMOS process can be reduced, because a process without high-voltage option can be used. Red, orange, white, green and blue OLED-stacks with doped charge transport layers were prepared on different dualmetal layer CMOS test substrates without active transistor area. Afterwards, the different devices were measured and compared with respect to their performance (current, luminance, voltage, luminance dependence on viewing angle, optical outcoupling etc.). Low operating voltages of 2.4V at 100cd/m2 for the red p-i-n type phosphorescent emitting OLED stack, 2.5V at 100cd/m2 for the orange phosphorescent emitting OLED stack and 3.2V at 100cd/m2 for the white fluorescent emitting OLED have been achieved here. Therefore, those OLED stacks are suitable for use in a CMOS process even within a regular 5V process option. Moreover, the operating voltage achieved so far is expected to be reduced further when using different top electrode materials. Integrating such OLEDs on a CMOS-substrate provide a preferable choice for silicon-based optical microsystems targeted towards optoelectronic sensor applications, as there are integrated light barriers, optocouplers, or lab-onchip devices.

  5. Delta Doping High Purity CCDs and CMOS for LSST

    NASA Technical Reports Server (NTRS)

    Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

    2006-01-01

    A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

  6. CMOS monolithic pixel sensors research and development at LBNL

    NASA Astrophysics Data System (ADS)

    Contarato, D.; Bussat, J.-M.; Denes, P.; Greiner, L.; Kim, T.; Stezelberger, T.; Wieman, H.; Battaglia, M.; Hooberman, B.; Tompkins, L.

    2007-12-01

    This paper summarizes the recent progress in the design and characterization of CMOS pixel sensors at LBNL. Results of lab tests, beam tests and radiation hardness tests carried out at LBNL on a test structure with pixels of various sizes are reported. The first results of the characterization of back-thinned CMOS pixel sensors are also reported, and future plans and activities are discussed.

  7. CMOS front end electronics for the ATLAS muon detector

    SciTech Connect

    Huth, J.; Oliver, J.; Hazen, E.; Shank, J.

    1997-12-31

    An all-CMOS design for an integrated ASD (Amplifier-Shaper-Discriminator) chip for readout of the ATLAS Monitored Drift Tubes (MDTs) is presented. Eight channels of charge-sensitive preamp, two-stage pole/zero shaper, Wilkinson ADC and discriminator with programmable hysteresis are integrated on a single IC. Key elements have been prototyped in 1.2 and 0.5 micron CMOS operating at 5V and 3.3V respectively.

  8. CMOS Image Sensors: Electronic Camera On A Chip

    NASA Technical Reports Server (NTRS)

    Fossum, E. R.

    1995-01-01

    Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

  9. Advancement of CMOS Doping Technology in an External Development Framework

    NASA Astrophysics Data System (ADS)

    Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

    2011-01-01

    The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

  10. Multiband CMOS sensor simplify FPA design

    NASA Astrophysics Data System (ADS)

    Wang, Weng Lyang B.; Ling, Jer

    2015-10-01

    Push broom multi-band Focal Plane Array (FPA) design needs to consider optics, image sensor, electronic, mechanic as well as thermal. Conventional FPA use two or several CCD device as an image sensor. The CCD image sensor requires several high speed, high voltage and high current clock drivers as well as analog video processors to support their operation. Signal needs to digitize using external sample / hold and digitized circuit. These support circuits are bulky, consume a lot of power, must be shielded and placed in close to the CCD to minimize the introduction of unwanted noise. The CCD also needs to consider how to dissipate power. The end result is a very complicated FPA and hard to make due to more weighs and draws more power requiring complex heat transfer mechanisms. In this paper, we integrate microelectronic technology and multi-layer soft / hard Printed Circuit Board (PCB) technology to design electronic portion. Since its simplicity and integration, the optics, mechanic, structure and thermal design will become very simple. The whole FPA assembly and dis-assembly reduced to a few days. A multi-band CMOS Sensor (dedicated as C468) was used for this design. The CMOS Sensor, allow for the incorporation of clock drivers, timing generators, signal processing and digitization onto the same Integrated Circuit (IC) as the image sensor arrays. This keeps noise to a minimum while providing high functionality at reasonable power levels. The C468 is a first Multiple System-On-Chip (MSOC) IC. This device used our proprietary wafer butting technology and MSOC technology to combine five long sensor arrays into a size of 120 mm x 23.2 mm and 155 mm x 60 mm for chip and package, respectively. The device composed of one Panchromatic (PAN) and four different Multi- Spectral (MS) sensors. Due to its integration on the electronic design, a lot of room is clear for the thermal design. The optical and mechanical design is become very straight forward. The flight model FPA

  11. A CMOS readout circuit for microstrip detectors

    NASA Astrophysics Data System (ADS)

    Nasri, B.; Fiorini, C.

    2015-03-01

    In this work, we present the design and the results of a CMOS analog channel for silicon microstrips detectors. The readout circuit was initially conceived for the outer layers of the SuperB silicon vertex tracker (SVT), but can serve more generally other microstrip-based detection systems. The strip detectors considered show a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been investigated. The ASIC is composed by a preamplifier, shaping amplifier and a Time over Threshold (T.o.T) block for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit includes the possibility to select the peaking time of the shaper output from four values: 250 ns, 375 ns, 500 ns and 750 ns. In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The ASIC prototype has been fabricated in the 130 nm IBM technology which is considered intrinsically radiation hard. The results of the experimental characterization of a produced prototype are satisfactorily matched with simulation.

  12. NSC 800, 8-bit CMOS microprocessor

    NASA Technical Reports Server (NTRS)

    Suszko, S. F.

    1984-01-01

    The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

  13. Simulation of SEU transients in CMOS ICs

    SciTech Connect

    Kaul, N.; Bhuva, B.L.; Kerns, S.E. )

    1991-12-01

    This paper reports that available analytical models of the number of single-event-induced errors (SEU) in combinational logic systems are not easily applicable to real integrated circuits (ICs). An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combinational logic circuits to SEU. SITA is described in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used to estimate the probability that ion-device interactions produce erroneous signals capable of propagating to a latch (or n output node), and logic-level simulation to predict the spread of such erroneous, latched information through the IC. Simulation results are compared to those from SPICE for several circuit and logic configurations. SITA results are comparable to this established circuit-level code, and SITA can analyze circuits with state-of-the-art device densities (which SPICE cannot). At all IC complexity levels, SITAS offers several factors of 10 savings in simulation time over SPICE.

  14. On noise in time-delay integration CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Levski, Deyan; Choubey, Bhaskar

    2016-05-01

    Time delay integration sensors are of increasing interest in CMOS processes owing to their low cost, power and ability to integrate with other circuit readout blocks. This paper presents an analysis of the noise contributors in current day CMOS Time-Delay-Integration image sensors with various readout architectures. An analysis of charge versus voltage domain readout modes is presented, followed by a noise classification of the existing Analog Accumulator Readout (AAR) and Digital Accumulator Readout (DAR) schemes for TDI imaging. The analysis and classification of existing readout schemes include, pipelined charge transfer, buffered direct injection, voltage as well as current-mode analog accumulators and all-digital accumulator techniques. Time-Delay-Integration imaging modes in CMOS processes typically use an N-number of readout steps, equivalent to the number of TDI pixel stages. In CMOS TDI sensors, where voltage domain readout is used, the requirements over speed and noise of the ADC readout chain are increased due to accumulation of the dominant voltage readout and ADC noise with every stage N. Until this day, the latter is the primary reason for a leap-back of CMOS TDI sensors as compared to their CCD counterparts. Moreover, most commercial CMOS TDI implementations are still based on a charge-domain readout, mimicking a CCD-like operation mode. Thus, having a good understanding of each noise contributor in the signal chain, as well as its magnitude in different readout architectures, is vital for the design of future generation low-noise CMOS TDI image sensors based on a voltage domain readout. This paper gives a quantitative classification of all major noise sources for all popular implementations in the literature.

  15. Printed thin film transistors and CMOS inverters based on semiconducting carbon nanotube ink purified by a nonlinear conjugated copolymer

    NASA Astrophysics Data System (ADS)

    Xu, Wenya; Dou, Junyan; Zhao, Jianwen; Tan, Hongwei; Ye, Jun; Tange, Masayoshi; Gao, Wei; Xu, Weiwei; Zhang, Xiang; Guo, Wenrui; Ma, Changqi; Okazaki, Toshiya; Zhang, Kai; Cui, Zheng

    2016-02-01

    Two innovative research studies are reported in this paper. One is the sorting of semiconducting carbon nanotubes and ink formulation by a novel semiconductor copolymer and second is the development of CMOS inverters using not the p-type and n-type transistors but a printed p-type transistor and a printed ambipolar transistor. A new semiconducting copolymer (named P-DPPb5T) was designed and synthesized with a special nonlinear structure and more condensed conjugation surfaces, which can separate large diameter semiconducting single-walled carbon nanotubes (sc-SWCNTs) from arc discharge SWCNTs according to their chiralities with high selectivity. With the sorted sc-SWCNTs ink, thin film transistors (TFTs) have been fabricated by aerosol jet printing. The TFTs displayed good uniformity, low operating voltage (+/-2 V) and subthreshold swing (SS) (122-161 mV dec-1), high effective mobility (up to 17.6-37.7 cm2 V-1 s-1) and high on/off ratio (104-107). With the printed TFTs, a CMOS inverter was constructed, which is based on the p-type TFT and ambipolar TFT instead of the conventional p-type and n-type TFTs. Compared with other recently reported inverters fabricated by printing, the printed CMOS inverters demonstrated a better noise margin (74% 1/2 Vdd) and was hysteresis free. The inverter has a voltage gain of up to 16 at an applied voltage of only 1 V and low static power consumption.Two innovative research studies are reported in this paper. One is the sorting of semiconducting carbon nanotubes and ink formulation by a novel semiconductor copolymer and second is the development of CMOS inverters using not the p-type and n-type transistors but a printed p-type transistor and a printed ambipolar transistor. A new semiconducting copolymer (named P-DPPb5T) was designed and synthesized with a special nonlinear structure and more condensed conjugation surfaces, which can separate large diameter semiconducting single-walled carbon nanotubes (sc-SWCNTs) from arc discharge

  16. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    PubMed Central

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  17. CMOS Cell Sensors for Point-of-Care Diagnostics

    PubMed Central

    Adiguzel, Yekbun; Kulah, Haluk

    2012-01-01

    The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

  18. Improved Space Object Observation Techniques Using CMOS Detectors

    NASA Astrophysics Data System (ADS)

    Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

    2013-08-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

  19. CMOS Imaging Sensor Technology for Aerial Mapping Cameras

    NASA Astrophysics Data System (ADS)

    Neumann, Klaus; Welzenbach, Martin; Timm, Martin

    2016-06-01

    In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

  20. High-performance monolithic CMOS detectors for space applications

    NASA Astrophysics Data System (ADS)

    Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Vignon, Bruno; Magnan, Pierre; Farre, Jean A.; Corbiere, Franck; Martin-Gonthier, Philippe

    2001-12-01

    During the last 10 years, research about CMOS image sensors (also called APS - Active Pixel Sensors) has been intensively carried out, in order to offer an alternative to CCDs as image sensors. This is particularly the case for space applications as CMOS image sensors feature characteristics which are obviously of interest for flight hardware: parallel or semi-parallel architecture, on chip control and processing electronics, low power dissipation, high level of radiation tolerance... Many image sensor companies, institutes and laboratories have demonstrated the compatibility of CMOS image sensors with consumer applications: micro-cameras, video-conferencing, digital- still cameras. And recent designs have shown that APS is getting closer to the CCD in terms of performance level. However, he large majority of the existing products do not offer the specific features which are required for many space applications. ASTRIUM and SUPAERO/CIMI have decided to work together in view of developing CMOS image sensors dedicated to space business. After a brief presentation of the team organization for space image sensor design and production, the latest results of a high performances 512 X 512 pixels CMOS device characterization are presented with emphasis on the achieved electro-optical performance. Finally, the on going and short-term coming activities of the team are discussed.

  1. Printed thin film transistors and CMOS inverters based on semiconducting carbon nanotube ink purified by a nonlinear conjugated copolymer.

    PubMed

    Xu, Wenya; Dou, Junyan; Zhao, Jianwen; Tan, Hongwei; Ye, Jun; Tange, Masayoshi; Gao, Wei; Xu, Weiwei; Zhang, Xiang; Guo, Wenrui; Ma, Changqi; Okazaki, Toshiya; Zhang, Kai; Cui, Zheng

    2016-02-28

    Two innovative research studies are reported in this paper. One is the sorting of semiconducting carbon nanotubes and ink formulation by a novel semiconductor copolymer and second is the development of CMOS inverters using not the p-type and n-type transistors but a printed p-type transistor and a printed ambipolar transistor. A new semiconducting copolymer (named P-DPPb5T) was designed and synthesized with a special nonlinear structure and more condensed conjugation surfaces, which can separate large diameter semiconducting single-walled carbon nanotubes (sc-SWCNTs) from arc discharge SWCNTs according to their chiralities with high selectivity. With the sorted sc-SWCNTs ink, thin film transistors (TFTs) have been fabricated by aerosol jet printing. The TFTs displayed good uniformity, low operating voltage (±2 V) and subthreshold swing (SS) (122-161 mV dec(-1)), high effective mobility (up to 17.6-37.7 cm(2) V(-1) s(-1)) and high on/off ratio (10(4)-10(7)). With the printed TFTs, a CMOS inverter was constructed, which is based on the p-type TFT and ambipolar TFT instead of the conventional p-type and n-type TFTs. Compared with other recently reported inverters fabricated by printing, the printed CMOS inverters demonstrated a better noise margin (74% 1/2 Vdd) and was hysteresis free. The inverter has a voltage gain of up to 16 at an applied voltage of only 1 V and low static power consumption. PMID:26847814

  2. A 1.5V 120nW CMOS programmable monolithic reference generator for wireless implantable system.

    PubMed

    Chang, Sun-Il; AlAshmouny, Khaled; Yoon, Euisik

    2011-01-01

    We implement and characterize a 1.5 V 120 nW CMOS programmable monolithic reference generator for wireless implantable system. The proposed generator is optimized to be tolerable for power supply variation in a small area with programmability to generate various reference voltages and currents. The measured power line sensitivity are 0.02 / 1.1%/V for voltage and current reference, respectively. This reference generator can operate for input voltage ranging from 1.5 V to 3.5 V and implemented in an area of 0.011 mm(2), which is the smallest monolithic reference generator in 0.25 μm technology to the best of our knowledge. The output can vary from 20 nA to 33 nA for current reference and from 0.71 V to 1.03 V for voltage reference. PMID:22254967

  3. A CMOS-compatible electronic synapse device based on Cu/SiO2/W programmable metallization cells

    NASA Astrophysics Data System (ADS)

    Chen, Wenhao; Fang, Runchen; Balaban, Mehmet B.; Yu, Weijie; Gonzalez-Velo, Yago; Barnaby, Hugh J.; Kozicki, Michael N.

    2016-06-01

    In this work, the resistance plasticity of Cu/SiO2/W programmable metallization cell devices is experimentally explored for the emulation of biological synapses. PMC devices were fabricated with foundry friendly materials using standard processes. The resistance can be continuously increased or decreased with both dc and voltage pulse programming. Impedance spectroscopy results indicate that the gradual change of resistance is attributable to the expansion or contraction of a Cu-rich layer within the device. Pulse programming experiments further show that the pulse amplitude plays a more important role in resistance change than pulse width, which is consistent with the proposed ‘dual-layer’ device model. The dense resistance-state distribution, 1 V operating voltage and inherent CMOS-compatibility suggests its potential application as electronic synapse in neuromorphic computing.

  4. High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

    PubMed

    Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

    2014-05-21

    We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics. PMID:24727896

  5. A CMOS-compatible electronic synapse device based on Cu/SiO2/W programmable metallization cells.

    PubMed

    Chen, Wenhao; Fang, Runchen; Balaban, Mehmet B; Yu, Weijie; Gonzalez-Velo, Yago; Barnaby, Hugh J; Kozicki, Michael N

    2016-06-24

    In this work, the resistance plasticity of Cu/SiO2/W programmable metallization cell devices is experimentally explored for the emulation of biological synapses. PMC devices were fabricated with foundry friendly materials using standard processes. The resistance can be continuously increased or decreased with both dc and voltage pulse programming. Impedance spectroscopy results indicate that the gradual change of resistance is attributable to the expansion or contraction of a Cu-rich layer within the device. Pulse programming experiments further show that the pulse amplitude plays a more important role in resistance change than pulse width, which is consistent with the proposed 'dual-layer' device model. The dense resistance-state distribution, 1 V operating voltage and inherent CMOS-compatibility suggests its potential application as electronic synapse in neuromorphic computing. PMID:27171505

  6. ESD protection design for advanced CMOS

    NASA Astrophysics Data System (ADS)

    Huang, Jin B.; Wang, Gewen

    2001-10-01

    ESD effects in integrated circuits have become a major concern as today's technologies shrink to sub-micron/deep- sub-micron dimensions. The thinner gate oxide and shallower junction depth used in the advanced technologies make them very vulnerable to ESD damages. The advanced techniques like silicidation and STI (shallow trench insulation) used for improving other device performances make ESD design even more challenging. For non-silicided technologies, a certain DCGS (drain contact to gate edge spacing) is needed to achieve ESD hardness for nMOS output drivers and nMOS protection transistors. The typical DCGS values are 4-5um and 2-3um for 0.5um and 0.25um CMOS, respectively. The silicidation reduces the ballast resistance provided by DCGS with at least a factor of 10. As a result, scaling of the ESD performance with device width is lost and even zero ESD performance is reported for standard silicided devices. The device level ESD design is focused in this paper, which includes GGNMOS (gate grounded NMOS) and GCNMOS (gate coupled NMOS). The device level ESD testing including TLP (transmission line pulse) is given. Several ESD issues caused by advanced technologies have been pointed out. The possible solutions have been developed and summarized including silicide blocking, process optimization, back-end ballasting, and new protection scheme, dummy gate/n-well resistor ballsting, etc. Some of them require process cost increase, and others provide novel, compact, and simple design but involving royalty/IP (intellectual property) issue. Circuit level ESD design and layout design considerations are covered. The top-level ESD protection strategies are also given.

  7. Adiabatic circuits: converter for static CMOS signals

    NASA Astrophysics Data System (ADS)

    Fischer, J.; Amirante, E.; Bargagli-Stoffi, A.; Schmitt-Landsiedel, D.

    2003-05-01

    Ultra low power applications can take great advantages from adiabatic circuitry. In this technique a multiphase system is used which consists ideally of trapezoidal voltage signals. The input signals to be processed will often come from a function block realized in static CMOS. The static rectangular signals must be converted for the oscillating multiphase system of the adiabatic circuitry. This work shows how to convert the input signals to the proposed pulse form which is synchronized to the appropriate supply voltage. By means of adder structures designed for a 0.13µm technology in a 4-phase system there will be demonstrated, which additional circuits are necessary for the conversion. It must be taken into account whether the data arrive in parallel or serial form. Parallel data are all in one phase and therefore it is advantageous to use an adder structure with a proper input stage, e.g. a Carry Lookahead Adder (CLA). With a serial input stage it is possible to read and to process four signals during one cycle due to the adiabatic 4-phase system. Therefore input signals with a frequency four times higher than the adiabatic clock frequency can be used. This reduces the disadvantage of the slow clock period typical for adiabatic circuits. By means of an 8 bit Ripple Carry Adder (8 bit RCA) the serial reading will be introduced. If the word width is larger than 4 bits the word can be divided in 4 bit words which are processed in parallel. This is the most efficient way to minimize the number of input lines and pads. At the same time a high throughput is achieved.

  8. Radiation tolerant back biased CMOS VLSI

    NASA Technical Reports Server (NTRS)

    Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

    2003-01-01

    A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

  9. Fabrication of the planar angular rotator using the CMOS process

    NASA Astrophysics Data System (ADS)

    Dai, Ching-Liang; Chang, Chien-Liu; Chen, Hung-Lin; Chang, Pei-Zen

    2002-05-01

    In this investigation we propose a novel planar angular rotator fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. Following the 0.6 μm single poly triple metal (SPTM) CMOS process, the device is completed by a simple maskless, post-process etching step. The rotor of the planar angular rotator rotates around its geometric center with electrostatic actuation. The proposed design adopts an intelligent mechanism including the slider-crank system to permit simultaneous motion. The CMOS planar angular rotator could be driven with driving voltages of around 40 V. The design proposed here has a shorter response time and longer life, without problems of friction and wear, compared to the more common planar angular micromotor.

  10. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    PubMed Central

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  11. A CMOS humidity sensor for passive RFID sensing applications.

    PubMed

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  12. CMOS Monolithic Active Pixel Sensors (MAPS): Developments and future outlook

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; Fant, A.; Gasiorek, P.; Esbrand, C.; Griffiths, J. A.; Metaxas, M. G.; Royle, G. J.; Speller, R.; Venanzi, C.; van der Stelt, P. F.; Verheij, H.; Li, G.; Theodoridis, S.; Georgiou, H.; Cavouras, D.; Hall, G.; Noy, M.; Jones, J.; Leaver, J.; Machin, D.; Greenwood, S.; Khaleeq, M.; Schulerud, H.; Østby, J. M.; Triantis, F.; Asimidis, A.; Bolanakis, D.; Manthos, N.; Longo, R.; Bergamaschi, A.

    2007-12-01

    Re-invented in the early 1990s, on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology are today the most sold solid-state imaging devices, overtaking the traditional technology of Charge-Coupled Devices (CCD). The slow uptake of CMOS MAPS started with low-end applications, for example web-cams, and is slowly pervading the high-end applications, for example in prosumer digital cameras. Higher specifications are required for scientific applications: very low noise, high speed, high dynamic range, large format and radiation hardness are some of these requirements. This paper will present a brief overview of the CMOS Image Sensor technology and of the requirements for scientific applications. As an example, a sensor for X-ray imaging will be presented. This sensor was developed within a European FP6 Consortium, intelligent imaging sensors (I-ImaS).

  13. Operation and biasing for single device equivalent to CMOS

    DOEpatents

    Welch, James D.

    2001-01-01

    Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

  14. IGBT scaling principle toward CMOS compatible wafer processes

    NASA Astrophysics Data System (ADS)

    Tanaka, Masahiro; Omura, Ichiro

    2013-02-01

    A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed "Structure Oriented" analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies.

  15. VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

    NASA Astrophysics Data System (ADS)

    Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

    2014-10-01

    This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

  16. Design of CMOS logic gates for TID radiation

    NASA Technical Reports Server (NTRS)

    Attia, John Okyere; Sasabo, Maria L.

    1993-01-01

    The rise time, fall time and propagation delay of the logic gates were derived. The effects of total ionizing dose (TID) radiation on the fall and rise times of CMOS logic gates were obtained using C program calculations and PSPICE simulations. The variations of mobility and threshold voltage on MOSFET transistors when subjected to TID radiation were used to determine the dependence of switching times on TID. The results of this work indicate that by increasing the size of P-channel transistor with respect to the N-channel transistors of the CMOS gates, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in TID radiation.

  17. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-07

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint... complaint entitled Certain CMOS Image Sensors and Products Containing Same, DN 2895; the Commission is... importation of certain CMOS image sensors and products containing same. The complaint names as...

  18. Spectrometer with CMOS demodulation of fiber optic Bragg grating sensors

    NASA Astrophysics Data System (ADS)

    Christiansen, Martin Brokner

    A CMOS imager based spectrometer is developed to interrogate a network containing a large number of Bragg grating sensors. The spectrometer uses a Prism-Grating- Prism (PGP) to spectrally separate serially multiplexed Bragg reflections on a single fiber. As a result, each Bragg grating produces a discrete spot on the CMOS imager that shifts horizontally as the Bragg grating experiences changes in strain or temperature. The reflected wavelength of the spot can be determined by finding the center of the spot produced. The use of a randomly addressable CMOS imager enables a flexible sampling rate. Some fibers can be interrogated at a high sampling rate while others can be interrogated at a low sampling rate. However, the use of a CMOS imager leads to several unique problems in terms of signal processing. These include a logarithmic pixel response, a low signal-to-noise ratio, a long pixel time constant, and software issues. The expected capabilities of the CMOS imager based spectrometer are determined with a theoretical model. The theoretical model tests three algorithms for determining the center of the spot: single row centroid, single row parabolic fit, and entire spot centroid. The theoretical results are compared to laboratory test data and field test data. The CMOS based spectrometer is capable of interrogating many optical fibers, and in the configuration tested, the fiber bundle consisted of 23 fibers. Using this system, a single fiber can be interrogated from 778 nm to 852 nm at 2100 Hz or multiple fibers can be interrogated over the same wavelength so that the total number of fiber interrogations is up to 2100 per second. The reflected Bragg wavelength can be determined within +/-3pm, corresponding to a +/-3μɛ uncertainty.

  19. A 65 nm CMOS LNA for Bolometer Application

    NASA Astrophysics Data System (ADS)

    Huang, Tom Nan; Boon, Chirn Chye; Zhu, Forest Xi; Yi, Xiang; He, Xiaofeng; Feng, Guangyin; Lim, Wei Meng; Liu, Bei

    2016-04-01

    Modern bolometers generally consist of large-scale arrays of detectors. Implemented in conventional technologies, such bolometer arrays suffer from integrability and productivity issues. Recently, the development of CMOS technologies has presented an opportunity for the massive production of high-performance and highly integrated bolometers. This paper presents a 65-nm CMOS LNA designed for a millimeter-wave bolometer's pre-amplification stage. By properly applying some positive feedback, the noise figure of the proposed LNA is minimized at under 6 dB and the bandwidth is extended to 30 GHz.

  20. Impact of technology trends on SEU in CMOS SRAMs

    SciTech Connect

    Dodd, P.E.; Sexton, F.W.; Hash, G.L.; Shaneyfelt, M.R.; Draper, B.L.; Farino, A.J.; Flores, R.S.

    1996-12-01

    The impact of technology trends on the SEU hardness of epitaxial CMOS SRAMs is investigated using three-dimensional simulation. The authors study trends in SEU susceptibility with parameter variations across and within technology generations. Upset mechanisms for various strike locations and their dependence on gate-length scaling are explored. Such studies are useful for technology development and providing input for process and design decisions. An application of SEU simulation to the development of a 0.5-{micro}m radiation-hardened CMOS SRAM is presented.

  1. CHARACTERIZATION OF THE DNA OF A NONOCCLUDED BACULOVIRUS, HZ-1V

    EPA Science Inventory

    The DNA of the nonoccluded baculovirus (Hz-1V) obtained from the IMC-Hz-1 cell line was characterized by physicochemical and restriction endonuclease techniques. Hz-1V DNA isolated from purified virus had buoyant densities of 1.58 and 1.54 g/ml in CsC1-ethidium bromide density gr...

  2. A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

    NASA Technical Reports Server (NTRS)

    Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

    1993-01-01

    A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

  3. Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs

    NASA Astrophysics Data System (ADS)

    Nuñez, Juan; Avedillo, María J.; Quintana, José M.

    2011-05-01

    The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. We compare RTD-CMOS and pure CMOS realizations of a network of logic gates which can be operated in a gate-level pipeline. Significant lower average power is obtained for RTD-CMOS implementations.

  4. A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics.

    PubMed

    Huang, Haiyun; Wang, Dejun; Xu, Yue

    2015-01-01

    This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW. PMID:26516864

  5. An SEU-hardened CMOS data latch design

    SciTech Connect

    Rockett, L.R. Jr.

    1988-12-01

    A Single Event Upset (SEU)-hardened Complementary Metal-Oxide Semiconductor (CMOS) data latch design is described. The hardness is achieved by virtue of the latch design, thus no fabrication process or design groundrule development is required. Hardness is gained with comparatively little adverse impact on performance. Cyclotron tests provided hardness verification.

  6. CMOS VLSI Layout and Verification of a SIMD Computer

    NASA Technical Reports Server (NTRS)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  7. Attributes and drawbacks of submicron CMOS for IR FPA readouts

    NASA Astrophysics Data System (ADS)

    Kozlowski, L. J.

    1998-09-01

    The availability of submicron CMOS has enabled the development of shingle-chip IR cameras having performance capabilities and on-chip functions which were previously impossible. Sensor designers are, however, encoutering and overcoming several challanges including steadily decreasing operating voltage.

  8. Relationship between IBICC imaging and SEU in CMOS ICs

    SciTech Connect

    Sexton, F.W.; Horn, K.M.; Doyle, B.L.; Laird, J.S.; Cholewa, M.; Saint, A.; Legge, G.J.F.

    1993-03-01

    Ion-beam-induced charge-collection (IBICC) images of the TA670 16K-bit CMOS SRAM are analyzed and compared to previous SEU images. Enhanced charge collection was observed in the n-source/drains regions consistent with bipolar amplification or shunting.

  9. Relationship between IBICC imaging and SEU in CMOS ICs

    SciTech Connect

    Sexton, F.W.; Horn, K.M.; Doyle, B.L. ); Laird, J.S.; Cholewa, M.; Saint, A.; Legge, G.J.F. )

    1993-01-01

    Ion-beam-induced charge-collection (IBICC) images of the TA670 16K-bit CMOS SRAM are analyzed and compared to previous SEU images. Enhanced charge collection was observed in the n-source/drains regions consistent with bipolar amplification or shunting.

  10. Overcoming scaling concerns in a radiation-hardening CMOS technology

    SciTech Connect

    Maimon, J.; Haddad, N.

    1999-12-01

    Scaling efforts to develop an advanced radiation-hardened CMOS process to support a 4M SRAM are described. Issues encountered during scaling of transistor, isolation, and resistor elements are discussed, as well as the solutions used to overcome these issues. Transistor data, total dose radiation results, and the performance of novel resistors for prevention of single event upsets (SEU) are presented.

  11. Reliability design of CMOS image sensor for space applications

    NASA Astrophysics Data System (ADS)

    Xie, Ning; Chen, Shijun; Chen, Yongping

    2013-08-01

    In space applications, sensors work in very harsh space environment. Thus the reliability design must be carefully considered. This paper addresses the techniques which effectively increase the reliability of CMOS image sensors. A radiation tolerant pixel design which is implemented in a sun tracker sensor is presented. Measurement results of total dose radiation, SEL, SEU, etc prove the radiation immunity of the sensor.

  12. Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

    PubMed Central

    Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

    2010-01-01

    This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K. PMID:22205869

  13. Thin Film on CMOS Active Pixel Sensor for Space Applications

    PubMed Central

    Schulze Spuentrup, Jan Dirk; Burghartz, Joachim N.; Graf, Heinz-Gerd; Harendt, Christine; Hutter, Franz; Nicke, Markus; Schmidt, Uwe; Schubert, Markus; Sterzel, Juergen

    2008-01-01

    A 664 × 664 element Active Pixel image Sensor (APS) with integrated analog signal processing, full frame synchronous shutter and random access for applications in star sensors is presented and discussed. A thick vertical diode array in Thin Film on CMOS (TFC) technology is explored to achieve radiation hardness and maximum fill factor.

  14. CMOS Ultra Low Power Radiation Tolerant (CULPRiT) Microelectronics

    NASA Technical Reports Server (NTRS)

    Yeh, Penshu; Maki, Gary

    2007-01-01

    Space Electronics needs Radiation Tolerance or hardness to withstand the harsh space environment: high-energy particles can change the state of the electronics or puncture transistors making them disfunctional. This viewgraph document reviews the use of CMOS Ultra Low Power Radiation Tolerant circuits for NASA's electronic requirements.

  15. CCD AND PIN-CMOS DEVELOPMENTS FOR LARGE OPTICAL TELESCOPE.

    SciTech Connect

    RADEKA, V.

    2006-04-03

    Higher quantum efficiency in near-IR, narrower point spread function and higher readout speed than with conventional sensors have been receiving increased emphasis in the development of CCDs and silicon PIN-CMOS sensors for use in large optical telescopes. Some key aspects in the development of such devices are reviewed.

  16. Mechanically Flexible and High-Performance CMOS Logic Circuits

    PubMed Central

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-01-01

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

  17. Low light level CMOS sensor for night vision systems

    NASA Astrophysics Data System (ADS)

    Gross, Elad; Ginat, Ran; Nesher, Ofer

    2015-05-01

    For many years image intensifier tubes were used for night vision systems. In 2014, Elbit systems developed a digital low-light level CMOS sensor, with similar sensitivity to a Gen II image-intensifiers, down to starlight conditions. In this work we describe: the basic principle behind this sensor, physical model for low-light performance estimation and results of field testing.

  18. Mechanically Flexible and High-Performance CMOS Logic Circuits.

    PubMed

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-01-01

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

  19. Research-grade CMOS image sensors for remote sensing applications

    NASA Astrophysics Data System (ADS)

    Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Martin-Gonthier, Philippe; Corbiere, Franck; Belliot, Pierre; Estribeau, Magali

    2004-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding space applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this paper will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments and performances of CIS prototypes built using an imaging CMOS process will be presented in the corresponding section.

  20. Research-grade CMOS image sensors for demanding space applications

    NASA Astrophysics Data System (ADS)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2004-06-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  1. CMOS image sensors as an efficient platform for glucose monitoring.

    PubMed

    Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

    2013-10-01

    Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications. PMID:23900281

  2. Effects Of Dose Rates On Radiation Damage In CMOS Parts

    NASA Technical Reports Server (NTRS)

    Goben, Charles A.; Coss, James R.; Price, William E.

    1990-01-01

    Report describes measurements of effects of ionizing-radiation dose rate on consequent damage to complementary metal oxide/semiconductor (CMOS) electronic devices. Depending on irradiation time and degree of annealing, survivability of devices in outer space, or after explosion of nuclear weapons, enhanced. Annealing involving recovery beyond pre-irradiation conditions (rebound) detrimental. Damage more severe at lower dose rates.

  3. Fabrication and characterization of CMOS-MEMS thermoelectric micro generators.

    PubMed

    Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

    2010-01-01

    This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K. PMID:22205869

  4. Upper-Bound Estimates Of SEU in CMOS

    NASA Technical Reports Server (NTRS)

    Edmonds, Larry D.

    1990-01-01

    Theory of single-event upsets (SEU) (changes in logic state caused by energetic charged subatomic particles) in complementary metal oxide/semiconductor (CMOS) logic devices extended to provide upper-bound estimates of rates of SEU when limited experimental information available and configuration and dimensions of SEU-sensitive regions of devices unknown. Based partly on chord-length-distribution method.

  5. CMOS Active-Pixel Image Sensor With Simple Floating Gates

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

    1996-01-01

    Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

  6. Planar CMOS analog SiPMs: design, modeling, and characterization

    NASA Astrophysics Data System (ADS)

    Zou, Yu; Villa, Federica; Bronzi, Danilo; Tisa, Simone; Tosi, Alberto; Zappa, Franco

    2015-11-01

    Silicon photomultipliers (SiPMs) are large area detectors consisting of an array of single-photon-sensitive microcells, which make SiPMs extremely attractive to substitute the photomultiplier tubes in many applications. We present the design, fabrication, and characterization of analog SiPMs in standard planar 0.35 μm CMOS technology, with about 1 mm × 1 mm total area and different kinds of microcells, based on single-photon avalanche diodes with 30 μm diameter reaching 21.0% fill-factor (FF), 50 μm diameter (FF = 58.3%) or 50 μm square active area with rounded corner of 5 μm radius (FF = 73.7%). We also developed the electrical SPICE model for CMOS SiPMs. Our CMOS SiPMs have 25 V breakdown voltage, in line with most commercial SiPMs and higher gain (8.8 × 106, 13.2 × 106, and 15.0 × 106, respectively). Although dark count rate density is slightly higher than state-of-the-art analog SiPMs, the proposed standard CMOS processing opens the feasibility of integration with active electronics, for switching hot pixels off, drastically reducing the overall dark count rate, or for further on-chip processing.

  7. Direct readout of gaseous detectors with tiled CMOS circuits

    NASA Astrophysics Data System (ADS)

    Visschers, J. L.; Blanco Carballo, V.; Chefdeville, M.; Colas, P.; van der Graaf, H.; Schmitz, J.; Smits, S.; Timmermans, J.

    2007-03-01

    A coordinated design effort is underway, exploring the three-dimensional direct readout of gaseous detectors by an anode plate equipped with a tiled array of many CMOS pixel readout ASICs, having amplification grids integrated on their topsides and being contacted on their backside.

  8. Neutron induced soft errors in CMOS memories under reduced bias

    SciTech Connect

    Hazucha, P.; Svensson, C.; Johansson, K.

    1998-12-01

    A custom designed 16 kbit CMOS memory was irradiated by 14 MeV neutrons and 100 MeV neutrons. SEU cross sections were evaluated under different supply voltages. The cross section values are compared to those predicted by the BGR model.

  9. INDEP approach for leakage reduction in nanoscale CMOS circuits

    NASA Astrophysics Data System (ADS)

    Sharma, Vijay Kumar; Pattanaik, Manisha; Raj, Balwinder

    2015-02-01

    Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node.

  10. Analysis of pixel circuits in CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Mei, Zou; Chen, Nan; Yao, Li-bin

    2015-04-01

    CMOS image sensors (CIS) have lower power consumption, lower cost and smaller size than CCD image sensors. However, generally CCDs have higher performance than CIS mainly due to lower noise. The pixel circuit used in CIS is the first part of the signal processing circuit and connected to photodiode directly, so its performance will greatly affect the CIS or even the whole imaging system. To achieve high performance, CMOS image sensors need advanced pixel circuits. There are many pixel circuits used in CIS, such as passive pixel sensor (PPS), 3T and 4T active pixel sensor (APS), capacitive transimpedance amplifier (CTIA), and passive pixel sensor (PPS). At first, the main performance parameters of each pixel structure including the noise, injection efficiency, sensitivity, power consumption, and stability of bias voltage are analyzed. Through the theoretical analysis of those pixel circuits, it is concluded that CTIA pixel circuit has good noise performance, high injection efficiency, stable photodiode bias, and high sensitivity with small integrator capacitor. Furthermore, the APS and CTIA pixel circuits are simulated in a standard 0.18-μm CMOS process and using a n-well/p-sub photodiode by SPICE and the simulation result confirms the theoretical analysis result. It shows the possibility that CMOS image sensors can be extended to a wide range of applications requiring high performance.

  11. Integrated imaging sensor systems with CMOS active pixel sensor technology

    NASA Technical Reports Server (NTRS)

    Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

    2002-01-01

    This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

  12. Hybrid CMOS SiPIN detectors as astronomical imagers

    NASA Astrophysics Data System (ADS)

    Simms, Lance Michael

    Charge Coupled Devices (CCDs) have dominated optical and x-ray astronomy since their inception in 1969. Only recently, through improvements in design and fabrication methods, have imagers that use Complimentary Metal Oxide Semiconductor (CMOS) technology gained ground on CCDs in scientific imaging. We are now in the midst of an era where astronomers might begin to design optical telescope cameras that employ CMOS imagers. The first three chapters of this dissertation are primarily composed of introductory material. In them, we discuss the potential advantages that CMOS imagers offer over CCDs in astronomical applications. We compare the two technologies in terms of the standard metrics used to evaluate and compare scientific imagers: dark current, read noise, linearity, etc. We also discuss novel features of CMOS devices and the benefits they offer to astronomy. In particular, we focus on a specific kind of hybrid CMOS sensor that uses Silicon PIN photodiodes to detect optical light in order to overcome deficiencies of commercial CMOS sensors. The remaining four chapters focus on a specific type of hybrid CMOS Silicon PIN sensor: the Teledyne Hybrid Visible Silicon PIN Imager (HyViSI). In chapters four and five, results from testing HyViSI detectors in the laboratory and at the Kitt Peak 2.1m telescope are presented. We present our laboratory measurements of the standard detector metrics for a number of HyViSI devices, ranging from 1k×1k to 4k×4k format. We also include a description of the SIDECAR readout circuit that was used to control the detectors. We then show how they performed at the telescope in terms of photometry, astrometry, variability measurement, and telescope focusing and guiding. Lastly, in the final two chapters we present results on detector artifacts such as pixel crosstalk, electronic crosstalk, and image persistence. One form of pixel crosstalk that has not been discussed elsewhere in the literature, which we refer to as Interpixel Charge

  13. A novel multi-actuation CMOS RF MEMS switch

    NASA Astrophysics Data System (ADS)

    Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

    2008-12-01

    This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

  14. Fully CMOS analog and digital SiPMs

    NASA Astrophysics Data System (ADS)

    Zou, Yu; Villa, Federica; Bronzi, Danilo; Tisa, Simone; Tosi, Alberto; Zappa, Franco

    2015-03-01

    Silicon Photomultipliers (SiPMs) are emerging single photon detectors used in many applications requiring large active area, photon-number resolving capability and immunity to magnetic fields. We present three families of analog SiPM fabricated in a reliable and cost-effective fully standard planar CMOS technology with a total photosensitive area of 1×1 mm2. These three families have different active areas with fill-factors (21%, 58.3%, 73.7%) comparable to those of commercial SiPM, which are developed in vertical (current flow) custom technologies. The peak photon detection efficiency in the near-UV tops at 38% (fill-factor included) comparable to commercial custom-process ones and dark count rate density is just a little higher than the best-in-class commercial analog SiPMs. Thanks to the CMOS processing, these new SiPMs can be integrated together with active components and electronics both within the microcell and on-chip, in order to act at the microcell level or to perform global pre-processing. We also report CMOS digital SiPMs in the same standard CMOS technology, based on microcells with digitalized processing, all integrated on-chip. This CMOS digital SiPMs has four 32×1 cells (128 microcells), each consisting of SPAD, active quenching circuit with adjustable dead time, digital control (to switch off noisy SPADs and readout position of detected photons), and fast trigger output signal. The achieved 20% fill-factor is still very good.

  15. Contact CMOS imaging of gaseous oxygen sensor array

    PubMed Central

    Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

    2014-01-01

    We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

  16. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; French, M.; Manolopoulos, S.; Tyndel, M.; Allport, P.; Bates, R.; O'Shea, V.; Hall, G.; Raymond, M.

    2003-03-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to tape. Because of the large number of pixels, data reduction is needed on the sensor itself or just outside. This brings in stringent requirements on the temporal noise as well as to the sensor uniformity, expressed as a Fixed Pattern Noise (FPN). A pixel architecture with an additional transistor is proposed. This architecture, coupled to correlated double sampling of the signal will allow cancellation of the two dominant noise sources, namely the reset or kTC noise and the FPN. A prototype has been designed in a standard 0.25 μm CMOS technology. It has also a structure for electrical calibration of the sensor. The prototype is functional and detailed tests are under way.

  17. An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

    PubMed Central

    Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

  18. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    PubMed

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

  19. Low-cost uncooled infrared detector arrays in standard CMOS

    NASA Astrophysics Data System (ADS)

    Eminoglu, Selim; Tanrikulu, M. Y.; Akin, Tayfun

    2003-09-01

    This paper reports the development of a low-cost 128 x 128 uncooled infrared focal plane array (FPA) based on suspended and thermally isolated CMOS p+-active/n-well diodes. The FPA is fabricated using a standard 0.35 μm CMOS process followed by simple post-CMOS bulk micromachining that does not require any critical lithography or complicated deposition steps; and therefore, the cost of the uncooled FPA is almost equal to the cost of the CMOS chip. The post-CMOS fabrication steps include an RIE etching to reach the bulk silicon and an anisotropic silicon etching to obtain thermally isolated pixels. During the RIE etching, CMOS metal layers are used as masking layers, and therefore, narrow openings such as 2 μm can be defined between the support arms. This approach allows achieving small pixel size of 40 μm x 40 μm with a fill factor of 44%. The FPA is scanned at 30 fps by monolithically integrated multi-channel parallel readout circuitry which is composed of low-noise differential transconductance amplifiers, switched capacitor (SC) integrators, sample-and-hold circuits, and various other circuit blocks for reducing the effects of variations in detector voltage and operating temperature. The fabricated detector has a temperature coefficient of -2 mV/K, a thermal conductance value of 1.8 x 10-7 W/K, and a thermal time constant value of 36 msec, providing a measured DC responsivity (R) of 4970 V/W under continuous bias. Measured detector noise is 0.69 μV in 8 kHz bandwidth at 30 fps scanning rate, resulting a measured detectivity (D*) of 9.7 x 108 cm√HzW. Contribution of the 1/f noise component is found to be negligible due to the single crystal nature of the silicon n-well and its low value at low bias levels. The noise of the readout circuit is measured as 0.76 μV, resulting in an expected NETD value of 1 K when scanned at 30 fps using f=1 optics. This NETD value can be decreased below 350 mK by decreasing the electrical bandwidth with the help of increased

  20. Improved Space Object Orbit Determination Using CMOS Detectors

    NASA Astrophysics Data System (ADS)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  1. High-Voltage-Input Level Translator Using Standard CMOS

    NASA Technical Reports Server (NTRS)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  2. CMOS VLSI Active-Pixel Sensor for Tracking

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  3. Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

    SciTech Connect

    Sumant, A.V.; Auciello, O.; Yuan, H.-C; Ma, Z.; Carpick, R. W.; Mancini, D. C.; Univ. of Wisconsin; Univ. of Pennsylvania

    2009-05-01

    Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materials integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.

  4. TID Simulation of Advanced CMOS Devices for Space Applications

    NASA Astrophysics Data System (ADS)

    Sajid, Muhammad

    2016-07-01

    This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

  5. Radiation Hard 0.13 Micron CMOS Library at IHP

    NASA Astrophysics Data System (ADS)

    Jagdhold, U.

    2013-08-01

    To support space applications we have developed an 0.13 micron CMOS library which should be radiation hard up to 200 krad. The article describes the concept to come to a radiation hard digital circuit and was introduces in 2010 [1]. By introducing new radiation hard design rules we will minimize IC-level leakage and single event latch-up (SEL). To reduce single event upset (SEU) we add two p-MOS transistors to all flip flops. For reliability reasons we use double contacts in all library elements. The additional rules and the library elements are integrated in our Cadence mixed signal design kit, “Virtuoso” IC6.1 [2]. A test chip is produced with our in house 0.13 micron BiCMOS technology, see Ref. [3]. As next step we will doing radiation tests according the european space agency (ESA) specifications, see Ref. [4], [5].

  6. Radiation Hard 0.25 Micron CMOS Library at IHP

    NASA Astrophysics Data System (ADS)

    Jagdhold, U.

    2008-08-01

    To support space applications we have produced a test chip with our in house 0.25 micron BiCMOS- Technology. Then the chips were radiated and measured. During measurements no threshold voltage shift and no single event latchup (SEL) were obtained up to a level of 200 krad. As conclusion of the measurement we developed new radiation hard design rules and according to these rules we created a new radiation hard CMOS library. With this new library we produced a Leon3 chip with triple module redundancy. Single event upsets did occur. Therefore we upgrade the library to make the flip flops more resistant against single event upset (SEU) by adding two p-MOS transistors.

  7. A CMOS image sensor dedicated to medical gamma camera application

    NASA Astrophysics Data System (ADS)

    Salahuddin, Nur S.; Paindavoine, Michel; Ginhac, Dominique; Parmentier, Michel; Tamda, Najia

    2005-03-01

    Generally, medical Gamma Camera are based on the Anger principle. These cameras use a scintillator block coupled to a bulky array of photomultiplier tube (PMT). To simplify this, we designed a new integrated CMOS image sensor in order to replace bulky PMT photodetetors. We studied several photodiodes sensors including current mirror amplifiers. These photodiodes have been fabricated using a CMOS 0.6 micrometers process from Austria Mikro Systeme (AMS). Each sensor pixel in the array occupies respectively, 1mm x 1mm area, 0.5mm x 0.5mm area and 0.2mm 0.2mm area with fill factor 98 % and total chip area is 2 square millimeters. The sensor pixels show a logarithmic response in illumination and are capable of detecting very low green light emitting diode (less than 0.5 lux) . These results allow to use our sensor in new Gamma Camera solid-state concept.

  8. Fundamental performance differences between CMOS and CCD imagers: Part II

    NASA Astrophysics Data System (ADS)

    Janesick, James; Andrews, James; Tower, John; Grygon, Mark; Elliott, Tom; Cheng, John; Lesser, Michael; Pinter, Jeff

    2007-09-01

    A new class of CMOS imagers that compete with scientific CCDs is presented. The sensors are based on deep depletion backside illuminated technology to achieve high near infrared quantum efficiency and low pixel cross-talk. The imagers deliver very low read noise suitable for single photon counting - Fano-noise limited soft x-ray applications. Digital correlated double sampling signal processing necessary to achieve low read noise performance is analyzed and demonstrated for CMOS use. Detailed experimental data products generated by different pixel architectures (notably 3TPPD, 5TPPD and 6TPG designs) are presented including read noise, charge capacity, dynamic range, quantum efficiency, charge collection and transfer efficiency and dark current generation. Radiation damage data taken for the imagers is also reported.

  9. A fully integrated CMOS inverse sine circuit for computational systems

    NASA Astrophysics Data System (ADS)

    Seon, Jong-Kug

    2010-08-01

    An inverse trigonometric function generator using CMOS technology is presented and implemented. The development and synthesis of inverse trigonometric functional circuits based on the simple approximation equations are also introduced. The proposed inverse sine function generator has the infinite input range and can be used in many measurement and instrumentation systems. The nonlinearity of less than 2.8% for the entire input range of 0.5 Vp-p with a small-signal bandwidth of 3.2 MHz is achieved. The chip implemented in 0.25 μm CMOS process operates from a single 1.8 V supply. The measured power consumption and the active chip area of the inverse sine function circuit are 350 μW and 0.15 mm2, respectively.

  10. Monolithic CMOS-MEMS integration for high-g accelerometers

    NASA Astrophysics Data System (ADS)

    Narasimhan, Vinayak; Li, Holden; Tan, Chuan Seng

    2014-10-01

    This paper highlights work-in-progress towards the conceptualization, simulation, fabrication and initial testing of a silicon-germanium (SiGe) integrated CMOS-MEMS high-g accelerometer for military, munition, fuze and shock measurement applications. Developed on IMEC's SiGe MEMS platform, the MEMS offers a dynamic range of 5,000 g and a bandwidth of 12 kHz. The low noise readout circuit adopts a chopper-stabilization technique implementing the CMOS through the TSMC 0.18 µm process. The device structure employs a fully differential split comb-drive set up with two sets of stators and a rotor all driven separately. Dummy structures acting as protective over-range stops were designed to protect the active components when under impacts well above the designed dynamic range.

  11. A CMOS integrated timing discriminator circuit for fast scintillation counters

    SciTech Connect

    Jochmann, M.W.

    1998-06-01

    Based on a zero-crossing discriminator using a CR differentiation network for pulse shaping, a new CMOS integrated timing discriminator circuit is proposed for fast (t{sub r} {ge} 2 ns) scintillation counters at the cooler synchrotron COSY-Juelich. By eliminating the input signal`s amplitude information by means of an analog continuous-time divider, a normalized pulse shape at the zero-crossing point is gained over a wide dynamic input amplitude range. In combination with an arming comparator and a monostable multivibrator this yields in a highly precise timing discriminator circuit, that is expected to be useful in different time measurement applications. First measurement results of a CMOS integrated logarithmic amplifier, which is part of the analog continuous-time divider, agree well with the corresponding simulations. Moreover, SPICE simulations of the integrated discriminator circuit promise a time walk well below 200 ps (FWHM) over a 40 dB input amplitude dynamic range.

  12. A Brief Discussion of Radiation Hardening of CMOS Microelectronics

    SciTech Connect

    Myers, D.R.

    1998-12-18

    Commercial microchips work well in their intended environments. However, generic microchips will not fimction correctly if exposed to sufficient amounts of ionizing radiation, the kind that satellites encounter in outer space. Modern CMOS circuits must overcome three specific concerns from ionizing radiation: total-dose, single-event, and dose-rate effects. Minority-carrier devices such as bipolar transistors, optical receivers, and solar cells must also deal with recombination-generation centers caused by displacement damage, which are not major concerns for majority-carrier CMOS devices. There are ways to make the chips themselves more resistant to radiation. This extra protection, called radiation hardening, has been called both a science and an art. Radiation hardening requires both changing the designs of the chips and altering the ways that the chips are manufactured.

  13. Diffuse reflectance measurements using lensless CMOS imaging chip

    NASA Astrophysics Data System (ADS)

    Schelkanova, I.; Pandya, A.; Shah, D.; Lilge, L.; Douplik, A.

    2014-10-01

    To assess superficial epithelial microcirculation, a diagnostic tool should be able to detect the heterogeneity of microvasculature, and to monitor qualitative derangement of perfusion in a diseased condition. Employing a lensless CMOS imaging chip with an RGB Bayer filter, experiments were conducted with a microfluidic platform to obtain diffuse reflectance maps. Haemoglobin (Hb) solution (160 g/l) was injected in the periodic channels (grooves) of the microfluidic phantom which were covered with ~250 μm thick layer of intralipid to obtain a diffusive environment. Image processing was performed on data acquired on the surface of the phantom to evaluate the diffuse reflectance from the subsurface periodic pattern. Thickness of the microfluidic grooves, the wavelength dependent contrast between Hb and the background, and effective periodicity of the grooves were evaluated. Results demonstrate that a lens-less CMOS camera is capable of capturing images of subsurface structures with large field of view.

  14. A back-illuminated megapixel CMOS image sensor

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

    2005-01-01

    In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

  15. CMOS floating-point vector-arithmetic unit

    NASA Astrophysics Data System (ADS)

    Timmermann, D.; Rix, B.; Hahn, H.; Hosticka, B. J.

    1994-05-01

    This work describes a floating-point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine, hyperbolic (co)sine, square root, natural logarithm, inverse (hyperbolic) tangent, vector norm, and phase. The chip has been integrated in 1.6 micron double-metal n-well CMOS technology and achieves a normalized peak performance of 220 MFLOPS.

  16. Accelerated life testing effects on CMOS microcircuit characteristics, phase 1

    NASA Technical Reports Server (NTRS)

    Maximow, B.

    1976-01-01

    An accelerated life test of sufficient duration to generate a minimum of 50% cumulative failures in lots of CMOS devices was conducted to provide a basis for determining the consistency of activation energy at 250 C. An investigation was made to determine whether any thresholds were exceeded during the high temperature testing, which could trigger failure mechanisms unique to that temperature. The usefulness of the 250 C temperature test as a predictor of long term reliability was evaluated.

  17. Characterization of a CMOS detector for limited-view mammography

    NASA Astrophysics Data System (ADS)

    Elbakri, Idris A.

    2007-03-01

    Sensors based on complementary metal oxide semiconductors (CMOS) technology have recently been considered for mammography applications. CMOS offers the advantages of lower cost and relative ease of fabrications. We report on the evaluation of a CMOS imager (C9730DK, Hamamatsu Corporation) with 14-bit digitization and 50-micron detector element (del) resolution. The imager has an active area of 5 x 5 cm and uses 160-micron layer of needle-crystal CsI (55 mg/cc) to convert x-rays to light. The detector is suitable for spot and specimen imaging and image-guided biopsy. To evaluate resolution performance, we measured the modulation transfer function (MTF) using the slanted edge method. We also measured the normalized noise power spectrum (NNPS) using Fourier analysis of uniform images. The MTF and NNPS were used to determine the detective quantum efficiency (DQE) of the detector. The detector was characterized using a molybdenum target/molybdenum filter mammography x-ray source operated at 28 kVp with 44mm of PMMA added to mimic clinical beam quality (HVL = 0.62 mm Al). Our analysis showed that the imager had a linear response. The MTF was 28% at 5 lp/mm and 8% at 10 lp/mm. The product of the NNPS and exposure showed that the detector was quantum limited. The DQE near 0 lp/mm was in the 55-60% range. The DQE and MTF performance of the CMOS detector are comparable to published values for other digital mammography detectors.

  18. A BiCMOS integrated charge to amplitude converter

    SciTech Connect

    Gallin-Martel, L.; Pouxe, J.; Rossetto, O.

    1996-12-31

    This paper describes a fast two channel gated charge to amplitude converter (QAC) which has been designed with the 1.2 {mu}m BiCMOS technology from AMS (Austria Mikro Systeme). It can integrate fast negative impulse currents up to 100 mA. Associated with an audio 18 bit low cost ADC, it can easily be used to make a 12 to 13 bit QDC. The problems of current to current conversion, pedestal and offset stability are discussed.

  19. Hardening of commercial CMOS PROMs with polysilicon fusible links

    NASA Technical Reports Server (NTRS)

    Newman, W. H.; Rauchfuss, J. E.

    1985-01-01

    The method by which a commercial 4K CMOS PROM with polysilicon fuses was hardened and the feasibility of applying this method to a 16K PROM are presented. A description of the process and the necessary minor modifications to the original layout are given. The PROM circuit and discrete device characteristics over radiation to 1000K rad-Si are summarized. The dose rate sensitivity of the 4K PROMs is also presented.

  20. Attenuation of single event induced pulses in CMOS combinational logic

    SciTech Connect

    Baze, M.P.; Buchner, S.P.

    1997-12-01

    Results are presented of a study of SEU generated transient pulse attenuation in combinational logic structures built using common digital CMOS design practices. SPICE circuit analysis, heavy ion tests, and pulsed, focused laser simulations were used to examine the response characteristics of transient pulse behavior in long logic strings. Results show that while there is an observable effect, it cannot be generally assumed that attenuation will significantly reduce observed circuit bit error rates.

  1. Linear dynamic range enhancement in a CMOS imager

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor)

    2008-01-01

    A CMOS imager with increased linear dynamic range but without degradation in noise, responsivity, linearity, fixed-pattern noise, or photometric calibration comprises a linear calibrated dual gain pixel in which the gain is reduced after a pre-defined threshold level by switching in an additional capacitance. The pixel may include a novel on-pixel latch circuit that is used to switch in the additional capacitance.

  2. CMOS integration of inkjet-printed graphene for humidity sensing.

    PubMed

    Santra, S; Hu, G; Howe, R C T; De Luca, A; Ali, S Z; Udrea, F; Gardner, J W; Ray, S K; Guha, P K; Hasan, T

    2015-01-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things. PMID:26616216

  3. CMOS integration of inkjet-printed graphene for humidity sensing

    PubMed Central

    Santra, S.; Hu, G.; Howe, R. C. T.; De Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-01-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10–80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things. PMID:26616216

  4. Cryogenic CMOS circuits for single charge digital readout.

    SciTech Connect

    Gurrieri, Thomas M.; Longoria, Erin Michelle; Eng, Kevin; Carroll, Malcolm S.; Hamlet, Jason R.; Young, Ralph Watson

    2010-03-01

    The readout of a solid state qubit often relies on single charge sensitive electrometry. However the combination of fast and accurate measurements is non trivial due to large RC time constants due to the electrometers resistance and shunt capacitance from wires between the cold stage and room temperature. Currently fast sensitive measurements are accomplished through rf reflectrometry. I will present an alternative single charge readout technique based on cryogenic CMOS circuits in hopes to improve speed, signal-to-noise, power consumption and simplicity in implementation. The readout circuit is based on a current comparator where changes in current from an electrometer will trigger a digital output. These circuits were fabricated using Sandia's 0.35 {micro}m CMOS foundry process. Initial measurements of comparators with an addition a current amplifier have displayed current sensitivities of < 1nA at 4.2K, switching speeds up to {approx}120ns, while consuming {approx}10 {micro}W. I will also discuss an investigation of noise characterization of our CMOS process in hopes to obtain a better understanding of the ultimate limit in signal to noise performance.

  5. Cryogenic CMOS circuits for single charge digital readout

    NASA Astrophysics Data System (ADS)

    Eng, Kevin; Gurrieri, T. M.; Hamlet, J.; Carroll, M. S.

    2010-03-01

    The readout of a solid state qubit often relies on single charge sensitive electrometry. However the combination of fast and accurate measurements is non trivial due to large RC time constants due to the electrometers resistance and shunt capacitance from wires between the cold stage and room temperature. Currently fast sensitive measurements are accomplished through rf reflectrometry. I will present an alternative single charge readout technique based on cryogenic CMOS circuits in hopes to improve speed, signal-to-noise, power consumption and simplicity in implementation. The readout circuit is based on a current comparator where changes in current from an electrometer will trigger a digital output. These circuits were fabricated using Sandia's 0.35μm CMOS foundry process. Initial measurements of comparators with an addition a current amplifier have displayed current sensitivities of < 1nA at 4.2K, switching speeds up to ˜120ns, while consuming ˜10μW. I will also discuss an investigation of noise characterization of our CMOS process in hopes to obtain a better understanding of the ultimate limit in signal to noise performance.

  6. First result on biased CMOS MAPs-on-diamond devices

    NASA Astrophysics Data System (ADS)

    Kanxheri, K.; Citroni, M.; Fanetti, S.; Lagomarsino, S.; Morozzi, A.; Parrini, G.; Passeri, D.; Sciortino, S.; Servoli, L.

    2015-10-01

    Recently a new type of device, the MAPS-on-diamond, obtained bonding a thinned to 25 μm CMOS Monolithic Active Pixel Sensor to a standard 500 μm pCVD diamond substrate, has been proposed and fabricated, allowing a highly segmented readout (10×10 μm pixel size) of the signal produced in the diamond substrate. The bonding between the two materials has been obtained using a new laser technique to deliver the needed energy at the interface. A biasing scheme has been adopted to polarize the diamond substrate to allow the charge transport inside the diamond without disrupting the functionalities of the CMOS Monolithic Active Pixel Sensor. The main concept of this class of devices is the capability of the charges generated in the diamond by ionizing radiation to cross the silicon-diamond interface and to be collected by the MAPS photodiodes. In this work we demonstrate that such passage occurs and measure its overall efficiency. This study has been carried out first calibrating the CMOS MAPS with monochromatic X-rays, and then testing the device with charged particles (electrons) either with and without biasing the diamond substrate, to compare the amount of signal collected.

  7. CMOS-liquid-crystal-based image transceiver device

    NASA Astrophysics Data System (ADS)

    Efron, Uzi; Davidov, Isak; Sinelnikov, Vladimir; Levin, Ilya

    2001-05-01

    A CMOS-Liquid Crystal-Based Image Transceiver Device (ITD) is under development at the Holon Institute of Technology. The device combines both functions of imaginary and display in a single array structure. This unique structure allows the combination of see-through, aiming, imaging and the displaying of a superposed image to be combined in a single, compact, head mounted display. The CMOS-based pixel elements are designed to provide image sensor part of the pixel is based on an n-well photodiode and a three-transistors readout circuit. The imaging function is based on a back- illuminated sensor configuration. In order to provide a high imager fill-factor, two pixel configuration are proposed: 1) A p++/p-/p-well silicon structure using twin- well CMOS process; 2) an n-well processed silicon structure with a micro-lens array. The display portion of the IT device is to be fabricate don a silicon-based reflective, active matrix driver, using nematic liquid crystal material. The reflective display pixel electrode is driven by an n-MOS transistor, formed in the corresponding pixel region on the silicon substrate. The timing, sequencing and control of the IT device array are designed in a pipeline array processing scheme. A preliminary prototype system and device design have been performed and the first test device is currently being tested. Details of the device design as well as its smart goggle applications are presented.

  8. CMOS/LCOS-based image transceiver device: II

    NASA Astrophysics Data System (ADS)

    Efron, Uzi; Davidov, Isak; Sinelnikov, Vladimir; Friesem, Asher A.

    2001-11-01

    A CMOS-liquid crystal-based image transceiver device (ITD) is under development at the Holon Institute of Technology. The device combines both functions of imaging and display in a single array configuration. This unique structure allows the combination of see-through, aiming, imaging and the displaying of a superposed image to be combined in a single, compact, head mounted display. The CMOS-based pixel elements are designed to provide efficient imaging in the visible range as well as driver capabilities for the overlying liquid crystal modulator. The image sensor part of the pixel is based on an n-well photodiode and a three-transistor readout circuit. The imaging function is based on a back- illuminated sensor configuration. In order to provide a high imager fill-factor, two pixel configurations are proposed: 1) A p++/p-/p-well silicon structure using twin- well CMOS process; 2) An n-well processed silicon structure with a micro-lens array. The display portion of the IT device is to be fabricated on a silicon-based reflective, active matrix driver, using nematic liquid crystal material, in LCOS technology. The timing, sequencing and control of the IT device array are designed in a pipeline array processing scheme. A preliminary prototype system and device design have been performed and the first test device is currently undergoing testing. Details of the device design as well as its Smart Goggle applications are presented.

  9. CMOS integration of inkjet-printed graphene for humidity sensing

    NASA Astrophysics Data System (ADS)

    Santra, S.; Hu, G.; Howe, R. C. T.; de Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-11-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things.

  10. Aluminum nitride on titanium for CMOS compatible piezoelectric transducers

    PubMed Central

    Doll, Joseph C; Petzold, Bryan C; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L

    2010-01-01

    Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d33f, d31 and d33 of up to 2.9, −1.9 and 6.5 pm V−1, respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals. PMID:20333316

  11. Fully depleted, thick, monolithic CMOS pixels with high quantum efficiency

    NASA Astrophysics Data System (ADS)

    Clarke, A.; Stefanov, K.; Johnston, N.; Holland, A.

    2015-04-01

    The Centre for Electronic Imaging (CEI) has an active programme of evaluating and designing Complementary Metal-Oxide Semiconductor (CMOS) image sensors with high quantum efficiency, for applications in near-infrared and X-ray photon detection. This paper describes the performance characterisation of CMOS devices made on a high resistivity 50 μ m thick p-type substrate with a particular focus on determining the depletion depth and the quantum efficiency. The test devices contain 8 × 8 pixel arrays using CCD-style charge collection, which are manufactured in a low voltage CMOS process by ESPROS Photonics Corporation (EPC). Measurements include determining under which operating conditions the devices become fully depleted. By projecting a spot using a microscope optic and a LED and biasing the devices over a range of voltages, the depletion depth will change, causing the amount of charge collected in the projected spot to change. We determine if the device is fully depleted by measuring the signal collected from the projected spot. The analysis of spot size and shape is still under development.

  12. Development of CMOS Imager Block for Capsule Endoscope

    NASA Astrophysics Data System (ADS)

    Shafie, S.; Fodzi, F. A. M.; Tung, L. Q.; Lioe, D. X.; Halin, I. A.; Hasan, W. Z. W.; Jaafar, H.

    2014-04-01

    This paper presents the development of imager block to be associated in a capsule endoscopy system. Since the capsule endoscope is used to diagnose gastrointestinal diseases, the imager block must be in small size which is comfortable for the patients to swallow. In this project, a small size 1.5V button battery is used as the power supply while the voltage supply requirements for other components such as microcontroller and CMOS image sensor are higher. Therefore, a voltage booster circuit is proposed to boost up the voltage supply from 1.5V to 3.3V. A low power microcontroller is used to generate control pulses for the CMOS image sensor and to convert the 8-bits parallel data output to serial data to be transmitted to the display panel. The results show that the voltage booster circuit was able to boost the voltage supply from 1.5V to 3.3V. The microcontroller precisely controls the CMOS image sensor to produce parallel data which is then serialized again by the microcontroller. The serial data is then successfully translated to 2fps image and displayed on computer.

  13. Neuronal cell biocompatibility and adhesion to modified CMOS electrodes.

    PubMed

    Graham, Anthony H D; Bowen, Chris R; Taylor, John; Robbins, Jon

    2009-10-01

    The use of CMOS (Complementary Metal Oxide Semiconductor) integrated circuits to create electrodes for biosensors, implants and drug-discovery has several potential advantages over passive multi-electrode arrays (MEAs). However, unmodified aluminium CMOS electrodes may corrode in a physiological environment. We have investigated a low-cost electrode design based on the modification of CMOS metallisation to produce a nanoporous alumina electrode as an interface to mammalian neuronal cells and corrosion inhibitor. Using NG108-15 mouse neuroblastoma x rat glioma hybrid cells, results show that porous alumina is biocompatible and that the inter-pore distance (pore pitch) of the alumina has no effect on cell vitality. To establish whether porous alumina and a cell membrane can produce a tight junction required for good electrical coupling between electrode and cell, we devised a novel cell detachment centrifugation assay to assess the long-term adhesion of cells. Results show that porous alumina substrates produced with a large pore pitch of 206 nm present a significantly improved surface compared to the unmodified aluminium control and that small pore-pitches of 17 nm and 69 nm present a less favourable surface for cell adhesion. PMID:19459049

  14. CMOS-compatible graphene photodetector covering all optical communication bands

    NASA Astrophysics Data System (ADS)

    Pospischil, Andreas; Humer, Markus; Furchi, Marco M.; Bachmann, Dominic; Guider, Romain; Fromherz, Thomas; Mueller, Thomas

    2013-11-01

    Optical interconnects are becoming attractive alternatives to electrical wiring in intra- and interchip communication links. Particularly, the integration with silicon complementary metal-oxide semiconductor (CMOS) technology has received considerable interest because of the ability of cost-effective integration of electronics and optics on a single chip. Although silicon enables the realization of optical waveguides and passive components, the integration of another, optically absorbing, material is required for photodetection. Traditionally, germanium or compound semiconductors are used for this purpose; however, their integration with silicon technology faces major challenges. Recently, graphene emerged as a viable alternative for optoelectronic applications, including photodetection. Here, we demonstrate an ultra-wideband CMOS-compatible photodetector based on graphene. We achieved a multigigahertz operation over all fibre-optic telecommunication bands beyond the wavelength range of strained germanium photodetectors, the responsivity of which is limited by their bandgap. Our work complements the recent demonstration of a CMOS-integrated graphene electro-optical modulator, and paves the way for carbon-based optical interconnects.

  15. A CMOS TDI image sensor for Earth observation

    NASA Astrophysics Data System (ADS)

    Rushton, Joseph E.; Stefanov, Konstantin D.; Holland, Andrew D.; Endicott, James; Mayer, Frederic; Barbier, Frederic

    2015-09-01

    Time Delay and Integration (TDI) is used to increase the Signal to Noise Ratio (SNR) in image sensors when imaging fast moving objects. One important TDI application is in Earth observation from space. In order to operate in the space radiation environment, the effect that radiation damage has on the performance of the image sensors must be understood. This work looks at prototype TDI sensor pixel designs, produced by e2v technologies. The sensor is a CCD-like charge transfer device, allowing in-pixel charge summation, produced on a CMOS process. The use of a CMOS process allows potential advantages such as lower power consumption, smaller pixels, higher line rate and extra on-chip functionality which can simplify system design. CMOS also allows a dedicated output amplifier per column allowing fewer charge transfers and helping to facilitate higher line rates than CCDs. In this work the effect on the pixels of radiation damage from high energy protons, at doses relevant to a low Earth orbit mission, is presented. This includes the resulting changes in Charge Transfer inefficiency (CTI) and dark signal.

  16. Polycrystalline Mercuric Iodide Films on CMOS Readout Arrays

    PubMed Central

    Hartsough, Neal E.; Iwanczyk, Jan S.; Nygard, Einar; Malakhov, Nail; Barber, William C.; Gandhi, Thulasidharan

    2009-01-01

    We have created high-resolution x-ray imaging devices using polycrystalline mercuric iodide (HgI2) films grown directly onto CMOS readout chips using a thermal vapor transport process. Images from prototype 400×400 pixel HgI2-coated CMOS readout chips are presented, where the pixel grid is 30 μm × 30 μm. The devices exhibited sensitivity of 6.2 μC/Rcm2 with corresponding dark current of ∼2.7 nA/cm2, and a 80 μm FWHM planar image response to a 50 μm slit aperture. X-ray CT images demonstrate a point spread function sufficient to obtain a 50 μm spatial resolution in reconstructed CT images at a substantially reduced dose compared to phosphor-coated readouts. The use of CMOS technology allows for small pixels (30 μm), fast readout speeds (8 fps for a 3200×3200 pixel array), and future design flexibility due to the use of well-developed fabrication processes. PMID:20161098

  17. Aluminum nitride on titanium for CMOS compatible piezoelectric transducers

    NASA Astrophysics Data System (ADS)

    Doll, Joseph C.; Petzold, Bryan C.; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L.

    2010-02-01

    Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d33f, d31 and d33 of up to 2.9, -1.9 and 6.5 pm V-1, respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals.

  18. Single photon detection and localization accuracy with an ebCMOS camera

    NASA Astrophysics Data System (ADS)

    Cajgfinger, T.; Dominjon, A.; Barbier, R.

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 μm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  19. Self-Calibrated Humidity Sensor in CMOS without Post-Processing

    PubMed Central

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2012-01-01

    A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry. PMID:22368466

  20. CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.

    SciTech Connect

    Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

    2008-08-01

    Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

  1. Top-down fabrication of fully CMOS-compatible silicon nanowire arrays and their integration into CMOS Inverters on plastic.

    PubMed

    Lee, Myeongwon; Jeon, Youngin; Moon, Taeho; Kim, Sangsig

    2011-04-26

    A route to the top-down fabrication of highly ordered and aligned silicon nanowire (SiNW) arrays with degenerately doped source/drain regions from a bulk Si wafer is presented. In this approach, freestanding n- and p-SiNWs with an inverted triangular cross section are obtained using conventional photolithography, crystal orientation dependent wet etching, size reduction oxidation, and ion implantation doping. Based on these n- and p-SiNWs transferred onto a plastic substrate, simple SiNW-based complementary metal-oxide-semiconductor (CMOS) inverters are constructed for the possible applications of these SiNW arrays in integrated circuits on plastic. The static voltage transfer characteristic of the SiNW-based CMOS inverter exhibits a voltage gain of ∼9 V/V and a transition of 0.32 V at an operating voltage of 1.5 V with a full output voltage swing between 0 V and V(DD), and its mechnical bendability indicates good fatigue properties for potential applications of flexible electronics. This novel top-down approach is fully compatible with the current state-of-the-art Si-based CMOS technologies and, therefore, offers greater flexibility in device design for both high-performance and low-power functionality. PMID:21355599

  2. Manipulation of magnetic and magneto-transport properties of amorphous CoO1-v films

    NASA Astrophysics Data System (ADS)

    Cao, Yan-ling; Zhang, Kun; Li, Huan-huan; Tian, Yu-feng; Yan, Shi-shen; Xiao, Shu-qin; Chen, Yan-xue; Kang, Shi-shou; Liu, Guo-lei; Mei, Liang-mo

    2015-04-01

    The magnetic and magneto-transport properties of amorphous CoO1-v films have been systematically studied and manipulated by changing the concentration of oxygen vacancies. A giant exchange bias field HE≈4380 Oe and a large coercivity HC≈8500 Oe are observed at 5 K for the composite films. And, a metal to insulator transition has been demonstrated in CoO1-v films by decreasing the concentration of oxygen vacancies. Moreover, a remarkable decrease of the exchange bias and a slight increase of the saturation magnetization can be obtained by modifying the microstructures through post-thermal annealing.

  3. Rationally Targeted Mutations at the V1V2 Domain of the HIV-1 Envelope to Augment Virus Neutralization by Anti-V1V2 Monoclonal Antibodies.

    PubMed

    Shen, Guomiao; Upadhyay, Chitra; Zhang, Jing; Pan, Ruimin; Zolla-Pazner, Susan; Kong, Xiang-Peng; Hioe, Catarina E

    2015-01-01

    HIV-1 envelope glycoproteins (Env) are the only viral antigens present on the virus surface and serve as the key targets for virus-neutralizing antibodies. However, HIV-1 deploys multiple strategies to shield the vulnerable sites on its Env from neutralizing antibodies. The V1V2 domain located at the apex of the HIV-1 Env spike is known to encompass highly variable loops, but V1V2 also contains immunogenic conserved elements recognized by cross-reactive antibodies. This study evaluates human monoclonal antibodies (mAbs) against V2 epitopes which overlap with the conserved integrin α4β7-binding LDV/I motif, designated as the V2i (integrin) epitopes. We postulate that the V2i Abs have weak or no neutralizing activities because the V2i epitopes are often occluded from antibody recognition. To gain insights into the mechanisms of the V2i occlusion, we evaluated three elements at the distal end of the V1V2 domain shown in the structure of V2i epitope complexed with mAb 830A to be important for antibody recognition of the V2i epitope. Amino-acid substitutions at position 179 that restore the LDV/I motif had minimal effects on virus sensitivity to neutralization by most V2i mAbs. However, a charge change at position 153 in the V1 region significantly increased sensitivity of subtype C virus ZM109 to most V2i mAbs. Separately, a disulfide bond introduced to stabilize the hypervariable region of V2 loop also enhanced virus neutralization by some V2i mAbs, but the effects varied depending on the virus. These data demonstrate that multiple elements within the V1V2 domain act independently and in a virus-dependent fashion to govern the antibody recognition and accessibility of V2i epitopes, suggesting the need for multi-pronged strategies to counter the escape and the shielding mechanisms obstructing the V2i Abs from neutralizing HIV-1. PMID:26491873

  4. CATS-ISS_L1B_N-M7.1-V2-04

    Atmospheric Science Data Center

    2016-04-27

    CATS-ISS_L1B_N-M7.1-V2-04 The Cloud-Aerosol Transport System (CATS) is a three wavelength, polarization-sensitive lidar that provides ... in the Earth's atmosphere. Project Title:  CATS Discipline:  Clouds Aerosols Version:  ...

  5. Design and experimental verification of low-voltage two-dimensional CMOS electrophoresis platform with 32 × 32 sample/hold cell array

    NASA Astrophysics Data System (ADS)

    Yamaji, Yuuki; Niitsu, Kiichi; Nakazato, Kazuo

    2016-03-01

    Electrophoresis is widely used in biomedical applications. However, conventional (centimeter-order) electrophoresis requires a high-voltage power supply, which is not suitable for point-of-care testing (POCT). Electrophoresis is driven by electric fields, and miniaturization (from the centimeter order to the micrometer order) is effective for low-voltage operation. A CMOS platform is a cost-competitive and promising candidate for miniaturization and enables the integration of biomolecule manipulation by electrophoresis and its electrochemical sensing. These features will contribute to the development of a biochemical analyzer called the micro-total analysis system (µ-TAS). To realize a truly portable electrophoresis system, we present the design and experimental verification of a low-voltage (<1 V), two-dimensional CMOS electrophoresis platform with 32 × 32 sample/hold cell array. Experimental results showed successful constant voltage outputs to each electrode. By miniaturizing the electrode structure to a 60 µm pitch, we achieved sufficient electric field strength even at low voltages.

  6. Robust design of a 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm CMOS

    NASA Astrophysics Data System (ADS)

    Long, Cheng; Yu, Zhu; Kai, Zhu; Chixiao, Chen; Junyan, Ren

    2013-10-01

    A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design. The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains. The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB. The measured SFDR at 1.7 MHz output signal is 58.91 dB, 58.53 dB and 56.98 dB for R/G/B channels, respectively. The DAC has good static and dynamic performance despite the single-ended output. The average rising time and falling time of three channels are 0.674 ns and 0.807 ns. The analog/digital power supply is 3.3 V/1.1 V. This triple-channel DAC occupies 0.5656 mm2.

  7. Comparative Immunogenicity of Evolved V1V2-Deleted HIV-1 Envelope Glycoprotein Trimers

    PubMed Central

    Tong, Tommy; van Montfort, Thijs; Eggink, Dirk; Montefiori, David; Olson, William C.; Moore, John P.; Binley, James M.; Berkhout, Ben; Sanders, Rogier W.

    2013-01-01

    Despite almost 30 years of research, no effective vaccine has yet been developed against HIV-1. Probably such a vaccine would need to induce both an effective T cell and antibody response. Any vaccine component focused on inducing humoral immunity requires the HIV-1 envelope (Env) glycoprotein complex as it is the only viral protein exposed on the virion surface. HIV-1 has evolved several mechanisms to evade broadly reactive neutralizing antibodies. One such a mechanism involves variable loop domains, which are highly flexible structures that shield the underlying conserved epitopes. We hypothesized that removal of such loops would increase the exposure and immunogenicity of these conserved regions. Env variable loop deletion however often leads to protein misfolding and aggregation because hydrophobic patches becoming solvent accessible. We have therefore previously used virus evolution to acquire functional Env proteins lacking the V1V2 loop. We then expressed them in soluble (uncleaved) gp140 forms. Three mutants were found to perform optimally in terms of protein expression, stability, trimerization and folding. In this study, we characterized the immune responses to these antigens in rabbits. The V1V2 deletion mutant ΔV1V2.9.VK induced a prominent response directed to epitopes that are not fully available on the other Env proteins tested but that effectively bound and neutralized the ΔV1V2 Env virus. This Env variant also induced more efficient neutralization of the tier 1 virus SF162. The immune refocusing effect was lost after booster immunization with a full-length gp140 protein with intact V1V2 loops. Collectively, this result suggests that deletion of variable domains could alter the specificity of the humoral immune response, but did not result in broad neutralization of neutralization-resistant virus isolates. PMID:23840716

  8. Swap intensified WDR CMOS module for I2/LWIR fusion

    NASA Astrophysics Data System (ADS)

    Ni, Yang; Noguier, Vincent

    2015-05-01

    The combination of high resolution visible-near-infrared low light sensor and moderate resolution uncooled thermal sensor provides an efficient way for multi-task night vision. Tremendous progress has been made on uncooled thermal sensors (a-Si, VOx, etc.). It's possible to make a miniature uncooled thermal camera module in a tiny 1cm3 cube with <1W power consumption. For silicon based solid-state low light CCD/CMOS sensors have observed also a constant progress in terms of readout noise, dark current, resolution and frame rate. In contrast to thermal sensing which is intrinsic day&night operational, the silicon based solid-state sensors are not yet capable to do the night vision performance required by defense and critical surveillance applications. Readout noise, dark current are 2 major obstacles. The low dynamic range at high sensitivity mode of silicon sensors is also an important limiting factor, which leads to recognition failure due to local or global saturations & blooming. In this context, the image intensifier based solution is still attractive for the following reasons: 1) high gain and ultra-low dark current; 2) wide dynamic range and 3) ultra-low power consumption. With high electron gain and ultra low dark current of image intensifier, the only requirement on the silicon image pickup device are resolution, dynamic range and power consumption. In this paper, we present a SWAP intensified Wide Dynamic Range CMOS module for night vision applications, especially for I2/LWIR fusion. This module is based on a dedicated CMOS image sensor using solar-cell mode photodiode logarithmic pixel design which covers a huge dynamic range (> 140dB) without saturation and blooming. The ultra-wide dynamic range image from this new generation logarithmic sensor can be used directly without any image processing and provide an instant light accommodation. The complete module is slightly bigger than a simple ANVIS format I2 tube with <500mW power consumption.

  9. NV-CMOS HD camera for day/night imaging

    NASA Astrophysics Data System (ADS)

    Vogelsong, T.; Tower, J.; Sudol, Thomas; Senko, T.; Chodelka, D.

    2014-06-01

    SRI International (SRI) has developed a new multi-purpose day/night video camera with low-light imaging performance comparable to an image intensifier, while offering the size, weight, ruggedness, and cost advantages enabled by the use of SRI's NV-CMOS HD digital image sensor chip. The digital video output is ideal for image enhancement, sharing with others through networking, video capture for data analysis, or fusion with thermal cameras. The camera provides Camera Link output with HD/WUXGA resolution of 1920 x 1200 pixels operating at 60 Hz. Windowing to smaller sizes enables operation at higher frame rates. High sensitivity is achieved through use of backside illumination, providing high Quantum Efficiency (QE) across the visible and near infrared (NIR) bands (peak QE <90%), as well as projected low noise (<2h+) readout. Power consumption is minimized in the camera, which operates from a single 5V supply. The NVCMOS HD camera provides a substantial reduction in size, weight, and power (SWaP) , ideal for SWaP-constrained day/night imaging platforms such as UAVs, ground vehicles, fixed mount surveillance, and may be reconfigured for mobile soldier operations such as night vision goggles and weapon sights. In addition the camera with the NV-CMOS HD imager is suitable for high performance digital cinematography/broadcast systems, biofluorescence/microscopy imaging, day/night security and surveillance, and other high-end applications which require HD video imaging with high sensitivity and wide dynamic range. The camera comes with an array of lens mounts including C-mount and F-mount. The latest test data from the NV-CMOS HD camera will be presented.

  10. A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager

    PubMed Central

    Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

    2012-01-01

    Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm2. Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624