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Sample records for 130-nm commercial cmos

  1. Optimal design of phase change random access memory based on 130nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Cai, Daolin; Chen, Houpeng; Wang, Qian; Hong, Xiao; Chen, Yifeng; Xu, Linhai; Li, Xi; Wang, Zhaomin; Zhang, Yiyun; Song, Zhitang

    An 8Mb phase change random access memory (PCRAM) has been developed by a 130nm 4-ML standard CMOS technology based on the Resistor-on-Via-stacked-Plug (RVP) storage cell structure. This phase change resistor is formed after CMOS logic fabrication. PCRAM can be embedded without changing any logic device and process. The memory cell selector is implemented by a standard 1.2V NMOS device. Aimed at the resistance distributions, lowering the operation current and improving the bit yield, some methods are used to optimize the design of the chip.

  2. A 12 GHz low-jitter LC-VCO PLL in 130 nm CMOS

    NASA Astrophysics Data System (ADS)

    You, Y.; Chen, J.; Feng, Y.; Tang, Y.; Huang, D.; Rui, W.; Gong, D.; Liu, T.; Ye, J.

    2015-03-01

    We present a wideband low-jitter LC-VCO phase-locked loop in 130 nm CMOS technology for high speed serial link applications. The PLL covers a 5.6 GHz to 13.4 GHz frequency range by using two LC-VCO cores with an RMS jitter of 370 fs. The single event effects testing is performed with a neutron beam at Los Alamos National Laboratory and no frequency disturbance is found over the test period. The PLL consumes 50.88 mW of power under a 1.2 V power supply.

  3. Development of a low power Delay-Locked Loop in two 130 nm CMOS technologies

    NASA Astrophysics Data System (ADS)

    Firlej, M.; Fiutowski, T.; Idzik, M.; Moron, J.; Swientek, K.

    2016-02-01

    The design and measurement results of two low power DLL prototypes for applications in particle physics readout systems are presented. The DLLs were fabricated in two different 130 nm CMOS technologies, called process A and process B, giving the opportunity to compare these two CMOS processes. Both circuits generate 64 uniform clock phases and operate at similar frequency range, from 20 MHz up to 60 MHz (10 MHz - 90 MHz in process B). The period jitter of both DLLs is in the range 2.5 ps - 12.1 ps (RMS) and depends on the selected output phase. The complete DLL functionality was experimentally verified, confirming a very low and frequency scalable power consumption of around 0.7 mW at typical 40 MHz input. The DLL prototype, designed in process A, occupies 680 μm × 210 μm, while the same circuit designed in process B occupies 430 μm × 190 μm.

  4. Development of scalable frequency and power Phase-Locked Loop in 130 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Firlej, M.; Fiutowski, T.; Idzik, M.; Moroń, J.; Świentek, K.

    2014-02-01

    The design and measurements results of a prototype very low power Phase-Locked Loop (PLL) ASIC for applications in readout systems of particle physics detectors are presented. The PLL was fabricated in 130 nm CMOS technology. It was designed and simulated for frequency range 10 MHz-3.5 GHz. Four division factors i.e. 6, 8, 10 and 16 were implemented in the PLL feedback loop. The main PLL block-voltage controlled oscillator (VCO) should work in 16 frequency ranges/modes, switched either manually or automatically. Preliminary measurements done in frequency range 20 MHz-1.6 GHz showed that the ASIC is functional and generates proper clock signal. The automatic VCO mode switching, one of the main design goals, was positively verified. Power consumption of around 0.6 mW was measured at 1 GHz for a division factor equal to 10.

  5. Development of front-end electronics for LumiCal detector in CMOS 130 nm technology

    NASA Astrophysics Data System (ADS)

    Firlej, M.; Fiutowski, T.; Idzik, M.; Moroń, J.; Świentek, K.; Terlecki, P.

    2015-01-01

    The design and the preliminary measurements results of a multichannel, variable gain front-end electronics for luminosity detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier with pole-zero cancellation circuit and a CR-RC shaper with 50 ns peaking time. The measurements results confirm full functionality of the prototype and compliance with the requirements imposed by the detector specification. The power consumption of the front-end is in the range 0.6-1.5 mW per channel and the noise ENC around 900 e - at 10 pF input capacitance.

  6. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology

    PubMed Central

    Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

    2015-01-01

    This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode’s current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm2 of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA. PMID:26205275

  7. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology.

    PubMed

    Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

    2015-01-01

    This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode's current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm(2) of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA. PMID:26205275

  8. A 200 mV low leakage current subthreshold SRAM bitcell in a 130 nm CMOS process

    NASA Astrophysics Data System (ADS)

    Na, Bai; Baitao, Lü

    2012-06-01

    A low leakage current subthreshold SRAM in 130 nm CMOS technology is proposed for ultra low voltage (200 mV) applications. Almost all of the previous subthreshold works ignore the leakage current in both active and standby modes. To minimize leakage, a self-adaptive leakage cut off scheme is adopted in the proposed design without any extra dynamic energy dissipation or performance penalty. Combined with buffering circuit and reconfigurable operation, the proposed design ensures both read and standby stability without deteriorating writability in the subthreshold region. Compared to the referenced subthreshold SRAM bitcell, the proposed bitcell shows: (1) a better critical state noise margin, and (2) smaller leakage current in both active and standby modes. Measurement results show that the proposed SRAM functions well at a 200 mV supply voltage with 0.13 μW power consumption at 138 kHz frequency.

  9. Cryogenic Lifetime Studies of 130 nm and 65 nm CMOS Technologies for High-Energy Physics Experiments

    SciTech Connect

    Hoff, James R.; Deptuch, G. W.; Wu, Guoying; Gui, Ping

    2015-03-09

    The Long Baseline Neutrino Facility intends to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. Research is under way to place the electronics inside the cryostat. For reasons of efficiency and economics, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This, then, requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130 nm and 65 nm nMOS transistors operating at cryogenic temperatures are investigated. Our results show that both technologies achieve the lifetimes required by the experiment. Minimal design changes are necessary in the case of the 130 nm process and no changes whatsoever are necessary for the 65 nm process.

  10. A wide range ultra-low power Phase-Locked Loop with automatic frequency setting in 130 nm CMOS technology for data serialisation

    NASA Astrophysics Data System (ADS)

    Firlej, M.; Fiutowski, T.; Idzik, M.; Moroń, J.; Świentek, K.

    2015-12-01

    The design and measurements results of a wide frequency range ultra-low power Phase-Locked Loop (PLL) for applications in readout systems of particle physics detectors are presented. The PLL was fabricated in a 130 nm CMOS technology. To allow the implementation of different data serialisation schemes multiple division factors (6, 8, 10, 16) were implemented in the PLL feedback loop. The main PLL block—VCO works in 16 frequency ranges/modes, switched either manually or automatically. A dedicated automatic frequency mode switching circuit was developed to allow simple frequency tuning. Although the PLL was designed and simulated for a frequency range of 30 MHz–3 GHz, due to the SLVS interface limits, the measurements were done only up to 1.3 GHz. The full PLL functionality was experimentally verified, confirming a very low and frequency scalable power consumption (0.7 mW at 1 GHz).

  11. A saw-less direct conversion long term evolution receiver with 25% duty-cycle LO in 130 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Siyuan, He; Changhong, Zhang; Liang, Tao; Weifeng, Zhang; Longyue, Zeng; Wei, Lü; Haijun, Wu

    2013-03-01

    A CMOS long-term evolution (LTE) direct convert receiver that eliminates the interstage SAW filter is presented. The receiver consists of a low noise variable gain transconductance amplifier (TCA), a quadrature passive current commutating mixer with a 25% duty-cycle LO, a trans-impedance amplifier (TIA), a 7th-order Chebyshev filter and programmable gain amplifiers (PGAs). A wide dynamic gain range is allocated in the RF and analog parts. A current commutating passive mixer with a 25% duty-cycle LO improves gain, noise, and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference. Fabricated in a 0.13 μm CMOS process, the receiver chain achieves a 107 dB maximum voltage gain, 2.7 dB DSB NF (from PAD port), -11 dBm IIP3, and > +65 dBm IIP2 after calibration, 96 dB dynamic control range with 1 dB steps, less than 2% error vector magnitude (EVM) from 2.3 to 2.7 GHz. The total receiver (total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.

  12. A 12-bit 60-MS/s 36-mW SHA-less opamp-sharing pipeline ADC in 130 nm CMOS

    NASA Astrophysics Data System (ADS)

    Wen, X.; Chen, J.; You, Y.; Feng, Y.; Tang, Y.; Zuo, Z.; Vosooghi, B.; Fan, Q.; Xiao, L.; Gong, D.; Liu, T.; Ye, J.

    2016-01-01

    This paper presents a 12-bit 60-MS/s SHA-less opamp-sharing pipeline analog-to-digital converter (ADC) implemented in a 0.13-μ m CMOS technology. A switch-embedded dual-input current-reused operational transconductance amplifier (OTA) with an overlapping two-phase clocking scheme is proposed to achieve low power consumption and eliminate the non-resetting and memory effects observed in conventional opamp-sharing techniques. To further reduce the power consumption, the ADC also incorporates a SHA-less multi-bit structure. The ADC achieves a signal-to-noise and distortion ratio of 64.9 dB and a spurious-free dynamic range of 77.1 dB at 60 MS/s. It occupies 2.3 mm 2 of area and consumes 36 mW of power under a 1.2-V supply.

  13. Tests of commercial colour CMOS cameras for astronomical applications

    NASA Astrophysics Data System (ADS)

    Pokhvala, S. M.; Reshetnyk, V. M.; Zhilyaev, B. E.

    2013-12-01

    We present some results of testing commercial colour CMOS cameras for astronomical applications. Colour CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in colour CMOS sensors is close to the astronomical Johnson BVR system. The basic camera characteristics: read noise (e^{-}/pix), thermal noise (e^{-}/pix/sec) and electronic gain (e^{-}/ADU) for the commercial digital camera Canon 5D MarkIII are presented. We give the same characteristics for the scientific high performance cooled CCD camera system ALTA E47. Comparing results for tests of Canon 5D MarkIII and CCD ALTA E47 show that present-day commercial colour CMOS cameras can seriously compete with the scientific CCD cameras in deep astronomical imaging.

  14. Hardening of commercial CMOS PROMs with polysilicon fusible links

    NASA Technical Reports Server (NTRS)

    Newman, W. H.; Rauchfuss, J. E.

    1985-01-01

    The method by which a commercial 4K CMOS PROM with polysilicon fuses was hardened and the feasibility of applying this method to a 16K PROM are presented. A description of the process and the necessary minor modifications to the original layout are given. The PROM circuit and discrete device characteristics over radiation to 1000K rad-Si are summarized. The dose rate sensitivity of the 4K PROMs is also presented.

  15. Overlay tool comparison for sub-130-nm technologies

    NASA Astrophysics Data System (ADS)

    Russo, Beth; Bishop, Michael; Benoit, David C.; Silver, Richard M.

    2002-07-01

    The Overlay Metrology Advisory Group (OMAG), which includes representatives from International SEMATECH Member Companies and the National Institute of Standards and Technology, has collaborated to create a unified specification for overlay measurement tools [1]. The methodology and results of an overlay benchmarking comparison of several tools are discussed in this paper. As device technologies shrink below the sub-130nm range, a critical need arises to develop more precise tools to measure overlay. Overlay metrology capability needs to be available for detecting and controlling total device overlay regardless of the source of error. The misregistration measurement uncertainty introduced by the overlay tool can be compared for several systems. A benchmarking study is currently underway and focuses on the existing technique of optical measurement of centerline offsets in different target designs. The critical parameters that the study analyzes include precision, accuracy, throughput, through focus measurements, and recipe portability. Imaging issues such as low contrast targets, across wafer thickness variation, CMP effects, and grainy metal targets can contribute greatly to overlay errors. Several process stacks were designed to incorporate some of these imaging issues and test the limitations of the overlay tools. The same set of wafers and test locations were measured at each supplier site and the results were analyzed. This paper focuses on the methodology used for overlay benchmarking and examples of the results generated with respect to the parameters tested.

  16. Feasibility studies of ArF lithography for sub-130-nm lithography

    NASA Astrophysics Data System (ADS)

    Lee, Seung-Hyuk; Yim, Donggyu; Ham, Young-Mog; Baik, Ki-Ho; Choi, Il-Hyun

    1999-07-01

    In this study, we evaluated the process margins of 193 nm lithography for sub-130 nm applications. We have investigated various cell structures and sizes for various illumination conditions such as the partial coherence factors, quadruple illuminations, and Optical Proximity Correction (OPC). We have also studied the Critical Dimension (CD) variation effects of topography with Bottom Anti-Reflective Coating (BARC) materials on various substrates such as silicon, nitride and aluminum. A 0.6 Numerical Aperture (NA) small field ArF stepper and a Hyundai-developed ArF single positive resist were used for this experiment. Internally-developed simulation program diffused aerial image model and Hyundai OPC simulation tool were also used to predict and effectively correct the optical proximity effect. The simulation result were compared with experimental results. Carefully optimizing the process conditions and optical settings, we obtained CD linearity of 190 nm, taking into account isolated-dense (ID) bias. With sub-130 nm VLSI cell pattern, we also verified the possibility of fabricating devices with sub-130 nm design rule by ArF lithography, with which we predicted some process issues such that ID bias of cell and peripheral patterns, CD bias of perpendicular axes in island patterns, contact hole patterns below 150 nm, pattern collapse, etc. Through this study, we verified that the 193 nm lithography could be applied for sub-130 nm technology.

  17. Packaging commercial CMOS chips for lab on a chip integration.

    PubMed

    Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

    2014-05-21

    Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems. PMID:24682025

  18. Performance improvement of ALTA4700 for 130nm and below mask productivity

    NASA Astrophysics Data System (ADS)

    Hsu, Jyh Wei; Lee, David; Tseng, Chen Rui; Hong, Eric; Wu, Chun Hung

    2007-10-01

    ALTA4700 DUV laser pattern generator employs chemical amplified resist to get better resolution. The capability of ALTA4700 for 130nm technology node mask production is obviously. Further improvement on ALTA4700 was performed to meet the state-of-the-art mask requirement. System optimization eliminates unusual critical dimension (CD) points and then reduces the range of uniformity. Appropriate post-exposure baking (PEB) temperature gets larger mask printing window and better CD linearity. ALTA4700 incorporate NTAR7 blank with particular dry etch recipe, the mask CD uniformity reduced from 25 to 15nm (range). Good Cr layer profile also obtains.

  19. Lifetime studies of 130nm nMOS transistors intended for long-duration, cryogenic high-energy physics experiments.

    SciTech Connect

    Hoff, J.R.; Arora, R.; Cressler, J.D.; Deptuch, G.W.; Gui, P.; Lourenco, N.E.; Wu, G.; Yarema, R.J.; /Fermilab

    2011-12-01

    Future neutrino physics experiments intend to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. To increase performance, integrated readout electronics should work inside the cryostat. Due to the scale and cost associated with evacuating and filling the cryostat, the electronics will be unserviceable for the duration of the experiment. Therefore, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is via hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130nm nMOS transistors operating at cryogenic temperatures are investigated. The results show that the difference in lifetime for room temperature operation and cryogenic operation for this process are not great and the lifetimes at both 300K and at 77K can be projected to more than 20 years at the nominal voltage (1.5V) for this technology.

  20. Evaluation of a high-dose extended multipass gray writing system for 130-nm pattern generation

    NASA Astrophysics Data System (ADS)

    Chabala, Jan M.; Weaver, Suzanne; Alexander, David W.; Pearce-Percy, Henry T.; Lu, Maiying; Cole, Damon M.; Abboud, Frank E.

    2000-07-01

    Recent developments in electron-beam (e-beam) systems and mask-writing strategies facilitate pattern generation for the 130-nm IC generation. The MEBESR 5500 pattern generation system incorporates a high-dose electron optical system and a high-throughput writing strategy, Multipass Gray-II (MPG-II). We evaluate the effectiveness of these innovations by three criteria: improved resolution, improved critical dimension (CD) control, and increased throughput. The conclusions of this paper are based on results from extensive modeling, test masks, and factory acceptance masks. Mask resist choice and processing have been optimized for the MEBES 5500 system. A consequence of these improvements is greater productivity for 150 nm devices and early development of 130 nm devices. The MEBES 5500 system uses a high-dose gun and electron optical system. The maximum current density that can be delivered to the mask is 800 A/cm2, twice the value of previous MEBES systems. Without loss of throughput, it is possible to increase the dose deposited in the resist, while using smaller e-beam sizes. These capabilities are exploited to improve printing of submicrometer features, including 200 nm-scale optical proximity correction (OPC) patterns. At small data addresses (<17.1 nm), the MPG-II writing strategy provides twice the throughput of the existing multipass gray (MPG) strategy with the same instrument, and 16X the throughput of traditional single-pass printing (SPP) with the MEBES 4500 system. The fundamentals of the MPG-II strategy are described, as well as throughput and lithographic results.

  1. Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

    NASA Technical Reports Server (NTRS)

    Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.; Ackland, B.; Dickinson, A.; Eid, E.; Inglis, D.

    1994-01-01

    This paper describes ongoing research and development of CMOS active pixel image sensors for low cost commercial applications. A number of sensor designs have been fabricated and tested in both p-well and n-well technologies. Major elements in the development of the sensor include on-chip analog signal processing circuits for the reduction of fixed pattern noise, on-chip timing and control circuits and on-chip analog-to-digital conversion (ADC). Recent results and continuing efforts in these areas will be presented.

  2. 130-nm reticle inspection using multibeam UV-wavelength database inspection

    NASA Astrophysics Data System (ADS)

    Aquino, Christopher M.; Schlaffer, Robert

    2002-07-01

    The TeraStar family of reticle inspection systems were introduced in 2000 with die-to-die and STARlightT capability. These tools set the standard for high-resolution reticle inspection for the 130 nm design rule and below. The latest addition to the TeraStar family is the TeraStar SLF77, which extends the tool platform to include die-to-database inspection capability. Sensitivity for Chrome on Glass is 100 nm with much greater tolerance for inspecting aggressive OPC features such as serifs and assist lines. Many advanced reticles that are not inspectable on previous generation inspection tools are all inspectable on the TeraStar SLF77. Data prep times and file structure have been significantly improved with the average prep time being less than 10 percent of the 365UV-HR and average output file size less than 25 percent of the GigaPrep. The TeraStar SLF77 incorporates all the features of the TeraStar family such as triple-beam optics and TeraPro HP High Productivity Modes with the ability to run STARlight inspections concurrently with either die-to-die or die-to-database pattern inspections. Advanced registration algorithms accommodate subtle plate and machine errors to provide high sensitivity with low false detections. Advanced image overlay inspects small lines and OPC features and is very independent of defect shape and location. The TeraStar SLF77 has removed the barriers that existed with previous generation database inspection tools and made advanced reticle die-to-database inspection cost effective. Last October, KLA-Tencor introduced the TeraStar SLF77 and the three beta sites have recently completed beta evaluation. Here we present the first results from the use of the TeraStar in a production environment triple beam die-to-database inspection system. We have also shipped more than ten systems to customers worldwide. This paper describes the implementation of productivity improvements at the beta sites, performance on 130nm node customer product reticles, and KLA-Tencor's continued development on advanced inspection reticles.

  3. Improved gate process control at the 130-nm node using spectroscopic-ellipsometry-based profile metrology

    NASA Astrophysics Data System (ADS)

    Hodges, J. Scott; Lin, Yu-Lun C.; Burrows, Dale R.; Chiao, Ray H.; Peters, Robert M.; Rangarajan, Srinivasan; Bhatia, Kamal N.; Lakkapragada, Suresh

    2003-05-01

    The ability to control the cross-sectional profile of polysilicon gate structures on semiconductor devices is paramount to maximize product yield and transistor performance. Tighter control of gate profile parameters leads to a tighter distribution of transistor speeds, resulting in more optimized and consistent device performance. Furthermore, the ability to correlate physical in-line profile measurements taken at gate patterning process steps, to back-end-of-line device parametric test results, enables semiconductor manufacturers to minimize the cost per good die produced, by accurately screening out-of-spec product early in the process flow. The significant increase in the number of chips on today's 300mm wafers heightens the importance of obtaining reliable in-line data. In addition, the reduction of design rules to 130nm and below is driving precision requirements on metrology to <1nm, in order to maintain acceptable precision-to-tolerance (P/T) ratios. Historical methods of in-line metrology (Low Voltage Scanning Electron Microscopy, Atomic Force Microscopy, Electrical Critical Dimension Measurement) all face limitations with regards to precision, correlation, or throughput. This paper will demonstrate the use of Spectroscopic Ellipsometry to provide fast, accurate, and precise two-dimensional profile information on polysilicon gate structures. This metrology technique is currently being utilized for in-line process control and product disposition, at the gate lithography and etch process steps, on 130nm generation logic devices manufactured in Texas Instruments' DMOS 6 300mm wafer fabrication facility. A brief description of the measurement theory and gate profile measurement solution for both dense and isolated structures will be given. This will be followed by data generated from DMOS 6 production material. Using Spectroscopic Ellipsometry, precision results of <0.5nm for CD and height, and <0.25 degrees for profile sidewall angle were obtained at both the lithography and etch measurement steps. The use of CD and sidewall angle information in an APC loop to improve control over the gate trim etch process will also be discussed. Data will be presented showing univariate and multivariate correlation of gate etch profile parameters to post-metalization transistor drive current (IDrive) that is equivalent or superior to existing metrology techniques. Finally, examples of where Spectroscopic Ellipsometry has both increased sensitivity and shortened response time to gate etch process excursions will be presented.

  4. Commercial CMOS image sensors as X-ray imagers and particle beam monitors

    NASA Astrophysics Data System (ADS)

    Castoldi, A.; Guazzoni, C.; Maffessanti, S.; Montemurro, G. V.; Carraresi, L.

    2015-01-01

    CMOS image sensors are widely used in several applications such as mobile handsets webcams and digital cameras among others. Furthermore they are available across a wide range of resolutions with excellent spectral and chromatic responses. In order to fulfill the need of cheap systems as beam monitors and high resolution image sensors for scientific applications we exploited the possibility of using commercial CMOS image sensors as X-rays and proton detectors. Two different sensors have been mounted and tested. An Aptina MT9v034, featuring 752 × 480 pixels, 6μm × 6μm pixel size has been mounted and successfully tested as bi-dimensional beam profile monitor, able to take pictures of the incoming proton bunches at the DeFEL beamline (1-6 MeV pulsed proton beam) of the LaBeC of INFN in Florence. The naked sensor is able to successfully detect the interactions of the single protons. The sensor point-spread-function (PSF) has been qualified with 1MeV protons and is equal to one pixel (6 mm) r.m.s. in both directions. A second sensor MT9M032, featuring 1472 × 1096 pixels, 2.2 × 2.2 μm pixel size has been mounted on a dedicated board as high-resolution imager to be used in X-ray imaging experiments with table-top generators. In order to ease and simplify the data transfer and the image acquisition the system is controlled by a dedicated micro-processor board (DM3730 1GHz SoC ARM Cortex-A8) on which a modified LINUX kernel has been implemented. The paper presents the architecture of the sensor systems and the results of the experimental measurements.

  5. Shallow-trench-isolation bounded single-photon avalanche diodes in commercial deep submicron CMOS technologies

    NASA Astrophysics Data System (ADS)

    Finkelstein, Hod

    This dissertation describes the first single-photon detection device to be manufactured in a commercial deep-submicron CMOS technology. It also describes novel self-timed peripheral circuits which optimize the performance of the new device. An extension of the new device for dual-color single-photon detection is investigated. Finally, an area- and power-efficient method for single-photon frequency upconversion is presented, analyzed, and experimentally examined. Single-photon avalanche diodes have been used in diverse applications, including three-dimensional laser radar, three-dimensional facial mapping, fluorescence-correlation techniques and time-domain tomography. Due to the high electric fields which these devices must sustain, they have traditionally been manufactured in custom processes, severely limiting their speed and the ability to integrate them in high-resolution imagers. By utilizing a process module originally designed to enhance the performance of CMOS transistors, we achieve highly planar junctions in an area-efficient manner. This results in SPADs exhibiting high fill factors, small pitch and ultrafast operation. Device miniaturization is accompanied by excessive noise, which was shown to emanate from trapped avalanche charges. Due to the fast recharging of the device, these charges are released in a subsequent charged phase of the device, causing correlated after-pulses. We present electrostatic and electrical simulation results, as well as a comprehensive characterization of the new device. We also show for the first time that by utilizing the two junctions included in the device, we can selectively detect photons of different wavelengths in the same pixel, as is desirable in cross-correlation experiments. This dissertation also describes an efficient new method for single-photon frequency upconversion. This is desirable for applications including quantum-key distribution and high-resolution near-infrared imaging. The new technique is based on electroluminescence in or near the multiplication region of the device, resulting from hot-carrier recombination. We model a proposed hybrid device and deduce the critical parameters for efficient upconversion. Lastly, we experimentally demonstrate that the electroluminescence yield from an InGaAs/InAlAs avalanche diode is sufficient for highly-efficient upconversion.

  6. Radiation-enhanced gate-induced-drain-leakage current in the 130 nm partially-depleted SOI pMOSFET

    NASA Astrophysics Data System (ADS)

    Peng, Chao; Hu, Zhiyuan; Ning, Bingxu; Dai, Lihua; Bi, Dawei; Zhang, Zhengxuan

    2015-04-01

    The total ionizing dose (TID) effect of the pMOSFET from 130 nm partially-depleted silicon-on-insulator (PDSOI) is investigated. The data obtained from 60Co ?-ray irradiation experiments indicate that input/output (I/O) device is more susceptible to TID effect than the core device. An anomalous off-state leakage increase is observed for I/O pMOSFET when drain is biased at a high voltage after irradiation. It is proved that this radiation-induced leakage relates to the enhanced gate-induce-drain-leakage (GIDL). Both the radiation-induced interface traps at the gate-oxide/body interface and the oxide trapped charges in the buried oxide (BOX) are responsible for the growth of the leakage current. These conclusions are also verified by the TCAD simulations. The isothermal annealing can recover the leakage current to the pre-irradiation level.

  7. Investigating the degradation mechanisms caused by the TID effects in 130 nm PDSOI I/O NMOS

    NASA Astrophysics Data System (ADS)

    Peng, Chao; Hu, Zhiyuan; Zhang, Zhengxuan; Huang, Huixiang; Ning, Bingxu; Bi, Dawei

    2014-06-01

    This paper evaluates the radiation responses of 3.3 V I/O NMOSFETs from 130 nm partially-depleted silicon-on-insulator (PDSOI) technology. The data obtained from 60Co ionizing radiation experiments indicate that charge trapped in the shallow trench isolation, particularly at the bottom region of the trench oxide, should be the dominant contributor to the off-state drain-to-source leakage current under ON bias. The body doping profile and device dimension are two key factors affecting the performance degradation of the PDSOI transistors after radiation. Significant front gate threshold voltage shift is observed in the T-shape gate device, which is well known as the Radiation Induced Narrow Channel Effect (RINCE). The charge trapped in the buried oxide can induce large threshold voltage shift in the front gate transistor through coupling effect in the low body doping device. The coupling effect is evaluated through three-dimensional simulation. A degradation of the carrier mobility which relates to shallow trench isolation (STI) oxide trapped charge in the narrow channel device is also discussed.

  8. High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments

    NASA Astrophysics Data System (ADS)

    Perić, Ivan; Fischer, Peter; Kreidl, Christian; Hanh Nguyen, Hong; Augustin, Heiko; Berger, Niklaus; Kiehn, Moritz; Perrevoort, Ann-Kathrin; Schöning, André; Wiedner, Dirk; Feigl, Simon; Heim, Timon; Meng, Lingxin; Münstermann, Daniel; Benoit, Mathieu; Dannheim, Dominik; Bompard, Frederic; Breugnon, Patrick; Clemens, Jean-Claude; Fougeron, Denis; Liu, Jian; Pangaud, Patrick; Rozanov, Alexandre; Barbero, Marlon; Backhaus, Malte; Hügging, Fabian; Krüger, Hans; Lütticke, Florian; Mariñas, Carlos; Obermann, Theresa; Garcia-Sciveres, Maurice; Schwenker, Benjamin; Dierlamm, Alexander; La Rosa, Alessandro; Miucci, Antonio

    2013-12-01

    High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 1015 neq/cm2, nearly 100% detection efficiency and a spatial resolution of about 3 μm were demonstrated. Since 2011 the HV detectors have first applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process.

  9. An Acetone Microsensor with a Ring Oscillator Circuit Fabricated Using the Commercial 0.18 μm CMOS Process

    PubMed Central

    Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

    2014-01-01

    This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is α-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the α-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm. PMID:25036331

  10. Micro ethanol sensors with a heater fabricated using the commercial 0.18 μm CMOS process.

    PubMed

    Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 µm complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

  11. Analysis of the performance of CMOS APS imagers after proton damage

    NASA Astrophysics Data System (ADS)

    Meroli, S.; Passeri, D.; Servoli, L.; Angelucci, A.

    2013-02-01

    In this work we have irradiated a standard commercial CMOS imager with a 24 MeV proton beam at INFN Laboratori Nazionali del Sud, Catania (Italy) up to a nominal fluence of 1014 [protons/cm-2]. The device under test was a standard VGA detector, fabricated with a 130 nm technology without radiation hardening. During the irradiation the detector was operated to monitor the progressive damaging of the sensor and the associated on-pixel electronics. After 18 months from the irradiation damage session, with the detector stored at room temperature, a study on the detection efficiency and charge collection capability has been carried out using fluorescent X-ray photons, emitted from copper target. We found that the detector is still working at 1013 protons/cm2, with a moderate increase of the noise and a slightly decrease of the detection capabilities.

  12. A Comparative Study of Heavy Ion and Proton Induced Bit Error Sensitivity and Complex Burst Error Modes in Commercially Available High Speed SiGe BiCMOS

    NASA Technical Reports Server (NTRS)

    Marshall, Paul; Carts, Marty; Campbell, Art; Reed, Robert; Ladbury, Ray; Seidleck, Christina; Currie, Steve; Riggs, Pam; Fritz, Karl; Randall, Barb

    2004-01-01

    A viewgraph presentation that reviews recent SiGe bit error test data for different commercially available high speed SiGe BiCMOS chips that were subjected to various levels of heavy ion and proton radiation. Results for the tested chips at different operating speeds are displayed in line graphs.

  13. Charge pump design in 130 nm SiGe BiCMOS technology for low-noise fractional-N PLLs

    NASA Astrophysics Data System (ADS)

    Kucharski, M.; Herzel, F.

    2015-11-01

    This paper presents a numerical comparison of charge pumps (CP) designed for a high linearity and a low noise to be used in a fractional-N phase-locked loop (PLL). We consider a PLL architecture, where two parallel CPs with DC offset are used. The CP for VCO fine tuning is biased at the output to keep the VCO gain constant. For this specific architecture, only one transistor per CP is relevant for phase detector linearity. This can be an nMOSFET, a pMOSFET or a SiGe HBT, depending on the design. The HBT-based CP shows the highest linearity, whereas all charge pumps show similar device noise. An internal supply regulator with low intrinsic device noise is included in the design optimization.

  14. Radiation Characteristics of a 0.11 Micrometer Modified Commercial CMOS Process

    NASA Technical Reports Server (NTRS)

    Poivey, Christian; Kim, Hak; Berg, Melanie D.; Forney, Jim; Seidleck, Christina; Vilchis, Miguel A.; Phan, Anthony; Irwin, Tim; LaBel, Kenneth A.; Saigusa, Rajan K.; Mirabedini, Mohammad R.; Finlinson, Rick; Suvkhanov, Agajan; Hornback, Verne; Sung, Jun; Tung, Jeffrey

    2006-01-01

    We present radiation data, Total Ionizing Dose and Single Event Effects, on the LSI Logic 0.11 micron commercial process and two modified versions of this process. Modified versions include a buried layer to guarantee Single Event Latchup immunity.

  15. Laser-induced plasma spectroscopy to as low as 130 nm when a gas-purged spectrograph and ICCD detection are used

    NASA Astrophysics Data System (ADS)

    Kaski, Saara; Häkkänen, Heikki; Korppi-Tommola, Jouko

    2003-10-01

    An experimental setup is described for measuring laser-induced plasma emission spectra in the near vacuum UV with a Czerny-Turner spectrograph and intensified charge-coupled device under atmospheric pressure. With a simple gas-purge technique, emission lines down to 130 nm could be recorded. The strongest emission lines of bromine, chlorine, and iodine in the near vacuum UV are easily detected.

  16. Micro Ethanol Sensors with a Heater Fabricated Using the Commercial 0.18 μm CMOS Process

    PubMed Central

    Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

  17. Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

    NASA Technical Reports Server (NTRS)

    Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Staller, C.; Zhou, Z; Fossum, E.

    1994-01-01

    JPL, under sponsorship from the NASA Office of Advanced Concepts and Technology, has been developing a second-generation solid-state image sensor technology. Charge-coupled devices (CCD) are a well-established first generation image sensor technology. For both commercial and NASA applications, CCDs have numerous shortcomings. In response, the active pixel sensor (APS) technology has been under research. The major advantages of APS technology are the ability to integrate on-chip timing, control, signal-processing and analog-to-digital converter functions, reduced sensitivity to radiation effects, low power operation, and random access readout.

  18. Cross/bar polymer electro-optic routing switch with broadband flatting spectral response over 130 nm: Principle, design and analysis

    NASA Astrophysics Data System (ADS)

    Zheng, Chuan-Tao; Zheng, Li-Hua; Luo, Qian-Qian; Liang, Lei; Ma, Chun-Sheng; Zhang, Da-Ming

    2013-05-01

    A novel non-resonance 2×2 polymer electro-optic (EO) switch with flatting spectral response is proposed by employing two-section reversed active Mach-Zehnder interferometers (MZIs), a passive middle directional coupler (M-DC) and two passive phase generating couplers (PGCs). Two crosstalk compensations are performed by optimizing the PGCs to broaden the spectrum under bar-state and optimizing the two active MZIs to broaden the spectrum under cross-state. The bar-state and cross-state voltages are 0 and ±4 V, respectively, with the two optimized MZI EO region lengths of 4068 and 5941 μm. Sufficiently considering wavelength dispersion of material and waveguide, a wide spectrum over 130 nm (1473-1603 nm) is achieved for dropping the crosstalk below -30 dB, and within this range, an insertion loss of 1.8-12.3 dB is observed. Under the same crosstalk level, this spectrum is over 2 times of that of the traditional 2×2 MZI switch (60 nm) based on the same materials. This broadband 2×2 switch is more attractive than our previously reported broadband 1×1 switch due to cross/bar routing operations other than simple ON/OFF functions.

  19. Continuous measurement of radiation damage of standard CMOS imagers

    NASA Astrophysics Data System (ADS)

    Servoli, Leonello; Bizzarri, Fabrizio; Passeri, Daniele

    2011-12-01

    In this work we have irradiated a standard CMOS VGA imager with a 24 MeV proton beam at INFN Laboratori Nazionali del Sud, up to a nominal fluence of 10 14 protons/cm 2. The device under test was fabricated with a 130 nm technology without radiation hardening. During the damaging the detector was fully operational to monitor the progressive damaging of the sensor and the associated on-pixel electronics in terms of detection efficiency, charge collection and noise. We found that the detector is still working at 10 13 protons/cm 2, with a moderate increase of the noise (20%).

  20. A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems.

    PubMed

    Zheng, Xuezhe; Liu, Frankie; Patil, Dinesh; Thacker, Hiren; Luo, Ying; Pinguet, Thierry; Mekis, Attila; Yao, Jin; Li, Guoliang; Shi, Jing; Raj, Kannan; Lexau, Jon; Alon, Elad; Ho, Ron; Cunningham, John E; Krishnamoorthy, Ashok V

    2010-01-01

    We report ultra-low-power (690fJ/bit) operation of an optical receiver consisting of a germanium-silicon waveguide detector intimately integrated with a receiver circuit and embedded in a clocked digital receiver. We show a wall-plug power efficiency of 690microW/Gbps for the photonic receiver made of a 130nm SOI CMOS Ge waveguide detector integrated to a 90nm Si CMOS receiver circuit. The hybrid CMOS photonic receiver achieved a sensitivity of -18.9dBm at 5Gbps for BER of 10(-12). Enabled by a unique low-overhead bias refresh scheme, the receiver operates without the need for DC balanced transmission. Small signal measurements of the CMOS Ge waveguide detector showed a 3dB bandwidth of 10GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit will be possible. PMID:20173840

  1. Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor/System-on-a-Chip

    NASA Technical Reports Server (NTRS)

    Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

    2015-01-01

    Hardness assurance test results of Intel state-of-the-art 14nm “Broadwell” U-series processor / System-on-a-Chip (SoC) for total ionizing dose (TID) are presented, along with exploratory results from trials at a medical proton facility. Test method builds upon previous efforts [1] by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

  2. Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor - System-on-a-Chip

    NASA Technical Reports Server (NTRS)

    Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

    2015-01-01

    Hardness assurance test results of Intel state-of-the-art 14nm Broadwell U-series processor System-on-a-Chip (SoC) for total dose are presented, along with first-look exploratory results from trials at a medical proton facility. Test method builds upon previous efforts by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

  3. High-temperature Complementary Metal Oxide Semiconductors (CMOS)

    NASA Technical Reports Server (NTRS)

    Mcbrayer, J. D.

    1981-01-01

    The results of an investigation into the possibility of using complementary metal oxide semiconductor (CMOS) technology for high temperature electronics are presented. A CMOS test chip was specifically developed as the test bed. This test chip incorporates CMOS transistors that have no gate protection diodes; these diodes are the major cause of leakage in commercial devices.

  4. A CMOS readout circuit for microstrip detectors

    NASA Astrophysics Data System (ADS)

    Nasri, B.; Fiorini, C.

    2015-03-01

    In this work, we present the design and the results of a CMOS analog channel for silicon microstrips detectors. The readout circuit was initially conceived for the outer layers of the SuperB silicon vertex tracker (SVT), but can serve more generally other microstrip-based detection systems. The strip detectors considered show a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been investigated. The ASIC is composed by a preamplifier, shaping amplifier and a Time over Threshold (T.o.T) block for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit includes the possibility to select the peaking time of the shaper output from four values: 250 ns, 375 ns, 500 ns and 750 ns. In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The ASIC prototype has been fabricated in the 130 nm IBM technology which is considered intrinsically radiation hard. The results of the experimental characterization of a produced prototype are satisfactorily matched with simulation.

  5. Graphene/Si CMOS hybrid hall integrated circuits.

    PubMed

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-01-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

  6. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  7. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    PubMed Central

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-01-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

  8. Ion traps fabricated in a CMOS foundry

    SciTech Connect

    Mehta, K. K.; Ram, R. J.; Eltony, A. M.; Chuang, I. L.; Bruzewicz, C. D.; Sage, J. M. Chiaverini, J.

    2014-07-28

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  9. Ion traps fabricated in a CMOS foundry

    NASA Astrophysics Data System (ADS)

    Mehta, K. K.; Eltony, A. M.; Bruzewicz, C. D.; Chuang, I. L.; Ram, R. J.; Sage, J. M.; Chiaverini, J.

    2014-07-01

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  10. 25Gb/s 1V-driving CMOS ring modulator with integrated thermal tuning.

    PubMed

    Li, Guoliang; Zheng, Xuezhe; Yao, Jin; Thacker, Hiren; Shubin, Ivan; Luo, Ying; Raj, Kannan; Cunningham, John E; Krishnamoorthy, Ashok V

    2011-10-10

    We report a high-speed ring modulator that fits many of the ideal qualities for optical interconnect in future exascale supercomputers. The device was fabricated in a 130 nm SOI CMOS process, with 7.5 μm ring radius. Its high-speed section, employing PN junction that works at carrier-depletion mode, enables 25 Gb/s modulation and an extinction ratio >5 dB with only 1V peak-to-peak driving. Its thermal tuning section allows the device to work in broad wavelength range, with a tuning efficiency of 0.19 nm/mW. Based on microwave characterization and circuit modeling, the modulation energy is estimated ~7 fJ/bit. The whole device fits in a compact 400 μm2 footprint. PMID:21997052

  11. Adaptive Threshold Neural Spike Detector Using Stationary Wavelet Transform in CMOS.

    PubMed

    Yang, Yuning; Boling, C Sam; Kamboh, Awais M; Mason, Andrew J

    2015-11-01

    Spike detection is an essential first step in the analysis of neural recordings. Detection at the frontend eases the bandwidth requirement for wireless data transfer of multichannel recordings to extra-cranial processing units. In this work, a low power digital integrated spike detector based on the lifting stationary wavelet transform is presented and developed. By monitoring the standard deviation of wavelet coefficients, the proposed detector can adaptively set a threshold value online for each channel independently without requiring user intervention. A prototype 16-channel spike detector was designed and tested in an FPGA. The method enables spike detection with nearly 90% accuracy even when the signal-to-noise ratio is as low as 2. The design was mapped to 130 nm CMOS technology and shown to occupy 0.014 mm(2) of area and dissipate 1.7 μW of power per channel, making it suitable for implantable multichannel neural recording systems. PMID:25955990

  12. CMOS dot matrix microdisplay

    NASA Astrophysics Data System (ADS)

    Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

    2011-03-01

    Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

  13. The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector

    NASA Astrophysics Data System (ADS)

    Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.

    2013-12-01

    This work presents the characterization of Deep N-well (DNW) active pixel sensors fabricated in a vertically integrated technology. The DNW approach takes advantage of the triple well structure to lay out a sensor with relatively large charge collecting area (as compared to standard three transistor MAPS), while the readout is performed by a classical signal processing chain for capacitive detectors. This new 3D design relies upon stacking two homogeneous tiers fabricated in a 130 nm CMOS process where the top tier is thinned down to about 12 μm to expose through silicon vias (TSV), therefore making connection to the buried circuits possible. This technology has been used to design a fine pitch 3D CMOS sensor with sparsification capabilities, in view of vertexing applications to the International Linear Collider (ILC) experiments. Results from the characterization of different kind of test structures, including single pixels, 3×3 and 8×8 matrices, are presented.

  14. All-CMOS night vision viewer with integrated microdisplay

    NASA Astrophysics Data System (ADS)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

    2014-02-01

    The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

  15. High-speed multicolour photometry with CMOS cameras

    NASA Astrophysics Data System (ADS)

    Pokhvala, S. M.; Zhilyaev, B. E.; Reshetnyk, V. M.

    2012-11-01

    We present the results of testing the commercial digital camera Nikon D90 with a CMOS sensor for high-speed photometry with a small telescope Celestron 11'' at the Peak Terskol Observatory. CMOS sensor allows to perform photometry in 3 filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system of CMOS sensors is close to the Johnson BVR system. The results of testing show that one can carry out photometric measurements with CMOS cameras for stars with the V-magnitude up to ≃14^{m} with the precision of 0.01^{m}. Stars with the V-magnitude up to ˜10 can be shot at 24 frames per second in the video mode.

  16. Enhanced Carrier Mobility for Improved CMOS Performance

    NASA Astrophysics Data System (ADS)

    Mooney, P. M.

    Various methods of increasing the carrier mobility in the Si channel of CMOS devices have been investigated with the goal of improving their performance. Enhanced mobility was first achieved in devices fabricated from engineered substrates having a surface layer of Si(100) under biaxial tensile strain. More recently increased hole mobility has been achieved using hybrid crystal orientation wafers with p-MOS devices fabricated on surface layers of Si(110) and n-MOS devices fabricated on Si(100) surfaces. Enhanced mobility has also been demonstrated in devices fabricated from engineered substrates having a surface layer of Ge. Uniaxial stress, applied locally to the Si channel, is achieved by certain device fabrication processes in the strained Si technology first commercialized by IBM and Intel. Examples of these different approaches to enhanced carrier mobility in CMOS devices are discussed in this chapter.

  17. Regenerative switching CMOS system

    DOEpatents

    Welch, James D.

    1998-01-01

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

  18. Regenerative switching CMOS system

    DOEpatents

    Welch, J.D.

    1998-06-02

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

  19. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    PubMed Central

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  20. Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

    SciTech Connect

    Sumant, A.V.; Auciello, O.; Yuan, H.-C; Ma, Z.; Carpick, R. W.; Mancini, D. C.; Univ. of Wisconsin; Univ. of Pennsylvania

    2009-05-01

    Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materials integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.

  1. CMOS array design automation techniques

    NASA Technical Reports Server (NTRS)

    Lombardi, T.; Feller, A.

    1976-01-01

    The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

  2. Reticle cleaning process for 130-nm lithography and beyond

    NASA Astrophysics Data System (ADS)

    Handa, Hitoshi; Takahashi, Masumi; Shirai, Hisatsugu

    2001-09-01

    Three cleaning methods were examined to check their strong points. Cleaning results were analyzed from the aspects on removal of particles and chemicals. Starlight inspection results showed that conventional wet cleaning based on chemicals, such as H2SO4 and NH4OH, could remain small particles on chrome-oxide (CrOX). DUV irradiation could assist this traditional SC-1 (mixture of NH4OH and H2O2 and HH(subscript 2O) cleaning in removing these sticking particles. Electrolyzed water, contained anode and cathode water, showed same tendency as SC-1 treatment, which could easily attract particles to CrOX surface. Mechanism of particle removal and attraction was considered from the aspect on electrostatic reaction between particles and photomask surface. ArF ((lambda) =193nm) lithography could cloud quartz surface with crystallized substances. Analytical results implied that they had been generated by optical-chemical reaction between ArF light and chemical residue after cleaning. Experimental results showed that DUV treatment before cleaning was effective to prevent reticle surface from chemical contamination. From the above knowledge, suggestion about reticle cleaning process for ArF lithography is described as a conclusion.

  3. Fully CMOS analog and digital SiPMs

    NASA Astrophysics Data System (ADS)

    Zou, Yu; Villa, Federica; Bronzi, Danilo; Tisa, Simone; Tosi, Alberto; Zappa, Franco

    2015-03-01

    Silicon Photomultipliers (SiPMs) are emerging single photon detectors used in many applications requiring large active area, photon-number resolving capability and immunity to magnetic fields. We present three families of analog SiPM fabricated in a reliable and cost-effective fully standard planar CMOS technology with a total photosensitive area of 11 mm2. These three families have different active areas with fill-factors (21%, 58.3%, 73.7%) comparable to those of commercial SiPM, which are developed in vertical (current flow) custom technologies. The peak photon detection efficiency in the near-UV tops at 38% (fill-factor included) comparable to commercial custom-process ones and dark count rate density is just a little higher than the best-in-class commercial analog SiPMs. Thanks to the CMOS processing, these new SiPMs can be integrated together with active components and electronics both within the microcell and on-chip, in order to act at the microcell level or to perform global pre-processing. We also report CMOS digital SiPMs in the same standard CMOS technology, based on microcells with digitalized processing, all integrated on-chip. This CMOS digital SiPMs has four 321 cells (128 microcells), each consisting of SPAD, active quenching circuit with adjustable dead time, digital control (to switch off noisy SPADs and readout position of detected photons), and fast trigger output signal. The achieved 20% fill-factor is still very good.

  4. CHARACTERIZATION OF A CMOS SENSING CORE FOR ULTRA-MINIATURE WIRELESS IMPLANTABLE TEMPERATURE SENSORS WITH APPLICATION TO CRYOMEDICINE

    PubMed Central

    Khairi, Ahmad; Thaokar, Chandrajit; Fedder, Gary; Paramesh, Jeyanandh; Rabin, Yoed

    2014-01-01

    In effort to improve thermal control in minimally invasive cryosurgery, the concept of a miniature, wireless, implantable sensing unit has been developed recently. The sensing unit integrates a wireless power delivery mechanism, wireless communication means, and a sensing core—the subject matter of the current study. The current study presents a CMOS ultra-miniature PTAT temperature sensing core and focuses on design principles, fabrication of a proof-of-concept, and characterization in a cryogenic environment. For this purpose, a 100μm × 400μm sensing core prototype has been fabricated using a 130nm CMOS process. The senor has shown to operate between −180°C and room temperature, to consume power of less than 1μW, and to have an uncertainty range of 1.4°C and non-linearity of 1.1%. Results of this study suggest that the sensing core is ready to be integrated in the sensing unit, where system integration is the subject matter of a parallel effort. PMID:25001173

  5. Characterization of a CMOS sensing core for ultra-miniature wireless implantable temperature sensors with application to cryomedicine.

    PubMed

    Khairi, Ahmad; Thaokar, Chandrajit; Fedder, Gary; Paramesh, Jeyanandh; Rabin, Yoed

    2014-09-01

    In effort to improve thermal control in minimally invasive cryosurgery, the concept of a miniature, wireless, implantable sensing unit has been developed recently. The sensing unit integrates a wireless power delivery mechanism, wireless communication means, and a sensing core-the subject matter of the current study. The current study presents a CMOS ultra-miniature PTAT temperature sensing core and focuses on design principles, fabrication of a proof-of-concept, and characterization in a cryogenic environment. For this purpose, a 100 μm × 400 μm sensing core prototype has been fabricated using a 130 nm CMOS process. The senor has shown to operate between -180°C and room temperature, to consume power of less than 1 μW, and to have an uncertainty range of 1.4°C and non-linearity of 1.1%. Results of this study suggest that the sensing core is ready to be integrated in the sensing unit, where system integration is the subject matter of a parallel effort. PMID:25001173

  6. Large area CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; Guerrini, N.; Sedgwick, I.

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  7. A Single-Chip 8-Band CMOS Transceiver for 3G Cellular Systems with Digital Interface

    NASA Astrophysics Data System (ADS)

    Yoshida, Hiroshi; Toyoda, Takehiko; Tsurumi, Hiroshi; Itoh, Nobuyuki

    In this paper, a single-chip dual-mode 8-band 130nm CMOS transceiver including A/D/A converters and digital filters with 312MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.

  8. Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

    PubMed Central

    Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

    2010-01-01

    This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K. PMID:22205869

  9. Fabrication and characterization of CMOS-MEMS thermoelectric micro generators.

    PubMed

    Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

    2010-01-01

    This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K. PMID:22205869

  10. CMOS Integrated Carbon Nanotube Sensor

    SciTech Connect

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

    2009-05-23

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  11. Proof of principle study of the use of a CMOS active pixel sensor for proton radiography

    SciTech Connect

    Seco, Joao; Depauw, Nicolas

    2011-02-15

    Purpose: Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). Methods: A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissue contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Results: Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Conclusion: Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The development and use of CMOS in proton radiography could allow in vivo proton range checks, patient setup QA, and real-time tumor tracking.

  12. Hybrid CMOS SiPIN detectors as astronomical imagers

    NASA Astrophysics Data System (ADS)

    Simms, Lance Michael

    Charge Coupled Devices (CCDs) have dominated optical and x-ray astronomy since their inception in 1969. Only recently, through improvements in design and fabrication methods, have imagers that use Complimentary Metal Oxide Semiconductor (CMOS) technology gained ground on CCDs in scientific imaging. We are now in the midst of an era where astronomers might begin to design optical telescope cameras that employ CMOS imagers. The first three chapters of this dissertation are primarily composed of introductory material. In them, we discuss the potential advantages that CMOS imagers offer over CCDs in astronomical applications. We compare the two technologies in terms of the standard metrics used to evaluate and compare scientific imagers: dark current, read noise, linearity, etc. We also discuss novel features of CMOS devices and the benefits they offer to astronomy. In particular, we focus on a specific kind of hybrid CMOS sensor that uses Silicon PIN photodiodes to detect optical light in order to overcome deficiencies of commercial CMOS sensors. The remaining four chapters focus on a specific type of hybrid CMOS Silicon PIN sensor: the Teledyne Hybrid Visible Silicon PIN Imager (HyViSI). In chapters four and five, results from testing HyViSI detectors in the laboratory and at the Kitt Peak 2.1m telescope are presented. We present our laboratory measurements of the standard detector metrics for a number of HyViSI devices, ranging from 1k×1k to 4k×4k format. We also include a description of the SIDECAR readout circuit that was used to control the detectors. We then show how they performed at the telescope in terms of photometry, astrometry, variability measurement, and telescope focusing and guiding. Lastly, in the final two chapters we present results on detector artifacts such as pixel crosstalk, electronic crosstalk, and image persistence. One form of pixel crosstalk that has not been discussed elsewhere in the literature, which we refer to as Interpixel Charge Transfer (IPCT), is introduced. This effect has an extremely significant impact on x-ray astronomy. For persistence, a new theory and accompanying simulations are presented to explain latent images in the HyViSI. In consideration of these artifacts and the overall measured performance, we argue that HyViSI sensors are ready for application in certain regimes of astronomy, such as telescope guiding, measurements of fast planetary transits, and x-ray imaging, but not for others, such as deep field imaging and large focal plane astronomical surveys.

  13. A back-illuminated megapixel CMOS image sensor

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

    2005-01-01

    In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

  14. A Brief Discussion of Radiation Hardening of CMOS Microelectronics

    SciTech Connect

    Myers, D.R.

    1998-12-18

    Commercial microchips work well in their intended environments. However, generic microchips will not fimction correctly if exposed to sufficient amounts of ionizing radiation, the kind that satellites encounter in outer space. Modern CMOS circuits must overcome three specific concerns from ionizing radiation: total-dose, single-event, and dose-rate effects. Minority-carrier devices such as bipolar transistors, optical receivers, and solar cells must also deal with recombination-generation centers caused by displacement damage, which are not major concerns for majority-carrier CMOS devices. There are ways to make the chips themselves more resistant to radiation. This extra protection, called radiation hardening, has been called both a science and an art. Radiation hardening requires both changing the designs of the chips and altering the ways that the chips are manufactured.

  15. Digital-Centric RF CMOS Technologies

    NASA Astrophysics Data System (ADS)

    Matsuzawa, Akira

    Analog-centric RFCMOS technology has played an important role in motivating the change of technology from conventional discrete device technology or bipolar IC technology to CMOS technology. However it introduces many problems such as poor performance, susceptibility to PVT fluctuation, and cost increase with technology scaling. The most important advantage of CMOS technology compared with legacy RF technology is that CMOS can use more high performance digital circuits for very low cost. In fact, analog-centric RF-CMOS technology has failed the FM/AM tuner business and the digital-centric CMOS technology is becoming attractive for many users. It has many advantages; such as high performance, no external calibration points, high yield, and low cost. From the above facts, digital-centric CMOS technology which utilizes the advantages of digital technology must be the right path for future RF technology. Further investment in this technology is necessary for the advancement of RF technology.

  16. Research on evaluation method of CMOS camera

    NASA Astrophysics Data System (ADS)

    Zhang, Shaoqiang; Han, Weiqiang; Cui, Lanfang

    2014-09-01

    In some professional image application fields, we need to test some key parameters of the CMOS camera and evaluate the performance of the device. Aiming at this requirement, this paper proposes a perfect test method to evaluate the CMOS camera. Considering that the CMOS camera has a big fixed pattern noise, the method proposes the `photon transfer curve method' based on pixels to measure the gain and the read noise of the camera. The advantage of this method is that it can effectively wipe out the error brought by the response nonlinearity. Then the reason of photoelectric response nonlinearity of CMOS camera is theoretically analyzed, and the calculation formula of CMOS camera response nonlinearity is deduced. Finally, we use the proposed test method to test the CMOS camera of 2560*2048 pixels. In addition, we analyze the validity and the feasibility of this method.

  17. A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.

    PubMed

    Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

    2011-01-01

    This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

  18. Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units

    SciTech Connect

    Smith, J.H.; Ellis, J.R.; Montague, S.; Allen, J.J.

    1997-03-01

    One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing. In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.

  19. A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

    PubMed Central

    Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

    2011-01-01

    This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

  20. Latest results of the R&D on CMOS MAPS for the Layer0 of the SuperB SVT

    NASA Astrophysics Data System (ADS)

    Balestri, G.; Batignani, G.; Beck, G.; Bernardelli, A.; Berra, A.; Bettarini, S.; Bevan, |A.; Bombelli, L.; Bosi, F.; Bosisio, L.; Casarosa, G.; Ceccanti, M.; Cenci, R.; Citterio, M.; Coelli, S.; Comotti, D.; Dalla Betta, G.-F.; Fabbri, L.; Fiorini, C.; Fontana, G.; Forti, F.; Gabrielli, A.; Gaioni, L.; Gannaway, F.; Giorgi, F.; Giorgi, M. A.; Lanceri, L.; Liberali, V.; Lietti, D.; Lusiani, A.; Mammini, P.; Manazza, A.; Manghisoni, M.; Monti, M.; Morris, J.; Morsani, F.; Nasri, B.; Neri, N.; Oberhof, B.; Palombo, F.; Pancheri, L.; Paoloni, E.; Pellegrini, G.; Perez, A.; Petragnani, G.; Prest, M.; Povoli, M.; Profeti, A.; Quartieri, E.; Rashevskaya, I.; Ratti, L.; Re, V.; Rizzo, G.; Sbarra, C.; Semprini-Cesari, N.; Soldani, A.; Stabile, A.; Stella, C.; Traversi, G.; Valentinetti, S.; Verzellesi, G.; Villa, M.; Vitale, L.; Walsh, J.; Wilson, F.; Zoccoli, A.; Zucca, S.

    2013-12-01

    Physics and high background conditions set very challenging requirements on readout speed, material budget and resolution for the innermost layer of the SuperB Silicon Vertex Tracker operated at the full luminosity. Monolithic Active Pixel Sensors (MAPS) are very appealing in this application since the thin sensitive region allows grinding the substrate to tens of microns. Deep N-Well MAPS, developed in the ST 130 nm CMOS technology, achieved in-pixel sparsification and fast time stamping. Further improvements are being explored with an intense R&D program, including both vertical integration and 2D MAPS with the INMAPS quadruple well. We present the results of the characterization with IR laser, radioactive sources and beam of several chips produced with the 3D (Chartered/Tezzaron) process. We have also studied prototypes exploiting the features of the quadruple well and the high resistivity epitaxial layer of the INMAPS 180 nm process. Promising results from an irradiation campaign with neutrons on small matrices and other test-structures, as well as the response of the sensors to high energy charged tracks are presented.

  1. Nanosecond monolithic CMOS readout cell

    DOEpatents

    Souchkov, Vitali V.

    2004-08-24

    A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

  2. CMOS foveal image sensor chip

    NASA Technical Reports Server (NTRS)

    Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

    2002-01-01

    A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

  3. Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

    NASA Technical Reports Server (NTRS)

    Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

    2012-01-01

    Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

  4. Accelerated life testing effects on CMOS microcircuit characteristics

    NASA Technical Reports Server (NTRS)

    1977-01-01

    Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

  5. Carbon Nanotube Integration with a CMOS Process

    PubMed Central

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  6. Neutron spectrum and dose in a CMOS

    NASA Astrophysics Data System (ADS)

    Vega-Carrillo, H. R.; Paredes-Gutierrez, L.; Borja-Hernandez, C. G.

    2012-10-01

    Using Monte Carlo methods the neutron spectrum in a pacemaker's CMOS has been estimated. A 18 MV LINAC model was used to expose a cell used to define the prostate located in a tissue equivalent phantom model. Neutron fluence at the CMOS is 2.6E(7) n/cm2-Gyx, the spectrum has thermal, epithermal and fast neutrons that will induce secondary, low and high LET, particles whose ionization could induce malfunction and failure of pacemaker in the oncological patient.

  7. Application of CMOS APS in star tracker

    NASA Astrophysics Data System (ADS)

    Liu, Zhi; Wang, Yefan; Yang, Jingyi; Hao, Zhihang

    2002-09-01

    Small satellites are now capable of performing missions that require accurate attitude determination and control. However, low weight, size, power, and cost requirements limit the types of attitude sensors that can be used on a small craft, making attitude estimation difficult. In particular, star trackers -- often the attitude sensors of choice for spacecraft, ballistic missile etc., are not practical for small satellites, and CMOS APS is a good substitute for attitude sensors. Some of the technical advantages of CMOS APS are no blooming, low power consumption, direct digital output, small size and little support circuitry, simple to design, etc. This paper discusses the application probability of CMOS APS technology in star tracker for use in small satellites. A ground-based prototype vision system based on CMOS APS has been built to demonstrate the advantages of using CMOS APS in star tracker. Resolving capability, noise, radiation hardening and some other characteristics are discussed in detail. CMOS image sensor is sure to be a potential replacement of CCD in the field of attitude sensors.

  8. CMOS compatible avalanche photodetector and its application in communications

    NASA Astrophysics Data System (ADS)

    Tang, Miangang; Wu, Zhigang; Li, Guohui

    2014-11-01

    CMOS compatible avalanche photodiodes (CMOS APDs) can be fabricated with standard CMOS technology, which make CMOS APDs are considered as a key optoelectronic device for optical communication systems and optical wireless communication systems. The guard-ring (GR) structure in CMOS APDs can alleviate the premature edge breakdown (PEB) effects and greatly improve the device performance. In this paper, the influence of various type GR structure on CMOS APDs performance are discussed, and its important applications in radio-over-fibre (RoF) are reviewed.

  9. Flexible packaging and integration of CMOS IC with elastomeric microfluidics

    NASA Astrophysics Data System (ADS)

    Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

    2013-05-01

    We have demonstrated flexible packaging and integration of CMOS IC chips with PDMS microfluidics. Microfluidic channels are used to deliver both liquid samples and liquid metals to the CMOS die. The liquid metals are used to realize electrical interconnects to the CMOS chip. As a demonstration we integrated a CMOS magnetic sensor die and matched PDMS microfluidic channels in a flexible package. The packaged system is fully functional under 3cm bending radius. The flexible integration of CMOS ICs with microfluidics enables previously unavailable flexible CMOS electronic systems with fluidic manipulation capabilities, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing.

  10. Integration of solid-state nanopores in a 0.5 μm cmos foundry process

    PubMed Central

    Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

    2013-01-01

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

  11. Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

    PubMed

    Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

    2013-04-19

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

  12. Integration of solid-state nanopores in a 0.5 μm CMOS foundry process

    NASA Astrophysics Data System (ADS)

    Uddin, A.; Yemenicioglu, S.; Chen, C.-H.; Corigliano, E.; Milaninia, K.; Theogarajan, L.

    2013-04-01

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

  13. Future of nano CMOS technology

    NASA Astrophysics Data System (ADS)

    Iwai, Hiroshi

    2015-10-01

    Although Si MOS devices have dominated the integrated circuit applications over the four decades, it has been anticipated that the development of CMOS would reach its limits after the next decade because of the difficulties in the technologies for further downscaling and also because of some fundamental limits of MOSFETs. However, there have been no promising candidates yet, which can replace Si MOSFETs with better performance with low cost. Thus, for the moment, it seems that we have to stick to the Si MOSFET devices until their end. The downsizing is limited by the increase of off-leakage current between source and drain. In order to suppress the off-leakage current, multi-gate structures (FinFET, Tri-gate, and Si-nanowire MOSFETs) are replacing conventional planar MOSFETs, and continuous innovation of high-k/metal gate technologies has enabled EOT scaling down to 0.9 nm in production. However, it was found that the multi-gate structures have a future big problem of significant conduction reduction with decrease in fin width. Also it is not easy to further decrease EOT because of the mobility and reliability degradation. Furthermore, the development of EUV (Extremely Ultra-Violet) lithography, which is supposed to be essential for sub-10 nm lithography, delays significantly because of insufficient illumination intensity for production. Thus, it is now expected that the reduction rate of the gate length, which has a strong influence on the off-leakage current, will become slower in near future.

  14. Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique.

    PubMed

    Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

    2009-01-01

    In this study we used the commercial 0.35 μm CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz. PMID:22454581

  15. Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique

    PubMed Central

    Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

    2009-01-01

    In this study we used the commercial 0.35 μm CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz. PMID:22454581

  16. Fabrication and Characterization of CMOS-MEMS Magnetic Microsensors

    PubMed Central

    Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5–200 mT. PMID:24172287

  17. A CMOS smart temperature and humidity sensor with combined readout.

    PubMed

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-01-01

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA. PMID:25230305

  18. A CMOS Smart Temperature and Humidity Sensor with Combined Readout

    PubMed Central

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-01-01

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 μA. PMID:25230305

  19. Investigation of heavy particle induced latch-up, using a Californium-252 source, in CMOS SRAMs and PROMs

    NASA Astrophysics Data System (ADS)

    Stephen, J. H.; Sanderson, T. K.; Mapper, D.; Hardman, M.; Farren, J.; Adams, L.; Harboe-Sorensen, R.

    1984-12-01

    Heavy ion-induced latch-up, in commercial CMOS SRAMs and PROMs, was examined using a laboratory Californium-252 source, in order to simulate the cosmic environment. The ability to use the CASE system (Californium-252 Assessment of Single-event Effects) enabled detailed electrical measurements to be made of the devices in the latched condition.

  20. Beam-test results of 4k pixel CMOS MAPS and high resistivity striplet detectors equipped with digital sparsified readout in the Slim5 low mass silicon demonstrator

    NASA Astrophysics Data System (ADS)

    Villa, M.; Bruschi, M.; Di Sipio, R.; Fabbri, L.; Giacobbe, B.; Gabrielli, A.; Giorgi, F.; Pellegrini, G.; Sbarra, C.; Semprini, N.; Spighi, R.; Valentinetti, S.; Zoccoli, A.; Avanzini, C.; Batignani, G.; Bettarini, S.; Bosi, F.; Calderini, G.; Ceccanti, M.; Cenci, R.; Cervelli, A.; Crescioli, F.; Dell'Orso, M.; Forti, F.; Giannetti, P.; Giorgi, M. A.; Lusiani, A.; Gregucci, S.; Mammini, P.; Marchiori, G.; Massa, M.; Morsani, F.; Neri, N.; Paoloni, E.; Piendibene, M.; Profeti, A.; Rizzo, G.; Sartori, L.; Walsh, J.; Yurtsev, E.; Manghisoni, M.; Re, V.; Traversi, G.; Andreoli, C.; Gaioni, L.; Pozzati, E.; Ratti, L.; Speziali, V.; Gamba, D.; Giraudo, G.; Mereu, P.; Dalla Betta, G. F.; Soncini, G.; Fontana, G.; Bomben, M.; Bosisio, L.; Cristaudo, P.; Giacomini, G.; Jugovaz, D.; Lanceri, L.; Rashevskaya, I.; Vitale, L.; Venier, G.

    2010-05-01

    The results obtained by the Slim5 collaboration on a low material budget tracking silicon demonstrator put on a 12 GeV/ c proton test beam at CERN are reported. Inside a reference telescope, two different and innovative detectors were placed for careful tests. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130 nm CMOS Technology, square pixels 50 μm wide, thinned down to 100 μm and equipped with a digital sparsified readout running up to 50 MHz. The other was a high resistivity double sided silicon detector, 200 μm thick, with short strips with 50 μm pitch at 45∘ angle to the detector's edge. The detectors were equipped with dedicated fast readout architectures performing on-chip data sparsification and providing the timing information for the hits. The criteria followed in the design of the pixel sensor and of the pixel readout architecture will be reviewed. Preliminary measurements of the pixel charge collection, track detection efficiencies and resolutions of pixel and strip sensors are discussed. The data driven architecture of the readout chips has been fully exploited in the test beam by a data acquisition system able to collect on electronic board up to 2.5 Million events per second before triggering. By using a dedicated Associative Memory board, we were able to perform a level 1 trigger system, with minimal latency, identifying cleanly tracks traversing the detectors. System architecture and main performances are shown.

  1. Spectrometry with consumer-quality CMOS cameras.

    PubMed

    Scheeline, Alexander

    2015-01-01

    Many modern spectrometric instruments use diode arrays, charge-coupled arrays, or CMOS cameras for detection and measurement. As portable or point-of-use instruments are desirable, one would expect that instruments using the cameras in cellular telephones and tablet computers would be the basis of numerous instruments. However, no mass market for such devices has yet developed. The difficulties in using megapixel CMOS cameras for scientific measurements are discussed, and promising avenues for instrument development reviewed. Inexpensive alternatives to use of the built-in camera are also mentioned, as the long-term question is whether it is better to overcome the constraints of CMOS cameras or to bypass them. PMID:25626545

  2. Noise Immunity Improvement in Dynamic CMOS circuits

    NASA Astrophysics Data System (ADS)

    Khare, Kavita; Ambulker, Sunanda

    2010-11-01

    For the purpose of high system performance dynamic CMOS circuits are widely use in high performance VLSI chips. But dynamic CMOS gates are found to be less noise resistant then static CMOS gates. Due to aggressive technology scaling, stringent noise requirement has been increased, hence the noise tolerance of dynamic circuits has to be first improved for the over all reliable operation of VLSI chip. A new technique (Transparency window technique) which increases the noise immunity with the precharge of one internal node of N-logic and isolating the precharge dynamic node-and consequently the output from the inputs during the evaluation phase, is introduced to improve the noise tolerance of digital circuits. Simulation result on Pspice 9.1 and 0.65 μm technology shows that this technique improves noise immunity of the dynamic circuits as compared to conventional and previous noise tolerance technique.

  3. A Standard CMOS Humidity Sensor without Post-Processing

    PubMed Central

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2011-01-01

    A 2 ?W power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 802310 humidity-sensitive layer, and a CMOS capacitance to voltage converter. PMID:22163949

  4. Resistor Extends Life Of Battery In Clocked CMOS Circuit

    NASA Technical Reports Server (NTRS)

    Wells, George H., Jr.

    1991-01-01

    Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

  5. Low power, CMOS digital autocorrelator spectrometer for spaceborne applications

    NASA Technical Reports Server (NTRS)

    Chandra, Kumar; Wilson, William J.

    1992-01-01

    A 128-channel digital autocorrelator spectrometer using four 32 channel low power CMOS correlator chips was built and tested. The CMOS correlator chip uses a 2-bit multiplication algorithm and a full-custom CMOS VLSI design to achieve low DC power consumption. The digital autocorrelator spectrometer has a 20 MHz band width, and the total DC power requirement is 6 Watts.

  6. Performance of radiation-hard HV/HR CMOS sensors for the ATLAS inner detector upgrades

    NASA Astrophysics Data System (ADS)

    Liu, J.; Barbero, M.; Bilbao De Mendizabal, J.; Breugnon, P.; Godiot-Basolo, S.; Pangaud, P.; Rozanov, A.

    2016-03-01

    A major upgrade (Phase II Upgrade) to the Large Hadron Collider (LHC), scheduled for 2022, will be brought to the machine so as to extend its discovery potential. The upgraded LHC, called High-Luminosity LHC (HL-LHC), will run with a nominal leveled instantaneous luminosity of 5×1034 cm-2s-1, more than twice the expected luminosity. This unprecedented luminosity will result in higher occupancy and background radiations, which will request the design of a new Inner Tracker (ITk) which should have higher granularity, reduced material budget and improved radiation tolerance. A new pixel sensor concept based on High Voltage and High Resistivity CMOS (HV/HR CMOS) technology targeting the ATLAS inner detector upgrade is under exploration. With respect to the traditional hybrid pixel detector, the HV/HR CMOS sensor can potentially offer lower material budget, reduced pixel pitch and lower cost. Several prototypes have been designed and characterized within the ATLAS upgrade R&D effort, to investigate the detection and radiation hardness performance of various commercial technologies. An overview of the HV/HR CMOS sensor operation principle is described in this paper. The characterizations of three prototypes with X-ray, proton and neutron irradiation are also given.

  7. CMOS VCSEL driver circuit for 25+Gbps/channel short-reach parallel optical links

    NASA Astrophysics Data System (ADS)

    Shibata, Masumi

    This thesis proposes a new CMOS driver for Vertical Cavity Surface Emitting LASER (VCSEL) diode arrays. A VCSEL is a promising light source for optical communication. However, its threshold voltage (1.5V for a 850-nm VCSEL) exceeds the rated supply voltage of nanoscale CMOS technologies. This makes difficult designing a driver sourcing a modulated current to a VCSELs anode directly, an arrangement suitable for low-cost parallel optical links. To overcome this problem, a combination of analog circuit techniques is proposed including a novel pad shield driving technique. A prototype fabricated in a 65-nm CMOS technology achieved 26-Gb/s bit-rate and 1.80-pJ/b power efficiency with an optical modulation amplitude (OMA) of +1.8dBm and 3.1ps-rms jitter when driving a 850-nm 14Gb/s commercial VCSEL. This is the highest-speed anode-driving CMOS VCSEL driver reported to date. Also it has the best power efficiency and the smallest area (0:024 mm2) amongst anode-driving drivers in any process technology.

  8. GaAs heteroepitaxy with submicron Si CMOS: an experimental compatibility study

    NASA Astrophysics Data System (ADS)

    Hornak, Lawrence A.; Tewksbury, Stuart K.; Nariman, Homi E.

    1993-07-01

    Routine use of optical interconnections in MCM based computing systems ideally favors monolithic integration to achieve both high density and manufacturability. The central issue facing this monolithic evolutionary path is the compatibility of both III-V semiconductor growth and subsequent optoelectronic device and passive optical interconnection processing with existing and future generations of CMOS and advanced packaging technology. The influence of GaAs heteroepitaxy and device processing on submicron CMOS is the subject of an ongoing program seeking to experimentally determine compatibility conflicts and through understanding of their physical mechanisms identify directions for achieving GaAs heteroepitaxy compatibility with future CMOS generations. Following a brief review of GaAs heteroepitaxy compatibility concerns, preliminary results from the current experimental program exploring the influence of both thermally simulated and actual GaAs heteroepitaxy on commercial 0.9 micrometers (0.6 micrometers minimum channel length) CMOS are presented including parametric device modeling, interface state, and hot electron measurements of experimental test lot devices.

  9. End-of-fabrication CMOS process monitor

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

    1990-01-01

    A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

  10. Radiation Tolerance of 65nm CMOS Transistors

    SciTech Connect

    Krohn, M.; Bentele, B.; Christian, D. C.; Cumalat, J. P.; Deptuch, G.; Fahim, F.; Hoff, J.; Shenai, A.; Wagner, S. R.

    2015-12-11

    We report on the effects of ionizing radiation on 65 nm CMOS transistors held at approximately -20C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

  11. Low energy CMOS for space applications

    NASA Technical Reports Server (NTRS)

    Panwar, Ramesh; Alkalaj, Leon

    1992-01-01

    The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

  12. Radiation Tolerance of 65nm CMOS Transistors

    DOE PAGESBeta

    Krohn, M.; Bentele, B.; Christian, D. C.; Cumalat, J. P.; Deptuch, G.; Fahim, F.; Hoff, J.; Shenai, A.; Wagner, S. R.

    2015-12-11

    We report on the effects of ionizing radiation on 65 nm CMOS transistors held at approximately -20°C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

  13. Radiation tolerance of 65 nm CMOS transistors

    NASA Astrophysics Data System (ADS)

    Krohn, M.; Bentele, B.; Christian, D. C.; Cumalat, J. P.; Deptuch, G.; Fahim, F.; Hoff, J.; Shenai, A.; Wagner, S. R.

    2015-12-01

    We report on the effects of ionizing radiation on 65 nm CMOS transistors held at approximately ?20 C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

  14. Fully CMOS-compatible titanium nitride nanoantennas

    NASA Astrophysics Data System (ADS)

    Briggs, Justin A.; Naik, Gururaj V.; Petach, Trevor A.; Baum, Brian K.; Goldhaber-Gordon, David; Dionne, Jennifer A.

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  15. Evaluation of a CMOS image detector for low-cost and power medical x-ray imaging applications

    NASA Astrophysics Data System (ADS)

    Smith, Scott T.; Bednarek, Daniel R.; Wobschall, Darold C.; Jeong, Myoungki; Kim, Hyunkeun; Rudin, Stephen

    1999-05-01

    Recent developments in CMOS image detectors are changing the way digital imaging is performed for many applications. The replacement of charge coupled devices (CCDs), with CMOS detectors is a desirable paradigm shift that will depend on the ability to match the high performance characteristics of CCDs. Digital X-ray imaging applications (chest X-ray, mammography) would benefit greatly from this shift because CMOS detectors have the following inherent characteristics: (1) Low operating power (5 - 10 times lower than CCD/processing electronics). (2) Standard CMOS manufacturing process (CCD requires special manufacturing). (3) On-chip integration of analog/digital processing functions (difficult with CCD). (4) Low Cost (5 - 10 times lower cost than CCD). The achievement of both low cost and low power is highly desirable for portable applications as well as situations where large, expensive X-ray imaging machines are not feasible (small hospitals and clinics, emergency medical vehicles, remote sites). Achieving this goal using commercially available components would allow rapid development of such digital X-ray systems as compared with the development difficulties incurred through specialized direct detectors and systems. The focus of this paper is to evaluate a CMOS image detector for medical X-ray applications and to demonstrate the results obtained from a prototype CMOS digital X-ray camera. Results from the images collected from this optically-coupled camera are presented for a particular lens, X-ray conversion screen, and demagnification factor. Further, an overview of the overall power consumption and cost of a multi-sensor CMOS mosaic compared to its CCD counterpart are also reported.

  16. SPICE analysis of the SEU sensitivity of a fully depleted SOI CMOS SRAM cell

    SciTech Connect

    Alles, M.L. )

    1994-12-01

    Fully depleted silicon-on-insulator (SOI) technologies are of interest for commercial applications as well as for use in harsh (radiation-intensive) environments. In both types of application, effects of charged particles (single-event effects) are of concern. Here, SPICE analysis of SEU sensitivity of a 6-T SRAM cell using commercially-representative fully depleted SOI CMOS technology parameters indicates that reduction of the minority carrier lifetime (parasitic bipolar gain) and use of thinner silicon can significantly reduce SEU sensitivity.

  17. Prototype Active Silicon Sensor in 150 nm HR-CMOS technology for ATLAS Inner Detector Upgrade

    NASA Astrophysics Data System (ADS)

    Rymaszewski, P.; Barbero, M.; Breugnon, P.; Godiot, S.; Gonella, L.; Hemperek, T.; Hirono, T.; Hügging, F.; Krüger, H.; Liu, J.; Pangaud, P.; Peric, I.; Rozanov, A.; Wang, A.; Wermes, N.

    2016-02-01

    The LHC Phase-II upgrade will lead to a significant increase in luminosity, which in turn will bring new challenges for the operation of inner tracking detectors. A possible solution is to use active silicon sensors, taking advantage of commercial CMOS technologies. Currently ATLAS R&D programme is qualifying a few commercial technologies in terms of suitability for this task. In this paper a prototype designed in one of them (LFoundry 150 nm process) will be discussed. The chip architecture will be described, including different pixel types incorporated into the design, followed by simulation and measurement results.

  18. Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

    NASA Astrophysics Data System (ADS)

    Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

    2014-03-01

    We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

  19. Region-of-interest cone beam computed tomography (ROI CBCT) with a high resolution CMOS detector

    PubMed Central

    Jain, A; Takemoto, H; Silver, M D; Nagesh, S V S; Ionita, C N; Bednarek, D R; Rudin, S

    2015-01-01

    Cone beam computed tomography (CBCT) systems with rotational gantries that have standard flat panel detectors (FPD) are widely used for the 3D rendering of vascular structures using Feldkamp cone beam reconstruction algorithms. One of the inherent limitations of these systems is limited resolution (<3 lp/mm). There are systems available with higher resolution but their small FOV limits them to small animal imaging only. In this work, we report on region-of-interest (ROI) CBCT with a high resolution CMOS detector (75 μm pixels, 600 μm HR-CsI) mounted with motorized detector changer on a commercial FPD-based C-arm angiography gantry (194 μm pixels, 600 μm HL-CsI). A cylindrical CT phantom and neuro stents were imaged with both detectors. For each detector a total of 209 images were acquired in a rotational protocol. The technique parameters chosen for the FPD by the imaging system were used for the CMOS detector. The anti-scatter grid was removed and the incident scatter was kept the same for both detectors with identical collimator settings. The FPD images were reconstructed for the 10 cm x10 cm FOV and the CMOS images were reconstructed for a 3.84 cm × 3.84 cm FOV. Although the reconstructed images from the CMOS detector demonstrated comparable contrast to the FPD images, the reconstructed 3D images of the neuro stent clearly showed that the CMOS detector improved delineation of smaller objects such as the stent struts (~70 μm) compared to the FPD. Further development and the potential for substantial clinical impact are suggested. PMID:26877577

  20. Region-of-interest cone beam computed tomography (ROI CBCT) with a high resolution CMOS detector

    NASA Astrophysics Data System (ADS)

    Jain, A.; Takemoto, H.; Silver, M. D.; Nagesh, S. V. S.; Ionita, C. N.; Bednarek, D. R.; Rudin, S.

    2015-03-01

    Cone beam computed tomography (CBCT) systems with rotational gantries that have standard flat panel detectors (FPD) are widely used for the 3D rendering of vascular structures using Feldkamp cone beam reconstruction algorithms. One of the inherent limitations of these systems is limited resolution (<3 lp/mm). There are systems available with higher resolution but their small FOV limits them to small animal imaging only. In this work, we report on region-of-interest (ROI) CBCT with a high resolution CMOS detector (75 μm pixels, 600 μm HR-CsI) mounted with motorized detector changer on a commercial FPD-based C-arm angiography gantry (194 μm pixels, 600 μm HL-CsI). A cylindrical CT phantom and neuro stents were imaged with both detectors. For each detector a total of 209 images were acquired in a rotational protocol. The technique parameters chosen for the FPD by the imaging system were used for the CMOS detector. The anti-scatter grid was removed and the incident scatter was kept the same for both detectors with identical collimator settings. The FPD images were reconstructed for the 10 cm x10 cm FOV and the CMOS images were reconstructed for a 3.84 cm x 3.84 cm FOV. Although the reconstructed images from the CMOS detector demonstrated comparable contrast to the FPD images, the reconstructed 3D images of the neuro stent clearly showed that the CMOS detector improved delineation of smaller objects such as the stent struts (~70 μm) compared to the FPD. Further development and the potential for substantial clinical impact are suggested.

  1. Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

    PubMed Central

    Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

    2011-01-01

    The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

  2. Faint-meteor survey with a large-format CMOS sensor

    NASA Astrophysics Data System (ADS)

    Watanabe, J.; Enomoto, T.; Terai, T.; Kasuga, T.; Miyazaki, S.; Oota, K.; Muraoka, F.; Onishi, T.; Yamasaki, T.; Mito, H.; Aoki, T.; Soyano, T.; Tarusawa, K.; Matsunaga, N.; Sako, S.; Kobayashi, N.; Doi, M.

    2014-07-01

    For observing faint meteors, we need a large telescope or similar optics, which always give a restriction of the field of view. It is a kind of trade-off between the high sensitivity by using larger telescope and narrower field of view. Reconciling this contradiction, we need a large-format imaging detector together with fast readout for meteor observations. A high-sensitivity CMOS sensor of the large format was developed by Canon Inc. in 2010[1]. Its size is 202 mm×205 mm which makes it the largest one-chip CMOS sensor in the world, and approximately 40 times the size of Canon's largest commercial CMOS sensor as shown in the figure. The number of pixel is 1280×1248. Because the increased size of the new CMOS sensor allows more light to be gathered, it enables shooting in low-light environments. The sensor makes image capture possible in one-hundredth the amount of light required by a 35 mm full-frame CMOS sensor, facilitating the shooting of 60 frame-per-second video with a mere 0.3 lux of illumination. We tried to use this large-format CMOS sensor attached to the prime focus of the 1.05-m (F3.1) Schmidt telescope at the Kiso Observatory, University of Tokyo, for surveying faint meteors. The field of view is 3.3 by 3.3 degrees. Test observations including operation check of the system were carried out in January 2011, September 2011,and December 2012. Images were obtained at a time resolution of 60 frames per second. In this system, the limiting magnitude is estimated to be about 11-12. Because of the limitation of the data storage, full-power observations (14-bit data per 1/60 second) were performed for about one or two hours each night. During the first period, we can count a sporadic meteor every 5 seconds. This is about one order higher detection rate of the faint meteors compared with the previous work[2]. Assuming the height of faint meteors at 100 km, the derived flux of the sporadic meteors is about 5 × 10^{-4} km^{-2} sec^{-1}. The last run was performed during the active period of the Geminid meteor shower. We could take valuable data on December 12 and 13. The result will be given in this presentation, together with the future potential of the large format CMOS sensor.

  3. Design of a total-dose radiation hardened monolithic CMOS DC-DC boost converter

    NASA Astrophysics Data System (ADS)

    Zhi, Liu; Hongying, Ning; Hongbo, Yu; Youbao, Liu

    2011-07-01

    This paper presents the design and implementation of a monolithic CMOS DC-DC boost converter that is hardened for total dose radiation. In order to improve its radiation tolerant abilities, circuit-level and device-level RHBD (radiation-hardening by design) techniques were employed. Adaptive slope compensation was used to improve the inherent instability. The H-gate MOS transistors, annular gate MOS transistors and guard rings were applied to reduce the impact of total ionizing dose. A boost converter was fabricated by a standard commercial 0.35 μm CMOS process. The hardened design converter can work properly in a wide range of total dose radiation environments, with increasing total dose radiation. The efficiency is not as strongly affected by the total dose radiation and so does the leakage performance.

  4. 30-Gb/s 90-nm CMOS-driven equalized multimode optical link.

    PubMed

    Hamel-Bissell, Brendan H; Proesel, Jonathan E; Lee, Benjamin G; Kuchta, Daniel M; Rylyakov, Alexander V; Schow, Clint L

    2013-05-01

    We report an 850-nm vertical cavity surface emitting laser (VCSEL)-based optical link that achieves a new record in speed. The laser driver and receiver ICs are fabricated in standard 90-nm bulk CMOS, and the optoelectronic devices are commercial components. Operation at 30 Gb/s with a bit-error rate < 10(-12) is achieved, representing to the authors' knowledge the highest speed reported to date for a CMOS-based full optical link. Transmitter feed-forward equalization is shown to improve maximum data rate from 25 to 30 Gb/s, timing margin by 17% at 23.5 Gb/s, and receiver sensitivity by 4 dB at 23.5 Gb/s. PMID:23669952

  5. A CMOS Neural Interface for a Multichannel Vestibular Prosthesis.

    PubMed

    Hageman, Kristin N; Kalayjian, Zaven K; Tejada, Francisco; Chiang, Bryce; Rahman, Mehdi A; Fridman, Gene Y; Dai, Chenkai; Pouliquen, Philippe O; Georgiou, Julio; Della Santina, Charles C; Andreou, Andreas G

    2016-04-01

    We present a high-voltage CMOS neural-interface chip for a multichannel vestibular prosthesis (MVP) that measures head motion and modulates vestibular nerve activity to restore vision- and posture-stabilizing reflexes. This application specific integrated circuit neural interface (ASIC-NI) chip was designed to work with a commercially available microcontroller, which controls the ASIC-NI via a fast parallel interface to deliver biphasic stimulation pulses with 9-bit programmable current amplitude via 16 stimulation channels. The chip was fabricated in the ONSemi C5 0.5 micron, high-voltage CMOS process and can accommodate compliance voltages up to 12 V, stimulating vestibular nerve branches using biphasic current pulses up to 1.45±0.06 mA with durations as short as 10 μs/phase. The ASIC-NI includes a dedicated digital-to-analog converter for each channel, enabling it to perform complex multipolar stimulation. The ASIC-NI replaces discrete components that cover nearly half of the 2nd generation MVP (MVP2) printed circuit board, reducing the MVP system size by 48% and power consumption by 17%. Physiological tests of the ASIC-based MVP system (MVP2A) in a rhesus monkey produced reflexive eye movement responses to prosthetic stimulation similar to those observed when using the MVP2. Sinusoidal modulation of stimulus pulse rate from 68-130 pulses per second at frequencies from 0.1 to 5 Hz elicited appropriately-directed slow phase eye velocities ranging in amplitude from 1.9-16.7 (°)/s for the MVP2 and 2.0-14.2 (°)/s for the MVP2A. The eye velocities evoked by MVP2 and MVP2A showed no significant difference ( t-test, p=0.34), suggesting that the MVP2A achieves performance at least as good as the larger MVP2. PMID:25974945

  6. A CMOS Neural Interface for a Multichannel Vestibular Prosthesis

    PubMed Central

    Hageman, Kristin N.; Kalayjian, Zaven K.; Tejada, Francisco; Chiang, Bryce; Rahman, Mehdi A.; Fridman, Gene Y.; Dai, Chenkai; Pouliquen, Philippe O.; Georgiou, Julio; Della Santina, Charles C.; Andreou, Andreas G.

    2015-01-01

    We present a high-voltage CMOS neural-interface chip for a multichannel vestibular prosthesis (MVP) that measures head motion and modulates vestibular nerve activity to restore vision- and posture-stabilizing reflexes. This application specific integrated circuit neural interface (ASIC-NI) chip was designed to work with a commercially available microcontroller, which controls the ASIC-NI via a fast parallel interface to deliver biphasic stimulation pulses with 9-bit programmable current amplitude via 16 stimulation channels. The chip was fabricated in the ONSemi C5 0.5 micron, high-voltage CMOS process and can accommodate compliance voltages up to 12 V, stimulating vestibular nerve branches using biphasic current pulses up to 1.45 ± 0.06 mA with durations as short as 10 µs/phase. The ASIC-NI includes a dedicated digital-to-analog converter for each channel, enabling it to perform complex multipolar stimulation. The ASIC-NI replaces discrete components that cover nearly half of the 2nd generation MVP (MVP2) printed circuit board, reducing the MVP system size by 48% and power consumption by 17%. Physiological tests of the ASIC-based MVP system (MVP2A) in a rhesus monkey produced reflexive eye movement responses to prosthetic stimulation similar to those observed when using the MVP2. Sinusoidal modulation of stimulus pulse rate from 68–130 pulses per second at frequencies from 0.1 to 5 Hz elicited appropriately-directed slow phase eye velocities ranging in amplitude from 1.9–16.7°/s for the MVP2 and 2.0–14.2°/s for the MVP2A. The eye velocities evoked by MVP2 and MVP2A showed no significant difference (t-test, p = 0.034), suggesting that the MVP2A achieves performance at least as good as the larger MVP2. PMID:25974945

  7. Radiation Hardening of CMOS Microelectronics

    NASA Astrophysics Data System (ADS)

    McCarthy, A.; Sigmon, T. W.

    2000-02-01

    A unique methodology, silicon transfer to arbitrary substrates, has been developed under this program and is being investigated as a technique for significantly increasing the radiation insensitivity of limited quantities of conventional silicon microelectronic circuits. In this approach, removal of the that part of the silicon substrate not required for circuit operation is carried out, following completion of the circuit fabrication process. This post-processing technique is therefore applicable to state-of-the-art ICs, effectively bypassing the 3-generation technology/performance gap presently separating today's electronics from available radiation-hard electronics. Also, of prime concern are the cost savings that result by eliminating the requirement for costly redesign of commercial circuits for Rad-hard applications. Successful deployment of this technology will result in a major impact on the radiation hard electronics community in circuit functionality, design and software availability and fabrication costs.

  8. Cmos spdt switch for wlan applications

    NASA Astrophysics Data System (ADS)

    Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

    2015-04-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

  9. Ultralow-Loss CMOS Copper Plasmonic Waveguides.

    PubMed

    Fedyanin, Dmitry Yu; Yakubovsky, Dmitry I; Kirtaev, Roman V; Volkov, Valentyn S

    2016-01-13

    Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which can outperform gold plasmonic waveguides simultaneously providing long (>40 μm) propagation length and deep subwavelength (∼λ(2)/50, where λ is the free-space wavelength) mode confinement in the telecommunication spectral range. These results create the backbone for the development of a CMOS plasmonic platform and its integration in future electronic chips. PMID:26654281

  10. Advanced CMOS Radiation Effects Testing Analysis

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, Kenneth P.; Gordon, Michael S.; LaBel, Kenneth A.; Schwank, James R.; Dodds, Nathaniel A.; Castaneda, Carlos M.; Berg, Melanie D.; Kim, Hak S.; Phan, Anthony M.; Seidleck, Christina M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  11. Advanced CMOS Radiation Effects Testing and Analysis

    NASA Technical Reports Server (NTRS)

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  12. Low-Power CMOS Digital Autocorrelator Spectrometer

    NASA Technical Reports Server (NTRS)

    Chandra, Kumar M.; Wilson, William J.

    1994-01-01

    Prototype digital autocorrelator spectrometer circuit designed and built as assembly of few very-large-scale integrated (VLSI) complementary metal oxide/semiconductor (CMOS) circuit chips. Spectrometer contains 128 frequency channels and operates at clock rate of as much as 40 MHz. Total dc power needed is only 6 W. Digital autocorrelator spectrometer consists of four 32-channel autocorrelator chips that collectively produce 128-point spectrum of input signal as computed by use of Fourier transform.

  13. CMOS Camera Array With Onboard Memory

    NASA Technical Reports Server (NTRS)

    Gat, Nahum

    2009-01-01

    A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

  14. Radiation effects on scientific CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Yuanfu, Zhao; Liyan, Liu; Xiaohui, Liu; Xiaofeng, Jin; Xiang, Li

    2015-11-01

    A systemic solution for radiation hardened design is presented. Besides, a series of experiments have been carried out on the samples, and then the photoelectric response characteristic and spectral characteristic before and after the experiments have been comprehensively analyzed. The performance of the CMOS image sensor with the radiation hardened design technique realized total-dose resilience up to 300 krad(Si) and resilience to single-event latch up for LET up to 110 MeV·cm2/mg.

  15. CMOS-controlled rapidly tunable photodetectors

    NASA Astrophysics Data System (ADS)

    Chen, Ray

    With rapidly increasing data bandwidth demands, wavelength-division-multiplexing (WDM) optical access networks seem unavoidable in the near future. To operate WDM optical networks in an efficient scheme, wavelength reconfigurability and scalability of the network are crucial. Unfortunately, most of the existing wavelength tunable technologies are neither rapidly tunable nor spectrally programmable. This dissertation presents a tunable photodetector that is designed for dynamic-wavelength allocation WDM network environments. The wavelength tuning mechanism is completely different from existing technologies. The spectrum of this detector is programmable through low-voltage digital patterns. Since the wavelength selection is achieved by electronic means, the device wavelength reconfiguration time is as fast as the electronic switching time. In this dissertation work, we have demonstrated a tunable detector that is hybridly integrated with its customized CMOS driver and receiver with nanosecond wavelength reconfiguration time. In addition to its nanosecond wavelength reconfiguration time, the spectrum of this detector is digitally programmable, which means that it can adapt to system changes without re-fabrication. We have theoretically developed and experimentally demonstrated two device operating algorithms based on the same orthogonal device-optics basis. Both the rapid wavelength tuning time and the scalability make this novel device very viable for new reconfigurable WDM networks. By taking advantage of CMOS circuit design, this detector concept can be further extended for simultaneous multiple wavelength detection. We have developed one possible chip architecture and have designed a CMOS tunable optical demux for simultaneous controllable two-wavelength detection.

  16. Behavior of faulty double BJT BiCMOS logic gates

    NASA Technical Reports Server (NTRS)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1992-01-01

    Logic Behavior of a Double BJT BiCMOS device under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS, to bring out the testability differences.

  17. Interferometric comparison of the performance of a CMOS and sCMOS detector

    NASA Astrophysics Data System (ADS)

    Flores-Moreno, J. M.; De la Torre I., Manuel H.; Hernández-Montes, M. S.; Pérez-López, Carlos; Mendoza S., Fernando

    2015-08-01

    We present an analysis of the imaging performance of two state-of-the-art sensors widely used in the nondestructive- testing area (NDT). The analysis is based on the quantification of the signal-to-noise (SNR) ratio from an optical phase image. The calculation of the SNR is based on the relation of the median (average) and standard deviation measurements over specific areas of interest in the phase images of both sensors. This retrieved phase is coming from the vibrational behavior of a large object by means of an out-of-plane holographic interferometer. The SNR is used as a figure-of-merit to evaluate and compare the performance of the CMOS and scientific CMOS (sCMOS) camera as part of the experimental set-up. One of the cameras has a high speed CMOS sensor while the other has a high resolution sCMOS sensor. The object under study is a metallically framed table with a Formica cover with an observable area of 1.1 m2. The vibration induced to the sample is performed by a linear step motor with an attached tip in the motion stage. Each camera is used once at the time to record the deformation keeping the same experimental conditions for each case. These measurements may complement the conventional procedures or technical information commonly used to evaluate a camerás performance such as: quantum efficiency, spatial resolution and others. Results present post processed images from both cameras, but showing a smoother and easy to unwrap optical phase coming from those recorded with the sCMOS camera.

  18. Fundamental performance differences of CMOS and CCD imagers: part V

    NASA Astrophysics Data System (ADS)

    Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

    2013-02-01

    Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

  19. Current-mode CMOS hybrid image sensor

    NASA Astrophysics Data System (ADS)

    Benyhesan, Mohammad Kassim

    Digital imaging is growing rapidly making Complimentary Metal-Oxide-Semi conductor (CMOS) image sensor-based cameras indispensable in many modern life devices like cell phones, surveillance devices, personal computers, and tablets. For various purposes wireless portable image systems are widely deployed in many indoor and outdoor places such as hospitals, urban areas, streets, highways, forests, mountains, and towers. However, the increased demand on high-resolution image sensors and improved processing features is expected to increase the power consumption of the CMOS sensor-based camera systems. Increased power consumption translates into a reduced battery life-time. The increased power consumption might not be a problem if there is access to a nearby charging station. On the other hand, the problem arises if the image sensor is located in widely spread areas, unfavorable to human intervention, and difficult to reach. Given the limitation of energy sources available for wireless CMOS image sensor, an energy harvesting technique presents a viable solution to extend the sensor life-time. Energy can be harvested from the sun light or the artificial light surrounding the sensor itself. In this thesis, we propose a current-mode CMOS hybrid image sensor capable of energy harvesting and image capture. The proposed sensor is based on a hybrid pixel that can be programmed to perform the task of an image sensor and the task of a solar cell to harvest energy. The basic idea is to design a pixel that can be configured to exploit its internal photodiode to perform two functions: image sensing and energy harvesting. As a proof of concept a 40 x 40 array of hybrid pixels has been designed and fabricated in a standard 0.5 microm CMOS process. Measurement results show that up to 39 microW of power can be harvested from the array under 130 Klux condition with an energy efficiency of 220 nJ /pixel /frame. The proposed image sensor is a current-mode image sensor which has several advantages over the voltage-mode. The most important advantages of using current-mode technique are: reduced power consumption of the chip, ease of arithmetic operations implementation, simplification of the circuit design and hence reduced layout complexity.

  20. Envelope tracking CMOS power amplifier with high-speed CMOS envelope amplifier for mobile handsets

    NASA Astrophysics Data System (ADS)

    Yoshida, Eiji; Sakai, Yasufumi; Oishi, Kazuaki; Yamazaki, Hiroshi; Mori, Toshihiko; Yamaura, Shinji; Suto, Kazuo; Tanaka, Tetsu

    2014-01-01

    A high-efficiency CMOS power amplifier (PA) based on envelope tracking (ET) has been reported for a wideband code division multiple access (W-CDMA) and long term evolution (LTE) application. By adopting a high-speed CMOS envelope amplifier with current direction sensing, a 5% improvement in total power-added efficiency (PAE) and a 11 dB decrease in adjacent channel leakage ratio (ACLR) are achieved with a W-CDMA signal. Moreover, the proposed PA achieves a PAE of 25.4% for a 10 MHz LTE signal at an output power (Pout) of 25.6 dBm and a gain of 24 dB.

  1. CMOS compatible on-chip decoupling capacitor based on vertically aligned carbon nanofibers

    NASA Astrophysics Data System (ADS)

    Saleem, A. M.; Göransson, G.; Desmaris, V.; Enoksson, P.

    2015-05-01

    On-chip decoupling capacitor of specific capacitance 55 pF/μm2 (footprint area) which is 10 times higher than the commercially available discrete and on-chip (65 nm technology node) decoupling capacitors is presented. The electrodes of the capacitor are based on vertically aligned carbon nanofibers (CNFs) capable of being integrated directly on CMOS chips. The carbon nanofibers employed in this study were grown on CMOS chips using direct current plasma enhanced chemical vapor deposition (DC-PECVD) technique at CMOS compatible temperature. The carbon nanofibers were grown at temperature from 390 °C to 550 °C. The capacitance of the carbon nanofibers was measured by cyclic voltammetry and thus compared. Futhermore the capacitance of decoupling capacitor was measured using different voltage scan rate to show their high charge storage capability and finally the cyclic voltammetry is run for 1000 cycles to assess their suitability as electrode material for decoupling capacitor. Our results show the high specific capacitance and long-term reliability of performance of the on-chip decoupling capacitors. Moreover, the specific capacitance shown is larger for carbon nanofibers grown at higher temperature.

  2. High-performance CMOS image sensors at BAE SYSTEMS Imaging Solutions

    NASA Astrophysics Data System (ADS)

    Vu, Paul; Fowler, Boyd; Liu, Chiao; Mims, Steve; Balicki, Janusz; Bartkovjak, Peter; Do, Hung; Li, Wang

    2012-07-01

    In this paper, we present an overview of high-performance CMOS image sensor products developed at BAE SYSTEMS Imaging Solutions designed to satisfy the increasingly challenging technical requirements for image sensors used in advanced scientific, industrial, and low light imaging applications. We discuss the design and present the test results of a family of image sensors tailored for high imaging performance and capable of delivering sub-electron readout noise, high dynamic range, low power, high frame rates, and high sensitivity. We briefly review the performance of the CIS2051, a 5.5-Mpixel image sensor, which represents our first commercial CMOS image sensor product that demonstrates the potential of our technology, then we present the performance characteristics of the CIS1021, a full HD format CMOS image sensor capable of delivering sub-electron read noise performance at 50 fps frame rate at full HD resolution. We also review the performance of the CIS1042, a 4-Mpixel image sensor which offers better than 70% QE @ 600nm combined with better than 91dB intra scene dynamic range and about 1 e- read noise at 100 fps frame rate at full resolution.

  3. Ultra-fast high-resolution hybrid and monolithic CMOS imagers in multi-frame radiography

    NASA Astrophysics Data System (ADS)

    Kwiatkowski, Kris; Douence, Vincent; Bai, Yibin; Nedrow, Paul; Mariam, Fesseha; Merrill, Frank; Morris, Christopher L.; Saunders, Andy

    2014-09-01

    A new burst-mode, 10-frame, hybrid Si-sensor/CMOS-ROIC FPA chip has been recently fabricated at Teledyne Imaging Sensors. The intended primary use of the sensor is in the multi-frame 800 MeV proton radiography at LANL. The basic part of the hybrid is a large (48×49 mm2) stitched CMOS chip of 1100×1100 pixel count, with a minimum shutter speed of 50 ns. The performance parameters of this chip are compared to the first generation 3-frame 0.5-Mpixel custom hybrid imager. The 3-frame cameras have been in continuous use for many years, in a variety of static and dynamic experiments at LANSCE. The cameras can operate with a per-frame adjustable integration time of ~ 120ns-to- 1s, and inter-frame time of 250ns to 2s. Given the 80 ms total readout time, the original and the new imagers can be externally synchronized to 0.1-to-5 Hz, 50-ns wide proton beam pulses, and record up to ~1000-frame radiographic movies typ. of 3-to-30 minute duration. The performance of the global electronic shutter is discussed and compared to that of a high-resolution commercial front-illuminated monolithic CMOS imager.

  4. Design of an ultra low power CMOS pixel sensor for a future neutron personal dosimeter

    SciTech Connect

    Zhang, Y.; Hu-Guo, C.; Husson, D.; Hu, Y.

    2011-07-01

    Despite a continuously increasing demand, neutron electronic personal dosimeters (EPDs) are still far from being completely established because their development is a very difficult task. A low-noise, ultra low power consumption CMOS pixel sensor for a future neutron personal dosimeter has been implemented in a 0.35 {mu}m CMOS technology. The prototype is composed of a pixel array for detection of charged particles, and the readout electronics is integrated on the same substrate for signal processing. The excess electrons generated by an impinging particle are collected by the pixel array. The charge collection time and the efficiency are the crucial points of a CMOS detector. The 3-D device simulations using the commercially available Synopsys-SENTAURUS package address the detailed charge collection process. Within a time of 1.9 {mu}s, about 59% electrons created by the impact particle are collected in a cluster of 4 x 4 pixels with the pixel pitch of 80 {mu}m. A charge sensitive preamplifier (CSA) and a shaper are employed in the frond-end readout. The tests with electrical signals indicate that our prototype with a total active area of 2.56 x 2.56 mm{sup 2} performs an equivalent noise charge (ENC) of less than 400 e - and 314 {mu}W power consumption, leading to a promising prototype. (authors)

  5. High responsivity CMOS imager pixel implemented in SOI technology

    NASA Technical Reports Server (NTRS)

    Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

    2000-01-01

    Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

  6. CMOS-compatible RF MEMS switch

    NASA Astrophysics Data System (ADS)

    Lakamraju, Narendra V.; Kim, Bruce; Phillips, Stephen M.

    2004-08-01

    Mobile technologies have relied on RF switches for a long time. Though the basic function of the switch has remained the same, the way they have been made has changed in the recent past. In the past few years work has been done to use MEMS technologies in designing and fabricating an RF switch that would in many ways replace the electronic and mechanical switches that have been used for so long. The work that is described here is an attempt to design and fabricate an RF MEMS switch that can handle higher RF power and have CMOS compatible operating voltages.

  7. Vertical Isolation for Photodiodes in CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2008-01-01

    In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

  8. Monolithic CMOS imaging x-ray spectrometers

    NASA Astrophysics Data System (ADS)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

    2014-07-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and spectrally resolved without saturation. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting x-ray astronomy. These features include read noise, x-ray spectral response and quantum efficiency. Funding for this work has been provided in large part by NASA Grant NNX09AE86G and a grant from the Betty and Gordon Moore Foundation.

  9. Design of high speed camera based on CMOS technology

    NASA Astrophysics Data System (ADS)

    Park, Sei-Hun; An, Jun-Sick; Oh, Tae-Seok; Kim, Il-Hwan

    2007-12-01

    The capacity of a high speed camera in taking high speed images has been evaluated using CMOS image sensors. There are 2 types of image sensors, namely, CCD and CMOS sensors. CMOS sensor consumes less power than CCD sensor and can take images more rapidly. High speed camera with built-in CMOS sensor is widely used in vehicle crash tests and airbag controls, golf training aids, and in bullet direction measurement in the military. The High Speed Camera System made in this study has the following components: CMOS image sensor that can take about 500 frames per second at a resolution of 1280*1024; FPGA and DDR2 memory that control the image sensor and save images; Camera Link Module that transmits saved data to PC; and RS-422 communication function that enables control of the camera from a PC.

  10. Radiation-hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Technology

    NASA Astrophysics Data System (ADS)

    Miucci, A.; Gonella, L.; Hemperek, T.; Hügging, F.; Krüger, H.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Backhaus, M.; Capeans, M.; Feigl, S.; Nessi, M.; Pernegger, H.; Ristic, B.; Gonzalez-Sevilla, S.; Ferrere, D.; Iacobucci, G.; La Rosa, A.; Muenstermann, D.; George, M.; Große-Knetter, J.; Quadt, A.; Rieger, J.; Weingarten, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.; Kreidl, C.; Peric, I.; Breugnon, P.; Pangaud, P.; Godiot-Basolo, S.; Fougeron, D.; Bompard, F.; Clemens, J. C.; Liu, J.; Barbero, M.; Rozanov, A.; HV-CMOS Collaboration

    2014-05-01

    Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown.

  11. A CMOS high speed imaging system design based on FPGA

    NASA Astrophysics Data System (ADS)

    Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

    2015-10-01

    CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

  12. A CMOS Amperometric System for Multi-Neurotransmitter Detection.

    PubMed

    Massicotte, Genevieve; Carrara, Sandro; Di Micheli, Giovanni; Sawan, Mohamad

    2016-06-01

    In vivo multi-target and selective concentration monitoring of neurotransmitters can help to unravel the brain chemical complex signaling interplay. This paper presents a dedicated integrated potentiostat transducer circuit and its selective electrode interface. A custom 2-electrode time-based potentiostat circuit was fabricated with 0.13 μm CMOS technology and provides a wide dynamic input current range of 20 pA to 600 nA with 56 μ W, for a minimum sampling frequency of 1.25 kHz. A multi-working electrode chip is functionalized with carbon nanotubes (CNT)-based chemical coatings that offer high sensitivity and selectivity towards electroactive dopamine and non-electroactive glutamate. The prototype was experimentally tested with different concentrations levels of both neurotransmitter types, and results were similar to measurements with a commercially available potentiostat. This paper validates the functionality of the proposed biosensor, and demonstrates its potential for the selective detection of a large number of neurochemicals. PMID:26761882

  13. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    NASA Technical Reports Server (NTRS)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  14. CMOS solid state photomultipliers for ultra-low light levels

    NASA Astrophysics Data System (ADS)

    Johnson, Erik B.; Stapels, Christopher J.; Chen, Xaio Jie; Whitney, Chad; Chapman, Eric C.; Alberghini, Guy; Rines, Rich; Augustine, Frank; Christian, James

    2011-05-01

    Detection of single photons is crucial for a number of applications. Geiger photodiodes (GPD) provide large gains with an insignificant amount of multiplication noise exclusively from the diode. When the GPD is operated above the reverse bias breakdown voltage, the diode can avalanche due to charged pairs generated from random noise (typically thermal) or incident photons. The GPD is a binary device, as only one photon is needed to trigger an avalanche, regardless of the number of incident photons. A solid-state photomultiplier (SSPM) is an array of GPDs, and the output of the SSPM is proportional to the incident light intensity, providing a replacement for photomultiplier tubes. We have developed CMOS SSPMs using a commercial fabrication process for a myriad of applications. We present results on the operation of these devices for low intensity light pulses. The data analysis provides a measured of the junction capacitance (~150 fF), which affects the rise time (~2 ns), the fall time (~32 ns), and gain (>106). Multipliers for the cross talk and after pulsing are given, and a consistent picture within the theory of operation of the expected dark current and photodetection efficiency is demonstrate. Enhancement of the detection efficiency with respect to the quantum efficiency at unity gain for shallow UV photons is measured, indicating an effect due to fringe fields within the diode structure. The signal and noise terms have been deconvolved from each other, providing the fundamental model for characterizing the behavior at low-light intensities.

  15. Real-time algorithm enabling high dynamic range imaging and high frame rate exploitation for custom CMOS image sensor system implemented by FPGA with co-processor

    NASA Astrophysics Data System (ADS)

    Jacquot, Blake C.; Johnson-Williams, Nathan

    2015-02-01

    We present results from a prototype CMOS camera system implementing a multiple sampled pixel level algorithm ("Last Sample Before Saturation") in real-time to create High-Dynamic Range (HDR) images that approach the dynamic range of CCDs. The system is built around a commercial 1280 × 1024 CMOS image sensor with 10-bits per pixel and up to 500 Hz full frame rate with higher frame rates available through windowing. We provide details of system architecture and present images collected with the system.

  16. Planar Microfluidic System Based on Electrophoresis for Detection of 130-nm Magnetic Labels for Biosensing

    NASA Astrophysics Data System (ADS)

    Takamura, Tsukasa; Morimoto, Yoshitaka; Sandhu, Adarsh

    2011-04-01

    Superparamagnetic beads (SPBs) used as magnetic labels offer potential for the realization of high sensitivity and low cost biosensors for point of care treatment (POCT). For better biomolecular affinity and higher sensitivity, it is desirable to use sub-200-nm-diameter SPBs comparable in size to actual biomolecules. However, the detection of small concentrations of such SPBs by magnetoresistive devices is extremely challenging due to small magnetic response of SPBs. As a solution to these limitations, we describe a simple detecting procedure where the capture of micro-SPBs by immobilized nano-target SPBs due to self-assembly induced by an external magnetic field, which was monitored under an optical microscope. Here we describe biosensing system based on self-assembly of micro-SPBs by nanoSPBs targets using a system without external pumps, thereby enabling greater miniaturization and portability.

  17. Scatterometry measurement method for gate CD control of sub-130nm technology

    NASA Astrophysics Data System (ADS)

    Jang, Jeongyeol; Kwak, Sungho; Lee, Karl; Kim, Keeho; Park, Heongsu; Youn, James; Sohn, Lucas

    2005-05-01

    Recently, the scatterometry is becoming more and more popular as a inline metrology tool for lithography process control as well as etching process control because of the advantage of fast measurement with high accuracy. Especially, at the gate patterning that fabricates transistors, the scatterometry can be very powerful because it gives massive volume of CD (Critical Dimension) measurement data and gate poly profile, simultaneously. Those results could help to understand and forecast the performance of transistors. In order to achieve accurate and consistent measurement results by scatterometry, the setup of stable model and library is very crucial since it has nature of indirect measurement. For example, as defining of substrate conditions, modeling range of parameters, target values and type of models, scatterometry (in this paper, we call as OCD; Optical CD) gives different results even if we use same data basis. In this paper we have shown the best practice how to optimize variables of scatterometry to get accurate and stable results. We used the OCD(Optic CD: Accent CDS200) angular scatterometry system which can rotate HeNe laser light source from -47 to +47 degree. In order to investigate the substrate dependency, various silicon wafer substrates having periodic patterned with different materials such as photoresist, BARC, poly silicon, and thermal oxide film has been used. Finally, we observed OCD has the excellent capability for inline process controllability.

  18. Impact of Spacecraft Shielding on Direct Ionization Soft Error Rates for sub-130 nm Technologies

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan A.; Xapsos, Michael A.; Stauffer, Craig A.; Jordan, Michael M.; Sanders, Anthony B.; Ladbury, Raymond L.; Oldham, Timothy R.; Marshall, Paul W.; Heidel, David F.; Rodbell, Kenneth P.

    2010-01-01

    We use ray tracing software to model various levels of spacecraft shielding complexity and energy deposition pulse height analysis to study how it affects the direct ionization soft error rate of microelectronic components in space. The analysis incorporates the galactic cosmic ray background, trapped proton, and solar heavy ion environments as well as the October 1989 and July 2000 solar particle events.

  19. Real-time reconfigurable subthreshold CMOS perceptron.

    PubMed

    Aunet, S; Oelmann, B; Norseng, P A; Berg, Y

    2008-04-01

    In this paper, a new, real-time reconfigurable perceptron circuit element is presented. A six-transistor version used as a threshold gate, having a fan-in of three, producing adequate outputs for threshold of T =1, 2 and 3 is demonstrated by chip measurements. Subthreshold operation for supply voltages in the range of 100-350 mV is shown. The circuit performs competitively with a standard static complimentary metal-oxide-semiconductor (CMOS) implementation when maximum speed and energy delay product are taken into account, when used in a ring oscillator. Functionality per transistor is, to our knowledge, the highest reported for a variety of comparable circuits not based on floating gate techniques. Statistical simulations predict probabilities for making working circuits under mismatch and process variations. The simulations, in 120-nm CMOS, also support discussions regarding lower limits to supply voltage and redundancy. A brief discussion on how the circuit may be exploited as a basic building block for future defect tolerant mixed signal circuits, as well as neural networks, exploiting redundancy, is included. PMID:18390310

  20. Modulated CMOS camera for fluorescence lifetime microscopy.

    PubMed

    Chen, Hongtao; Holst, Gerhard; Gratton, Enrico

    2015-12-01

    Widefield frequency-domain fluorescence lifetime imaging microscopy (FD-FLIM) is a fast and accurate method to measure the fluorescence lifetime of entire images. However, the complexity and high costs involved in construction of such a system limit the extensive use of this technique. PCO AG recently released the first luminescence lifetime imaging camera based on a high frequency modulated CMOS image sensor, QMFLIM2. Here we tested and provide operational procedures to calibrate the camera and to improve the accuracy using corrections necessary for image analysis. With its flexible input/output options, we are able to use a modulated laser diode or a 20 MHz pulsed white supercontinuum laser as the light source. The output of the camera consists of a stack of modulated images that can be analyzed by the SimFCS software using the phasor approach. The nonuniform system response across the image sensor must be calibrated at the pixel level. This pixel calibration is crucial and needed for every camera settings, e.g. modulation frequency and exposure time. A significant dependency of the modulation signal on the intensity was also observed and hence an additional calibration is needed for each pixel depending on the pixel intensity level. These corrections are important not only for the fundamental frequency, but also for the higher harmonics when using the pulsed supercontinuum laser. With these post data acquisition corrections, the PCO CMOS-FLIM camera can be used for various biomedical applications requiring a large frame and high speed acquisition. PMID:26500051

  1. The 1.2 micron CMOS technology

    NASA Technical Reports Server (NTRS)

    Pina, C. A.

    1985-01-01

    A set of test structures was designed using the Jet Propulsion Laboratory (JPL) test chip assembler and was used to evaluate the first CMOS-bulk foundry runs with feature sizes of 1.2 microns. In addition to the problems associated with the physical scaling of the structures, this geometry provided an additional set of problems, since the design files had to be generated in such a way as to be capable of being processed through p-well, n-well, and twin-well processing lines. This requirement meant that the files containing the geometric design rules as well as the structure design files had to produce process-insensitive designs, a requirement that does not apply to the more mature 3.0-micron CMOS feature size technology. Because of the photolithographic steps required with this feature size, the maximum allowable chip size was 10 x 10 mm, and this chip was divided into 24 project areas, with each area being 1.6 x 1.6 mm in size. The JPL-designed structures occupied 13 out of the 21 allowable project sizes and provided the only test information obtained from these three preliminary runs. The structures were used to successfully evaluate three different manufacturing runs through two separate foundries.

  2. Challenges of nickel silicidation in CMOS technologies

    SciTech Connect

    Breil, Nicolas; Lavoie, Christian; Ozcan, Ahmet; Baumann, Frieder; Klymko, Nancy; Nummy, Karen; Sun, Bing; Jordan-Sweet, Jean; Yu, Jian; Zhu, Frank; Narasimha, Shreesh; Chudzik, Michael

    2015-04-01

    In our paper, we review some of the key challenges associated with the Ni silicidation process in the most recent CMOS technologies. The introduction of new materials (e.g.SiGe), and of non-planar architectures bring some important changes that require fundamental investigation from a material engineering perspective. Following a discussion of the device architecture and silicide evolution through the last CMOS generations, we focus our study on a very peculiar defect, termed NiSi-Fangs. We describe a mechanism for the defect formation, and present a detailed material analysis that supports this mechanism. We highlight some of the possible metal enrichment processes of the nickel monosilicide such as oxidation or various RIE (Reactive Ion Etching) plasma process, leading to a metal source available for defect formation. Furthermore, we investigate the NiSi formation and re-formation silicidation differences between Si and SiGe materials, and between (1 0 0) and (1 1 1) orientations. Finally, we show that the thermal budgets post silicidation can lead to the formation of NiSi-Fangs if the structure and the processes are not optimized. Beyond the understanding of the defect and the discussion on the engineering solutions used to prevent its formation, the interest of this investigation also lies in the fundamental learning within the Ni–Pt–Si–Ge system and some additional perspective on Ni-based contacts to advanced microelectronic devices.

  3. Ink-Jet Printed CMOS Electronics from Oxide Semiconductors.

    PubMed

    Garlapati, Suresh Kumar; Baby, Tessy Theres; Dehm, Simone; Hammad, Mohammed; Chakravadhanula, Venkata Sai Kiran; Kruk, Robert; Hahn, Horst; Dasgupta, Subho

    2015-08-01

    Complementary metal oxide semiconductor (CMOS) technology with high transconductance and signal gain is mandatory for practicable digital/analog logic electronics. However, high performance all-oxide CMOS logics are scarcely reported in the literature; specifically, not at all for solution-processed/printed transistors. As a major step toward solution-processed all-oxide electronics, here it is shown that using a highly efficient electrolyte-gating approach one can obtain printed and low-voltage operated oxide CMOS logics with high signal gain (≈21 at a supply voltage of only 1.5 V) and low static power dissipation. PMID:25867029

  4. Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

    2008-01-01

    Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

  5. A novel spiral CMOS compatible micromachined thermoelectric IR microsensor

    NASA Astrophysics Data System (ADS)

    Socher, E.; Bochobza-Degani, O.; Nemirovsky, Y.

    2001-09-01

    A novel sensing structure and realization method is proposed for complementary metal-oxide semiconductor (CMOS) compatible thermoelectric uncooled infrared microsensors. The structure enables high sensitivity and excellent thermal isolation in sensor pixels with small dimensions suitable for two-dimensional thermal imaging. Front-side dry micromachining allows fast CMOS post-processing, small pixel pitch and integration with on-chip CMOS readout. Prototype sensors with an area of 70×70 µm2 achieved a measured noise equivalent power of 0.36 nW Hz-1/2 and a response time of 3 ms.

  6. An electrostatic CMOS/BiCMOS Lithium ion vibration-based harvester-charger IC

    NASA Astrophysics Data System (ADS)

    Torres, Erick Omar

    Self-powered microsystems, such as wireless transceiver microsensors, appeal to an expanding application space in monitoring, control, and diagnosis for commercial, industrial, military, space, and biomedical products. As these devices continue to shrink, their microscale dimensions allow them to be unobtrusive and economical, with the potential to operate from typically unreachable environments and, in wireless network applications, deploy numerous distributed sensing nodes simultaneously. Extended operational life, however, is difficult to achieve since their limited volume space constrains the stored energy available, even with state-of-the-art technologies, such as thin-film lithium-ion batteries (Li Ion) and micro-fuel cells. Harvesting ambient energy overcomes this deficit by continually replenishing the energy reservoir and, as a result, indefinitely extending system lifetime. In this work, an electrostatic harvester that harnesses ambient kinetic energy from vibrations to charge an energy-storage device (e.g., a battery) is investigated, developed, and evaluated. The proposed harvester charges and holds the voltage across a vibration-sensitive variable capacitor so that vibrations can induce it to generate current into the battery when capacitance decreases (as its plates separate). The challenge is that energy is harnessed at relatively slow rates, producing low output power, and the electronics required to transfer it to charge a battery can easily demand more than the power produced. To this end, the system reduces losses by time-managing and biasing its circuits to operate only when needed and with just enough energy while charging the capacitor through an efficient quasi-lossless inductor-based precharger. As result, the proposed energy harvester stores a net energy gain in the battery during every vibration cycle. Two energy-harvesting integrated circuits (IC) were analyzed, designed, developed, and validated using a 0.7-im BiCMOS process and a 30-Hz mechanical variable capacitor. The precharger, harvester, monitoring, and control microelectronics of the first prototype draw sufficient power to operate and at the same time produce experimentally 1.27, 2.14, and 2.87 nJ per vibration cycle for battery voltages at 2.7, 3.5, and 4.2 V, which with 30-Hz vibrations produce 38.1, 64.2, and 86.1 nW. By incorporating into the system a self-tuning loop that adapts optimally the inductor-based precharger to varying battery voltages, the second prototype harnessed and gained 1.93, 2.43, and 3.89 nJ per vibration cycle at battery voltages 2.7, 3.5, and 4.2 V, generating 57.89, 73.02, and 116.55 nW at 30 Hz. The harvester ultimately charges from 2.7 to 4.2 V a 1-muF capacitor (which emulates a small thin-film Li Ion) in approximately 69 s, harnessing in the same length of time 47.9% more energy than with a non-adapting harvester.

  7. Advances in CMOS Solid-state Photomultipliers for Scintillation Detector Applications

    PubMed Central

    Christian, James F.; Stapels, Christopher J.; Johnson, Erik B.; McClish, Mickel; Dokhale, Purushotthom; Shah, Kanai S.; Mukhopadhyay, Sharmistha; Chapman, Eric; Augustine, Frank L.

    2014-01-01

    Solid-state photomultipliers (SSPMs) are a compact, lightweight, potentially low-cost alternative to a photomultiplier tube for a variety of scintillation detector applications, including digital-dosimeter and medical-imaging applications. Manufacturing SSPMs with a commercial CMOS process provides the ability for rapid prototyping, and facilitates production to reduce the cost. RMD designs CMOS SSPM devices that are fabricated by commercial foundries. This work describes the characterization and performance of these devices for scintillation detector applications. This work also describes the terms contributing to device noise in terms of the excess noise of the SSPM, the binomial statistics governing the number of pixels triggered by a scintillation event, and the background, or thermal, count rate. The fluctuations associated with these terms limit the resolution of the signal pulse amplitude. We explore the use of pixel-level signal conditioning, and characterize the performance of a prototype SSPM device that preserves the digital nature of the signal. In addition, we explore designs of position-sensitive SSPM detectors for medical imaging applications, and characterize their performance. PMID:25540471

  8. Latchup in CMOS devices from heavy ions

    NASA Technical Reports Server (NTRS)

    Soliman, K.; Nichols, D. K.

    1983-01-01

    It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

  9. CMOS digital pixel sensors: technology and applications

    NASA Astrophysics Data System (ADS)

    Skorka, Orit; Joseph, Dileepan

    2014-04-01

    CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

  10. CMOS imager for pointing and tracking applications

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

    2006-01-01

    Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

  11. CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

    NASA Technical Reports Server (NTRS)

    Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

    2006-01-01

    This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

  12. A safety monitoring system for taxi based on CMOS imager

    NASA Astrophysics Data System (ADS)

    Liu, Zhi

    2005-01-01

    CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

  13. Formal specification of a high speed CMOS correlator

    NASA Technical Reports Server (NTRS)

    Windley, P. J.

    1991-01-01

    The formal specification of a high speed CMOS correlator is presented. The specification gives the high-level behavior of the correlator and provides a clear, unambiguous description of the high-level architecture of the device.

  14. Implementation of CMOS Millimeter-Wave Devices for Rotational Spectroscopy

    NASA Astrophysics Data System (ADS)

    Drouin, Brian; Tang, Adrian; Schlecht, Erich T.; Daly, Adam M.; Brageot, Emily; Gu, Qun Jane; Ye, Yu; Shu, Ran; Chang, M.-C. Frank; Kim, Rod M.

    2015-06-01

    The extension of radio-frequency CMOS circuitry into millimeter wavelengths promises the extension of spectroscopic techniques in compact, power efficient systems. We are now exploring the use of CMOS millimeter devices for low-mass, low-power instrumentation capable of remote or in-situ detection of gas composition during space missions. This effort focuses on the development of a semi-confocal Fabry-Perot cavity with mm-wavelength CMOS transmitter and receiver attached directly to a cavity coupler. Placement of the devices within the cavity structure bypasses problems encountered with signal injection and extraction in traditional cavity designs and simultaneously takes full advantage of the miniaturized form of the CMOS hardware. The presentation will provide an overview of the project and details of the accomplishments thus far, including the development and testing of a pulse modulated 83-98 GHz transmitter.

  15. CMOS Image Sensors: Electronic Camera On A Chip

    NASA Technical Reports Server (NTRS)

    Fossum, E. R.

    1995-01-01

    Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

  16. An advanced, radiation hardened bulk CMOS/LSI technology

    NASA Technical Reports Server (NTRS)

    Schroeder, J. E.; Lichtel, R. L.; Gingerich, B. L.

    1981-01-01

    An advanced, second generation, bulk, Si-gate CMOS process is described. This process is capable of producing LSI and VLSI parts that are latch-up free and hardened to total dose levels in excess of 2 x 10 to the 5th rad-Si for applications in space and weapons radiation environments. Two memories designed to use this process are also described. Both circuits are 4096-bit, static CMOS RAMs.

  17. Delta Doping High Purity CCDs and CMOS for LSST

    NASA Technical Reports Server (NTRS)

    Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

    2006-01-01

    A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

  18. Advancement of CMOS Doping Technology in an External Development Framework

    NASA Astrophysics Data System (ADS)

    Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

    2011-01-01

    The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

  19. Integration of complex optical functionality in a production CMOS process

    NASA Astrophysics Data System (ADS)

    Gunn, Lawrence C., III

    Optical functionality has been developed within the confines of an existing CMOS process. As of this writing, 10Gigabit modulators, electrically tunable optical filters, waveguides, and grating coupler technology have been successfully implemented alongside the existing transistors in the Freescale Hip7SOI process. This technology will be used to manufacture high bandwidth optical interconnections directly on silicon chips, allowing a new type of network and computing infrastructure to be developed. This work is covered in two distinct phases. First, the exploratory work done to gain experience with high index contrast silicon waveguides primarily served to uncover challenges related with simulation of these devices, and with the practical limitations of efficiently coupling the resulting waveguide devices with the outside world. The second phase began as the grating coupler emerged to address the coupling challenge. It became feasible to conceive of a commercially viable technology based on silicon photonics. The coupler has been evolved to a high level, currently achieving coupling loss of less than 1dB. Once the light is on chip, filtering and modulation technology are implemented. The reverse-biased plasma dispersion modulator has a 3dB roll-off of 10GHz, and an insertion loss less than 5dB. Optical filters based on ring resonators, arrayed waveguide gratings, and interleavers have all been implemented, often with world record performance, and many of the devices have been made electronically tunable to compensate for manufacturing variations and environmental excursions. Finally, circuitry has been designed and constructed on the same die with the optical functionality, fully demonstrating the ability to achieve monolithic integration of these devices.

  20. CMOS Hybrid Pixel Detectors for Scientific, Industrial and Medical Applications

    NASA Astrophysics Data System (ADS)

    Broennimann, Christian

    2009-03-01

    Crystallography is the principal technique for determining macromolecular structures at atomic resolution and uses advantageously the high intensity of 3rd generation synchrotron X-ray sources . Macromolecular crystallography experiments benefit from excellent beamline equipment, recent software advances and modern X-ray detectors. However, the latter do not take full advantage of the brightness of modern synchrotron sources. CMOS Hybrid pixel array detectors, originally developed for high energy physics experiments, meet these requirements. X-rays are recorded in single photon counting mode and data thus are stored digitally at the earliest possible stage. This architecture leads to several advantages over current detectors: No detector noise is added to the signal. Readout time is reduced to a few milliseconds. The counting rates are matched to beam intensities at protein crystallography beamlines at 3rd generation synchrotrons. The detector is not sensitive to X-rays during readout; therefore no mechanical shutter is required. The detector has a very sharp point spread function (PSF) of one pixel, which allows better resolution of adjacent reflections. Low energy X-rays can be suppressed by the comparator At the Paul Scherrer Institute (PSI) in Switzerland the first and largest array based on this technology was constructed: The Pilatus 6M detector. The detector covers an area of 43.1 x 44.8 cm2 , has 6 million pixels and is read out noise free in 3.7 ms. Since June 2007 the detector is in routine operation at the beamline 6S of the Swiss Light Source (SLS). The company DETCRIS Ltd, has licensed the technology from PSI and is commercially offering the PILATUS detectors. Examples of the wide application range of the detectors will be shown.

  1. Multiband CMOS sensor simplify FPA design

    NASA Astrophysics Data System (ADS)

    Wang, Weng Lyang B.; Ling, Jer

    2015-10-01

    Push broom multi-band Focal Plane Array (FPA) design needs to consider optics, image sensor, electronic, mechanic as well as thermal. Conventional FPA use two or several CCD device as an image sensor. The CCD image sensor requires several high speed, high voltage and high current clock drivers as well as analog video processors to support their operation. Signal needs to digitize using external sample / hold and digitized circuit. These support circuits are bulky, consume a lot of power, must be shielded and placed in close to the CCD to minimize the introduction of unwanted noise. The CCD also needs to consider how to dissipate power. The end result is a very complicated FPA and hard to make due to more weighs and draws more power requiring complex heat transfer mechanisms. In this paper, we integrate microelectronic technology and multi-layer soft / hard Printed Circuit Board (PCB) technology to design electronic portion. Since its simplicity and integration, the optics, mechanic, structure and thermal design will become very simple. The whole FPA assembly and dis-assembly reduced to a few days. A multi-band CMOS Sensor (dedicated as C468) was used for this design. The CMOS Sensor, allow for the incorporation of clock drivers, timing generators, signal processing and digitization onto the same Integrated Circuit (IC) as the image sensor arrays. This keeps noise to a minimum while providing high functionality at reasonable power levels. The C468 is a first Multiple System-On-Chip (MSOC) IC. This device used our proprietary wafer butting technology and MSOC technology to combine five long sensor arrays into a size of 120 mm x 23.2 mm and 155 mm x 60 mm for chip and package, respectively. The device composed of one Panchromatic (PAN) and four different Multi- Spectral (MS) sensors. Due to its integration on the electronic design, a lot of room is clear for the thermal design. The optical and mechanical design is become very straight forward. The flight model FPA passed all of the reliability testing.

  2. Multichannel lens-free CMOS sensors for real-time monitoring of cell growth.

    PubMed

    Chang, Ko-Tung; Chang, Yu-Jen; Chen, Chia-Ling; Wang, Yao-Nan

    2015-02-01

    A low-cost platform is proposed for the growth and real-time monitoring of biological cells. The main components of the platform include a PMMA cell culture microchip and a multichannel lens-free CMOS (complementary metal-oxide-semiconductor) / LED imaging system. The PMMA microchip comprises a three-layer structure and is fabricated using a low-cost CO2 laser ablation technique. The CMOS / LED monitoring system is controlled using a self-written LabVIEW program. The platform has overall dimensions of just 130 × 104 × 115 mm(3) and can therefore be placed within a commercial incubator. The feasibility of the proposed system is demonstrated using HepG2 cancer cell samples with concentrations of 5000, 10 000, 20 000, and 40 000 cells/mL. In addition, cell cytotoxicity tests are performed using 8, 16, and 32 mM cyclophosphamide. For all of the experiments, the cell growth is observed over a period of 48 h. The cell growth rate is found to vary in the range of 44∼52% under normal conditions and from 17.4∼34.5% under cyclophosphamide-treated conditions. In general, the results confirm the long-term cell growth and real-time monitoring ability of the proposed system. Moreover, the magnification provided by the lens-free CMOS / LED observation system is around 40× that provided by a traditional microscope. Consequently, the proposed system has significant potential for long-term cell proliferation and cytotoxicity evaluation investigations. PMID:25224658

  3. A CMOS wireless biomolecular sensing system-on-chip based on polysilicon nanowire technology.

    PubMed

    Huang, C-W; Huang, Y-J; Yen, P-W; Tsai, H-H; Liao, H-H; Juang, Y-Z; Lu, S-S; Lin, C-T

    2013-11-21

    As developments of modern societies, an on-field and personalized diagnosis has become important for disease prevention and proper treatment. To address this need, in this work, a polysilicon nanowire (poly-Si NW) based biosensor system-on-chip (bio-SSoC) is designed and fabricated by a 0.35 μm 2-Poly-4-Metal (2P4M) complementary metal-oxide-semiconductor (CMOS) process provided by a commercialized semiconductor foundry. Because of the advantages of CMOS system-on-chip (SoC) technologies, the poly-Si NW biosensor is integrated with a chopper differential-difference amplifier (DDA) based analog-front-end (AFE), a successive approximation analog-to-digital converter (SAR ADC), and a microcontroller to have better sensing capabilities than a traditional Si NW discrete measuring system. In addition, an on-off key (OOK) wireless transceiver is also integrated to form a wireless bio-SSoC technology. This is pioneering work to harness the momentum of CMOS integrated technology into emerging bio-diagnosis technologies. This integrated technology is experimentally examined to have a label-free and low-concentration biomolecular detection for both Hepatitis B Virus DNA (10 fM) and cardiac troponin I protein (3.2 pM). Based on this work, the implemented wireless bio-SSoC has demonstrated a good biomolecular sensing characteristic and a potential for low-cost and mobile applications. As a consequence, this developed technology can be a promising candidate for on-field and personalized applications in biomedical diagnosis. PMID:24080725

  4. CMOS compatible micro-scintillators for wireless multi-species radiation detection and tracking

    NASA Astrophysics Data System (ADS)

    Waguespack, Randy; Wilson, Chester G.

    2010-04-01

    This paper reports on an integrated system of wirelessly linked radiation detectors that are sensitive to alpha, beta, gamma, and neutron radiation. The detectors use glass and quartz doped with 10B nanoparticles to detect impinging radiation producing varying optical pulses which exit the material. The varying optical pulses are differentiated by onchip pulse height spectroscopy. Signal discrimination is done with on-chip CMOS circuitry using a 0.35 μm process and a photodiode or photo-multiplier (PM) tube. On-chip CMOS interfacing is key to the production of small integrated radiation detection packages that are cheaper, more reliable, and easier to produce than assembled devices that use commercial off-the-shelf parts. CMOS packages are designed for low power consumption with maximum battery life; this lends itself to creating small, hard to detect radiation sensor packages that are easy to integrate with wireless sensor nodes. The network would use a mesh configuration and transmit real time radiation information from each node to a local hub. As a radiation source enters the coverage area, the data from sensors in the immediate area is transmitted and compared to find the location of the source. Pinpointing the source is achieved by comparing data received from each node. Radiation testing was done using 241Am, 90Sr, and 60Co sources for alpha, beta, and gamma particles. Initial results show that quartz and glass scintillators doped with boron are able to detect each form of radiation. The quartz scintillator is also able to detect neutron radiation particles, which being neutral, are undetected with traditional solid state radiation detectors.

  5. Simulation of SEU transients in CMOS ICs

    SciTech Connect

    Kaul, N.; Bhuva, B.L.; Kerns, S.E. )

    1991-12-01

    This paper reports that available analytical models of the number of single-event-induced errors (SEU) in combinational logic systems are not easily applicable to real integrated circuits (ICs). An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combinational logic circuits to SEU. SITA is described in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used to estimate the probability that ion-device interactions produce erroneous signals capable of propagating to a latch (or n output node), and logic-level simulation to predict the spread of such erroneous, latched information through the IC. Simulation results are compared to those from SPICE for several circuit and logic configurations. SITA results are comparable to this established circuit-level code, and SITA can analyze circuits with state-of-the-art device densities (which SPICE cannot). At all IC complexity levels, SITAS offers several factors of 10 savings in simulation time over SPICE.

  6. NSC 800, 8-bit CMOS microprocessor

    NASA Technical Reports Server (NTRS)

    Suszko, S. F.

    1984-01-01

    The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

  7. Space Commercialization

    NASA Technical Reports Server (NTRS)

    Martin, Gary L.

    2011-01-01

    A robust and competitive commercial space sector is vital to continued progress in space. The United States is committed to encouraging and facilitating the growth of a U.S. commercial space sector that supports U.S. needs, is globally competitive, and advances U.S. leadership in the generation of new markets and innovation-driven entrepreneurship. Energize competitive domestic industries to participate in global markets and advance the development of: satellite manufacturing; satellite-based services; space launch; terrestrial applications; and increased entrepreneurship. Purchase and use commercial space capabilities and services to the maximum practical extent Actively explore the use of inventive, nontraditional arrangements for acquiring commercial space goods and services to meet United States Government requirements, including measures such as public-private partnerships, . Refrain from conducting United States Government space activities that preclude, discourage, or compete with U.S. commercial space activities. Pursue potential opportunities for transferring routine, operational space functions to the commercial space sector where beneficial and cost-effective.

  8. Depleted Monolithic Active Pixel Sensors (DMAPS) implemented in LF-150 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Kishishita, T.; Hemperek, T.; Krüger, H.; Wermes, N.

    2015-03-01

    We present the recent development of Depleted Monolithic Active Pixel Sensors (DMAPS), implemented with an LFoundry (LF) 150 nm CMOS process. MAPS detectors based on an epi-layer have been matured in recent years and have attractive features in terms of reducing material budget and handling cost compared to conventional hybrid pixel detectors. However, the obtained signal is relatively small (~1000 e-) due to the thin epi-layer, and charge collection time is relatively slow, e.g., in the order of 100 ns, because charges are mainly collected by diffusion. Modern commercial CMOS technology, however, offers advanced process options to overcome such difficulties and enable truly monolithic devices as an alternative to hybrid pixel sensors and charge coupled devices. Unlike in the case of the standard MAPS technologies with epi-layers, the LF process provides a high-resistivity substrate that enables large signal and fast charge collection by drift in a ~50 μm thick depleted layer. Since this process also enables the use of deep n- and p-wells to isolate the collection electrode from the thin active device layer, PMOS and NMOS transistors are available for the readout electronics in each pixel cell. In order to evaluate the sensor and transistor characteristics, several collection electrodes variants and readout architectures have been implemented. In this report, we focus on its design aspect of the LF-DMAPS prototype chip.

  9. Development of a CMOS MEMS pressure sensor with a mechanical force-displacement transduction structure

    NASA Astrophysics Data System (ADS)

    Cheng, Chao-Lin; Chang, Heng-Chung; Chang, Chun-I.; Fang, Weileun

    2015-12-01

    This study presents a capacitive pressure sensor with a mechanical force-displacement transduction structure based on the commercially available standard CMOS process (the TSMC 0.18 μm 1P6M CMOS process). The pressure sensor has a deformable diaphragm to support a movable plate with an embedded sensing electrode. As the diaphragm is deformed by the ambient pressure, the movable plate and its embedded sensing electrode are displaced. Thus, the pressure is detected from the capacitance change between the movable and fixed electrodes. The undeformed movable electrode will increase the effective sensing area between the sensing electrodes, thereby improving the sensitivity. Experimental results show that the proposed pressure sensor with a force-displacement transducer will increase the sensitivity by 126% within the 20 kPa-300 kPa absolute pressure range. Moreover, this study extends the design to add pillars inside the pressure sensor to further increase its sensing area as well as sensitivity. A sensitivity improvement of 117% is also demonstrated for a pressure sensor with an enlarged sensing electrode (the overlap area is increased two fold).

  10. Improved Space Object Observation Techniques Using CMOS Detectors

    NASA Astrophysics Data System (ADS)

    Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

    2013-08-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

  11. CMOS Cell Sensors for Point-of-Care Diagnostics

    PubMed Central

    Adiguzel, Yekbun; Kulah, Haluk

    2012-01-01

    The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

  12. CMOS APS imaging system application in star tracker

    NASA Astrophysics Data System (ADS)

    Li, Jie; Liu, Jinguo; Li, Xuekui; Liu, Yaxia; Hao, Zhihang

    2005-01-01

    Small satellites are capable of performing space explore missions that require accurate attitude determination and control. However, low weight, size, power and cost requirements limit the types of attitude sensor of small craft, such as CCD, are not practical for small satellites. CMOS APS is a good substitute for attitude sensors of small craft. Some of the technical advantages of CMOS APS are no blooming, single power, low power consumption, small size and little support circuitry, direct digital output, simple to system design, in particular, radiation-hard characteristic compare with CCD. This paper discusses the application probability of CMOS APS in star tracker for small satellites, further more, a prototype ground-based star camera based on STAR250 CMOS image sensor has been built. In order to extract stars positions coordinates, subpixel accuracy centroiding algorithm has been developed and tested on some ground-based images. Moreover, the camera system star sensitivity and noise model are analyzed, and the system accuracy is been evaluated. Experimental results indicate that a star camera based on CMOS APS is a viable practical attitude sensor appropriate for space small satellites.

  13. High-speed CMOS optical communication using silicon light emitters

    NASA Astrophysics Data System (ADS)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Nell, Ilse J.; Bogalecki, Alfons W.; Rademeyer, Pieter

    2011-01-01

    The idea of moving CMOS into the mainstream optical domain remains an attractive one. In this paper we discuss our recent advances towards a complete silicon optical communication solution. We prove that transmission of baseband data at multiples of megabits per second rates are possible using improved silicon light sources in a completely native standard CMOS process with no post processing. The CMOS die is aligned to a fiber end and the light sources are directly modulated. An optical signal is generated and transmitted to a silicon Avalanche Photodiode (APD) module, received and recovered. Signal detectability is proven through eye diagram measurements. The results show an improvement of more than tenfold over our previous results, also demonstrating the fastest optical communication from standard CMOS light sources. This paper presents an all silicon optical data link capable of 2 Mb/s at a bit error rate of 10-10, or alternatively 1 Mb/s at a bit error rate of 10-14. As the devices are not operating at their intrinsic switching speed limit, we believe that even higher transmission rates are possible with complete integration of all components in CMOS.

  14. Figures of merit for CMOS SPADs and arrays

    NASA Astrophysics Data System (ADS)

    Bronzi, D.; Villa, F.; Bellisai, S.; Tisa, S.; Ripamonti, G.; Tosi, A.

    2013-05-01

    SPADs (Single Photon Avalanche Diodes) are emerging as most suitable photodetectors for both single-photon counting (Fluorescence Correlation Spectroscopy, Lock-in 3D Ranging) and single-photon timing (Lidar, Fluorescence Lifetime Imaging, Diffuse Optical Imaging) applications. Different complementary metal-oxide semiconductor (CMOS) implementations have been reported in literature. We present some figure of merit able to summarize the typical SPAD performances (i.e. Dark Counting Rate, Photo Detection Efficiency, afterpulsing probability, hold-off time, timing jitter) and to identify a proper metric for SPAD comparison, both as single detectors and also as imaging arrays. The goal is to define a practical framework within which it is possible to rank detectors based on their performances in specific experimental conditions, for either photon-counting or photon-timing applications. Furthermore we review the performances of some CMOS and custom-made SPADs. Results show that CMOS SPADs performances improve as the technology scales down; moreover, miniaturization of SPADs and new solutions adopted to counteract issues related with the SPAD design (electric field uniformity, premature edge breakdown, tunneling effects, defect-rich STI interface) along with advances in standard CMOS processes led to a general improvement in all fabricated photodetectors; therefore, CMOS SPADs can be suitable for very dense and cost-effective many-pixels imagers with high performances.

  15. Radiation tolerant back biased CMOS VLSI

    NASA Technical Reports Server (NTRS)

    Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

    2003-01-01

    A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

  16. VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

    NASA Astrophysics Data System (ADS)

    Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

    2014-10-01

    This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

  17. Design of CMOS logic gates for TID radiation

    NASA Astrophysics Data System (ADS)

    Attia, John Okyere; Sasabo, Maria L.

    The rise time, fall time and propagation delay of the logic gates were derived. The effects of total ionizing dose (TID) radiation on the fall and rise times of CMOS logic gates were obtained using C program calculations and PSPICE simulations. The variations of mobility and threshold voltage on MOSFET transistors when subjected to TID radiation were used to determine the dependence of switching times on TID. The results of this work indicate that by increasing the size of P-channel transistor with respect to the N-channel transistors of the CMOS gates, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in TID radiation.

  18. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    PubMed Central

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  19. A CMOS image sensor method of focal spot size measurement.

    PubMed

    Tuchyna, T; Paix, D

    2004-06-01

    A phosphor opto-coupled monochrome CMOS image sensor with a slit diaphragm was used to investigate focal spot characteristics. Images were captured during x-ray exposure with a triggered frame grabber and subsequently enhanced. Dimensions of the focal spot width (1.39mm) and length (1.92mm) were determined from the focal spot intensity profiles and their corresponding Full Width at Half Maxima (FWHM) in two orthogonal orientations. The CMOS image sensor measurements demonstrated differences in the measured width and length dimensions when compared to film measurements. The obtained nominal focal spot values however showed that image-sensor determined focal spot dimensions agreed with the direct film and film-screen methods when based on the AS/NZS defined nominal focal spot values. The CMOS image sensor tested appears to lack the measurement accuracy required for the measurement of small focal spot sizes due in part to its limited camera sensitivity. PMID:15462588

  20. A hybrid CMOS-microfluidic contact imaging microsystem

    NASA Astrophysics Data System (ADS)

    Singh, Ritu Raj; Leng, Lian; Guenther, Axel; Genov, Roman

    2009-08-01

    A hybrid CMOS/Microfluidic microsystem is presented. The microsystem integrates a soft polymer microfluidic network with a 64x128 pixel imager fabricated in low-cost standard 0.35 micron CMOS technology. The multiple microfluidic channels facilitate in-situ photochemical reactions of analytes and their detection directly on the surface of the CMOS photosensor array. The promixity between the analyte and the photosensor enhances the microsystem sensitivity, thus requiring only microliter volumes of the sample. Circuit techniques such as pixel binning and a two transistor reset path technique are employed to improve the imager sensitivity. The integrated microsystem is validated in on-chip chemiluminescence detection of luminol for the two microfluidic network prototypes designed.

  1. IGBT scaling principle toward CMOS compatible wafer processes

    NASA Astrophysics Data System (ADS)

    Tanaka, Masahiro; Omura, Ichiro

    2013-02-01

    A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed "Structure Oriented" analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies.

  2. Design of CMOS logic gates for TID radiation

    NASA Technical Reports Server (NTRS)

    Attia, John Okyere; Sasabo, Maria L.

    1993-01-01

    The rise time, fall time and propagation delay of the logic gates were derived. The effects of total ionizing dose (TID) radiation on the fall and rise times of CMOS logic gates were obtained using C program calculations and PSPICE simulations. The variations of mobility and threshold voltage on MOSFET transistors when subjected to TID radiation were used to determine the dependence of switching times on TID. The results of this work indicate that by increasing the size of P-channel transistor with respect to the N-channel transistors of the CMOS gates, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in TID radiation.

  3. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-07

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint... complaint entitled Certain CMOS Image Sensors and Products Containing Same, DN 2895; the Commission is... importation of certain CMOS image sensors and products containing same. The complaint names as...

  4. A CMOS image sensor using floating capacitor load readout operation

    NASA Astrophysics Data System (ADS)

    Wakashima, S.; Goda, Y.; Li, T. L.; Kuroda, R.; Sugawa, S.

    2013-02-01

    In this paper, a CMOS image sensor using floating capacitor load readout operation has been discussed. The floating capacitor load readout operation is used during pixel signals readout. And this operation has two features: 1. in-pixel driver transistor drives load capacitor without current sources, 2. parasitic capacitor of pixel output vertical signal line is used as a sample/hold capacitor. This operation produces three advantages: a smaller chip size, a lower power consumption, and a lower output noise than conventional CMOS image sensors. The prototype CMOS image sensor has been produced using 0.18 μm 1-Poly 3-Metal CMOS process technology with pinned photodiodes. The chip size is 2.5 mmH x 2.5 mmV, the pixel size is 4.5 μmH x 4.5 μmV, and the number of pixels is 400H x 300V. This image sensor consists of only a pixel array, vertical and horizontal shift registers, column source followers of which height is as low as that of some pixels and output buffers. The size of peripheral circuit is reduced by 90.2 % of a conventional CMOS image sensor. The power consumption in pixel array is reduced by 96.9 %. Even if the power consumption of column source follower is included, it reduced by 39.0 %. With an introduction of buried channel transistors as in-pixel driver transistors, the dark random noise of pixels of the floating capacitor load readout operation CMOS image sensor is 168 μVrms. The noise of conventional image sensor is 466 μVrms therefore, reduction of 63.8 % of noise was achieved.

  5. Design Considerations for CMOS-Integrated Hall-Effect Magnetic Bead Detectors for Biosensor Applications

    PubMed Central

    Skucha, K.; Gambini, S.; Liu, P.; Megens, M.; Kim, J.; Boser, BE

    2014-01-01

    We describe a design methodology for on-chip magnetic bead label detectors based on Hall-effect sensors. Signal errors caused by the label-binding process and other factors that limit the minimum detection area are quantified and adjusted to meet typical assay accuracy standards. The methodology is demonstrated by designing an 8192 element Hall sensor array, implemented in a commercial 0.18 μm CMOS process with single-mask postprocessing. The array can quantify a 1% surface coverage of 2.8 μm beads in 30 seconds with a coefficient of variation of 7.4%. This combination of accuracy and speed makes this technology a suitable detection platform for biological assays based on magnetic bead labels. PMID:25031503

  6. Design Considerations for CMOS-Integrated Hall-Effect Magnetic Bead Detectors for Biosensor Applications.

    PubMed

    Skucha, K; Gambini, S; Liu, P; Megens, M; Kim, J; Boser, Be

    2013-06-01

    We describe a design methodology for on-chip magnetic bead label detectors based on Hall-effect sensors. Signal errors caused by the label-binding process and other factors that limit the minimum detection area are quantified and adjusted to meet typical assay accuracy standards. The methodology is demonstrated by designing an 8192 element Hall sensor array, implemented in a commercial 0.18 μm CMOS process with single-mask postprocessing. The array can quantify a 1% surface coverage of 2.8 μm beads in 30 seconds with a coefficient of variation of 7.4%. This combination of accuracy and speed makes this technology a suitable detection platform for biological assays based on magnetic bead labels. PMID:25031503

  7. A 0.5-GHz CMOS digital RF memory chip

    NASA Astrophysics Data System (ADS)

    Schnaitter, W. M.; Lewis, E. T.; Gordon, B. E.

    1986-10-01

    Digital RF memories (DRFM's) are key elements for modern radar jamming. An RF signal is sampled, stored in random access memory (RAM), and later recreated from the stored data. Here the first CMOS DRFM chip, integrating static RAM, control circuitry, and two channels of shift registers, on a single chip is described. The sample rate achieved was 0.5 GHz, VLSI density was made possible by the low-power dissipation of quiescent CMOS circuits. An 8K RAM prototype chip has been built and tested.

  8. A 65 nm CMOS LNA for Bolometer Application

    NASA Astrophysics Data System (ADS)

    Huang, Tom Nan; Boon, Chirn Chye; Zhu, Forest Xi; Yi, Xiang; He, Xiaofeng; Feng, Guangyin; Lim, Wei Meng; Liu, Bei

    2016-01-01

    Modern bolometers generally consist of large-scale arrays of detectors. Implemented in conventional technologies, such bolometer arrays suffer from integrability and productivity issues. Recently, the development of CMOS technologies has presented an opportunity for the massive production of high-performance and highly integrated bolometers. This paper presents a 65-nm CMOS LNA designed for a millimeter-wave bolometer's pre-amplification stage. By properly applying some positive feedback, the noise figure of the proposed LNA is minimized at under 6 dB and the bandwidth is extended to 30 GHz.

  9. CMOS 6-T SRAM cell design subject to ``atomistic'' fluctuations

    NASA Astrophysics Data System (ADS)

    Cheng, B.; Roy, S.; Asenov, A.

    2007-04-01

    Intrinsic parameter fluctuations adversely affect SRAM cell stability, and will become one of the major factors limiting future CMOS 6-T SRAM scaling. In this work, using the driveability ratio and cell ratio parameters, and employing 'Write Assist' technology, we present a compromise design methodology which can balance WNM and SNM performance, improving CMOS 6-T SRAM scalability in the decananometer regime. The feasibility of the approach is demonstrated through detailed statistical SRAM simulations using models calibrated against MOSFETs with physical gate length of 35 nm.

  10. A 65 nm CMOS LNA for Bolometer Application

    NASA Astrophysics Data System (ADS)

    Huang, Tom Nan; Boon, Chirn Chye; Zhu, Forest Xi; Yi, Xiang; He, Xiaofeng; Feng, Guangyin; Lim, Wei Meng; Liu, Bei

    2016-04-01

    Modern bolometers generally consist of large-scale arrays of detectors. Implemented in conventional technologies, such bolometer arrays suffer from integrability and productivity issues. Recently, the development of CMOS technologies has presented an opportunity for the massive production of high-performance and highly integrated bolometers. This paper presents a 65-nm CMOS LNA designed for a millimeter-wave bolometer's pre-amplification stage. By properly applying some positive feedback, the noise figure of the proposed LNA is minimized at under 6 dB and the bandwidth is extended to 30 GHz.

  11. Modifications in CMOS Dynamic Logic Style: A Review Paper

    NASA Astrophysics Data System (ADS)

    Meher, Preetisudha; Mahapatra, Kamalakanta

    2015-12-01

    Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper, an overview and classification of these techniques are first presented and then compared according to their performance.

  12. An equivalent doping profile for CMOS substrate characterization

    NASA Astrophysics Data System (ADS)

    Quaresma, Henrique J.; Mendonça dos Santos, P.; Cruz Serra, A.

    2013-01-01

    This work presents a non-destructive methodology to accurately estimate an equivalent substrate doping profile of a typical CMOS process. The methodology is based on simple experimental resistive measurements at different temperatures, obtained from a set of basic integrated test structures, and in 3D semiconductor simulations, to compute an estimate for the unknown CMOS process parameters. It is demonstrated that the resultant box distribution equivalent doping profile could be used to evaluate the variation of the substrate impedance as a function of temperature and substrate contact distance.

  13. Commercial Fishing.

    ERIC Educational Resources Information Center

    Florida State Dept. of Education, Tallahassee. Div. of Vocational Education.

    This document is a curriculum framework for a program in commercial fishing to be taught in Florida secondary and postsecondary institutions. This outline covers the major concepts/content of the program, which is designed to prepare students for employment in occupations with titles such as net fishers, pot fishers, line fishers, shrimp boat…

  14. Commercial applications

    NASA Technical Reports Server (NTRS)

    Togai, Masaki

    1990-01-01

    Viewgraphs on commercial applications of fuzzy logic in Japan are presented. Topics covered include: suitable application area of fuzzy theory; characteristics of fuzzy control; fuzzy closed-loop controller; Mitsubishi heavy air conditioner; predictive fuzzy control; the Sendai subway system; automatic transmission; fuzzy logic-based command system for antilock braking system; fuzzy feed-forward controller; and fuzzy auto-tuning system.

  15. Total dose and proton testing of a commercial HgCdTe array

    SciTech Connect

    Hopkinson, G.R. ); Baddiley, C.J.; Guy, D.R.P. ); Parsons, J.E. )

    1994-12-01

    The radiation tolerance of a commercially available 256 x 4 HgCdTe array has been measured. The main effects were ionization-induced and produced changes in diode slope resistance and CMOS multiplexer characteristics particularly the onset of parasitic leakage currents after [approximately]15krad(Si). However these effects annealed with storage above 20 C.

  16. A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

    NASA Technical Reports Server (NTRS)

    Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

    1993-01-01

    A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

  17. Commercial Sensory Survey Radiation Testing Progress Report

    NASA Technical Reports Server (NTRS)

    Becker, Heidi N.; Dolphic, Michael D.; Thorbourn, Dennis O.; Alexander, James W.; Salomon, Phil M.

    2008-01-01

    The NASA Electronic Parts and Packaging (NEPP) Program Sensor Technology Commercial Sensor Survey task is geared toward benefiting future NASA space missions with low-cost, short-duty-cycle, visible imaging needs. Such applications could include imaging for educational outreach purposes or short surveys of spacecraft, planetary, or lunar surfaces. Under the task, inexpensive commercial grade CMOS sensors were surveyed in fiscal year 2007 (FY07) and three sensors were selected for total ionizing dose (TID) and displacement damage dose (DDD) tolerance testing. The selected sensors had to meet selection criteria chosen to support small, low-mass cameras that produce good resolution color images. These criteria are discussed in detail in [1]. This document discusses the progress of radiation testing on the Micron and OmniVision sensors selected in FY07 for radiation tolerance testing.

  18. Analysis of pixel circuits in CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Mei, Zou; Chen, Nan; Yao, Li-bin

    2015-04-01

    CMOS image sensors (CIS) have lower power consumption, lower cost and smaller size than CCD image sensors. However, generally CCDs have higher performance than CIS mainly due to lower noise. The pixel circuit used in CIS is the first part of the signal processing circuit and connected to photodiode directly, so its performance will greatly affect the CIS or even the whole imaging system. To achieve high performance, CMOS image sensors need advanced pixel circuits. There are many pixel circuits used in CIS, such as passive pixel sensor (PPS), 3T and 4T active pixel sensor (APS), capacitive transimpedance amplifier (CTIA), and passive pixel sensor (PPS). At first, the main performance parameters of each pixel structure including the noise, injection efficiency, sensitivity, power consumption, and stability of bias voltage are analyzed. Through the theoretical analysis of those pixel circuits, it is concluded that CTIA pixel circuit has good noise performance, high injection efficiency, stable photodiode bias, and high sensitivity with small integrator capacitor. Furthermore, the APS and CTIA pixel circuits are simulated in a standard 0.18-μm CMOS process and using a n-well/p-sub photodiode by SPICE and the simulation result confirms the theoretical analysis result. It shows the possibility that CMOS image sensors can be extended to a wide range of applications requiring high performance.

  19. High speed CMOS/SOS standard cell notebook

    NASA Technical Reports Server (NTRS)

    1978-01-01

    The NASA/MSFC high speed CMOS/SOS standard cell family, designed to be compatible with the PR2D (Place, Route in 2-Dimensions) automatic layout program, is described. Standard cell data sheets show the logic diagram, the schematic, the truth table, and propagation delays for each logic cell.

  20. Research-grade CMOS image sensors for remote sensing applications

    NASA Astrophysics Data System (ADS)

    Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Martin-Gonthier, Philippe; Corbiere, Franck; Belliot, Pierre; Estribeau, Magali

    2004-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding space applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this paper will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments and performances of CIS prototypes built using an imaging CMOS process will be presented in the corresponding section.

  1. Research-grade CMOS image sensors for demanding space applications

    NASA Astrophysics Data System (ADS)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2004-06-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  2. Integrated imaging sensor systems with CMOS active pixel sensor technology

    NASA Technical Reports Server (NTRS)

    Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

    2002-01-01

    This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

  3. CMOS image sensors as an efficient platform for glucose monitoring.

    PubMed

    Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

    2013-10-01

    Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications. PMID:23900281

  4. Attributes and drawbacks of submicron CMOS for IR FPA readouts

    NASA Astrophysics Data System (ADS)

    Kozlowski, L. J.

    1998-09-01

    The availability of submicron CMOS has enabled the development of shingle-chip IR cameras having performance capabilities and on-chip functions which were previously impossible. Sensor designers are, however, encoutering and overcoming several challanges including steadily decreasing operating voltage.

  5. Single Event Upset Behavior of CMOS Static RAM Cells

    NASA Technical Reports Server (NTRS)

    Lieneweg, Udo; Jeppson, Kjell O.; Buehler, Martin G.

    1993-01-01

    An improved state-space analysis of the CMOS static RAM cell is presented. Introducing theconcept of the dividing line, the critical charge for heavy-ion-induced upset of memory cells can becalculated considering symmetrical as well as asymmetrical capacitive loads. From the criticalcharge, the upset-rate per bit-day for static RAMs can be estimated.

  6. Effects Of Dose Rates On Radiation Damage In CMOS Parts

    NASA Technical Reports Server (NTRS)

    Goben, Charles A.; Coss, James R.; Price, William E.

    1990-01-01

    Report describes measurements of effects of ionizing-radiation dose rate on consequent damage to complementary metal oxide/semiconductor (CMOS) electronic devices. Depending on irradiation time and degree of annealing, survivability of devices in outer space, or after explosion of nuclear weapons, enhanced. Annealing involving recovery beyond pre-irradiation conditions (rebound) detrimental. Damage more severe at lower dose rates.

  7. CMOS VLSI Layout and Verification of a SIMD Computer

    NASA Technical Reports Server (NTRS)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  8. Mechanically Flexible and High-Performance CMOS Logic Circuits

    NASA Astrophysics Data System (ADS)

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-10-01

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices.

  9. Mechanically Flexible and High-Performance CMOS Logic Circuits.

    PubMed

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-01-01

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

  10. Mechanically Flexible and High-Performance CMOS Logic Circuits

    PubMed Central

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-01-01

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

  11. Low light level CMOS sensor for night vision systems

    NASA Astrophysics Data System (ADS)

    Gross, Elad; Ginat, Ran; Nesher, Ofer

    2015-05-01

    For many years image intensifier tubes were used for night vision systems. In 2014, Elbit systems developed a digital low-light level CMOS sensor, with similar sensitivity to a Gen II image-intensifiers, down to starlight conditions. In this work we describe: the basic principle behind this sensor, physical model for low-light performance estimation and results of field testing.

  12. CMOS Active-Pixel Image Sensor With Simple Floating Gates

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

    1996-01-01

    Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

  13. CCD AND PIN-CMOS DEVELOPMENTS FOR LARGE OPTICAL TELESCOPE.

    SciTech Connect

    RADEKA, V.

    2006-04-03

    Higher quantum efficiency in near-IR, narrower point spread function and higher readout speed than with conventional sensors have been receiving increased emphasis in the development of CCDs and silicon PIN-CMOS sensors for use in large optical telescopes. Some key aspects in the development of such devices are reviewed.

  14. Performance of CMOS ternary full adder at liquid nitrogen temperature

    NASA Astrophysics Data System (ADS)

    Srivastava, A.; Venkatapathy, K.

    We have designed, implemented and studied the performance at liquid nitrogen temperature (77 K) of a CMOS ternary full adder and its building blocks, the simple ternary inverter (STI), positive ternary inverter (PTI) and negative ternary inverter (NTI), and compared the corresponding performance at room temperature (300 K). The ternary full adder has been fabricated in 2 μm, n-well CMOS through MOSIS. In a ternary full adder, the basic building blocks, the PTI and NTI, have been developed using combinations of a CMOS inverter and transmission gate(s). There is close agreement between the simulated and measured voltage transfer characteristics and noise margins of ternary-valued devices. The measured transient times for the NTI, PTI and ternary full adder at 77 K show an improvement by a factor of ≈1.5-2.5 over the corresponding values at 300 K. The present design does not use linear resistors and depletion-mode MOSFETs to implement the ternary full adder and its building blocks, and is fully compatible with current CMOS technology.

  15. CMOS Ultra Low Power Radiation Tolerant (CULPRiT) Microelectronics

    NASA Technical Reports Server (NTRS)

    Yeh, Penshu; Maki, Gary

    2007-01-01

    Space Electronics needs Radiation Tolerance or hardness to withstand the harsh space environment: high-energy particles can change the state of the electronics or puncture transistors making them disfunctional. This viewgraph document reviews the use of CMOS Ultra Low Power Radiation Tolerant circuits for NASA's electronic requirements.

  16. CMOS-based avalanche photodiodes for direct particle detection

    NASA Astrophysics Data System (ADS)

    Stapels, Christopher J.; Squillante, Michael R.; Lawrence, William G.; Augustine, Frank L.; Christian, James F.

    2007-08-01

    Active Pixel Sensors (APSs) in complementary metal-oxide-semiconductor (CMOS) technology are augmenting Charge-Coupled Devices (CCDs) as imaging devices and cameras in some demanding optical imaging applications. Radiation Monitoring Devices are investigating the APS concept for nuclear detection applications and has successfully migrated avalanche photodiode (APD) pixel fabrication to a CMOS environment, creating pixel detectors that can be operated with internal gain as proportional detectors. Amplification of the signal within the diode allows identification of events previously hidden within the readout noise of the electronics. Such devices can be used to read out a scintillation crystal, as in SPECT or PET, and as direct-conversion particle detectors. The charge produced by an ionizing particle in the epitaxial layer is collected by an electric field within the diode in each pixel. The monolithic integration of the readout circuitry with the pixel sensors represents an improved design compared to the current hybrid-detector technology that requires wire or bump bonding. In this work, we investigate designs for CMOS APD detector elements and compare these to typical values for large area devices. We characterize the achievable detector gain and the gain uniformity over the active area. The excess noise in two different pixel structures is compared. The CMOS APD performance is demonstrated by measuring the energy spectra of X-rays from 55Fe.

  17. Distinct development patterns of c-mos protooncogene expression in female and male mouse germ cells

    SciTech Connect

    Mutter, G.L.; Wolgemuth, D.J.

    1987-08-01

    The protooncogene c-mos is expressed in murine reproductive tissues, producing transcripts of 1.7 and 1.4 kilobases in testis and ovary, respectively. In situ hybridization analysis of c-mos expression in histological sections of mouse ovaries revealed that oocytes are the predominant if not exclusive source of c-mos transcripts. /sup 35/S- or /sup 32/P-labelled RNA probes were transcribed. c-mos transcripts accumulate in growing oocytes, increasing 40- to 90-fold during oocyte and follicular development. c-mos transcripts were also detected in male germ cells and are most abundant after the cells have entered the haploid stage of spermatogenesis. This developmentally regulated pattern of c-mos expression in oocytes and spermatogenic cells suggest that the c-mos gene product may have a function in normal germ-cell differentiation or early embryogenesis.

  18. Contact CMOS imaging of gaseous oxygen sensor array

    PubMed Central

    Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

    2014-01-01

    We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

  19. An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

    PubMed Central

    Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

  20. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    PubMed

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

  1. Development of a CMOS SOI Pixel Detector

    SciTech Connect

    Arai, Y.; Hazumi, M.; Ikegami, Y.; Kohriki, T.; Tajima, O.; Terada, S.; Tsuboyama, T.; Unno, Y.; Ushiroda, Y.; Ikeda, H.; Hara, K.; Ishino, H.; Kawasaki, T.; Miyake, H.; Martin, E.; Varner, G.; Tajima, H.; Ohno, M.; Fukuda, K.; Komatsubara, H.; Ida, J.; /NONE - OKI ELECTR INDUST TOKYO

    2008-08-19

    We have developed a monolithic radiation pixel detector using silicon on insulator (SOI) with a commercial 0.15 {micro}m fully-depleted-SOI technology and a Czochralski high resistivity silicon substrate in place of a handle wafer. The SOI TEG (Test Element Group) chips with a size of 2.5 x 2.5 mm{sup 2} consisting of 20 x 20 {micro}m{sup 2} pixels have been designed and manufactured. Performance tests with a laser light illumination and a {beta} ray radioactive source indicate successful operation of the detector. We also briefly discuss the back gate effect as well as the simulation study.

  2. Commercial Capaciflector

    NASA Technical Reports Server (NTRS)

    Vranish, John M.

    1991-01-01

    A capacitive proximity/tactile sensor with unique performance capabilities ('capaciflector' or capacitive reflector) is being developed by NASA/Goddard Space Flight Center (GSFC) for use on robots and payloads in space in the interests of safety, efficiency, and ease of operation. Specifically, this sensor will permit robots and their attached payloads to avoid collisions in space with humans and other objects and to dock these payloads in a cluttered environment. The sensor is simple, robust, and inexpensive to manufacture with obvious and recognized commercial possibilities. Accordingly, NASA/GSFC, in conjunction with industry, is embarking on an effort to 'spin' this technology off into the private sector. This effort includes prototypes aimed at commercial applications. The principles of operation of these prototypes are described along with hardware, software, modelling, and test results. The hardware description includes both the physical sensor in terms of a flexible printed circuit board and the electronic circuitry. The software description will include filtering and detection techniques. The modelling will involve finite element electric field analysis and will underline techniques used for design optimization.

  3. Practicality of Evaluating Soft Errors in Commercial sub-90 nm CMOS for Space Applications

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan A.; LaBel, Kenneth A.

    2010-01-01

    The purpose of this presentation is to: Highlight space memory evaluation evolution, Review recent developments regarding low-energy proton direct ionization soft errors, Assess current space memory evaluation challenges, including increase of non-volatile technology choices, and Discuss related testing and evaluation complexities.

  4. Feasibility study of a latchup-based particle detector exploiting commercial CMOS technologies

    NASA Astrophysics Data System (ADS)

    Gabrielli, A.; Matteucci, G.; Civera, P.; Demarchi, D.; Villani, G.; Weber, M.

    2009-12-01

    The stimulated ignition of latchup effects caused by external radiation has so far proved to be a hidden hazard. Here this effect is described as a novel approach to detect particles by means of a solid-state device susceptible to latchup effects. In addition, the device can also be used as a circuit for reading sensors devices, leaving the capability of sensing to external sensors. The paper first describes the state-of-the-art of the project and its development over the latest years, then the present and future studies are proposed. An elementary cell composed of two transistors connected in a thyristor structure is shown. The study begins using traditional bipolar transistors since the latchup effect is originated as a parasitic circuit composed of such devices. Then, an equivalent circuit built up of MOS transistors is exploited, resulting an even more promising and challenging configuration than that obtained via bipolar transistors. As the MOS transistors are widely used at present in microelectronics devices and sensors, a latchup-based cell is proposed as a novel structure for future applications in particle detection, amplification of signal sensors and radiation monitoring.

  5. High-gain cryogenic amplifier assembly employing a commercial CMOS operational amplifier.

    PubMed

    Proctor, J E; Smith, A W; Jung, T M; Woods, S I

    2015-07-01

    We have developed a cryogenic amplifier for the measurement of small current signals (10 fA-100 nA) from cryogenic optical detectors. Typically operated with gain near 10(7) V/A, the amplifier performs well from DC to greater than 30 kHz and exhibits noise level near the Johnson limit. Care has been taken in the design and materials to control heat flow and temperatures throughout the entire detector-amplifier assembly. A simple one-board version of the amplifier assembly dissipates 8 mW to our detector cryostat cold stage, and a two-board version can dissipate as little as 17 μW to the detector cold stage. With current noise baseline of about 10 fA/(Hz)(1/2), the cryogenic amplifier is generally useful for cooled infrared detectors, and using blocked impurity band detectors operated at 10 K, the amplifier enables noise power levels of 2.5 fW/(Hz)(1/2) for detection of optical wavelengths near 10 μm. PMID:26233351

  6. Improved Space Object Orbit Determination Using CMOS Detectors

    NASA Astrophysics Data System (ADS)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario a sensor in a sun-synchronous LEO orbit, always pointing in the anti-sun direction to achieve optimum illumination conditions for small LEO debris, was simulated. For the space-based scenario the simulations showed a 20 130 % improvement of the accuracy of all orbital parameters when varying the frame rate from 1/3 fps, which is the fastest rate for a typical CCD detector, to 50 fps, which represents the highest rate of scientific CMOS cameras. Changing the epoch registration accuracy from a typical 20.0 ms for a mechanical shutter to 0.025 ms, the theoretical value for the electronic shutter of a CMOS camera, improved the orbit accuracy by 4 to 190 %. The ground-based scenario also benefit from the specific CMOS characteristics, but to a lesser extent.

  7. High-Voltage-Input Level Translator Using Standard CMOS

    NASA Technical Reports Server (NTRS)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

  8. CMOS VLSI Active-Pixel Sensor for Tracking

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The diagonal-switch and memory addresses would be generated by the on-chip controller. The memory array would be large enough to hold differential signals acquired from all 8 windows during a frame period. Following the rapid sampling from all the windows, the contents of the memory array would be read out sequentially by use of a capacitive transimpedance amplifier (CTIA) at a maximum data rate of 10 MHz. This data rate is compatible with an update rate of almost 10 Hz, even in full-frame operation

  9. A theoretical investigation of spectra utilization for a CMOS based indirect detector for dual energy applications

    NASA Astrophysics Data System (ADS)

    Kalyvas, N.; Martini, N.; Koukou, V.; Michail, C.; Sotiropoulou, P.; Valais, I.; Kandarakis, I.; Fountos, G.

    2015-09-01

    Dual Energy imaging is a promising method for visualizing masses and microcalcifications in digital mammography. Currently commercially available detectors may be suitable for dual energy mammographic applications. The scope of this work was to theoretically examine the performance of the Radeye CMOS digital indirect detector under three low- and high-energy spectral pairs. The detector was modeled through the linear system theory. The pixel size was equal to 22.5μm and the phosphor material of the detector was a 33.9 mg/cm2 Gd2O2S:Tb phosphor screen. The examined spectral pairs were (i) a 40kV W/Ag (0.01cm) and a 70kV W/Cu (0.1cm) target/filter combinations, (ii) a 40kV W/Cd (0.013cm) and a 70kV W/Cu (0.1cm) target/filter combinations and (iii) a 40kV W/Pd (0.008cm) and a 70kV W/Cu (0.1cm) target/filter combinations. For each combination the Detective Quantum Efficiency (DQE), showing the signal to noise ratio transfer, the detector optical gain (DOG), showing the sensitivity of the detector and the coefficient of variation (CV) of the detector output signal were calculated. The second combination exhibited slightly higher DOG (326 photons per X-ray) and lower CV (0.755%) values. In terms of electron output from the RadEye CMOS, the first two combinations demonstrated comparable DQE values; however the second combination provided an increase of 6.5% in the electron output.

  10. Performance of PHOTONIS' low light level CMOS imaging sensor for long range observation

    NASA Astrophysics Data System (ADS)

    Bourree, Loig E.

    2014-05-01

    Identification of potential threats in low-light conditions through imaging is commonly achieved through closed-circuit television (CCTV) and surveillance cameras by combining the extended near infrared (NIR) response (800-10000nm wavelengths) of the imaging sensor with NIR LED or laser illuminators. Consequently, camera systems typically used for purposes of long-range observation often require high-power lasers in order to generate sufficient photons on targets to acquire detailed images at night. While these systems may adequately identify targets at long-range, the NIR illumination needed to achieve such functionality can easily be detected and therefore may not be suitable for covert applications. In order to reduce dependency on supplemental illumination in low-light conditions, the frame rate of the imaging sensors may be reduced to increase the photon integration time and thus improve the signal to noise ratio of the image. However, this may hinder the camera's ability to image moving objects with high fidelity. In order to address these particular drawbacks, PHOTONIS has developed a CMOS imaging sensor (CIS) with a pixel architecture and geometry designed specifically to overcome these issues in low-light level imaging. By combining this CIS with field programmable gate array (FPGA)-based image processing electronics, PHOTONIS has achieved low-read noise imaging with enhanced signal-to-noise ratio at quarter moon illumination, all at standard video frame rates. The performance of this CIS is discussed herein and compared to other commercially available CMOS and CCD for long-range observation applications.

  11. A CMOS integrated timing discriminator circuit for fast scintillation counters

    SciTech Connect

    Jochmann, M.W.

    1998-06-01

    Based on a zero-crossing discriminator using a CR differentiation network for pulse shaping, a new CMOS integrated timing discriminator circuit is proposed for fast (t{sub r} {ge} 2 ns) scintillation counters at the cooler synchrotron COSY-Juelich. By eliminating the input signal`s amplitude information by means of an analog continuous-time divider, a normalized pulse shape at the zero-crossing point is gained over a wide dynamic input amplitude range. In combination with an arming comparator and a monostable multivibrator this yields in a highly precise timing discriminator circuit, that is expected to be useful in different time measurement applications. First measurement results of a CMOS integrated logarithmic amplifier, which is part of the analog continuous-time divider, agree well with the corresponding simulations. Moreover, SPICE simulations of the integrated discriminator circuit promise a time walk well below 200 ps (FWHM) over a 40 dB input amplitude dynamic range.

  12. Forced Chaos Generator with CMOS Variable Active Inductor Circuit

    NASA Astrophysics Data System (ADS)

    Tsubaki, Yusuke; Sekikawa, Munehisa; Horio, Yosihiko

    We propose a forced chaos generator with a CMOS variable active inductor circuit. The equivalent inductance of the variable active inductor in the proposed circuit can be controlled by an external voltage. Therefore, the oscillation frequencies of the circuit can be altered by applying an external periodic square waveform. As a result, we can generate chaos from the circuit. We then confirm the folding-and-stretching mechanism of the chaotic motion in the circuit. Complex phenomena, observed in the proposed circuit, are analyzed through the Poincaré sections from the SPICE simulations with TSMC 0.35μm CMOS semiconductor process parameters. In addition, we define a return map on the Poincaré section to examine the properties of the observed attractors. Moreover, we investigate the bifurcation phenomena when the amplitude and period of the external signal are changed as bifurcation parameters.

  13. On testing stuck-open faults in CMOS combinational circuits

    NASA Technical Reports Server (NTRS)

    Chandramouli, R.

    1982-01-01

    Recently it has been found that a class of failure related to a particular technology (CMOS) cannot be modelled as the conventional stuck-at fault model. These failures change the combinational behavior of CMOS logic gates into a sequential one. Such a failure is modelled as a fault, called the Stuck-Open fault (SOP). The object of this paper is to develop a procedure to detect single SOPs in combinational circuits. It is shown, that in general, tests generated for stuck-at faults when applied in a particular sequence will detect all single SOP faults. In case of single redundancy in the network, the SOP fault on the redundant line cannot be detected. When there is reconvergent fan-out in the network, there is a one-one correspondence between the conditions for stuck-at fault and stuck-open fault detectability.

  14. Analysis of CMOS-compatible lateral insulated base transistors

    NASA Astrophysics Data System (ADS)

    Narayanan, E. M. S.; Amaratunga, G. A. J.; Milne, W. I.; Huang, Q.; Humphrey, J. I.

    1991-07-01

    Performance results are reported for various lateral insulated-base transistors (LIBTs) fabricated with a 2.5-micron digital CMOS-compatible high-voltage integrated circuit (HVIC) process. Structural modifications have been proposed to the LIBTs reported to date, in order to improve their on-stage performance. The modifications have been achieved with the use of charge-controlled n(+) buried layers incorporated within the device structures. The fabrication process utilizes three additional steps carried out prior to the CMOS fabrication sequence. An important feature of this HVIC process is the use of a 40-nm gate oxide, which makes the power devices fully compatible with the low-voltage digital circuits. During this work, a specific on-resistance of 0.016 ohm sq cm and a turn-off delay of 90 nsec have been obtained in an improved LIBT structure which is capable of withstanding up to 250 V.

  15. Fundamental performance differences between CMOS and CCD imagers: Part II

    NASA Astrophysics Data System (ADS)

    Janesick, James; Andrews, James; Tower, John; Grygon, Mark; Elliott, Tom; Cheng, John; Lesser, Michael; Pinter, Jeff

    2007-09-01

    A new class of CMOS imagers that compete with scientific CCDs is presented. The sensors are based on deep depletion backside illuminated technology to achieve high near infrared quantum efficiency and low pixel cross-talk. The imagers deliver very low read noise suitable for single photon counting - Fano-noise limited soft x-ray applications. Digital correlated double sampling signal processing necessary to achieve low read noise performance is analyzed and demonstrated for CMOS use. Detailed experimental data products generated by different pixel architectures (notably 3TPPD, 5TPPD and 6TPG designs) are presented including read noise, charge capacity, dynamic range, quantum efficiency, charge collection and transfer efficiency and dark current generation. Radiation damage data taken for the imagers is also reported.

  16. Monolithic CMOS-MEMS integration for high-g accelerometers

    NASA Astrophysics Data System (ADS)

    Narasimhan, Vinayak; Li, Holden; Tan, Chuan Seng

    2014-10-01

    This paper highlights work-in-progress towards the conceptualization, simulation, fabrication and initial testing of a silicon-germanium (SiGe) integrated CMOS-MEMS high-g accelerometer for military, munition, fuze and shock measurement applications. Developed on IMEC's SiGe MEMS platform, the MEMS offers a dynamic range of 5,000 g and a bandwidth of 12 kHz. The low noise readout circuit adopts a chopper-stabilization technique implementing the CMOS through the TSMC 0.18 µm process. The device structure employs a fully differential split comb-drive set up with two sets of stators and a rotor all driven separately. Dummy structures acting as protective over-range stops were designed to protect the active components when under impacts well above the designed dynamic range.

  17. A high precision CMOS weak current readout circuit

    NASA Astrophysics Data System (ADS)

    Qisong, Wu; Haigang, Yang; Tao, Yin; Chong, Zhang

    2009-07-01

    This paper presents a high precision CMOS weak current readout circuit. This circuit is capable of converting a weak current into a frequency signal for amperometric measurements with high precision and further delivering a 10-bit digital output. A fast stabilization-enhanced potentiostat has been proposed in the design, which is used to maintain a constant bias potential for amperometric biochemical sensors. A technique based on source voltage shifting that reduces the leakage current of the MOS transistor to the reverse diode leakage level at room temperature was employed in the circuit. The chip was fabricated in the 0.35 μm chartered CMOS process, with a single 3.3 V power supply. The interface circuit maintains a dynamic range of more than 100 dB. Currents from 1 pA to 300 nA can be detected with a maximum nonlinearity of 0.3% over the full scale.

  18. An electrochemical dopamine sensor with a CMOS detection circuit

    NASA Astrophysics Data System (ADS)

    Chan, Feng-Lin; Chang, Wen-Ying; Kuo, Li-Min; Lin, Chih-Heng; Wang, Shi-Wei; Yang, Yuh-Shyong; S-C Lu, Michael

    2008-07-01

    This paper presents the integration of interdigitated microelectrodes and a CMOS circuit for electrochemical sensing of the neurotransmitter dopamine. Gold electrodes with a gap of 3 µm are fabricated by the lift-off technique. The CMOS sensing circuit has a current gain of 10, an integrating capacitor of 4 pF, and a measured dynamic range of 60 dB. The applied reduction and oxidation potentials are determined by voltammetry at about -0.2 V and 0.6 V, respectively. The measured collection efficiency can reach up to 84%. The produced oxidation current with respect to dopamine concentration averages 0.44 nA µM-1.

  19. High dynamic range CMOS (HDRC) imagers for safety systems

    NASA Astrophysics Data System (ADS)

    Strobel, Markus; Döttling, Dietmar

    2013-04-01

    The first part of this paper describes the high dynamic range CMOS (HDRC®) imager - a special type of CMOS image sensor with logarithmic response. The powerful property of a high dynamic range (HDR) image acquisition is detailed by mathematical definition and measurement of the optoelectronic conversion function (OECF) of two different HDRC imagers. Specific sensor parameters will be discussed including the pixel design for the global shutter readout. The second part will give an outline on the applications and requirements of cameras for industrial safety. Equipped with HDRC global shutter sensors SafetyEYE® is a high-performance stereo camera system for safe three-dimensional zone monitoring enabling new and more flexible solutions compared to existing safety guards.

  20. Diffuse reflectance measurements using lensless CMOS imaging chip

    NASA Astrophysics Data System (ADS)

    Schelkanova, I.; Pandya, A.; Shah, D.; Lilge, L.; Douplik, A.

    2014-10-01

    To assess superficial epithelial microcirculation, a diagnostic tool should be able to detect the heterogeneity of microvasculature, and to monitor qualitative derangement of perfusion in a diseased condition. Employing a lensless CMOS imaging chip with an RGB Bayer filter, experiments were conducted with a microfluidic platform to obtain diffuse reflectance maps. Haemoglobin (Hb) solution (160 g/l) was injected in the periodic channels (grooves) of the microfluidic phantom which were covered with ~250 μm thick layer of intralipid to obtain a diffusive environment. Image processing was performed on data acquired on the surface of the phantom to evaluate the diffuse reflectance from the subsurface periodic pattern. Thickness of the microfluidic grooves, the wavelength dependent contrast between Hb and the background, and effective periodicity of the grooves were evaluated. Results demonstrate that a lens-less CMOS camera is capable of capturing images of subsurface structures with large field of view.

  1. Radiation-hard active CMOS pixel sensors for HL-LHC detector upgrades

    NASA Astrophysics Data System (ADS)

    Backhaus, Malte

    2015-02-01

    The luminosity of the Large Hadron Collider (LHC) will be increased during the Long Shutdown of 2022 and 2023 (LS3) in order to increase the sensitivity of its experiments. A completely new inner detector for the ATLAS experiment needs to be developed to withstand the extremely harsh environment of the upgraded, so-called High-Luminosity LHC (HL-LHC). High radiation hardness as well as granularity is mandatory to cope with the requirements in terms of radiation damage as well as particle occupancy. A new silicon detector concept that uses commercial high voltage and/or high resistivity full complementary metal-oxide-semiconductor (CMOS) processes as active sensor for pixel and/or strip layers has risen high attention, because it potentially provides high radiation hardness and granularity and at the same time reduced price due to the commercial processing and possibly relaxed requirements for the hybridization technique. Results on the first prototypes characterized in a variety of laboratory as well as test beam environments are presented.

  2. X-ray imaging and spectroscopy using low cost COTS CMOS sensors

    NASA Astrophysics Data System (ADS)

    Lane, David W.

    2012-08-01

    Whilst commercial X-ray sensor arrays are capable of both imaging and spectroscopy they are currently expensive and this can limit their widespread use. This study examines the use of very low cost CMOS sensors for X-ray imaging and spectroscopy based on the commercial off the shelf (COTS) technology used in cellular telephones, PC multimedia and children's toys. Some examples of imaging using a 'webcam' and a modified OmniVision OV7411 sensor are presented, as well as a simple energy dispersive X-ray detector based on an OmniVision OV7221 sensor. In each case X-ray sensitivity was enabled by replacing the sensor's front glass window with a 5 μm thick aluminium foil, with X-rays detected as an increase in a pixel's dark current due to the generation of additional electron-hole pairs within its active region. The exposure control and data processing requirements for imaging and spectroscopy are discussed. The modified OV7221 sensor was found to have a linear X-ray energy calibration and a resolution of approximately 510 eV.

  3. Attenuation of single event induced pulses in CMOS combinational logic

    SciTech Connect

    Baze, M.P.; Buchner, S.P.

    1997-12-01

    Results are presented of a study of SEU generated transient pulse attenuation in combinational logic structures built using common digital CMOS design practices. SPICE circuit analysis, heavy ion tests, and pulsed, focused laser simulations were used to examine the response characteristics of transient pulse behavior in long logic strings. Results show that while there is an observable effect, it cannot be generally assumed that attenuation will significantly reduce observed circuit bit error rates.

  4. Linear dynamic range enhancement in a CMOS imager

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor)

    2008-01-01

    A CMOS imager with increased linear dynamic range but without degradation in noise, responsivity, linearity, fixed-pattern noise, or photometric calibration comprises a linear calibrated dual gain pixel in which the gain is reduced after a pre-defined threshold level by switching in an additional capacitance. The pixel may include a novel on-pixel latch circuit that is used to switch in the additional capacitance.

  5. Accelerated life testing effects on CMOS microcircuit characteristics, phase 1

    NASA Technical Reports Server (NTRS)

    Maximow, B.

    1976-01-01

    An accelerated life test of sufficient duration to generate a minimum of 50% cumulative failures in lots of CMOS devices was conducted to provide a basis for determining the consistency of activation energy at 250 C. An investigation was made to determine whether any thresholds were exceeded during the high temperature testing, which could trigger failure mechanisms unique to that temperature. The usefulness of the 250 C temperature test as a predictor of long term reliability was evaluated.

  6. CMOS floating-point vector-arithmetic unit

    NASA Astrophysics Data System (ADS)

    Timmermann, D.; Rix, B.; Hahn, H.; Hosticka, B. J.

    1994-05-01

    This work describes a floating-point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine, hyperbolic (co)sine, square root, natural logarithm, inverse (hyperbolic) tangent, vector norm, and phase. The chip has been integrated in 1.6 micron double-metal n-well CMOS technology and achieves a normalized peak performance of 220 MFLOPS.

  7. Development of a silicon gate CMOS technology with small structures

    NASA Astrophysics Data System (ADS)

    Milosevic, I.; Tilenschi, L.; Luft, R.; Cornwell, D.

    1982-09-01

    The development of HCMOS technology for 3 to 4 microns structures in order to improve packing density and performance for very large scale integration CMOS circuits, operating at 1,5V, is outlined. Design rule definition, photolithography/contact and projection, layout techniques, and process development (high value polysilicon resistors) are discussed. The technology developed was successfully demonstrated on an advanced 4 MHz (1,5V) watch circuit.

  8. Cryogenic CMOS circuits for single charge digital readout

    NASA Astrophysics Data System (ADS)

    Eng, Kevin; Gurrieri, T. M.; Hamlet, J.; Carroll, M. S.

    2010-03-01

    The readout of a solid state qubit often relies on single charge sensitive electrometry. However the combination of fast and accurate measurements is non trivial due to large RC time constants due to the electrometers resistance and shunt capacitance from wires between the cold stage and room temperature. Currently fast sensitive measurements are accomplished through rf reflectrometry. I will present an alternative single charge readout technique based on cryogenic CMOS circuits in hopes to improve speed, signal-to-noise, power consumption and simplicity in implementation. The readout circuit is based on a current comparator where changes in current from an electrometer will trigger a digital output. These circuits were fabricated using Sandia's 0.35μm CMOS foundry process. Initial measurements of comparators with an addition a current amplifier have displayed current sensitivities of < 1nA at 4.2K, switching speeds up to ˜120ns, while consuming ˜10μW. I will also discuss an investigation of noise characterization of our CMOS process in hopes to obtain a better understanding of the ultimate limit in signal to noise performance.

  9. CMOS integration of inkjet-printed graphene for humidity sensing.

    PubMed

    Santra, S; Hu, G; Howe, R C T; De Luca, A; Ali, S Z; Udrea, F; Gardner, J W; Ray, S K; Guha, P K; Hasan, T

    2015-01-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things. PMID:26616216

  10. CMOS integration of inkjet-printed graphene for humidity sensing

    NASA Astrophysics Data System (ADS)

    Santra, S.; Hu, G.; Howe, R. C. T.; de Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-11-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things.

  11. CMOS integration of inkjet-printed graphene for humidity sensing

    PubMed Central

    Santra, S.; Hu, G.; Howe, R. C. T.; De Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-01-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10–80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things. PMID:26616216

  12. Cryogenic CMOS circuits for single charge digital readout.

    SciTech Connect

    Gurrieri, Thomas M.; Longoria, Erin Michelle; Eng, Kevin; Carroll, Malcolm S.; Hamlet, Jason R.; Young, Ralph Watson

    2010-03-01

    The readout of a solid state qubit often relies on single charge sensitive electrometry. However the combination of fast and accurate measurements is non trivial due to large RC time constants due to the electrometers resistance and shunt capacitance from wires between the cold stage and room temperature. Currently fast sensitive measurements are accomplished through rf reflectrometry. I will present an alternative single charge readout technique based on cryogenic CMOS circuits in hopes to improve speed, signal-to-noise, power consumption and simplicity in implementation. The readout circuit is based on a current comparator where changes in current from an electrometer will trigger a digital output. These circuits were fabricated using Sandia's 0.35 {micro}m CMOS foundry process. Initial measurements of comparators with an addition a current amplifier have displayed current sensitivities of < 1nA at 4.2K, switching speeds up to {approx}120ns, while consuming {approx}10 {micro}W. I will also discuss an investigation of noise characterization of our CMOS process in hopes to obtain a better understanding of the ultimate limit in signal to noise performance.

  13. Organic thin-film transistors for flexible CMOS integration

    NASA Astrophysics Data System (ADS)

    Perez, Michael Ramon

    In this work a fully photolithographically defined complementary metal oxide semiconductor (CMOS) device is fabricated. Particular focus was on the use of solution based materials for device integration. P-type and n-type materials were evaluated for use in an organic thin film transistor (OTFT) device. The reliability and organic thin-film transistor performance of solution based dielectric polymeric dielectric materials are presented. Fabrication and characterization of integrated hybrid complementary metal oxide semiconductor devices (CMOS) using 6, 13-bis (triisopropylsilylethynyl) pentacene (TIPS-PC) and cadmium sulfide (CdS) as the active layers deposited using solution based processes are demonstrated. The hybrid CMOS technology demonstrated is compatible with large-area and mechanically flexible substrates given the low temperature processing (<100°C) and scalable design. Devices evaluated are diodes, n- and p-type thin film transistors (TFTs), inverters, NAND and NOR gates. The inverters exhibited a DC gain of ≈52 V/V with full rail-to-rail switching. The NAND logic gates switch rail-to-rail with a transition point of V DD/2.

  14. Development of CMOS Imager Block for Capsule Endoscope

    NASA Astrophysics Data System (ADS)

    Shafie, S.; Fodzi, F. A. M.; Tung, L. Q.; Lioe, D. X.; Halin, I. A.; Hasan, W. Z. W.; Jaafar, H.

    2014-04-01

    This paper presents the development of imager block to be associated in a capsule endoscopy system. Since the capsule endoscope is used to diagnose gastrointestinal diseases, the imager block must be in small size which is comfortable for the patients to swallow. In this project, a small size 1.5V button battery is used as the power supply while the voltage supply requirements for other components such as microcontroller and CMOS image sensor are higher. Therefore, a voltage booster circuit is proposed to boost up the voltage supply from 1.5V to 3.3V. A low power microcontroller is used to generate control pulses for the CMOS image sensor and to convert the 8-bits parallel data output to serial data to be transmitted to the display panel. The results show that the voltage booster circuit was able to boost the voltage supply from 1.5V to 3.3V. The microcontroller precisely controls the CMOS image sensor to produce parallel data which is then serialized again by the microcontroller. The serial data is then successfully translated to 2fps image and displayed on computer.

  15. An integrated CMOS detection system for optical short-pulse

    NASA Astrophysics Data System (ADS)

    Kim, Chang-Gun; Hong, Nam-Pyo; Choi, Young-Wan

    2014-03-01

    We present design of a front-end readout system consisting of charge sensitive amplifier (CSA) and pulse shaper for detection of stochastic and ultra-small semiconductor scintillator signal. The semiconductor scintillator is double sided silicon detector (DSSD) or avalanche photo detector (APD) for high resolution and peak signal reliability of γ-ray or X-ray spectroscopy. Such system commonly uses low noise multichannel CSA. Each CSA in multichannel includes continuous reset system based on tens of MΩ and charge-integrating capacitor in feedback loop. The high value feedback resistor requires large area and huge power consumption for integrated circuits. In this paper, we analyze these problems and propose a CMOS short pulse detection system with a novel CSA. The novel CSA is composed of continuous reset system with combination of diode connected PMOS and 100 fF. This structure has linearity with increased input charge quantity from tens of femto-coulomb to pico-coulomb. Also, the front-end readout system includes both slow and fast shapers for detecting CSA output and preventing pile-up distortion. Shaping times of fast and slow shapers are 150 ns and 1.4 μs, respectively. Simulation results of the CMOS detection system for optical short-pulse implemented in 0.18 μm CMOS technology are presented.

  16. Fully depleted, thick, monolithic CMOS pixels with high quantum efficiency

    NASA Astrophysics Data System (ADS)

    Clarke, A.; Stefanov, K.; Johnston, N.; Holland, A.

    2015-04-01

    The Centre for Electronic Imaging (CEI) has an active programme of evaluating and designing Complementary Metal-Oxide Semiconductor (CMOS) image sensors with high quantum efficiency, for applications in near-infrared and X-ray photon detection. This paper describes the performance characterisation of CMOS devices made on a high resistivity 50 μ m thick p-type substrate with a particular focus on determining the depletion depth and the quantum efficiency. The test devices contain 8 × 8 pixel arrays using CCD-style charge collection, which are manufactured in a low voltage CMOS process by ESPROS Photonics Corporation (EPC). Measurements include determining under which operating conditions the devices become fully depleted. By projecting a spot using a microscope optic and a LED and biasing the devices over a range of voltages, the depletion depth will change, causing the amount of charge collected in the projected spot to change. We determine if the device is fully depleted by measuring the signal collected from the projected spot. The analysis of spot size and shape is still under development.

  17. A CMOS TDI image sensor for Earth observation

    NASA Astrophysics Data System (ADS)

    Rushton, Joseph E.; Stefanov, Konstantin D.; Holland, Andrew D.; Endicott, James; Mayer, Frederic; Barbier, Frederic

    2015-09-01

    Time Delay and Integration (TDI) is used to increase the Signal to Noise Ratio (SNR) in image sensors when imaging fast moving objects. One important TDI application is in Earth observation from space. In order to operate in the space radiation environment, the effect that radiation damage has on the performance of the image sensors must be understood. This work looks at prototype TDI sensor pixel designs, produced by e2v technologies. The sensor is a CCD-like charge transfer device, allowing in-pixel charge summation, produced on a CMOS process. The use of a CMOS process allows potential advantages such as lower power consumption, smaller pixels, higher line rate and extra on-chip functionality which can simplify system design. CMOS also allows a dedicated output amplifier per column allowing fewer charge transfers and helping to facilitate higher line rates than CCDs. In this work the effect on the pixels of radiation damage from high energy protons, at doses relevant to a low Earth orbit mission, is presented. This includes the resulting changes in Charge Transfer inefficiency (CTI) and dark signal.

  18. Aluminum nitride on titanium for CMOS compatible piezoelectric transducers

    PubMed Central

    Doll, Joseph C; Petzold, Bryan C; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L

    2010-01-01

    Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d33f, d31 and d33 of up to 2.9, −1.9 and 6.5 pm V−1, respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals. PMID:20333316

  19. Commercial applications

    NASA Astrophysics Data System (ADS)

    The near term (one to five year) needs of domestic and foreign commercial suppliers of radiochemicals and radiopharmaceuticals for electromagnetically separated stable isotopes are assessed. Only isotopes purchased to make products for sale and profit are considered. Radiopharmaceuticals produced from enriched stable isotopes supplied by the Calutron facility at ORNL are used in about 600,000 medical procedures each year in the United States. A temporary or permanent disruption of the supply of stable isotopes to the domestic radiopharmaceutical industry could curtail, if not eliminate, the use of such diagnostic procedures as the thallium heart scan, the gallium cancer scan, the gallium abscess scan, and the low radiation dose thyroid scan. An alternative source of enriched stable isotopes exist in the USSR. Alternative starting materials could, in theory, eventually be developed for both the thallium and gallium scans. The development of a new technology for these purposes, however, would take at least five years and would be expensive. Hence, any disruption of the supply of enriched isotopes from ORNL and the resulting unavailability of critical nuclear medicine procedures would have a dramatic negative effect on the level of health care in the United States.

  20. Single photon detection and localization accuracy with an ebCMOS camera

    NASA Astrophysics Data System (ADS)

    Cajgfinger, T.; Dominjon, A.; Barbier, R.

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 μm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  1. CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.

    SciTech Connect

    Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

    2008-08-01

    Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

  2. Polyadenylation of c-mos mRNA as a control point in Xenopus meiotic maturation.

    PubMed

    Sheets, M D; Wu, M; Wickens, M

    1995-04-01

    c-mos protein, encoded by a proto-oncogene, is essential for the meiotic maturation of frog oocytes. Polyadenylation of c-mos messenger RNA is shown here to be a pivotal regulatory step in meiotic maturation. Maturation is prevented by selective amputation of polyadenylation signals from c-mos mRNA. Injection of a prosthetic RNA, which restores c-mos polyadenylation signals by base pairing to the amputated mRNA, rescues maturation and can stimulate translation in trans. Prosthetic RNAs may provide a general strategy by which to alter patterns of mRNA expression in vivo. PMID:7700377

  3. CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

    NASA Astrophysics Data System (ADS)

    Davidson, Bradley Darren

    This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different WALD fabrication technologies two generations of 2-terminal WALD NEMS switches have been developed. These devices have functional gap heights of 30-50 nm, and actuation voltages typically ranging from 3--5 Volts. Via the extension of a two terminal WALD technology novel 3-terminal WALD NEMS devices were developed. These devices have actuation voltages ranging from 1.5--3 Volts, reliabilities in excess of 2 million cycles, and have been designed to be the fundamental building blocks for WALD NEMS complementary inverters. Through the development of these devices several advancements in the modeling and design of thin-film NEMS devices were achieved. A new model was developed to better characterize pre-actuation currents commonly measured for NEMS switches with nano-scale gate-to-source gap heights. The developed model is an extension of the standard field-emission model and considers the electromechanical response, and electric field effects specific to thin-film NEMS switches. Finally, a multi-physics FEM/FD based model was developed to simulate the dynamic behavior of 2 or 3-terminal electrostatically actuated devices whose electrostatic domains have an aspect ratio on the order of 10-3. The model uses a faux-Lagrangian finite difference method to solve Laplaces equation in a quasi-statatically deforming domain. This model allows for the numerical characterization and design of thin-film NEMS devices not feasible using typical non-specialized BEM/FEM based software. Using this model several novel and feasible designs for fixed-fixed 3-terminal WALD NEMS switches capable for the construction of complementary inverters were discovered.

  4. Scaled CMOS Technology Reliability Users Guide

    NASA Technical Reports Server (NTRS)

    White, Mark

    2010-01-01

    The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. A methodology on how to accomplish this and techniques for deriving the expected product-level reliability on commercial memory products are provided.Competing mechanism theory and the multiple failure mechanism model are applied to the experimental results of scaled SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope (beta)=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is presented revealing a power relationship. General models describing the soft error rates across scaled product generations are presented. The analysis methodology may be applied to other scaled microelectronic products and their key parameters.

  5. Digital pixel CMOS focal plane array with on-chip multiply accumulate units for low-latency image processing

    NASA Astrophysics Data System (ADS)

    Little, Jeffrey W.; Tyrrell, Brian M.; D'Onofrio, Richard; Berger, Paul J.; Fernandez-Cull, Christy

    2014-06-01

    A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization occurs at the pixel level, enabling in-pixel DSP and noiseless data transfer from the pixel array to the peripheral processing units. The pipelined processing of row and column image data prior to off chip readout reduces the required output bandwidth of the image sensor, thus reducing the latency of computations necessary to implement various image processing systems. Data volume reductions of over 80% lead to sub 10μs latency for completing various tracking and sensor algorithms. This paper details the architecture of the pixel-processing imager (PPI) and presents some initial results from a prototype device fabricated in a standard 65nm CMOS process hybridized to a commercial off-the-shelf short-wave infrared (SWIR) detector array.

  6. High gain CMOS image sensor design and fabrication on SOI and bulk technology

    NASA Astrophysics Data System (ADS)

    Zhang, Weiquan

    2000-12-01

    The CMOS imager is now competing with the CCD imager, which still dominates the electronic imaging market. By taking advantage of the mature CMOS technology, the CMOS imager can integrate AID converters, digital signal processing (DSP) and timing control circuits on the same chip. This low cost and high-density integration solution to the image capture is the strong driving force in industry. Silicon on insulator (SOI) is considered as the coming mainstream technology. It challenges the current bulk CMOS technology because of its reduced power consumption, high speed, radiation hardness etc. Moving the CMOS imager from the bulk to the SOI substrate will benefit from these intrinsic advantages. In addition, the blooming and the cross-talk between the pixels of the sensor array can be ideally eliminated, unlike those on the bulk technology. Though there are many advantages to integrate CMOS imager on SOI, the problem is that the top silicon film is very thin, such as 2000Å. Many photons can just pass through this layer without being absorbed. A good photo-detector on SOI is critical to integrate SOI CMOS imagers. In this thesis, several methods to make photo-detectors on SOI substrate are investigated. A floating gate MOSFET on SOI substrate, operating in its lateral bipolar mode, is photon sensitive. One step further, the SOI MOSFET gate and body can be tied together. The positive feedback between the body and gate enables this device have a high responsivity. A similar device can be found on the bulk CMOS technology: the gate-well tied PMOSFET. A 32 x 32 CMOS imager is designed and characterized using such a device as the light-sensing element. I also proposed the idea of building hybrid active pixels on SOI substrate. Such devices are fabricated and characterized. The work here represents my contribution on the CMOS imager, especially moving the CMOS imager onto the SOI substrate.

  7. Radiation hardness by design for mixed signal infrared readout circuit applications

    NASA Astrophysics Data System (ADS)

    Gaalema, Stephen; Gates, James; Dobyns, David; Pauls, Greg; Wall, Bruce

    2013-09-01

    Readout integrated circuits (ROICs) to support space-based infrared detection applications often have severe radiation tolerance requirements. Radiation hardness-by-design (RHBD) significantly enhances the radiation tolerance of commercially available CMOS and custom radiation hardened fabrication techniques are not required. The combination of application specific design techniques, enclosed gate architecture nFETs and intrinsic thin oxide radiation hardness of 180 nm process node commercial CMOS allows realization of high performance mixed signal circuits. Black Forest Engineering has used RHBD techniques to develop ROICs with integrated A/D conversion that operate over a wide range of temperatures (40K-300K) to support infrared detection. ROIC radiation tolerance capability for 256x256 LWIR area arrays and 1x128 thermopile linear arrays is presented. The use of 130 nm CMOS for future ROIC RHBD applications is discussed.

  8. A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager.

    PubMed

    Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

    2011-10-01

    Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm(2) at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm(2). Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm(2) while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624

  9. Swap intensified WDR CMOS module for I2/LWIR fusion

    NASA Astrophysics Data System (ADS)

    Ni, Yang; Noguier, Vincent

    2015-05-01

    The combination of high resolution visible-near-infrared low light sensor and moderate resolution uncooled thermal sensor provides an efficient way for multi-task night vision. Tremendous progress has been made on uncooled thermal sensors (a-Si, VOx, etc.). It's possible to make a miniature uncooled thermal camera module in a tiny 1cm3 cube with <1W power consumption. For silicon based solid-state low light CCD/CMOS sensors have observed also a constant progress in terms of readout noise, dark current, resolution and frame rate. In contrast to thermal sensing which is intrinsic day&night operational, the silicon based solid-state sensors are not yet capable to do the night vision performance required by defense and critical surveillance applications. Readout noise, dark current are 2 major obstacles. The low dynamic range at high sensitivity mode of silicon sensors is also an important limiting factor, which leads to recognition failure due to local or global saturations & blooming. In this context, the image intensifier based solution is still attractive for the following reasons: 1) high gain and ultra-low dark current; 2) wide dynamic range and 3) ultra-low power consumption. With high electron gain and ultra low dark current of image intensifier, the only requirement on the silicon image pickup device are resolution, dynamic range and power consumption. In this paper, we present a SWAP intensified Wide Dynamic Range CMOS module for night vision applications, especially for I2/LWIR fusion. This module is based on a dedicated CMOS image sensor using solar-cell mode photodiode logarithmic pixel design which covers a huge dynamic range (> 140dB) without saturation and blooming. The ultra-wide dynamic range image from this new generation logarithmic sensor can be used directly without any image processing and provide an instant light accommodation. The complete module is slightly bigger than a simple ANVIS format I2 tube with <500mW power consumption.

  10. SOI CMOS Imager with Suppression of Cross-Talk

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

    2009-01-01

    A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

  11. NV-CMOS HD camera for day/night imaging

    NASA Astrophysics Data System (ADS)

    Vogelsong, T.; Tower, J.; Sudol, Thomas; Senko, T.; Chodelka, D.

    2014-06-01

    SRI International (SRI) has developed a new multi-purpose day/night video camera with low-light imaging performance comparable to an image intensifier, while offering the size, weight, ruggedness, and cost advantages enabled by the use of SRI's NV-CMOS HD digital image sensor chip. The digital video output is ideal for image enhancement, sharing with others through networking, video capture for data analysis, or fusion with thermal cameras. The camera provides Camera Link output with HD/WUXGA resolution of 1920 x 1200 pixels operating at 60 Hz. Windowing to smaller sizes enables operation at higher frame rates. High sensitivity is achieved through use of backside illumination, providing high Quantum Efficiency (QE) across the visible and near infrared (NIR) bands (peak QE <90%), as well as projected low noise (<2h+) readout. Power consumption is minimized in the camera, which operates from a single 5V supply. The NVCMOS HD camera provides a substantial reduction in size, weight, and power (SWaP) , ideal for SWaP-constrained day/night imaging platforms such as UAVs, ground vehicles, fixed mount surveillance, and may be reconfigured for mobile soldier operations such as night vision goggles and weapon sights. In addition the camera with the NV-CMOS HD imager is suitable for high performance digital cinematography/broadcast systems, biofluorescence/microscopy imaging, day/night security and surveillance, and other high-end applications which require HD video imaging with high sensitivity and wide dynamic range. The camera comes with an array of lens mounts including C-mount and F-mount. The latest test data from the NV-CMOS HD camera will be presented.

  12. Determining the thermal expansion coefficient of thin films for a CMOS MEMS process using test cantilevers

    NASA Astrophysics Data System (ADS)

    Cheng, Chao-Lin; Tsai, Ming-Han; Fang, Weileun

    2015-02-01

    Many standard CMOS processes, provided by existing foundries, are available. These standard CMOS processes, with stacking of various metal and dielectric layers, have been extensively applied in integrated circuits as well as micro-electromechanical systems (MEMS). It is of importance to determine the material properties of the metal and dielectric films to predict the performance and reliability of micro devices. This study employs an existing approach to determine the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. Test cantilevers with different stacking of metal and dielectric layers for standard CMOS processes have been designed and implemented. The CTEs of standard CMOS films can be determined from measurements of the out-of-plane thermal deformations of the test cantilevers. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacture Company 0.35 μm 2P4M CMOS process are characterized. Eight test cantilevers with different stacking of CMOS layers and an auxiliary Si cantilever on a SOI wafer are fabricated. The equivalent elastic moduli and CTEs of the CMOS thin films including the metal and dielectric layers are determined, respectively, from the resonant frequency and static thermal deformation of the test cantilevers. Moreover, thermal deformations of cantilevers with stacked layers different to those of the test beams have been employed to verify the measured CTEs and elastic moduli.

  13. 77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-06-06

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to... States after importation of certain CMOS image sensors and products containing same by reason of... image sensors and products containing same that infringe one or more of claims 1 and 2 of the...

  14. 77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-12-14

    ... (``CalTech''). 77 FR 33488 (June 6, 2012). The complaint alleged violations of section 337 of the Tariff... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations... importation, and the sale within the United States after importation of certain CMOS image sensors...

  15. Integration of GMR-based spin torque oscillators and CMOS circuitry

    NASA Astrophysics Data System (ADS)

    Chen, Tingsu; Eklund, Anders; Sani, Sohrab; Rodriguez, Saul; Malm, B. Gunnar; kerman, Johan; Rusu, Ana

    2015-09-01

    This paper demonstrates the integration of giant magnetoresistance (GMR) spin torque oscillators (STO) with dedicated high frequency CMOS circuits. The wire-bonding-based integration approach is employed in this work, since it allows easy implementation, measurement and replacement. A GMR STO is wire-bonded to the dedicated CMOS integrated circuit (IC) mounted on a PCB, forming a (GMR STO + CMOS IC) pair. The GMR STO has a lateral size of 70 nm and more than an octave of tunability in the microwave frequency range. The proposed CMOS IC provides the necessary bias-tee for the GMR STO, as well as electrostatic discharge (ESD) protection and wideband amplification targeting high frequency GMR STO-based applications. It is implemented in a 65 nm CMOS process, offers a measured gain of 12 dB, while consuming only 14.3 mW and taking a total silicon area of 0.329 mm2. The measurement results show that the (GMR STO + CMOS IC) pair has a wide tunability range from 8 GHz to 16.5 GHz and improves the output power of the GMR STO by about 10 dB. This GMR STO-CMOS integration eliminates wave reflections during the signal transmission and therefore exhibits good potential for developing high frequency GMR STO-based applications, which combine the features of CMOS and STO technologies.

  16. Design rules for RCA self-aligned silicon-gate CMOS/SOS process

    NASA Technical Reports Server (NTRS)

    1977-01-01

    The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.

  17. Comparison of Total Dose Effects on Micropower Op-Amps: Bipolar and CMOS

    NASA Technical Reports Server (NTRS)

    Lee, C.; Johnston, A.

    1998-01-01

    This paper compares low-paper op-amps, OPA241 (bipolar) and OPA336 (CMOS), from Burr-Brown, MAX473 (bipolar) and MAX409 (CMOS), characterizing their total dose response with a single 2.7V power supply voltage.

  18. Predicting Lifetimes Of CMOS ASIC's From Test Data

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.; Zamani, Nasser; Zoutendyk, John A.

    1993-01-01

    Concise report discusses recent developments in use of semiempirical mathematical models to predict rates of failure and operating lifetimes of complementary metal oxide/semiconductor (CMOS) application-specific integrated circuits (ASIC's). Each model represents specific mechanism of failure. Once failure mechanisms and models relevant to given ASIC chosen, adjustable parameters in models fitted to life-test data acquired from representative integrated-circuit structures on test coupons fabricated along with ASIC's. Then design parameters of ASIC's incorporated into models, and models yield lifetimes.

  19. A CMOS clock and data recovery circuit for intraocular microsystems.

    PubMed

    Prmassing, F; Pttjer, D; Buss, R; Jger, D

    2002-01-01

    This paper presents the implementation of a clock and data recovery circuit (CDR) for intraocular microsystems. The CDR was designed to minimize chip area and power consumption and to recover the clock and data signals from the incoming data stream. Since the CDR has been designed without any external components it is well suited for being integrated in an intraocular microsystem. Simulation results show that this CDR works with power dissipation of less than 2.4 mW with a single 3.3 V power supply. The simulations are based on a 0.6 micron n-well CMOS single-polysilicon, three-metal technology. PMID:12451805

  20. Defect classes - an overdue paradigm for CMOS IC testing

    SciTech Connect

    Hawkins, C.F.; Soden, J.M.; Righter, A.W.; Ferguson, F.J.

    1994-09-01

    The IC test industry has struggled for more than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the test strategy match the defect electrical properties, while fault models require that IC defects match the fault definition. We use data from Sandia Labs failure analysis and test facilities and from public literature. We describe test pattern requirements for each defect class and propose a test paradigm.

  1. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

    PubMed Central

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-01-01

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly measures humidity in % RH. PMID:26184204

  2. Logic compatible process technology for embedded atom switches in CMOS

    NASA Astrophysics Data System (ADS)

    Okamoto, Koichiro; Tada, Munehiro; Banno, Naoki; Iguchi, Noriyuki; Sakamoto, Toshitsugu; Hada, Hiromitsu

    2015-05-01

    We have developed a CMOS logic compatible process for embedding Cu atom switches in a Cu/low-k back-end-of-line without degrading interconnect and switch performance characteristics. The key technologies are (i) burying a via-interlayer dielectric layer between the switches without voids, followed by surface planarization using chemical mechanical polishing, and (ii) introducing a Ta protective second top electrode, which realizes simultaneous via-openings to both the switches and the lower interconnects without degrading physical morphology and electric properties of the switches. The developed process enables us to integrate the atom switches on logic with only two additional masks at low cost.

  3. Test of radiation hardness of CMOS transistors under neutron irradiation

    SciTech Connect

    Sadrozinski, H.F.W.; Rowe, W.A.; Seiden, A.; Spencer, E.; Hoffman, C.M.; Holtkamp, D.; Kinnison, W.W.; Sommer, W.F. Jr.; Ziock, H.J.

    1989-01-01

    We have tested 2 micron CMOS test structures from various foundries in the LAMPF Beam stop for radiation damage under prolongued neutron irradiation. The fluxes employed covered the region expected to be encountered at the SSC and led to fluences of up to 10/sup 14/ neutrons/cm/sup 2/ in about 500 hrs of running. We show that test structures which have been measured to survive ionizing radiation of the order MRad also survive these high neutron fluences. 5 refs., 4 figs.

  4. 120-MHz BiCMOS superscalar RISC processor

    NASA Astrophysics Data System (ADS)

    Tanaka, Shigeya; Hotta, Takashi; Murabayashi, Fumio; Yamada, Hiromichi; Yoshida, Shoji; Shimamura, Kotaro; Katsura, Koyo; Bandoh, Tadaaki; Ikeda, Koichi; Matsubara, Kenji

    1994-04-01

    A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm x 16.5 mm, and utilizes 3.3 V/0.5 micron BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design.

  5. Charge collection in submicron CMOS/SOI technology

    SciTech Connect

    Musseau, O.; Ferlet-Cavrois, V.; Campbell, A.B.; Knudson, A.R.; Stapor, W.J.; McDonald, P.T.; Pelloie, J.L.; Raynaud, C.

    1997-12-01

    The authors present experimental measurements of charge collection spectroscopy from high energy ion strikes in submicron CMOS/SOI devices. Due to the specific structure of SOI technology, with symmetrical source and drain junctions, a direct equivalence between upset mechanism and charge collection is established. The bipolar mechanism, responsible for the amplification of the deposited charge is discussed based on 2D device simulations. Based on the experimental data the authors determine qualitatively the influence of transistor geometry on the bipolar gain. Finally the limits of the usual SEU concepts (LET threshold and cross section) are discussed for scaled devices.

  6. A high speed CMOS A/D converter

    NASA Technical Reports Server (NTRS)

    Wiseman, Don R.; Whitaker, Sterling R.

    1992-01-01

    This paper presents a high speed analog-to-digital (A/D) converter. The converter is a 7 bit flash converter with one half LSB accuracy. Typical parts will function at approximately 200 MHz. The converter uses a novel comparator circuit that is shown to out perform more traditional comparators, and thus increases the speed of the converter. The comparator is a clocked, precharged circuit that offers very fast operation with a minimal offset voltage (2 mv). The converter was designed using a standard 1 micron digital CMOS process and is 2,244 microns by 3,972 microns.

  7. Performance Analysis of Visible Light Communication Using CMOS Sensors.

    PubMed

    Do, Trong-Hop; Yoo, Myungsik

    2016-01-01

    This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis. PMID:26938535

  8. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

    PubMed

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-01-01

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly measures humidity in % RH. PMID:26184204

  9. Performance Analysis of Visible Light Communication Using CMOS Sensors

    PubMed Central

    Do, Trong-Hop; Yoo, Myungsik

    2016-01-01

    This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis. PMID:26938535

  10. Measurements with a CMOS pixel sensor in magnetic fields

    NASA Astrophysics Data System (ADS)

    de Boer, W.; Bartsch, V.; Bol, J.; Dierlamm, A.; Grigoriev, E.; Hauler, F.; Herz, O.; Jungermann, L.; Koppenhöfer, M.; Sopczak, A.; Schneider, Th.

    2002-07-01

    CMOS technique, which is the standard process used by most of the semiconductor factories worldwide, allows the production of both cheap and highly integrated sensors. The prototypes MIMOSA -I and MIMOSA-II were designed by the IReS-LEPSI collaboration in order to investigate the potential of this new technique for charged particle tracking (Design and Testing of Monolithic Active Pixel Sensors for Charged Particle Tracking, LEPSI, IN2P3, Strasbourg, France). For this purpose it is necessary to study the effects of magnetic fields as they appear in high-energy physics on these sensors. MIMOSA: Minimum Ionizing particle MOS Active pixel sensor.

  11. The DUV Stability of Superlattice-Doped CMOS Detector Arrays

    NASA Technical Reports Server (NTRS)

    Hoenk, M. E.; Carver, A. G.; Jones, T.; Dickie, M.; Cheng, P.; Greer, H. F.; Nikzad, S.; Sgro, J.; Tsur, S.

    2013-01-01

    JPL and Alacron have recently developed a high performance, DUV camera with a superlattice doped CMOS imaging detector. Supperlattice doped detectors achieve nearly 100% internal quantum efficiency in the deep and far ultraviolet, and a single layer, Al2O3 antireflection coating enables 64% external quantum efficiency at 263nm. In lifetime tests performed at Applied Materials using 263 nm pulsed, solid state and 193 nm pulsed excimer laser, the quantum efficiency and dark current of the JPL/Alacron camera remained stable to better than 1% precision during long-term exposure to several billion laser pulses, with no measurable degradation, no blooming and no image memory at 1000 fps.

  12. The total dose effects on the 1/f noise of deep submicron CMOS transistors

    NASA Astrophysics Data System (ADS)

    Rongbin, Hu; Yuxin, Wang; Wu, Lu

    2014-02-01

    Using 0.18 μm CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI (shallow trench isolation) SiO2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion.

  13. Fabrication and device characteristics of strained-Si-on-insulator (strained-SOI) CMOS

    NASA Astrophysics Data System (ADS)

    Takagi, Shin-ichi; Mizuno, Tomohisa; Tezuka, Tsutomu; Sugiyama, Naoharu; Numata, Toshinori; Usuda, Koji; Moriyama, Yoshihiko; Nakaharai, Shu; Koga, Junji; Tanabe, Akihito; Maeda, Tatsuro

    2004-03-01

    Strained-Si-on-insulator (strained-SOI) CMOS is a promising device structure for satisfying requirements of both high current drive and low supply voltage under sub-100 nm nodes, because of the combination of advantages of SOI MOSFETs and high mobility strained-Si channels. In this paper, we present the concept, the device structures and the fabrication techniques of strained-SOI CMOS. We introduce our original fabrication method of strained-SOI substrates, called the Ge condensation technique. It is experimentally shown that strained-SOI CMOS has higher electron and hole mobility and that strained-SOI CMOS ring oscillators successfully operate with the performance enhancement of 30-70% against conventional SOI CMOS ones.

  14. Optimum Design of CMOS DC-DC Converter for Mobile Applications

    NASA Astrophysics Data System (ADS)

    Katayama, Yasushi; Edo, Masaharu; Denta, Toshio; Kawashima, Tetsuya; Ninomiya, Tamotsu

    In recent years, low output power CMOS DC-DC converters which integrate power stage MOSFETs and a PWM controller using CMOS process have been used in many mobile applications. In this paper, we propose the calculation method of CMOS DC-DC converter efficiency and report optimum design of CMOS DC-DC converter based on this method. By this method, converter efficiencies are directly calculated from converter specifications, dimensions of power stage MOSFET and device parameters. Therefore, this method can be used for optimization of CMOS DC-DC converter design, such as dimensions of power stage MOSFET and switching frequency. The efficiency calculated by the proposed method agrees well with the experimental results.

  15. Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

    PubMed

    Kazior, Thomas E

    2014-03-28

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

  16. Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

    PubMed Central

    Kazior, Thomas E.

    2014-01-01

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

  17. Radiation damages in CMOS image sensors: testing and hardening challenges brought by deep sub-micrometer CIS processes

    NASA Astrophysics Data System (ADS)

    Goiffon, Vincent; Virmontois, Cédric; Magnan, Pierre; Cervantes, Paola; Corbière, Franck; Estribeau, Magali; Pinel, Philippe

    2010-10-01

    This paper presents a summary of the main results we observed after several years of study on irradiated custom imagers manufactured using 0.18 μm CMOS processes dedicated to imaging. These results are compared to irradiated commercial sensor test results provided by the Jet Propulsion Laboratory to enlighten the differences between standard and pinned photodiode behaviors. Several types of energetic particles have been used (gamma rays, X-rays, protons and neutrons) to irradiate the studied devices. Both total ionizing dose (TID) and displacement damage effects are reported. The most sensitive parameter is still the dark current but some quantum efficiency and MOSFET characteristics changes were also observed at higher dose than those of interest for space applications. In all these degradations, the trench isolations play an important role. The consequences on radiation testing for space applications and radiation-hardening-by-design techniques are also discussed.

  18. Design considerations for a new high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS)

    NASA Astrophysics Data System (ADS)

    Loughran, Brendan; Swetadri Vasan, S. N.; Singh, Vivek; Ionita, Ciprian N.; Jain, Amit; Bednarek, Daniel R.; Titus, Albert H.; Rudin, Stephen

    2013-03-01

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

  19. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    PubMed Central

    He, Diwei; Morgan, Stephen P.; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R.

    2015-01-01

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring. PMID:26184225

  20. Multiplexed Oversampling Digitizer in 65 nm CMOS for Column-Parallel CCD Readout

    SciTech Connect

    Grace, Carl; Walder, Jean-Pierre; von der Lippe, Henrik

    2012-04-10

    A digitizer designed to read out column-parallel charge-coupled devices (CCDs) used for high-speed X-ray imaging is presented. The digitizer is included as part of the High-Speed Image Preprocessor with Oversampling (HIPPO) integrated circuit. The digitizer module comprises a multiplexed, oversampling, 12-bit, 80 MS/s pipelined Analog-to-Digital Converter (ADC) and a bank of four fast-settling sample-and-hold amplifiers to instrument four analog channels. The ADC multiplexes and oversamples to reduce its area to allow integration that is pitch-matched to the columns of the CCD. Novel design techniques are used to enable oversampling and multiplexing with a reduced power penalty. The ADC exhibits 188 ?V-rms noise which is less than 1 LSB at a 12-bit level. The prototype is implemented in a commercially available 65 nm CMOS process. The digitizer will lead to a proof-of-principle 2D 10 Gigapixel/s X-ray detector.

  1. Laser Doppler blood flow imaging with a 64×64 pixel full custom CMOS sensor

    NASA Astrophysics Data System (ADS)

    He, D.; Nguyen, H. C.; Hayes-Gill, B. R.; Zhu, Y.; Crowe, J. A.; Morgan, S. P.; Clough, G. F.; Gill, C. A.

    2011-03-01

    Full field laser Doppler perfusion imaging offers advantages over scanning laser Doppler imaging as the effects of movement artifacts are reduced. The increased frame rate allows rapid changes in blood flow to be imaged. A custom made CMOS sensor offers several advantages over commercial cameras as the design can be optimized to the detected signals. For example, laser Doppler signals are known to have a bandwidth from DC up to ~20KHz and be of a low modulation depth. Therefore a design that can amplify the AC component and have a sampling rate and an antialiasing filter appropriate to the signal bandwidth would be beneficial. An additional advantage of custom made sensors is that on-chip processing of blood flow allows the data bottleneck that exists between the photo-detector array and processing electronics to be overcome, as the processed data can be read out from the image sensor to a PC or display at a low data rate. A fully integrated 64x64 pixel array for imaging blood flow is presented. On-chip analog signal processing is used to amplify the AC component, normalize the AC signal by the DC light intensity and provide anti-aliasing. On-chip digital signal processing is used to implement the filters required to calculate blood flow. The imaging array has been incorporated into a device that has been used in a clinical setting. Results are presented demonstrating changes in blood flow in occlusion and release tests.

  2. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

    PubMed

    He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

    2015-01-01

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring. PMID:26184225

  3. Demonstration of a fast-reconfigurable silicon CMOS optical lattice filter.

    PubMed

    Ibrahim, Salah; Fontaine, Nicolas K; Djordjevic, Stevan S; Guan, Binbin; Su, Tiehui; Cheung, Stanley; Scott, Ryan P; Pomerene, Andrew T; Seaford, Liberty L; Hill, Craig M; Danziger, Steve; Ding, Zhi; Okamoto, K; Yoo, S J B

    2011-07-01

    We demonstrate a fully-reconfigurable fourth-order optical lattice filter built by cascading identical unit cells consisting of a Mach-Zehnder interferometer (MZI) and a ring resonator. The filter is fabricated using a commercial silicon complementary metal oxide semiconductor (CMOS) process and reconfigured by current injection into p-i-n diodes with a reconfiguration time of less than 10 ns. The experimental results show full control over the single unit cell pole and zero, switching the unit cell transfer function between a notch filter and a bandpass filter, narrowing the notch width down to 400 MHz, and tuning the center wavelength over the full free spectral range (FSR) of 10 GHz. Theoretical and experimental results show tuning dynamics and associated optical losses in the reconfigurable filters. The full-control of each of the four cascaded single unit cells resulted in demonstrations of a number of fourth-order transfer functions. The multimedia experimental data show live tuning and reconfiguration of optical lattice filters. PMID:21747479

  4. Illumination robust change detection with CMOS imaging sensors

    NASA Astrophysics Data System (ADS)

    Rengarajan, Vijay; Gupta, Sheetal B.; Rajagopalan, A. N.; Seetharaman, Guna

    2015-05-01

    Change detection between two images in the presence of degradations is an important problem in the computer vision community, more so for the aerial scenario which is particularly challenging. Cameras mounted on moving platforms such as aircrafts or drones are subject to general six-dimensional motion as the motion is not restricted to a single plane. With CMOS cameras increasingly in vogue due to their low power consumption, the inevitability of rolling-shutter (RS) effect adds to the challenge. This is caused by sequential exposure of rows in CMOS cameras unlike conventional global shutter cameras where all pixels are exposed simultaneously. The RS effect is particularly pronounced in aerial imaging since each row of the imaging sensor is likely to experience a different motion. For fast-moving platforms, the problem is further compounded since the rows are also affected by motion blur. Moreover, since the two images are shot at different times, illumination differences are common. In this paper, we propose a unified computational framework that elegantly exploits the scarcity constraint to deal with the problem of change detection in images degraded by RS effect, motion blur as well as non-global illumination differences. We formulate an optimization problem where each row of the distorted image is approximated as a weighted sum of the corresponding rows in warped versions of the reference image due to camera motion within the exposure period to account for geometric as well as photometric differences. The method has been validated on both synthetic and real data.

  5. A 50Mbit/Sec. CMOS Video Linestore System

    NASA Astrophysics Data System (ADS)

    Jeung, Yeun C.

    1988-10-01

    This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

  6. Review of radiation damage studies on DNW CMOS MAPS

    NASA Astrophysics Data System (ADS)

    Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.; Zucca, S.; Bettarini, S.; Rizzo, G.; Morsani, F.; Bosisio, L.; Rashevskaya, I.; Cindro, V.

    2013-12-01

    Monolithic active pixel sensors fabricated in a bulk CMOS technology with no epitaxial layer and standard resistivity (10 Ω cm) substrate, featuring a deep N-well as the collecting electrode (DNW MAPS), have been exposed to γ-rays, up to a final dose of 10 Mrad (SiO2), and to neutrons from a nuclear reactor, up to a total 1 MeV neutron equivalent fluence of about 3.7 ·1013cm-2. The irradiation campaign was aimed at studying the effects of radiation on the most significant parameters of the front-end electronics and on the charge collection properties of the sensors. Device characterization has been carried out before and after irradiations. The DNW MAPS irradiated with 60Co γ-rays were also subjected to high temperature annealing (100 °C for 168 h). Measurements have been performed through a number of different techniques, including electrical characterization of the front-end electronics and of DNW diodes, laser stimulation of the sensors and tests with 55Fe and 90Sr radioactive sources. This paper reviews the measurement results, their relation with the damage mechanisms underlying performance degradation and provides a new comparison between DNW devices and MAPS fabricated in a CMOS process with high resistivity (1 kΩ cm) epitaxial layer.

  7. CMOS-TDI detector technology for reconnaissance application

    NASA Astrophysics Data System (ADS)

    Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

    2014-10-01

    The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

  8. IR CMOS: near infrared enhanced digital imaging (Presentation Recording)

    NASA Astrophysics Data System (ADS)

    Pralle, Martin U.; Carey, James E.; Joy, Thomas; Vineis, Chris J.; Palsule, Chintamani

    2015-08-01

    SiOnyx has demonstrated imaging at light levels below 1 mLux (moonless starlight) at video frame rates with a 720P CMOS image sensor in a compact, low latency camera. Low light imaging is enabled by the combination of enhanced quantum efficiency in the near infrared together with state of the art low noise image sensor design. The quantum efficiency enhancements are achieved by applying Black Silicon, SiOnyx's proprietary ultrafast laser semiconductor processing technology. In the near infrared, silicon's native indirect bandgap results in low absorption coefficients and long absorption lengths. The Black Silicon nanostructured layer fundamentally disrupts this paradigm by enhancing the absorption of light within a thin pixel layer making 5 microns of silicon equivalent to over 300 microns of standard silicon. This results in a demonstrate 10 fold improvements in near infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Applications include surveillance, nightvision, and 1064nm laser see spot. Imaging performance metrics will be discussed. Demonstrated performance characteristics: Pixel size : 5.6 and 10 um Array size: 720P/1.3Mpix Frame rate: 60 Hz Read noise: 2 ele/pixel Spectral sensitivity: 400 to 1200 nm (with 10x QE at 1064nm) Daytime imaging: color (Bayer pattern) Nighttime imaging: moonless starlight conditions 1064nm laser imaging: daytime imaging out to 2Km

  9. W-CMOS blanking device for projection multibeam lithography

    NASA Astrophysics Data System (ADS)

    Jurisch, Michael; Irmscher, Mathias; Letzkus, Florian; Eder-Kapl, Stefan; Klein, Christof; Loeschner, Hans; Piller, Walter; Platzgummer, Elmar

    2010-05-01

    As the designs of future mask nodes become more and more complex the corresponding pattern writing times will rise significantly when using single beam writing tools. Projection multi-beam lithography [1] is one promising technology to enhance the throughput compared to state of the art VSB pattern generators. One key component of the projection multi-beam tool is an Aperture Plate System (APS) to form and switch thousands of individual beamlets. In our present setup a highly parallel beam is divided into 43,008 individual beamlets by a Siaperture- plate. These micrometer sized beams pass through larger openings in a blanking-plate and are individually switched on and off by applying a voltage to blanking-electrodes which are placed around the blanking-plate openings. A charged particle 200x reduction optics demagnifies the beamlet array to the substrate. The switched off beams are filtered out in the projection optics so that only the beams which are unaffected by the blanking-plate are projected to the substrate with 200x reduction. The blanking-plate is basically a CMOS device for handling the writing data. In our work the blanking-electrodes are fabricated using CMOS compatible add on processes like SiO2-etching or metal deposition and structuring. A new approach is the implementation of buried tungsten electrodes for beam blanking.

  10. A CMOS active pixel sensor for retinal stimulation

    NASA Astrophysics Data System (ADS)

    Prydderch, Mark L.; French, Marcus J.; Mathieson, Keith; Adams, Christopher; Gunning, Deborah; Laudanski, Jonathan; Morrison, James D.; Moodie, Alan R.; Sinclair, James

    2006-02-01

    Degenerative photoreceptor diseases, such as age-related macular degeneration and retinitis pigmentosa, are the most common causes of blindness in the western world. A potential cure is to use a microelectronic retinal prosthesis to provide electrical stimulation to the remaining healthy retinal cells. We describe a prototype CMOS Active Pixel Sensor capable of detecting a visual scene and translating it into a train of electrical pulses for stimulation of the retina. The sensor consists of a 10 x 10 array of 100 micron square pixels fabricated on a 0.35 micron CMOS process. Light incident upon each pixel is converted into output current pulse trains with a frequency related to the light intensity. These outputs are connected to a biocompatible microelectrode array for contact to the retinal cells. The flexible design allows experimentation with signal amplitudes and frequencies in order to determine the most appropriate stimulus for the retina. Neural processing in the retina can be studied by using the sensor in conjunction with a Field Programmable Gate Array (FPGA) programmed to behave as a neural network. The sensor has been integrated into a test system designed for studying retinal response. We present the most recent results obtained from this sensor.

  11. CMOS: Efficient Clustered Data Monitoring in Sensor Networks

    PubMed Central

    2013-01-01

    Tiny and smart sensors enable applications that access a network of hundreds or thousands of sensors. Thus, recently, many researchers have paid attention to wireless sensor networks (WSNs). The limitation of energy is critical since most sensors are battery-powered and it is very difficult to replace batteries in cases that sensor networks are utilized outdoors. Data transmission between sensor nodes needs more energy than computation in a sensor node. In order to reduce the energy consumption of sensors, we present an approximate data gathering technique, called CMOS, based on the Kalman filter. The goal of CMOS is to efficiently obtain the sensor readings within a certain error bound. In our approach, spatially close sensors are grouped as a cluster. Since a cluster header generates approximate readings of member nodes, a user query can be answered efficiently using the cluster headers. In addition, we suggest an energy efficient clustering method to distribute the energy consumption of cluster headers. Our simulation results with synthetic data demonstrate the efficiency and accuracy of our proposed technique. PMID:24459444

  12. High-stage analog accumulator for TDI CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Jianxin, Li; Fujun, Huang; Yong, Zong; Jing, Gao

    2016-02-01

    The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is employed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature (PVT) variations. The post layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 dB, while an ideal value is 21.072 dB. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. Furthermore, it is promising to design a higher stage accumulator based on the proposed structure. Project supported by the National Natural Science Foundation of China (Nos. 61404090, 61434004).

  13. A CMOS Imager with Focal Plane Compression using Predictive Coding

    NASA Technical Reports Server (NTRS)

    Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

    2007-01-01

    This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

  14. CMOS-compatible active thermopiles for noise-added theory

    NASA Astrophysics Data System (ADS)

    Shen, Chih-Hsiung; Hou, Kuan-Chou

    2004-05-01

    Recently a novel signal processing theory related with noise has grown and proven. Certain complex systems can improve performance with added optimal noise that classical theory cannot explain. Their behavior may be represented by a simplified scheme that combines both a deterministic and stochastic source. To that end, we are using noise in remote temperature sensing system to enhance their function without altering the system. A new investigation of noise added scheme has been realized by an embedded heater for CMOS compatible thermoelectric infrared sensor. The design and fabrication of thermopile sensors are realized by using 1.2μm CMOS IC technology combined with a subsequent anisotropic front-side etching. We firstly develop an active thermopile with a heater embedded which is easily and naturally driven by a noise generation circuit. The stochastic resonance theory can be realized as a reduction in threshold of temperature detection. We have shown the possibility of improving the performance of remote temperature sensing system in the presence of noise. The strategy depends on the application. Stochastic resonance can reduce threshold detection resolution and greatly improve the temperature detection limit with a low cost scheme without using higher resolution ADC.

  15. Planarization for the integration of CMOS and micromirror arrays

    NASA Astrophysics Data System (ADS)

    Zheng, Yun; Dutta, Mitra B.; Kotecki, Carl A.; Zincke, Christian A.

    2002-07-01

    A large format individually addressable Micro-Mirror-Array (MMA) has been developed at NASA, GSFC for possible application in the Next Generation Space Telescope (NGST). The 100micron X100micron aluminum micro-mirrors are built on top of CMOS driven address and driver circuit for individual addressing. The high voltage CMOS fabrication process produces about 2.8microns surface roughness on the silicon wafer. The wafer surface is planarized before integration of the MMA. Three different planarization materials were evaluated; polyimide, spin-on glass and BCB. BCB showed the best results for our application. A single layer of BCB coating reduced the surface topology from 2.8micron to less than 1,700Angstroms and two layers of BCB coating reduced the surface topology to about 600Angstroms. Since the MMA has to operate at 30K for the NGST application, a wafer coated with cured BCB was dunk tested in liquid nitrogen at 77K and no cracks were found after thermal cycling. For specific application in NGST, the optical reflectance of BCB was measured at 40K over 1-5micron wavelength range and the results showed that BCB could absorb 30-40 percent of infrared light over this range. Details of coating, curing and etching properties of BCB are discussed along with its low temperature optical properties.

  16. An integrated CMOS high data rate transceiver for video applications

    NASA Astrophysics Data System (ADS)

    Yaping, Liang; Dazhi, Che; Cheng, Liang; Lingling, Sun

    2012-07-01

    This paper presents a 5 GHz CMOS radio frequency (RF) transceiver built with 0.18 μm RF-CMOS technology by using a proprietary protocol, which combines the new IEEE 802.11n features such as multiple-in multiple-out (MIMO) technology with other wireless technologies to provide high data rate robust real-time high definition television (HDTV) distribution within a home environment. The RF frequencies cover from 4.9 to 5.9 GHz: the industrial, scientific and medical (ISM) band. Each RF channel bandwidth is 20 MHz. The transceiver utilizes a direct up transmitter and low-IF receiver architecture. A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration. The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude (EVM) at -3 dBm output power.

  17. Custom CMOS Reed Solomon coder for the Hubble Space Telescope

    NASA Technical Reports Server (NTRS)

    Whitaker, S.; Cameron, K.; Owsley, P.; Maki, G.

    1990-01-01

    A VLSI coder is presented that can function either as an encoder or decoder for Reed-Solomon codes. VLSI is one approach to implementing high-performance Reed-Solomon decoders. There are three VLSI technologies that could be used: gate arrays, standard cells, and full custom. The first two approaches are relatively easy to implement, but are limited in both performance and density. Full-custom VLSI is used to achieve both circuit density and speed, and allows control of the amount of interconnect. Speed, which is a function of capacitance, which is a function of interconnect, is an important parameter in high-performance VLSI. A single 8.2 mm x 8.4 mm, 200,000 transistor CMOS chip implementation of the Reed-Solomon code required by the Hubble Space Telescope is reported. The chip features a 10-MHz sustained byte rate independent of error pattern. The 1.6-micron CMOS integrated circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths up to 255 bytes and shortened codes are supported with no external buffering. Erasure corrections and random error corrections are supported with programmable correction of up to 10 symbol errors. Correction time is independent of error pattern and the number of errors in the incoming message.

  18. 3D integration of sub-surface photonics with CMOS

    NASA Astrophysics Data System (ADS)

    Jalali, Bahram; Indukuri, Tejaswi; Koonath, Prakash

    2006-02-01

    The integration of photonics and electronics on a single silicon substrate requires technologies that can add optical functionalities without significantly sacrificing valuable wafer area. To this end, we have developed an innovative fabrication process, called SIMOX 3-D Sculpting, that enables monolithic optoelectronic integration in a manner that does not compromise the economics of CMOS manufacturing. In this technique, photonic devices are realized in subsurface silicon layers that are separated from the surface silicon layer by an intervening SiO II layer. The surface silicon layer may then be utilized for electronic circuitry. SIMOX 3-D sculpting involves (1) the implantation of oxygen ions into a patterned silicon substrate followed by (2) high temperature anneal to create buried waveguide-based photonic devices. This process has produced subterranean microresonators with unloaded quality factors of 8000 and extinction ratios >20dB. On the surface silicon layers, MOS transistor structures have been fabricated. The small cross-sectional area of the waveguides lends itself to the realization of nonlinear optical devices. We have previously demonstrated spectral broadening and continuum generation in silicon waveguides utilizing Kerr optical nonlinearity. This may be combined with microresonator filters for on-chip supercontiuum generation and spectral carving. The monolithic integration of CMOS circuits and optical modulators with such multi-wavelength sources represent an exciting avenue for silicon photonics.

  19. Single phase dynamic CMOS PLA using charge sharing technique

    NASA Technical Reports Server (NTRS)

    Dhong, Y. B.; Tsang, C. P.

    1991-01-01

    A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

  20. Single donor electronics and quantum functionalities with advanced CMOS technology

    NASA Astrophysics Data System (ADS)

    Jehl, Xavier; Niquet, Yann-Michel; Sanquer, Marc

    2016-03-01

    Recent progresses in quantum dots technology allow fundamental studies of single donors in various semiconductor nanostructures. For the prospect of applications figures of merits such as scalability, tunability, and operation at relatively large temperature are of prime importance. Beyond the case of actual dopant atoms in a host crystal, similar arguments hold for small enough quantum dots which behave as artificial atoms, for instance for single spin control and manipulation. In this context, this experimental review focuses on the silicon-on-insulator devices produced within microelectronics facilities with only very minor modifications to the current industrial CMOS process and tools. This is required for scalability and enabled by shallow trench or mesa isolation. It also paves the way for real integration with conventional circuits, as illustrated by a nanoscale device coupled to a CMOS circuit producing a radio-frequency drive on-chip. At the device level we emphasize the central role of electrostatics in etched silicon nanowire transistors, which allows to understand the characteristics in the full range from zero to room temperature.

  1. Single donor electronics and quantum functionalities with advanced CMOS technology.

    PubMed

    Jehl, Xavier; Niquet, Yann-Michel; Sanquer, Marc

    2016-03-16

    Recent progresses in quantum dots technology allow fundamental studies of single donors in various semiconductor nanostructures. For the prospect of applications figures of merits such as scalability, tunability, and operation at relatively large temperature are of prime importance. Beyond the case of actual dopant atoms in a host crystal, similar arguments hold for small enough quantum dots which behave as artificial atoms, for instance for single spin control and manipulation. In this context, this experimental review focuses on the silicon-on-insulator devices produced within microelectronics facilities with only very minor modifications to the current industrial CMOS process and tools. This is required for scalability and enabled by shallow trench or mesa isolation. It also paves the way for real integration with conventional circuits, as illustrated by a nanoscale device coupled to a CMOS circuit producing a radio-frequency drive on-chip. At the device level we emphasize the central role of electrostatics in etched silicon nanowire transistors, which allows to understand the characteristics in the full range from zero to room temperature. PMID:26871255

  2. Large CMOS imager using hadamard transform based multiplexing

    NASA Technical Reports Server (NTRS)

    Karasik, Boris S.; Wadsworth, Mark V.

    2005-01-01

    We have developed a concept design for a large (10k x 10k) CMOS imaging array whose elements are grouped in small subarrays with N pixels in each. The subarrays are code-division multiplexed using the Hadamard Transform (HT) based encoding. The Hadamard code improves the signal-to-noise (SNR) ratio to the reference of the read-out amplifier by a factor of N^1/2. This way of grouping pixels reduces the number of hybridization bumps by N. A single chip layout has been designed and the architecture of the imager has been developed to accommodate the HT base multiplexing into the existing CMOS technology. The imager architecture allows for a trade-off between the speed and the sensitivity. The envisioned imager would operate at a speed >100 fps with the pixel noise < 20 e-. The power dissipation would be 100 pW/pixe1. The combination of the large format, high speed, high sensitivity and low power dissipation can be very attractive for space reconnaissance applications.

  3. Monolithic integration of high bandwidth waveguide coupled Ge photodiode in a photonic BiCMOS process

    NASA Astrophysics Data System (ADS)

    Lischke, S.; Knoll, D.; Zimmermann, L.

    2015-03-01

    Monolithic integration of photonic functionality in the frontend-of-line (FEOL) of an advanced microelectronics technology is a key step towards future communication applications. This combines photonic components such as waveguides, couplers, modulators, and photo detectors with high-speed electronics plus shortest possible interconnects crucial for high-speed performance. Integration of photonics into CMOS FEOL is therefore in development for quite some time reaching 90nm node recently [1]. However, an alternative to CMOS is high-performance BiCMOS, offering significant advantages for integrated photonics-electronics applications with regard to cost and RF performance. We already presented results of FEOL integration of photonic components in a high-performance SiGe:C BiCMOS baseline to establish a novel, photonic BiCMOS process. Process cornerstone is a local-SOI approach which allows us to fabricate SOI-based, thus low-loss photonic components in a bulk BiCMOS environment [2]. A monolithically integrated 10Gbit/sec Silicon modulator with driver was shown here [3]. A monolithically integrated 25Gbps receiver was presented in [4], consisting of 200GHz bipolar transistors and CMOS devices, low-loss waveguides, couplers, and highspeed Ge photo diodes showing 3-dB bandwidth of 35GHz, internal responsivity of more than 0.6A/W at λ= 1.55μm, and ~ 50nA dark current at 1V. However, the BiCMOS-given thermal steps cause a significant smearing of the Germanium photo diodes doping profile, limiting the photo diode performance. Therefore, we introduced implantation of non-doping elements to overcome such limiting factors, resulting in photo diode bandwidths of more than 50GHz even under the effect of thermal steps necessary when the diodes are integrated in a high performance BiCMOS process.

  4. Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

    NASA Technical Reports Server (NTRS)

    Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

    2009-01-01

    In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

  5. High-performance VGA-resolution digital color CMOS imager

    NASA Astrophysics Data System (ADS)

    Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

    1999-04-01

    This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be suitable for a variety of color imaging applications including still/full motion imaging, security/surveillance, and teleconferencing/multimedia among other high performance, cost sensitive, low power consumer applications.

  6. A platform for monolithic CMOS-MEMS integration on SOI wafers

    NASA Astrophysics Data System (ADS)

    Villarroya, María; Figueras, Eduard; Montserrat, Josep; Verd, Jaume; Teva, Jordi; Abadal, Gabriel; Pérez Murano, Francesc; Esteve, Jaume; Barniol, Núria

    2006-10-01

    A new platform for micro- and nano-electromechanical systems based on crystalline silicon as the structural layer in CMOS substrates is presented. This platform is fabricated using silicon on insulator (SOI) substrates, which allows the monolithic integration of the mechanical transducer on crystalline silicon while the characteristics of the structural layer are kept independent from the CMOS technology. We report the design characteristics, the fabrication process and an example of application of the CMOS SOI-MEMS platform to obtain a mass sensor based on a crystalline silicon resonating cantilever.

  7. CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

    PubMed Central

    Guo, Nan; Cheung, Ka Wai; Wong, Hiu Tung; Ho, Derek

    2014-01-01

    Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art. PMID:25365460

  8. Top-Down CMOS-NEMS Polysilicon Nanowire with Piezoresistive Transduction

    PubMed Central

    Marigó, Eloi; Sansa, Marc; Pérez-Murano, Francesc; Uranga, Arantxa; Barniol, Núria

    2015-01-01

    A top-down clamped-clamped beam integrated in a CMOS technology with a cross section of 500 nm × 280 nm has been electrostatic actuated and sensed using two different transduction methods: capacitive and piezoresistive. The resonator made from a single polysilicon layer has a fundamental in-plane resonance at 27 MHz. Piezoresistive transduction avoids the effect of the parasitic capacitance assessing the capability to use it and enhance the CMOS-NEMS resonators towards more efficient oscillator. The displacement derived from the capacitive transduction allows to compute the gauge factor for the polysilicon material available in the CMOS technology. PMID:26184222

  9. A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

    PubMed

    Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

    2012-01-11

    Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. PMID:22141918

  10. Novel CMOS readout techniques for uncooled pyroelectric IR FPA

    NASA Astrophysics Data System (ADS)

    Sun, Tai-Ping; Chin, Yuan-Lung; Chung, Wen-Yaw; Hsiung, Shen-Kan; Chou, Jung-Chuan

    1998-09-01

    Based on the application of the source follower per detector (SFD) input biasing technique, a new redout structure for the IR focal-plane-array (FPA), called the variable gain source follower per detector (VGSFD) is proposed and analyzed. The readout circuit of VGSFD of a unit cell of pyroelectric sensor under investigation, is composed of a source follower per detector circuit, high gain amplifier, and the reset switch. The VGSFD readout chip has been designed in 0.5 micrometers double-poly-double-metal n-well CMOS technology in various formats from 8 by 8 to 128 by 128. The experimental 8 by 8 VGSFD measurement results of the fabricated readout chip at room temperature have successfully verified both the readout function and performance. The high gain, low power, high sensitivity readout performances are achieved in a 50 by 50 micrometers (superscript 2) pixel size.

  11. An Approach for Self-Timed Synchronous CMOS Circuit Design

    NASA Technical Reports Server (NTRS)

    Walker, Alvernon; Lala, Parag K.

    2001-01-01

    In this letter we present a timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modi@ the circuit clock period. This letter is concluded with an example of the proposed approach applied to a static CMOS ripple-carry adder.

  12. Triple inverter pierce oscillator circuit suitable for CMOS

    DOEpatents

    Wessendorf; Kurt O.

    2007-02-27

    An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

  13. A new visible watermarking technique applied to CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Yu, Pingping; Shang, Yan; Li, Chunming

    2013-10-01

    This paper presents a new visible watermarking solution for CMOS image sensor which can enhance secure features of captured images. Visible watermarks are embedded in the Bayer format image data and can be transferred by the subsequent interpolation process. A piecewise function is setup based on the gray scale resolution characteristics of human eyes. Watermark stretch factor can be adaptively chosen according to the gray value of the current pixel. The advantage of this algorithm is that the watermark has the same visibility in different image brightness region. A number of color images have been used to test the method. In order to check the robustness of watermarked images, we conducted adding noise and filtering experiments, results show that the visibility of watermark is also good after the experiments. The approach allows a digital watermark to be embedded in an image immediately upon its capture, before leaving the imaging chip.

  14. A portable swappable method scientific CMOS image data storage system

    NASA Astrophysics Data System (ADS)

    Liu, Wen-long; Pi, Hai-feng; Hu, Bing-liang; Gao, Jia-rui

    2015-11-01

    In the field of deep space exploration, the detector needs high-speed data real-time transmission and large capacity storage. SATA(Serial advanced technology attachment) as a new generation of interface protocols, SATA interface hard disk has the advantages of with large storage capacity, high transmission rate, the cheap price, data is not lost when power supply drop, so it is suitable for used in high speed large capacity data storage system. This paper by using Kintex-7 XCE7K325T XILINK series FPGA, the data of scientific CMOS CIS2521F through the SATA controller is stored in the hard disk. If the hard disk storage is full, it will automatically switch to the next hard disk.

  15. A CMOS frequency generation module for 60-GHz applications

    NASA Astrophysics Data System (ADS)

    Chunyuan, Zhou; Lei, Zhang; Hongrui, Wang; He, Qian

    2012-08-01

    A frequency generation module for 60-GHz transceivers and phased array systems is presented in this paper. It is composed of a divide-by-2 current mode logic divider (CML) and a doubler in push-push configuration. Benefiting from the CML structure and push-push configuration, the proposed frequency generation module has a wide operating frequency range to cover process, voltage, and temperature variation. It is implemented in a 90-nm CMOS process, and occupies a chip area of 0.64 × 0.65 mm2 including pads. The measurement results show that the designed frequency generation module functions properly with input frequency over 15 GHz to 25 GHz. The whole chip dissipates 12.1 mW from a 1.2-V supply excluding the output buffers.

  16. Back-illuminated CMOS APS with low crosstalk level

    NASA Astrophysics Data System (ADS)

    David, Y.; Efron, U.

    2007-09-01

    A new technological solution for backside illuminated CMOS imagers is proposed. The pixel area consists of an n-well/ substrate photo diode and a deep p-well, which contains the APS pixel circuitry as well as additional application specific circuits. This structure was analyzed using Silvaco's ATLAS device simulator. Simulation results show that this structure provides low cross-talk, high photo response and effectively shields the pixel circuitry from the photo charges generated in the substrate. The deep p-well pixel technology allows increasing the thickness of the die up to 30 micrometers, thus improving its mechanical ruggedness following the thinning process. Such deep p-well imager structure will also be integrated into the Image Transceiver Device, which combines a front side LCOS micro display with a back-illuminated imager.

  17. An Improved Equivalent Simulation Model for CMOS Integrated Hall Plates

    PubMed Central

    Xu, Yue; Pan, Hong-Bin

    2011-01-01

    An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model’s simulation results are in good agreement with the classic experimental results reported in the literature. PMID:22163955

  18. A 20 MHz CMOS reorder buffer for a superscalar microprocessor

    NASA Technical Reports Server (NTRS)

    Lenell, John; Wallace, Steve; Bagherzadeh, Nader

    1992-01-01

    Superscalar processors can achieve increased performance by issuing instructions out-of-order from the original sequential instruction stream. Implementing an out-of-order instruction issue policy requires a hardware mechanism to prevent incorrectly executed instructions from updating register values. A reorder buffer can be used to allow a superscalar processor to issue instructions out-of-order and maintain program correctness. This paper describes the design and implementation of a 20MHz CMOS reorder buffer for superscalar processors. The reorder buffer is designed to accept and retire two instructions per cycle. A full-custom layout in 1.2 micron has been implemented, measuring 1.1058 mm by 1.3542 mm.

  19. Design of a CMOS multi-mode GNSS receiver VCO

    NASA Astrophysics Data System (ADS)

    Qiang, Long; Yiqi, Zhuang; Yue, Yin; Zhenrong, Li

    2012-05-01

    A voltage-controlled oscillator (VCO) with dual stages of accumulation mode varactors for a multi-mode global navigation satellite system (GNSS) application, which adopts sigma-delta fractional-N technology in the synthesizer, is presented. The structure is selected to optimize the frequency coverage and tuning linearity, based on a general analysis of the parasitic capacitance in the coarse tuning switch bank cells, which cover the global positioning system (GPS) and Beidou (BD) bands. The VCO implemented in the 0.18 μm CMOS process can cover the GPS L1, BD B1, B2 and B3 bands with sufficient margin, and exhibits low phase noise by using this tuning curve linearization technique. The equalized Kvco characteristic behavior further offers a wide voltage tuning range and improves the stability of the closed loop.

  20. A radiation hardened SONOS/CMOS EEPROM family

    NASA Astrophysics Data System (ADS)

    Klein, V. F.; Wood, G. M.; Buller, J. F.; Murray, J. R.; Rodriquez, J. L.

    1990-07-01

    There has long been a need for fast read nonvolatile, rad hard memories for military and space applications. Recent advances in Electrically Erasably Programmable Read Only Memory (EEPROM) technology now allow this need to be met for many applications. Harris/Sandia have developed a 16k and a 256k rad hard EEPROM. The EEPROMs utilize a Silicon Oxide Nitride Oxide Silicon (SONOS) memory transistor integrated into a 2 microns rad hard two level metal CMOS process. Both the 16k and the 256k parts were designed to interface with the Intel 8085 or 80C51 and National 32000 series microprocessors and feature page and block clear modes. Both parts are functionally identical, and are produced by the same fabrication process. They are also pin for pin compatible with each other, except for the extra address and ground pins on the 256k. The characteristics of this EEPROM family are described.

  1. Wide Dynamic Range CMOS Potentiostat for Amperometric Chemical Sensor

    PubMed Central

    Wang, Wei-Song; Kuo, Wei-Ting; Huang, Hong-Yi; Luo, Ching-Hsing

    2010-01-01

    Presented is a single-ended potentiostat topology with a new interface connection between sensor electrodes and potentiostat circuit to avoid deviation of cell voltage and linearly convert the cell current into voltage signal. Additionally, due to the increased harmonic distortion quantity when detecting low-level sensor current, the performance of potentiostat linearity which causes the detectable current and dynamic range to be limited is relatively decreased. Thus, to alleviate these irregularities, a fully-differential potentiostat is designed with a wide output voltage swing compared to single-ended potentiostat. Two proposed potentiostats were implemented using TSMC 0.18-μm CMOS process for biomedical application. Measurement results show that the fully differential potentiostat performs relatively better in terms of linearity when measuring current from 500 pA to 10 uA. Besides, the dynamic range value can reach a value of 86 dB. PMID:22294899

  2. Accelerated life testing effects on CMOS microcircuit characteristics

    NASA Technical Reports Server (NTRS)

    1980-01-01

    The 250 C, 200C and 125C accelerated tests are described. The wear-out distributions from the 250 and 200 C tests were used to estimate the activation energy between the two test temperatures. The duration of the 125 C test was not sufficient to bring the test devices into the wear-out region. It was estimated that, for the most complex of the three devices types, the activation energy between 200 C and 125 C should be at least as high as that between 250 C and 200 C. The practicality of the use of high temperature for the accelerated life tests from the point of view of durability of equipment is assessed. Guidlines for the development of accelerated life-test conditions are proposed. The use of the silicon nitride overcoat to improve the high temperature accelerated life-test characteristics of CMOS microcircuits is described.

  3. Enabling Solutions for 28 nm CMOS Advanced Junction Formation

    NASA Astrophysics Data System (ADS)

    Li, C. I.; Kuo, P.; Lai, H. H.; Ma, K.; Liu, R.; Wu, H. H.; Chan, M.; Yang, C. L.; Wu, J. Y.; Guo, B. N.; Colombeau, B.; Thirumal, T.; Arevalo, E.; Toh, T.; Shim, K. H.; Sun, H. L.; Wu, T.; Lu, S.

    2011-01-01

    Controlling short channel effects for further scaled CMOS is required to take full advantage of the introduction of high K/metal gate or stress induced carrier mobility enhancement. Ultra-Shallow junction formation is necessary to minimize the short channel effects. In this paper, we will discuss the challenges for 28 nm Ultra-Shallow Junction formations in terms of figure of merits of Rs/Xj and junction leakage. We will demonstrate that by adopting and integrating Carborane (CBH, C2B10H12) molecular implant and Phosphorus along with co-implantation and PTC II (VSEA Process Temperature Control) technology, sub-32 nm pLDD and nLDD junction targets can be timely achieved using traditional anneals. Those damage engineering solutions can be readily implemented on state-of-the-art 28 nm device manufacturing.

  4. A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

    NASA Technical Reports Server (NTRS)

    Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

    2014-01-01

    Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

  5. Radiation Performance of 1 Gbit DDR SDRAMs Fabricated in the 90 nm CMOS Technology Node

    NASA Technical Reports Server (NTRS)

    Ladbury, Raymond L.; Gorelick, Jerry L.; Berg, M. D.; Kim, H.; LaBel, K.; Friendlich, M.; Koga, R.; George, J.; Crain, S.; Yu, P.; Reed, R. A.

    2006-01-01

    We present Single Event Effect (SEE) and Total Ionizing Dose (TID) data for 1 Gbit DDR SDRAMs (90 nm CMOS technology) as well as comparing this data with earlier technology nodes from the same manufacturer.

  6. Discovery of heavy-ion induced latchup in CMOS/epi devices

    NASA Technical Reports Server (NTRS)

    Nichols, D. K.; Price, W. E.; Shoga, M. A.; Duffey, J.; Kolasinsky, W. A.

    1986-01-01

    The observance of latchup in CMOS/epi devices upon exposure to krypton ions is reported. The effect of epi layer thickness on latchup susceptibility is discussed. An approach to eliminating this effect is indicated.

  7. ''Normal'' tissues from humans exposed to radium contain an alteration in the c-mos locus

    SciTech Connect

    Huberman, E.; Schlenker, R.A.; Hardwick, J.P.

    1989-01-01

    The structures of a number of human proto-oncogenes from persons with internal systemic exposure to radium were analyzed by restriction enzyme digestion and southern blotting of their DNA. Two extra c-mos Eco R1 restriction-fragment-length bands of 5.0 kb and 5.5 kb were found in tissue DNA from six of seven individuals. The extra c-mos bands were detected in DNA from many, but not all, of the tissues of the individuals exposed to radium. Our results suggest that the c-mos restriction-fragment-length alterations (RFLA) found in individuals exposed to radium were induced rather than inherited, are epigenetic in origin, and most likely result from changes in the methylation of bases surrounding the single exon of the c-mos proto-oncogene. 7 refs., 3 figs., 2 tabs.

  8. Compressive Sensing Based Bio-Inspired Shape Feature Detection CMOS Imager

    NASA Technical Reports Server (NTRS)

    Duong, Tuan A. (Inventor)

    2015-01-01

    A CMOS imager integrated circuit using compressive sensing and bio-inspired detection is presented which integrates novel functions and algorithms within a novel hardware architecture enabling efficient on-chip implementation.

  9. Speckle-based modulation transfer function measurements for comparative evaluation of CCD and CMOS detector arrays

    NASA Astrophysics Data System (ADS)

    Fernández-Oliveras, Alicia; Pozo, Antonio M.; Rubiño, Manuel

    2013-01-01

    Charge-coupled device (CCD) and complementary metal-oxide semiconductor (CMOS) matrices offer excellent features in imaging systems. For assessing the suitability of each technology according to the application, the complete characterization of the detector arrays becomes necessary. A system is optically characterized by the modulation transfer function (MTF). We have comparatively studied the results provided by the speckle method for detectors of two types: CCD and CMOS. To do so, we first analysed the precision in determining the MTF of the CCD using two apertures at the exit port of an integrating sphere: a single and a double-slit. For the single-slit, we propose a new procedure of fitting the experimental data which overcomes the drawbacks of the conventional procedure. Since it offered lower uncertainty and better reproducibility, the single-slit was used for the study with the CMOS detector. Significant differences were found between the MTF of the CCD and the CMOS detectors.

  10. Prediction and measurement of radiation damage to CMOS devices on board spacecraft

    NASA Technical Reports Server (NTRS)

    Cliff, R. A.; Danchenko, V.; Stassinopoulos, E. G.; Sing, M.; Brucker, G. J.; Ohanian, R. S.

    1976-01-01

    The CMOS Radiation Effects Measurement (CREM) experiment is presently being flown on the Explorer-55. The purpose of the experiment is to evaluate device performance in the actual space radiation environment and to correlate the respective measurements to on-the-ground laboratory irradiation results. The experiment contains an assembly of C-MOS and P-MOS devices shielded in front by flat slabs of aluminum and by a practically infinite shield in the back. Predictions of radiation damage to C-MOS devices are based on standard environment models and computational techniques. A comparison of the shifts in CMOS threshold potentials, that is, those measured in space to those obtained from the on-the-ground simulation experiment with Co-60, indicates that the measured space damage is smaller than predicted by about a factor of 2-3 for thin shields, but agrees well with predictions for thicker shields.

  11. Commercial Buildings Characteristics, 1992

    SciTech Connect

    Not Available

    1994-04-29

    Commercial Buildings Characteristics 1992 presents statistics about the number, type, and size of commercial buildings in the United States as well as their energy-related characteristics. These data are collected in the Commercial Buildings Energy Consumption Survey (CBECS), a national survey of buildings in the commercial sector. The 1992 CBECS is the fifth in a series conducted since 1979 by the Energy Information Administration. Approximately 6,600 commercial buildings were surveyed, representing the characteristics and energy consumption of 4.8 million commercial buildings and 67.9 billion square feet of commercial floorspace nationwide. Overall, the amount of commercial floorspace in the United States increased an average of 2.4 percent annually between 1989 and 1992, while the number of commercial buildings increased an average of 2.0 percent annually.

  12. A low-noise, wide-band CMOS charge-sensitive preamplifier for use with APD/LSO PET detectors

    SciTech Connect

    Paulus, M.J.; Andreaco, M.S.; Binkley, D.M.; Rochelle, J.M.

    1996-06-01

    The recent emergence of LSO as a potential scintillator for positron emission tomography (PET) and recent improvements in avalanche photodiode (APD) technology offer encouragement that an APD/LSO based PET detector may be commercially viable in the near future. An important component of any APD/LSO based PET detector will be the preamplifier used to read out the low-level detector signals. Due to the large number of detectors (>18,000) in a high-resolution PET scanner, the preamplifier must be implemented as a monolithic integrated circuit. Additionally, in order to achieve the timing resolution required for high resolution PET, the preamplifier must have a large band-width and a low equivalent input noise voltage. This paper presents a CMOS charge-sensitive preamplifier design which uses local feedback to improve the performance of the common gate transistor. The modified cascode circuit is analyzed and compared with a previously reported simple folded cascode circuit. A prototype circuit was fabricated in a 2 {micro}m NWELL CMOS process. The prototype amplifier has a measured 10--90% rise-time of 7 ns with an external input capacitance of {approximately}6 pF and has an equivalent input noise voltage of {approximately}1.1 nV/rt-Hz above the flicker noise corner. A pulse height resolution of 14.3% FWHM and a timing resolution of 1.57 ns FWHM (vs. plastic) were obtained with the preamplifier, an Advanced Photonix 5 mm diameter beveled-edge APD and a 3.5 x 3.5 x 22 mm{sup 3} Teflon wrapped LSO crystal.

  13. CMOS-sensors for energy-resolved X-ray imaging

    NASA Astrophysics Data System (ADS)

    Doering, D.; Amar-Youcef, S.; Baudot, J.; Deveaux, M.; Dulinski, W.; Kachel, M.; Linnik, B.; Müntz, C.; Stroth, Joachim

    2016-01-01

    Due to their low noise, CMOS Monolithic Active Pixel Sensors are suited to sense X-rays with a few keV quantum energy, which is of interest for high resolution X-ray imaging. Moreover, the good energy resolution of the silicon sensors might be used to measure this quantum energy. Combining both features with the good spatial resolution of CMOS sensors opens the potential to build ``color sensitive" X-ray cameras. Taking such colored images is hampered by the need to operate the CMOS sensors in a single photon counting mode, which restricts the photon flux capability of the sensors. More importantly, the charge sharing between the pixels smears the potentially good energy resolution of the sensors. Based on our experience with CMOS sensors for charged particle tracking, we studied techniques to overcome the latter by means of an offline processing of the data obtained from a CMOS sensor prototype. We found that the energy resolution of the pixels can be recovered at the expense of reduced quantum efficiency. We will introduce the results of our study and discuss the feasibility of taking colored X-ray pictures with CMOS sensors.

  14. Alteration of the c-mos locus in ''normal'' tissues from humans exposed to radium

    SciTech Connect

    Hardwick, J.P.; Schlenker, R.A.; Huberman, E.

    1989-05-15

    The structure of a number of human protooncogenes of persons with internal systemic exposure to radium was analyzed by restriction enzyme digestion and Southern blotting of their DNA. Two extra c-mos EcoRI restriction fragment length bands of 5.0 and 5.5 kilobases were found in tissue DNA from six of seven such individuals. The extra c-mos bands were detected in DNA from many, but not all, of the tissues of the individuals exposed to radium. Kidney DNA, however, from three of four individuals exposed to radium contained these alterations; kidney DNA from six age-matched controls did not. The 5.0- and 5.5-kilobase bands, which were of a similar intensity, varied in their intensity with respect to that of the normal 2.5-kilobase band of the c-mos gene. The DNAs that have the polymorphic bands also appear to have a more complex c-mos methylation pattern. Our results suggest that the c-mos restriction fragment length alterations found in individuals exposed to radium were induced rather than inherited, are epigenetic in origin, and most likely result from changes in the methylation of bases surrounding the single exon of the c-mos protooncogene.

  15. Nanowatt-Power-Level Automatic Switch Combining ED-CMOS Circuit and LED

    NASA Astrophysics Data System (ADS)

    Utsunomiya, Fumiyasu; Douseki, Takakuni

    A nanowatt-power-level automatic switch that combines a multi-Vth CMOS level converter and an LED as a photodiode has been developed for a sensor application. The level converter is a single-input latch-type multi-Vth CMOS circuit featuring the use of an enhancement-mode nMOSFET and a depletion-mode common-gate nMOSFET as a pair of driver transistors. The ED-CMOS level converter cuts the DC current path; and the LED, which generates a high output voltage under illumination, suppresses the leakage current of the depletion-mode common-gate nMOSFET in the ED-CMOS level converter, resulting in nanowatt-order power dissipation. To verify the effectiveness of the ED-CMOS circuit, a prototype level converter was fabricated on a 0.6-µm CMOS process and used in an automatic switch in a wireless mouse. The switch is composed of two LEDs, a current-mirror circuit, the level converter, and a power switch MOSFET. It senses when a hand grabs or releases the mouse and automatically turns the mouse on or off, respectively. The measured power dissipation of the mouse is 3nW in the standby mode.

  16. CMOS-APS Detectors for Solar Physics: Lessons Learned during the SWAP Preflight Calibration

    NASA Astrophysics Data System (ADS)

    de Groof, A.; Berghmans, D.; Nicula, B.; Halain, J.-P.; Defise, J.-M.; Thibert, T.; Schühle, U.

    2008-05-01

    CMOS-APS imaging detectors open new opportunities for remote sensing in solar physics beyond what classical CCDs can provide, offering far less power consumption, simpler electronics, better radiation hardness, and the possibility of avoiding a mechanical shutter. The SWAP telescope onboard the PROBA2 technology demonstration satellite of the European Space Agency will be the first actual implementation of a CMOS-APS detector for solar physics in orbit. One of the goals of the SWAP project is precisely to acquire experience with the CMOS-APS technology in a real-live space science context. Such a precursor mission is essential in the preparation of missions such as Solar Orbiter where the extra CMOS-APS functionalities will be hard requirements. The current paper concentrates on specific CMOS-APS issues that were identified during the SWAP preflight calibration measurements. We will discuss the different readout possibilities that the CMOS-APS detector of SWAP provides and their associated pros and cons. In particular we describe the “image lag” effect, which results in a contamination of each image with a remnant of the previous image. We have characterised this effect for the specific SWAP implementation and we conclude with a strategy on how to successfully circumvent the problem and actually take benefit of it for solar monitoring.

  17. Research on spaceborne low light detection based on EMCCD and CMOS

    NASA Astrophysics Data System (ADS)

    Wu, Xingxing; Liu, Jinguo; Zhou, Huaide; Zhang, Boyan

    2015-10-01

    Electron Multiplying Charge Coupled Device(EMCCD) can realize read out noise of less than 1e- by promoting gain of charges with the charge multiplication principle and is suitable for low light imaging. With the development of back Illuminated CMOS technology CMOS with high quantum efficiency and less than 1.5e- read noise has been developed by Changchun Institute of Optics, Fine Mechanics and Physics(CIOMP). Spaceborne low light detection cameras based on EMCCD CCD201 and based on CMOS were respectively established and system noise models were founded. Low light detection performance as well as principle of spaceborne camera based on EMCCD and spaceborne camera based on CMOS were compared and analyzed. Results of analysis indicated that signal to noise(SNR) of spaceborne low light detection camera based on EMCCD would be 23.78 as radiance at entrance pupil of the camera was as low as 10-9 W/cm2/sr/?m at the focal plane temperature of 20C. Spaceborne low light detection camera worked in starring mode and the integration time was 2 second. SNR of low light detection camera based on CMOS would be 27.42 under the same conditions. If cooling systems were used and the temperature was lowered from 20C to -20C, SNR of low light detection camera based on EMCCD would be improved to 27.533 while SNR of low light detection camera based on CMOS would be improved to 27.79.

  18. A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

    NASA Astrophysics Data System (ADS)

    Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

    2013-03-01

    Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

  19. Thermochromism in Commercial Products

    NASA Astrophysics Data System (ADS)

    White, Mary Anne; Leblanc, Monique

    1999-09-01

    Many commercial products change color with a change of temperature. How do they do it? The processes responsible for the two major categories of commercial thermochromic coloring agents are presented, along with a description of applications of thermochromic materials.

  20. NASA commercial programs

    NASA Technical Reports Server (NTRS)

    1988-01-01

    An expanded role for the U.S. private sector in America's space future has emerged as a key national objective, and NASA's Office of Commercial Programs is providing a focus for action. The Office supports new high technology commercial space ventures, the commercial application of existing aeronautics and space technology, and expanded commercial access to available NASA capabilities and services. The progress NASA has made in carrying out its new assignment is highlighted.

  1. Commercialism in Schools.

    ERIC Educational Resources Information Center

    Larson, Kirstin

    2001-01-01

    This document gives voice to concerns raised by critics and supporters of commercialism in schools and provides brief descriptions of several important resources on this topic. "Commercial Activities in School" (U.S. General Accounting Office) reports on the nature and frequency of commercial activities in public schools, as well as the laws and…

  2. Commercial Banking Industry Survey.

    ERIC Educational Resources Information Center

    Bright Horizons Children's Centers, Cambridge, MA.

    Work and family programs are becoming increasingly important in the commercial banking industry. The objective of this survey was to collect information and prepare a commercial banking industry profile on work and family programs. Fifty-nine top American commercial banks from the Fortune 500 list were invited to participate. Twenty-two…

  3. Advanced source/drain and contact design for nanoscale CMOS

    NASA Astrophysics Data System (ADS)

    Vega, Reinaldo

    The development of nanoscale MOSFETs has given rise to increased attention paid to the role of parasitic source/drain and contact resistance as a performance-limiting factor. Dopant-segregated Schottky (DSS) source/drain MOSFETs have become popular in recent years to address this series resistance issue, since DSS source/drain regions comprise primarily of metal or metal silicide. The small source/drain extension (SDE) regions extending from the metallic contact regions are an important design parameter in DSS MOSFETs, since their size and concentration affect contact resistance, series resistance, band-to-band tunneling (BTBT), SDE tunneling, and direct source-to-drain tunneling (DSDT) leakage. This work investigates key design issues surrounding DSS MOSFETs from both a modeling and experimental perspective, including the effect of SDE design on ambipolar leakage, the effect of random dopant fluctuation (RDF) on specific contact resistivity, 3D FinFET source/drain and contact design optimization, and experimental methods to achieve tuning of the SDE region. It is found that DSS MOSFETs are appropriate for thin body high performance (HP) and low operating power (LOP) MOSFETs, but not low standby power (LSTP) MOSFETs, due to a trade-off between ambipolar leakage and contact resistance. It is also found that DSDT will not limit DSS MOSFET scalability, nor will RDF limit contact resistance scaling, at the end of the CMOS roadmap. Furthermore, it is found that SDE tunability in DSS MOSFETs is achievable in the real-world, for an implant-to-silicide (ITS) process, by employing fluorine implant prior to metal deposition and silicidation. This is found to open up the DSS process design space for the trade-off between SDE junction depth and contact resistance. Si1-xGex process technology is also explored, and Ge melt processing is found to be a promising low-cost alternative to epitaxial Si1-xGex growth for forming crystalline Si1-xGe x films. Finally, a new device structure is proposed, wherein a bulk Tri-Gate MOSFET utilizes high-k trench isolation (HTI) to achieve enhanced control over short channel effects. This structure (the HTI MOSFET) is shown, through 3D TCAD modeling, to extend bulk LSTP scalability to the end of the CMOS roadmap. In a direct performance comparison to FinFETs, the HTI MOSFET achieves competitive circuit delay.

  4. A digital output accelerometer using MEMS-based piezoelectric accelerometers and arrayed CMOS inverters with satellite capacitors

    NASA Astrophysics Data System (ADS)

    Kobayashi, T.; Okada, H.; Masuda, T.; Maeda, R.; Itoh, T.

    2011-06-01

    The present paper describes the development of a digital output accelerometer composed of microelectromechanical systems (MEMS)-based piezoelectric accelerometers and arrayed complementary metal-oxide-semiconductor (CMOS) inverters accompanied by capacitors. The piezoelectric accelerometers were fabricated from multilayers of Pt/Ti/PZT/Pt/Ti/SiO2 deposited on silicon-on-insulator (SOI) wafers. The fabricated piezoelectric accelerometers were connected to arrayed CMOS inverters. Each of the CMOS inverters was accompanied by a capacitor with a different capacitance called a 'satellite capacitor'. We have confirmed that the output voltage generated from the piezoelectric accelerometers can vary the output of the CMOS inverters from a high to a low level; the state of the CMOS inverters has turned from the 'off-state' into the 'on-state' when the output voltage of the piezoelectric accelerometers is larger than the threshold voltage of the CMOS inverters. We have also confirmed that the CMOS inverters accompanied by the larger satellite capacitor have become 'on-state' at a lower acceleration. On increasing the acceleration, the number of on-state CMOS inverters has increased. Assuming that the on-state and off-state of CMOS inverters correspond to logic '0' and '1', the present digital output accelerometers have expressed the accelerations of 2.0, 3.0, 5.0, and 5.5 m s - 2 as digital outputs of 111, 110, 100, and 000, respectively.

  5. Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

    NASA Technical Reports Server (NTRS)

    White, Mark; Cooper, Mark; Johnston, Allan

    2011-01-01

    Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

  6. Passive radiation detection using optically active CMOS sensors

    NASA Astrophysics Data System (ADS)

    Dosiek, Luke; Schalk, Patrick D.

    2013-05-01

    Recently, there have been a number of small-scale and hobbyist successes in employing commodity CMOS-based camera sensors for radiation detection. For example, several smartphone applications initially developed for use in areas near the Fukushima nuclear disaster are capable of detecting radiation using a cell phone camera, provided opaque tape is placed over the lens. In all current useful implementations, it is required that the sensor not be exposed to visible light. We seek to build a system that does not have this restriction. While building such a system would require sophisticated signal processing, it would nevertheless provide great benefits. In addition to fulfilling their primary function of image capture, cameras would also be able to detect unknown radiation sources even when the danger is considered to be low or non-existent. By experimentally profiling the image artifacts generated by gamma ray and β particle impacts, algorithms are developed to identify the unique features of radiation exposure, while discarding optical interaction and thermal noise effects. Preliminary results focus on achieving this goal in a laboratory setting, without regard to integration time or computational complexity. However, future work will seek to address these additional issues.

  7. A CMOS pressure sensor tag chip for passive wireless applications.

    PubMed

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-01-01

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation. PMID:25806868

  8. CMOS compatible polarization splitter using hybrid plasmonic waveguide.

    PubMed

    Chee, Jingyee; Zhu, Shiyang; Lo, G Q

    2012-11-01

    We design and experimentally demonstrate an ultrashort integrated polarization splitter on silicon-on-insulator (SOI) platform. Our polarization splitter uses a hybrid plasmonic waveguide as the middle waveguide in a three-core arrangement to achieve large birefringence, allowing only transverse-magnetic (TM) polarized light to directionally couple to the cross port of the directional coupler. Finite-difference time-domain (FDTD) and eigenmode expansive (EME) calculations show that the splitter can achieve an extinction ratio of greater than 15 dB with less than 0.5 dB insertion losses. The polarization splitter was fabricated on SOI platform using standard complementary metal-oxide-semiconductor (CMOS) technology and measured at telecommunications wavelengths. Extinction ratios of 12.3 dB and 13.9 dB for the transverse-electric (TE) and TM polarizations were obtained, together with insertion losses of 2.8 dB and 6.0 dB. PMID:23187351

  9. A new architecture of current-mode CMOS TDI Sensor

    NASA Astrophysics Data System (ADS)

    Ji, Cheng; Chen, Yongping

    2015-10-01

    Nowadays, CMOS sensors still suffer from the problem of low SNR, especially in the stage of low illumination and high relative scanning velocity. Lots of methods have been develop to overcome this problem. Among these researches, TDI (Time Delay Integration) architecture is a more natural choice, which is natively supported by CCD sensors. In this paper a new kind of proposed current-mode sensor is used to achieve TDI operation in analog domain. The circuit is composed of three main parts. At first, a current-type pixel is proposed, in which the active MOSFET is operated in the triode region to ensure the output current is linearly dependent on the gate voltage and avoid the reduction of threshold voltage in the traditional voltage mode pixels, such as 3T, 4T which use the source followers as its active part. Then a discrete double sampling (DDS) unit, which is operated in the form of currents is used to efficiently reduce the fixed pattern noise (FPN) and make the output is independent of reset voltage of pixels. For accumulation, an improved current mirror adder under controlled of timing circuits is proposed to overcome the problem of saturation suffered in voltage domain. Some main noise sources, especially come from analog sample and holds capacitors and switches is analyzed. Finally, simulation results with CSMC 0.5um technology and Cadence IC show that the proposed method is reasonable and efficient to improve the SNR.

  10. Noise analysis of a fully integrated CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Singh, Kalwant

    1999-03-01

    The read noise characteristics of a 3T photodiode-based CMOS active pixel image sensor IC is described. The sensor is fabricated in Hewlett Packard's standard 0.5 micrometers and 3.3V mixed-signal process. The read noise characteristic of the analog signal path is theoretically estimated by adding together the noise contributions of the pixel, column amplifier and programmable gain amplifier (PGA). The read noise of the imager is then measured as a function of the on-chip programmable gain with a HP9494 mixed-signal production tester. An analysis of the measured read noise is performed to separate the noise contribution into pre-PGA and post-PGA components. The measured pre-PGA noise component is compared to the calculated estimate of the analog signal path noise. The measured pre-PGA noise is found to be much smaller than the calculated estimate. Consistency is substantially improved if pixel kTC reset noise is excluded from the calculated estimate.

  11. Temperature impact on multiple-input CMOS gates delay

    NASA Astrophysics Data System (ADS)

    de Benito, C.; Bota, S.; Rosselló, J. L.; Segura, J.

    2007-05-01

    CMOS IC scaling has surpassed the 100nm barrier being now in the 65nm node with a rapid migration to the 35nm generation. In achieving the primary goals of technology scaling such as performance and density increase at a reduced cost per transistor, new side effects must be solved representing further challenges to the advance of the predicted roadmap. One of these challenges is related to the management of thermal-related effects such as hot-spots and overall junction temperature increase as they may have a significant impact on performance, power containment, circuit reliability, and even functionality. The adoption of adequate thermal management solutions requires a detailed analysis of the fundamental relationships governing the device and interconnect subsystem. Although much attention has been given to such analysis at the device and the logic inverter levels, less is known about such dependences in complex gates with transistor stacks. In this work we study the fundamental mechanisms underlying the temperature dependence of transistor stacks showing the key role of the stack dynamic threshold on the overall delay-temperature behavior at the gate level.

  12. A CMOS Smart Thermal Sensor for Biomedical Application

    NASA Astrophysics Data System (ADS)

    Lee, Ho-Yin; Chen, Shih-Lun; Luo, Ching-Hsing

    This paper describes a smart thermal sensing chip with an integrated vertical bipolar transistor sensor, a Sigma Delta Modulator (SDM), a Micro-Control Unit (MCU), and a bandgap reference voltage generator for biomedical application by using 0.18?m CMOS process. The npn bipolar transistors with the Deep N-Well (DNW) instead of the pnp bipolar transistor is first adopted as the sensor for good isolation from substrate coupling noise. In addition to data compression, Micro-Control Unit (MCU) plays an important role for executing auto-calibration by digitally trimming the bipolar sensor in parallel to save power consumption and to reduce feedback complexity. It is different from the present analog feedback calibration technologies. Using one sensor, instead of two sensors, to create two differential signals in 180 phase difference input to SDM is also a novel design of this work. As a result, in the range of 0C to 80C or body temperature (375C), the inaccuracy is less than 0.1C or 0.05C respectively with one-point calibration after packaging. The average power consumption is 268.4?W with 1.8V supply voltage.

  13. Circuit design for nuclear radiation test of CMOS multiplier chips

    SciTech Connect

    Lim, T.S.; Martin, R.L.; Hughes, H.L.

    1986-09-01

    This paper describes the design of a microprocessor-based electronic circuit to be used in testing the effects of nuclear radiation on a CMOS 8 x 8 multiplier chip. Knowledge of such effects is important for military and space applications of integrated circuits. The multiplier chip undergoing testing is attached to a DUT (device under test) board which is enclosed in a metal container. The container is then lowered to the cobalt 60 radiation source located at the bottom of a 15-ft-deep pool. The gamma-ray radiation test setup is schematically shown. The in-source test board containing the multiplier chip is attached to an 8085-based, single-board microcomputer (SDK-85) by a 30-ft multiconductor cable. Doses of gamma-ray radiation from cobalt 60 are applied in steps at increasing quantities until the multiplier chip, which is tested between doses, begins to malfunction. An 8085 assembly language program is used for functional test of the multiplier. The leakage current and the propagation delay time are also measured between doses.

  14. A 16-channel CMOS preamplifier for laser ranging radar receivers

    NASA Astrophysics Data System (ADS)

    Liu, Ru-qing; Zhu, Jing-guo; Jiang, Yan; Li, Meng-lin; Li, Feng

    2015-10-01

    A 16-channal front-end preamplifier array has been design in a 0.18um CMOS process for pulse Laser ranging radar receiver. This front-end preamplifier array incorporates transimpedance amplifiers(TIAs) and differential voltage post-amplifier(PAMP),band gap reference and other interface circuits. In the circuit design, the regulated cascade (RGC) input stage, Cherry-Hooper and active inductor peaking were employed to enhance the bandwidth. And in the layout design, by applying the layout isolation structure combined with P+ guard-ring(PGR), N+ guard-ring(NGR),and deep-n-well(DNW) for amplifier array, the crosstalk and the substrate noise coupling was reduced effectively. The simulations show that a single channel receiver front-end preamplifier achieves 95 dBΩ transimpedance gain and 600MHz bandwidth for 3 PF photodiode capacitance. The total power of 16-channel front-end amplifier array is about 800mW for 1.8V supply.

  15. A CMOS retinal neurostimulator capable of focussed, simultaneous stimulation.

    PubMed

    Dommel, N B; Wong, Y T; Lehmann, T; Dodds, C W; Lovell, N H; Suaning, G J

    2009-06-01

    Restoring vision to the blind by way of medical device technology has been an objective of several research teams for a number of years. It is known that spots of light-phosphenes-can be elicited by way of electrical stimulation of surviving retinal neurons. Beyond this our understanding of prosthetic vision remains rudimentary. We have designed and manufactured an integrated circuit neurostimulator with substantial versatility, able to provide focussed, simultaneous stimulation using current sources and sinks, steering the current to the intended site of stimulation. The ASIC utilizes high-voltage CMOS transistors in key circuits, to manage voltage compliance issues (due to an unknown or changing electrode/tissue interface impedance) given the relatively high stimulation thresholds necessary to elicit physiological excitation of retinal neurons. In addition, a unique multiplexing system comprised of electrodes arranged in a hexagonal mosaic is used, wherein each electrode can be addressed to be a stimulating electrode and all adjacent electrodes serve as the return path. This allows for simultaneous stimulation to be delivered while appropriately managing cross-talk between the stimulating electrodes. Test results indicate highly linear current sources and sinks (differential nonlinearity error of 0.13 least significant bits -2.6 microA), with the ASIC clearly able to provide focussed stimulation using electrodes immersed in a saline solution. PMID:19458399

  16. A CMOS retinal neurostimulator capable of focussed, simultaneous stimulation

    NASA Astrophysics Data System (ADS)

    Dommel, N. B.; Wong, Y. T.; Lehmann, T.; Dodds, C. W.; Lovell, N. H.; Suaning, G. J.

    2009-06-01

    Restoring vision to the blind by way of medical device technology has been an objective of several research teams for a number of years. It is known that spots of lightphosphenescan be elicited by way of electrical stimulation of surviving retinal neurons. Beyond this our understanding of prosthetic vision remains rudimentary. We have designed and manufactured an integrated circuit neurostimulator with substantial versatility, able to provide focussed, simultaneous stimulation using current sources and sinks, steering the current to the intended site of stimulation. The ASIC utilizes high-voltage CMOS transistors in key circuits, to manage voltage compliance issues (due to an unknown or changing electrode/tissue interface impedance) given the relatively high stimulation thresholds necessary to elicit physiological excitation of retinal neurons. In addition, a unique multiplexing system comprised of electrodes arranged in a hexagonal mosaic is used, wherein each electrode can be addressed to be a stimulating electrode and all adjacent electrodes serve as the return path. This allows for simultaneous stimulation to be delivered while appropriately managing cross-talk between the stimulating electrodes. Test results indicate highly linear current sources and sinks (differential nonlinearity error of 0.13 least significant bits -2.6 A), with the ASIC clearly able to provide focussed stimulation using electrodes immersed in a saline solution.

  17. High resolution, high bandwidth global shutter CMOS area scan sensors

    NASA Astrophysics Data System (ADS)

    Faramarzpour, Naser; Sonder, Matthias; Li, Binqiao

    2013-10-01

    Global shuttering, sometimes also known as electronic shuttering, enables the use of CMOS sensors in a vast range of applications. Teledyne DALSA Global shutter sensors are able to integrate light synchronously across millions of pixels with microsecond accuracy. Teledyne DALSA offers 5 transistor global shutter pixels in variety of resolutions, pitches and noise and full-well combinations. One of the recent generations of these pixels is implemented in 12 mega pixel area scan device at 6 um pitch and that images up to 70 frames per second with 58 dB dynamic range. These square pixels include microlens and optional color filters. These sensors also offer exposure control, anti-blooming and high dynamic range operation by introduction of a drain and a PPD reset gate to the pixel. The state of the art sense node design of Teledyne DALSA's 5T pixel offers exceptional shutter rejection ratio. The architecture is consistent with the requirements to use stitching to achieve very large area scan devices. Parallel or serial digital output is provided on these sensors using on-chip, column-wise analog to digital converters. Flexible ADC bit depth combined with windowing (adjustable region of interest, ROI) allows these sensors to run with variety of resolution/bandwidth combinations. The low power, state of the art LVDS I/O technology allows for overall power consumptions of less than 2W at full performance conditions.

  18. CMOS Image Sensor with a Built-in Lane Detector.

    PubMed

    Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%. PMID:22573983

  19. Submicron CMOS MIL-STD-1750A based mission processor

    NASA Astrophysics Data System (ADS)

    Coulon, Kenneth E.

    The author describes the design of a MIL-STD-1750A mission processor (MP), which is generally based on the US Air Force Pave Pillar architecture. The MP is composed of a power conditioner unit, a chassis assembly, and a set of SEM-E (3/4 ATR)-size common modules. The common modules utilize a set of seven complex submicrometer CMOS integrated circuits as building blocks. The internal design architecture features a dual PI-Bus for intermodule communication and a dual TM-Bus for operational test and maintenance. The MP is capable of over 22-million-instructions/s performance on the Defense Avionics Instructions Set (DAIS) mix and contains up to 2.56 million words of random-access memory and 288 thousand words of read-only memory. The MP provides external interfaces to three dual redundant MIL-STD-1553B serial communication buses, two differential Small Computer System Interface (SCSI) buses, an IEEE-488 bus, and miscellaneous digital and analog discrete lines.

  20. A CMOS Pressure Sensor Tag Chip for Passive Wireless Applications

    PubMed Central

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-01-01

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of −20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation. PMID:25806868

  1. Sub-band structure engineering for advanced CMOS channels

    NASA Astrophysics Data System (ADS)

    Takagi, Shin-ichi; Mizuno, T.; Tezuka, T.; Sugiyama, N.; Nakaharai, S.; Numata, T.; Koga, J.; Uchida, K.

    2005-05-01

    This paper reviews our recent studies of novel CMOS channels based on the concept of sub-band structure engineering. This device design concept can be realized as strained-Si channel MOSFETs, ultra-thin SOI MOSFETs and Ge-on-Insulator (GOI) MOSFETs. An important factor for the electron mobility enhancement is the introduction of larger sub-band energy splitting between the 2- and 4-fold valleys on a (1 0 0) surface, which can be obtained in strained-Si and ultra-thin body channels. The electrical properties of strained-Si MOSFETs are summarized with an emphasis on strained-SOI structures. Also, the importance of the precise control of ultra-thin SOI thickness is pointed out from the experimental results of the SOI thickness dependence of mobility. Furthermore, it is shown that the increase in the sub-band energy splitting can also be effective in obtaining higher current drive of n-channel MOSFETs under ballistic transport regime. This suggests that the current drive enhancement based on MOS channel engineering utilizing strain and ultra-thin body structures can be extended to ultra-short channel MOSFETs dominated by ballistic transport.

  2. A global shutter CMOS image sensor for hyperspectral imaging

    NASA Astrophysics Data System (ADS)

    Stefanov, Konstantin D.; Dryer, Ben J.; Hall, David J.; Holland, Andrew D.; Pratlong, Jérôme; Fryer, Martin; Pike, Andrew

    2015-09-01

    Hyperspectral imaging has been providing vital information on the Earth landscape in response to the changing environment, land use and natural phenomena. While conventional hyperspectral imaging instruments have typically used rows of linescan CCDs, CMOS image sensors (CIS) have been slowly penetrating space instrumentation for the past decade, and Earth observation (EO) is no exception. CIS provide distinct advantages over CCDs that are relevant to EO hyperspectral imaging. The lack of charge transfer through the array allows the reduction of cross talk usually present in CCDs due to imperfect charge transfer efficiency, and random pixel addressing makes variable integration time possible, and thus improves the camera sensitivity and dynamic range. We have developed a 10T pixel design that integrates a pinned photodiode with global shutter and in-pixel correlated double sampling (CDS) to increase the signal to noise ratio in less intense spectral regimes, allowing for both high resolution and low noise hyperspectral imaging for EO. This paper details the characterization of a test device, providing baseline performance measurements of the array such as noise, responsivity, dark current and global shutter efficiency, and also discussing benchmark hyperspectral imaging requirements such as dynamic range, pixel crosstalk, and image lag.

  3. Charge collection studies in irradiated HV-CMOS particle detectors

    NASA Astrophysics Data System (ADS)

    Affolder, A.; Andelković, M.; Arndt, K.; Bates, R.; Blue, A.; Bortoletto, D.; Buttar, C.; Caragiulo, P.; Cindro, V.; Das, D.; Dopke, J.; Dragone, A.; Ehrler, F.; Fadeyev, V.; Galloway, Z.; Gorišek, A.; Grabas, H.; Gregor, I. M.; Grenier, P.; Grillo, A.; Hommels, L. B. A.; Huffman, T.; John, J.; Kanisauskas, K.; Kenney, C.; Kramberger, G.; Liang, Z.; Mandić, I.; Maneuski, D.; McMahon, S.; Mikuž, M.; Muenstermann, D.; Nickerson, R.; Perić, I.; Phillips, P.; Plackett, R.; Rubbo, F.; Segal, J.; Seiden, A.; Shipsey, I.; Song, W.; Stanitzki, M.; Su, D.; Tamma, C.; Turchetta, R.; Vigani, L.; Volk, J.; Wang, R.; Warren, M.; Wilson, F.; Worm, S.; Xiu, Q.; Zavrtanik, M.; Zhang, J.; Zhu, H.

    2016-04-01

    Charge collection properties of particle detectors made in HV-CMOS technology were investigated before and after irradiation with reactor neutrons. Two different sensor types were designed and processed in 180 and 350 nm technology by AMS. Edge-TCT and charge collection measurements with electrons from 90Sr source were employed. Diffusion of generated carriers from undepleted substrate contributes significantly to the charge collection before irradiation, while after irradiation the drift contribution prevails as shown by charge measurements at different shaping times. The depleted region at a given bias voltage was found to grow with irradiation in the fluence range of interest for strip detectors at the HL-LHC. This leads to large gains in the measured charge with respect to the one before irradiation. The increase of the depleted region was attributed to removal of effective acceptors. The evolution of depleted region with fluence was investigated and modeled. Initial studies show a small effect of short term annealing on charge collection.

  4. A CMOS ASIC Design for SiPM Arrays

    PubMed Central

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K.; Miyaoka, Robert S.; Rudell, Jacques C.

    2012-01-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

  5. Novel integrated CMOS pixel structures for vertex detectors

    SciTech Connect

    Kleinfelder, Stuart; Bieser, Fred; Chen, Yandong; Gareus, Robin; Matis, Howard S.; Oldenburg, Markus; Retiere, Fabrice; Ritter, Hans Georg; Wieman, Howard H.; Yamamoto, Eugene

    2003-10-29

    Novel CMOS active pixel structures for vertex detector applications have been designed and tested. The overriding goal of this work is to increase the signal to noise ratio of the sensors and readout circuits. A large-area native epitaxial silicon photogate was designed with the aim of increasing the charge collected per struck pixel and to reduce charge diffusion to neighboring pixels. The photogate then transfers the charge to a low capacitance readout node to maintain a high charge to voltage conversion gain. Two techniques for noise reduction are also presented. The first is a per-pixel kT/C noise reduction circuit that produces results similar to traditional correlated double sampling (CDS). It has the advantage of requiring only one read, as compared to two for CDS, and no external storage or subtraction is needed. The technique reduced input-referred temporal noise by a factor of 2.5, to 12.8 e{sup -}. Finally, a column-level active reset technique is explored that suppresses kT/C noise during pixel reset. In tests, noise was reduced by a factor of 7.6 times, to an estimated 5.1 e{sup -} input-referred noise. The technique also dramatically reduces fixed pattern (pedestal) noise, by up to a factor of 21 in our tests. The latter feature may possibly reduce pixel-by-pixel pedestal differences to levels low enough to permit sparse data scan without per-pixel offset corrections.

  6. Capacitively Coupled CMOS VCSEL Driver Circuits for Optical Communication

    NASA Astrophysics Data System (ADS)

    Kozlov, Victor

    This thesis presents the analysis, design and implementation of a common-cathode capacitively-coupled VCSEL driver in 65nm CMOS intended for short-reach optical interconnects. The driver consists of an AC-coupled high-frequency path and a low-frequency path that provides DC signal components. By increasing the low-frequency path bandwidth by 10 times compared to previous AC-coupled drivers allowed the on-chip coupling capacitor to be reduced to 2.1pF, occupying 3 times less area than prior art. The driver introduces capacitively-coupled two-tap emphasis to equalize the VCSEL's optical response. The VCSEL was modulated with an OMA of up to 5.1dBm and an ER of 9dB, measuring an RMS jitter of 5ps at a data rate of 15Gb/s, which represents the highest OMA and ER achieved in high-speed anode-driving LDDs. The driver could be programmed for a low-power mode, outputting 2.3dBm OMA at power consumption of only 30mW, corresponding to an energy efficiency of 2pJ/bit.

  7. Improved Signal Chains for Readout of CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Hancock, Bruce; Cunningham, Thomas

    2009-01-01

    An improved generic design has been devised for implementing signal chains involved in readout from complementary metal oxide/semiconductor (CMOS) image sensors and for other readout integrated circuits (ICs) that perform equivalent functions. The design applies to any such IC in which output signal charges from the pixels in a given row are transferred simultaneously into sampling capacitors at the bottoms of the columns, then voltages representing individual pixel charges are read out in sequence by sequentially turning on column-selecting field-effect transistors (FETs) in synchronism with source-follower- or operational-amplifier-based amplifier circuits. The improved design affords the best features of prior source-follower-and operational- amplifier-based designs while overcoming the major limitations of those designs. The limitations can be summarized as follows: a) For a source-follower-based signal chain, the ohmic voltage drop associated with DC bias current flowing through the column-selection FET causes unacceptable voltage offset, nonlinearity, and reduced small-signal gain. b) For an operational-amplifier-based signal chain, the required bias current and the output noise increase superlinearly with size of the pixel array because of a corresponding increase in the effective capacitance of the row bus used to couple the sampled column charges to the operational amplifier. The effect of the bus capacitance is to simultaneously slow down the readout circuit and increase noise through the Miller effect.

  8. CMOS-based chemical microsensors: components of a micronose system

    NASA Astrophysics Data System (ADS)

    Hierlemann, Andreas; Koll, Andreas; Lange, Dirk; Hagleitner, Christoph; Kerness, Nicole; Brand, Oliver; Baltes, Henry

    1999-11-01

    We report on results achieved with three different types of polymer-coated chemical microsensors fabricated in industrial CMOS technology. The first and most extensively studied transducer is a microcapacitor sensitive to changes in dielectric properties of the polymer layer due to analyte absorption. An on-chip integrated (Sigma) (Delta) -converter allows for detecting the minute capacitance changes. The second transducer is a resonant cantilever sensitive to predominantly mass changes. The cantilever is electrothermally excited, its vibrations are detected using a piezoresistive Wheatstone bridge. In analogy to acoustic wave devices, analyte absorption in the polymer causes resonance frequency shifts as a consequent of changes in the vibrating mass. The last transducer is a microcalorimeter consisting of a polymer-coated sensing thermopile and an uncoated reference thermopile each on micromachined membranes. The measurand is the absorption or desorption heat of organic volatiles in the polymer layer. The difference between the resulting thermovoltages is processed with an on-chip low-noise differential amplifier. Enthalpy changes on the order of (mu) J have been detected.

  9. Read disturb errors in a CMOS static RAM chip

    NASA Astrophysics Data System (ADS)

    Wood, Steven H.; Marr, James C., IV; Nguyen, Tien T.; Padgett, Dwayne J.; Tran, Joe C.; Griswold, Thomas W.; Lebowitz, Daniel C.

    Results are reported from an extensive investigation into pattern-sensitive soft errors (read disturb errors) in the TCC244 CMOS static RAM chip. The TCC244, also known as the SA2838, is a radiation-hard single-event-upset-resistant 4 x 256 memory chip. This device is being used by the Jet Propulsion Laboratory in the Galileo and Magellan spacecraft, which will have encounters with Jupiter and Venus, respectively. Two aspects of the part's design are shown to result in the occurrence of read disturb errors: the transparence of the signal path from the address pins to the array of cells, and the large resistance in the Vdd and Vss lines of the cells in the center of the array. Probe measurements taken during a read disturb failure illustrate how address skews and the data pattern in the chip combine to produce a bit flip. A capacitive charge pump formed by the individual cell capacitances and the resistance in the supply lines pumps down both the internal cell voltage and the local supply voltage until a bit flip occurs.

  10. A CMOS ASIC Design for SiPM Arrays.

    PubMed

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2011-12-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

  11. Smart CMOS sensor for wideband laser threat detection

    NASA Astrophysics Data System (ADS)

    Schwarze, Craig R.; Sonkusale, Sameer

    2015-09-01

    The proliferation of lasers has led to their widespread use in applications ranging from short range standoff chemical detection to long range Lidar sensing and target designation operating across the UV to LWIR spectrum. Recent advances in high energy lasers have renewed the development of laser weapons systems. The ability to measure and assess laser source information is important to both identify a potential threat as well as determine safety and nominal hazard zone (NHZ). Laser detection sensors are required that provide high dynamic range, wide spectral coverage, pulsed and continuous wave detection, and large field of view. OPTRA, Inc. and Tufts have developed a custom ROIC smart pixel imaging sensor architecture and wavelength encoding optics for measurement of source wavelength, pulse length, pulse repetition frequency (PRF), irradiance, and angle of arrival. The smart architecture provides dual linear and logarithmic operating modes to provide 8+ orders of signal dynamic range and nanosecond pulse measurement capability that can be hybridized with the appropriate detector array to provide UV through LWIR laser sensing. Recent advances in sputtering techniques provide the capability for post-processing CMOS dies from the foundry and patterning PbS and PbSe photoconductors directly on the chip to create a single monolithic sensor array architecture for measuring sources operating from 0.26 - 5.0 microns, 1 mW/cm2 - 2 kW/cm2.

  12. Multi-Aperture CMOS Sun Sensor for Microsatellite Attitude Determination.

    PubMed

    Rufino, Giancarlo; Grassi, Michele

    2009-01-01

    This paper describes the high precision digital sun sensor under development at the University of Naples. The sensor determines the sun line orientation in the sensor frame from the measurement of the sun position on the focal plane. It exploits CMOS technology and an original optical head design with multiple apertures. This allows simultaneous multiple acquisitions of the sun as spots on the focal plane. The sensor can be operated either with a fixed or a variable number of sun spots, depending on the required field of view and sun-line measurement precision. Multiple acquisitions are averaged by using techniques which minimize the computational load to extract the sun line orientation with high precision. Accuracy and computational efficiency are also improved thanks to an original design of the calibration function relying on neural networks. Extensive test campaigns are carried out using a laboratory test facility reproducing sun spectrum, apparent size and distance, and variable illumination directions. Test results validate the sensor concept, confirming the precision improvement achievable with multiple apertures, and sensor operation with a variable number of sun spots. Specifically, the sensor provides accuracy and precision in the order of 1 arcmin and 1 arcsec, respectively. PMID:22408538

  13. Accelerated life testing effects on CMOS microcircuit characteristics

    NASA Technical Reports Server (NTRS)

    1980-01-01

    This report covers the time period from May 1976 to December 1979 and encompasses the three phases of accelerated testing: Phase 1, the 250 C testing; Phase 2, the 200 C testing; and Phase 3, the 125 C testing. The duration of the test in Phase 1 and Phase 2 was sufficient to take the devices into the wear out region. The wear out distributions were used to estimate the activation energy between the 250 C and the 200 C test temperatures. The duration of the 125 C test, 20,000 hours, was not sufficient to bring the test devices into the wear out region; consequently the third data point at 125 C for determining the consistency of activation energy could not be obtained. It was estimated that, for the most complex of the three device types, the activation energy between 200 C and 125 C should be at least as high as that between 250 C and 200 C. The practicality of the use of high temperature for the accelerated life tests from the point of view of durability of equipment was assessed. Guidelines for the development of accelerated life test conditions were proposed. The use of the silicon nitride overcoat to improve the high temperature accelerated life test characteristics of CMOS microcircuits was explored in Phase 4 of this study and is attached as an appendix to this report.

  14. Multi-Aperture CMOS Sun Sensor for Microsatellite Attitude Determination

    PubMed Central

    Rufino, Giancarlo; Grassi, Michele

    2009-01-01

    This paper describes the high precision digital sun sensor under development at the University of Naples. The sensor determines the sun line orientation in the sensor frame from the measurement of the sun position on the focal plane. It exploits CMOS technology and an original optical head design with multiple apertures. This allows simultaneous multiple acquisitions of the sun as spots on the focal plane. The sensor can be operated either with a fixed or a variable number of sun spots, depending on the required field of view and sun-line measurement precision. Multiple acquisitions are averaged by using techniques which minimize the computational load to extract the sun line orientation with high precision. Accuracy and computational efficiency are also improved thanks to an original design of the calibration function relying on neural networks. Extensive test campaigns are carried out using a laboratory test facility reproducing sun spectrum, apparent size and distance, and variable illumination directions. Test results validate the sensor concept, confirming the precision improvement achievable with multiple apertures, and sensor operation with a variable number of sun spots. Specifically, the sensor provides accuracy and precision in the order of 1 arcmin and 1 arcsec, respectively. PMID:22408538

  15. Dielectrophoretic lab-on-CMOS platform for trapping and manipulation of cells.

    PubMed

    Park, Kyoungchul; Kabiri, Shideh; Sonkusale, Sameer

    2016-02-01

    Trapping and manipulation of cells are essential operations in numerous studies in biology and life sciences. We discuss the realization of a Lab-on-a-Chip platform for dielectrophoretic trapping and repositioning of cells and microorganisms on a complementary metal oxide semiconductor (CMOS) technology, which we define here as Lab-on-CMOS (LoC). The LoC platform is based on dielectrophoresis (DEP) which is the force experienced by any dielectric particle including biological entities in non-uniform AC electrical field. DEP force depends on the permittivity of the cells, its size and shape and also on the permittivity of the medium and therefore it enables selective targeting of cells based on their phenotype. In this paper, we address an important matter that of electrode design for DEP for which we propose a three-dimensional (3D) octapole geometry to create highly confined electric fields for trapping and manipulation of cells. Conventional DEP-based platforms are implemented stand-alone on glass, silicon or polymers connected to external infrastructure for electronics and optics, making it bulky and expensive. In this paper, the use of CMOS as a platform provides a pathway to truly miniaturized lab-on-CMOS or LoC platform, where DEP electrodes are designed using built-in multiple metal layers of the CMOS process for effective trapping of cells, with built-in electronics for in-situ impedance monitoring of the cell position. We present electromagnetic simulation results of DEP force for this unique 3D octapole geometry on CMOS. Experimental results with yeast cells validate the design. These preliminary results indicate the promise of using CMOS technology for truly compact miniaturized lab-on-chip platform for cell biotechnology applications. PMID:26780441

  16. World commercial aircraft accidents

    SciTech Connect

    Kimura, C.Y.

    1993-01-01

    This report is a compilation of all accidents world-wide involving aircraft in commercial service which resulted in the loss of the airframe or one or more fatality, or both. This information has been gathered in order to present a complete inventory of commercial aircraft accidents. Events involving military action, sabotage, terrorist bombings, hijackings, suicides, and industrial ground accidents are included within this list. Included are: accidents involving world commercial jet aircraft, world commercial turboprop aircraft, world commercial pistonprop aircraft with four or more engines and world commercial pistonprop aircraft with two or three engines from 1946 to 1992. Each accident is presented with information in the following categories: date of the accident, airline and its flight numbers, type of flight, type of aircraft, aircraft registration number, construction number/manufacturers serial number, aircraft damage, accident flight phase, accident location, number of fatalities, number of occupants, cause, remarks, or description (brief) of the accident, and finally references used. The sixth chapter presents a summary of the world commercial aircraft accidents by major aircraft class (e.g. jet, turboprop, and pistonprop) and by flight phase. The seventh chapter presents several special studies including a list of world commercial aircraft accidents for all aircraft types with 100 or more fatalities in order of decreasing number of fatalities, a list of collision accidents involving commercial aircrafts, and a list of world commercial aircraft accidents for all aircraft types involving military action, sabotage, terrorist bombings, and hijackings.

  17. Testability of VLSI (Very Large Scale Integration) leakage faults in CMOS (Complementary Metal Oxide Semiconductor)

    NASA Astrophysics Data System (ADS)

    Malaiya, Y. K.; Su, S. Y. H.

    1983-09-01

    With the advent of VLSI (Very Large Scale Integration), the importance of CMOS (Complementary Metal Oxide Semiconductor) technology has increased. CMOS offers some very significant advantages over NMOS, and has emerged very competitive. Therefore, testability of CMOS devices is of considerable importance. CMOS devices exhibit some failure modes which are not adequately represented by the classical stuck-at fault model. A new fault model is introduced here to represent such faults. Leakage faults are specifically examined in this report, such faults increase the static supply current (which is ordinarily quite low) substantially. A leakage testing experiment consists of applying different vectors to the circuit, and in each case measuring the static supply current. This experimentally obtained data is then analyzed to obtain fault-related information. Leakage testing offers extra testability without any additional pins. It can detect some faults which cannot be detected by the conventional testing. Test generation for several basic CMOS structures is considered. Correspondence between leakage testing and conventional testing is studied. Two methods for analyzing experimental data are presented. Available experimental data was analyzed to obtain statistical information.

  18. High-sensitivity chemiluminescence detection of cytokines using an antibody-immobilized CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Hong, Dong-Gu; Joung, Hyou-Arm; Kim, Sang-Hyo; Kim, Min-Gon

    2013-05-01

    In this study, we used a Complementary Metal Oxide Semiconductor (CMOS) image sensor with immobilizing antibodies on its surface to detect human cytokines, which are activators that mediate intercellular communication including expression and control of immune responses. The CMOS image sensor has many advantages over the Charge Couple Device, including lower power consumption, operation voltage, and cost. The photodiode, a unit pixel component in the CMOS image sensor, receives light from the detection area and generates digital image data. About a million pixels are embedded, and size of each pixel is 3 x 3 μm. The chemiluminescence reaction produces light from the chemical reaction of luminol and hydrogen peroxide. To detect cytokines, antibodies were immobilized on the surface of the CMOS image sensor, and a sandwich immunoassay using an HRP-labeled antibody was performed. An HRP-catalyzed chemiluminescence reaction was measured by each pixel of the CMOS image sensor. Pixels with stronger signals indicated higher cytokine concentrations; thus, we were able to measure human interleukin-5 (IL-5) at femtomolar concentrations.

  19. Self-Vth-Cancellation High-Efficiency CMOS Rectifier Circuit for UHF RFIDs

    NASA Astrophysics Data System (ADS)

    Kotani, Koji; Ito, Takashi

    A high-efficiency CMOS rectifier circuit for UHF RFID applications was developed. The rectifier utilizes a self-Vth-cancellation (SVC) scheme in which the threshold voltage of MOSFETs is cancelled by applying gate bias voltage generated from the output voltage of the rectifier itself. A very simple circuit configuration and zero power dissipation characteristics in biasing enable excellent power conversion efficiency (PCE), especially under small RF input power conditions. At higher RF input power conditions, the PCE of the rectifier automatically decreases. This is the built-in self-power-regulation function. The proposed SVC CMOS rectifier was fabricated with a 0.35-m CMOS process and the measured performance was compared with those of conventional nMOS, pMOS, and CMOS rectifiers and other types of Vth cancellation rectifiers as well. The SVC CMOS rectifier achieves 32% of PCE at the -10dBm RF input power condition. This PCE is larger than rectifiers reported to date under this condition.

  20. Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

    SciTech Connect

    Wang, Zujun Huang, Shaoyan; Liu, Minbo; Xiao, Zhigang; He, Baoping; Yao, Zhibin; Sheng, Jiangkun

    2014-07-15

    The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 μm CMOS technology. The flux of neutron beams was about 1.33 × 10{sup 8} n/cm{sup 2}s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 10{sup 11}, 5 × 10{sup 11}, and 1 × 10{sup 12} n/cm{sup 2}, respectively. The mean dark signal (K{sub D}), dark signal spike, dark signal non-uniformity (DSNU), noise (V{sub N}), saturation output signal voltage (V{sub S}), and dynamic range (DR) versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike.

  1. Lunar Commercialization Workshop

    NASA Technical Reports Server (NTRS)

    Martin, Gary L.

    2008-01-01

    This slide presentation describes the goals and rules of the workshop on Lunar Commercialization. The goal of the workshop is to explore the viability of using public-private partnerships to open the new space frontier. The bulk of the workshop was a team competition to create a innovative business plan for the commercialization of the moon. The public private partnership concept is reviewed, and the open architecture as an infrastructure for potential external cooperation. Some possible lunar commercialization elements are reviewed.

  2. Commercialization of space

    NASA Technical Reports Server (NTRS)

    Rose, James T.; Stone, Barbara A.

    1988-01-01

    Space-commercialization activities are grouped into five categories: private sector development from existing technology for private sector use; pure privatization; private sector development for U.S. government use; private sector development from novel technology for private sector use; and, finally, full commercialization. The commercialization of space categories is defined, and the key issues in each are highlighted. A description of key NASA actions is included for each category. It is concluded that NASA and other government agency involvement is a common thread across the spectrum of space commercialization activities.

  3. Advanced Simulation Technology to Design Etching Process on CMOS Devices

    NASA Astrophysics Data System (ADS)

    Kuboi, Nobuyuki

    2015-09-01

    Prediction and control of plasma-induced damage is needed to mass-produce high performance CMOS devices. In particular, side-wall (SW) etching with low damage is a key process for the next generation of MOSFETs and FinFETs. To predict and control the damage, we have developed a SiN etching simulation technique for CHxFy/Ar/O2 plasma processes using a three-dimensional (3D) voxel model. This model includes new concepts for the gas transportation in the pattern, detailed surface reactions on the SiN reactive layer divided into several thin slabs and C-F polymer layer dependent on the H/N ratio, and use of ``smart voxels''. We successfully predicted the etching properties such as the etch rate, polymer layer thickness, and selectivity for Si, SiO2, and SiN films along with process variations and demonstrated the 3D damage distribution time-dependently during SW etching on MOSFETs and FinFETs. We confirmed that a large amount of Si damage was caused in the source/drain region with the passage of time in spite of the existing SiO2 layer of 15 nm in the over etch step and the Si fin having been directly damaged by a large amount of high energy H during the removal step of the parasitic fin spacer leading to Si fin damage to a depth of 14 to 18 nm. By analyzing the results of these simulations and our previous simulations, we found that it is important to carefully control the dose of high energy H, incident energy of H, polymer layer thickness, and over-etch time considering the effects of the pattern structure, chamber-wall condition, and wafer open area ratio. In collaboration with Masanaga Fukasawa and Tetsuya Tatsumi, Sony Corporation. We thank Mr. T. Shigetoshi and Mr. T. Kinoshita of Sony Corporation for their assistance with the experiments.

  4. Etch challenges for DSA implementation in CMOS via patterning

    NASA Astrophysics Data System (ADS)

    Pimenta Barros, P.; Barnola, S.; Gharbi, A.; Argoud, M.; Servin, I.; Tiron, R.; Chevalier, X.; Navarro, C.; Nicolet, C.; Lapeyre, C.; Monget, C.; Martinez, E.

    2014-03-01

    This paper reports on the etch challenges to overcome for the implementation of PS-b-PMMA block copolymer's Directed Self-Assembly (DSA) in CMOS via patterning level. Our process is based on a graphoepitaxy approach, employing an industrial PS-b-PMMA block copolymer (BCP) from Arkema with a cylindrical morphology. The process consists in the following steps: a) DSA of block copolymers inside guiding patterns, b) PMMA removal, c) brush layer opening and finally d) PS pattern transfer into typical MEOL or BEOL stacks. All results presented here have been performed on the DSA Leti's 300mm pilot line. The first etch challenge to overcome for BCP transfer involves in removing all PMMA selectively to PS block. In our process baseline, an acetic acid treatment is carried out to develop PMMA domains. However, this wet development has shown some limitations in terms of resists compatibility and will not be appropriated for lamellar BCPs. That is why we also investigate the possibility to remove PMMA by only dry etching. In this work the potential of a dry PMMA removal by using CO based chemistries is shown and compared to wet development. The advantages and limitations of each approach are reported. The second crucial step is the etching of brush layer (PS-r-PMMA) through a PS mask. We have optimized this step in order to preserve the PS patterns in terms of CD, holes features and film thickness. Several integrations flow with complex stacks are explored for contact shrinking by DSA. A study of CD uniformity has been addressed to evaluate the capabilities of DSA approach after graphoepitaxy and after etching.

  5. CMOS compatible high-speed electro-optical modulator

    NASA Astrophysics Data System (ADS)

    Kekatpure, Rohan D.; Brongersma, Mark L.

    2005-08-01

    Demand for a silicon (Si) based optical modulator is becoming more pressing as optical interconnects are starting to be considered seriously as replacement for conventional copper wires in electronic chips. Difficulties in realizing this device in Si are well known as are the stringent requirements on its performance in terms of size (~μm), power (~μW-mW), speed (>1 GHz) and operating voltage (<5 V). Here we present a detailed numerical design and analysis of a compact, high-speed silicon-on-insulator (SOI) waveguide electro-optical modulator. The device operates by tuning the reflection resonance of a microring resonator by means of field-effect generated free carriers in metal-oxide-semiconductor accumulation layers. Electrical and optical analyses are carried out by solution of Poisson's, charge continuity, and Maxwell's equations by finite-element method. Our simulations predict a ~0.5 nm shift in the spectral response of the resonator around 1550 nm. With an appropriate pre-biasing, this leads to ~80% modulation depth switching with voltage swing of 2 V. Field-effect induced generation of free-carriers allows for operating bandwidth >5 GHz while consuming a total dynamic power of < 500 μW. Use of the field effect results in extremely thin charge layers of very high carrier concentration. We show that an appropriate placement of these layers in the modal field of strong-confinement SOI waveguides greatly enhances the charge-field interaction. This enables significant improvements in size and modulation depth and allows the device to operate at CMOS compatible power and voltage levels. Present work adds to the design space explored in the previous works and aims to advance the field-effect based micro-resonator modulator as an active photonic device to be used in future generations of opto-electronic circuits.

  6. Compact CMOS Camera Demonstrator (C3D) for Ukube-1

    NASA Astrophysics Data System (ADS)

    Harriss, R. D.; Holland, A. D.; Barber, S. J.; Karout, S.; Burgon, R.; Dryer, B. J.; Murray, N. J.; Hall, D. J.; Smith, P. H.; Grieg, T.; Tutt, J. H.; Endicott, J.; Jerram, P.; Morris, D.; Robbins, M.; Prevost, V.; Holland, K.

    2011-09-01

    The Open University, in collaboration with e2v technologies and XCAM Ltd, have been selected to fly an EO (Earth Observation) technology demonstrator and in-orbit radiation damage characterisation instrument on board the UK Space Agency's UKube-1 pilot Cubesat programme. Cubesat payloads offer a unique opportunity to rapidly build and fly space hardware for minimal cost, providing easy access to the space environment. Based around the e2v 1.3 MPixel 0.18 micron process eye-on-Si CMOS devices, the instrument consists of a radiation characterisation imager as well as a narrow field imager (NFI) and a wide field imager (WFI). The narrow and wide field imagers are expected to achieve resolutions of 25 m and 350 m respectively from a 650 km orbit, providing sufficient swathe width to view the southern UK with the WFI and London with the NFI. The radiation characterisation experiment has been designed to verify and reinforce ground based testing that has been conducted on the e2v eye-on-Si family of devices and includes TEC temperature control circuitry as well as RADFET in-orbit dosimetry. Of particular interest are SEU and SEL effects. The novel instrument design allows for a wide range of capabilities within highly constrained mass, power and space budgets providing a model for future use on similarly constrained missions, such as planetary rovers. Scheduled for launch in December 2011, this 1 year low cost programme should not only provide valuable data and outreach opportunities but also help to prove flight heritage for future missions.

  7. sCMOS detector for imaging VNIR spectrometry

    NASA Astrophysics Data System (ADS)

    Eckardt, Andreas; Reulke, Ralf; Schwarzer, Horst; Venus, Holger; Neumann, Christian

    2013-09-01

    The facility Optical Information Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the scientific results of the institute of leading edge instruments and focal plane designs for EnMAP VIS/NIR spectrograph. EnMAP (Environmental Mapping and Analysis Program) is one of the selected proposals for the national German Space Program. The EnMAP project includes the technological design of the hyper spectral space borne instrument and the algorithms development of the classification. The EnMAP project is a joint response of German Earth observation research institutions, value-added resellers and the German space industry like Kayser-Threde GmbH (KT) and others to the increasing demand on information about the status of our environment. The Geo Forschungs Zentrum (GFZ) Potsdam is the Principal Investigator of EnMAP. DLR OS and KT were driving the technology of new detectors and the FPA design for this project, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generations of space borne sensor systems are focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large swath and high spectral resolution with intelligent synchronization control, fast-readout ADC chains and new focal-plane concepts open the door to new remote-sensing and smart deep space instruments. The paper gives an overview over the detector verification program at DLR on FPA level, new control possibilities for sCMOS detectors in global shutter mode and key parameters like PRNU, DSNU, MTF, SNR, Linearity, Spectral Response, Quantum Efficiency, Flatness and Radiation Tolerance will be discussed in detail.

  8. Prototyping of an HV-CMOS demonstrator for the High Luminosity-LHC upgrade

    NASA Astrophysics Data System (ADS)

    Vilella, E.; Benoit, M.; Casanova, R.; Casse, G.; Ferrere, D.; Iacobucci, G.; Peric, I.; Vossebeld, J.

    2016-01-01

    HV-CMOS sensors can offer important advantages in terms of material budget, granularity and cost for large area tracking systems in high energy physics experiments. This article presents the design and simulated results of an HV-CMOS pixel demonstrator for the High Luminosity-LHC. The pixel demonstrator has been designed in the 0.35 μm HV-CMOS process from ams AG and submitted for fabrication through an engineering run. To improve the response of the sensor, different wafers with moderate to high substrate resistivities are used to fabricate the design. The prototype consists of four large analog and standalone matrices with several pixel flavours, which are all compatible for readout with the FE-I4 ASIC. Details about the matrices and the pixel flavours are provided in this article.

  9. A scalable neural chip with synaptic electronics using CMOS integrated memristors

    NASA Astrophysics Data System (ADS)

    Cruz-Albrecht, Jose M.; Derosier, Timothy; Srinivasa, Narayan

    2013-09-01

    The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

  10. Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

    NASA Astrophysics Data System (ADS)

    Tongqiang, Gao; Chun, Zhang; Baoyong, Chi; Zhihua, Wang

    2009-06-01

    To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-μm CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

  11. A 3-D optoelectronic integration methodology utilizing CMOS post-backend process

    NASA Astrophysics Data System (ADS)

    Zhang, Zan; Huang, Beiju; Zhang, Zanyun; Cheng, Chuantong; Mao, Xurui; Chen, Hongda

    2014-10-01

    The integration of optical devices and electronic integrated circuits (IC) is a main issue for optoelectronic convergence. In this work, a CMOS post-backend process flow is proposed to potentially achieve a 3-D monolithic optoelectronic integrated chip. The proposed integrated chip is composed of an IC die as electronic layer and a waveguide device layer as photonic layer above electronic layer. The photonic layer is fabricated by CMOS post-backend process with a temperature blow 450 ºC, which would do no harm to the performance of the CMOS ICs. We also fabricated Si3N4 mircoring add-drop filters on a bulk Si wafer. The cross-section of the waveguide is 400 nm × 1 μm, and the radius of microring is 30μm. Measured results match well with numerical simulations.

  12. A CMOS-compatible, surface-micromachined pressure sensor for aqueous ultrasonic application

    SciTech Connect

    Eaton, W.P.; Smith, J.H.

    1994-12-31

    A surface micromachined pressure sensor array is under development at the Integrated Micromechanics, Microsensors, and CMOS Technologies organization at Sandia National Laboratories. This array is designed to sense absolute pressures from ambient pressure to 650 psia with frequency responses from DC to 2 MHz. The sensor is based upon a sealed, deformable, circular LPCVD silicon nitride diaphragm. Absolute pressure is determined from diaphragm deflection, which is sensed with low-stress, micromechanical, LPCVD polysilicon piezoresistors. All materials and processes used for sensor fabrication are CMOS compatible, and are part of Sandia`s ongoing effort of CMOS integration with Micro-ElectroMechanical Systems (MEMS). Test results of individual sensors are presented along with process issues involving the release etch and metal step coverage.

  13. A CMOS Time-Resolved Fluorescence Lifetime Analysis Micro-System

    PubMed Central

    Rae, Bruce R.; Muir, Keith R.; Gong, Zheng; McKendry, Jonathan; Girkin, John M.; Gu, Erdan; Renshaw, David; Dawson, Martin D.; Henderson, Robert K.

    2009-01-01

    We describe a CMOS-based micro-system for time-resolved fluorescence lifetime analysis. It comprises a 16 × 4 array of single-photon avalanche diodes (SPADs) fabricated in 0.35 μm high-voltage CMOS technology with in-pixel time-gated photon counting circuitry and a second device incorporating an 8 × 8 AlInGaN blue micro-pixellated light-emitting diode (micro-LED) array bump-bonded to an equivalent array of LED drivers realized in a standard low-voltage 0.35 μm CMOS technology, capable of producing excitation pulses with a width of 777 ps (FWHM). This system replaces instrumentation based on lasers, photomultiplier tubes, bulk optics and discrete electronics with a PC-based micro-system. Demonstrator lifetime measurements of colloidal quantum dot and Rhodamine samples are presented. PMID:22291564

  14. A modular process for integrating thick polysilicon MEMS devices with sub-micron CMOS

    NASA Astrophysics Data System (ADS)

    Yasaitis, John A.; Judy, Michael; Brosnihan, Tim; Garone, Peter M.; Pokrovskiy, Nikolay; Sniderman, Debbie; Limb, Scott; Howe, Roger T.; Boser, Bernhard E.; Palaniapan, Moorthi; Jiang, Xuesong; Bhave, Sunil

    2003-01-01

    A new MEMS process module, called Mod MEMS, has been developed to monolithically integrate thick (5-10um), multilayer polysilicon MEMS structures with sub-micron CMOS. This process is particularly useful for advanced inertial MEMS products such as automotive airbag accelerometers where reduced cost and increased functionality is required, or low cost, high performance gyroscopes where thick polysilicon (>6um) and CMOS integration is required to increase poly mass and stiffness, and reduce electrical parasitics in order to optimize angular rate sensing. In this paper we will describe the new modular process flow, development of the critical unit process steps, integration of the module with a foundry sub-micron CMOS process, and provide test data on several inertial designs fabricated with this process.

  15. CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results

    NASA Astrophysics Data System (ADS)

    Rivetti, A.; Battaglia, M.; Bisello, D.; Caselle, M.; Chalmet, P.; Costa, M.; Demaria, N.; Giubilato, P.; Ikemoto, Y.; Kloukinas, K.; Mansuy, C.; Marchioro, A.; Mugnier, H.; Pantano, D.; Potenza, A.; Rousset, J.; Silvestrin, L.; Wyss, J.

    2013-12-01

    The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400 Ω cm, which is at least one order of magnitude greater than the typical value (1 - 10 Ω cm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported.

  16. Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

    NASA Astrophysics Data System (ADS)

    Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2015-07-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×1012 1 MeV neq/cm2 and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  17. Evaluation of sCMOS cameras for detection and localization of single Cy5 molecules

    PubMed Central

    Saurabh, Saumya; Maji, Suvrajit; Bruchez, Marcel P.

    2012-01-01

    The ability to detect single molecules over the electronic noise requires high performance detector systems. Electron Multiplying Charge-Coupled Device (EMCCD) cameras have been employed successfully to image single molecules. Recently, scientific Complementary Metal Oxide Semiconductor (sCMOS) based cameras have been introduced with very low read noise at faster read out rates, smaller pixel sizes and a lower price compared to EMCCD cameras. In this study, we have compared the two technologies using two EMCCD and three sCMOS cameras to detect single Cy5 molecules. Our findings indicate that the sCMOS cameras perform similar to EMCCD cameras for detecting and localizing single Cy5 molecules. PMID:22453414

  18. An approach to the optical interconnect made in standard CMOS process

    NASA Astrophysics Data System (ADS)

    Changliang, Yu; Luhong, Mao; Xindong, Xiao; Sheng, Xie; Shilin, Zhang

    2009-05-01

    A standard CMOS optical interconnect is proposed, including an octagonal-annular emitter, a field oxide, metal 1-PSG/BPSG-metal 2 dual waveguide, and an ultra high-sensitivity optical receiver integrated with a fingered P+/N-well/P-sub dual photodiode detector. The optical interconnect is implemented in a Chartered 3.3-V 0.35-μm standard analog CMOS process with two schemes for the research of the substrate noise coupling effect on the optical interconnect performance: with or without a GND-guardring around the emitter. The experiment results show that the optical interconnect can work at 100 kHz, and it is feasible to implement optical interconnects in standard CMOS processes.

  19. Nanostructured metallic surfaces for enhanced transmission and polarization filtering in CMOS fabricated photodetectors

    NASA Astrophysics Data System (ADS)

    Dunbar, L. A.; Guillaumée, M.; de León-Pérez, F.; Rüedi, P.-F.; Spassov, V.; Eckert, R.; Lopez-Tejeira, F.; García-Vidal, F. J.; Franzi, E.; Martín-Moreno, L.; Stanley, R. P.

    2010-05-01

    The miniaturization of photodetectors often comes at the expense of a smaller photosensitive area. This can reduce the signal and thus limit the image quality. One way to overcome this limitation is to reduce the photosensitive area but with no reduction of signal i.e. harvest the light. Here we investigate, theoretically and experimentally, light harvesting with nanostructured metals. Nanostructured metals can also give additional functionality such as polarization filtering which is also investigated. After defining the figure of merits used when characterizing light harvesting and polarization filtering structures, we detail the fabrication and measurement process. Structures were made on glass substrate, as a post process step on CMOS fabricated detectors and directly in the CMOS fabrication of the detectors. The optical characterization results are presented and compared with theory. Finally, we discuss the challenges and advantages of integrating metallic nanostructures within the CMOS process.

  20. A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

    NASA Astrophysics Data System (ADS)

    Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

    2016-02-01

    We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

  1. The evaluation system of the 2-D scanning mirror based on CMOS sensor

    NASA Astrophysics Data System (ADS)

    Zeng, Gui-ying; Xie, Yuan; Chen, Jin-xing

    2010-10-01

    The high precision two-dimension scanning control technique is being developed for the next geosynchronous satellites FY-4 satellites which is using the three-axis stabilization stages. How to evaluate the point and scanning precision of the scanning mirror is one of the most important technologies. This paper describes the optoelectronic measure method based on CMOS sensors to evaluate the point and scanning precision of the scanning mirror in the laboratory, which is a 2-D dynamic angle measurement system. Some technologies, such as the sup-pixel orientation technology and the CMOS ROI technology, are used in the measurement system. The research shows that the angle measurement system based on IBIS-6600CMOS sensors can attain the 20°× 20° field of view, 2" accuracy, and 1Kframes/s speed. But the system is sensitive to the environment and it can only be worked in the laboratory.

  2. 60-GHz array antenna with standard CMOS technology on Schott Borofloat

    NASA Astrophysics Data System (ADS)

    Jun, Luo; Yan, Wang; Ruifeng, Yue

    2013-11-01

    This design is presented of a 2 × 2 planar array, with a half-wave dipole antenna to be its element, on a new substrate material, Schott Borofloat, with CMOS technology in the 60 GHz band. In the proposed structure, all the designs are based on the CMOS technology and similar performance could be achieved with the same size in contrast to the design on low-temperature co-fired ceramic (LTCC). This could lead to the improving of the compatibility with the CMOS IC process, the design cost and the design precision which is restricted in the LTCC process. The simulated -10 dB bandwidth of the array is from 58 to 64 GHz. A peak gain of 9.4 dBi is achieved. Good agreement on return loss is achieved between simulations and measurements.

  3. Commercialism in Intercollegiate Athletics.

    ERIC Educational Resources Information Center

    Delany, James E.

    1997-01-01

    Outlines the history of intercollegiate athletics and the evolution of commercialization in college sports, particularly through television. Argues that few Division I programs could be self-sufficient; the issue is the degree to which sports are commercialized for revenue, and the challenge to balance schools' needs, private sector interests, and…

  4. Lunar Commercialization Workshop

    NASA Technical Reports Server (NTRS)

    Martin, Gary L.

    2009-01-01

    This slide presentation outlines a competition that has as its goal to explores the viability of using public-private partnerships to open space frontier for commercial uses. The teams have the objective of designing a business plan to open the space frontier to commercial interests.

  5. Fabrication and characterization of a charge-biased CMOS-MEMS resonant gate field effect transistor

    NASA Astrophysics Data System (ADS)

    Chin, C. H.; Li, C. S.; Li, M. H.; Wang, Y. L.; Li, S. S.

    2014-09-01

    A high-frequency charge-biased CMOS-MEMS resonant gate field effect transistor (RGFET) composed of a metal-oxide composite resonant-gate structure and an FET transducer has been demonstrated utilizing the TSMC 0.35 μm CMOS technology with Q > 1700 and a signal-to-feedthrough ratio greater than 35 dB under a direct two-port measurement configuration. As compared to the conventional capacitive-type MEMS resonators, the proposed CMOS-MEMS RGFET features an inherent transconductance gain (gm) offered by the FET transduction capable of enhancing the motional signal of the resonator and relaxing the impedance mismatch issue to its succeeding electronics or 50 Ω-based test facilities. In this work, we design a clamped-clamped beam resonant-gate structure right above a floating gate FET transducer as a high-Q building block through a maskless post-CMOS process to combine merits from the large capacitive transduction areas of the large-width beam resonator and the high gain of the underneath FET. An analytical model is also provided to simulate the behavior of the charge-biased RGFET; the theoretical prediction is in good agreement with the experimental results. Thanks to the deep-submicrometer gap spacing enabled by the post-CMOS polysilicon release process, the proposed resonator under a purely capacitive transduction already attains motional impedance less than 10 kΩ, a record-low value among CMOS-MEMS capacitive resonators. To go one step further, the motional signal of the proposed RGFET is greatly enhanced through the FET transduction. Such a strong transmission and a sharp phase transition across 0° pave a way for future RGFET-type oscillators in RF and sensor applications. A time-elapsed characterization of the charge leakage rate for the floating gate is also carried out.

  6. Investigation of III-V semiconductor heterostructures for post-Si-CMOS applications

    NASA Astrophysics Data System (ADS)

    Bhatnagar, Kunal

    Silicon complementary metal-oxide-semiconductor (CMOS) technology in the past few decades has been driven by aggressive device scaling to increase performance, reduce cost and lower power consumption. However, as devices are scaled below the 100 nm region, performance gain has become increasingly difficult to obtain by traditional scaling. As we move towards advanced technology nodes, materials innovation and physical architecture are becoming the primary enabler for performance enhancement in CMOS technology rather than scaling. One class of materials that can potentially result in improved electrical performance are III-V semiconductors, which are ideal candidates for replacing the channel in Si CMOS owing to their high electron mobilities and capabilities for band-engineering. This work is aimed towards the growth and characterization of III-V semiconductor heterostructures and their application in post-Si-CMOS devices. The two main components of this study include the integration of III-V compound semiconductors on silicon for tunnel-junction Esaki diodes, and the investigation of carrier transport properties in low-power III-V n-channel FETs under uniaxial strain for advanced III-V CMOS solutions. The integration of III-V compound semiconductors with Si can combine the cost advantage and maturity of the Si technology with the superior performance of III-V materials. We have demonstrated high quality epitaxial growth of GaAs and GaSb on Si (001) wafers through the use of various buffer layers including AlSb and crystalline SrTiO3. These GaSb/Si virtual substrates were used for the fabrication and characterization of InAs/GaSb broken-gap Esaki-tunnel diodes as a possible solution for heterojunction Tunnel-FETs. In addition, the carrier transport properties of InAs channels were evaluated under uniaxial strain for the potential use of strain solutions in III-V CMOS.

  7. Label free sensing of creatinine using a 6 GHz CMOS near-field dielectric immunosensor.

    PubMed

    Guha, S; Warsinke, A; Tientcheu, Ch M; Schmalz, K; Meliani, C; Wenger, Ch

    2015-05-01

    In this work we present a CMOS high frequency direct immunosensor operating at 6 GHz (C-band) for label free determination of creatinine. The sensor is fabricated in standard 0.13 μm SiGe:C BiCMOS process. The report also demonstrates the ability to immobilize creatinine molecules on a Si3N4 passivation layer of the standard BiCMOS/CMOS process, therefore, evading any further need of cumbersome post processing of the fabricated sensor chip. The sensor is based on capacitive detection of the amount of non-creatinine bound antibodies binding to an immobilized creatinine layer on the passivated sensor. The chip bound antibody amount in turn corresponds indirectly to the creatinine concentration used in the incubation phase. The determination of creatinine in the concentration range of 0.88-880 μM is successfully demonstrated in this work. A sensitivity of 35 MHz/10 fold increase in creatinine concentration (during incubation) at the centre frequency of 6 GHz is gained by the immunosensor. The results are compared with a standard optical measurement technique and the dynamic range and sensitivity is of the order of the established optical indication technique. The C-band immunosensor chip comprising an area of 0.3 mm(2) reduces the sensing area considerably, therefore, requiring a sample volume as low as 2 μl. The small analyte sample volume and label free approach also reduce the experimental costs in addition to the low fabrication costs offered by the batch fabrication technique of CMOS/BiCMOS process. PMID:25782697

  8. Amorphous selenium direct detection CMOS digital x-ray imager with 25 micron pixel pitch

    NASA Astrophysics Data System (ADS)

    Scott, Christopher C.; Abbaszadeh, Shiva; Ghanbarzadeh, Sina; Allan, Gary; Farrier, Michael; Cunningham, Ian A.; Karim, Karim S.

    2014-03-01

    We have developed a high resolution amorphous selenium (a-Se) direct detection imager using a large-area compatible back-end fabrication process on top of a CMOS active pixel sensor having 25 micron pixel pitch. Integration of a-Se with CMOS technology requires overcoming CMOS/a-Se interfacial strain, which initiates nucleation of crystalline selenium and results in high detector dark currents. A CMOS-compatible polyimide buffer layer was used to planarize the backplane and provide a low stress and thermally stable surface for a-Se. The buffer layer inhibits crystallization and provides detector stability that is not only a performance factor but also critical for favorable long term cost-benefit considerations in the application of CMOS digital x-ray imagers in medical practice. The detector structure is comprised of a polyimide (PI) buffer layer, the a-Se layer, and a gold (Au) top electrode. The PI layer is applied by spin-coating and is patterned using dry etching to open the backplane bond pads for wire bonding. Thermal evaporation is used to deposit the a-Se and Au layers, and the detector is operated in hole collection mode (i.e. a positive bias on the Au top electrode). High resolution a-Se diagnostic systems typically use 70 to 100 μm pixel pitch and have a pre-sampling modulation transfer function (MTF) that is significantly limited by the pixel aperture. Our results confirm that, for a densely integrated 25 μm pixel pitch CMOS array, the MTF approaches the fundamental material limit, i.e. where the MTF begins to be limited by the a-Se material properties and not the pixel aperture. Preliminary images demonstrating high spatial resolution have been obtained from a frst prototype imager.

  9. A single-supply, monolithic, MIL-STD-1553 transceiver implemented in BiCMOS wafer fabrication technology

    NASA Astrophysics Data System (ADS)

    Albrecht, Thomas L.; Molinari, Lou

    An integrated circuit has been designed for use as a single supply, MIL-STD-1553 transceiver using BiCMOS technology. Use of the BiCMOS fabrication process has advantages over both Bipolar and CMOS technologies. These advantages include: reduced standby current drain, increased flexibility in mating the transceiver to various remote terminals, increased control over output amplitude and rise/fall times, easier methods for adjusting filter response and residual voltage, and reduced chip size (over a CMOS transceiver). Development of this monolithic transceiver opens the door to future advances in remote terminal design. By combining the current driving capacity of Bipolar with the digital design capability of CMOS, the next probable step in the progression of MIL-STD-1553 technology would be a fully monolithic remote terminal. This device would combine a transceiver with the encoder/decoder and protocol logic on a single semiconductor device.

  10. Design and experimental demonstration of low-power CMOS magnetic cell manipulation platform using charge recycling technique

    NASA Astrophysics Data System (ADS)

    Niitsu, Kiichi; Yoshida, Kohei; Nakazato, Kazuo

    2016-03-01

    We present the world’s first charge-recycling-based low-power technique of complementary metal-oxide-semiconductor (CMOS) magnetic cell manipulation. CMOS magnetic cell manipulation associated with magnetic beads is a promissing tool for on-chip biomedical-analysis applications such as drug screening because CMOS can integrate control electronics and electro-chemical sensors. However, the conventional CMOS cell manipulation requires considerable power consumption. In this work, by concatenating multiple unit circuits and recycling electric charge among them, power consumption is reduced by a factor of the number of the concatenated unit circuits (1/N). For verifying the effectiveness, test chip was fabricated in a 0.6-µm CMOS. The chip successfully manipulates magnetic microbeads with achieving 49% power reduction (from 51 to 26.2 mW). Even considering the additional serial resistance of the concatenated inductors, nearly theoretical power reduction effect can be confirmed.

  11. Technology Transfer and Commercialization

    NASA Technical Reports Server (NTRS)

    Martin, Katherine; Chapman, Diane; Giffith, Melanie; Molnar, Darwin

    2001-01-01

    During concurrent sessions for Materials and Structures for High Performance and Emissions Reduction, the UEET Intellectual Property Officer and the Technology Commercialization Specialist will discuss the UEET Technology Transfer and Commercialization goals and efforts. This will include a review of the Technology Commercialization Plan for UEET and what UEET personnel are asked to do to further the goals of the Plan. The major goal of the Plan is to define methods for how UEET assets can best be infused into industry. The National Technology Transfer Center will conduct a summary of its efforts in assessing UEET technologies in the areas of materials and emissions reduction for commercial potential. NTTC is assisting us in completing an inventory and prioritization by commercialization potential. This will result in increased exposure of UEET capabilities to the private sector. The session will include audience solicitation of additional commercializable technologies.

  12. A zirconium dioxide ammonia microsensor integrated with a readout circuit manufactured using the 0.18 μm CMOS process.

    PubMed

    Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm. PMID:23503294

  13. Design and Fabrication of a Monolithic Optoelectronic Integrated Circuit Chip Based on CMOS Compatible Technology

    NASA Astrophysics Data System (ADS)

    Guo, Wei-Feng; Zhao, Yong; Wang, Wan-Jun; Shao, Hai-Feng; Yang, Jian-Yi; Jiang, Xiao-Qing

    2012-04-01

    A monolithic optoelectronic integrated circuit chip on a silicon-on-insulator is designed and fabricated based on complementary metal oxide semiconductor compatible technology. The chip integrates an optical Mach-Zehnder modulator (MZM) and a CMOS driving circuit with the amplification function. Test results show that the extinction ratio of the MZM is close to 20 dB and the small-signal gain of the CMOS driving circuit is about 26.9 dB. A 50 mV 10 MHz sine wave signal is amplified by the driving circuit, and then drives the MZM successfully.

  14. 180 Degree Hybrid (Rat-Race) Junction on CMOS Grade Silicon with a Polyimide Interface Layer

    NASA Technical Reports Server (NTRS)

    Ponchak, George E.; Papapolymerou, John

    2003-01-01

    180-degree hybrid junctions can be used to equally divide power between two output ports with either a 0 or 180-degree phase difference. Alternatively, they can be used to combine signals from two sources and output a sum and difference signal. The main limitation of implementing; these on CMOS grade silicon is the high loss associated with the substrate. In this paper, we present a low loss 180-degree hybrid junction on CMOS grade (15 omega-cm) silicon with a polyimide interface layer for the first time. The divider utilizes Finite Ground Coplanar (FGC) line technology, and operates at a center frequency of 15 GIIz.

  15. MTD 132; A new sub-nanosecond multi-hit CMOS time-to-digital converter

    SciTech Connect

    Kleinfelder, S.; Majors, T.J.; Blumer, K.A.; Farr, W.; Manor, B. )

    1991-04-01

    This paper describes a new 8 channel, 16 hit, sub-nanosecond resolution, 16 bit dynamic range time-to- digital VLSI CMOS circuit. It can operate in either common start or common stop mode and records either leading, trailing, or both input edges. Double pulse resolution is 15 ns. Readout is sparsified, and input signal levels are ECL while control and output levels are CMOS. Measured performance of prototype devices is presented. A CAMAC and a FASTBUS TDC board using this chip are under development.

  16. A CMOS sensor for rapid testing of pathogen susceptibility to pore-forming antibiotics.

    PubMed

    Nikkhoo, Nasim; Gulak, P Glenn; Maxwell, Karen

    2015-08-01

    An integrated CMOS chip is implemented in 0.13μm technology that detects the efficacy of pore-forming antibiotics on bacterial samples in 10 minutes. The chip has been tested using two strains of E. coli and polymyxin B as the model antibiotic. An array of potassium-sensitive ISFETs and their readout circuits are integrated on the CMOS chip and a potassium-sensitive membrane is directly attached to the top metal electrodes, to measure potassium efflux from the affected bacterial cells. PMID:26738035

  17. A novel CMOS sensor with in-pixel auto-zeroed discrimination for charged particle tracking

    NASA Astrophysics Data System (ADS)

    Degerli, Y.; Guilloux, F.; Orsini, F.

    2014-05-01

    With the aim of developing fast and granular Monolithic Active Pixels Sensors (MAPS) as new charged particle tracking detectors for high energy physics experiments, a new rolling shutter binary pixel architecture concept (RSBPix) with in-pixel correlated double sampling, amplification and discrimination is presented. The discriminator features auto-zeroing in order to compensate process-related transistor mismatches. In order to validate the pixel, a first monolithic CMOS sensor prototype, including a pixel array of 96 × 64 pixels, has been designed and fabricated in the Tower-Jazz 0.18 μm CMOS Image Sensor (CIS) process. Results of laboratory tests are presented.

  18. Use of CMOS imagers to measure high fluxes of charged particles

    NASA Astrophysics Data System (ADS)

    Servoli, L.; Tucceri, P.

    2016-03-01

    The measurement of high flux charged particle beams, specifically at medical accelerators and with small fields, poses several challenges. In this work we propose a single particle counting method based on CMOS imagers optimized for visible light collection, exploiting their very high spatial segmentation (> 3 106 pixels/cm2) and almost full efficiency detection capability. An algorithm to measure the charged particle flux with a precision of ~ 1% for fluxes up to 40 MHz/cm2 has been developed, using a non-linear calibration algorithm, and several CMOS imagers with different characteristics have been compared to find their limits on flux measurement.

  19. Prediction and measurement of radiation damage to CMOS devices on board spacecraft

    NASA Technical Reports Server (NTRS)

    Cliff, R. A.; Danchenko, V.; Stassinopoulos, E. G.; Sing, M.; Brucker, G. J.; Ohanian, R. S.

    1976-01-01

    The initial results obtained from the Complementary Metal Oxide Semiconductors Radiation Effects Measurement experiment are presented. Predictions of radiation damage to C-MOS devices are based on standard environment models and computational techniques. A comparison of the shifts in CMOS threshold potentials, that is, those measured in space to those obtained from the on the ground simulation experiment with Co 60, indicated that the measured space damage is greater than predicted by a factor of two for shields thicker than 100 mils (2.54 mm), but agrees well with predictions for the thinner shields.

  20. Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Lee, M. J.; Brown, D. N.; Chang, J. K.; Ding, D.; Gnani, D.; Grace, C. R.; Jones, J. A.; Kolomensky, Y. G.; von der Lippe, H.; Mcvittie, P. J.; Stettler, M. W.; Walder, J.-P.

    2015-06-01

    We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

  1. Automatic Synthesis of CMOS Algorithmic Analog To-Digital Converter.

    NASA Astrophysics Data System (ADS)

    Jusuf, Gani

    The steady decrease in technological feature size is allowing increasing levels of integration in analog/digital interface functions. These functions consist of analog as well as digital circuits. While the turn around time for an all digital IC chip is very short due to the maturity of digital IC computer-aided design (CAD) tools over the last ten years, most analog circuits have to be designed manually due to the lack of analog IC CAD tools. As a result, analog circuit design becomes the bottleneck in the design of mixed signal processing chips. One common analog function in a mixed signal processing chip is an analog-to-digital conversion (ADC) function. This function recurs frequently but with varying performance requirements. The objective of this research is to study the design methodology of a compilation program capable of synthesizing ADC's with a broad range of sampling rates and resolution, and silicon area and performance comparable with the manual approach. The automatic compilation of the ADC function is a difficult problem mainly because ADC techniques span such a wide spectrum of performance, with radically different implementations being optimum for different ranges of conversion range, resolution, and power dissipation. We will show that a proper choice of the ADC architectures and the incorporation of many analog circuit design techniques will simplify the synthesis procedure tremendously. Moreover, in order to speed up the device sizing, hierarchical optimization procedure and behavioral simulation are implemented into the ADC module generation steps. As a result of this study, a new improved algorithmic ADC without the need of high precision comparators has been developed. This type of ADC lends itself to automatic generation due to its modularity, simplicity, small area consumption, moderate speed, low power dissipation, and single parameter trim capability that can be added at high resolution. Furthermore, a performance-driven CMOS ADC module generator, CADICS based on design rules and spice parameters has been developed. CADICS takes a set of input files and generates the complete ADC netlist, layout, and performance summary. A prototype of the automatically generated ADC has also been fabricated and tested.

  2. Commercial Biomedical Experiments Payload

    NASA Technical Reports Server (NTRS)

    2003-01-01

    Experiments to seek solutions for a range of biomedical issues are at the heart of several investigations that will be hosted by the Commercial Instrumentation Technology Associates (ITA), Inc. The biomedical experiments CIBX-2 payload is unique, encompassing more than 20 separate experiments including cancer research, commercial experiments, and student hands-on experiments from 10 schools as part of ITA's ongoing University Among the stars program. Here, Astronaut Story Musgrave activates the CMIX-5 (Commercial MDA ITA experiment) payload in the Space Shuttle mid deck during the STS-80 mission in 1996 which is similar to CIBX-2. The experiments are sponsored by NASA's Space Product Development Program (SPD).

  3. Commercial considerations for immunoproteomics.

    PubMed

    Ferguson, Scott M

    2013-01-01

    The underlying drivers of scientific processes have been rapidly evolving, but the ever-present need for research funding is typically foremost amongst these. Successful laboratories are embracing this reality by making certain that their projects have commercial value right from the beginning of the project conception. Which factors to be considered for commercial success need to be well thought out and incorporated into a project plan with similar levels of detail as would be the technical elements. Specific examples of commercial outcomes in the field of Immunoproteomics are exemplified in this discussion. PMID:23963949

  4. Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

    NASA Astrophysics Data System (ADS)

    Fiorini, M.; Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2014-12-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×1012 1 MeV neq /cm2 and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 1014 cm-2 and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  5. Comparing Commercial WWW Browsers.

    ERIC Educational Resources Information Center

    Notess, Greg R.

    1995-01-01

    Four commercial World Wide Web browsers are evaluated for features such as handling of WWW protocols and different URLs: FTP, Telnet, Gopher and WAIS, and e-mail and news; bookmark capabilities; navigation features; file management; and security support. (JKP)

  6. NASA commercial programs

    NASA Technical Reports Server (NTRS)

    1990-01-01

    Highlights of NASA-sponsored and assisted commercial space activities of 1989 are presented. Industrial R and D in space, centers for the commercial development of space, and new cooperative agreements are addressed in the U.S. private sector in space section. In the building U.S. competitiveness through technology section, the following topics are presented: (1) technology utilization as a national priority; (2) an exploration of benefits; and (3) honoring Apollo-Era spinoffs. International and domestic R and D trends, and the space sector are discussed in the section on selected economic indicators. Other subjects included in this report are: (1) small business innovation; (2) budget highlights and trends; (3) commercial programs management; and (4) the commercial programs advisory committee.

  7. COMMERCIALIZATION OF BIOCONTROL

    Technology Transfer Automated Retrieval System (TEKTRAN)

    Successful commercialization of biocontrol products requires the marriage of science and industry. From a science perspective, some of the issues to be addressed include knowledge of efficacy under various environmental conditions, inoculum density relationships, formulation, and when, where and ho...

  8. Commodification and commercial surrogacy.

    PubMed

    Arneson, Richard J

    1992-01-01

    ... In this article I shall argue tentatively for the claim that commercial surrogacy should be legally permissible. I am more strongly convinced that a commitment to feminism should not predispose anyone against surrogacy. At least, no arguments offered so far should persuade anyone who is committed to equal rights for women and men and the dismantling of gender-based hierarchies to favor either legal prohibition or moral condemnation of commercial surrogacy. PMID:11651242

  9. Technology Commercialization Program 1991

    SciTech Connect

    Not Available

    1991-11-01

    This reference compilation describes the Technology Commercialization Program of the Department of Energy, Defense Programs. The compilation consists of two sections. Section 1, Plans and Procedures, describes the plans and procedures of the Defense Programs Technology Commercialization Program. The second section, Legislation and Policy, identifies legislation and policy related to the Program. The procedures for implementing statutory and regulatory requirements are evolving with time. This document will be periodically updated to reflect changes and new material.

  10. A CMOS-MEMS arrayed resonant-gate field effect transistor (RGFET) oscillator

    NASA Astrophysics Data System (ADS)

    Chin, Chi-Hang; Li, Ming-Huang; Chen, Chao-Yu; Wang, Yu-Lin; Li, Sheng-Shian

    2015-11-01

    A high-frequency CMOS-MEMS arrayed resonant-gate field effect transistor (RGFET) fabricated by a standard 0.35 μm 2-poly-4-metal CMOS-MEMS platform is implemented to enable a Pierce-type oscillator. The proposed arrayed RGFET exhibits low motional impedance of only 5 kΩ under a purely capacitive transduction and decent power handling capability. With such features, the implemented oscillator shows impressive phase noise of  -117 dBc Hz-1 at the far-from-carrier offset (1 MHz). In this work, we design a clamped-clamped beam (CCB) arrayed resonator utilizing a high-velocity mechanical coupling scheme to serve as the resonant-gate array. To achieve a functional arrayed RGFET, a corresponding FET array is directly placed underneath the resonant gate array to convert the motional current on the resonant-gate array into a voltage output with a tunable transconductance gain. To understand the behavior of the proposed device, an equivalent circuit model consisting of the resonant unit and FET is also provided. To verify the effects of the post-CMOS process on device performance, a conventional MOS I D current measurement is carried out. Finally, a CMOS-MEMS arrayed RGFET oscillator is realized by utilizing a Pierce oscillator architecture, showing decent phase noise performance that benefits from the array design to alleviate the nonlinear effect of the resonant gate.

  11. Creating a parameterized model of a CMOS transistor with a gate of enclosed layout

    NASA Astrophysics Data System (ADS)

    Vinogradov, S. M.; Atkin, E. V.; Ivanov, P. Y.

    2016-02-01

    The method of creating a parameterized spice model of an N-channel transistor with a gate of enclosed layout is considered. Formulas and examples of engineering calculations for use of models in the computer-aided Design environment of Cadence Vitruoso are presented. Calculations are made for the CMOS technology with 180 nm design rules of the UMC.

  12. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.

    PubMed

    Aull, Brian

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging. PMID:27070609

  13. INVITED PAPER: Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

    NASA Astrophysics Data System (ADS)

    Contopanagos, Harry

    2005-01-01

    We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 μm. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance.

  14. Fabrication of cantilever based mass sensors integrated with CMOS using direct write laser lithography on resist

    NASA Astrophysics Data System (ADS)

    Forsén, E.; Nilsson, S. G.; Carlberg, P.; Abadal, G.; Pérez-Murano, F.; Esteve, J.; Montserrat, J.; Figueras, E.; Campabadal, F.; Verd, J.; Montelius, L.; Barniol, N.; Boisen, A.

    2004-10-01

    A CMOS compatible direct write laser lithography technique has been developed for cantilever fabrication on pre-fabricated standard CMOS. We have developed cantilever based sensors for mass measurements in vacuum and air. The cantilever is actuated into lateral vibration by electrostatic excitation and the resonant frequency is detected by capacitive readout. The device is integrated on standard CMOS circuitry. In the work a new direct write laser lithography (DWL) technique is introduced. This laser lithography technique is based on direct laser writing on substrates coated with a resist bi-layer consisting of poly(methyl methacrylate) (PMMA) on lift-off resist (LOR). Laser writing evaporates the PMMA, exposing the LOR. A resist solvent is used to transfer the pattern down to the substrate. Metal lift-off followed by reactive ion etching is used for patterning the structural poly-Si layer in the CMOS. The developed laser lithography technique is compatible with resist exposure techniques such as electron beam lithography. We demonstrate the fabrication of sub-micrometre wide suspended cantilevers as well as metal lift-off with feature line widths down to approximately 500 nm.

  15. Design and fabrication of a CMOS-compatible MHP gas sensor

    SciTech Connect

    Li, Ying; Yu, Jun Wu, Hao; Tang, Zhenan

    2014-03-15

    A novel micro-hotplate (MHP) gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO{sub 2} film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3%) in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.

  16. Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks

    NASA Technical Reports Server (NTRS)

    Dogan, Numan S.

    2003-01-01

    The objective of this work is to design and develop Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks. We briefly report on the accomplishments in this work. We also list the impact of this work on graduate student research training/involvement.

  17. Wide Range CMOS Voltage Detector with Low Current Consumption and Low Temperature Variation

    NASA Astrophysics Data System (ADS)

    Takakubo, Kawori; Takakubo, Hajime

    A wide range CMOS voltage detector with low current consumption consisting of CMOS inverters operating in both weak inversion and saturation region is proposed. A terminal of power supply for CMOS inverter can be expanded to a signal input terminal. A voltage-detection point and hysteresis characteristics of the proposed circuit can be designed by geometrical factor in MOSFET and an external bias voltage. The core circuit elements are fabricated in standard 0.18µm CMOS process and measured to confirm the operation. The detectable voltage is from 0.3V to 1.8V. The current consumption of voltage detection, standby current, is changed from 65pA for Vin =0.3V to 5.5µA for Vin =1.8V. The thermal characteristics from 250K to 400K are also considered. The measured temperature coefficient of the proposed voltage-detector core operating in weak inversion region is 4ppm/K and that in saturation region is 10ppm/K. The proposed voltage detector can be implemented with tiny chip area and is expected to an on-chip voltage detector of power supply for mobile application systems.

  18. Single-Photon Avalanche Diodes (SPAD) in CMOS 0.35 μm technology

    NASA Astrophysics Data System (ADS)

    Pellion, D.; Jradi, K.; Brochard, N.; Prêle, D.; Ginhac, D.

    2015-07-01

    Some decades ago single photon detection used to be the terrain of photomultiplier tube (PMT), thanks to its characteristics of sensitivity and speed. However, PMT has several disadvantages such as low quantum efficiency, overall dimensions, and cost, making them unsuitable for compact design of integrated systems. So, the past decade has seen a dramatic increase in interest in new integrated single-photon detectors called Single-Photon Avalanche Diodes (SPAD) or Geiger-mode APD. SPAD are working in avalanche mode above the breakdown level. When an incident photon is captured, a very fast avalanche is triggered, generating an easily detectable current pulse. This paper discusses SPAD detectors fabricated in a standard CMOS technology featuring both single-photon sensitivity, and excellent timing resolution, while guaranteeing a high integration. In this work, we investigate the design of SPAD detectors using the AMS 0.35 μm CMOS Opto technology. Indeed, such standard CMOS technology allows producing large surface (few mm2) of single photon sensitive detectors. Moreover, SPAD in CMOS technologies could be associated to electronic readout such as active quenching, digital to analog converter, memories and any specific processing required to build efficient calorimeters1

  19. Defect-sensitivity analysis of an SEU immune CMOS logic family

    NASA Technical Reports Server (NTRS)

    Ingermann, Erik H.; Frenzel, James F.

    1992-01-01

    Fault testing of resistive manufacturing defects is done on a recently developed single event upset immune logic family. Resistive ranges and delay times are compared with those of traditional CMOS logic. Reaction of the logic to these defects is observed for a NOR gate, and an evaluation of its ability to cope with them is determined.

  20. A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

    PubMed

    Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

    2016-01-01

    A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented. PMID:27104122

  1. Strained SOI/SGOI dual-channel CMOS technology based on the Ge condensation technique

    NASA Astrophysics Data System (ADS)

    Tezuka, Tsutomu; Nakaharai, Shu; Moriyama, Yoshihiko; Hirashita, Norio; Toyoda, Eiji; Numata, Toshinori; Irisawa, Toshifumi; Usuda, Koji; Sugiyama, Naoharu; Mizuno, Tomohisa; Takagi, Shin-ichi

    2007-01-01

    Ge-rich strained SiGe-on-insulator (SGOI) pMOSFETs were fabricated by oxidizing strained SiGe layers on SOI substrates at high temperatures. It was found that strain was accumulated in the SGOI channels during this process, called Ge condensation, associated with the increase in the Ge fraction. Significant hole-mobility enhancements up to a factor of 10 were observed due to the high Ge fractions over 0.5 and large strain values over 1%. The SGOI pMOSFETs were also co-integrated with strained SOI nMOSFETs or ultra-thin SOI nMOSFETs to form dual-channel CMOS devices. The dual-channel structures were fabricated by conventional CMOS processes combined with the Ge condensation process and selective epitaxial growth processes. High hole mobility was observed in the SGOI pMOSFETs of the CMOS devices, whereas an enhancement or no degradation of electron mobility was observed in the strained or the unstrained SOI nMOSFETs. Based on the measured carrier mobility of the long-channel nMOSFETs and pMOSFETs, short-channel CMOS performance enhancement of around 30% was estimated.

  2. CMOS Active-Pixel Image Sensor With Intensity-Driven Readout

    NASA Technical Reports Server (NTRS)

    Langenbacher, Harry T.; Fossum, Eric R.; Kemeny, Sabrina

    1996-01-01

    Proposed complementary metal oxide/semiconductor (CMOS) integrated-circuit image sensor automatically provides readouts from pixels in order of decreasing illumination intensity. Sensor operated in integration mode. Particularly useful in number of image-sensing tasks, including diffractive laser range-finding, three-dimensional imaging, event-driven readout of sparse sensor arrays, and star tracking.

  3. The use of light emission in failure analysis of CMOS ICs

    SciTech Connect

    Hawkins, C.F. . Dept. of Electrical and Computer Engineering); Soden, J.M.; Cole, E.I. Jr.; Snyder, E.S. )

    1990-01-01

    The use of photon emission for analyzing failure mechanisms and defects in CMOS ICs is presented. Techniques are given for accurate identification and spatial localization of failure mechanisms and physical defects, including defects such as short and open circuits which do not themselves emit photons.

  4. An integrated CMOS high voltage supply for lab-on-a-chip systems.

    PubMed

    Behnam, M; Kaigala, G V; Khorasani, M; Marshall, P; Backhouse, C J; Elliott, D G

    2008-09-01

    Electrophoresis is a mainstay of lab-on-a-chip (LOC) implementations of molecular biology procedures and is the basis of many medical diagnostics. High voltage (HV) power supplies are necessary in electrophoresis instruments and are a significant part of the overall system cost. This cost of instrumentation is a significant impediment to making LOC technologies more widely available. We believe one approach to overcoming this problem is to use microelectronic technology (complementary metal-oxide semiconductor, CMOS) to generate and control the HV. We present a CMOS-based chip (3 mm x 2.9 mm) that generates high voltages (hundreds of volts), switches HV outputs, and is powered by a 5 V input supply (total power of 28 mW) while being controlled using a standard computer serial interface. Microchip electrophoresis with laser induced fluorescence (LIF) detection is implemented using this HV CMOS chip. With the other advancements made in the LOC community (e.g. micro-fluidic and optical devices), these CMOS chips may ultimately enable 'true' LOC solutions where essentially all the microfluidics, photonics and electronics are on a single chip. PMID:18818808

  5. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    PubMed Central

    Aull, Brian

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging. PMID:27070609

  6. On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

    NASA Technical Reports Server (NTRS)

    Samoska, Lorene; Man Fung, King; Gaier, Todd; Huang, Daquan; Larocca, Tim; Chang, M. F.; Campbell, Richard; Andrews, Michael

    2008-01-01

    The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.

  7. X-ray characterization of CMOS imaging detector with high resolution for fluoroscopic imaging application

    NASA Astrophysics Data System (ADS)

    Cha, Bo Kyung; Kim, Cho Rong; Jeon, Seongchae; Kim, Ryun Kyung; Seo, Chang-Woo; Yang, Keedong; Heo, Duchang; Lee, Tae-Bum; Shin, Min-Seok; Kim, Jong-Boo; Kwon, Oh-Kyung

    2013-12-01

    This paper introduces complementary metal-oxide semiconductor (CMOS) active pixel sensor (APS)-based X-ray imaging detectors with high spatial resolution for medical imaging application. In this study, our proposed X-ray CMOS imaging sensor has been fabricated by using a 0.35 μm 1 Poly 4 Metal CMOS process. The pixel size is 100 μm×100 μm and the pixel array format is 24×96 pixels, which provide a field-of-view (FOV) of 9.6 mm×2.4 mm. The 14.3-bit extend counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. Both thallium-doped CsI (CsI:Tl) and Gd2O2S:Tb scintillator screens were used as converters for incident X-rays to visible light photons. The optical property and X-ray imaging characterization such as X-ray to light response as a function of incident X-ray exposure dose, spatial resolution and X-ray images of objects were measured under different X-ray energy conditions. The measured results suggest that our developed CMOS-based X-ray imaging detector has the potential for fluoroscopic imaging and cone-beam computed tomography (CBCT) imaging applications.

  8. Method for implementation of back-illuminated CMOS or CCD imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor)

    2008-01-01

    A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.

  9. Total Ionizing Dose Effects in Bipolar and BiCMOS Devices

    NASA Technical Reports Server (NTRS)

    Chavez, Rosa M.; Rax, Bernard G.; Scheick, Leif Z.; Johnston, Allan H.

    2005-01-01

    This paper describes total ionizing dose (TID) test results performed at JPL. Bipolar and BiCMOS device samples were tested exhibiting significant degradation and failures at different irradiation levels. Linear technology which is susceptible to low-dose dependency (ELDRS) exhibited greater damage for devices tested under zero bias condition.

  10. Ka-Band, RF MEMS Switches on CMOS Grade Silicon with a Polyimide Interface Layer

    NASA Technical Reports Server (NTRS)

    Ponchak, George E.; Varaljay, Nicholas C.; Papapolymerou, John

    2003-01-01

    For the first time, RF MEMS switcbes on CMOS grade Si witb a polyimide interface layer are fabricated and characterized. At Ka-Band (36.6 GHz), an insertion loss of 0.52 dB and an isolation of 20 dB is obtained.

  11. Overview of CMOS process and design options for image sensor dedicated to space applications

    NASA Astrophysics Data System (ADS)

    Martin-Gonthier, P.; Magnan, P.; Corbiere, F.

    2005-10-01

    With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35μm generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques.

  12. Electroabsorption modulators for CMOS compatible optical interconnects in III-V and group IV materials

    NASA Astrophysics Data System (ADS)

    Roth, Jonathan Edgar

    While electrical systems excel at information processing, photonics is useful in systems for high-bandwidth, low-loss signal transmission. As photonics technology has become increasingly widespread and has been deployed at shorter distance scales than traditional long-haul networks, it has become important to efficiently integrate photonics components with electrical integrated circuits. Optoelectronic modulators used as transmitters are an important class of device for use in optical interconnects. Many optoelectronic modulator designs use waveguides. Coupling light into waveguides requires a difficult alignment step. This dissertation will describe a number of optoelectronic modulators that do not have the tight alignment constraints associated with waveguide-based modulators. The eased alignment constraints may be important for the practical manufacturing and packaging of systems using optical interconnects. Most currently deployed photonics technologies also use substrates other than silicon and materials incompatible with CMOS manufacturing. Recently we discovered a strong quantum-confined Stark effect in Ge/SiGe quantum well structures that can be used to create efficient optoelectronic modulators on silicon substrates. Optoelectronic modulators using this technology can be fabricated with conventional CMOS foundry processes, possibly on the same chips as CMOS circuits. In this dissertation, an optical interconnect operating in the C-band will be presented. We believe this is the first such device employing an optical transmitter flip-chip bonded to silicon CMOS. A number of novel modulators will be presented, which are fabricated on silicon substrates, and employ Ge/SiGe quantum well structures. These modulators include a novel architecture known as the side-entry modulator, which is designed for monolithic integration with electronics. One side-entry modulator achieved over 3 dB of contrast in the telecommunications C-band for a voltage swing of 1V. Such a device is compatible with both the voltage swing of modern CMOS circuits, and long-distance telecommunications technologies including low-loss optical fiber and erbium-doped fiber amplifiers.

  13. Design and Fabrication of High-Efficiency CMOS/CCD Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2007-01-01

    An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

  14. Precision of FLEET Velocimetry Using High-Speed CMOS Camera Systems

    NASA Technical Reports Server (NTRS)

    Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

    2015-01-01

    Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 microseconds, precisions of 0.5 meters per second in air and 0.2 meters per second in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision HighSpeed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

  15. Precision of FLEET Velocimetry Using High-speed CMOS Camera Systems

    NASA Technical Reports Server (NTRS)

    Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

    2015-01-01

    Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 micro sec, precisions of 0.5 m/s in air and 0.2 m/s in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision High Speed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

  16. Increasing Linear Dynamic Range of a CMOS Image Sensor

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2007-01-01

    A generic design and a corresponding operating sequence have been developed for increasing the linear-response dynamic range of a complementary metal oxide/semiconductor (CMOS) image sensor. The design provides for linear calibrated dual-gain pixels that operate at high gain at a low signal level and at low gain at a signal level above a preset threshold. Unlike most prior designs for increasing dynamic range of an image sensor, this design does not entail any increase in noise (including fixed-pattern noise), decrease in responsivity or linearity, or degradation of photometric calibration. The figure is a simplified schematic diagram showing the circuit of one pixel and pertinent parts of its column readout circuitry. The conventional part of the pixel circuit includes a photodiode having a small capacitance, CD. The unconventional part includes an additional larger capacitance, CL, that can be connected to the photodiode via a transfer gate controlled in part by a latch. In the high-gain mode, the signal labeled TSR in the figure is held low through the latch, which also helps to adapt the gain on a pixel-by-pixel basis. Light must be coupled to the pixel through a microlens or by back illumination in order to obtain a high effective fill factor; this is necessary to ensure high quantum efficiency, a loss of which would minimize the efficacy of the dynamic- range-enhancement scheme. Once the level of illumination of the pixel exceeds the threshold, TSR is turned on, causing the transfer gate to conduct, thereby adding CL to the pixel capacitance. The added capacitance reduces the conversion gain, and increases the pixel electron-handling capacity, thereby providing an extension of the dynamic range. By use of an array of comparators also at the bottom of the column, photocharge voltages on sampling capacitors in each column are compared with a reference voltage to determine whether it is necessary to switch from the high-gain to the low-gain mode. Depending upon the built-in offset in each pixel and in each comparator, the point at which the gain change occurs will be different, adding gain-dependent fixed pattern noise in each pixel. The offset, and hence the fixed pattern noise, is eliminated by sampling the pixel readout charge four times by use of four capacitors (instead of two such capacitors as in conventional design) connected to the bottom of the column via electronic switches SHS1, SHR1, SHS2, and SHR2, respectively, corresponding to high and low values of the signals TSR and RST. The samples are combined in an appropriate fashion to cancel offset-induced errors, and provide spurious-free imaging with extended dynamic range.

  17. Commercialization of NESSUS: Status

    NASA Technical Reports Server (NTRS)

    Thacker, Ben H.; Millwater, Harry R.

    1991-01-01

    A plan was initiated in 1988 to commercialize the Numerical Evaluation of Stochastic Structures Under Stress (NESSUS) probabilistic structural analysis software. The goal of the on-going commercialization effort is to begin the transfer of Probabilistic Structural Analysis Method (PSAM) developed technology into industry and to develop additional funding resources in the general area of structural reliability. The commercialization effort is summarized. The SwRI NESSUS Software System is a general purpose probabilistic finite element computer program using state of the art methods for predicting stochastic structural response due to random loads, material properties, part geometry, and boundary conditions. NESSUS can be used to assess structural reliability, to compute probability of failure, to rank the input random variables by importance, and to provide a more cost effective design than traditional methods. The goal is to develop a general probabilistic structural analysis methodology to assist in the certification of critical components in the next generation Space Shuttle Main Engine.

  18. A PEDA approach for monolithic photonic BiCMOS technologies

    NASA Astrophysics Data System (ADS)

    Simon, Stefan; Winzer, Georg; Roßmann, Helmut; Kroh, Marcel; Zimmermann, Lars; Mausolf, Thomas

    2015-06-01

    The paper describes a novel approach to photonic electronic design automation (PEDA) based on the commercial design suite Laytools for circuit and physical layout design and simulation. The goal of this work is the integration of an electronic-photonic design flow into an existing electronic design automation (EDA) tool. Contrary to other solutions, with this approach, it is possible to minimize the required interfaces to other third party tools. In addition to existing electronic device models, photonic components are described with behavioral models. The mask layout has been extended to the needs of the electronic photonic integrated circuit (ePIC) designer and the verification flow was adapted to the photonic structures.

  19. Commercial Biomedical Experiments

    NASA Technical Reports Server (NTRS)

    2003-01-01

    Experiments to seek solutions for a range of biomedical issues are at the heart of several investigations that will be hosted by the Commercial Instrumentation Technology Associates (ITA), Inc. Biomedical Experiments (CIBX-2) payload. CIBX-2 is unique, encompassing more than 20 separate experiments including cancer research, commercial experiments, and student hands-on experiments from 10 schools as part of ITA's ongoing University Among the Stars program. Valerie Cassanto of ITA checks the Canadian Protein Crystallization Experiment (CAPE) carried by STS-86 to Mir in 1997. The experiments are sponsored by NASA's Space Product Development Program (SPD).

  20. Commercial Fisheries Surveys

    USGS Publications Warehouse

    Fabrizio, Mary C.; Richards, R. Anne

    1996-01-01

    In this chapter, we describe methods for sampling commercial fisheries and identify factors affecting the design of sampling plans. When sampled properly, commercial fisheries can provide important information on the response of aquatic organisms to exploitation; such information can be used by management agencies to develop regulations for ensuring long-term production of the resource and long-term economic benefit. Fishery statistics are typically used to estimate abundance, mortality, recruitment, growth, and other vital characterisitcs of populations. Fishery statistics can also be used to study changes in fish community composition resulting from differential exploitation of species.