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1

Electron Charge Noise Minimization, in 130 nm CMOS Preamplifiers  

NASA Astrophysics Data System (ADS)

In this paper we present the design aspects for low-power, low-noise CMOS charge sensitive preamplifier that uses a leakage current compensation circuit for use with radiation sensors. The preamplifier has unipolar response with the peaking time of about 45 ns and the gain about 115-145 mV/ke. Equivalent noise charge (ENC) is less than 80 e, when the input charge is 1-20 ke and the sensors capacitance is equal to 30 fF. In this work we present the quality function of the charge sensitive preamplifier, which characterizes best the optimal input transistor width W, with respect to equivalent noise charge and to the power consumptions.

Barzdenas, V.; Navickas, R.

2008-03-01

2

A 59–66 GHz Highly Stable Millimeter Wave Amplifier in 130 nm CMOS Technology  

Microsoft Academic Search

The design and fabrication of four-stage cascaded mm-wave low noise amplifiers (LNAs) in a 130 nm CMOS tech- nology are presented. The simultaneous high stability factor and low noise figure are obtained using proper inductors in both gate and source of the transistor. Measured gain of 14.7 dB with a 7 GHz bandwidth has been achieved. The larger inductors are

Mehrdad Fahimnia; Mahmoud Mohammad-Taheri; Ying Wang; Ming Yu; Safieddin Safavi-Naeini

2011-01-01

3

A 130 nm CMOS mixed mode front end readout chip for silicon strip tracking at the future linear collider  

Microsoft Academic Search

A 130nm mixed (analog and digital) CMOS chip intended to read silicon strip detectors for future linear collider experiments was developed. Currently under testing, this chip has been optimized for a silicon micro-strip tracking device. It includes 88 channels of a full analog signal processing chain with the corresponding digital control and readout. Every analog channel includes (i) a low

T. H. Pham; A. Charpy; C. Ciobanu; A. Comerma; J. David; M. Dhellot; A. Diéguez; D. Gascon; J. F. Genat; A. Savoy Navarro; R. Sefri

2010-01-01

4

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS  

Microsoft Academic Search

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The trans- ceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase\\/frequency detector and charge-pump

Robert Bogdan Staszewski; Khurram Muhammad; Dirk Leipold; Chih-Ming Hung; Yo-Chuol Ho; John L. Wallberg; Chan Fernando; Ken Maggio; Roman Staszewski; Tom Jung; Jinseok Koh; Soji John; Irene Yuanying Deng; Vivek Sarda; Oscar Moreira-Tamayo; Valerian Mayega; Ofer Friedman; Oren Eytan Eliezer; Poras T. Balsara; E. de-Obaldia

2004-01-01

5

Design and Layout Techniques for the Optimization of nMOS SPDT Series-Shunt Switches in a 130nm SiGe BiCMOS Technology  

Microsoft Academic Search

This work investigates various design and layout optimization approaches for MOSFET-based series-shunt, single-pole double-throw (SPDT) switches in a commercially-available 130 nm silicon-germanium (SiGe) BiCMOS technology. The incorporation of deep-trench isolation, additional substrate contacts, and additional gate resistance for the series nMOS device are examined, and the impact of these design and layout optimizations on the switches insertion loss, bandwidth, isolation

Jonathan P. Comeau; John D. Cressler; Mark Mitchell

2007-01-01

6

Heavy ion-induced SEEs on 130 nm CMOS technology for LHC application—status and challenges  

NASA Astrophysics Data System (ADS)

This work summarizes the status of the art of electronic designs, using CMOS technologies, to stand LHC and S-LHC radiation-hard environments. Radiation effects can be divided into Single Event Effects and Total Ionizing Dose effects, which are consequences of different interaction effects within the silicon and the electronics. These types of effects are commonly investigated and faced separately. The commercial 130 nm CMOS technology, today primarily proposed for SLHC electronic upgrades, only implements redundancies against the Single Event Effects`. On the contrary, the 250 nm technology node used in the past years for LHC experiments, was also hardened against the Total Ionizing Dose. Hence, the choice of the technology to be used for high-energy experiments is very crucial as it implies huge efforts in the designs of the components. In addition, an unavoidable technology scaling keeps moving toward ever-smaller sizes and this affects the availability of the silicon process for medium and long-term experiments.

Gabrielli, A.

2011-12-01

7

Effects of body biasing on the low-frequency noise of NMOSFETs from a 130-nm CMOS technology  

NASA Astrophysics Data System (ADS)

We investigate the impact of body biasing on the low frequency noise (LFN) performances of NMOS transistors from a transistors 130 nm CMOS technology. The body-to-source voltage VBS was varied from 0.5 to + 0.5 V for reverse and forward mode substrate biasing. A detailed electrical characterization was performed and the benefits of the body bias analysed in terms of current and maximum transconductance variations. Noise measurements were first performed at low drain bias VDS = 25 mV and VBS = 0 V in order to discuss the noise model. Results are in agreement with the carrier number fluctuation theory. Bulk bias dependence of the LFN was investigated at VDS = VDD = 1.2 V. Significant noise reduction is observed in the subthreshold regime when applying a forward body bias. In strong inversion, the noise level is found to be approximately independent of the substrate bias VBS.

Marin, Mathieu; Deen, M. Jamal; de Murcia, Mario; Llinares, Pierre; Vildeuil, Jean Charles

2003-05-01

8

Radiation hardness evaluation of a 130 nm SiGe BiCMOS technology for high energy physics applications  

NASA Astrophysics Data System (ADS)

Final results for a comprehensive radiation hardness evaluation of a high performance, low cost, 130 nm SiGe BiCMOS technology are presented. After a survey of several available SiGe technologies, one was chosen in terms of performance, power consumption, radiation hardness, and cost and it is presented as a suitable technology for the future upgrades of the ATLAS detector of the High Luminosity LHC. Bipolar devices of different sizes and geometries have been evaluated, along with a prototype Front-End readout ASIC designed for binary readout of silicon microstrip detectors. Gamma, neutron and proton irradiations have been performed up to the expected doses and fluences of the experiment.

Díez, S.; Clark, T.; Grillo, A. A.; Kononenko, W.; Martinez-McKinney, F.; Newcomer, F. M.; Norgren, M.; Rescia, S.; Spencer, E.; Spieler, H.; Ullán, M.; Wilder, M.

2013-10-01

9

A 130 nm CMOS mixed mode front end readout chip for silicon strip tracking at the future linear collider  

NASA Astrophysics Data System (ADS)

A 130 nm mixed (analog and digital) CMOS chip intended to read silicon strip detectors for future linear collider experiments was developed. Currently under testing, this chip has been optimized for a silicon micro-strip tracking device. It includes 88 channels of a full analog signal processing chain with the corresponding digital control and readout. Every analog channel includes (i) a low noise charge amplifier and integration with long pulse shaping, (ii) an eight by eight positions analog sampler for both storing successive events and reconstructing the full pulse shape, and (iii) a sparsifier performing analog sum of three adjacent inputs to decide whether there is signal or not. The whole system is controlled by the digital part, which allows configuring all the reference currents and voltages, drives the control signals to the analog memories, records the timing and channel information and subsequently performs the conversion to digital values of samples. The total surface of the circuit is 10×5 mm2, with each analog channel occupying an area of 105×3500 ?m2, and the remaining space of about 9000×700 ?m2 being filled by the analog channels on the silicon.

Pham, T. H.; Charpy, A.; Ciobanu, C.; Comerma, A.; David, J.; Dhellot, M.; Diéguez, A.; Gascon, D.; Genat, J. F.; Savoy Navarro, A.; Sefri, R.

2010-11-01

10

A 1.2V 0.1–3GHz software-defined radio receiver front-end in 130nm CMOS  

Microsoft Academic Search

A 1.2V 0.1-3GHz software-defined radio (SDR) receiver front-end in 130nm CMOS is presented. The current- driven passive mixer with 25% duty-cycle LO and reconfigurable inverter-based RF transconductor array (TCA) is utilized to satisfy the low 1\\/f noise and high linearity requirements. The current buffer is implemented as a like Tow- Thomas transimpedance biquad amplifier (TIA) with built-in 2 nd -order

Meng Cao; Baoyong Chi; Chun Zhang; Zhihua Wang

2011-01-01

11

The 1-V 24GHz low-voltage low-power current- mode transmitter in 130-nm CMOS technology  

Microsoft Academic Search

A new high frequency CMOS current-mode up-conversion mixer is proposed to realize the transmitter front-end in the frequency band of 24 GHz. The transmitter integrates with a double-balance current-mode up-conversion mixer, an IF amplifier\\/repeater, a differential VCO and a differential VCO buffer\\/repeater. The performance of the transmitter exhibits a conversion gain of 1.3 dB, the input 1-dB compression point (P-1db)

Wen-Chieh Wang; Chung-Yu Wu

2007-01-01

12

A 10–Bit 1.6GS\\/s 27mW Current-Steering D\\/A Converter With 550MHz 54dB SFDR Bandwidth in 130-nm CMOS  

Microsoft Academic Search

This paper presents a 10-bit 5-5 segmented current- steering digital-to-analog converter implemented in a standard 130-nm CMOS technology. It achieves full-Nyquist performance up to 1 GS\\/s and maintains 54-dB SFDR over a 550-MHz output bandwidth up to 1.6 GS\\/s. The power consumption for a near-Nyquist output signal sampled at 1.6 GS\\/s equals 27 mW. To enable the presented performance a

Pieter Palmers; Michiel S. J. Steyaert

2010-01-01

13

A saw-less direct conversion long term evolution receiver with 25% duty-cycle LO in 130 nm CMOS technology  

NASA Astrophysics Data System (ADS)

A CMOS long-term evolution (LTE) direct convert receiver that eliminates the interstage SAW filter is presented. The receiver consists of a low noise variable gain transconductance amplifier (TCA), a quadrature passive current commutating mixer with a 25% duty-cycle LO, a trans-impedance amplifier (TIA), a 7th-order Chebyshev filter and programmable gain amplifiers (PGAs). A wide dynamic gain range is allocated in the RF and analog parts. A current commutating passive mixer with a 25% duty-cycle LO improves gain, noise, and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference. Fabricated in a 0.13 ?m CMOS process, the receiver chain achieves a 107 dB maximum voltage gain, 2.7 dB DSB NF (from PAD port), -11 dBm IIP3, and > +65 dBm IIP2 after calibration, 96 dB dynamic control range with 1 dB steps, less than 2% error vector magnitude (EVM) from 2.3 to 2.7 GHz. The total receiver (total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.

Siyuan, He; Changhong, Zhang; Liang, Tao; Weifeng, Zhang; Longyue, Zeng; Wei, Lü; Haijun, Wu

2013-03-01

14

130-nm node mask development  

NASA Astrophysics Data System (ADS)

As device dimensions shrink, a detailed understanding of the exposure and development of masks is necessary to optimize electron-beam lithography. Because of proximity effects and dose distributions within the resist, achieving small- pattern fidelity is one of the most challenging tasks in maskmaking. The research discussed in this paper examines the exposure and process parameters that influence the fidelity of features on a photomask, with a focus on critical dimension (CD) uniformity, CD linearity, small- feature resolution, and long-term system performance. In accordance with operating recommendations for the MEBESTM 5500 systems, all experiments are performed with ZEP 7000 resist, 10 (mu) C/cm2 dose, ZED 750 developer, and dry etch. Some experiments employ GHOST proximity effect correction (FastPEC). These results are instructive for improved 130 nm node lithography and 180 nm node productivity.

Chabala, Jan M.; Weaver, Suzanne; Alexander, David W.; Lu, Maiying; Kim, Nam-Wook; Cole, Damon M.

2001-04-01

15

Overlay tool comparison for sub-130-nm technologies  

Microsoft Academic Search

The Overlay Metrology Advisory Group (OMAG), which includes representatives from International SEMATECH Member Companies and the National Institute of Standards and Technology, has collaborated to create a unified specification for overlay measurement tools [1]. The methodology and results of an overlay benchmarking comparison of several tools are discussed in this paper. As device technologies shrink below the sub-130nm range, a

Beth Russo; Michael Bishop; David C. Benoit; Richard M. Silver

2002-01-01

16

Improvement of photomask repeater for 130-nm lithography  

Microsoft Academic Search

Device masks for 180nm lithography was fabricated by PR system. These masks were verified by device yields comparing with masks written by other conventional systems. There were no differences in device yields between PR system and conventional system. Fine analysis of CD error was carried out for enhancement of CD uniformity to apply Photomask Repeater to 130nm lithography. It revealed

Suigen Kyoh; Soichi Inoue; Ichiro Mori; Nobuyuki Irie; Yuuki Ishii; Toshikazu Umatate; Haruo Kokubo; Naoya Hayashi

2001-01-01

17

Overlay tool comparison for sub-130-nm technologies  

NASA Astrophysics Data System (ADS)

The Overlay Metrology Advisory Group (OMAG), which includes representatives from International SEMATECH Member Companies and the National Institute of Standards and Technology, has collaborated to create a unified specification for overlay measurement tools [1]. The methodology and results of an overlay benchmarking comparison of several tools are discussed in this paper. As device technologies shrink below the sub-130nm range, a critical need arises to develop more precise tools to measure overlay. Overlay metrology capability needs to be available for detecting and controlling total device overlay regardless of the source of error. The misregistration measurement uncertainty introduced by the overlay tool can be compared for several systems. A benchmarking study is currently underway and focuses on the existing technique of optical measurement of centerline offsets in different target designs. The critical parameters that the study analyzes include precision, accuracy, throughput, through focus measurements, and recipe portability. Imaging issues such as low contrast targets, across wafer thickness variation, CMP effects, and grainy metal targets can contribute greatly to overlay errors. Several process stacks were designed to incorporate some of these imaging issues and test the limitations of the overlay tools. The same set of wafers and test locations were measured at each supplier site and the results were analyzed. This paper focuses on the methodology used for overlay benchmarking and examples of the results generated with respect to the parameters tested.

Russo, Beth; Bishop, Michael; Benoit, David C.; Silver, Richard M.

2002-07-01

18

Micromachined thermal radiation emitter from a commercial CMOS process  

NASA Astrophysics Data System (ADS)

Fabrication of thermally isolated micromechanical structures capable of generating thermal radiation for dynamic thermal scene simulation (DTSS) is described. Complete compatibility with a commercial CMOS process is achieved through design of a novel, but acceptable, layout for implementation by the CMOS foundry using its regular process sequence. Following commercial production and delivery of the CMOS chips, a single maskless etch in an aqueous ethylemediamine-pyrocatechol mixture is performed to realize the micromechanical structures. The resulting structures are suspended plates consisting of polysilicon resistors encapsulated in the field and CVD (chemical-vapor-deposited) oxides available in the CMOS process. The plates are suspended by aluminum heater leads that are also encapsulated in the field and CVD oxides. Studies of the suitability of these structures for DTSS have been initiated, and early favorable results are reported.

Parameswaran, M.; Robinson, Alexander M.; Blackburn, David L.; Gaitan, Michael; Geist, Jon

1991-02-01

19

RET-compliant cell generation for sub-130-nm processes  

NASA Astrophysics Data System (ADS)

The use of Resolution Enhancement Technologies (RET) is becoming mainstream for sub-wavelength lithography processes. Optical tools will not likely meet the process requirements for sub-130nm designs on their own. Different RET are being explored and in some cases, heavily used in order to improve the process window of sub-wavelength imaging. Model-based OPC, sub-resolution assist feature and phase shift masks are some of the most common RET Methods used to achieve production-worthy imaging. Every RET has its own limitations and advantages for every specific one. Some designs will not be able to be subjected to a specific RET because the layout is not friendly to it. Manual redesign of such layouts becomes intractable for very complex design with multiple cell attractive from the process integration point of view. By analysis standard cell libraries from an RET compliance attractive from the process integration point of view. By analysis standard cell libraries from an RET compliance perspective, it is possible to envision a methodology that can find the most RET-friendly design while maintaining the functional specification of every cell. This investigation focuses on sub-resolution assist features, alternating phase shift masks and double dipole. For most common RET approaches, minimum spacing, placement, width and feature geometry can be extracted from the RET compliance analysis. Later, a set of enhanced design rules that incorporate RET specific constraints is used to re-derive the optimal feature arrangement within the cells, until the cell meets the level of RET compliance defined by the user. Eventually, the process can be extended to ful layout compliance when all the interactions between individual cells is accounted for, and modified accordingly. The advantage of having RET compliant cell sis that during lace and route, the use can concentrate on optimizing global placement parameters instead of focusing on each individual cell. The final results will depend on the user requirements and acceptable parameters of ear, power, manufacturability, etc. This a general flow that is able to generate cells that meet electrical and manufacturing specifications and it is flexible enough to accommodate every existing RET.

Torres, Juan Andres; Chow, David; de Dood, Paul; Albers, Daniel J.

2002-07-01

20

Hardening of commercial CMOS PROMs with polysilicon fusible links  

NASA Astrophysics Data System (ADS)

The method by which a commercial 4K CMOS PROM with polysilicon fuses was hardened and the feasibility of applying this method to a 16K PROM are presented. A description of the process and the necessary minor modifications to the original layout are given. The PROM circuit and discrete device characteristics over radiation to 1000K rad-Si are summarized. The dose rate sensitivity of the 4K PROMs is also presented.

Newman, W. H.; Rauchfuss, J. E.

1985-12-01

21

Total dose hardness of three commercial CMOS microelectronics foundries  

Microsoft Academic Search

We have measured the effects of total ionizing dose (TID) on CMOS FETs, ring oscillators and field-oxide transistor test structures fabricated at three different commercial foundries with four different processes. The foundries spanned a range of integration levels and included Hewlett-Packard (HP) 0.5 ?m and 0.8 ?m processes, an Orbit 1.2 ?m process, and an AMI 1.6 ?m process. We

J. V. Osborn; R. C. Lacoe; D. C. Mayer; G. Yabiku

1998-01-01

22

Feasibility studies of ArF lithography for sub-130-nm lithography  

NASA Astrophysics Data System (ADS)

In this study, we evaluated the process margins of 193 nm lithography for sub-130 nm applications. We have investigated various cell structures and sizes for various illumination conditions such as the partial coherence factors, quadruple illuminations, and Optical Proximity Correction (OPC). We have also studied the Critical Dimension (CD) variation effects of topography with Bottom Anti-Reflective Coating (BARC) materials on various substrates such as silicon, nitride and aluminum. A 0.6 Numerical Aperture (NA) small field ArF stepper and a Hyundai-developed ArF single positive resist were used for this experiment. Internally-developed simulation program diffused aerial image model and Hyundai OPC simulation tool were also used to predict and effectively correct the optical proximity effect. The simulation result were compared with experimental results. Carefully optimizing the process conditions and optical settings, we obtained CD linearity of 190 nm, taking into account isolated-dense (ID) bias. With sub-130 nm VLSI cell pattern, we also verified the possibility of fabricating devices with sub-130 nm design rule by ArF lithography, with which we predicted some process issues such that ID bias of cell and peripheral patterns, CD bias of perpendicular axes in island patterns, contact hole patterns below 150 nm, pattern collapse, etc. Through this study, we verified that the 193 nm lithography could be applied for sub-130 nm technology.

Lee, Seung-Hyuk; Yim, Donggyu; Ham, Young-Mog; Baik, Kiho; Choi, Ilhyun

1999-07-01

23

Piezoresistive cantilevers in a commercial CMOS technology for intermolecular force detection  

Microsoft Academic Search

We report the development of piezoresistive cantilevers for intermolecular force detection in biochemical sensing, by using a commercial CMOS technology. The detection of the small forces involved in molecular recognition requires cantilevers with a small spring constant and high force sensitivity. We have fabricated polycrystalline silicon cantilevers by using the two polysilicon layers of a commercial CMOS process with minimum

Guillermo Villanueva; Francesc Pérez-Murano; Martin Zimmermann; Jan Lichtenberg; Joan Bausells

2006-01-01

24

Evaluation of DNQ\\/novolac resists for 130 nm device maskmaking  

Microsoft Academic Search

Several optical resists based on diazonaphthoquinone(DNQ)\\/novolac chemistry were evaluated for maskmaking application in the 130 nm device generation. Initial screening was performed at 10 kV with additional optimization at 50 kV. To enhance the electron-beam sensitivity, stronger metal ion developers were used. A Shipley i-line resist, SPR700, in conjunction with an optimized process, was found to demonstrate a bulk sensitivity

Zoilo C. H. Tan; Phuong Le; Homer Lem

1998-01-01

25

Embedded ferroelectric memory using a 130-nm 5 metal layer Cu \\/ FSG logic process  

Microsoft Academic Search

An embedded ferroelectric memory (FRAM) has been developed using a 1.5V, 130nm 5 metal layer Cu \\/ FSG logic process. The only modification to the logic process was the addition of a ferroelectric process consisting of two additional masks (FECAP, VIA0) immediately before MET1. The ferroelectric was 70nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The bit distribution

S. Summerfelt; S. Aggarwal; K. Boku; F. Celii; L. Hall; L. Matz; S. Martin; H. McAdams; K. Remack; J. Rodriguez; K. Taylor; K. R. Udayakumar; T. Moise; R. Bailey; M. Depner; G. Fox; J. Eliason

2004-01-01

26

Benchmarking of current generation overlay systems at the 130-nm technology node  

NASA Astrophysics Data System (ADS)

The Overlay Metrology Advisory Group (OMAG) is a group comprised of technical experts in the field of optical metrology from International SEMATECH Member Companies and the National Institute of Standards and Technology (NIST). This council created a specification for overlay metrology benchmarking which indicates the critical parameters to be addressed in order to comply with the International Technology Roadmap for Semiconductors (ITRS) for the 130-nm technology node. A benchmarking study was completed that compares several of the currently available overlay metrology tools. This paper contains the methodologies for benchmarking overlay metrology tools, a comparison of repeatability, reproducibility, throughput, tool-induced shift (TIS) variability, accuracy, and TIS through focus measurements between the participating tools. The tools were identified to the International SEMATECH Member Companies and the appropriate tool suppliers. The identity of the tools will remain only with these select groups. This paper intends to serve as a reference to the current tools' ability to meet the ITRS Roadmap specifications for the 130-nm technology node.

Russo, Beth; Bishop, Michael

2003-05-01

27

Lifetime studies of 130nm nMOS transistors intended for long-duration, cryogenic high-energy physics experiments.  

SciTech Connect

Future neutrino physics experiments intend to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. To increase performance, integrated readout electronics should work inside the cryostat. Due to the scale and cost associated with evacuating and filling the cryostat, the electronics will be unserviceable for the duration of the experiment. Therefore, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is via hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130nm nMOS transistors operating at cryogenic temperatures are investigated. The results show that the difference in lifetime for room temperature operation and cryogenic operation for this process are not great and the lifetimes at both 300K and at 77K can be projected to more than 20 years at the nominal voltage (1.5V) for this technology.

Hoff, J.R.; /Fermilab; Arora, R.; Cressler, J.D.; /Georgia Tech; Deptuch, G.W.; /Fermilab; Gui, P.; /Southern Methodist U.; Lourenco, N.E.; /Georgia Tech; Wu, G.; /Southern Methodist U.; Yarema, R.J.; /Fermilab

2011-12-01

28

Integration of RF-MEMS resonators on submicrometric commercial CMOS technologies  

NASA Astrophysics Data System (ADS)

Integration of electrostatically driven and capacitively transduced MEMS resonators in commercial CMOS technologies is discussed. A figure of merit to study the performance of different structural layers and different technologies is defined. High frequency (HF) and very high frequency (VHF) resonance MEMS metal resonators are fabricated on a deep submicron 0.18 µm commercial CMOS technology and are characterized using electrical tests without amplification, demonstrating the applicability of the MEMS fabrication process for future technologies. Moreover, the fabricated devices show comparable performance in terms of Q × fres with previously presented MEMS resonators, whereas the small gap allows obtaining a low motional resistance with a single resonator approach.

Lopez, J. L.; Verd, J.; Teva, J.; Murillo, G.; Giner, J.; Torres, F.; Uranga, A.; Abadal, G.; Barniol, N.

2009-01-01

29

A commercial 65nm CMOS technology for space applications: Heavy ion, proton and gamma test results and modeling  

Microsoft Academic Search

This paper presents new experimental and modeling evidences that advanced commercial CMOS technologies get intrinsically harder against space radiations with technology downscaling. When further using innovative rad-hard design techniques, electrical performances and radiation-hardness can be both met in a commercial CMOS 65 nm.

Philippe Roche; Gilles Gasiot; Slawosz Uznanski; Jean-Marc Daveau; Josep Torras-Flaquer; Sylvain Clerc; Reno Harboe-Sorensen

2009-01-01

30

Design And Testing Of SEU\\/ SEL Immune Memory And Logic Circuits In A Commercial Cmos Process  

Microsoft Academic Search

Test results for logic\\/circuit hardened memory circuits verify upset and latch-up immunity of greater than 120 MeV - cm2\\/mg using a commercial, non-radiation hardened CMOS process. An SEU immune logic family is also described.

Don Wiseman; John Canaris; Sterling Whitaker; Jack Venbrux; Kelly Cameron; Kari Arave; Larry Arave; M. Norley Liu; Kathy Liu

1993-01-01

31

Practicality of evaluating soft errors in commercial sub-90 nm CMOS for space applications  

Microsoft Academic Search

Inclusion of commercial technologies in civil spaceflight applications is reality. These technologies enable higher performance, reduce power consumption, and ultimately yield better science. However, the benefits do not come without cost, and radiation-induced soft errors in advanced, sub-90 nm CMOS technologies present new challenges. These challenges include sensitivity to proton direct ionization, memory technology evaluation, as well as testing and

Jonathan A. Pellish; Kenneth A. LaBel

2010-01-01

32

Meeting the challenges of process module and fab-wide active control for 300 mm, 130 nm, and beyond  

Microsoft Academic Search

With the introduction of 300 mm wafers to the ICS production line and the move to the 130 nm technology node, the requirements from individual tool and process modules become more critical when optimizing productivity and yield. For achieving top performance for the Fab, an 'Active control' is required. This 'Active control' system includes several components: Health Monitor, Fault Detection,

Israel Beinglass

2002-01-01

33

A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects  

Microsoft Academic Search

A leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported. Dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V. High Vt transistors have drive currents of 1.03 mA\\/?m and 0.5 mA\\/?m for NMOS and PMOS respectively, while low Vt transistors have currents of 1.17 mA\\/?m

S. Tyagi; M. Alavi; R. Bigwood; T. Bramblett; J. Brandenburg; W. Chen; B. Crew; M. Hussein; P. Jacob; C. Kenyon; C. Lo; B. McIntyre; Z. Ma; P. Moon; P. Nguyen; L. Rumaner; R. Schweinfurth; S. Sivakumar; M. Stettler; S. Thompson; B. Tufts; J. Xu; S. Yang; M. Bohr

2000-01-01

34

A 64 Mbit embedded FeRAM utilizing a 130 nm, 5LM Cu\\/FSG logic process  

Microsoft Academic Search

A low-voltage (1.3V), 64 Mbit Ferroelectric Random Access Memory using a 1-transistor, 1-capacitor (1T1C) cell is demonstrated. This is the largest FRAM memory demonstrated to date. The memory is constructed using a state-of-the-art 130 nm transistor and a five-level Cu\\/FSG interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate oxide, low-voltage logic

H. McAdams; R. Acklin; T. Blake; J. Fong; D. Liu; S. Madan; T. Moise; S. Natarajan; N. Qian; Y. Qui; J. Roscher; A. Seshadri; S. Summerfelt; X. Du; J. Eliason; W. Kraus; R. Lanham; F. Li; C. Pietrzyk; J. Rickes

2003-01-01

35

Millimeter-wave CMOS design  

Microsoft Academic Search

Abstract—This paper describes the design and modeling of CMOS transistors, integrated passives, and circuit blocks at millimeter-wave (mm-wave) frequencies. The effects of parasitics on the high-frequency performance of 130-nm CMOS transistors are investigated, and a peak of 135 GHz has been achieved with optimal device layout. The inductive quality factor is proposed as a more representative metric for transmission lines,

C. H. Doan; S. Emami; A. M. Niknejad; R. W. Brodersen

2005-01-01

36

Study of total ionizing dose radiation effects on enclosed gate transistors in a commercial CMOS technology  

Microsoft Academic Search

This paper studies the total ionizing dose radiation effects on MOS (metal-oxide-semiconductor) transistors with normal and enclosed gate layout in a standard commercial CMOS (compensate MOS) bulk process. The leakage current, threshold voltage shift, and transconductance of the devices were monitored before and after gamma-ray irradiation. The parameters of the devices with different layout under different bias condition during irradiation

Dong-Mei Li; Zhi-Hua Wang; Li-Ying Huangfu; Qiu-Jing Gou

2007-01-01

37

Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology  

Microsoft Academic Search

This work presents an efficient hybrid simulation approach, developed for accurate characterization of single-event transients (SETs) in combinational logic. Using this approach, we show that charges as small as 3.5fC can introduce transients in commercial 90nm CMOS technology, hence increasing the likelihood of SET- induced soft errors. SET pulse-widths as large as 942ps are predicted at an LET (Linear Energy

Riaz Naseer; Jeff Draper; Younes Boulghassoul; Sandeepan Dasgupta; Art Witulski

2007-01-01

38

Introducing 65 nm CMOS technology in low-noise read-out of semiconductor detectors  

NASA Astrophysics Data System (ADS)

The large scale of integration provided by CMOS processes with minimum feature size in the 100 nm range, makes them very attractive in the design of front-end electronics for highly pixelated detectors, where several functions need to be packed inside a relatively small silicon area. Nowadays, processes with 130 nm minimum channel length are widely available for Application Specific Integrated Circuits (ASICs) design, nonetheless designers are considering more scaled technologies following the trend of commercial silicon foundries. This work provides an extensive analysis of the noise performance which can be attained by detector front-end circuits in a 65 nm CMOS process. The behavior of the 1/f and white noise terms in this technology node is studied as a function of the device polarity, of the gate length and width and of the bias conditions. A comparison with data from previous CMOS generations is also carried out to evaluate the impact of scaling down to the 65 nm node.

Manghisoni, M.; Gaioni, L.; Ratti, L.; Re, V.; Traversi, G.

2010-12-01

39

Study of total ionizing dose radiation effects on enclosed gate transistors in a commercial CMOS technology  

NASA Astrophysics Data System (ADS)

This paper studies the total ionizing dose radiation effects on MOS (metal-oxide-semiconductor) transistors with normal and enclosed gate layout in a standard commercial CMOS (compensate MOS) bulk process. The leakage current, threshold voltage shift, and transconductance of the devices were monitored before and after ?-ray irradiation. The parameters of the devices with different layout under different bias condition during irradiation at different total dose are investigated. The results show that the enclosed layout not only effectively eliminates the leakage but also improves the performance of threshold voltage and transconductance for NMOS (n-type channel MOS) transistors. The experimental results also indicate that analogue bias during irradiation is the worst case for enclosed gate NMOS. There is no evident different behaviour observed between normal PMOS (p-type channel MOS) transistors and enclosed gate PMOS transistors.

Li, Dong-Mei; Wang, Zhi-Hua; Huangfu, Li-Ying; Gou, Qiu-Jing

2007-12-01

40

Micro Ethanol Sensors with a Heater Fabricated Using the Commercial 0.18 ?m CMOS Process.  

PubMed

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 µm complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-09-25

41

An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V  

Microsoft Academic Search

A leading edge 130 nm technology with 6 layers of Cu interconnects and 1.3 V operation has previously been presented (Tyagi et al., 2000). In this work, we enhance the previous technology with the following: transistor improvements which support a 60 nm gate dimension and increased drive current, improved 6-T SRAM device matching to allow low power and high performance

S. Thompson; M. Alavi; R. Arghavani; A. Brand; R. Bigwood; J. Brandenburg; B. Crew; V. Dubin; M. Hussein; P. Jacob; C. Kenyon; E. Lee; B. Mcintyre; Z. Ma; P. Moon; P. Nguyen; M. Prince; R. Schweinfurth; S. Sivakumar; P. Smith; M. Stettler; S. Tyagi; M. Wei; J. Xu; S. Yang; M. Bohr

2001-01-01

42

Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu\\/FSG logic process  

Microsoft Academic Search

We demonstrate the bit functionality of a low-voltage, embedded ferroelectric random-access memory constructed using a 130 nm gate and five-level Cu\\/FSG interconnect process. By inserting the two additional masks required for the eFRAM module into this logic flow, we have co-integrated ferroelectric memory and SRAM on a single wafer.

T. S. Moise; S. R. Summerfelt; H. McAdams; S. Aggarwal; K. R. Udayakumar; F. G. Celii; J. S. Martin; G. Xing; L. Hall; K. J. Taylor; T. Hurd; J. Rodriguez; K. Remack; M. D. Khan; K. Boku; G. Stacey; M. Yao; M. G. Albrecht; E. Zielinski; M. Thakre; S. Kuchimanchi; A. Thomas; B. McKee; J. Rickes; A. Wang; J. Grace; J. Fong; D. Lee; C. Pietrzyk; R. Lanham; S. R. Gilbert; D. Taylor; J. Amano; R. Bailey; F. Chu; G. Fox; S. Sun; T. Davenport

2002-01-01

43

Adaptation of a commercial optical CMOS image sensor for direct-detection fast x-ray imaging.  

SciTech Connect

We have adapted a commercial CMOS optical image sensor for use as a fast x-ray detector. The sensor was used in a mode where the x-rays impinge directly on the sensor. Area detectors can significantly improve the signal-to-noise ratio of acquired data in the low photon count rate situations (even at 3rd generation synchrotron sources) encountered in both small angle x-ray scattering (SAXS) and x-ray photon correlation spectroscopy (XPCS) experiments. CCD area detectors have been used for these types of experiments, but the relatively slow readout times typical of CCDs limit their use for studying the dynamics and kinetics of many samples. We characterized the performance of a CMOS optical detector for use in XPCS experiments.

Marschand, L. W.; Xuesong, J.; Sprung, M.; Kubik, D.; Tieman, B.; Lurio, L. B.; Sandy, A. R.; X-Ray Science Division; Northern Illinois Univ.

2007-01-01

44

Adaptation of a Commercial Optical CMOS Image Sensor for Direct-Detection Fast X-ray Imaging  

SciTech Connect

We have adapted a commercial CMOS optical image sensor for use as a fast x-ray detector. The sensor was used in a mode where the x-rays impinge directly on the sensor. Area detectors can significantly improve the signal-to-noise ratio of acquired data in the low photon count rate situations (even at 3rd generation synchrotron sources) encountered in both small angle x-ray scattering (SAXS) and x-ray photon correlation spectroscopy (XPCS) experiments,. CCD area detectors have been used for these types of experiments, but the relatively slow readout times typical of CCDs limit their use for studying the dynamics and kinetics of many samples. We characterized the performance of a CMOS optical detector for use in XPCS experiments.

Marschand, Lyle W.; Kubik, Donna; Lurio, Laurence B. [Department of Physics, Northern Illinois University, DeKalb, Illinois 60115 (United States); Jiao Xuesong; Sprung, Michael; Tieman, Brian; Sandy, Alec R. [Advanced Photon Source, Argonne National Laboratory, Argonne, IL 60439 (United States)

2007-01-19

45

Characterization of large-scale non-uniformities in a 20k TDC\\/SPAD array integrated in a 130nm CMOS process  

Microsoft Academic Search

With the emergence of large arrays of high- functionality pixels, it has become critical to characterize the performance non-uniformity of such arrays. In this paper we characterize a 160x128 array of complex pixels, each with a single-photon avalanche diode (SPAD) and a time-to-digital con- verter (TDC). A study of the array's non-uniformities in terms of the timing resolution, jitter, and

C. Veerappan; J. Richardson; R. Walker; D. U. Li; M. W. Fishburn; D. Stoppa; F. Borghetti; Y. Maruyama; M. Gersbach; R. K. Henderson; C. Bruschini; E. Charbon

2011-01-01

46

Analysis of the performance of CMOS APS imagers after proton damage  

NASA Astrophysics Data System (ADS)

In this work we have irradiated a standard commercial CMOS imager with a 24 MeV proton beam at INFN Laboratori Nazionali del Sud, Catania (Italy) up to a nominal fluence of 1014 [protons/cm-2]. The device under test was a standard VGA detector, fabricated with a 130 nm technology without radiation hardening. During the irradiation the detector was operated to monitor the progressive damaging of the sensor and the associated on-pixel electronics. After 18 months from the irradiation damage session, with the detector stored at room temperature, a study on the detection efficiency and charge collection capability has been carried out using fluorescent X-ray photons, emitted from copper target. We found that the detector is still working at 1013 protons/cm2, with a moderate increase of the noise and a slightly decrease of the detection capabilities.

Meroli, S.; Passeri, D.; Servoli, L.; Angelucci, A.

2013-02-01

47

130-nm node mask development  

Microsoft Academic Search

As device dimensions shrink, a detailed understanding of the exposure and development of masks is necessary to optimize electron-beam lithography. Because of proximity effects and dose distributions within the resist, achieving small- pattern fidelity is one of the most challenging tasks in maskmaking. The research discussed in this paper examines the exposure and process parameters that influence the fidelity of

Jan M. Chabala; Suzanne Weaver; David W. Alexander; Maiying Lu; Nam-Wook Kim; Damon M. Cole

2001-01-01

48

Development of a Radiation Tolerant 2.0 V standard cell library using a commercial deep submicron CMOS technology for the LHC experiments  

Microsoft Academic Search

A standard cell library was developed using a commercial 0.24 µm, 2.5 V CMOS technology. Radiation tolerant design techniques have been employed on the layout of the cells to achieve the total dose hardness levels required by LHC experiments. The library consists of digital core cell elements as well as a number of I\\/O pad cells. Additionally, it includes a

K. Kloukinas; F. Faccio; A. Marchioro; P. Moreira

49

Radiation Tolerant Circuits Designed in 2 Commercial 0.25(micro) CMOS Processes.  

National Technical Information Service (NTIS)

Characterization of simple devices as well as complex circuits, in two commercial 0.25 micron processes, demonstrates a high level (up to 58 Mrad) radiation tolerance of these technologies. They are also very likely to be immune to single event gate damag...

A. Mekkaoui J. Hoff D. C. Christian W. Wester R. Yarema

2001-01-01

50

Radiation tolerant circuits designed in 2 commercial 0.25{micro} CMOS processes  

SciTech Connect

Characterization of simple devices as well as complex circuits, in two commercial 0.25{micro} processes, demonstrates a high level (up to 58 Mrad) radiation tolerance of these technologies. They are also very likely to be immune to single event gate damage according to the results from 200 MeV-protons irradiation.

Mekkaoui, A. [and others

2001-03-08

51

Analysis of ESD protection components in 65nm CMOS technology: Scaling perspective and impact on ESD design window  

Microsoft Academic Search

A scaling analysis of fundamental ESD components (low voltage transistors, N-well diodes, interconnects and thin dielectrics) for the last three CMOS technology nodes (130 nm, 90 nm and 65 nm) targeting the same low-power applications is presented. The impact of technology scaling on the ESD design window will be discussed.

G. Boselli; J. Rodriguez; C. Duvvury; J. Smith

2005-01-01

52

Design methodology for micromechanical systems at commercial CMOS foundries through MOSIS  

Microsoft Academic Search

A methodology is presented for the design and fabrication of micromechanical structures through MOSIS. These structures form a new class of devices which are based on electro-thermal-mechanical properties and can be fabricated at commercial foundries. Associated circuits can be integrated for communication and control. The technique is a method of making micro-electro-mechanical systems with minimal additional equipment cost using existing

Michael Gaitan; M. Parameswaran; M. Zaghloul; Janet Marshall; Donald Novotny; J. Suehle

1992-01-01

53

Illumination pupil fill measurement and analysis and its application in scanner V-H bias characterization for 130-nm node and beyond  

NASA Astrophysics Data System (ADS)

A detailed characterization of across chip line width variation (ACLV) has been carried out on the latest Nikon scanners with a combination of advanced metrology techniques in Texas Instruments, including scatterometer-based image field and CD fingerprinting, lens aberrations measurement using a Litel in-situ interferometer, and illumination source imaging with a pin-hole camera. This paper describes the application of the above techniques in our investigation of the root causes for pattern CD bias between vertical and horizontal features. Illumination source radiance distribution is found sometimes to have a significant impact on V-H bias and the final overall ACLV on production wafers. Examples are given to demonstrate a comprehensive methodology that is used to quantitatively break down the overall CD errors and correlate them back to the basic optical and imaging components. It is shown through pupil-gram analysis that the ellipticity in partial coherence is typically within 1+/-1% for conventional illuminations settings on the advanced Nikon scanners while the uneven radiance distribution across the source plays a major role in V-H pattern CD bias. For scanners with low and uniform lens coma aberrations, the V-H bias after removing the contribution from image field errors is found to follow a linear relationship with the source radiance non-uniformity described also in terms of ellipticity. It is shown that radiance ellipticity is a bigger concern for off-axis illuminators. Tighter design rules patterned with off-axis illumination are more vulnerable to source radiance non-uniformity as well as lens aberrations. Illuminator induced V-H bias across the slit is compared to the signature caused by lens aberrations specifically uneven x,y-coma. Implications to exposure tool specification, control, and matching are further explored through experiments and lithography simulation for the current 130nm production and the future technology nodes in development.

Zhang, Gary; Wang, Changan; Tan, Colin L.; Ilzhoefer, John R.; Atkinson, Chris; Renwick, Stephen P.; Slonaker, Steve D.; Godfrey, David; Fruga, Catherine H.

2003-06-01

54

A 243GHz Ft and 208GHz Fmax, 90-nm SOI CMOS SoC technology with low-power millimeter-wave digital and RF circuit capability  

Microsoft Academic Search

SOI CMOS technology offers low parasitic junction capacitance, and therefore provides speed and power enhancements to digital applications compared to bulk CMOS. It is also emerging as a good candidate for high-performance SoC, with integratable RF circuits that operate beyond 30-GHz already demonstrated at the 130-nm technology node. The digital aspects of the base 90-nm SOI technology were previously reported.

Noah Zamdmer; Jonghae Kim; Robert Trzcinski; Jean-Olivier Plouchart; Shreesh Narasimha; Mukesh Khare; Lawrence Wagner; Susan Chaloux

2004-01-01

55

CMOS IC Fabrication Issues for High-k Gate Dielectric and Alternate Electrode Materials  

Microsoft Academic Search

Silicon dioxide based dielectrics such as SiO2 and nitrided SiO 2 (SiON) are reaching the limit of their usefulness in complementary metal oxide semiconductor (CMOS) devices principally because of high tunnel currents. The semiconductor industry has adopted SiON at the 130 nm node where equivalent oxide thicknesses less than 2 nm are typically used for the high-performance devices. But SiON

L. Colombo; A. L. P. Rotondaro; M. R. Visokay; J. J. Chambers

56

SiGe BiCMOS Technology with 3.0 ps Gate Delay  

Microsoft Academic Search

This work reports on a 130 nm BiCMOS technology with high-speed SiGe:C HBTs featuring a transit frequency of 255 GHz and a maximum oscillation frequency of 315 GHz at an emitter area of 0.17 x 0.53 mum2. A minimum gate delay of 3.0 ps was achieved for CML ring oscillators. Breakdown voltages of the HBTs are measured to be BVCEO=1.8

H. Riicker; B. Heinemann; R. Barth; J. Bauer; D. B. K. Blum; D. Bolze; J. Drews; G. G. Fischer; A. Fox; O. Fursenko; T. Grabolla; U. Haak; W. Hoppner; D. Knoll; K. Kopke; B. Kuck; A. Mai; S. Marschmeyer; T. Morgenstern; H. H. Richter; P. Schley; D. Schmidt; K. Schulz; B. Tillack; G. Weidner; W. Winkler; D. Wolansky; H.-E. Wulf; Y. Yamamototo

2007-01-01

57

Schottky barrier diodes for millimeter wave detection in a foundry CMOS process  

Microsoft Academic Search

CoSi2-Si Schottky barrier diodes on an n-well and on a p-well\\/substrate are fabricated without a guard ring in a 130-nm foundry CMOS process. The nand p-type diodes with an area of 16×0.32×0.32 ?m2 achieve cutoff frequencies of ?1.5 and ?1.2 THz at 0-V bias, respectively. These are the highest cutoff frequencies for Schottky diodes fabricated in foundry silicon processes. The

Swaminathan Sankaran; Kenneth K. O

2005-01-01

58

Total dose radiation effects on the hardened CMOS\\/bulk and CMOS\\/SOS  

Microsoft Academic Search

Radiation-resistant performance of commercial and rad-hard CMOS\\/bulk and CMOS\\/SOS devices is presented in the total dose environment, when the static power currents of CMOS are increased by a hundred times over the limit value before irradiation, the IDD is determined as the failure criteria of ionizing radiation damage. The ? total dose ionizing radiation failure threshold of commercial CMOS devices

Panxun Chen; Hongzhi Wu; Guanglun Li; Yunhan He; Peijen Li; Yi Mao

1991-01-01

59

Continuous measurement of radiation damage of standard CMOS imagers  

NASA Astrophysics Data System (ADS)

In this work we have irradiated a standard CMOS VGA imager with a 24 MeV proton beam at INFN Laboratori Nazionali del Sud, up to a nominal fluence of 10 14 protons/cm 2 . The device under test was fabricated with a 130 nm technology without radiation hardening. During the damaging the detector was fully operational to monitor the progressive damaging of the sensor and the associated on-pixel electronics in terms of detection efficiency, charge collection and noise. We found that the detector is still working at 10 13 protons/cm 2 , with a moderate increase of the noise (20%).

Servoli, Leonello; Bizzarri, Fabrizio; Passeri, Daniele

2011-12-01

60

A 5MHz low-noise 130nm CMOS analog front-end electronics for the readout of non-linear DEPFET sensor with signal compression for the European XFEL  

Microsoft Academic Search

We present an integrated analog front-end for the readout of a non-linear DEPFET Sensor with Signal Compression (DSSC). The DSSC system, currently under development, is a 1-Mega pixel detector system for the European X-ray Free Electron Laser (XFEL) in Hamburg. It will record X-ray images with a maximum frame rate of 4.5MHz and will achieve at the same time a

Giulio De Vita; Luca Bombelli; Matteo Porro; Sven Herrmann; Andreas Wassatsch; Stefano Facchinetti; Carlo Fiorini; Florian Erdinger

2010-01-01

61

A Ultra-Wideband Amplitude Modulation (AM) Detector Using Schottky Barrier Diodes Fabricated in Foundry CMOS Technology  

Microsoft Academic Search

Utility of Schottky diodes fabricated in foundry digital 130-nm CMOS technology is demonstrated by implementing an ultra-wideband (UWB) amplitude modulation detector consisting of a low-noise amplifier (LNA), a Schottky diode rectifier, and a low-pass filter. The input and output matching of the detector is better than -10 dB from 0-10.3 GHz and 0-1.7 GHz, respectively, and almost covers the entire

Swaminathan Sankaran; Kenneth K. O

2007-01-01

62

Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu\\/PECVD low-k BEOL  

Microsoft Academic Search

Integration and development of Cu Back-End of Line (BEOL) with PECVD low-k organosilicate glass (OSG, also called SiCOH, carbon-doped oxide, CDO, etc.) for 130 nm and 90 nm CMOS technologies has been reported by a number of institutions. Here we report on a Cu\\/SiCOH technology which has similarities, but also enhanced integration and reliability characteristics while preserving the R and

D. Edelstein; H. Rathore; C. Davis; L. Clevenger; A. Cowley; T. Nogami; B. Agarwala; S. Arai; A. Carbone; K. Chanda; F. Chen; S. Cohen; W. Cote; M. Cullinan; T. Dalton; S. Das; P. Davis; J. Demarest; D. Dunn; C. Dziobkowski; R. Filippi; J. Fitzsimmons; P. Flaitz; S. Gates; J. Gill; A. Grill; D. Hawken; K. Ida; D. Klaus; N. Klymko; J. Lee; W. Landers; W.-K. Li; Y.-H. Lin; E. Liniger; X.-H. Liu; A. Madan; S. Malhotra; J. Martin; S. Molis; C. Muzzy; D. Nguyen; S. Nguyen; M. Ono; C. Parks; D. Questad; D. Restaino; A. Sakamoto; T. Shaw; Y. Shimooka; A. Simon; E. Simonyi; A. Swift; T. Van Kleeck; S. Vogt; Y.-Y. Wang; W. Wille; J. Wright; C.-C. Yang; M. Yoon; T. Ivers

2004-01-01

63

CMOS photonics  

Microsoft Academic Search

Light will be connecting CMOS chips sooner than you think. While every major semiconductor company is exploring silicon photonics in their research labs, Luxtera has implemented a practical version of the technology in a high-volume production CMOS process. The base process is Freescale's 0.13 ?m SOI CMOS, used to manufacture many of their high-performance PowerPC processors. In addition to the

C. Gunn

2005-01-01

64

Beam-test results of 4k pixel CMOS MAPS and high resistivity striplet detectors equipped with digital sparsified readout in the Slim5 low mass silicon demonstrator  

Microsoft Academic Search

The results obtained by the Slim5 collaboration on a low material budget tracking silicon demonstrator put on a 12GeV\\/c proton test beam at CERN are reported. Inside a reference telescope, two different and innovative detectors were placed for careful tests. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130nm CMOS Technology, square pixels 50?m

M. Villa; M. Bruschi; R. Di Sipio; L. Fabbri; B. Giacobbe; A. Gabrielli; F. Giorgi; G. Pellegrini; C. Sbarra; N. Semprini; R. Spighi; S. Valentinetti; A. Zoccoli; C. Avanzini; G. Batignani; S. Bettarini; F. Bosi; G. Calderini; M. Ceccanti; R. Cenci; A. Cervelli; F. Crescioli; M. Dell’Orso; F. Forti; P. Giannetti; M. A. Giorgi; A. Lusiani; S. Gregucci; P. Mammini; G. Marchiori; M. Massa; F. Morsani; N. Neri; E. Paoloni; M. Piendibene; A. Profeti; G. Rizzo; L. Sartori; J. Walsh; E. Yurtsev; M. Manghisoni; V. Re; G. Traversi; C. Andreoli; L. Gaioni; E. Pozzati; L. Ratti; V. Speziali; D. Gamba; G. Giraudo; P. Mereu; G. F. Dalla Betta; G. Soncini; G. Fontana; M. Bomben; L. Bosisio; P. Cristaudo; G. Giacomini; D. Jugovaz; L. Lanceri; I. Rashevskaya; L. Vitale; G. Venier

2010-01-01

65

Vertically integrated deep N-well CMOS MAPS with sparsification and time stamping capabilities for thin charged particle trackers  

NASA Astrophysics Data System (ADS)

A fine pitch, deep N-well CMOS monolithic active pixel sensor (DNW CMOS MAPS) with sparsified readout architecture and time stamping capabilities has been designed in a vertical integration (3D) technology. In this process, two 130 nm CMOS wafers are face-to-face bonded by means of thermo-compression techniques ensuring both the mechanical stability of the structure and the electrical interconnection between circuits belonging to different layers. This 3D design represents the evolution of a DNW monolithic sensor already fabricated in a planar 130 nm CMOS technology in view of applications to the vertex detector of the International Linear Collider (ILC). The paper is devoted to discussing the main design features and expected performance of the 3D DNW MAPS. Besides describing the front-end circuits and the general architecture of the detector, the work also provides some results from calculations and Monte Carlo device simulations comparing the old 2D solution with the new 3D one and illustrating the attainable detection efficiency improvements.

Ratti, L.; Gaioni, L.; Manghisoni, M.; Re, V.; Traversi, G.

2010-12-01

66

Mixing in a 220MHz CMOS-MEMS  

Microsoft Academic Search

This paper describes the frequency mixing operation of a micro electro mechanical system device designed and fabricated in a CMOS commercial technology (AMS 0.35mum). The theory of the MEMS is summarized and a CMOS fully integrated MEMS is characterized as a mixer. The designed MEMS is a polysilicon clamped-clamped beam that presents a resonance frequency in the VHF range. CMOS-MEMS

J. L. Lopez; Jordi Teva; Arantxa Uranga; F. Torres; Jaume Verd; Gabriel Abadal; Nuria Barniol; Jaume Esteve; Francesc Pérez-murano

2007-01-01

67

Solar XUV Imaging and Nondispersive Spectroscopy for Solar-C Enabled by Scientific CMOS APS Arrays  

Microsoft Academic Search

Monolithic CMOS Advanced Pixel Sensor (APS) arrays are showing great promise as eventual replacements for the current workhorse of solar physics focal planes, the scientific CCD. CMOS APS devices have individually addressable pixels, increased radiation tolerance compared to CCDs, and require lower clock voltages, and thus lower power. However, commercially available CMOS chips, while suitable for use with intensifiers or

Robert A. Stern; J. R. Lemen; L. Shing; J. Janesick; J. Tower

2009-01-01

68

A CMOS SPDT switch  

Microsoft Academic Search

In this work, a novel architecture with stacked-type CMOS device is presented. The reformed CMOS switch was implemented by the TSMC 0.18 um 1P6M standard CMOS process. In order to improve power handling capability and strengthen the isolation, the proposed circuit is inserted with an excess transistor adjacent to the receiver side. The insertion loss of the designed CMOS T\\/R

Jheng-Da Wu; Janne-Wha Wu; Chih-Ho Tu; Ching-Wen Tang; Chien-You Lai; Bing-Jiun Lai; Wei-Ju Lai; Liang-Yeh Chi; Ying-Zong Juang

2008-01-01

69

65-nm CMOS Monolithically Integrated Subterahertz Transmitter  

Microsoft Academic Search

This letter presents a transmitter for subterahertz ra- diation (up to 160 GHz), which consists of a nonlinear transmission line (NLTL) and an extremely wideband (EWB) slot antenna on a silicon substrate of low resistivity (10 ? · cm). The fabrication was realized using a commercially available 65-nm CMOS pro- cess. On-wafer characterization of the whole transmitter, of the stand-alone

Xin Hu; Lorenzo Tripodi; Marion K. Matters-Kammerer; Shi Cheng; Anders Rydberg

2011-01-01

70

CMOS image sensors  

Microsoft Academic Search

In this article, we provide a basic introduction to CMOS image-sensor technology, design and performance limits and present recent developments and future directions in this area. We also discuss image-sensor operation and describe the most popular CMOS image-sensor architectures. We note the main non-idealities that limit CMOS image sensor performance, and specify several key performance measures. One of the most

A. El Gamal; H. Eltoukhy

2005-01-01

71

3D monolithically stacked CMOS active pixel sensor detectors for particle tracking applications  

NASA Astrophysics Data System (ADS)

In this work we propose an innovative approach to particle tracking based on CMOS Active Pixel Sensors layers, monolithically integrated in an all-in-one chip featuring multiple, stacked, fully functional detector layers capable to provide momentum measurement (particle impact point and direction) within a single detector. This will results in a very low material detector, thus dramatically reducing multiple scattering issues. To this purpose, we rely on the capabilities of the CMOS vertical scale integration (3D IC) technology. A first chip prototype has been fabricated within a multi-project run using a 130 nm CMOS Chartered/Tezzaron technology, featuring two layers bonded face-to-face. Tests have been carried out on full 3D structures, providing the functionalities of both tiers. To this purpose, laser scans have been carried out using highly focussed spot size obtaining coincidence responses of the two layers. Tests have been made as well with X-ray sources in order to calibrate the response of the sensor. Encouraging results have been found, fostering the suitability of both the adopted 3D-IC vertical scale fabrication technology and the proposed approach for particle tracking applications.

Passeri, D.; Servoli, L.; Meroli, S.; Magalotti, D.; Placidi, P.; Marras, A.

2012-08-01

72

Intelligent CMOS sensors  

Microsoft Academic Search

CMOS including micromechanics using polysilicon structures as functional layers is a promising technology for production of Intelligent CMOS Sensors. Its cost and performance advantages allow to address volume markets like monolithic integrated sensors for automotive application. Using modern silicon processes and their potential for large scale integration, new functions like on-chip calibration and diagnosis are possible. Furthermore, it offers direct

Christofer Hierold

2000-01-01

73

A 1.2 V 10-bit 60MS\\/s 23 mW CMOS pipeline ADC with 0.67 pJ\\/conversion-step and on-chip reference voltages generator  

Microsoft Academic Search

A 1.2 V 10-bit 60 MS\\/s pipeline Analog-to-Digital Converter (ADC), fabricated in a 130 nm CMOS technology, is presented. The prototype is composed by five 3-bit pipeline stages\\u000a and a Sample and Hold (S&H) circuit at the front. Two-stage Miller-compensated Operational Transconductance Amplifiers (OTAs), offset-compensated comparators and bootstrapping sampling switches have been used due to the low voltage\\u000a supply requirements. Special attention has

Jesús Ruiz-Amaya; Manuel Delgado-Restituto; Ángel Rodríguez-Vázquez

74

DRAM lithographic scaling in the sub-130-nm regime  

NASA Astrophysics Data System (ADS)

Continuous downward pressure on chip size has led to aggressive ground rule shrink paths in the semiconductor industry, especially in the DRAM sector. Ever-decreasing feature sizes have necessitated the extensive use of attenuated phase shift masks, off-axis illumination, optical proximity correction, etc. For the foreseeable future, the ability to meet the demands of the design is closely tied to the extendibility of ArF lithography. This paper explores DRAM lithographic scaling by predicting required process latitude and depth of focus based on litho-graphic merit function scaling. This allows the predictions to be anchored against data collected on current products, as well as indicating the rate at which learning must occur for a ground rule shrink to be successful. Modeling of ArF extendibility is presented, with particular emphasis on the role of alternating phase shift masks. Additionally, simple signal-to-noise argu-ments are made in connection with the required process window for a given technology, taking into the account fundamental error sources of the process. The analyses are anchored to existing technologies wherever possible. The results indicate that ArF lithography will extend through the 90 nm technology node with a critical dependence on alternating phase shift masks.

Bukofsky, Scott J.

2001-09-01

75

A CMOS humidity sensor with on-chip calibration  

Microsoft Academic Search

This paper describes a capacitive humidity sensor with on-chip calibration circuit fabricated by a standard CMOS process to achieve a cost-effective solution for accurate and reliable humidity measurement. The humidity sensing property on-chip is obtained by a post-processing step after the standard CMOS fabrication and whereby a commercial polyimide is deposited on the packaged chip. The sensing principle of the

Y. Y. Qiu; C. Azeredo-Leme; L. R. Alcácer; J. E. Franca

2001-01-01

76

CMOS active pixel image sensors for highly integrated imaging systems  

Microsoft Academic Search

A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-?m CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression

Sunetra K. Mendis; Sabrina E. Kemeny; Russell C. Gee; Bedabrata Pain; Craig O. Staller; Quiesup Kim; Eric R. Fossum

1997-01-01

77

A Ku-band CMOS low-noise amplifier  

Microsoft Academic Search

A Ku-band monolithic low-noise amplifier is presented in this paper. This LNA fabricated in commercial 0.18-?m CMOS technology is a two-stage common-source design instead of cascode configuration for lower noise performance. This CMOS LNA demonstrates a gain of better than 10 dB and a NF of better than 3.2 dB from 14 to 15 GHz. The measured output P1dB is

Kuo-Liang Deng; Ming-Da Tsai; Chin-Shen Lin; Kun-You Lin; Huei Wang; S. H. Wang; W. Y. Lien; G. J. Chem

2005-01-01

78

Review of RF CMOS Performance and Future Process Innovations  

Microsoft Academic Search

This report contains a review of CMOS process technology in terms of radio-frequency(RF) performance around and beyond 1GHz. First, the use of integrated technology forwireless communications is justified and state-of-the-art commercial chipsets are presented.After CMOS is presented as a potential RF candidate, the major elements of the technologyare evaluated in an RF context and current performance is listed. Elements include

Troels Emil Kolding

1998-01-01

79

Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis  

Microsoft Academic Search

FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0\\/1 fault model. Faults

John Paul Shen; F. Joel Ferguson

1988-01-01

80

Integrated CMOS-MEMS with on-chip readout electronics for high-frequency applications  

Microsoft Academic Search

A bridge-shaped first-lateral-mode 60-MHz mechanical resonator, which is monolithically integrated with capacitive CMOS readout electronics, is presented. The resonator is fabricated directly on a commercial CMOS technology using the top metal level as a structural layer. A maskless single-step wet-etching process for mechanical structure release after the standard CMOS integration process is the only postfabrication requirement. Electrical characterization of the

J. Verd; A. Uranga; J. Teva; J. L. Lopez; F. Torres; J. Esteve; G. Abadal; F. Perez-Murano; N. Barniol

2006-01-01

81

Implantable CMOS Biomedical Devices  

PubMed Central

The results of recent research on our implantable CMOS biomedical devices are reviewed. Topics include retinal prosthesis devices and deep-brain implantation devices for small animals. Fundamental device structures and characteristics as well as in vivo experiments are presented.

Ohta, Jun; Tokuda, Takashi; Sasagawa, Kiyotaka; Noda, Toshihiko

2009-01-01

82

Pulsed bipolar CMOS imager  

Microsoft Academic Search

This paper will describe an acti ve pixel CMOS-compatible im- ager aimed at high resolution still cameras. We will discuss pixel operation, column sense circuits, serial output, and show results from existing imagers. In this abstract, we show results from a prototype 640x480 imager with 5.9x5.9 ?m2 pixels built in 0.8 ?m double-poly CMOS with one additional base implant.

Tobi Delbruck; Nicholas Mascarenhas; Min-Hwa Chi; Albert Bergemont; Carver Mead

83

Monolithic CMUT on CMOS Integration for Intravascular Ultrasound Applications  

PubMed Central

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array.

Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F. Levent

2012-01-01

84

Graphene for CMOS and Beyond CMOS Applications  

Microsoft Academic Search

Owing in part to complementary metal-oxide-semiconductor (CMOS) scaling issues, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide a solution beyond the 22-nm node. Single and few layers of carbon sheets (graphene) have been fabricated by a variety of techniques including mechanical exfoliation and chemical vapor deposition, and field-effect devices have been demonstrated

Sanjay K. Banerjee; Leonard Franklin Register; Emanuel Tutuc; Dipanjan Basu; Seyoung Kim; Dharmendar Reddy; Allan H. MacDonald

2010-01-01

85

A 3D Vertically Integrated Deep N-Well CMOS MAPS for the SuperB Layer0  

NASA Astrophysics Data System (ADS)

Deep N-Well (DNW) Monolithic Active Pixel Sensors (MAPS) have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. In these devices the triple well option, available in deep submicron processes, is exploited to implement analog and digital signal processing at the pixel level. Many prototypes have been fabricated in a planar (2D) 130nm CMOS technology. A new kind of DNW-MAPS, namely Apsel5_3D, which exploits the capabilities of vertical integration (3D) processes, is presented and discussed in this paper. The impact of 3D processes on the design and performance of DNW pixel sensors could be large, with significant advantages in terms of detection efficiency, pixel cell size and immunity to cross-talk, therefore complying with the severe constraints set by future HEP experiments.

Traversi, G.; Gaioni, L.; Manghisoni, M.; Ratti, L.; Re, V.

2011-01-01

86

CMOS image sensors: State-Of-the-art and future perspectives  

Microsoft Academic Search

Over the last decade, CMOS image sensor technology made huge progress. Not only the performance of the imagers was drastically improved, but also their commercial success boomed after the introduction of mobile phones with an onboard camera. Many scientists and marketing specialists predicted 15 years ago that CMOS image sensors were going to completely take over from CCD imagers, in

Albert THEUWISSEN

2007-01-01

87

CMOS image sensors: State-of-the-art and future perspectives  

Microsoft Academic Search

Over the last decade, CMOS image sensor technology made huge progress. Not only the performance of the imagers was drastically improved, but also their commercial success boomed after the introduction of mobile phones with an onboard camera. Many scientists and marketing specialists predicted 15 years ago that CMOS image sensors were going to completely take over from CCD imagers, in

Albert THEUWISSEN

2007-01-01

88

Electronics and photonics convergence on Si CMOS platform  

NASA Astrophysics Data System (ADS)

The present paper describes Si microphotonics and its current status of electronics and photonics convergence on Si platform based on monolithic integration using CMOS (Complementary Metal Oxide Semiconductor) technologies. The Si CMOS platform is advantageous over III-V semiconductor based platform because of a short time-lag between basic research and commercialization in terms of the standardized materials and processes. To implement photonic devices on the Si CMOS platform, it is important to reduce materials diversity in current photonics devices. Low loss SiNx waveguides with sharp bends, high performance strained Ge photodetectors for C+L band, and demultiplexer/multiplexer for WDM (wavelength division multiplexing) have been successfully implemented on the Si CMOS platform. The current targets are cost-effective OADMs (optical add-drop multiplexers) for optical communication and optical clocking for Si LSIs beyond Cu-low k technologies.

Wada, Kazumi

2004-07-01

89

CMOS imaging for automotive applications  

Microsoft Academic Search

This contribution is devoted to CMOS imaging for automotive applications. It is shown that unlike CCD-based imaging, imaging based on CMOS-sensing meets adequately requirements posed by automotive vision applications. In addition, besides classical vision, CMOS imaging enables new applications like, e.g., occupancy sensing, rangefinding, and 3-D vision.

B. J. Hosticka; W. Brockherde; A. Bussmann; T. Heimann; R. Jeremias; A. Kemna; C. Nitta; O. Schrey

2003-01-01

90

CMOS dot matrix microdisplay  

NASA Astrophysics Data System (ADS)

Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

Venter, Petrus J.; Bogalecki, Alfons W.; Du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

2011-02-01

91

CMOS MEMS capacitive absolute pressure sensor  

NASA Astrophysics Data System (ADS)

This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal-oxide-semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa-1 in the pressure range of 0-300 kPa.

Narducci, M.; Yu-Chia, L.; Fang, W.; Tsai, J.

2013-05-01

92

Smart 45nm Foundry CMOS with Mask-Lite (trademark) Reduced Mask Costs.  

National Technical Information Service (NTIS)

American Semiconductor has created Mask-Lite which is a layout and fabrication strategy that reduces mask costs and improves access to advanced 45nm bulk CMOS from their ITAR registered and TRUSTED ready on-shore commercial foundry.

D. G. Wilson K. Hebert R. L. Chaney S. D. Hackler

2011-01-01

93

Scaled CMOS MEMS for real-time infrared scene generation  

NASA Astrophysics Data System (ADS)

CMOS/MEMS is used as a technique to create infrared emitters. A commercial CMOS process is used that, with a post-processing silicon etch, creates thermally isolated, electronically addressable polysilicon resistors suitable for infrared scene generation. Previous efforts have focused on 2.0 micron CMOS processes which require large suspended structures in order to accommodate the design rules. This work has successfully used a 1.2 micron commercial process with a post-processing silicon etch to scale down the emitter structure to 40 X 40 microns. This allows higher density arrays, and together with using the high value poly resistor available in the 1.2 micrometer process, allows lower current operation, significantly relaxing the design constraints previously encountered. A 128 X 128 design was fabricated in this process and is characterized using a microradiometer. A silicon-on-insulator thermal pixel array design with a further reduction in emitter dimensions is also presented.

Offord, Bruce W.; Marlin, H. Ronald; Bates, Richard L.; Perkins, Gordon C.; Hutchens, Chris; Huang, Derek

2000-07-01

94

Surface enhanced biodetection on a CMOS biosensor chip  

NASA Astrophysics Data System (ADS)

We present a rigorous electromagnetic theory of the electromagnetic power emitted by a dipole located in the vicinity of a multilayer stack. We applied this formalism to a luminescent molecule attached to a CMOS photodiode surface and report light collection efficiency larger than 80% toward the CMOS silicon substrate. We applied this result to the development of a low-cost, simple, portable device based on CMOS photodiodes technology for the detection and quantification of biological targets through light detection, presenting high sensitivity, multiplex ability, and fast data processing. The key feature of our approach is to perform the analytical test directly on the CMOS sensor surface, improving dramatically the optical detection of the molecule emitted light into the high refractive index semiconductor CMOS material. Based on adequate surface chemistry modifications, probe spotting and micro-fluidics, we performed proof-of-concept bio-assays directed against typical immuno-markers (TNF-? and IFN-?). We compared the developed CMOS chip with a commercial micro-plate reader and found similar intrinsic sensitivities in the pg/ml range.

Belloni, Federico; Sandeau, Laure; Contié, Sylvain; Vicaire, Florence; Owens, Roisin; Rigneault, Hervé

2012-02-01

95

Automotive CMOS Image Sensors  

Microsoft Academic Search

After penetrating the consumer and industrial world for over a decade, digital imaging is slowly but inevitably gaining marketshare in the automotive world. Cameras will become a key sensor in increasing car safety, driving assistance and driving comfort. The image sensors for automotive will be dominated by CMOS sensors as the requirements are different from the consumer market or the

S. Maddalena; A. Darmon; R. Diels

96

Implantable CMOS Biomedical Devices.  

PubMed

The results of recent research on our implantable CMOS biomedical devices are reviewed. Topics include retinal prosthesis devices and deep-brain implantation devices for small animals. Fundamental device structures and characteristics as well as in vivo experiments are presented. PMID:22291554

Ohta, Jun; Tokuda, Takashi; Sasagawa, Kiyotaka; Noda, Toshihiko

2009-11-17

97

CMOS Bridging Fault Detection  

Microsoft Academic Search

The authors compare the performance of two test generation techniques, stuck fault testing and current testing, when applied to CMOS bridging faults. Accurate simulation of such faults mandated the development of several new design automation tools, including an analog-digital fault simulator. The results of this simulation are analyzed. It is shown that stuck fault test generation, while inherently incapable of

Thomas M. Storey; Wojciech Maly

1990-01-01

98

Reconfigurable subthreshold CMOS perceptron  

Microsoft Academic Search

We present an idea for a new real-time reconfigurable perceptron, also called, a threshold element. The circuit example contain three inverters with shorted outputs. SPICE simulations for a 0.6 ?m CMOS implementation operating in the subthreshold region. are shown. The threshold voltages of the active devices, seen from driving nodes, may be dynamically changed by adjusting their substrate potentials. This

Snorre Aunet; Bengt Oelmann; Suliman Abdalla; Yngvar Berg

2004-01-01

99

A Fully Cmos 622 Mbit\\/s Atm Switching Element  

Microsoft Academic Search

This paper deals with the CMOS realization of a circuit for ATM (Asynchronous Transfer Mode) switching applications. We realized the basic component of a switching architecture that receives the ATM cells at about 622 Mbitis. We used commercial devices to solve the high speed transmission problem, in order to realize the switching element with a low cost and low power

L. Licciardi; S. Claretto; M. Fassino; M. Gandini; M. Turolla; V. Vercellone

1992-01-01

100

Experimental procedure influence on total dose CMOS inverters hardness  

Microsoft Academic Search

This issue deals with Co60 irradiation results on three commercial CMOS inverters. About ten years ago, it was proved that this type of “soft oxide” component could undergo rebound effect although only rad-hard NMOS was concerned. The work presented here takes into account dose rate (tested over 5 decades) and bias effects. The results of prediction with linear system theory

E. Mondot; J. P. David

1993-01-01

101

CCD and CMOS sensors  

NASA Astrophysics Data System (ADS)

The charge-coupled device (CCD) has been developed primarily as a compact image sensor for consumer and industrial markets, but is now also the preeminent visible and ultraviolet wavelength image sensor in many fields of scientific research including space-science and both Earth and planetary remote sensing. Today"s scientific or science-grade CCD will strive to maximise pixel count, focal plane coverage, photon detection efficiency over the broadest spectral range and signal dynamic range whilst maintaining the lowest possible readout noise. The relatively recent emergence of complementary metal oxide semiconductor (CMOS) image sensor technology is arguably the most important development in solid-state imaging since the invention of the CCD. CMOS technology enables the integration on a single silicon chip of a large array of photodiode pixels alongside all of the ancillary electronics needed to address the array and digitise the resulting analogue video signal. Compared to the CCD, CMOS promises a more compact, lower mass, lower power and potentially more radiation tolerant camera.

Waltham, Nick

102

An illumination system for CMOS based 3D cameras  

NASA Astrophysics Data System (ADS)

Canesta, Inc. has developed a CMOS based technique that yields 3D information using only one 2D array sensor and is commercializing this 3D camera. The camera is composed of a light source (illumination system) and a CMOS based 2D array camera. The illumination system can generate 4 types of illumination fields of view with IEC eye classification class 1 or class 1M by simply switching diffusers. In this paper, the design of the illumination system is described and the performance results are presented.

Zhao, Peter P.; O'Connor, Patrick

2005-08-01

103

CMOS and BiCMOS VCO — Status and trends  

Microsoft Academic Search

This paper gives a brief overview of voltage controlled oscillator(VCO) based on Si CMOS and SiGeBiCMOS process technologies. The status of designing techniques for high performance VCO is summarized because of its importance for high-speed communication systems and radar sensors. Then, the development tendency of VCO is introduced.

Xiang Li; Guang-Yin Feng; Jing-ye Cai; Zhen-Hai Shao; Lianfu Liu; Xueyong Zhu

2011-01-01

104

CMOS chip planarization by chemical mechanical polishing for a vertically stacked metal MEMS integration  

NASA Astrophysics Data System (ADS)

In this paper we present the planarization process of a CMOS chip for the integration of a microelectromechanical systems (MEMS) metal mirror array. The CMOS chip, which comes from a commercial foundry, has a bumpy passivation layer due to an underlying aluminum interconnect pattern (1.8 µm high), which is used for addressing individual micromirror array elements. To overcome the tendency for tilt error in the CMOS chip planarization, the approach is to sputter a thick layer of silicon nitride at low temperature and to surround the CMOS chip with dummy silicon pieces that define a polishing plane. The dummy pieces are first lapped down to the height of the CMOS chip, and then all pieces are polished. This process produced a chip surface with a root-mean-square flatness error of less than 100 nm, including tilt and curvature errors.

Lee, Hocheol; Miller, Michele H.; Bifano, Thomas G.

2004-01-01

105

Monolithic CMUT-on-CMOS integration for intravascular ultrasound applications.  

PubMed

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter-based volumetric imaging arrays, for which the elements must be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom-designed CMOS receiver electronics from a commercial IC foundry. The CMUT-on-CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low-temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT-to-CMOS interconnection. This CMUT-to-CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire-bonding method. Characterization experiments indicate that the CMUT-on-CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Ex- periments on a 1.6-mm-diameter dual-ring CMUT array with a center frequency of 15 MHz show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging chronic total occlusions located 1 cm from the CMUT array. PMID:23443701

Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F Levent

2011-12-01

106

Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.  

SciTech Connect

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materials integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.

Sumant, A.V.; Auciello, O.; Yuan, H.-C; Ma, Z.; Carpick, R. W.; Mancini, D. C.; Univ. of Wisconsin; Univ. of Pennsylvania

2009-05-01

107

Process integration for submicron CMOS  

NASA Astrophysics Data System (ADS)

Four aspects of submicron CMOS process integration are examined. They are: (1) device and systems goals, (2) unit processes, (3) process interactions, and (4) process modeling and characterization. It is believed that sub-half-micron CMOS technologies offer the potential for realizing electronic systems with a complexity approaching that of the human brain.

Krusius, J. Peter

108

Performance of CMOS differential circuits  

Microsoft Academic Search

Differential CMOS logic family has potential advantages over the standard static CMOS logic family implemented using NAND\\/NOR logic. These circuits tend to be faster and require fewer transistors. In this paper, various static and dynamic circuit techniques from the differential logic family are evaluated using application circuits like adders and multipliers. Circuits with self-timed characteristics are also considered. Evaluations are

Pius Ng; Poras T. Balsara; Don Steiss

1996-01-01

109

Review of CMOS image sensors  

Microsoft Academic Search

The role of CMOS Image Sensors since their birth around the 1960s, has been changing a lot. Unlike the past, current CMOS Image Sensors are becoming competitive with regard to Charged Couple Device (CCD) technology. They offer many advantages with respect to CCD, such as lower power consumption, lower voltage operation, on-chip functionality and lower cost. Nevertheless, they are still

M. Bigas; Enric Cabruja; Josep Forest; Joaquim Salvi

2006-01-01

110

CMOS active pixel image sensor  

Microsoft Academic Search

A new CMOS active pixel image sensor is reported. The sensor uses a 2.0 ?m double-poly, double-metal foundry CMOS process and is realized as a 128×128 array of 40 ?m×40 ?m pixels. The sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications

S. Mendis; S. E. Kemeny; E. R. Fossum

1994-01-01

111

Low-light hyperspectral imager for characterization of biological samples based on an sCMOS image sensor  

NASA Astrophysics Data System (ADS)

The new "scientific CMOS" (sCMOS) sensor technology has been tested for use in hyperspectral imaging. The sCMOS offers extremely low readout noise combined with high resolution and high speed, making it attractive for hyperspectral imaging applications. A commercial HySpex hyperspectral camera has been modified to be used in low light conditions integrating an sCMOS sensor array. Initial tests of fluorescence imaging in challenging light settings have been performed. The imaged objects are layered phantoms labelled with controlled location and concentration of fluorophore. The camera has been compared to a state of the art spectral imager based on CCD technology. The image quality of the sCMOS-based camera suffers from artifacts due to a high density of pixels with excessive noise, attributed to the high operating temperature of the array. Image processing results illustrate some of the benefits and challenges of the new sCMOS technology.

Hernandez-Palacios, J.; Randeberg, L. L.; Haug, I. J.; Baarstad, I.; Løke, T.; Skauli, T.

2011-02-01

112

Design and fabrication of vertically-integrated CMOS image sensors.  

PubMed

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Skorka, Orit; Joseph, Dileepan

2011-04-27

113

SiGe BiCMOS manufacturing platform for mmWave applications  

Microsoft Academic Search

TowerJazz offers high volume manufacturable commercial SiGe BiCMOS technology platforms to address the mmWave market. In this paper, first, the SiGe BiCMOS process technology platforms such as SBC18 and SBC13 are described. These manufacturing platforms integrate 200 GHz fT\\/fMAX SiGe NPN with deep trench isolation into 0.18mum and 0.13mum node CMOS processes along with high density 5.6fF\\/mum2 stacked MIM capacitors,

Arjun Kar-Roy; David Howard; Edward Preisler; Marco Racanelli; Samir Chaudhry; Volker Blaschke

2010-01-01

114

270GHz SiGe BiCMOS manufacturing process platform for mmWave applications  

Microsoft Academic Search

TowerJazz has been offering the high volume commercial SiGe BiCMOS process technology platform, SBC18, for more than a decade. In this paper, we describe the TowerJazz SBC18H3 SiGe BiCMOS process which integrates a production ready 240GHz FT \\/ 270 GHz FMAX SiGe HBT on a 1.8V\\/3.3V dual gate oxide CMOS process in the SBC18 technology platform. The high-speed NPNs in

Arjun Kar-Roy; Edward J. Preisler; George Talor; Zhixin Yan; Roger Booth; Jie Zheng; Samir Chaudhry; David Howard; Marco Racanelli

2011-01-01

115

Survey of noise performances and scaling effects in deep submicrometer CMOS devices from different foundries  

Microsoft Academic Search

Submicrometer CMOS technologies provide well-established solutions to the implementation of low-noise front-end electronics for a wide range of detector applications. Since commercial CMOS processes maintain a steady trend in device scaling, it is essential to monitor the impact of these technological advances on the noise parameters of the devices. In this paper we present the results of an extensive analysis

V. Re; M. Manghisoni; L. Ratti; V. Speziali; G. Traversi

2005-01-01

116

CMOS MAPS with pixel level sparsification and time stamping capabilities for applications at the ILC  

NASA Astrophysics Data System (ADS)

This paper is intended to discuss the features of a novel kind of monolithic active pixel sensors (MAPS) in deep submicron CMOS technology (130 nm minimum feature size) for use in charged particle trackers and vertex detectors. As compared to conventional MAPS with 3-transistor readout scheme, the design approach proposed here, where a deep N-well (DNW) is used as the collecting electrode, lends itself to pixel-level sparsified processing and is expected to provide the ability to manage the large data flow of information anticipated for future, high luminosity colliders. Lately, the applicability of the DNW-MAPS concept to the design of the vertex detector for future high luminosity colliders, like the International Linear Collider (ILC), has been investigated. This paper will discuss the design and performance of a recently submitted DNW monolithic sensor, the SDR0 (Sparsified Digital Readout) chip, including different test structures, where both analog (charge amplification and threshold discrimination) and digital (sparsification, time stamping) functions have been integrated inside the elementary sensor, as large as 25?m×25?m.

Traversi, Gianluca; Manghisoni, Massimo; Ratti, Lodovico; Re, Valerio; Speziali, Valeria

2007-10-01

117

Strained Si CMOS (SS CMOS) technology: opportunities and challenges  

Microsoft Academic Search

Strain-induced enhancement of current drive is a promising way to extend the advancement of CMOS performance. Fabrication of strained Si MOSFET has been demonstrated with key elements of modern day’s CMOS technology. Significant mobility and current drive enhancements were observed. Recent advancements in the SS devices are summarized, and the challenges in device physics\\/design issues as well as in materials\\/process

K. Rim; R. Anderson; D. Boyd; F. Cardone; K. Chan; H. Chen; S. Christansen; J. Chu; K. Jenkins; T. Kanarsky; S. Koester; B. H. Lee; K. Lee; V. Mazzeo; A. Mocuta; D. Mocuta; P. M. Mooney; P. Oldiges; J. Ott; P. Ronsheim; R. Roy; A. Steegen; M. Yang; H. Zhu; M. Ieong; H.-S. P. Wong

2003-01-01

118

How a CMOS Device Works  

NSDL National Science Digital Library

This website includes an animation of a CMOS device and how it works. Objective: Identify the required electrical variables that allow a CMOS device to operate. This simulation is from Module 001 of the Process & Equipment I Cluster of the MATEC Module Library (MML). To view other clusters or for more information about the MML visit http://matec.org/ps/library3/process_I.shtmlKey

2012-11-02

119

Future of Nano CMOS Technology  

Microsoft Academic Search

CMOS technology has been developed into the sub-100 nm range. It is expected that the nano-CMOS technology will governed the IC manufacturing for at least another couple of decades. Though there are many challenges ahead, further down-sizing the device to a few nanometers is still on the schedule of International Technology Roadmap for Semiconductors (ITRS). Several technological options for manufacturing

Hiroshi Iwai

2007-01-01

120

Reconfigurable RF CMOS Circuit for Cognitive Radio  

NASA Astrophysics Data System (ADS)

Cognitive radio and/or SDR (Software Defined Radio) inherently requires multi-band and multi standard wireless circuit. The circuit is implemented based on Si CMOS technology. In this article, the recent progress of Si RF CMOS is described and the reconfigurable RF CMOS circuit which was proposed by the authors is introduced. At the present and in the future, several kind of Si CMOS technology can be used for RF CMOS circuit implementation. The realistic RF CMOS circuit implementation toward cognitive and/or SDR is discussed.

Masu, Kazuya; Okada, Kenichi

121

Integration of top-emitting organic light emitting diodes on CMOS substrates  

NASA Astrophysics Data System (ADS)

The integration of top-emitting OLEDs on CMOS substrates is of interest for a variety of applications. Whereas OLEDbased microdisplays have already been commercialized, OLEDs could also be used to realize sensor applications, optocouplers, etc. Red top-emitting OLED structures were deposited on CMOS substrates. The OLED technology includes phosphorescent emitters and doped transport layers. This approach results in high efficiencies and low operating voltage. The CMOS top metal is crucial for this type of devices since this layer is the interface between CMOS and OLED technology. In a first step, OLED process development was carried out on passive substrates without transistor circuit but CMOS compatible interface. Luminance values of 100cd/m2 and 1000cd/m2 are reached at 2.45V and 3.1V, respectively. Current efficiency at these luminance values is 14.2 cd/A and 13.4 cd/A, respectively, with a peak wavelength of 627nm. This OLED stack was then successfully prepared on full-CMOS-substrates. luminance values is 14.2 cd/A and 13.4 cd/A, respectively, with a peak wavelength of 627nm. This OLED stack was then successfully prepared on full-CMOS-substrates.

Toerker, M.; Grillberger, Ch.; Kreye, D.; Vogel, U.; Amelung, J.

2008-05-01

122

Large Format CMOS-based Detectors for Diffraction Studies  

NASA Astrophysics Data System (ADS)

Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 ?m × 100 ?m are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 ?m × 100 ?m pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at reasonable cost.

Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

2013-03-01

123

Proof of principle study of the use of a CMOS active pixel sensor for proton radiography  

SciTech Connect

Purpose: Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). Methods: A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissue contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Results: Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Conclusion: Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The development and use of CMOS in proton radiography could allow in vivo proton range checks, patient setup QA, and real-time tumor tracking.

Seco, Joao; Depauw, Nicolas [Francis H. Burr Proton Therapy Center, Department of Radiation Oncology, Massachusetts General Hospital (MGH), Boston, Massachusetts 02114 (United States)

2011-02-15

124

A low-voltage CMOS complementary active pixel sensor (CAPS) fabricated using a 0.25 ?m CMOS technology  

Microsoft Academic Search

A low voltage rail-to-rail CMOS complementary active pixel sensor (CAPS) architecture is presented. Compared with a conventional active pixel sensor (APS), the CAPS surpasses the bottleneck of limited output swing at ultra-low supply voltage operation imposed by highly scaled technology, making it more scalable compared with other reported architectures. The CAPS has been implemented with a commercially available 0.25 ?m

Chen Xu; Wing-Hung Ki; Mansun Chan

2002-01-01

125

Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators  

PubMed Central

This work presents a thermoelectric micro generator fabricated by the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 ?V at the temperature difference of 1 K.

Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

2010-01-01

126

Design and fabrication of a CMOS MEMS logic gate  

NASA Astrophysics Data System (ADS)

This study aims to develop a novel CMOS-MEMS logic gate via commercially available CMOS process (TSMC, 2P4M®). Compared to existing CMOS MEMS designs, which uses foundry processes, the proposed design imposes several new challenges including: carrying two voltage levels on a non-warping suspended plate, metal-to- metal contact, and etc. Different combinations of oxide-metal films and post-CMOS process are investigated to achieve a non-warping suspended structure layer. And different wet etchants are investigated to remove sacrificial layers without attacking structure layers and features. In a prototype design, the selected structure layer is metal-3 and oxide film; the device is released using AD-10 and titanium etchant; the device is 250 ?m long, 100 ?m wide, and 1.5 ?m gap. The experimental results show that the suspended plate slightly curls down 0.485 ?m. This device can be actuated by 10/0 V with a moving distance 50nm. The resonant frequency is measured at 36 kHz. Due to the damage of the tungsten plugs, the logic function can only be verified by its mechanical movements instead of electrical readouts for now.

Tsai, Chun-Yin; Chen, Tsung-Lin; Liao, Hsin-Hao; Lin, Chen-Fu; Juang, Ying-Zong

2011-02-01

127

The Making of the CMOS Microchip  

NSDL National Science Digital Library

The animation of the making of the CMOS Microchip.Objective: Determine the process steps needed to complete a CMOS device.This simulation is from Module 002 of the Process & Equipment I Cluster of the MATEC Module Library (MML).

2010-05-05

128

Integrated CMOS amplifier for ENG signal recording  

Microsoft Academic Search

The development and in vivo test of a fully integrated differential CMOS amplifier, implemented with standard 0.7-?m CMOS technology (one poly, two metals, self aligned twin-well CMOS process) intended to record extracellular neural signals is described. In order to minimize the flicker noise generated by the CMOS circuitry, a chopper technique has been chosen. The fabricated amplifier has a gain

A. Uranga; X. Navarro; N. Barniol

2004-01-01

129

Materials and structures for future nano CMOS  

Microsoft Academic Search

Recently, CMOS downsizing has been accelerated very aggressively in both production and research levels, and even beautiful transistor operation of several nm gate length CMOS devices were reported in conferences. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits. It is still questionable if we can successfully introduce deep sub-10 nm CMOS LSIs into

Hiroshi Iwai

2011-01-01

130

CMOS Circuit Speed and Buffer Optimization  

Microsoft Academic Search

An improved timing model for CMOS combinational logic is presented. The model is based on an analytical solution for the CMOS inverter output response to an input ramp. This model yields a better understanding of the switching behavior of the CMOS inverter than the step-response model by considering the slope of the input waveform. Essentially, the propagation delay is shown

Nils Hedenstierna; Kjell O. Jeppson

1987-01-01

131

Microimage processing system based on CMOS sensor  

Microsoft Academic Search

A CMOS IS (image sensor) has been widely applied in the multimedia field due to its unique features. One application of the CMOS IS is the microimage processing field is presented. An electronic eyepiece, mainly incorporating optical lens and a CMOS IS, is developed to digitize an optical image, process the digital signals and transmit them to a processor (i.e.

Xiangdong Xu; Feng Li; Chao Zeng; Xianbing Zheng

2002-01-01

132

A CMOS floating point multiplier  

NASA Astrophysics Data System (ADS)

This paper describes a 32-bit CMOS floating point multiplier. The chip can perform 32-bit floating point multiplication (based on the proposed IEEE Standard format) and 24-bit fixed point multiplication (two's complement format) in less than 78.7 and 71.1 ns, respectively, and the typical power dissipation is 195 mW at 10 million operations per second. High-speed multiplication techniques - a modified Booth's allgorithm, a carry save adder scheme, a high-speed CMOS full adder, and a modified carry select adder - are used to achieve the above high performance. The chip is designed for compatibility with 16-bit microcomputer systems, and is fabricated in 2 micron n-well CMOS technology; it contains about 23000 transistors of 5.75 x 5.67 sq mm in size.

Uya, M.; Kaneko, K.; Yasui, J.

1984-10-01

133

MonoColor CMOS sensor  

NASA Astrophysics Data System (ADS)

A new breed of CMOS color sensor called MonoColor sensor is developed for a barcode reading application in AIDC industry. The RGBW color filter array (CFA) in a MonoColor sensor is arranged in a 8 x 8 pixels CFA with only 4 pixels of them are color (RGB) pixels and the rest of 60 pixels are transparent or monochrome. Since the majority of pixels are monochrome, MonoColor sensor maintains 98% barcode decode performance compared with a pure monochrome CMOS sensor. With the help of monochrome and color pixel fusion technique, the resulting color pictures have similar color quality in terms of Color Semantic Error (CSE) compared with a Bayer pattern (RGB) CMOS color camera. Since monochrome pixels are more sensitive than color pixels, a MonoColor sensor produces in general about 2X brighter color picture and higher luminance pixel resolution.

Wang, Ynjiun P.

2009-02-01

134

Mixed-signal 0.18mum CMOS and SiGe BiCMOS foundry technologies for ROIC applications  

Microsoft Academic Search

Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18mum CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V\\/3.3V and CA18HA dual gate oxide 1.8V\\/5V RF\\/mixed signal processes, consisting of

Arjun Kar-Roy; David Howard; Marco Racanelli; Mike Scott; Paul Hurwitz; Robert Zwingman; Samir Chaudhry; Scott Jordan

2010-01-01

135

CMOS Integrated Carbon Nanotube Sensor  

SciTech Connect

Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A. [Grupo MEMS, Comision Nacional de Energia Atomica, Buenos Aires (Argentina); Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S. [Dpto. de Ing. Electrica y de Computadoras, Universidad Nacional del Sur, Bahia Blanca (Argentina); Buffa, F. A. [INTEMA Facultad de Ingenieria, Universidad Nacional de Mar del Plata, Mar del Plata (Argentina)

2009-05-23

136

A Brief Discussion of Radiation Hardening of CMOS Microelectronics  

SciTech Connect

Commercial microchips work well in their intended environments. However, generic microchips will not fimction correctly if exposed to sufficient amounts of ionizing radiation, the kind that satellites encounter in outer space. Modern CMOS circuits must overcome three specific concerns from ionizing radiation: total-dose, single-event, and dose-rate effects. Minority-carrier devices such as bipolar transistors, optical receivers, and solar cells must also deal with recombination-generation centers caused by displacement damage, which are not major concerns for majority-carrier CMOS devices. There are ways to make the chips themselves more resistant to radiation. This extra protection, called radiation hardening, has been called both a science and an art. Radiation hardening requires both changing the designs of the chips and altering the ways that the chips are manufactured.

Myers, D.R.

1998-12-18

137

A CMOS enhanced solid-state nanopore based single molecule detection platform.  

PubMed

Solid-state nanopores have emerged as a single molecule label-free electronic detection platform. Existing transimpedance stages used to measure ionic current nanopores suffer from dynamic range limitations resulting from steady-state baseline currents. We propose a digitally-assisted baseline cancellation CMOS platform that circumvents this issue. Since baseline cancellation is a form of auto-zeroing, the 1/f noise of the system is also reduced. Our proposed design can tolerate a steady state baseline current of 10µA and has a usable bandwidth of 750kHz. Quantitative DNA translocation experiments on 5kbp DNA was performed using a 5nm silicon nitride pore using both the CMOS platform and a commercial system. Comparison of event-count histograms show that the CMOS platform clearly outperforms the commercial system, allowing for unambiguous interpretation of the data. PMID:24109650

Chen, Chinhsuan; Yemenicioglu, Sukru; Uddin, Ashfaque; Corgliano, Ellie; Theogarajan, Luke

2013-07-01

138

Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units  

SciTech Connect

One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing. In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.

Smith, J.H.; Ellis, J.R.; Montague, S.; Allen, J.J.

1997-03-01

139

A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.  

PubMed

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 ?m CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 ?m CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-08-11

140

A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass  

PubMed Central

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 ?m CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 ?m CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

141

A high density CMOS process  

Microsoft Academic Search

A 3? CMOS process yielding circuit densities comparable to 1.5? design rules will be reported. The procedure was used to construct an 8b microcomputer for telecom use: clock frequency was 20MHz at 9V; 50k transistors were placed in an area of 31mm2.

R. Luscher; J. De Zaldivar

1985-01-01

142

Smart CMOS image sensor arrays  

Microsoft Academic Search

In this paper, we present several smart image sensor arrays intended for various applications. We discuss the realization of image sensors in CMOS technology and show some examples of one-dimensional (1-D) and two-dimensional (2-D) smart image arrays

Michael Schanz; Werner Brockherde; Ralf Hauschild; Bedrich J. Hosticka; Markus Schwarz

1997-01-01

143

MonoColor CMOS sensor  

Microsoft Academic Search

A new breed of CMOS color sensor called MonoColor sensor is developed for a barcode reading application in AIDC industry. The RGBW color filter array (CFA) in a MonoColor sensor is arranged in a 8 x 8 pixels CFA with only 4 pixels of them are color (RGB) pixels and the rest of 60 pixels are transparent or monochrome. Since

Ynjiun P. Wang

2009-01-01

144

CMOS voltage to current transducers  

Microsoft Academic Search

This paper explores in detail the possible approaches to. the design of voltage- or current-controllable linear transconductance elements needed for the design of continuous-time CMOS active filters. The focus of the paper is on circuit configurations, techniques of achieving linearity, and temperature compensation using the controlling variable. Circuit techniques for obtaining small transductance values are outlined. Simulation results are presented.

R. Torrance; T. Viswanathan; J. Hanson

1985-01-01

145

Low Power CMOS Digital Design  

Microsoft Academic Search

: Motivated by emerging battery operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit and technology optimizations. An architectural based scaling strategy is presented which

Anantha P. Chandrakasan; Samuel Sheng; Robert W. Brodersen

1995-01-01

146

Radiation characterization of the austriamicrosystems 0.35 µm CMOS technology  

Microsoft Academic Search

The design of mixed-signal ASICs for space requires a detailed knowledge of the behaviour of the technology to be used in an environment imposing radiation levels and temperatures beyond those found in standard applications. Commercial foundries providing standard CMOS technologies do not usually have or make available data on the behaviour of their devices under those conditions. Instituto de Microelectrónica

J. Ramos-Martos; A. Arias-Drake; A. Ragel-Morales; J. Ceballos-Caceres; J. M. Mora-Gutierrez; B. Pinero-Garcia; M. Munoz-Diaz; M. A. Lagos-Florido; S. Espejo-Meana

2011-01-01

147

Process-dependent thin-film thermal conductivities for thermal CMOS MEMS  

Microsoft Academic Search

The thermal conductivities ? of the dielectric and conducting thin films of three commercial CMOS processes were determined in the temperature range from 120 to 400 K. The measurements were performed using micromachined heatable test structures containing the layers to be characterized. The ? values of thermally grown silicon oxides are reduced from bulk fused silica by roughly 20%. The

Martin von Arx; Oliver Paul; Henry Baltes

2000-01-01

148

Using CMOS image sensors to detect photons  

NASA Astrophysics Data System (ADS)

A research is carried out on the characteristics of CMOS (Complementary Metal-Oxide Semiconductor) image sensors. A CMOS image sensor is used to probe the fluorescence intensity of atoms or absorbed photons in order to measure the shape and atomicity density of Rb (Rubidium) cold-atom-cloud. A series of RGB data of images is obtained and the spectrum response curve of CMOS image sensor is deduced. After filtering out the noise of the pixel signals of CMOS image sensor, the number of photons received by every pixel of the CMOS image sensor is obtained. Compared with CCD camera, the CMOS image sensor has some advantages in measuring the properties of cold-atom-cloud,such as quick response, large sensory area, low cost, and so on.

Xu, Chenzhi; Tong, Xiaobo; Zhou, Xiang; Zheng, Xiaodong; Xu, Yunfei

2010-04-01

149

Digital-Centric RF CMOS Technologies  

NASA Astrophysics Data System (ADS)

Analog-centric RFCMOS technology has played an important role in motivating the change of technology from conventional discrete device technology or bipolar IC technology to CMOS technology. However it introduces many problems such as poor performance, susceptibility to PVT fluctuation, and cost increase with technology scaling. The most important advantage of CMOS technology compared with legacy RF technology is that CMOS can use more high performance digital circuits for very low cost. In fact, analog-centric RF-CMOS technology has failed the FM/AM tuner business and the digital-centric CMOS technology is becoming attractive for many users. It has many advantages; such as high performance, no external calibration points, high yield, and low cost. From the above facts, digital-centric CMOS technology which utilizes the advantages of digital technology must be the right path for future RF technology. Further investment in this technology is necessary for the advancement of RF technology.

Matsuzawa, Akira

150

Recent Developments of CMOS Image Sensors  

NASA Astrophysics Data System (ADS)

Recent developments in CMOS image sensors are reviewed. High-speed, wide-dynamic-range, and range or 3D cameras are typical examples of recent success of CMOS image sensors. The fastest CMOS image with 100 M pixels reaches 2000 frames/s. Many techniques for achieving wide dynamic range have been proposed. CMOS image sensors employing wide dynamic range pixels with logarithmic response are applied for imaging of arc-welding process. CMOS sensors for real-time range imaging based on light stripe scanning, TOF (time of flight), and stereoscopic measurement methods are developed. The image quality of CMOS image sensor is being improved by the process technology and signal processing techniques.

Kawahito, Shoji

151

Using CMOS image sensors to detect photons  

Microsoft Academic Search

A research is carried out on the characteristics of CMOS (Complementary Metal-Oxide Semiconductor) image sensors. A CMOS image sensor is used to probe the fluorescence intensity of atoms or absorbed photons in order to measure the shape and atomicity density of Rb (Rubidium) cold-atom-cloud. A series of RGB data of images is obtained and the spectrum response curve of CMOS

Chenzhi Xu; Xiaobo Tong; Xiang Zhou; Xiaodong Zheng; Yunfei Xu

2010-01-01

152

1\\/f noise in advanced CMOS transistors  

Microsoft Academic Search

Complementary metal-oxide-semiconductor (CMOS) technology is dominant in the microelectronics industry for a wide range of applications, including analog, digital, RF, and sensor systems. The advantages of silicon CMOS technology compared to bipolar technology as well as transistors in other semiconductors is well-established. CMOS technology scaling has been a main drive for continuous progress in the silicon based semiconductor industry over

Yael Nemirovsky; Dan Corcos; Igor Brouk; Amikam Nemirovsky; Samir Chaudhry

2011-01-01

153

High speed CMOS technology for ASIC application  

Microsoft Academic Search

In order to realize high speed and high density CMOS logic LSI's, an advanced two-level metal CMOS technology, having minimum feature size of 1.0 µm, has been developed. The technology has proven very high speed feasibility of CMOS logic arrays of less than half-nsec delay times, in addition to high reliability of 5V operation. BCD3structure is employed for 1.0 µm

H. Ooka; S. Murakami; M. Murayama; K. Yoshida; S. Takao; O. Kudoh

1986-01-01

154

CMOS Image Sensors for High Speed Applications.  

PubMed

Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4?5 ?m) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps). PMID:22389609

El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

2009-01-13

155

CMOS Image Sensors for High Speed Applications  

PubMed Central

Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4?5 ?m) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

El-Desouki, Munir; Deen, M. Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

2009-01-01

156

SPICE macromodel and CMOS emulator for memristors.  

PubMed

In this paper, a new SPICE macromodel and CMOS emulator for memristors are proposed and verified to fit to the memristor's model equation very well in the entire range of memristor's resistance from the RESET state to the SET state. Compared with the memristor's model equation, average percentage errors in the new SPICE macromodel and in the 4-bit CMOS emulator are less than 0.5% and 0.9%, respectively. In addition, the CMOS emulator for memristors which can be implemented by a CMOS circuit will be very useful to design and verify various peripheral circuits for memristor applications particularly when the memristor fabrication process is not ready. PMID:22629985

Jung, Chul-Moon; Jo, Kwan-Hee; Min, Kyeong-Sik

2012-02-01

157

A CMOS Tunable Transimpedance Amplifier  

Microsoft Academic Search

A tunable transimpedance amplifier (TIA) is presented in this letter. By incorporating a mechanism for gain and bandwidth tuning, the TIA can be adjusted to achieve optimum circuit performance with a lowest bit-error-rate (BER) for high-speed applications. The proposed circuit is implemented in a 0.18-mum CMOS process. Consuming a dc power of 34mW from a 2.0-V supply voltage, the fabricated

Huei-Yan Hwang; Jun-Chau Chien; Tai-Yuan Chen; Liang-Hung Lu

2006-01-01

158

Topics on CMOS Image Sensors  

Microsoft Academic Search

Abstract Today there exist several applications where a real visible scene needs to be sampled to electrical signals, e.g., video cameras, digital still cameras, and machine vision systems. Since the 1970’s charge-coupled device (CCD) sensors have primarily been used for this task, but during the last decade CMOS image sensors have become,more and more popular. The demand,for image sensors has

Leif Lindgren

2005-01-01

159

Novel integrated CMOS sensor circuits  

Microsoft Academic Search

Three novel integrated CMOS active pixel sensor circuits for vertex detector applications have been designed with the goal of increased signal-to-noise ratio and speed. First, a large-area native epitaxial silicon photogate sensor was designed to increase the charge collected per hit pixel and to reduce charge diffusion to neighboring pixels. High charge to voltage conversion is maintained by subsequent charge

Stuart Kleinfelder; Fred Bieser; Yandong Chen; Robin Gareus; Howard S. Matis; Markus Oldenburg; Fabrice Retiere; H. G. Ritter; Howard H. Wieman; Eugene Yamamoto

2004-01-01

160

High Resolution CMOS Current Comparators  

Microsoft Academic Search

A 2¿m CMOS current comparator prototype is presented with an input current comparison range of 140dB and virtual zero offset(?10pA). The circuit uses capacitive sensing for high resolution and nonlinear feedback to achieve small input voltage variations in the complete input current range. Operation speed for low current is abot two orders of magnitude larger than for conventional circuits. Simplified

R. Dominguez-Castro; A. Rodriguez-Vazquez; F. Medeiro; J. L. Huertas

1992-01-01

161

CMOS wavelet compression imager architecture  

Microsoft Academic Search

The CMOS imager architecture implements ??-modulated Haar wavelet image compression on the focal plane in real time. The active pixel array is integrated with a bank of column-parallel first-order incremental over-sampling analog-to-digital converters (ADCs). Each ADC performs column-wise distributed focal-plane sampling and concurrent signed weighted average quantization, realizing a one-dimensional spatial Haar wavelet transform. A digital delay and adder loop

Ashkan Olyaei; R. Genov

2005-01-01

162

Scaling fully depleted SOI CMOS  

Microsoft Academic Search

Quasi-two-dimensional (2-D) device analyses, 2-D numerical device simulations, and circuit simulations of nanoscale conventional, single-gate fully depleted (FD) silicon-on-insulator (SOI) CMOS are done to examine the scalability and performance potential of the technology. The quasi-2-D analyses, which can apply to double-gate devices as well, also provide a simple expression to estimate the effective channel length (Leff) of FD\\/SOI MOSFETs. The

Vishal P. Trivedi; Jerry G. Fossum

2003-01-01

163

5GHz CMOS wireless LANs  

Microsoft Academic Search

This paper first provides an overview of some recently ratified wireless local-area network (WLAN) standards before describing an illustrative 5-GHz WLAN receiver implementation. The receiver, built in a standard 0.25-?m CMOS logic technology, exploits several recent developments, including lateral-flux capacitors, accumulation-mode varactors, injection-locked frequency dividers, and an image-reject low-noise amplifier. The receiver readily complies with the performance requirements of both

T. H. Lee; H. Samavati; H. R. Rategh

2002-01-01

164

Enhanced total ionizing dose tolerance of bulk CMOS transistors fabricated for ultra-low power applications  

SciTech Connect

The first radiation tests of transistors fabricated in a commercial bulk CMOS process designed for ultra-low power applications in space are presented and analyzed. The predominant failure mode of bulk CMOS, i.e., radiation-induced parasitic leakage currents in n-channel transistors, is greatly suppressed by the use of low threshold voltage devices and by the application of backbias used to optimize their performance. With 2 volts of backbias applied, the transistors tested here show no degradation up to a dose of 200 krad(Si).

Xapsos, M.A.; Summers, G.P.; Jackson, E.M.

1999-12-01

165

Compatibility of Submicron Silicon CMOS Circuits with Gallium Arsenide-On Heteroepitaxy.  

NASA Astrophysics Data System (ADS)

Advanced packaging and high density interconnections are emerging technologies as silicon MOS device dimensions scale down to minimum physical limits. Multi-chip Modules and Wafer Scale Integration improve packing density, and provide solutions to board area issues beyond the capabilities of even the most densely packed surface mount technologies. Such technologies could confront increasingly complex interconnection constraints, and might provide opportunities for the insertion of high performance optical interconnections into future microelectronic systems. However, successful integration of optics with microelectronic system technologies requires a careful evaluation of the practical issues confronting monolithic co-integration of GaAs optoelectronics with high performance silicon CMOS technologies. This work presents a systematic evaluation of degradation in the performance and characteristics of submicron silicon CMOS devices, induced by heteroepitaxial growth of gallium arsenide. An aggressive yet stable, commercial 0.9 mu m AT&T Twin-Tub V silicon CMOS fabrication process is used to study the compatibility issues.

Nariman, Hormuzdiar E.

1994-01-01

166

Novel fully CMOS-compatible vacuum sensor  

Microsoft Academic Search

We present a new CMOS-compatible pressure sensor operating in the range of 100–106 Pa. The sensor is fabricated in standard CMOS technology, followed by simple postprocessing consisting of photolithography and a sacrificial metal etch. No anisotropic etching of silicon is required.

Oliver Paul; Henry Baltes

1995-01-01

167

One-M bit CMOS Dynamic RAM.  

National Technical Information Service (NTIS)

Described herein is a 1-M words x 1-bit CMOS dynamic RAM fabricated with an advanced n-well CMOS technology. More than 2.2 millions of element devices are integrated on a 62.5-sq. mm. silicon chip employing an n-channel memory cell of triple-layer polysil...

S. Saito S. Fujii Y. Matsumoto

1985-01-01

168

CMOS–MEMS Lateral Electrothermal Actuators  

Microsoft Academic Search

In this paper, a type of lateral electrothermal (ET) actuator fabricated with post-CMOS micromachining is presented. The actuator is a beam with a multimorph structure, composed of CMOS dielectric and metal interconnect. Following structural release, the actuators demonstrate self-assembly under the moments arising from residual stress. Actuation is achieved through the imbalanced thermal expansion of internal interconnect members, whose relative

Peter J. Gilgunn; Jingwei Liu; Niladri Sarkar; Gary K. Fedder

2008-01-01

169

Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics  

NASA Astrophysics Data System (ADS)

Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm2 with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensors are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.

Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka; Pithawa, C. K.

2011-10-01

170

Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics  

SciTech Connect

Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm{sup 2} with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensors are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.

Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka; Pithawa, C. K. [Centre for Microelectronics, Prabhadevi, Mumbai-400028 (India)

2011-10-20

171

Maintaining the benefits of CMOS scaling when scaling bogs down  

Microsoft Academic Search

A survey of industry trends from the last two decades of scaling for CMOS logic is examined in an attempt to extrapolate practical directions for CMOS technology as lithography progresses toward the point at which CMOS is limited by the size of the silicon atom itself. Some possible directions for various specialized applications in CMOS logic are explored, and it

Edward J. Nowak

2002-01-01

172

CMOS image sensors-recent advances and device scaling considerations  

Microsoft Academic Search

This paper reviews the industry trend and the recent advances in CMOS image sensor technology, covering advances in technology, devices, pixel architecture, as well as on-chip circuit integration. Compatibility with “standard” CMOS technology is an important consideration for CMOS image sensors. We therefore explore the question: “will the image sensing performance of CMOS imagers get better or get worse as

Hon-Sum Philip Wong

1997-01-01

173

Design of high speed camera based on CMOS technology  

Microsoft Academic Search

The capacity of a high speed camera in taking high speed images has been evaluated using CMOS image sensors. There are 2 types of image sensors, namely, CCD and CMOS sensors. CMOS sensor consumes less power than CCD sensor and can take images more rapidly. High speed camera with built-in CMOS sensor is widely used in vehicle crash tests and

Sei-Hun Park; Jun-Sick An; Tae-Seok Oh; Il-Hwan Kim

2007-01-01

174

CMOS Imaging Detectors as X-ray Detectors for Synchrotron Radiation Experiments  

SciTech Connect

CMOS imagers are matrix-addressed photodiode arrays, which have been utilized in devices such as commercially available digital cameras. The pixel size of CMOS imagers is usually larger than that of CCD and smaller than that of TFT, giving them a unique position. Although CMOS x-ray imaging devices have already become commercially available, they have not been used as an x-ray area detector in synchrotron radiation experiments. We tested performance of a CMOS detector from Rad-icon (Shad-o-Box1024) in medical imaging, small-angle scattering, and protein crystallography experiments. It has pixels of 0.048 mm square, read-out time of 0.45 sec, 12-bit ADC, and requires a frame grabber for image acquisition. The detection area is 5-cm square. It uses a Kodak Min-R scintillator screen as a phosphor. The sensitivity to x-rays with an energy less than 15 keV was low because of the thick window materials. Since the readout noise is high, the dynamic range is limited to 2000. The biggest advantages of this detector are cost-effectiveness (about 10,000 US dollars) and compactness (thickness < 3 cm, weight < 2 kg)

Yagi, Naoto; Uesugi, Kentaro; Inoue, Katsuaki [SPring-8/JASRI, Mikazuki, Sayo, Hyogo, 679-5198 (Japan); Yamamoto, Masaki [SPring-8/RIKEN, Mikazuki, Sayo, Hyogo, 679-5198 (Japan)

2004-05-12

175

A 32 x 32 capacitive micromachined ultrasonic transducer array manufactured in standard CMOS.  

PubMed

As ultrasound imagers become increasingly portable and lower cost, breakthroughs in transducer technology will be needed to provide high-resolution, real-time 3-D imaging while maintaining the affordability needed for portable systems. This paper presents a 32 x 32 ultrasound array prototype, manufactured using a CMUT-in-CMOS approach whereby ultrasonic transducer elements and readout circuits are integrated on a single chip using a standard integrated circuit manufacturing process in a commercial CMOS foundry. Only blanket wet-etch and sealing steps are added to complete the MEMS devices after the CMOS process. This process typically yields better than 99% working elements per array, with less than ±1.5 dB variation in receive sensitivity among the 1024 individually addressable elements. The CMUT pulseecho frequency response is typically centered at 2.1 MHz with a -6 dB fractional bandwidth of 60%, and elements are arranged on a 250 ?m hexagonal grid (less than half-wavelength pitch). Multiplexers and CMOS buffers within the array are used to make on-chip routing manageable, reduce the number of physical output leads, and drive the transducer cable. The array has been interfaced to a commercial imager as well as a set of custom transmit and receive electronics, and volumetric images of nylon fishing line targets have been produced. PMID:22828847

Lemmerhirt, David F; Cheng, Xiaoyang; White, Robert; Rich, Collin A; Zhang, Man; Fowlkes, J Brian; Kripfgans, Oliver D

2012-07-01

176

Beam-test results of 4k pixel CMOS MAPS and high resistivity striplet detectors equipped with digital sparsified readout in the Slim5 low mass silicon demonstrator  

NASA Astrophysics Data System (ADS)

The results obtained by the Slim5 collaboration on a low material budget tracking silicon demonstrator put on a 12 GeV/c proton test beam at CERN are reported. Inside a reference telescope, two different and innovative detectors were placed for careful tests. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130 nm CMOS Technology, square pixels 50?m wide, thinned down to 100?m and equipped with a digital sparsified readout running up to 50 MHz. The other was a high resistivity double sided silicon detector, 200?m thick, with short strips with 50?m pitch at 45? angle to the detector's edge. The detectors were equipped with dedicated fast readout architectures performing on-chip data sparsification and providing the timing information for the hits. The criteria followed in the design of the pixel sensor and of the pixel readout architecture will be reviewed. Preliminary measurements of the pixel charge collection, track detection efficiencies and resolutions of pixel and strip sensors are discussed. The data driven architecture of the readout chips has been fully exploited in the test beam by a data acquisition system able to collect on electronic board up to 2.5 Million events per second before triggering. By using a dedicated Associative Memory board, we were able to perform a level 1 trigger system, with minimal latency, identifying cleanly tracks traversing the detectors. System architecture and main performances are shown.

Villa, M.; Bruschi, M.; di Sipio, R.; Fabbri, L.; Giacobbe, B.; Gabrielli, A.; Giorgi, F.; Pellegrini, G.; Sbarra, C.; Semprini, N.; Spighi, R.; Valentinetti, S.; Zoccoli, A.; Avanzini, C.; Batignani, G.; Bettarini, S.; Bosi, F.; Calderini, G.; Ceccanti, M.; Cenci, R.; Cervelli, A.; Crescioli, F.; Dell'Orso, M.; Forti, F.; Giannetti, P.; Giorgi, M. A.; Lusiani, A.; Gregucci, S.; Mammini, P.; Marchiori, G.; Massa, M.; Morsani, F.; Neri, N.; Paoloni, E.; Piendibene, M.; Profeti, A.; Rizzo, G.; Sartori, L.; Walsh, J.; Yurtsev, E.; Manghisoni, M.; Re, V.; Traversi, G.; Andreoli, C.; Gaioni, L.; Pozzati, E.; Ratti, L.; Speziali, V.; Gamba, D.; Giraudo, G.; Mereu, P.; Dalla Betta, G. F.; Soncini, G.; Fontana, G.; Bomben, M.; Bosisio, L.; Cristaudo, P.; Giacomini, G.; Jugovaz, D.; Lanceri, L.; Rashevskaya, I.; Vitale, L.; Venier, G.

2010-05-01

177

Back-thinned CMOS sensor optimization  

NASA Astrophysics Data System (ADS)

Back-thinning of a CCD image sensor is a very well established process for achieving high quantum efficiency and the majority of high-specification space and science applications have used such back-thinned devices for many years. CMOS sensors offer advantages over CCDs for a number of these applications and, in principle, it should be possible to back-thin CMOS devices and obtain the same performance as the CCD. This has now been demonstrated by e2v and results from two recent programmes to back-thin CMOS sensors show excellent quantum efficiency values.

Jerram, Paul; Burt, David; Guyatt, Neil; Hibon, Vincent; Vaillant, Joel; Henrion, Yann

2010-02-01

178

Benchmarking of current generation overlay systems at the 130-nm technology node  

Microsoft Academic Search

The Overlay Metrology Advisory Group (OMAG) is a group comprised of technical experts in the field of optical metrology from International SEMATECH Member Companies and the National Institute of Standards and Technology (NIST). This council created a specification for overlay metrology benchmarking which indicates the critical parameters to be addressed in order to comply with the International Technology Roadmap for

Beth Russo; Michael Bishop

2003-01-01

179

Scatterometry measurement method for gate CD control of sub-130nm technology  

NASA Astrophysics Data System (ADS)

Recently, the scatterometry is becoming more and more popular as a inline metrology tool for lithography process control as well as etching process control because of the advantage of fast measurement with high accuracy. Especially, at the gate patterning that fabricates transistors, the scatterometry can be very powerful because it gives massive volume of CD (Critical Dimension) measurement data and gate poly profile, simultaneously. Those results could help to understand and forecast the performance of transistors. In order to achieve accurate and consistent measurement results by scatterometry, the setup of stable model and library is very crucial since it has nature of indirect measurement. For example, as defining of substrate conditions, modeling range of parameters, target values and type of models, scatterometry (in this paper, we call as OCD; Optical CD) gives different results even if we use same data basis. In this paper we have shown the best practice how to optimize variables of scatterometry to get accurate and stable results. We used the OCD(Optic CD: Accent CDS200) angular scatterometry system which can rotate HeNe laser light source from -47 to +47 degree. In order to investigate the substrate dependency, various silicon wafer substrates having periodic patterned with different materials such as photoresist, BARC, poly silicon, and thermal oxide film has been used. Finally, we observed OCD has the excellent capability for inline process controllability.

Jang, Jeongyeol; Kwak, Sungho; Lee, Karl; Kim, Keeho; Park, Heongsu; Youn, James; Sohn, Lucas

2005-05-01

180

Impact of Spacecraft Shielding on Direct Ionization Soft Error Rates for Sub130 nm Technologies  

Microsoft Academic Search

We use ray tracing software to model various levels of spacecraft shielding complexity and energy deposition pulse height analysis to study how it affects the direct ionization soft error rate of microelectronic components in space. The analysis incorporates the galactic cosmic ray background, trapped proton, and solar heavy ion environments as well as the October 1989 and July 2000 solar

Jonathan A. Pellish; Michael A. Xapsos; Craig A. Stauffer; Thomas M. Jordan; Anthony B. Sanders; Raymond L. Ladbury; Timothy R. Oldham; Paul W. Marshall; David F. Heidel; Kenneth P. Rodbell

2010-01-01

181

Integrated CMOS amplifier for ENG signal recording.  

PubMed

The development and in vivo test of a fully integrated differential CMOS amplifier, implemented with standard 0.7-microm CMOS technology (one poly, two metals, self aligned twin-well CMOS process) intended to record extracellular neural signals is described. In order to minimize the flicker noise generated by the CMOS circuitry, a chopper technique has been chosen. The fabricated amplifier has a gain of 74 dB, a bandwidth of 3 kHz, an input noise of 6.6 nV/(Hz)0.5, a power dissipation of 1.3 mW, and the active area is 2.7 mm2. An ac coupling has been used to adapt the electrode to the amplifier circuitry for the in vivo testing. Compound muscle action potentials, motor unit action potentials, and compound nerve action potentials have been recorded in acute experiments with rats, in order to validate the amplifier. PMID:15605867

Uranga, A; Navarro, X; Barniol, N

2004-12-01

182

Gigahertz low noise CMOS transimpedance amplifier  

Microsoft Academic Search

A new class of low noise CMOS common gate transimpedance amplifier is described. What is novel about the design is the total isolation of the photodiode capacitance from determining the -3 dB bandwidth. HSPICE simulations of this amplifier were conducted using the Tritech 0.6 ?m CMOS process. Simulated performance gives 2 GHz bandwidth, 1.13 k? transimpedance gain and very low

S. M. Park; C. Toumazou

1997-01-01

183

CMOS photodiodes for narrow linewidth applications  

Microsoft Academic Search

In recent years CMOS image sensors have gained a major market share for general imaging applications. However, when standard CMOS image sensors are employed in applications that require the detection of light with a very small spectral width, like 3D-time-of-flight imaging or other applications with laser light illumination, problems arise, that are negligible in standard imaging applications with broadband illumination.

Frank Hochschulz; Stefan Dreiner; Holger Vogt; Uwe Paschen

2011-01-01

184

CMOS scaling into the nanometer regime  

Microsoft Academic Search

Starting with a brief review on 0.1-?m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect

Yuan Taur; DOUGLAS A. BUCHANAN; Wei Chen; DAVID J. FRANK; KHALID E. ISMAIL; Shih-Hsien Lo; G. A. Sai-Halasz; R. G. Viswanathan; H.-J. C. Wann; S. J. Wind; Hon-Sum Wong

1997-01-01

185

High Linearity Down-Conversion CMOS Mixers  

Microsoft Academic Search

This paper gives a quantitative analysis of the main mechanisms setting fundamental limits to the linearity performances of CMOS direct down-conversion mixers. An advanced low voltage solution is proposed for 3G cell-phones in a 90 nm CMOS technology that achieves: 3nV\\/radicHz average input referred noise in the band from 10 kHz to 1.92 MHz, a flicker noise corner of 300

Danilo Manstretta

2008-01-01

186

Design and defect tolerance beyond CMOS  

Microsoft Academic Search

ABSTRACT It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advance- ment of CMOS-based VLSI circuits and systems. Regardless of the models, devices and technologies, any enhancement\\/replacement to CMOS must show,significant gains in at least one of the key met- rics (including speed, power and cost) for at least a

Xiaobo Sharon Hu; Alexander Khitun; Konstantin K. Likharev; Michael T. Niemier; Mingqiang Bao; Kang L Wang

2008-01-01

187

CMOS image sensors for sensor networks  

Microsoft Academic Search

We report on two generations of CMOS image sensors with digital output fabricated in a 0.6 ?m CMOS process. The imagers embed\\u000a an ALOHA MAC interface for unfettered self-timed pixel read-out targeted to energy-aware sensor network applications. Collision\\u000a on the output is monitored using contention detector circuits. The image sensors present very high dynamic range and ultra-low\\u000a power operation. This

Eugenio Culurciello; Andreas G. Andreou

2006-01-01

188

Embedded OTP fuse in CMOS logic process  

Microsoft Academic Search

This paper presents the embedded OTP fuse in standard CMOS logic compatible process without additional mask. The embedded OTP fuse can be programmed in 100?s per byte and be accessed in 6ns for 32 bits at once. The 32-bit OTP fuse takes less than 0.0085mm 2 in 0.25?m CMOS process and has 10-year data retention at 85°C.

Ching-Yuan Lin; Chung-Hung Lin; Chien-Hung Ho; Wei-Wu Liao; Shu-Yueh Lee; Ming-Chou Ho; Shin-Chen Wang; Shih-Chan Huang; Yuan-Tai Lin; Charles Ching-Hsiang Hsu

2005-01-01

189

Neutron spectrum and dose in a CMOS  

NASA Astrophysics Data System (ADS)

Using Monte Carlo methods the neutron spectrum in a pacemaker's CMOS has been estimated. A 18 MV LINAC model was used to expose a cell used to define the prostate located in a tissue equivalent phantom model. Neutron fluence at the CMOS is 2.6E(7) n/cm2-Gyx, the spectrum has thermal, epithermal and fast neutrons that will induce secondary, low and high LET, particles whose ionization could induce malfunction and failure of pacemaker in the oncological patient.

Vega-Carrillo, H. R.; Paredes-Gutierrez, L.; Borja-Hernandez, C. G.

2012-10-01

190

Back-thinned CMOS Sensor Optimisation  

Microsoft Academic Search

Back-thinning of a CCD image sensor is a very well established process for achieving high quantum efficiency and the majority of high-specification space and science applications have used such back-thinned devices for many years. CMOS sensors offer advantages over CCDs for a number of these applications and, in principle, it should be possible to back-thin CMOS devices and obtain the

Paul Jerram; David Burt; Neil Guyatt; Vincent Hibon; Joel Vaillant; Yann Henrion

191

Low-voltage log-domain signal processing in CMOS and BiCMOS  

Microsoft Academic Search

This paper presents the most important properties of log-domain filters for the realization of low-voltage and low power analog signal processing circuits. The noise behavior is discussed and the advantage of the combination of companding and class AB operation is highlighted. Examples of BiCMOS and CMOS realizations operating at supply voltages as low as 1 V are presented

Christian Enz; Manfred Punzenberger; Dominique Python

1999-01-01

192

BiCMOS current source reference network for ULSI BiCMOS with ECL circuitry  

Microsoft Academic Search

A BiCMOS current source reference network which eliminates the impact of DC power supply voltage drops on the operation of ECL (emitter coupled logic) circuits is described. This is essential for implementing ECL design techniques in ULSI BiCMOS circuits. Using the current source network, reference voltages are generated locally, so that the ECL voltage references are correctly referenced to the

Hiep Van Tran; Pak Kuen Fung; David Barry Scott

1989-01-01

193

Tin oxide gas sensor fabricated using CMOS micro-hotplates and in-situ processing  

Microsoft Academic Search

A monolithic tin oxide (SnO2) gas sensor realized by commercial CMOS foundry fabrication (MOSIS) and postfabrication processing techniques is reported. The device is composed of a sensing film that is sputter-deposited on a silicon micromachined hotplate. The fabrication technique requires no masking and utilizes in situ process control and monitoring of film resistivity during film growth. Microhotplate temperature is controlled

John S. Suehle; Richard E. Cavicchi; Michael Gaitan; Steve Semancik

1993-01-01

194

Infrared picosecond superconducting single-photon detectors for cmos-tircuit testing  

Microsoft Academic Search

Novel, NbN superconducting single-photon detectors have been developed for ultrafast, high quantum efficiency detection of single quanta of infrared radiation. Our devices have been successfully implemented in a commercial VLSI CMOS circuit testing system. 02003 Optical Society of America OCIS codes: (040.5570) Quantum detectors; (040.3060) Infrared We have developed novel, NbN-based, superconducting single-photon detectors (SSPDs) for non-contact testing and debugging

J. Zhang; A. Pearlman; W. Slysz; A. Verevkin; Roman Sobolewski; O. Okunev; A. Korneev; P. Kouminov; K. Smirnov; G. Chulkova; G. N. Gol'tsman; W. Lo; K. Wilsher

2003-01-01

195

Fabrication and Characterization of CMOS-MEMS Magnetic Microsensors.  

PubMed

This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5-200 mT. PMID:24172287

Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

2013-10-29

196

Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique  

PubMed Central

In this study we used the commercial 0.35 ?m CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz.

Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

2009-01-01

197

Ultrahigh-speed CMOS scanning linear imager family  

NASA Astrophysics Data System (ADS)

A family of monochrome, high-speed linear imagers has been developed with each device to be available as a single chip fabricated using a standard commercially available CMOS process. Currently, the 2048 pixel device has been fabricated using a 0.5-micron CMOS process and its architecture, functionality and performance is described. The family of imagers features a unique combination of high functional integration, very high speed, low dark current, high sensitivity and high pixel-to-pixel uniformity. The pixels are 7.0 microns by 7.0 microns and have 100 percent fill factor. The high pixel-pixel uniformity is made possible by using low dark current pixels, a correlated double sampler circuit per pixel and a fully differential video bus. High functional integration is enabled by on-chip logic that is provided to minimize support circuitry and simplify application. Included are several exposure modes that provide full-frame electronic shutter, independent control of integration time and simultaneous integration and read-out. Only 5 volts DC and clock signal running at twice the desired pixel rate are required for basic operation. Low dark current and high sensitivity result from a novel pixel and low-noise preamplifier structure. A novel video multiplexing structure provides the very high read-out speed of 60 Mpixel/sec per 2048 pixel segment while sustaining an MTF of 50 percent at 35 line pairs per millimeter.

Iodice, Robert M.; Zarnowski, Jeffrey J.; Pace, Matthew A.; Joyner, Michael; Vogelsong, Thomas L.; Zarnowski, Terry L.

2001-05-01

198

Smart optical and image sensors fabricated with industrial CMOS/CCD semiconductor processes  

NASA Astrophysics Data System (ADS)

Photosensitive elements with well-chosen geometry, combined with suitable analog and digital circuitry on the same CMOS/CCD chip, lead to 'smart image sensors' with interesting capabilities and properties. All our smart sensors were fabricated with commercially available multi-process wafer services of CMOS process, one of them with a buried-channel CCD option. Measurement of the optoelectronic properties of standard CMOS/CCD processes (wavelength-dependent quantum efficiency, lateral homogeneity of quantum efficiency/photo- conductivity, CCD charge transport efficiency, etc.) show excellent performance. The smartness that lies in the geometry is illustrated with a single-chip motion detector, a 3-D depth video camera, a single-chip planar distance sensor, and a sine/cosine (Fourier) transform sensor for fast optical phase measurements. The concept of problem-adapted geometry is also shown with a dynamic frame-transfer CCD whose pixel size and shape can be changed electrically in real-time through charge-binning. Based on the wavelength-dependent absorption of silicon, all-solid-state color pixels are demonstrated by properly arranging the available pn-junctions in the third (bulk) dimension. Moderate color measurement performance is achieved using an unmodified CMOS/CCD process, with a CIE general color-rendering index of Ra equals 69.5.

Seitz, Peter; Leipold, Dirk; Kramer, Joerg; Raynor, Jeffrey M.

1993-07-01

199

CMOS-Memristor Hybrid Nanoelectronics for AES Encryption.  

National Technical Information Service (NTIS)

Complementary metal oxide-semiconductor (CMOS) compatible nanotechnology was investigated under this effort to advance information technology by leveraging the well-proven vast functionality of the existing industry-standard CMOS integrated circuit manufa...

B. Wysocki J. Van Nostrand N. McDonald T. McEwen

2013-01-01

200

The comparison of CCD and CMOS image sensors  

NASA Astrophysics Data System (ADS)

The architectures of CCD and CMOS image sensors are introduced briefly, followed by comparison of their performances in detail. At last, the future development trends of CCD and CMOS image sensors are prospected. It is pointed out that CCD and CMOS image sensors will remain complementary and competition, and flourish the image sensor market together in predictable future.

Zhang, Lihua; Jin, Yongjun; Lin, Lin; Li, Jijun; Du, Yungang

2008-12-01

201

The comparison of CCD and CMOS image sensors  

Microsoft Academic Search

The architectures of CCD and CMOS image sensors are introduced briefly, followed by comparison of their performances in detail. At last, the future development trends of CCD and CMOS image sensors are prospected. It is pointed out that CCD and CMOS image sensors will remain complementary and competition, and flourish the image sensor market together in predictable future.

Lihua Zhang; Yongjun Jin; Lin Lin; Jijun Li; Yungang Du

2008-01-01

202

Technology and device scaling considerations for CMOS imagers  

Microsoft Academic Search

This paper presents an analysis of the impact of device and technology scaling on active pixel CMOS image sensors. Using the SLA roadmap as a guideline, we calculate the device characteristics that are germane to the image sensing performance of CMOS imagers, and highlight the areas where the CIMOS imager technology may need to depart from “standard” CMOS technologies. The

Hon-Sum Wong

1996-01-01

203

CMOS image sensors: electronic camera-on-a-chip  

Microsoft Academic Search

CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed

Eric R. Fossum

1997-01-01

204

Cascode voltage switch logic: A differential CMOS logic family  

Microsoft Academic Search

A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A CMOS circuit using 10,880 NMOS differential pairs has been developed using this approach.

L. Heller; W. Griffin; J. Davis; N. Thoma

1984-01-01

205

A standard CMOS humidity sensor without post-processing.  

PubMed

A 2 ?W power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023-10 humidity-sensitive layer, and a CMOS capacitance to voltage converter. PMID:22163949

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2011-06-08

206

New package for CMOS sensors  

NASA Astrophysics Data System (ADS)

Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

2004-02-01

207

Rad-tolerant flight VLSI from commercial foundries  

Microsoft Academic Search

This paper reviews techniques which have been used to protect CMOS circuits from the deleterious effects of the natural space radiation environment. Three custom flight VLSI processors have been designed and fabricated at commercial foundries. A program has been initiated to provide this radiation-tolerant VLSI technology to designers of Application Specific Integrated Circuits

J. W. Gambes; Gary K. Maki

1996-01-01

208

Analog CMOS/SOS in radiative environments  

NASA Astrophysics Data System (ADS)

A radiation tolerant Silicon On Sapphire (SOS) process used to produce Complementary Metal Oxide Semiconductor Application Specific Integrated Circuits (CMOS ASIC's) is described. Use of such analog/digital CMOS/bulk ASIC's in pacemakers and hearing aids is discussed. Recent development on the SOS process now makes it possible to make radiation hard analog designs as well. The SOS4 process and its analog opportunities are discussed. The SOS4 technology in general is presented and its advantages and drawbacks are discussed. Radiation effects on CMOS/SOS devices are presented in order to understand their impact on analog design. Performance results from a high speed comparator and a charge amplifier show different useful aspects of the SOS4 process.

Paulsson, Magnus

1991-03-01

209

CMOS cassette for digital upgrade of film-based mammography systems  

NASA Astrophysics Data System (ADS)

While full-field digital mammography (FFDM) technology is gaining clinical acceptance, the overwhelming majority (96%) of the installed base of mammography systems are conventional film-screen (FSM) systems. A high performance, and economical digital cassette based product to conveniently upgrade FSM systems to FFDM would accelerate the adoption of FFDM, and make the clinical and technical advantages of FFDM available to a larger population of women. The planned FFDM cassette is based on our commercial Digital Radiography (DR) cassette for 10 cm x 10 cm field-of-view spot imaging and specimen radiography, utilizing a 150 micron columnar CsI(Tl) scintillator and 48 micron active-pixel CMOS sensor modules. Unlike a Computer Radiography (CR) cassette, which requires an external digitizer, our DR cassette transfers acquired images to a display workstation within approximately 5 seconds of exposure, greatly enhancing patient flow. We will present the physical performance of our prototype system against other FFDM systems in clinical use today, using established objective criteria such as the Modulation Transfer Function (MTF), Detective Quantum Efficiency (DQE), and subjective criteria, such as a contrast-detail (CD-MAM) observer performance study. Driven by the strong demand from the computer industry, CMOS technology is one of the lowest cost, and the most readily accessible technologies available for FFDM today. Recent popular use of CMOS imagers in high-end consumer cameras have also resulted in significant advances in the imaging performance of CMOS sensors against rivaling CCD sensors. This study promises to take advantage of these unique features to develop the first CMOS based FFDM upgrade cassette.

Baysal, Mehmet A.; Toker, Emre

2006-03-01

210

IBM: Scaling CMOS to the Limit  

NSDL National Science Digital Library

This is the latest issue of the IBM Journal of Research and Development. "This double issue contains fifteen papers which address the challenges of scaling CMOS devices as physical limits are approached." Specifically, research teams report on topics such as silicon-on-insulator technology, new CMOS materials and device structures, dynamic random-access memory, and many others. The papers provide views of how far scaling could progress in the future and what constrains further advancement. Several back issues of the journal are also available, and each focuses on a different area of research.

2002-01-01

211

CMOS sensor for face tracking and recognition  

NASA Astrophysics Data System (ADS)

This paper describes the main principles of a vision sensor dedicated to the detecting and tracking faces in video sequences. For this purpose, a current mode CMOS active sensor has been designed using an array of pixels that are amplified by using current mirrors of column amplifier. This circuit is simulated using Mentor Graphics software with parameters of a 0.6 µm CMOS process. The circuit design is added with a sequential control unit which purpose is to realise capture of subwindows at any location and any size in the whole image.

Ginhac, Dominique; Prasetyo, Eri; Paindavoine, Michel

2005-03-01

212

Low-voltage log-domain signal processing in CMOS and BiCMOS  

Microsoft Academic Search

This paper presents the most important properties of log-domain filters for the realization of low-voltage (LV) and low-power (LP) analog signal processing circuits. The noise behavior is briefly discussed and the advantage of the combination of companding and class AB operation is highlighted. Examples of BiCMOS and standard digital CMOS realizations operating at supply voltages as low as 1 V

C. C. Enz; M. Punzenberger; D. Python

1997-01-01

213

Ge photodetectors integrated in CMOS photonic circuits  

NASA Astrophysics Data System (ADS)

We describe our approach to the monolithic integration of Ge photodetectors in a photonics-enabled CMOS technology. Ge waveguide photodetectors allow fast and efficient conversion of optical signals in the near infrared (1.55?m) to the electrical domain thus enabling the fabrication of compact, high speed (10Gbps) receivers.

Masini, G.; Sahni, S.; Capellini, G.; Witzens, J.; White, J.; Song, D.; Gunn, C.

2008-02-01

214

High-Performance CMOS Gate Array.  

National Technical Information Service (NTIS)

Mitsubishi Electric's unique gate-isolation configuration, which permits hybrid integration, was employed to develop a CMOS gate array having two gate modes: a 3 micrometer mode (3ns/gate) with 2,600, 1,600, and 1,100 gates; and a 2 micrometer mode (1.5ns...

M. Ueda T. Arakawa Y. Kuramitsu K. Okazaki K. Sugisaki

1984-01-01

215

Small-Signal Modeling of RF CMOS  

Microsoft Academic Search

This paper presents accurate small-signal modeling of RF CMOS, valid from DC to GHz ranges, using device simulation and analytical modeling. Distributed NQS effects in terms of circuit parameters are discussed and an estimation of the limit up to which quasi-static MOS- FET models are reasonable is presented. The impact of the substrate network through gmb multiplication on terminal ac

Jaejune Jang; Robert W. Dutton

216

Monolithic piezoresistive CMOS magnetic field sensors  

Microsoft Academic Search

Two original electromechanical magnetic sensors have been developed using a fully industrial fabrication process that relies on bulk wet etching of CMOS dies. The first device uses the Lorentz force to actuate a U-shaped cantilever beam, while piezoresistive polysilicon gauges convert the beam bending into an electrical signal. A 2?T sensor resolution is demonstrated, making this device suitable for earth

Vincent Beroulle; Yves Bertrand; Laurent Latorre; Pascal Nouet

2003-01-01

217

CMOS Equivalent Model of Ferroelectric RAM  

Microsoft Academic Search

The current research work in the paper is the representation of FRAM (Ferroelectric Random Access Memory) as an equivalent Model of Ferroelectric memory cell in Spice Tool. This Equivalent CMOS based model is designed to work at par with the behaviour working of the FRAM. The crux of the design of ferroelectric capacitor in the Ferroelectric Random Access Memory lies

Parvinder S. Sandhu; Iqbaldeep Kaur; Amit Verma; Birinderjit S. Kalyan; Jagdeep Kaur; Sanyam Anand

2010-01-01

218

Power-delay characteristics of CMOS adders  

Microsoft Academic Search

An approach to designing CMOS adders for both high speed and low power is presented by analyzing the performance of three types of adders - linear time adders, logN time adders and constant time adders. The representative adders used are a ripple carry adder, a blocked carry lookahead adder and several signed-digit adders, respectively. Some of the tradeoffs that are

Chetana Nagendra; Robert Michael Owens; Mary Jane Irwin

1994-01-01

219

Resonant mechanical magnetic sensor in standard CMOS  

Microsoft Academic Search

A novel micromechanical magnetic sensor has been built and tested. The field is detected by measuring the vibration amplitude of a mechanical Lorentz force oscillator. This device is made from a standard 2-?m CMOS fabrication process with a post-processing etch step to undercut and release the sensor. When operated at the resonant frequency of the mechanical system, a sensitivity of

Beverley Eyre; Kristofer S. J. Pister; William Kaiser

1998-01-01

220

Decoupling capacitor calculations for CMOS circuits  

Microsoft Academic Search

CMOS circuits on printed circuit boards with continuous power planes require decoupling capacitors to keep power supply within specification, provide signal integrity and reduce EMC\\/EMI radiated noise. Capacitor values and quantities are calculated using time and frequency domain techniques

L. D. Smith

1994-01-01

221

Multijunction thermal converters by commerical CMOS fabrication  

Microsoft Academic Search

New multijunction thermal converters (MJTCs) fabricated in a commerical CMOS foundry are described. The MJTC is a cantilever structure with a suspended, resistance heating element and thermocouple hot junctions located near the heater on the cantilever. The pit etched below is 150 × 150 ?m in size. The heater structure is composed of a polysilicon resistor and the thermocouples are

Michael Gaitan; John Suehle; Joseph R. Kinard; D. X. Huang

1993-01-01

222

Variable RF Inductor on Si CMOS Chip  

Microsoft Academic Search

We propose a novel variable inductor on a Si complementary metal oxide semiconductor (CMOS) chip, whose inductance is of nH-order, for GHz applications. The inductance value can be varied by moving a metal plate above the inductor. The magnetic flux penetrating the spiral inductor continuously varies depending on the position of the metal plate. The metal plate is slid horizontally

Hirotaka Sugawara; Yoshisato Yokoyama; Shinichiro Gomi; Hiroyuki Ito; Kenichi Okada; Hiroaki Hoshino; Hidetoshi Onodera; Kazuya Masu

2004-01-01

223

Minimizing power consumption in digital CMOS circuits  

Microsoft Academic Search

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology

ANANTHA P. CHANDRAKASAN; ROBERT W. BRODERSEN

1995-01-01

224

Power consumption estimation in CMOS VLSI chips  

Microsoft Academic Search

Power consumption from logic circuits, interconnections, clock distribution, on chip memories, and off chip driving in CMOS VLSI is estimated. Estimation methods are demonstrated and verified. An estimate tool is created. Power consumption distribution between interconnections, clock distribution, logic gates, memories, and off chip driving are analyzed by examples. Comparisons are done between cell library, gate array, and full custom

Dake Liu; Christer Svensson

1994-01-01

225

CMOS\\/SOS for electronic watch applications  

Microsoft Academic Search

Crystal-controlled watch circuits using CMOS\\/SOS technology will be discussed. The low-power high-speed features of this technology allows the use of less costly, high-frequency, thermally-stable, AT-cut quartz crystals. Circuits have operated at 1.4 V\\/4 MHz, consuming less than 12?W.

A. Ipri; J. Sarace

1974-01-01

226

SOC CMOS technology for personal Internet products  

Microsoft Academic Search

Worldwide demand for Personal Internet Products is increasing rapidly, and will shape the directions of CMOS technology in the years ahead. Personal Internet Products are loosely defined in this paper as communication, computing and consumer products, which are enabled by the Internet: cell phones, PDAs, WLANs, Internet audio\\/video, ADSL, cable modems etc. Personal Internet Products are based on Digital Signal

Dennis Buss; Brian L. Evans; Jeff Bellay; William Krenik; Baher Haroun; Dirk Leipold; Ken Maggio; Jau-Yuann Yang; Ted Moise

2003-01-01

227

Substrate bonding techniques for CMOS processed wafers  

NASA Astrophysics Data System (ADS)

Transferring a CMOS circuit to a foreign substrate can be accomplished by bonding a processed silicon wafer to the substrate and subsequently thinning the silicon wafer. This paper presents both anodic bonding and adhesive bonding and evaluates their potential for circuit transfer.

van der Groen, S.; Rosmeulen, M.; Baert, K.; Jansen, P.; Deferm, L.

1997-09-01

228

A CNN universal chip in CMOS technology  

Microsoft Academic Search

This paper describes the design of a CNN universal chip in a standard CMOS technology. The core of the chip consists of an array of 32×32 completely programmable CNN cells. Input image can be loaded in optical or electrical form. Accuracy is in the range of 7-8 bit and cell density is of 33 cells\\/mm2

R. Dominguez-Castro; S. Espejo; A. Rodriguez-Vazquez; R. Carmona

1994-01-01

229

Current Reference Circuit for Subthreshold CMOS LSIs  

Microsoft Academic Search

Intelligent network systems for the future will require a great number of smart sensor LSIs that measure various physical data in surroundings. These LSIs have to operate with a low power, tens of microwatts or less, because they will probably be placed in non-ideal environments where energy for operation cannot be obtained sufficiently. To achieve such ultra-low power operation, CMOS

Ken Ueno; Tetsuya Asai; Yoshihito Amemiya; IBIAS IBIAS

230

Toward CMOS image sensor based glucose monitoring.  

PubMed

Complementary metal oxide semiconductor (CMOS) image sensor is a powerful tool for biosensing applications. In this present study, CMOS image sensor has been exploited for detecting glucose levels by simple photon count variation with high sensitivity. Various concentrations of glucose (100 mg dL(-1) to 1000 mg dL(-1)) were added onto a simple poly-dimethylsiloxane (PDMS) chip and the oxidation of glucose was catalyzed with the aid of an enzymatic reaction. Oxidized glucose produces a brown color with the help of chromogen during enzymatic reaction and the color density varies with the glucose concentration. Photons pass through the PDMS chip with varying color density and hit the sensor surface. Photon count was recognized by CMOS image sensor depending on the color density with respect to the glucose concentration and it was converted into digital form. By correlating the obtained digital results with glucose concentration it is possible to measure a wide range of blood glucose levels with great linearity based on CMOS image sensor and therefore this technique will promote a convenient point-of-care diagnosis. PMID:22764059

Devadhasan, Jasmine Pramila; Kim, Sanghyo

2012-07-05

231

A Beta neuron in CMOS subthreshold mode  

Microsoft Academic Search

Beta Basis Function Neural Networks (BBFNN) are powerful systems for learning and universal approximation characteristics. In this paper, we present a hardware implementation of the Beta neuron using the CMOS subthreshold-mode. We describe a low power low voltage analog Beta neuron circuit. Three main modules are used to realize the Beta function: a logarithmic current to voltage converter, a multiplier

Mounix SAMET; M. Masmoudi; Fahmi GHOZZI; Yassine BEN AYED; Adel M. ALIMI

1998-01-01

232

CMOS sensor arrays for bio molecule diagnostics  

Microsoft Academic Search

CMOS-based sensor array chips for bio molecule detection provide high parallelism and further attractive features as compared to today's standard tools. They open the way to smart systems in medical and diagnostic applications. In this paper, a topical review is given concerning the basic operating principles of such arrays, transducer principles, related technical requirements and specifications, circuit design and system

Roland Thewes

2010-01-01

233

SiGe HBT X-Band LNAs for Ultra-Low-Noise Cryogenic Receivers  

Microsoft Academic Search

We report results on the cryogenic operation of two different monolithic X-band silicon-germanium (SiGe) heterojunction bipolar transistor low noise amplifiers (LNAs) implemented in a commercially-available 130 nm SiGe BiCMOS platform. These SiGe LNAs exhibit a dramatic reduction in noise temperature with cooling, yielding of less than 21 K (0.3 dB noise figure) across X-band at a 15 K operating temperature.

Tushar K. Thrivikraman; Jiahui Yuan; Joseph C. Bardin; Hamdi Mani; Stanley D. Phillips; Wei-Min Lance Kuo; John D. Cressler; Sander Weinreb

2008-01-01

234

Architecture of a Slow-Control ASIC for Future High-Energy Physics Experiments at SLHC  

Microsoft Academic Search

This work is aimed at defining the architecture of a new digital ASIC, namely slow control logic (SCL), which will be designed and fabricated in a commercial 130 nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics proposed for future high-energy physics experiments at the super-Large

A. Gabrielli; G. De Robertis; D. Fiore; F. Loddo; A. Ranieri

2009-01-01

235

77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...  

Federal Register 2010, 2011, 2012, 2013

...Investigation No. 337-TA-846] Certain CMOS Image Sensors and Products Containing Same...United States after importation of certain CMOS image sensors and products containing same...United States after importation of certain CMOS image sensors and products containing...

2012-06-06

236

77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...  

Federal Register 2010, 2011, 2012, 2013

...COMMISSION [Docket No. 2895] Certain CMOS Image Sensors and Products Containing Same...has received a complaint entitled Certain CMOS Image Sensors and Products Containing Same...United States after importation of certain CMOS image sensors and products containing...

2012-05-07

237

Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers  

NASA Astrophysics Data System (ADS)

This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

Liu, Yu-Chia; Tsai, Ming-Han; Tang, Tsung-Lin; Fang, Weileun

2011-10-01

238

Modeling and Estimation of FPN Components in CMOS Image Sensors  

Microsoft Academic Search

Fixed pattern noise #FPN# for a CCD sensor is modeled as a sample of a spatial white noise process. This model is,however, not adequate for characterizing FPN in CMOS sensors, since the readout circuitry of CMOS sensors andCCDs are very di#erent. The paper presents a model for CMOS FPN as the sum of two components: a columnand a pixel component.

Abbas El Gamal; Boyd Fowler; Hao Min; Xinqiao Liu

1998-01-01

239

CMOS Image Sensors With Self-Powered Generation Capability  

Microsoft Academic Search

Considerations for CMOS image sensors with self-power generation capability design are presented. Design of CMOS imagers, utilizing self-powered sensors (SPS) is a new approach for ultra low-power CMOS active pixel sensors (APS) implementations. The SPS architecture allows generation of electric power by employing a light sensitive device, located on the same silicon die with an APS and thus reduces power

Alexander Fish; Shy Hamami; Orly Yadid-Pecht

2006-01-01

240

Checkered white-RGB color LOFIC CMOS image sensor  

Microsoft Academic Search

We succeeded in developing a checkered White-RGB color CMOS image sensor based on a lateral overflow integration capacitor (LOFIC) architecture. The LOFIC CMOS image sensor with a 1\\/3.3-inch optical format, 1280H x 480V pixels, 4.2-?m effective pixel pitch along with 45° direction was designed and fabricated through 0.18-?m 2-Poly 3-Metal CMOS technology with buried pinned photodiode (PD) process. The image

Shun Kawada; Shin Sakai; Yoshiaki Tashiro; Shigetoshi Sugawa

2010-01-01

241

Performance of 70 nm strained-silicon CMOS devices  

Microsoft Academic Search

An 86% electron mobility improvement and over 20% Idn-sat enhancement were demonstrated for a 70 nm strained-Si CMOS process fabricated on SiGe virtual substrates. Compared to a bulk-Si CMOS process, the strained-Si process delivered 95% higher inverter peak-current and a 2.2 ps reduction in ring oscillator delay for the same drive current. Strained and bulk CMOS featured equivalent gate leakage

J. R. Hwang; J. H. Ho; S. M. Ting; T. P. Chen; Y. S. Hsieh; C. C. Huang; Y. Y. Chiang; H. K. Lee; Ariel Liu; T. M. Shen; G. Braithwaite; M. Currie; N. Gerrish; R. Hammond; A. Lochtefeld; F. Singaporewala; M. Bulsara; Q. Xiang; M. R. Lin; W. T. Shiau; Y. T. Loh; J. K. Chen; S. C. Chien; F. Wen

2003-01-01

242

300GHz Transistor Performance in Production CMOS Technologies  

Microsoft Academic Search

CMOS technology scaling has resulted in a continuous improvement in RF performance of silicon MOSFETs. fT and fMAX in excess of 300GHz has been demonstrated in production CMOS nodes [1]. 400GHz fT for ultra-short channel MOSFET with LGATE of 10nm has also been reported [2]. CMOS based RF solutions are already mainstream for applications in the 1-10GHz regime and with

B. Jagannathan; D. Chidambarrao; J. Pekarik

2006-01-01

243

CMOS compatible thin-film ALD tungsten nanoelectromechanical devices  

Microsoft Academic Search

This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS\\/NEMS hybrid systems, and NEMS based micro-processors\\/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches\\/devices to

Bradley Darren Davidson

2010-01-01

244

Universal high voltage multiplexer for CMOS OTP memory applications  

Microsoft Academic Search

A CMOS-compatible high voltage multiplexer (HV MUX) for zero-additional-mask CMOS one time programmable (OTP) memory array mask is presented. The HV MUX uses standard CMOS with low input voltage and produce high output voltage beyond the VDD allowed by the process for programming the OTP memory array. By limiting the instantaneous voltage between any two nodes, the HV MUX can

Kwok Ping Ng; M. C. Lee; Wan Tim Chan; Randy Barsatan; Mansun Chan

2008-01-01

245

3Transistor antifuse OTP ROM array using standard CMOS process  

Microsoft Academic Search

A 3-transistor cell CMOS OTP ROM array using CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the

Jinbong Kim; Kwyro Lee

2003-01-01

246

A generalized CMOS-MEMS platform for micromechanical resonators monolithically integrated with circuits  

NASA Astrophysics Data System (ADS)

A generalized foundry-oriented CMOS-MEMS platform well suited for integrated micromechanical resonators alongside IC amplifiers has been developed for commercial multi-user purpose and demonstrated with a fast turnaround time of only 3 months and a variety of design flexibilities for resonator applications. With this platform, different configurations of capacitively-transduced resonators monolithically integrated with their amplifier circuits, spanning frequencies from 500 kHz to 14.5 MHz, have been realized with resonator Q's ranging between 700 and 3500. This platform, specifically featured with various configurations of structural materials, multi-dimensional displacements, different arrangements of mechanical boundary conditions, tiny supports of resonators, large transduction areas, well-defined anchors and performance enhancement scaling with IC fabrication technology, offers a variety of flexible design options targeted for sensor, timing reference, and RF applications. In addition, resonators consisting of metal-oxide composite structures fabricated by this platform offer an effective temperature compensation scheme for the first time in CMOS-MEMS resonators, showing TCf six times better than that of resonators merely made by CMOS metals.

Chen, Wen-Chien; Fang, Weileun; Li, Sheng-Shian

2011-06-01

247

SiGe BiCMOS manufacturing platform for mmWave applications  

NASA Astrophysics Data System (ADS)

TowerJazz offers high volume manufacturable commercial SiGe BiCMOS technology platforms to address the mmWave market. In this paper, first, the SiGe BiCMOS process technology platforms such as SBC18 and SBC13 are described. These manufacturing platforms integrate 200 GHz fT/fMAX SiGe NPN with deep trench isolation into 0.18?m and 0.13?m node CMOS processes along with high density 5.6fF/?m2 stacked MIM capacitors, high value polysilicon resistors, high-Q metal resistors, lateral PNP transistors, and triple well isolation using deep n-well for mixed-signal integration, and, multiple varactors and compact high-Q inductors for RF needs. Second, design enablement tools that maximize performance and lowers costs and time to market such as scalable PSP and HICUM models, statistical and Xsigma models, reliability modeling tools, process control model tools, inductor toolbox and transmission line models are described. Finally, demonstrations in silicon for mmWave applications in the areas of optical networking, mobile broadband, phased array radar, collision avoidance radar and W-band imaging are listed.

Kar-Roy, Arjun; Howard, David; Preisler, Edward; Racanelli, Marco; Chaudhry, Samir; Blaschke, Volker

2010-10-01

248

270GHz SiGe BiCMOS manufacturing process platform for mmWave applications  

NASA Astrophysics Data System (ADS)

TowerJazz has been offering the high volume commercial SiGe BiCMOS process technology platform, SBC18, for more than a decade. In this paper, we describe the TowerJazz SBC18H3 SiGe BiCMOS process which integrates a production ready 240GHz FT / 270 GHz FMAX SiGe HBT on a 1.8V/3.3V dual gate oxide CMOS process in the SBC18 technology platform. The high-speed NPNs in SBC18H3 process have demonstrated NFMIN of ~2dB at 40GHz, a BVceo of 1.6V and a dc current gain of 1200. This state-of-the-art process also comes with P-I-N diodes with high isolation and low insertion losses, Schottky diodes capable of exceeding cut-off frequencies of 1THz, high density stacked MIM capacitors, MOS and high performance junction varactors characterized up to 50GHz, thick upper metal layers for inductors, and various resistors such as low value and high value unsilicided poly resistors, metal and nwell resistors. Applications of the SBC18H3 platform for millimeter-wave products for automotive radars, phased array radars and Wband imaging are presented.

Kar-Roy, Arjun; Preisler, Edward J.; Talor, George; Yan, Zhixin; Booth, Roger; Zheng, Jie; Chaudhry, Samir; Howard, David; Racanelli, Marco

2011-10-01

249

Design of an ultra low power CMOS pixel sensor for a future neutron personal dosimeter  

SciTech Connect

Despite a continuously increasing demand, neutron electronic personal dosimeters (EPDs) are still far from being completely established because their development is a very difficult task. A low-noise, ultra low power consumption CMOS pixel sensor for a future neutron personal dosimeter has been implemented in a 0.35 {mu}m CMOS technology. The prototype is composed of a pixel array for detection of charged particles, and the readout electronics is integrated on the same substrate for signal processing. The excess electrons generated by an impinging particle are collected by the pixel array. The charge collection time and the efficiency are the crucial points of a CMOS detector. The 3-D device simulations using the commercially available Synopsys-SENTAURUS package address the detailed charge collection process. Within a time of 1.9 {mu}s, about 59% electrons created by the impact particle are collected in a cluster of 4 x 4 pixels with the pixel pitch of 80 {mu}m. A charge sensitive preamplifier (CSA) and a shaper are employed in the frond-end readout. The tests with electrical signals indicate that our prototype with a total active area of 2.56 x 2.56 mm{sup 2} performs an equivalent noise charge (ENC) of less than 400 e - and 314 {mu}W power consumption, leading to a promising prototype. (authors)

Zhang, Y.; Hu-Guo, C.; Husson, D.; Hu, Y. [Institut Pluridisplinaire Hubert Curien IPHC, Univ. of Strasbourg, CNRS/IN2P3, 23 Rue du Loess, 67037 Strasbourg (France)

2011-07-01

250

High-performance CMOS image sensors at BAE SYSTEMS Imaging Solutions  

NASA Astrophysics Data System (ADS)

In this paper, we present an overview of high-performance CMOS image sensor products developed at BAE SYSTEMS Imaging Solutions designed to satisfy the increasingly challenging technical requirements for image sensors used in advanced scientific, industrial, and low light imaging applications. We discuss the design and present the test results of a family of image sensors tailored for high imaging performance and capable of delivering sub-electron readout noise, high dynamic range, low power, high frame rates, and high sensitivity. We briefly review the performance of the CIS2051, a 5.5-Mpixel image sensor, which represents our first commercial CMOS image sensor product that demonstrates the potential of our technology, then we present the performance characteristics of the CIS1021, a full HD format CMOS image sensor capable of delivering sub-electron read noise performance at 50 fps frame rate at full HD resolution. We also review the performance of the CIS1042, a 4-Mpixel image sensor which offers better than 70% QE @ 600nm combined with better than 91dB intra scene dynamic range and about 1 e- read noise at 100 fps frame rate at full resolution.

Vu, Paul; Fowler, Boyd; Liu, Chiao; Mims, Steve; Balicki, Janusz; Bartkovjak, Peter; Do, Hung; Li, Wang

2012-07-01

251

Noise in a CMOS digital pixel sensor  

NASA Astrophysics Data System (ADS)

Based on the study of noise performance in CMOS digital pixel sensor (DPS), a mathematical model of noise is established with the pulse-width-modulation (PWM) principle. Compared with traditional CMOS image sensors, the integration time is different and A/D conversion is implemented in each PWM DPS pixel. Then, the quantitative calculating formula of system noise is derived. It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region. In this model, photodiode shot noise does not vary with luminance, but dark current shot noise does. According to increasing photodiode capacitance and the comparator's reference voltage or optimizing the mismatch in the comparator, the total noise can be reduced. These results serve as a guideline for the design of PWM DPS.

Chi, Zhang; Suying, Yao; Jiangtao, Xu

2011-11-01

252

IR CMOS: infrared enhanced silicon imaging  

NASA Astrophysics Data System (ADS)

SiOnyx has developed visible and infrared CMOS image sensors leveraging a proprietary ultrafast laser semiconductor process technology. This technology demonstrates 10 fold improvements in infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Furthermore, these sensitivity enhancements are achieved on a focal plane with state of the art noise performance of 2 electrons/pixel. By capturing light in the visible regime as well as infrared light from the night glow, this sensor technology provides imaging in daytime through twilight and into nighttime conditions. The measured 10x quantum efficiency at the critical 1064 nm laser node enables see spot imaging capabilities in a variety of ambient conditions. The spectral sensitivity is from 400 to 1200 nm.

Pralle, M. U.; Carey, J. E.; Haddad, Homayoon; Vineis, C.; Sickler, J.; Li, X.; Jiang, J.; Sahebi, F.; Palsule, C.; McKee, J.

2013-06-01

253

CMOS X-ray Image Sensor Array  

Microsoft Academic Search

This paper describes a pixel array for x-rays imaging consisting in an 8??8 photodiode array fabricated in CMOS technology, with the respective readout circuit. Above the photodiodes, an array of scintillating CsI:Tl crystals are placed. So, the x-ray energy is first converted to visible light by the scintillating crystals, which is then detected by the photodiodes. The photocurrent produced by

J. Silva; S. Lanceros-Mendez; G. Minas; J. G. Rocha

2007-01-01

254

Smart optical CMOS sensor for endoluminal applications  

Microsoft Academic Search

A custom CMOS image sensor designed for low power endoluminal applications is presented. The fabricated chip includes a 320×240 pixel array, a complete read-out channel, a 10-bit ADC converter, a series of DACs for internal references and digital blocks for chip control. The complete functionality of the chip is guaranteed through 7 signal pins, used for the I2C-like input and

Monica Vatteroni; Daniele Covi; Carmela Cavallotti; Luca Clementel; Pietro Valdastri; Arianna Menciassi; Paolo Dario; Alvise Sartori

2010-01-01

255

Delay optimization of combinational static CMOS logic  

Microsoft Academic Search

Several methods for increasing the speed of combinational static CMOS circuits, including techniques for partitioning gates on the basis of circuit complexity and input arrival time, are described. The target layout style is standard cell, rather than a PLA or gate matrix scheme. Use of a standard-cell-like image allows a two-level buffered hierarchy to be introduced which is beneficial to

M. Hofmann; Jac K. Kim

1987-01-01

256

Deep-submicron tungsten gate CMOS technology  

Microsoft Academic Search

A tungsten-gate CMOS technology has been developed using a low-impurity selective epi-channel and thin gate oxide. The use of this technology leads to a reduction in threshold-voltage sensitivity to process fluctuations such as epi-channel concentration and gate-oxide thickness. The short-channel effect for deep submicron gate MOSFETs can be suppressed by a 50 approximately 10-nm-thick epi-layer with an abrupt impurity profile.

N. Kasai; N. Endo; A. Ishitani

1988-01-01

257

RF-CMOS oscillators with switched tuning  

Microsoft Academic Search

Fully integrated CMOS oscillators are of great interest for use in single-chip wireless transceivers. In most oscillator circuits reported to date that operate in the 0.9 to 2 GHz frequency range, an integrated spiral inductor sets the frequency. It is generally believed that an LC oscillator, even when it uses a low-Q inductor, displays a lower phase noise than a

A. Kral; F. Behbahani; A. A. Abidi

1998-01-01

258

High-speed CMOS circuit technique  

Microsoft Academic Search

Ahtract -We have demonstrated that clock frequencies in ewes5 of 200 MHz are feasible in a 3-pm CMOS process. This is obtained by mean5 of clocking strategj, device sizing, and logic style selection. We use a precharge technique with a true single-phase clock, which remarkably increases the clock frequent) and reduces the skew problems, Device sizing with the help of

JIREN YUAN; CHRISTER SVENSSON

1989-01-01

259

Cantilever-Based Biosensors in CMOS Technology  

Microsoft Academic Search

Single-chip CMOS-based biosensors that feature microcantilevers as transducer elements are presented. The cantilevers are functionalized for the capturing of specific analytes, e.g., proteins or DNA. The binding of the analyte changes the mechanical properties of the cantilevers such as surface stress and resonant frequency, which can be detected by an integrated Wheatstone bridge. The monolithic integrated readout allows for a

Kay-uwe Kirstein; Yue Li; Martin Zimmermann; Cyril Vancura; Tormod Volden; Wan Ho Song; Jan Lichtenberg; Andreas Hierlemann

2007-01-01

260

Cantilever-Based Biosensors in CMOS Technology  

Microsoft Academic Search

Single-chip CMOS-based biosensors that feature microcantilevers as transducer elements are presented. The cantilevers are functionalized for the capturing of specific analytes, e.g., proteins or DNA. The binding of the analyte changes the mechanical properties of the cantilevers such as surface stress and resonant frequency, which can be detected by an integrated Wheatstone bridge. The monolithic integrated readout allows for a

A. Hierlemannn

261

Cantilever-Based Biosensors in CMOS Technology  

Microsoft Academic Search

Single-chip CMOS-based biosensors that feature microcantilevers as transducer elements are presented. The cantilevers are functionalized for the capturing of specific analytes, e.g., proteins or DNA. The binding of the analyte changes the mechanical properties of the cantilevers such as surface stress and resonant frequency, which can be detected by an integrated Wheatstone bridge. The monolithic integrated readout allows for a

Kay-Uwe Kirstein; Yue Li; Martin Zimmermann; Cyril Vancura; Tormod Volden; Wan Ho Song; Jan Lichtenberg; A. Hierlemannn

2005-01-01

262

A CNN UNIVERSAL CHIP IN CMOS TECHNOLOGY  

Microsoft Academic Search

This paper describes the design of a programmable Cellular Neural Network (CNN) chip,with added functionalities similar to those of the CNN Universal Machine. The prototype contains1024 cells and has been designed in a 1.0|ìm, n-well CMOS technology. Careful selectionof the topology and design parameters has resulted in a cell density of 31 cells\\/mm2and around7-8 bits accuracy in the weight values.

S. ESPEJO; R. Domínguez-Castro; R. Carmona; A. RODRÍGUEZ-VÁZQUEZ

1996-01-01

263

Broadband esd protection circuits in cmos technology  

Microsoft Academic Search

Abstract, A broadband technique using monolithic T-coils is applied to electrostatic discharge (ESD) structures for both input and output pads. Fabricated in 0.18-m CMOS technology, the prototypes achieve operation at 10 Gb\\/s while providing a return loss of 20 dB at 10 GHz. The human-body model tolerance is 1000 V for the input structure and 800-900 V for the output

Sherif Galal; Behzad Razavi

2003-01-01

264

Space efficient CMOS nonlinear transmission lines  

Microsoft Academic Search

Nonlinear transmission lines (NLTLs) are used in diverse applications such as edge-sharpening, pulse generation, and frequency conversion, however, length of a useful NLTL can require significant MMIC or RFIC real estate. We present an analytical model for the complex propagation constant of lossy, distributed NLTLs and fabricate several NLTLs in 0.25 mum CMOS for verification. Space-saving layout techniques such as

Keith G. Lyon; Fan Yu; Edwin C. Kan

2009-01-01

265

IDDQ testing in CMOS digital ASICs  

Microsoft Academic Search

IDDQ testing with precision measurement unit (PMU) was used to eliminate early life failures caused by CMOS digital ASICs in our products. Failure analysis of the rejected parts found that bridging faults caused by particles were not detected in incoming tests created by automatic test generation (ATG) for stuck-at-faults (SAF). The nominal 99.6% SAF test coverage required to release a

Roger Perry

1992-01-01

266

CMOS active pixel image sensors fabricated using a 1.8-V, 0.25-?m CMOS technology  

Microsoft Academic Search

This paper reports the experimental results of the first CMOS active pixel image sensors (APS) fabricated using a high-performance 1.8-V, 0.25-?m CMOS logic technology. No process modifications were made to the CMOS logic technology so that the impact of device scaling on the image sensing performance can be studied. This paper highlights the device and process design considerations required to

Hon-Sum Philip Wong; Richard T. Chang; E. Crabbe; P. D. Agnello

1998-01-01

267

Single-pixel carrier-based approach for full-field laser interferometry using a CMOS-DSP camera  

NASA Astrophysics Data System (ADS)

This investigation describes the implementation of a Single Pixel Carrier Based Demodulation (SPCBD) approach on a digital CMOS-DSP camera for full-field heterodyne interferometry. A full-field vibration measurement system is presented as an alternative to a classical scanning Laser Doppler Vibrometer (LDV). The Heterodyne set-up, CMOS-DSP camera and the signal demodulation techniques adopted are described. Characterisation tests that describe the basic performance of the CMOS-DSP camera, in terms of acquisition rates and time response are presented. A simple experiment was performed to demonstrate the novel laser vibrometry system that consisted of determining the displacement of a point on the surface of a vibrating mirror. The measured velocity and displacement data were compared to the output from a commercial LDV. The integration of a CMOS sensor, DSP and a laser-doppler interferometer has lead to the development of a fully digital "functional" machine vision system that provides a flexible, compact and inexpensive tool for automated high-precision optical measurements.

Aguanno, Mauro V.; Lakestani, Fereydoun; Whelan, Maurice P.; Connelly, Michael J.

2004-02-01

268

A novel compact model for on-chip stacked transformers in RF-CMOS technology  

NASA Astrophysics Data System (ADS)

A novel compact model for on-chip stacked transformers is presented. The proposed model topology gives a clear distinction to the eddy current, resistive and capacitive losses of the primary and secondary coils in the substrate. A method to analytically determine the non-ideal parasitics between the primary coil and substrate is provided. The model is further verified by the excellent match between the measured and simulated S -parameters on the extracted parameters for a 1 : 1 stacked transformer manufactured in a commercial RF-CMOS technology.

Jun, Liu; Jincai, Wen; Qian, Zhao; Lingling, Sun

2013-08-01

269

Evaluation and verification of improved edgebead removal process in CMOS production  

NASA Astrophysics Data System (ADS)

This paper describes an engineering approach that was taken to improve an existing edgebead removal process which used acetone exclusively. Production problems were encountered after exposure and develop of positive photoresist: after the UV bake step. These problems were manifested by popping photoresist. The approach taken here was to evaluate acetone by itself as an edgebead remover and compare it with a commercially available EBR. Specifically, a combination of ethyl lactate and 2-pentanone. The improved edgebead removal process is presented as a function of photoresist popping after the UV bake step for our CMOS process.

Christensen, Lorna D.; Marchione, M.; Luce, K.

1995-06-01

270

CMOS image sensor integrated with micro-LED and multielectrode arrays for the patterned photostimulation and multichannel recording of neuronal tissue.  

PubMed

We developed a complementary metal oxide semiconductor (CMOS) integrated device for optogenetic applications. This device can interface via neuronal tissue with three functional modalities: imaging, optical stimulation and electrical recording. The CMOS image sensor was fabricated on 0.35 ?m standard CMOS process with built-in control circuits for an on-chip blue light-emitting diode (LED) array. The effective imaging area was 2.0 × 1.8 mm². The pixel array was composed of 7.5 × 7.5 ?m² 3-transistor active pixel sensors (APSs). The LED array had 10 × 8 micro-LEDs measuring 192 × 225 ?m². We integrated the device with a commercial multichannel recording system to make electrical recordings. PMID:22418489

Nakajima, Arata; Kimura, Hiroshi; Sawadsaringkarn, Yosmongkol; Maezawa, Yasuyo; Kobayashi, Takuma; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Ishikawa, Yasuyuki; Shiosaka, Sadao; Ohta, Jun

2012-03-12

271

Intelligent Vehicle Road Recognition based on the CMOS camera  

Microsoft Academic Search

Since the problems of intelligent auxiliary driving and co-navigating have received more and more attention recent years, a road recognition system is developed for the intelligent vehicle with CMOS camera as its road sensor, which provides solutions for the road recognition and automatic drive functions of the intelligent vehicle. The installation and sampling process of the CMOS camera is explained.

Chu Liu; Jie Chen; Yifan Xu; Feng Luo

2008-01-01

272

Trends in CMOS image sensor technology and design  

Microsoft Academic Search

Three trends that promise to increase CMOS image sensor system performance are presented: (i) modifications of deep submicron CMOS processes to improve their imaging characteristics, (ii) developments that take advantage of these modified deep submicron processes, and (iii) high frame rate sensors and applications to still and video imaging, specifically to extending sensor dynamic range. Recent research on Digital Pixel

Abbas El Gamal

2002-01-01

273

A portable oxygen sensor based on a CMOS detector  

Microsoft Academic Search

This work describes a portable and sensitive optical oxygen sensor based on a consumer CMOS image sensor array and polarization signal isolation. The CMOS sensor was fully characterized and the feasibility of using it as an optical detector was explored. The oxygen sensor is based on quenching of platinum octaethylporphine (PtOEP) luminophore. Sensitivity of the demonstrated sensor is comparable to

Li Shen; Michael Ratterman; Ian Papautsky; David Klotzkin

2010-01-01

274

LECTOR: a technique for leakage reduction in CMOS circuits  

Microsoft Academic Search

In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in subthreshold leakage current and hence static power dissipation. We propose a novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. In the proposed technique, we introduce two leakage control transistors (a

Narender Hanchate; Nagarajan Ranganathan

2004-01-01

275

Recent status on Nano CMOS and future direction  

Microsoft Academic Search

Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length CMOS was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node, and it is still questionable if we can successfully

H. Iwai

2006-01-01

276

A 1-V CMOS log-domain integrator  

Microsoft Academic Search

A novel circuit implementation of a CMOS log-domain integrator is presented. Unlike most other implementations, it does not require placing of MOSFETs in separated wells, and therefore allows very compact filters, which are fully compatible with modern standard CMOS technologies. Besides the saving of chip area, this also helps to reduce parasitic capacitances. The most important advantage of this circuit

Dominique Python; Manfred Punzenberger; Christian C. Enz

1999-01-01

277

A CMOS serial link for fully duplexed data communication  

Microsoft Academic Search

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by

Kyeongho Lee; Sungjoon Kim; Gijung Ahn; Deog-Kyoon Jeong

1995-01-01

278

Quiescent power supply current measurement for CMOS IC defect detection  

Microsoft Academic Search

Quiescent power supply current (IDDQ) measurement is a very effective technique for detecting in CMOS integrated circuits (ICs). This technique uniquely detects certain CMOS IC defects such as gate oxide shorts, defective p-n junctions, and parasitic transistor leakage. In addition, IDDQ monitoring will detect all stuck-at faults with the advantage of using a node toggling test set that has fewer

CHARLES F. HAWKINS; JERRY M. SODEN; RONALD R. FRITZEMEIER; LUTHER K. HORNING

1989-01-01

279

A CMOS fault extractor for inductive fault analysis  

Microsoft Academic Search

The inductive fault analysis (IFA) method is presented and a description is given of the CMOS fault extraction program FXT. The IFA philosophy is to consider the causes of faults (manufacturing defects) and then simulate these causes to find the faults that are likely to occur in a circuit. FXT automates IFA for a CMOS technology by generating a list

F. Joel Ferguson; John Paul Shen

1988-01-01

280

CMOS front end components for micropower RF wireless systems  

Microsoft Academic Search

New applications have recently appeared for a low power, low cost, “embedded radio”. These wireless interfaces for handheld mobile nodes and Wireless Integrated Network Sensors (WINS) must provide spread spectrum signaling for multi-user operation at 902-928 MHz. Cost considerations motivate the development of complete micropower CMOS RF systems operating at previously unexplored low power levels. Micropower CMOS VCO and mixer

Tsuiig-Hsien Lin; Henry Sanchez; Razieh Rofougaran; William J. Kaiser

1998-01-01

281

Lab-on-CMOS integration of microfluidics and electrochemical sensors.  

PubMed

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Huang, Yue; Mason, Andrew J

2013-08-27

282

Supply and threshold voltage scaling for low power CMOS  

Microsoft Academic Search

This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially when the transistors are velocity saturated and the nodes have a high activity factor, In

Ricardo Gonzalez; Benjamin M. Gordon; Mark A. Horowitz

1997-01-01

283

Low-Power, Highspeed 1M bit CMOS DRAM.  

National Technical Information Service (NTIS)

The paper describes a 1M words X 1 bit CMOS DRAM fabricated with an advanced n-well CMOS technology. More than 2.2 million element devices are integrated on a 62.5 sq mm silicon chip employing an n-channel memory cell of triple-layer polysilicon structure...

S. Fujii S. Saito Y. Matsumoto

1985-01-01

284

Aluminum nitride on titanium for CMOS compatible piezoelectric transducers  

Microsoft Academic Search

Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture

Joseph C. Doll; Bryan C. Petzold; Biju Ninan; Ravi Mullapudi; Beth L. Pruitt

2010-01-01

285

GaAs MQW modulators integrated with silicon CMOS  

Microsoft Academic Search

We demonstrate integration of GaAs-AlGaAs multiple quantum well modulators to silicon CMOS circuitry via flip-chip solder-bonding followed by substrate removal. We obtain 95% device yield for 32×32 arrays of devices with 15 micron solder pads. We show operation of a simple circuit composed of a modulator and a CMOS transistor

K. W. Goossen; J. A. Walker; L. A. D'Asaro; S. P. Hui; B. Tseng; R. Leibenguth; D. Kossives; D. D. Bacon; D. Dahringer; L. M. F. Chirovsky; A. L. Lentine; D. A. B. Miller

1995-01-01

286

Readout architectures for high speed CMOS image sensor  

NASA Astrophysics Data System (ADS)

High speed CMOS image sensors are very widely used in many applications such as machine vision, robotic sensing and scientifically imaging etc. Flexibility in design with CMOS technology allows the invention of various sensor architecture and tricks which can improve the sensor speed. In this paper we discuss several architectures for high speed sensors and their limitations.

Ma, Cheng; Li, Jing; Wang, Xinyang

2013-08-01

287

Process Optimization of Radiation-Hardened CMOS Integrated Circuits  

Microsoft Academic Search

The effects of processing steps on the radiation hardness of MOS devices have been systematically investigated. Quantitative relationships between the radiation-induced voltage shifts and processing parameters have been determined, where possible. Using the results of process optimization, a controlled baseline fabrication process for aluminum-gate CMOS has been defined. CMOS inverters which can survive radiation exposures well in excess of 108

G. F. Derbenwick; B. L. Gregory

1975-01-01

288

Low-Power Strategies for High-Performance CMOS Circuits  

Microsoft Academic Search

Power dissipation has become one of the most critical CMOS design parameters. It will be shown that even under constraints on the supply voltage there are effective strategies for the reduction of power dissipation on the different levels of the CMOS design process. Enforcing localization, using redundant number representations and applying an optimal degree of pipelining will be demonstrated as

Tobias G. Noll; RWTH Aachen Rogowski-Institu

1994-01-01

289

Novel Architectures of Class AB CMOS Mirrors with Programmable Gain  

Microsoft Academic Search

Two schemes for power-efficient gain-programmable V-I conversion based on class AB CMOS mirrors are introduced. The proposed topologies also allow for high-speed gain-programmable precision rectification. Experimental results from a test chip prototype in 0.5-µ m CMOS technology with ±1 V supplies are shown that validate the proposed circuits.

Chandrika Durbha; Jaime Ramírez-Angulo; RAM ´ ON G. CARVAJAL; Antonio J. López-Martín

2005-01-01

290

Two 1-V Fully Differential CMOS Switched-Capacitor Amplifiers  

Microsoft Academic Search

Two 1-V fully differential CMOS switched-capacitor amplifiers in a standard CMOS 0.35-?m technology are presented. The improved\\u000a bootstrapped switches are used to allow rail-to-rail signal swing. The circuit design of the major building blocks is described.\\u000a The performance of these two circuits is demonstrated by experimental results.

Tsung-Sum Lee; Chi-Chang Lu

2010-01-01

291

Simultaneous switching ground noise calculation for packaged CMOS devices  

Microsoft Academic Search

Here, it is assumed that the internal switching current is small compared to the output driver switching current. In the past, it was assumed that simultaneous switching noise created by CMOS outputs was directly proportional to the number of outputs switching simultaneously. Recent studies indicate that CMOS circuits exhibit sublinear behavior (due to the negative feedback influence) of power\\/ground noise

R. Senthinathan; J. L. Prince

1991-01-01

292

CMOS IC fault models, physical defect coverage, and IDDQ testing  

Microsoft Academic Search

The development of the stuck-at fault (SAF) model is reviewed with emphasis on its relationship to CMOS integrated circuit (IC) technologies. The ability of the SAF model to represent common physical defects in CMOS ICs is evaluated. A test strategy for defect detection, which includes IDDQ testing, is presented

Ronald R. Fritzemeier; Charles F. Hawkins; Jerry M. Soden

1991-01-01

293

ESD Phenomena and Protection Issues in CMOS Output Buffers  

Microsoft Academic Search

In VLSI devices with 1 ¿m CMOS technologies the use of silicided diffusions has been found to have a negative impact on the ESD protection levels of both inputs and outputs. In this paper the ESD phenomena for CMOS output buffers is presented to show that it can be improved for advanced processes. The primary findings here show that the

C. Duvvury; R. N. Rountree; Y. Fong; R. A. McPhee

1987-01-01

294

ESD protection for submicron CMOS circuits-issues and solutions  

Microsoft Academic Search

Key issues pertinent to design with advanced CMOS ESD (electrostatic discharge)-protection circuits are discussed. Input protection elements and their limitations with respect to output and power supply applications are examined. The lateral silicon-controlled rectifier has proved to be an effective primary protection element for a wide range of CMOS processes when it is combined with an optimized secondary protection network.

Robert N. Rountree

1988-01-01

295

A CMOS rotary encoder using magnetic sensor arrays  

Microsoft Academic Search

A new type of small magnetic rotary encoder is presented. The device detects the magnetic field of a permanent magnet attached to the end of the rotating shaft using complementary metal-oxide semiconductor (CMOS) magnetic sensors [magnetic field effect transistor (MAGFET) arrays] set in a square arrangement. The sensor array is integrated onto a CMOS chip along with angle-detection circuits, leading

Kazuhiro Nakano; Toru Takahashi; Shoji Kawahito

2005-01-01

296

Fundamental performance differences between CMOS and CCD imagers: part III  

NASA Astrophysics Data System (ADS)

This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff.

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Cheng, John; Bishop, Jeanne

2009-08-01

297

CMOS RAM 1-M Word X 1-Bit/256K-Word X4-Bit CMOS Dynamic RAM.  

National Technical Information Service (NTIS)

A plastic package version of 1-M word x 1 bit/256-K word x 4 bit CMOS dynamic RAMs has been developed by using advanced 1.2-micrometers CMOS fabrication and circuit techniques. These RAMs, being capable of either 1 M x 1 version or 256 K x 4 version, real...

S. Saito Y. Matsumoto S. Matsumoto

1986-01-01

298

CMOS arrays as chemiluminescence detectors on microfluidic devices.  

PubMed

A simple, low-cost process to integrate complementary metal oxide semiconductor array detectors (CMOSAD) for chemiluminescence is presented, evaluated, and applied to the determination of nitrite in ground water samples. CMOS arrays of different brands (obtained from commercial image sensors) were adapted as chemiluminescence detectors on microfluidic devices. The performance of the CMOSADs was evaluated in the visible zone of the spectrum using a tungsten halogen lamp as light source. Intrinsic parameters assessed included signal stability, spectral response, dark current, and signal-to-noise ratio. Thereafter, the CMOSADs were integrated on microfluidic devices and their performances in quantitative analysis were assessed with the chemiluminometric reaction of hydrogen peroxide with luminol, catalyzed with hexacyanoferrate (III). The parameters assessed were sensitivity, linear range, detection limit, reproducibility, correlation coefficient of the calibration curves, and baseline drift during measurements. The CMOSAD with the best performance was selected to assess the applicability of the developed microfluidic devices with the integrated detector. The microfluidic system permitted the determination of nitrite with both good precision and good recovery values in the analysis of ground water samples. Integration was easily achieved and enabled the development of a simple, low-cost, and feasible alternative to conventional detectors. PMID:20177663

Rodrigues, Eunice R G O; Lapa, Rui A S

2010-02-23

299

Cmos-Compatible High Voltage Integrated Circuits.  

NASA Astrophysics Data System (ADS)

Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5 ?m CMOS process are first studied. High -voltage n- and p-channel transistors with breakdown voltages of 50 V and 190 V respectively, have been fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed and their accuracy verified by comparison with the experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS -bipolar concept, is proposed and implemented. The device, which can be implemented using a standard CMOS process, is capable of handling high current densities without latching. The IBT exhibits a fivefold increase in the current density compared to the lateral DMOS transistor. A simple technique to improve the breakdown voltage and the switching speed of the IBT, without significantly compromising its current carrying capability, is also presented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed. High-voltage lateral DMOS transistors and merged MOS-bipolar devices such as the LIGT and IBT with breakdown voltages of 400 V, have been fabricated using this process. The IBTs, which in addition to having high breakdown voltages have high current handling capabilities as well as high switching speeds, offer better performance than the LIGTs. In addition, the IBT, because it doesn't latch-up, is a more reliable device than the LIGT. The processes and devices developed in this work have potential applications in the telecommunications and display driver fields.

Parpia, Zahir

300

Nanoscale Materials and Structures for CMOS Devices  

NSDL National Science Digital Library

This presentation was given at the Arizona Nanotechnology Conference in March of 2008 by Dr. Stefan Zollner, Freescale Semiconductor, USA. The focus is on problems with planar CMOS and their solutions. These solutions consist of: SOI or FINFET to reduce source and drain leakage, high mobility channel materials to increase drive current, new silicide materials to reduce source and drain contact resistance, metal oxides with high dielectric constants to reduce gate leakage and metal gate electrodes to reduce gate depletion. Overall, the presentation is filled with images and diagrams allowing it to flow easily. This is an excellent resource for anyone looking to learn more about nanotechnology and its applications.

Zollner, Stefan

2008-10-27

301

Nanomechanical switch for integration with CMOS logic.  

SciTech Connect

We designed, fabricated and measured the performance of nanoelectromechanical (NEMS) switches. Initial data are reported with one of the switch designs having a measured switching time of 400 ns and an operating voltage of 5 V. The switches operated laterally with unmeasurable leakage current in the 'off' state. Surface micromachining techniques were used to fabricate the switches. All processing was CMOS compatible. A single metal layer, defined by a single mask step, was used as the mechanical switch layer. The details of the modeling, fabrication and testing of the NEMS switches are reported.

Nordquist, Christopher Daniel; Wolfley, Steven L.; Baker, Michael Sean; Czaplewski, David A.; Wendt, Joel Robert; Kraus, Garth Merlin; de Boer, Maarten Pieter; Patrizi, Gary A.

2008-11-01

302

Design of prototype scientific CMOS image sensors  

NASA Astrophysics Data System (ADS)

We present the design and test results of a prototype 4T CMOS image sensor fabricated in 0.18-?m technology featuring 20 different 6.5 ?m pixel pitch designs. We review the measured data which clearly show the impact of the pixel topologies on sensor performance parameters such as conversion gain, read noise, dark current, full well capacity, non-linearity, PRNU, DSNU, image lag, QE and MTF. Read noise of less than 1.5e- rms and peak QE greater than 70%, with microlens, are reported.

Vu, Paul; Fowler, Boyd; Liu, Chiao; Balicki, Janusz; Mims, Steve; Do, Hung; Laxson, Dan

2008-08-01

303

CMOS pH-to-Digital Converter  

Microsoft Academic Search

A CMOS delta-sigma (??) pH-to-digital converter has been developed for continuous monitoring of H+-ion concentrations. The SnO2\\/ITO glass, fabricated sputtering SnO2 on the conductive ITO glass, was used as a pH-sensitive membrane of extended gate field effect transistor (EGFET) operational amplifier. The ?? pH-to-digital converter, constructed by using EGFET-OP to realize switched-capacitor (SC) ?? converter, converted the H+-ion concentration into

Chung-Yuan Chen; Tai-Ping Sun; Hsiu-Li Hsieh

2010-01-01

304

Performance of commercial analog multiplexers for spaceborne applications  

Microsoft Academic Search

Commercial CMOS analog\\/digital processes are considered for spaceborne applications. Total dose hardness of three processes is compared by the testing of analog multiplexers. Parts were irradiated at 18 and 1.8 rad(Si) per sec. The total dose results are then compared with the requirements for a low Earth and a geosynchronous orbital design. Shielding thicknesses for each of the orbital designs

G. K. Lum; D. K. Kinell; R. J. May; L. E. Robinette

1996-01-01

305

A 128×128 CMOS active pixel image sensor for highly integrated imaging systems  

Microsoft Academic Search

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 ?m p-well CMOS process, and consists of a 128×128 array of 40 ?m×40 ?m pixels. The CMOS image

Sunetra K. Mendis; Sabrina E. Kemeny; Eric R. Fossum

1993-01-01

306

A piezoresistive cantilever for lateral force detection fabricated by a monolithic post-CMOS process  

Microsoft Academic Search

This paper presents a post-CMOS process to monolithically integrate a piezoresistive cantilever for lateral force detection and signal processing circuitry. The fabrication process includes a standard CMOS process and one more lithography step to micromachine the cantilever structure in the post-CMOS process. The piezoresistors are doped in the CMOS process but defined in the post-CMOS micromachining process without any extra

Xu Ji; Zhihong Li; Jianzhong Xi; Juan Li; Yangyuan Wang

2008-01-01

307

SEMICONDUCTOR INTEGRATED CIRCUITS: A full on-chip CMOS low-dropout voltage regulator with VCCS compensation  

NASA Astrophysics Data System (ADS)

A full on-chip CMOS low-dropout (LDO) voltage regulator with high PSR is presented. Instead of relying on the zero generated by the load capacitor and its equivalent series resistance, the proposed LDO generates a zero by voltage-controlled current sources for stability. The compensating capacitor for the proposed scheme is only 0.18 pF, which is much smaller than the capacitor of the conventional compensation scheme. The full on-chip LDO was fabricated in commercial 0.35 ?m CMOS technology. The active chip area of the LDO (including the bandgap voltage reference) is 400 × 270 ?m2. Experimental results show that the PSR of the LDO is -58.7 dB at a frequency of 10 Hz and -20 dB at a frequency of 1 MHz. The proposed LDO is capable of sourcing an output current up to 50 mA.

Leisheng, Gao; Yumei, Zhou; Bin, Wu; Jianhua, Jiang

2010-08-01

308

Fault detection in CMOS manufacturing using MBPCA  

NASA Astrophysics Data System (ADS)

This paper describes the application of model-based principal component analysis (MBPCA) to the identification and isolation of faults in CMOS manufacture. Some of the CMOS fabrication processing steps are well understood, with first principles mathematical models available which can describe the physical and chemical phenomena that takes place. The fabrication of the device using a known industrial process is therefore first modeled 'ideally', using ATHENA and MATLAB. Detailed furnace models are used to investigate the effect of errors in furnace control on the device fabrication and the subsequent effect on the device electrical properties. This models the distribution of device properties resulting from processing a stack of wafers in a furnace, and allows faults and production errors to be simulated for analysis. The analysis is performed using MBPCA. which has been shown to improve fault-detection resolution for batch processes. The diagnosis method is demonstrated on an industrial NMOS transistor fabrication process with faults introduced in places where they might realistically occur.

Lachman-Shalem, Sivan; Haimovitch, Nir; Shauly, Eitan N.; Lewin, Daniel R.

2000-08-01

309

Organic CMOS technology by interface treatment  

NASA Astrophysics Data System (ADS)

In the present paper a new concept towards O-CMOS technology is presented substantiating the importance of the semiconductor/dielectric interface for charge carrier transport in organic semiconductors. It will be demonstrated that by controlling the interface properties of either SiO2 or PMMA, unipolar p- and n-type OFETs can be realized using a single organic semiconductor and even a single metal for source and drain contacts. Two dielectric/semiconductor interface modifications are considered for the realization of complementary OFETs on the basis of pentacene, otherwise known for its exclusive hole transporting properties. Selective modification of the SiO2 dielectric interface with traces of vacuum deposited Ca, allows for electron transport in pentacene and the realization of complementary pentacene OFETs on a single substrate. By this technique electron traps are removed due to a reaction of atomic Ca with oxygen from available hydroxide groups, resulting in the formation of an oxidized Ca layer. In a second approach, it is demonstrated that by selective UV treatment of a PMMA dielectric surface, unipolar n-type pentacene OFETs can be converted to unipolar p-type by the introduction of electron traps in the form of -OH and -COOH groups at the PMMA interface. Both methods allow for the realization of CMOS organic inverter stages with decent electrical properties.

Benson, Niels; Ahles, Marcus; Schidleja, Martin; Gassmann, Andrea; Mankel, Eric; Mayer, Thomas; Melzer, Christian; Schmechel, Roland; von Seggern, Heinz

2006-09-01

310

Commercial Fishing.  

ERIC Educational Resources Information Center

|This document is a curriculum framework for a program in commercial fishing to be taught in Florida secondary and postsecondary institutions. This outline covers the major concepts/content of the program, which is designed to prepare students for employment in occupations with titles such as net fishers, pot fishers, line fishers, shrimp boat…

Florida State Dept. of Education, Tallahassee. Div. of Vocational Education.

311

Scaling trends in SET pulse widths in Sub-100 nm bulk CMOS processes.  

SciTech Connect

Digital single-event transient (SET) measurements in a bulk 65-nm process are compared to transients measured in 130-nm and 90-nm processes. The measured SET widths are shorter in a 65-nm test circuit than SETs measured in similar 90-nm and 130-nm circuits, but, when the factors affecting the SET width measurements (in particular pulse broadening and the parasitic bipolar effect) are considered, the actual SET width trends are found to be more complex. The differences in the SET widths between test circuits can be attributed in part to differences in n-well contact area. These results help explain some of the inconsistencies in SET measurements presented by various researchers over the past few years.

Narasimham, Balaji; Ahlbin, Jonathan R.; Schrimpf, Ronald D.; Gadlage, Matthew J.; Massengill, Lloyd W.; Vizkelethy, Gyorgy; Reed, Robert A.; Bhuva, Bharat L.

2010-07-01

312

Series M74HC High-Speed CMOS Logic Devices.  

National Technical Information Service (NTIS)

Mitsubishi Electric plans ultimately to market 140 high-speed CMOS logic devices that retain the low power dissipation and high noise immunity characteristics typical of such devices while achieving speeds comparable with LSTTL devices. As of April 1986, ...

S. Hayami Y. Miyazaki J. Moritani T. Okitaka M. Taniguchi

1986-01-01

313

Complimentary Metal Oxide Semiconductor (CMOS)-Memristor Hybrid Nanoelectronics.  

National Technical Information Service (NTIS)

The goal of this project was to explore CMOS-memristor hybrid nanoelectronic circuits for memory, FPGA, DSP, analog, and neuromorphic applications. The specific tasks of the project included: material selection, integration flow development, circuit desig...

W. Wang

2011-01-01

314

Upset hardened memory design for submicron CMOS technology  

Microsoft Academic Search

A novel design technique is proposed for storage elements which are insensitive to radiation-induced single-event upsets. This technique is suitable for implementation in high density ASICs and static RAMs using submicron CMOS technology

T. Calin; M. Nicolaidis; R. Velazco

1996-01-01

315

A SubMicron BiCMOS Technology for Telecommunications  

Microsoft Academic Search

A high performance, 0.8 ¿m, analog-digital technology is presented. Telecommunication circuit and system diversity has been accommodated by incorporating modular device options into a triple-level-metal BiCMOS process.

R. Hadaway; P. Kempf; P. Schvan; M. Rowlandson; V. Ho; J. Kolk; B. Tait; D. Sutherland; G. Jolly; I. Emesh

1991-01-01

316

A safety monitoring system for taxi based on CMOS imager  

NASA Astrophysics Data System (ADS)

CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

Liu, Zhi

2005-01-01

317

Upset hardened memory design for submicron CMOS technology  

SciTech Connect

A novel design technique is proposed for storage elements which are insensitive to radiation-induced single-event upsets. This technique is suitable for implementation in high density ASICs and static RAMs using submicron CMOS technology.

Calin, T.; Nicolaidis, M. [TIMA/INPG, Grenoble (France); Velazco, R. [LSR/IMAG Lab., Grenoble (France)

1996-12-01

318

A CMOS wireless biomolecular sensing system-on-chip based on polysilicon nanowire technology.  

PubMed

As developments of modern societies, an on-field and personalized diagnosis has become important for disease prevention and proper treatment. To address this need, in this work, a polysilicon nanowire (poly-Si NW) based biosensor system-on-chip (bio-SSoC) is designed and fabricated by a 0.35 ?m 2-Poly-4-Metal (2P4M) complementary metal-oxide-semiconductor (CMOS) process provided by a commercialized semiconductor foundry. Because of the advantages of CMOS system-on-chip (SoC) technologies, the poly-Si NW biosensor is integrated with a chopper differential-difference amplifier (DDA) based analog-front-end (AFE), a successive approximation analog-to-digital converter (SAR ADC), and a microcontroller to have better sensing capabilities than a traditional Si NW discrete measuring system. In addition, an on-off key (OOK) wireless transceiver is also integrated to form a wireless bio-SSoC technology. This is pioneering work to harness the momentum of CMOS integrated technology into emerging bio-diagnosis technologies. This integrated technology is experimentally examined to have a label-free and low-concentration biomolecular detection for both Hepatitis B Virus DNA (10 fM) and cardiac troponin I protein (3.2 pM). Based on this work, the implemented wireless bio-SSoC has demonstrated a good biomolecular sensing characteristic and a potential for low-cost and mobile applications. As a consequence, this developed technology can be a promising candidate for on-field and personalized applications in biomedical diagnosis. PMID:24080725

Huang, Che-Wei; Huang, Yu-Jie; Yen, Pei-Wen; Tsai, Hann-Huei; Liao, Hsin-Hao; Juang, Ying-Zong; Lu, Shey-Shi; Lin, Chih-Ting

2013-10-15

319

256 x 256 CMOS active pixel image sensor  

Microsoft Academic Search

A 256 X 256 CMOS photo-gate active pixel image sensor is presented. The image sensor uses four MOS transistors within each pixel to buffer the photo-signal, enhance sensitivity, and suppress noise. The pixel size is 20 micrometers X 20 micrometers and was implemented in a standard digital 0.9 micrometers single-polysilicon, double-metal, n-well CMOS process; leading to 25% fill-factor. Row and

El-Sayed I. Eid; Alex G. Dickinson; Dave A. Inglis; Brian D. Ackland; Eric R. Fossum

1995-01-01

320

Power dissipated by CMOS gates driving lossless transmission lines  

Microsoft Academic Search

The dynamic and short-circuit power consumption of a CMOS gate driving an LC transmission line as a limiting case of an RLC transmission line is investigated in this paper. Closed form solutions for the output voltage and short-circuit power of a CMOS gate driving an LC transmission line are presented. These solutions agree with AS\\/X simulations within 11% error for

Yehea I. Ismail; Eby G. Friedman; José Luis Neves

1998-01-01

321

Quantified Temperature Effect in a CMOS Image Sensor  

Microsoft Academic Search

In recent years, CMOS image sensors (CISs) have increasingly become major players in the solid-state imaging market, a market in which charge-coupled device image sensors were once the dominant product. Exceptional circuit integration capability makes CMOS imagers suitable for implementation in a single-chip imaging system while inducing the temperature variation of an image sensor. In this paper, global and local

Dong-Long Lin; Ching-Chun Wang; Chia-Ling Wei

2010-01-01

322

Designing 1-V op amps using standard digital CMOS technology  

Microsoft Academic Search

This paper addresses the difficulty of designing 1-V capable analog circuits in standard digital complementary metal-oxide-semiconductor (CMOS) technology, Design techniques for facilitating 1-V operation are discussed and 1-V analog building block circuits are presented. Most of these circuits use the bulk-driving technique to circumvent the metal-oxide-semiconductor field-effect transistor turn-on (threshold) voltage requirement. Finally, techniques are combined within a 1-V CMOS

Benjamin J. Blalock; Phillip E. Allen; Gabriel A. Rincon-Mora

1998-01-01

323

A Floating-Gate-Based Programmable CMOS Reference  

Microsoft Academic Search

We describe a compact programmable CMOS reference, where the reference is determined by the charge difference between two floating-gate transistors, thereby making the reference insensitive to temperature and other environmental effects. Using floating-gate transistors adds programmability making a wide range of reference voltages possible with negligible long-term drift. A prototype circuit has been implemented in a 0.35-mum CMOS process, and

Venkatesh Srinivasan; Guillermo Serrano; Christopher M. Twigg; Paul Hasler

2008-01-01

324

Frame-transfer CMOS active pixel sensor with pixel binning  

Microsoft Academic Search

The first frame-transfer CMOS active pixel sensor (APS) is reported. The sensor architecture integrates an array of active pixels with an array of passive memory cells. Charge integration amplifer-based readout of the memory cells permits binning of pixels for variable resolution imaging. A 32×32 element prototype sensor with 24-?m pixel pitch was fabricated in 1.2-?m CMOS and demonstrated

Zhimin Zhou; Bedabrata Pain; Eric R. Fossum

1997-01-01

325

CMOS image sensor using a floating diffusion driving buried photodiode  

Microsoft Academic Search

Two 2.5V VGA CMOS image sensors with 3.45?m and 3.1?m buried photodiode-pixels on a 0.25?m 2P3M CMOS technology are described. The test chips utilize a floating diffusion driving technique to achieve 3-transistors\\/pixel and 2-transistors\\/pixel respectively, and operate at 60 frames\\/s with 49mW dissipation.

Keiji Mabuchi; Nobuo Nakamura; Eiichi Funatsu; Takashi Abe; Tomoyuki Umeda; Tetsuro Hoshino; Ryoji Suzuki; Hirofumi Sumi

2004-01-01

326

A CMOS image sensor for high-speed imaging  

Microsoft Academic Search

Acquisition of the images of fast-moving objects requires imagers with high photoresponsivity at short integration times, synchronous exposure, and high-speed parallel readout. Previous CMOS implementations yield frame rates around 500 frames\\/s at integration times ranging from 75 to 200 ps, and some use rolling shutter only. This CMOS imager achieves more than 1000 frames\\/s with integration time in synchronous exposure

Nenad Stevanovic; Mathias Hillebrand; Bedrich J. Hosticka; Andreas Teuner

2000-01-01

327

Nano-CMOS Technology for Next Fifteen Years  

Microsoft Academic Search

Complementary metal-oxide-semiconductor (CMOS) technology has been developed into the sub-100 nm range. It is expected that the nano-CMOS technology will govern the IC manufacturing for at least another couple of decades. Though there are many challenges ahead, further down-sizing the device to a few nanometers is still on the schedule of International Technology Roadmap for Semiconductors (ITRS). Several technological options

H. Iwai; H. Wong

2006-01-01

328

CMOS IC reliability indicators and burn-in economics  

Microsoft Academic Search

Sensitive IDDQ and LVMF (low VDD, maximum frequency) tests were done to examine reliability indicators and burn-in economics for CMOS ICs. These experiments used 3,495 CMOS 1 Mb SRAMs for special IDDQ tests, LVMF tests, burn-in and life tests, and failure analysis. IDDQ was measured at the maximum VDD tolerated by the IC, ranging from 40% to 60% above the

Alan W. Righter; Charles F. Hawkins; Jerry M. Soden; Peter C. Maxwell

1998-01-01

329

CMOS High Power SPDT Switch using Multigate Structure  

Microsoft Academic Search

A novel CMOS high power RF switch using the multi-gate structure in a 0.18-mum triple-well CMOS process is designed, implemented, and characterized. The receive switch incorporates the multi-gate structure in order to provide high power handling capability to the transmit switch side. In addition, the RF switch with the multi-gate structure reduces insertion loss more than the one with the

Minsik Ahn; Chang-ho Lee; Joy Laskar

2007-01-01

330

Electrical properties and detection methods for CMOS IC defects  

Microsoft Academic Search

CMOS failure modes and mechanisms and the test vector and parametric test requirements for the detection are reviewed. The CMOS stuck-open fault is discussed from a physical viewpoint, with results given from failure analysis of ICs having this failure mode. The results show that among functional, stuck-at, stuck-open, and IDDQ test strategies, no single method guarantees detection of all types

Jerry M. Soden; Charles F. Hawkins

1989-01-01

331

A study of phase noise in CMOS oscillators  

Microsoft Academic Search

This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis of a linear oscillatory system leads to a noise shaping function and a new definition of Q. A linear model of CMOS ring oscillators is used to calculate their phase noise, and three phase noise phenomena, namely, additive noise, high-frequency multiplicative noise, and low-frequency multiplicative

Behzad Razavi

1996-01-01

332

OLED-on-CMOS integration for optoelectronic sensor applications  

Microsoft Academic Search

Highly-efficient, low-voltage organic light emitting diodes (OLEDs) are well suitable for post-processing integration onto the top metal layer of CMOS devices. This has been proven for OLED microdisplays so far. Moreover, OLEDon- CMOS technology may also be excellently suitable for various optoelectronic sensor applications by combining highly efficient emitters, use of low-cost materials and cost-effective manufacturing together with silicon-inherent photodetectors

Uwe Vogel; Daniel Kreye; Sven Reckziegel; Michael Toerker; Christiane Grillberger; Jörg Amelung

2007-01-01

333

OLED-on-CMOS integration for optoelectronic sensor applications  

NASA Astrophysics Data System (ADS)

Highly-efficient, low-voltage organic light emitting diodes (OLEDs) are well suitable for post-processing integration onto the top metal layer of CMOS devices. This has been proven for OLED microdisplays so far. Moreover, OLEDon- CMOS technology may also be excellently suitable for various optoelectronic sensor applications by combining highly efficient emitters, use of low-cost materials and cost-effective manufacturing together with silicon-inherent photodetectors and CMOS circuitry. The use of OLEDs on CMOS substrates requires a top-emitting, low-voltage and highly efficient OLED structure. By reducing the operating voltage for the OLED below 5V, the costs for the CMOS process can be reduced, because a process without high-voltage option can be used. Red, orange, white, green and blue OLED-stacks with doped charge transport layers were prepared on different dualmetal layer CMOS test substrates without active transistor area. Afterwards, the different devices were measured and compared with respect to their performance (current, luminance, voltage, luminance dependence on viewing angle, optical outcoupling etc.). Low operating voltages of 2.4V at 100cd/m2 for the red p-i-n type phosphorescent emitting OLED stack, 2.5V at 100cd/m2 for the orange phosphorescent emitting OLED stack and 3.2V at 100cd/m2 for the white fluorescent emitting OLED have been achieved here. Therefore, those OLED stacks are suitable for use in a CMOS process even within a regular 5V process option. Moreover, the operating voltage achieved so far is expected to be reduced further when using different top electrode materials. Integrating such OLEDs on a CMOS-substrate provide a preferable choice for silicon-based optical microsystems targeted towards optoelectronic sensor applications, as there are integrated light barriers, optocouplers, or lab-onchip devices.

Vogel, Uwe; Kreye, Daniel; Reckziegel, Sven; Toerker, Michael; Grillberger, Christiane; Amelung, Jörg

2007-03-01

334

A fully-integrated CMOS-MEMS audio microphone  

Microsoft Academic Search

We report on the construction of a microphone and associated electronics fabricated entirely within a standard CMOS (complementary metal oxide semiconductor) die. An A-weighted noise level of 46 dB SPL was achieved with a total diaphragm area of 0.61 mm2. Because the microphone uses the same processing sequence as CMOS-MEMS (microelectromechanical systems) microspeakers it is now possible to create acoustic

K. J. Gabriel

2003-01-01

335

Material choice for optimum stress memorization in SOI CMOS processes  

Microsoft Academic Search

Stress engineering has become the sine qua non of any advanced CMOS technology since the 90nm technology node. In this paper, we focus on the influence of material properties and anneal sequences on the benefit of the stress-memorization technique for SOI CMOS transistors. We distinguish between low- and high-temperature stress memorization. Film hardness, stress level, and the order of anneals

A. Gehring; A. Mowry; A. Wei; M. Wiatr; R. Boschke; P. Javorka; B. Mulfinger; C. Scott; M. Lenski; G. Koerner; K. Huy; R. Otterbach; J. Klais; H. Geisler; T. Mantei; D. Greenlaw; M. Horstmann

2007-01-01

336

W-band pulsed radar receiver in low cost CMOS  

Microsoft Academic Search

A CMOS heterodyne receiver integrating a phase-locked loop that includes a bulk of transmitter functions for W-band pulsed radar is realized using low leakage transistors of a low cost 65-nm bulk CMOS process with 5 thin and 1 thick metal layers used to manufacture cell phone RFIC's. The peak conversion gain of receiver is 7 dB and the minimum NF

Ning Zhang; K. O. Kenneth

2010-01-01

337

CMOS implementation of an analogically programmable cellular neural network  

Microsoft Academic Search

The criteria for designing the basic building blocks of an analogically programmable cellular neural network (CNN) in a 1.5-?m CMOS technology are reported. The simulated electrical performances of a 10×10 CMOS CNN, consisting of about 8000 MOS transistors, are presented and discussed. It is shown that the designed CNN can be successfully used to perform such useful functions as noise

G. F. Dalla Betta; S. Graffi; Z. M. Kovacs; G. Masetti

1993-01-01

338

Wideband VGAs Using a CMOS Transconductor in Triode region  

Microsoft Academic Search

Wideband variable gain amplifiers (VGAs) fabricated using 0.18 mum CMOS process are presented. A scheme with a CMOS triode transconductor is proposed to achieve linear-in-dB characteristics of VGAs for ultra wideband (UWB) systems. The implemented transmitter (TX) VGA shows a highly linear gain range of 28.4 dB (7 dB to -21.4 dB) and a bandwidth of 1200 MHz, while drawing

Hui Dong Lee; Kyung Ai Lee; Songcheol Hong

2006-01-01

339

A Direct Digital Frequency Synthesizer with CMOS OTP ROM§  

Microsoft Academic Search

A direct digital frequency synthesizer (DDFS) using on-chip CMOS one-time programmable read-only memory (OTP ROM) are presented. A straight-line approximation algorithm for sinusoid with compensation is adopted such that the accuracy could be maintained and the cost is reduced. Most important of all, a CMOS OTP ROM is employed as a look-up ROM table to simplify the ROM fabrication without

Chi-Chun Huang; Guo-Lin Jhuang; Chua-Chin Wang

2007-01-01

340

CMOS magnetic sensor integrated circuit with sectorial MAGFET  

Microsoft Academic Search

In this paper, a CMOS magnetic sensor integrated circuit (IC) for a perpendicular magnetic field is introduced. The sensor integrated circuit is designed and fabricated in a 0.6?m digital CMOS process. It consists of a pair of common-source split-drain magnetic field-effect transistor (MAGFET), a pre-processing circuit with a switches array, a correlated double sampling (CDS) circuit and a digital controlling

Guo Qing; Zhu Dazhong; Yao Yunruo

2006-01-01

341

High sensitivity vertical Hall sensor integrated with SOI CMOS  

Microsoft Academic Search

We present the design and performance of the gated vertical Hall sensor integrated with silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) integrated circuits. We demonstrated almost a factor of ten improvement in sensitivity over the comparable vertical Hall sensor integrated on bulk CMOS i.e. constant voltage and constant current sensitivity of 1200 V\\/V*T versus 130 V\\/V*T and 200mV\\/A*T

A. Peczalski; D. Berndt; D. Sandquist

2003-01-01

342

CMOS varactors in NLTL pulse-compression applications  

Microsoft Academic Search

This paper discusses the feasibility of using CMOS varactors in designing all-silicon pulse-compression nonlinear transmission lines (NLTLs). Six different varactor structures based on CMOS transistors are investigated, and are divided into two groups. One group, with a monotonic C(I) characteristic, can be used in single-edge pulse-compression NLTLs, while the other, having a non-monotonic C(I), is suited for double-edge pulse-compression. After

Ming Li; Robert G. Harrison; Rony E. Amaya; Jean-Marc Duchamp; Philippe Ferrari; N. Garry Tarr

2007-01-01

343

CMOS varactors in NLTL pulse-compression applications  

Microsoft Academic Search

This paper discusses the feasibility of using CMOS varactors in designing all-silicon pulse-compression nonlinear transmission lines (NLTLs). Six different varactor structures based on CMOS transistors are investigated, and are divided into two groups. One group, with a monotonic C(V) characteristic, can be used in single-edge pulse-compression NLTLs, while the other, having a non-monotonic C(V), is suited for double-edge pulse-compression. After

Ming Li; Robert G. Harrison; Rony E. Amaya; Jean-Marc Duchamp; Philippe Ferrari; N. Garry Tarr

2007-01-01

344

A CMOS smart rotary encoder using magnetic sensor arrays  

Microsoft Academic Search

This paper presents a new concept of small magnetic rotary encoders. The magnetic field induced by a rotatable magnet is detected by integrated CMOS magnetic sensors (MAGFETs) arranged in a square form. This magnetic sensor array is integrated on a CMOS chip with angle detection circuits, leading to the realization of a small-size and cost-effective rotary encoder. Commonly-used magnetic encoders

Kazuhiro Nakano; Toru Takahashi; Shoji Kawahito

2003-01-01

345

CMOS image sensor with contour enhancement  

NASA Astrophysics Data System (ADS)

Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5?m DPTM CMOS process.

Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

2010-05-01

346

Modeling and simulation of TDI CMOS image sensors  

NASA Astrophysics Data System (ADS)

In this paper, a mathematical model of TDI CMOS image sensors was established in behavioral level through MATLAB based on the principle of a TDI CMOS image sensor using temporal oversampling rolling shutter in the along-track direction. The geometric perspective and light energy transmission relationships between the scene and the image on the sensor are included in the proposed model. A graphical user interface (GUI) of the model was also established. A high resolution satellitic picture was used to model the virtual scene being photographed. The effectiveness of the proposed model was verified by computer simulations based on the satellitic picture. In order to guide the design of TDI CMOS image sensors, the impacts of some parameters of TDI CMOS image sensors including pixel pitch, pixel photosensitive size, and integration time on the performance of the sensors were researched through the proposed model. The impacts of the above parameters on the sensors were quantified by sensor's modulation transfer function (MTF) of the along-track direction, which was calculated by slanted-edge method. The simulation results indicated that the TDI CMOS image sensor can get a better performance with smaller pixel photosensitive size and shorter integration time. The proposed model is useful in the process of researching and developing a TDI CMOS image sensor.

Nie, Kai-ming; Yao, Su-ying; Xu, Jiang-tao; Gao, Jing

2013-09-01

347

Totally self-checking circuits and testable CMOS circuits  

NASA Astrophysics Data System (ADS)

A Totally Self-Checking (TSC) circuit belongs to a class of circuits used for Concurrent Error Detection (CED) purposes. It consists of a functional circuit that has encoded inputs and outputs and a checker that monitors these outputs and gives and error indication. It is known that the traditional stuck-at fault model is not sufficient to model realistic physical failures. Techniques for implementing existing gate-level TSC circuits in CMOS, Domino-CMOS and standard CMOS technologies, so that they are TSC with respect to physical failures, are described. Design methods which reduce the transistor count, delay, and the number of tests of TSC checkers are also given. Another problem in the area of TSC circuits concerns embedded checkers whose inputs are not directly controllable. If they do not get all the required codewords to test them they cannot be guaranteed to be TSC. A new encoding technique and a design procedure to solve this problem are presented. It has been shown previously that the two-pattern tests used to test CMOS circuits can be invalidated by timing skews. A necessary and sufficient condition is derived to find out whether or not an AND-OR or and OR-AND CMOS realization exists for a given function so that a valid test set can always be found, even in the presence of arbitrary timing skews. A new Hybrid CMOS realization is introduced to take care of the cases in which this is not possible.

Jha, N. K.

1986-06-01

348

Advancement of CMOS Doping Technology in an External Development Framework  

NASA Astrophysics Data System (ADS)

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

349

CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) Circuit Design for Nanosecond Quantum-Bit Read-out  

Microsoft Academic Search

Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling

Thomas M. Gurrieri; Malcolm S. Carroll; Michael P. Lilly; James E. Levy

2008-01-01

350

Design of a K-Band Chip Filter With Three Tunable Transmission Zeros Using a Standard 0.13- CMOS Technology  

Microsoft Academic Search

A novel bandpass filter (BPF), which is fabricated with a commercial CMOS process, demonstrating a low insertion loss in the passband and multiple transmission zeros in stopbands, is presented for 24-GHz automotive ultrawideband (UWB) radar systems. The filter combines a second-order asymmetrically compact resonator filter with a source-load coupling mechanism to realize three transmission zeros; two zeros are arranged in

Chin-Lung Yang; Shin-Yi Shu; Yi-Chyun Chiang

2010-01-01

351

Total ionizing dose radiation hardness of the ATLAS MDT-ASD and the HP-Agilent 0.5 m CMOS process  

Microsoft Academic Search

A total ionizing dose (TID) test of the MDT-ASD, the ATLAS MDT front-end chip (12)(13) has been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5 m CMOS process (AMOS14TB). The accumulated TID at the end of the test was 300 krad, delivered by 160 MeV protons at a

C. Posch; E. Hazen

2002-01-01

352

Characterization of SOS-CMOS FETs at Low Temperatures for the Design of Integrated Circuits for Quantum Bit Control and Readout  

Microsoft Academic Search

We have assessed the use of commercial silicon-on-sapphire CMOS electronics in control circuits, which could be used to interface with quantum bits at low temperatures. We have characterized n-type MOSFETs, p-type MOSFETs, and an n+-diffusion resistor at 300 K and 4.2 K and extended these studies into the millikelvin regime. Our measurements of dc responses at 300 K, 4.2 K,

S. Ramesh Ekanayake; Torsten Lehmann; Andrew S. Dzurak; Robert G. Clark; Andrew Brawley

2010-01-01

353

77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...  

Federal Register 2010, 2011, 2012, 2013

...TRADE COMMISSION [Investigation No. 337-TA-846] Certain CMOS Image Sensors and Products Containing Same; Investigations...the sale within the United States after importation of certain CMOS image sensors and products containing the same based on...

2012-12-14

354

Monolithic integration of 5 V CMOS and high-voltage devices  

Microsoft Academic Search

A fully CMOS-compatible HVIC technology has been developed that features 5 V high-performance digital CMOS with high-voltage devices of more than 400 V. This technology uses only one or two masks in addition to standard p-well CMOS technology. Design optimization has been achieved to meet the needs of both CMOS and high-voltage devices. A large number of different devices are

Qin Huang; Gehan A. J. Amaratunga; Jean Humphrey; E. M. S. Narayanan; W. I. Milne; C. M. Starbuck

1992-01-01

355

A high performance, low complexity 14V Complementary BiCMOS process built on bulk silicon  

Microsoft Academic Search

This paper details a new 14V Complementary BiCMOS (CBiCMOS) addition to the TowerJazz SBC35 family of BiCMOS technologies. The SBC35 family previously supported BVceo values up to 6V. The bipolar architecture is nearly identical with that used in the lower voltage technologies, leveraging 10 years of manufacturing history. The complementary bipolar transistors are paired with 5V CMOS currently available in

Todd Thibeault; Edward Preisler; Jie Zheng; Lynn Lao; Paul Hurwitz; Marco Racanelli

2010-01-01

356

Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano\\/CMOS Circuit Design  

Microsoft Academic Search

Hybrid Nano (e.g. Nanotube and Nanowire) \\/CMOS circuits combine both the advantages of Nano-devices and CMOS technologies;\\u000a they have thus become the most promising candidates to relax the intrinsic drawbacks of CMOS circuits beyond Moore’s law.\\u000a A functional simulation model for an hybrid Nano\\/CMOS design is presented in this paper. It is based on Optically Gated Carbon\\u000a NanoTube Field Effect

Weisheng Zhao; Guillaume Agnus; Vincent Derycke; Ariana Filoramo; Christian Gamrat; Jean-Philippe Bourgoin

2009-01-01

357

Circuit techniques for CMOS low-power high-performance multipliers  

Microsoft Academic Search

In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-?m CMOS (in BiCMOS) technology. The complementary pass-transistor logic-transmission gate (CPL-TG) full adder implementation provided an energy savings of 50% compared to the conventional CMOS full adder. CPL implementation of the Booth encoder provided 30% power savings at

Issam S. Abu-Khater; Abdellatif Bellaouar; M. I. Elmasry

1996-01-01

358

Low-noise Imaging System with CMOS Sensor for High-Quality Imaging  

Microsoft Academic Search

Image sensors are widely used in the high-volume markets of digital still cameras and camcorders. In recent years, mobile phones with cameras have employed CMOS image sensors because of their low power consumption and single power supply. Initially, CMOS image sensors were inexpensive and provided poor imaging performance. However, more recently, some CMOS image sensors have achieved high-quality imaging performance

Hirofumi Sumi

2006-01-01

359

Design of real-time image enhancement preprocessor for CMOS image sensor  

Microsoft Academic Search

This paper presents a design of the real-time digital image enhancement preprocessor for a CMOS image sensor. The CMOS image sensor offers various advantages while it provides lower-quality images than the CCD does. In order to compensate for the physical limitation of the CMOS sensor, a spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma

Yun Ho Jung; Jae Seok Kim; Bong Soo Hur; Moon Gi Kang

2000-01-01

360

A study of the threshold voltage variation for ultra-small bulk and SOI CMOS  

Microsoft Academic Search

This paper addresses the scalability of bulk CMOS, and the feasibility of intrinsic channel SOI (IC-SOI) CMOS, as an alternative to the bulk, in view of the threshold voltage (VTH) fluctuations. The impact of dopant-induced VTH variations on bulk CMOS SRAM operation is evaluated using a newly proposed analytical method. It is estimated that the bulk SRAM performance will be

Kiyoshi Takeuchi; Risho Koh; Tohru Mogami

2001-01-01

361

An 8×8 CMOS microelectrode array for electrochemical dopamine detection  

Microsoft Academic Search

This work presents the design and characterization of an integrated CMOS (complementary metal oxide semiconductor) electrochemical sensor array for dopamine (DA) detection. The chip is intended to provide as a platform for high- throughput measurement of neurotransmitter release during exocytosis. Interdigitated gold microelectrodes with a 5-Pm gap are fabricated on CMOS chips by a post-CMOS lithographic process. A buffer with

Po-Hung Yang; Michael S.-C. Lu

2011-01-01

362

A 12 mW wide dynamic range CMOS front end for a portable GPS receiver  

Microsoft Academic Search

At submicron channel lengths, CMOS is an attractive alternative to silicon bipolar and GaAs MESFET technologies for use in wireless receivers. A 12mW Global Positioning System (GPS) receiver front-end, comprising a low noise amplifier (LNA) and mixer implemented in a standard 0.35?m digital CMOS process, demonstrates the aptitude of CMOS for portable wireless applications

A. R. Shahani; D. K. Shaeffer; T. H. Lee

1997-01-01

363

CMOS cell sensors for point-of-care diagnostics.  

PubMed

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

Adiguzel, Yekbun; Kulah, Haluk

2012-07-25

364

CMOS Cell Sensors for Point-of-Care Diagnostics  

PubMed Central

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies.

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

365

High-speed CMOS optical communication using silicon light emitters  

NASA Astrophysics Data System (ADS)

The idea of moving CMOS into the mainstream optical domain remains an attractive one. In this paper we discuss our recent advances towards a complete silicon optical communication solution. We prove that transmission of baseband data at multiples of megabits per second rates are possible using improved silicon light sources in a completely native standard CMOS process with no post processing. The CMOS die is aligned to a fiber end and the light sources are directly modulated. An optical signal is generated and transmitted to a silicon Avalanche Photodiode (APD) module, received and recovered. Signal detectability is proven through eye diagram measurements. The results show an improvement of more than tenfold over our previous results, also demonstrating the fastest optical communication from standard CMOS light sources. This paper presents an all silicon optical data link capable of 2 Mb/s at a bit error rate of 10-10, or alternatively 1 Mb/s at a bit error rate of 10-14. As the devices are not operating at their intrinsic switching speed limit, we believe that even higher transmission rates are possible with complete integration of all components in CMOS.

Goosen, Marius E.; Venter, Petrus J.; Du Plessis, Monuko; Nell, Ilse J.; Bogalecki, Alfons W.; Rademeyer, Pieter

2011-02-01

366

VLSI scaling methods and low power CMOS buffer circuit  

NASA Astrophysics Data System (ADS)

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.

Sharma, Vijay Kumar; Pattanaik, Manisha

2013-09-01

367

CMOS Conductometric System for Growth Monitoring and Sensing of Bacteria.  

PubMed

We present the design and implementation of a prototype complementary metal-oxide semiconductor (CMOS) conductometric integrated circuit (IC) for colony growth monitoring and specific sensing of Escherichia coli (E. coli) bacteria. The detection of E. coli is done by employing T4 bacteriophages as receptor organisms. The conductometric system operates by measuring the resistance of the test sample between the electrodes of a two-electrode electrochemical system (reference electrode and working electrode). The CMOS IC is fabricated in a TSMC 0.35-?m process and uses a current-to-frequency (I to F) conversion circuit to convert the test sample resistance into a digital output modulated in frequency. Pulsewidth control (one-shot circuit) is implemented on-chip to control the pulsewidth of the output digital signal. The novelty in the current work lies in the ability of the CMOS sensor system to monitor very low initial concentrations of bacteria (4×10(2) to 4×10(4) colony forming unit (CFU)/mL). The CMOS system is also used to record the interaction between E. coli and its specific receptor T4 bacteriophage. The prototype CMOS IC consumes an average power of 1.85 mW with a 3.3-V dc power supply. PMID:23851473

Lei Yao; Lamarche, P; Tawil, N; Khan, R; Aliakbar, A M; Hassan, M H; Chodavarapu, V P; Mandeville, R

2011-06-01

368

Feasibility study of CMOS detectors for mammography  

NASA Astrophysics Data System (ADS)

We investigated the potential use of CMOS (complementary metal-oxide-semiconductor) imaging detectors with a pixel pitch of 48 ?m for mammography. Fundamental imaging characteristics were evaluated in terms of modulation-transfer function (MTF), noise-power spectrum (NPS), and detective quantum efficiency (DQE). The magnitudes of various image noise sources, such as optical photons, direct x rays unattenuated and scattered x rays from the scintillator, and additive electronic noise, were measured and analyzed. For the analysis of the measurement results, we applied a model describing the signal and noise transfer based on the cascaded linear-systems approach. The direct x-ray was very harmful to the detector noise performance with white noise characteristics in the spatial frequency domain, and which significantly degraded the spatial-frequency-dependent DQE at higher frequencies. Although the use of a fiber-optic plate (FOP) reduces the detector sensitivity and the MTF performance, it enhances the DQE performance by preventing the direct x-ray photons from the absorption within the photodiode array.

Han, Jong Chul; Yun, Seungman; Lim, Chang Hwy; Kim, Tae Woo; Kim, Ho Kyung

2009-02-01

369

Commercial applications  

NASA Astrophysics Data System (ADS)

The near term (one to five year) needs of domestic and foreign commercial suppliers of radiochemicals and radiopharmaceuticals for electromagnetically separated stable isotopes are assessed. Only isotopes purchased to make products for sale and profit are considered. Radiopharmaceuticals produced from enriched stable isotopes supplied by the Calutron facility at ORNL are used in about 600,000 medical procedures each year in the United States. A temporary or permanent disruption of the supply of stable isotopes to the domestic radiopharmaceutical industry could curtail, if not eliminate, the use of such diagnostic procedures as the thallium heart scan, the gallium cancer scan, the gallium abscess scan, and the low radiation dose thyroid scan. An alternative source of enriched stable isotopes exist in the USSR. Alternative starting materials could, in theory, eventually be developed for both the thallium and gallium scans. The development of a new technology for these purposes, however, would take at least five years and would be expensive. Hence, any disruption of the supply of enriched isotopes from ORNL and the resulting unavailability of critical nuclear medicine procedures would have a dramatic negative effect on the level of health care in the United States.

370

A New CMOS Posicast Pre-shaper for Vibration Reduction of CMOS Op-Amps  

NASA Astrophysics Data System (ADS)

Posicast-based control is a widely used method in vibration reduction of lightly damped oscillatory systems especially in mechanical fields. The target systems to apply Posicast method are the systems which are excited by pulse inputs. Using the Posicast idea, the input pulse is reshaped into a new pulse, which is called Posicast pulse. Applying the generated Posicast pulse reduces the undesired oscillatory manner of under-test systems. In this paper, a fully CMOS Pulse pre-shaper circuit for realization of Posicast command is proposed. Our design is based on delay-and-add approach for the incoming pulses. The delay is done via a modified Schmitt Trigger-like circuit. The adder circuit is implemented by a simple non-binary analog adder terminated by a passive element. Our proposed design has a reasonable flexibility in configuration of time delay and amplitude of the desired pulse-like shapes. The delay is controlled via the delay unit and the pre-shaped pulse's amplitudes are controlled by an analog adder unit. The overall system has 18 MOS transistors, one small capacitor, and one resistor. To verify the effectiveness of the recommended method, it is experienced on a real CMOS Op-Amp. HSPICE simulation results, on 0.25u technology, show a significant reduction on overshoot and settling time of the under-test Op-Amp. The mentioned reduction is more than 95% in overshoot and more than 60% in settling time of the system.

Rasoulzadeh, M.; Ghaznavi-Ghoushchi, M. B.

2010-06-01

371

Fabrication of the planar angular rotator using the CMOS process  

NASA Astrophysics Data System (ADS)

In this investigation we propose a novel planar angular rotator fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. Following the 0.6 ?m single poly triple metal (SPTM) CMOS process, the device is completed by a simple maskless, post-process etching step. The rotor of the planar angular rotator rotates around its geometric center with electrostatic actuation. The proposed design adopts an intelligent mechanism including the slider-crank system to permit simultaneous motion. The CMOS planar angular rotator could be driven with driving voltages of around 40 V. The design proposed here has a shorter response time and longer life, without problems of friction and wear, compared to the more common planar angular micromotor.

Dai, Ching-Liang; Chang, Chien-Liu; Chen, Hung-Lin; Chang, Pei-Zen

2002-05-01

372

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.  

PubMed

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices. PMID:19722537

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

373

Operation and biasing for single device equivalent to CMOS  

SciTech Connect

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

2001-01-01

374

A hybrid CMOS-microfluidic contact imaging microsystem  

NASA Astrophysics Data System (ADS)

A hybrid CMOS/Microfluidic microsystem is presented. The microsystem integrates a soft polymer microfluidic network with a 64x128 pixel imager fabricated in low-cost standard 0.35 micron CMOS technology. The multiple microfluidic channels facilitate in-situ photochemical reactions of analytes and their detection directly on the surface of the CMOS photosensor array. The promixity between the analyte and the photosensor enhances the microsystem sensitivity, thus requiring only microliter volumes of the sample. Circuit techniques such as pixel binning and a two transistor reset path technique are employed to improve the imager sensitivity. The integrated microsystem is validated in on-chip chemiluminescence detection of luminol for the two microfluidic network prototypes designed.

Singh, Ritu Raj; Leng, Lian; Guenther, Axel; Genov, Roman

2009-08-01

375

Micro-image processing system based on CMOS sensor  

NASA Astrophysics Data System (ADS)

A CMOS IS (image sensor) has been widely applied in the multimedia field due to its unique features. One application of the CMOS IS is the microimage processing field is presented. An electronic eyepiece, mainly incorporating optical lens and a CMOS IS, is developed to digitize an optical image, process the digital signals and transmit them to a processor (i.e. computer). The digitized images are displayed in real time and stored off-line for post-mission analysis. An algorithm to process the image is adopted to extract features after the preprocessing operation. In this paper we will describe the system, introduce the structure of eyepiece and discuss the preprocessing technique. Finally some results of feature extraction are given. The system has been applied in the microimage processing field and the availability has been verified.

Xu, Xiangdong; Li, Feng; Zeng, Chao; Zheng, Xianbing

2002-09-01

376

A CMOS image sensor method of focal spot size measurement.  

PubMed

A phosphor opto-coupled monochrome CMOS image sensor with a slit diaphragm was used to investigate focal spot characteristics. Images were captured during x-ray exposure with a triggered frame grabber and subsequently enhanced. Dimensions of the focal spot width (1.39mm) and length (1.92mm) were determined from the focal spot intensity profiles and their corresponding Full Width at Half Maxima (FWHM) in two orthogonal orientations. The CMOS image sensor measurements demonstrated differences in the measured width and length dimensions when compared to film measurements. The obtained nominal focal spot values however showed that image-sensor determined focal spot dimensions agreed with the direct film and film-screen methods when based on the AS/NZS defined nominal focal spot values. The CMOS image sensor tested appears to lack the measurement accuracy required for the measurement of small focal spot sizes due in part to its limited camera sensitivity. PMID:15462588

Tuchyna, T; Paix, D

2004-06-01

377

Radiation hardness by design for mixed signal infrared readout circuit applications  

NASA Astrophysics Data System (ADS)

Readout integrated circuits (ROICs) to support space-based infrared detection applications often have severe radiation tolerance requirements. Radiation hardness-by-design (RHBD) significantly enhances the radiation tolerance of commercially available CMOS and custom radiation hardened fabrication techniques are not required. The combination of application specific design techniques, enclosed gate architecture nFETs and intrinsic thin oxide radiation hardness of 180 nm process node commercial CMOS allows realization of high performance mixed signal circuits. Black Forest Engineering has used RHBD techniques to develop ROICs with integrated A/D conversion that operate over a wide range of temperatures (40K-300K) to support infrared detection. ROIC radiation tolerance capability for 256x256 LWIR area arrays and 1x128 thermopile linear arrays is presented. The use of 130 nm CMOS for future ROIC RHBD applications is discussed.

Gaalema, Stephen; Gates, James; Dobyns, David; Pauls, Greg; Wall, Bruce

2013-09-01

378

A CMOS image sensor using floating capacitor load readout operation  

NASA Astrophysics Data System (ADS)

In this paper, a CMOS image sensor using floating capacitor load readout operation has been discussed. The floating capacitor load readout operation is used during pixel signals readout. And this operation has two features: 1. in-pixel driver transistor drives load capacitor without current sources, 2. parasitic capacitor of pixel output vertical signal line is used as a sample/hold capacitor. This operation produces three advantages: a smaller chip size, a lower power consumption, and a lower output noise than conventional CMOS image sensors. The prototype CMOS image sensor has been produced using 0.18 ?m 1-Poly 3-Metal CMOS process technology with pinned photodiodes. The chip size is 2.5 mmH x 2.5 mmV, the pixel size is 4.5 ?mH x 4.5 ?mV, and the number of pixels is 400H x 300V. This image sensor consists of only a pixel array, vertical and horizontal shift registers, column source followers of which height is as low as that of some pixels and output buffers. The size of peripheral circuit is reduced by 90.2 % of a conventional CMOS image sensor. The power consumption in pixel array is reduced by 96.9 %. Even if the power consumption of column source follower is included, it reduced by 39.0 %. With an introduction of buried channel transistors as in-pixel driver transistors, the dark random noise of pixels of the floating capacitor load readout operation CMOS image sensor is 168 ?Vrms. The noise of conventional image sensor is 466 ?Vrms therefore, reduction of 63.8 % of noise was achieved.

Wakashima, S.; Goda, Y.; Li, T. L.; Kuroda, R.; Sugawa, S.

2013-02-01

379

A resistorless CMOS current reference with temperature compensation  

NASA Astrophysics Data System (ADS)

A resistorless CMOS current reference is presented. Temperature compensation is achieved by subtracting two sub-currents with different positive temperature coefficients. The circuit has been implemented with a Chartered 0.35 ?m CMOS process. The output current is 1.5 ?A, and the circuit works properly with a supply voltage down to 2 V. Measurement results show that the temperature coefficient is 98 ppm/°C, and the line regulation is 0.45%/V. The occupied chip area is 0.065 mm2.

Wei, Yan; Xin, Tian; Wenhong, Li; Ran, Liu

2011-03-01

380

IR CMOS: ultrafast laser-enhanced silicon detection  

NASA Astrophysics Data System (ADS)

SiOnyx has developed a novel silicon processing technology for CMOS sensors that will extend spectral sensitivity into the near/shortwave infrared (NIR/SWIR) and enable a full performance digital night vision capability comparable to that of current image-intensifier based night vision goggles. The process is compatible with established CMOS manufacturing infrastructure and has the promise of much lower cost than competing approaches. The measured thin layer quantum efficiency is as much as 10x that of incumbent imaging sensors with spectral sensitivity from 400 to 1200 nm.

Pralle, M. U.; Carey, J. E.; Homayoon, H.; Sickler, J.; Li, X.; Jiang, J.; Miller, D.; Palsule, C.; McKee, J.

2011-05-01

381

Novel neuromorphic CMOS device array for biochemical charge sensing.  

PubMed

Novel neuromorphic CMOS device is proposed as a biochemical charge sensor. The basic architecture of an extended floating-gate field-effect transistor (FET) is modified to be suited for large-array applications. The FET has a floating-gate that is umbrella-shaped (UGFET), maximizing its charge sensing area in a much reduced transistor area. Compared to previous chemoreceptive FET-based charge sensors, the UGFET shows improved scalability and sensitivity. 3-D device simulations validate the UGFET model. The design is fabricated in a standard CMOS process and characterized. Experimental results on biochemical charge sensing are presented employing the transconductance and subthreshold measurement schemes. PMID:19163158

Pandey, Santosh; Daryanani, Michelle; Chen, Baozhen; Tao, Chengwu

2008-01-01

382

Radiation-hardened N (+) gate CMOS/SOS  

NASA Astrophysics Data System (ADS)

Process development work for a hardened N+ polysilicon-gate CMOS/SOS process has demonstrated that it is possible to make functional 4K CMOS/SOS static RAMs that are hard to 5 x 10 to the 5th power rads without the implementation of special hardened circuit design techniques. Present circuit probe yields are low, limited by the lack of a hardened low-temperature contoured field oxide. Independent research has shown that a hardened reflow process is possible for such field oxides. Development of this reflow process is nearly complete and should result in significant improvement in yields when fully integrated into the rad-hard N+ process.

Hughes, G. W.; Brucker, G. J.; Smeltzer, R. K.

1981-05-01

383

Testing of CMOS devices in NIF's harsh neutron environment  

NASA Astrophysics Data System (ADS)

Vendor supplied CMOS sensors were exposed to 14 MeV neutrons on yield shots in NIF and examined for damage. The sensors were exposed to multiple shots with a maximum fluence on one of the sensors of 4.3E11 n/cm2. The results of post-shot testing will be presented. LLNL is investigating the suitability of CMOS imaging sensors for use in the camera of the ARIANE diagnostic which will mitigate the effects of the NIF neutron environment by dumping photoelectrons during the neutron pulse and then recording an image stored on a long persistence phosphor.

Teruya, Alan T.; Bell, Perry M.; Burns, Scott; Hagmann, Chris; Moody, James D.; Richardson, Mike

2012-10-01

384

NOTE: Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies  

NASA Astrophysics Data System (ADS)

This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process.

Yu, Xiaomei; Tang, Yaquan; Zhang, Haitao

2008-03-01

385

Antiferroelectric liquid crystal on CMOS technology for microdisplays and microphotonics  

Microsoft Academic Search

Tristate antiferroelectric and v-shaped liquid crystal materials have recently offered the promise of both the fast switching of ferroelectric materials and the analogue switching of nematic materials at drive voltages compatible with those available from standard CMOS technology thereby making them, at least in principle, suitable for consideration in microdisplay and other photonic applications. AFLC development is in its early

Ian Underwood; David G. Vass; M. I. Newsam; William J. Hossack; Georg K. Bodammer; Vidar K. Nilsen; J. Tom M. Stevenson; Alan M. Gundlach; W. Parkes; Jose M. Oton; Xabier Quintana; L. K. Chan; P. Bartelous; N. Flannigan; G. Swedenkrans; Claes Waldelof; M. Rampin; Antonio Vindigni

2001-01-01

386

Thin Film on CMOS Active Pixel Sensor for Space Applications  

PubMed Central

A 664 × 664 element Active Pixel image Sensor (APS) with integrated analog signal processing, full frame synchronous shutter and random access for applications in star sensors is presented and discussed. A thick vertical diode array in Thin Film on CMOS (TFC) technology is explored to achieve radiation hardness and maximum fill factor.

Schulze Spuentrup, Jan Dirk; Burghartz, Joachim N.; Graf, Heinz-Gerd; Harendt, Christine; Hutter, Franz; Nicke, Markus; Schmidt, Uwe; Schubert, Markus; Sterzel, Juergen

2008-01-01

387

An integrated CMOS micromechanical resonator high-Q oscillator  

Microsoft Academic Search

A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator with the intent of achieving high stability. The operation and performance of micromechanical resonators are modeled, with emphasis on circuit and noise modeling of multiport resonators. A series resonant oscillator design is

Clark T.-C. Nguyen; Roger T. Howe

1999-01-01

388

Research-grade CMOS image sensors for remote sensing applications  

Microsoft Academic Search

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been

Olivier Saint-Pe; Michel Tulet; Robert Davancens; Franck Larnaudie; Pierre Magnan; Philippe Martin-Gonthier; Franck Corbiere; Pierre Belliot; Magali Estribeau

2004-01-01

389

Research-grade CMOS image sensors for demanding space applications  

Microsoft Academic Search

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been

Olivier Saint-Pé; Michel Tulet; Robert Davancens; Franck Larnaudie; Pierre Magnan; Franck Corbière; Philippe Martin-Gonthier; Pierre Belliot

2004-01-01

390

Design and CAD challenges in 45nm CMOS and beyond  

Microsoft Academic Search

With semiconductor industry's aggressive march towards 45nm CMOS technology and introduction of new materials and device structures in sight for 32nm and 22nm nodes, it is crucial for the IC design and CAD community to understand the challenges posed by these potential technology changes. This tutorial will focus on these challenges starting from front end of line (devices) to the

David J. Frank; Ruchir Puri; Dorel Toma

2006-01-01

391

Gate engineering for deep-submicron CMOS transistors  

Microsoft Academic Search

Gate depletion and boron penetration through thin gate oxide place directly opposing requirements on the gate engineering for advanced MOSFET's. In this paper, several important issues of deep-submicron CMOS transistor gate engineering are discussed. First, the impact of gate nitrogen implantation on the performance and reliability of deep-submicron CMOSFET's is investigated. The suppression of boron penetration is confirmed by the

Bin Yu; Dong-Hyuk Ju; Wen-Chin Lee; Nick Kepler; Tsu-Jae King; Chenming Hu

1998-01-01

392

CCD and PIN-CMOS Developments for Large Optical Telescope.  

National Technical Information Service (NTIS)

Higher quantum efficiency in near-IR, narrower point spread function and higher readout speed than with conventional sensors have been receiving increased emphasis in the development of CCDs and silicon PIN-CMOS sensors for use in large optical telescopes...

V. Radeka

2006-01-01

393

Novel Integrated CMOS Pixel Structures for Vertex Detectors.  

National Technical Information Service (NTIS)

Novel CMOS active pixel structures for vertex detector applications have been designed and tested. The overriding goal of this work is to increase the signal to noise ratio of the sensors and readout circuits. A large-area native epitaxial silicon photoga...

2004-01-01

394

Radiation-induced dark current in CMOS active pixel sensors  

Microsoft Academic Search

Degradation behavior of CMOS active pixel sensors\\u000d\\u000a(APS) exposed to protons and Cobalt60 is presented. The most sensitive\\u000d\\u000aparameter is the dark current: the mean value of the degradation\\u000d\\u000ais always dominated by ionizing effects.

Michael Cohen; Jean-Pierre David

2000-01-01

395

Total dose effects on CMOS active pixel sensors  

Microsoft Academic Search

Co60 irradiations have been carried out on test structures for the development of CMOS Active Pixel Sensors that can be used in a radiation environment. The basic mechanisms that may cause failure are presented. Ionization induced damage effects such as field leakage currents and dark current increase are discussed in detail. Two different approaches to overcome these problems are considered

Jan Bogaerts; Bart Dierickx

2000-01-01

396

Charge Domain Interlace Scan Implementation in a CMOS Image Sensor  

Microsoft Academic Search

This paper presents the first CMOS image sensor which implements a charge domain interlacing principle to improve the signal-to-noise ratio (SNR) under equal exposure condition (integration time and light intensity). Inspired by the shared amplifier pixel structure, a novel pixel is designed to fit the charge domain interlacing principle, which works in field integration and frame integration mode. The designed

Yang Xu; Adri J. Mierop; Albert J. P. Theuwissen

2011-01-01

397

Photocurrent estimation for a self-reset CMOS image sensor  

Microsoft Academic Search

CMOS image sensors are capable of very high frame rate non- destructive readout. This capability and the potential of integrating memory and signal processing with the sensor on the same chip enable the implementation of many still and video imaging applications. An important example is dynamic range extension, where several images are captured during a normal exposure time - shorter

Xinqiao Liu; Abbas El Gamal

2002-01-01

398

CMOS image sensor camera with focal plane edge detection  

Microsoft Academic Search

We present a simple, yet robust, VLSI implementation of sampled-method edge detection. Our technique adopts the well-known correlated double sampling (CDS), usually used for fixed pattern noise (FPN) reduction, to perform a sampled differentiation of the captured image to detect visual edges. This circuit is usually an integral part of most CMOS image sensors; therefore no additional area is required

Muahel Tabet; Richard Hornsey

2001-01-01

399

Through silicon vias technology for CMOS image sensors packaging  

Microsoft Academic Search

In this paper a low temperature 'via-last' technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. The design rules of the vias will be briefly described and then, the steps of the technology will be presented : glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific

D. Henry; F. Jacquet; M. Neyret; X. Baillin; T. Enot; V. Lapras; C. Brunet-Manquat; J. Charbonnier; B. Aventurier; N. Sillon

2008-01-01

400

Space-variant nonorthogonal structure CMOS image sensor design  

Microsoft Academic Search

A CMOS log-polar image sensor has been designed and fabricated. As a result, a systematic approach has been proposed to design space-variant sensors and layouts. The pixels in this sensor are distributed in a polar fashion; the image plane consists of concentric rings containing the elementary sensing cells. Such a structure, where polygons use any space orientation, does not match

Fernando Pardo; Bart Dierickx; Danny Scheffer

1998-01-01

401

Single chip CMOS image sensors for a retina implant system  

Microsoft Academic Search

This work describes the architecture and realization of microelectronic components for a retina implant system that will provide visual sensations to patients with photoreceptor degeneration by applying electrostimulation of the intact retinal ganglion cell layer. Special circuitry has been developed for a fast single-chip CMOS image sensor system which provides high dynamic range of more than seven decades (without a

M. Schwarz; R. Hauschild; B. J. Hosticka; J. Huppertz; T. Kneip; S. Kolnsberg; W. Mokwa; H. K. Trieu

1998-01-01

402

A Method for Estimating Quantum Efficiency for CMOS Image Sensors  

Microsoft Academic Search

The standard method for measuring QE for a CCD sensor is not adequate for CMOS APS since it does not take into consideration the random offset, gain variations, and nonlinearity introduced by the APS readout circuits. The paper presents a new method to accurately estimate QE of an APS. Instead of varying illumination as in the CCD method, illumination is

Boyd Fowler; Abbas El Gamal; David Yang; Hui Tian

1998-01-01

403

Crosstalk and microlens study in a color CMOS image sensor  

Microsoft Academic Search

The paper describes results of crosstalk investigations and microlens (?-lens) scan experiments in a color CMOS image sensor with active pixel structure . The investigation of optical and electrical crosstalk was made on 7.8- and 5.6-?m pixels by using samples with continuous shift of color filter (CF ) and ?-lens across the array. As a result of this investigation, the

G. Agranov; V. Berezin; R. H. Tsai

2003-01-01

404

Photocurrent estimation from multiple nondestructive samples in CMOS image sensor  

Microsoft Academic Search

CMOS image sensors generally suffer form lower dynamic range than CCDs due to their higher readout noise. Their high speed readout capability and the potential of integrating memory and signal processing with the sensor on the same chip, open up many possibilities for enhancing their dynamic range. Earlier work have demonstrated the use of multiple non-destructive samples to enhance dynamic

Xinqiao Liu; Abbas El Gamal

2001-01-01

405

SRAM Design Techniques for Sub-nano CMOS Technology  

Microsoft Academic Search

The scaling of CMOS technology has significant impacts on SRAM cell ? random fluctuation of electrical characteristics and substantial leakage current. The random fluctuation of electrical property causes the symmetrical 6T cell to have huge mismatch in transistor threshold voltage. Consequently, the static noise margin (Read Margin) and the write margin are degraded dramatically. The SRAM cell tends to be

Jordan Lai

2006-01-01

406

A new design of the CMOS full adder  

Microsoft Academic Search

By using the transmission function theory, two CMOS full adders are designed, both of which have simpler circuits than the conventional full adder. Computer simulations with SPICE2G5 show that they can realize the expected logic functions and they have desirable transfer characteristics

Nan Zhuang; Haomin Wu

1992-01-01

407

100 frames\\/s CMOS range image sensor  

Microsoft Academic Search

Summary form only given. A row-parallel CMOS sensor for triangulation-based range imaging includes embedded winner-take-all circuits for detecting location of the brightest spot in each row. The brightest spot originates from a planar light continuously sweeping across a scene. The sensor delivers more than 100 range maps per second

V. Brajovic; K. Mori; N. Jankovic

2001-01-01

408

CMOS foveated image sensor: signal scaling and small geometry effects  

Microsoft Academic Search

A new foveated (log-polar) image sensor using standard CMOS technology has been designed and fabricated. The pixel distribution follows the log polar transform having more resolution in the center than in the periphery. For the fovea or central part, a different but also polar distribution has been adopted to fit the inner pixels. The particular problem of foveated image sensors

Fernando Pardo; Bart Dierickx; Danny Scheffer

1997-01-01

409

Relationship between IBICC imaging and SEU in CMOS ICs  

SciTech Connect

Ion-beam-induced charge-collection (IBICC) images of the TA670 16K-bit CMOS SRAM are analyzed and compared to previous SEU images. Enhanced charge collection was observed in the n-source/drains regions consistent with bipolar amplification or shunting.

Sexton, F.W.; Horn, K.M.; Doyle, B.L. (Sandia National Labs., Albuquerque, NM (United States)); Laird, J.S.; Cholewa, M.; Saint, A.; Legge, G.J.F. (Melbourne Univ., Parkville, VIC (Australia))

1993-01-01

410

Relationship between IBICC imaging and SEU in CMOS ICs  

SciTech Connect

Ion-beam-induced charge-collection (IBICC) images of the TA670 16K-bit CMOS SRAM are analyzed and compared to previous SEU images. Enhanced charge collection was observed in the n-source/drains regions consistent with bipolar amplification or shunting.

Sexton, F.W.; Horn, K.M.; Doyle, B.L. [Sandia National Labs., Albuquerque, NM (United States); Laird, J.S.; Cholewa, M.; Saint, A.; Legge, G.J.F. [Melbourne Univ., Parkville, VIC (Australia)

1993-03-01

411

Noise performance of a color CMOS photogate image sensor  

Microsoft Academic Search

We report on the noise performance of a color CMOS photogate image sensor that supports two levels of correlated double sampling and has high conversion gain at each pixel. Imager performance is limited by low quantum efficiency and dark current non-uniformity and not by read-out circuit temporal or fixed-pattern noise

Andrew J. Blanksby; Marc J. Loinaz; D. A. Inglis; Bryan D. Ackland

1997-01-01

412

Model for CMOS\\/SOI single-event vulnerability  

Microsoft Academic Search

This paper reports a lumped-parameter model derived from transistor characterization data used in SPICE analyses to study and predict the single-event upset thresholds for Texas Instruments SIMOX SOI SRAMs with a variety of cell designs. The modeling of CMOS\\/SOI transistors with fully bottomed sources and drains includes direct representation of the parasitic lateral bipolar structure.

S. E. Kerns; L. W. Massengill; Kerns D. V. Jr; M. L. Alles; T. W. Houston; H. Lu; L. R. Hite

1989-01-01

413

A CMOS Structure with high latchup holding voltage  

Microsoft Academic Search

Latchup free operation is demonstrated in CMOS by attaining holding voltages in excess of Vdd(5V). A thin epitaxial layer over a heavily doped substrate together with butted background contact at transistor sources is shown to be an effective structure to control the parasitic bipolar latchup. Experimental results are presented with and without butted contact and with different epi-thicknesses. In addition

G. J. Hu; R. H. Bruce

1984-01-01

414

Characterization Techniques for Evaluating Strained Si CMOS Materials  

Microsoft Academic Search

The electron and hole mobility of Si complementary metal on oxide field effect transistors (CMOS) can be enhanced by introducing a biaxial tensile stress in the Si channel. This paper outlines several key analytical techniques needed to investigate such layers. Raman scattering is used to measure the strain in the Si channel as well as to map the spatial distribution

Qianghua Xie; Ran Liu; Xiang-Dong Wang; Michael Canonico; Erika Duda; Shifeng Lu; Candi Cook; Alex A. Volinsky; Stefan Zollner; Shawn G. Thomas; Ted White; Alex Barr; Mariam Sadaka; Bich-Yen Nguyen

2003-01-01

415

Monitoring SEU parameters at reduced bias [CMOS SRAM  

Microsoft Academic Search

SEU (single event upset) sensitivity of a CMOS SRAM (static random-access memory) increases with decreasing bias in such a manner that the critical charge exhibits a linear dependence on bias. This should allow proton and neutron monitoring of SEU parameters even for radiation-hardened devices. The sensitivity of SEU rates to the thickness of the sensitive volume is demonstrated, and procedures

D. R. Roth; P. J. McNulty; W. G. Abdel-Kader; L. Strauss; E. G. Stassinopoulos

1993-01-01

416

Nanoscale CMOS at low temperature: design, reliability, and scaling trend  

Microsoft Academic Search

The semiconductor industry is not motivated to make practical use of cryogenic operation as long as IC performance could be improved at room temperature. However, as CMOS approaches the scaling limits, cooled chip operation becomes an attractive alternative. This paper explores the feasibility of IC temperature \\

Bin Yu; Haihong Wang; C. Riccobene; Hyeon-Seag Kim; Qi Xiang; Ming-Ren Lin; Leland Chang; Chenming Hu

2001-01-01

417

Probabilistic simulation for reliability analysis of CMOS VLSI circuits  

Microsoft Academic Search

A current-estimation approach to support the analysis of electromigration (EM) failures in power supply and ground buses of CMOS VLSI circuits is discussed. It uses the original concept of probabilistic simulation to efficiently generate accurate estimates of the expected current waveform required for electromigration analysis. Thus, the approach is pattern-independent and relieves the designer of the tedious task of specifying

Farid N. Najm; Richard Burch; Ping Yang; Ibrahim N. Hajj

1990-01-01

418

Overcoming scaling concerns in a radiation-hardening CMOS technology  

SciTech Connect

Scaling efforts to develop an advanced radiation-hardened CMOS process to support a 4M SRAM are described. Issues encountered during scaling of transistor, isolation, and resistor elements are discussed, as well as the solutions used to overcome these issues. Transistor data, total dose radiation results, and the performance of novel resistors for prevention of single event upsets (SEU) are presented.

Maimon, J.; Haddad, N.

1999-12-01

419

Complementary MetalâÂÂOxideâÂÂSemiconductor (CMOS) Simulation  

NSDL National Science Digital Library

This resource is an Interactive Complementary metalâÂÂoxideâÂÂsemiconductor (CMOS) simulation. All the different variables can be modified to represent different aspects of this simulation. Results are presented once the calculations are made. This can be a useful resource for those involved in engineering or physics.

2010-10-26

420

Neutron induced soft errors in CMOS memories under reduced bias  

SciTech Connect

A custom designed 16 kbit CMOS memory was irradiated by 14 MeV neutrons and 100 MeV neutrons. SEU cross sections were evaluated under different supply voltages. The cross section values are compared to those predicted by the BGR model.

Hazucha, P.; Svensson, C. [Linkoeping Univ. (Sweden). Electronic Devices Group; Johansson, K. [Linkoeping Univ. (Sweden). Electronic Devices Group]|[Ericsson Saab Avionics AB, Linkoeping (Sweden)

1998-12-01

421

Testing for bridging faults (shorts) in CMOS circuits  

Microsoft Academic Search

The stuck-at fault model, which is commonly used with fault simulation, does not adequately evaluate the effects of bridging faults (shorts between adjacent signal lines) in CMOS circuits. Tests for bridging faults can be performed on automatic test equipment, and the test vectors can be evaluated using logic simulation.

John M. Acken

1983-01-01

422

CMOS image sensors as an efficient platform for glucose monitoring.  

PubMed

Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications. PMID:23900281

Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

2013-08-27

423

Quantification of Shallow-junction Dopant Loss during CMOS Process  

SciTech Connect

We analyzed dopant concentration and profiles in source drain extension (SDE) by using in-line low energy electron induced x-ray emission spectrometry (LEXES), four point probe (FPP), and secondary ion mass spectroscopy (SIMS). By monitoring the dopant dose with LEXES, dopant loss in implantation and annealing process was successfully quantified. To measure the actual SDE sheet resistance in CMOS device structure without probe penetration in FPP, we fabricated a simple SDE sheet-resistance test structure (SSTS) by modifying a conventional CMOS process. It was found that the sheet resistances determined with SSTS are larger than those measured with FPP. There are three mechanisms of dopants loss in CMOS process: 1) wet-etching removal during photo resist cleaning, 2) out-diffusion, and 3) deactivation by post-thermal process. We quantified the loss of the dopant in SDE during the CMOS process, and found that the wet-etching removal and out-diffusion are the most significant causes for dopant loss in n-SDE and p-SDE, respectively.

Buh, G.H.; Park, T.; Jee, Y.; Hong, S.J.; Ryoo, C.; Yoo, J.; Lee, J.W.; Yon, G.H.; Jun, C.S.; Shin, Y.G.; Chung, U.-In; Moon, J.T. [Semiconductor R and D Center, Samsung Electronics Co., Ltd., Yongin-City, Gyeonggi-Do, 449-711 (Korea, Republic of)

2005-09-09

424

Defect classes-an overdue paradigm for CMOS IC testing  

Microsoft Academic Search

The IC test industry has struggled for move than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the rest

Charles F. Hawkins; Jerry M. Soden; A. W. Righter; F. Joel Fergusonti

1994-01-01

425

Test Considerations for Gate Oxide Shorts in CMOS ICs  

Microsoft Academic Search

Gate oxide shorts are defects that must be detected to produce high-reliability ICs. These problems will continue as devices are scaled down and oxide thicknesses are reduced to the 100-?? range. Complete detection of gate oxide shorts and other CMOS failure mechanisms requires measuring the IDD current during the quiescent state after each test vector is applied to the IC.

Jerry M. Soden; Charles Hawkins

1986-01-01

426

CCD AND PIN-CMOS DEVELOPMENTS FOR LARGE OPTICAL TELESCOPE.  

SciTech Connect

Higher quantum efficiency in near-IR, narrower point spread function and higher readout speed than with conventional sensors have been receiving increased emphasis in the development of CCDs and silicon PIN-CMOS sensors for use in large optical telescopes. Some key aspects in the development of such devices are reviewed.

RADEKA, V.

2006-04-03

427

Cache design of a sub-micron CMOS system\\/370  

Microsoft Academic Search

An innovative cache accessing scheme based on high MRU (most recently used) hit ratio [1] is proposed for the design of a one-cycle cache in a CMOS implementation of System\\/370. It is shown that with this scheme the cache access time is reduced by 30 ~ 35% and the performance is within 4% of a true one-cycle cache. This cache

J. H. Chang; H. Chao; Kimming So

1987-01-01

428

Event-based color change pixel in standard CMOS  

Microsoft Academic Search

This paper describes a novel spiking pixel circuit that reacts to color change but not to intensity change. It is built in standard CMOS without the use of color filters using a buried double junction to sense wavelength information. The pixel can detect light wavelength changes of about 14nm, while not responding to intensity changes of at least a factor

Raphael Berner; Tobi Delbrück

2010-01-01

429

Operation of SOI CMOS Devices at Liquid-Nitrogen Temperature.  

National Technical Information Service (NTIS)

Liquid-nitrogen-temperature (LNT) operation of silicon-on-insulator (SOI) CMOS devices has been investigated experimentally. The maximum carrier mobilities in these devices increase by factors from 1.25 to 4.5 between room temperature and LNT. At LNT, the...

K. K. Young B. Y. Tsaur

1990-01-01

430

A BiCMOS ASIC for modeling biological neurons  

Microsoft Academic Search

We developed an analog BiCMOS ASIC device modeling the electrical properties of biological neurons. The model parameters are variable, driven by specific inputs of the chip. We present here the first test results, and compare it to numerically-computed models, based on experimental data

S. Le Masson; Y. Deval; G. Le Masson; J. Tomas; D. Dupeyron; J. P. Dom

1994-01-01

431

Multiple Stress Memorization In Advanced SOI CMOS Technologies  

Microsoft Academic Search

Two distinct stress memorization phenomena in advanced SOI CMOS are reported in this work. Both require a capping layer and anneal, but can be categorized as techniques 1) requiring an amorphized source\\/drain region and low temperature anneal, and 2) requiring a high temperature anneal, independent of the crystalline state of the Si. Both improve NMOS drive current, and the resulting

A. Wei; M. Wiatr; A. Mowry; A. Gehring; R. Boschke; C. Scott; J. Hoentschel; S. Duenkel; M. Gerhardt; T. Feudel; M. Lenski; F. Wirbeleit; R. Otterbach; R. Callahan; G. Koerner; N. Krumm; D. Greenlaw; M. Raab; M. Horstmann

2007-01-01

432

Low-Power SRAMs in Nanoscale CMOS Technologies  

Microsoft Academic Search

As CMOS technology scaling is advancing beyond 100 nm, it has become increasingly difficult to meet the power and performance goals for various product applications while achieving aggressive area scaling in static random access memory (SRAM) development. This paper addresses many of the most pressing challenges in today's SRAM design from perspectives of both process technology optimization and design innovation.

Kevin Zhang; Fatih Hamzaoglu; Yih Wang

2008-01-01

433

Modeling of layout-dependent stress effect in CMOS design  

Microsoft Academic Search

Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically captures this behavior is essential to

Chi-Chao Wang; Wei Zhao; Frank Liu; Min Chen; Yu Cao

2009-01-01

434

Layout-dependent proximity effects in deep nanoscale CMOS  

Microsoft Academic Search

As CMOS scaling extends into the nanoscale regime, designers need to be aware that device behavior depends not only on traditional geometric parameters such as channel length and width, but also on layout implementation details of the device and its surrounding neighborhood. The advent of stress engineering, in which intentional mechanical stress is applied to improve device performance, also adds

John V. Faricelli

2010-01-01

435

Advanced SOI CMOS transistor technology for high performance microprocessors  

Microsoft Academic Search

An overview of state of the art Silicon on Insulator CMOS transistors used for 65nm and 45nm volume manufacturing of microprocessors will be given. AMD's unique technology and transistor progression model as well as the key challenges to increase the power efficiency of microprocessor products will be described. For advanced SOI transistors stress engineering has become a standard feature since

Maciej Wiatr

2008-01-01

436

Hybrid 90 GHz rectenna chip with CMOS preamplifier  

Microsoft Academic Search

In this paper a multi chip module (MCM) method for combining high frequency circuits with low frequency readout electronics is presented. The RF chip consists of a rectifying antenna (rectenna) and is manufactured by silicon mm-wave integrated circuit (SIMMWIC) technology. The rectenna signal is amplified by a CMOS preamplifier mounted in a hybrid construction. An amplification gain of 32 dB

M. Herrmann; D. Beck; E. Kasper; J.-F. Luy; K. Strohm; J. Buechler

1996-01-01

437

GPCAD: a tool for CMOS op-amp synthesis  

Microsoft Academic Search

We present a method for optimizing and automating compo- nent and transistor sizing for CMOS operational amplifiers. We observe that a wide variety of performance measures can be formulated as posynomial functions of the design variables. As a result, amplifier design problems can be formulated as a ge- ometric program, a special type of convex optimization problem for which very

Maria del Mar Hershenson; Stephen P. Boyd; Thomas H. Lee

1998-01-01

438

Future perspective and scaling down roadmap for RF CMOS  

Microsoft Academic Search

The concept of future scaling-down for RF CMOS technology has been investigated in terms of fT, fmax, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are key parameters, especially in sub-100 nm gate length generations

E. Morifuji; H. S. Momose; T. Ohguro; T. Yoshitomi; H. Kimijima; F. Matsuoka; M. Kinugawa; Y. Katsumata; H. Iwai

1999-01-01

439

Test of CMOS circuits based on its energy consumption  

Microsoft Academic Search

A modified Keating-Meyer technique to test CMOS circuits by measuring its energy consumption is presented. The circuit is fed by a capacitor being successively recharged while it is excited by a set of test vectors. A Binary Counter is incremented after a quantum of energy has been supplied to the CUT while the circuit is excited by test vectors. The

M. A. Ortega; J. Rius; J. Figueras

1996-01-01

440

A High Temperature SOI CMOS NO2 Sensor  

NASA Astrophysics Data System (ADS)

For more than 20 years researchers have been interested in developing micro-gas sensors based on silicon technology. Most of the reported devices are based on micro-hotplates, however they use materials that are not CMOS compatible, and therefore are not suitable for large volume manufacturing. Furthermore, they do not allow the circuitry to be integrated on to the chip. CMOS compatible devices have been previously reported. However, these use polysilicon as the heater material, which has long term stability problems at high temperatures. Here we present low power, low cost SOI CMOS NO2 sensors, based on high stability single crystal silicon P+ micro-heaters platforms, capable of measuring gas concentrations down to 0.1 ppm. We have integrated a thin tungsten molybdenum oxide layer as a sensing material with a foundry-standard SOI CMOS micro-hotplate and tested this to NO2. We believe these devices have the potential for use as robust, very low power consumption, low cost gas sensors.

Ali, S. Z.; Ho, W. O.; Chowdhury, M. F.; Covington, J. A.; Moseley, P.; Saffell, J.; Gardner, J. W.; Udrea, F.

2011-09-01

441

Radiation response of high speed CMOS integrated circuits  

SciTech Connect

This paper studies the total dose and dose rate radiation response of the FCT family of high speed CMOS integrated circuits. Data taken on the devices is used to establish the dominant failure modes, and this data is further analyzed using one-sided tolerance factors for normal distribution statistical analysis.

Yue, H.; Davison, D.; Jennings, R.F.; Lothongkam, P.; Rinerson, D.; Wyland, D.

1987-12-01

442

Industrial microsystems on top of CMOS design and process  

NASA Astrophysics Data System (ADS)

We propose a design and technology methodology and CAD tools for a microsystems fabrication based on the 1.0 micrometers CMOS from ATMEL-ES2. In order to profit from vendor cell libraries, design kits have to be enhanced to deal with the new conception environment. Main contributions are, sensor dependent technology file, device modeling and automatic generation for different ranges, and adaptation of semi- custom tools (simulation environment and P and R) for complete microsystems design. A library of dedicated sensor cells is being designed using Cadence DFWII and the foundry design kit. These sensors are fabricated with the standard CMOS process plus some post-processing steps. Three levels of post-processing are considered: 1) pH-ISFET sensors fabricated using standard CMOS, 2) gas flow and radiation sensors based on thermopiles using simple post-processing. The post-processing is compatible with the foundry CMOS process. Our technology has been developed up tot he point of maximum simplification that results in the use of only one additional mask for back-side etching. Passivation layer together with oxide windows are used for front-side etching with excellent results.

Carrabina, Jordi; Saiz, Joaquin; Marin, David; Marin, Xavier; Merlos, Angel; Bausells, Juan

1996-09-01

443

Reliability design of CMOS image sensor for space applications  

NASA Astrophysics Data System (ADS)

In space applications, sensors work in very harsh space environment. Thus the reliability design must be carefully considered. This paper addresses the techniques which effectively increase the reliability of CMOS image sensors. A radiation tolerant pixel design which is implemented in a sun tracker sensor is presented. Measurement results of total dose radiation, SEL, SEU, etc prove the radiation immunity of the sensor.

Xie, Ning; Chen, Shijun; Chen, Yongping

2013-08-01

444

Dynamic internal testing of CMOS circuits using hot luminescence  

Microsoft Academic Search

Subnanosecond pulses of hot electron luminescence are shown to be generated coincident with logic state switching of individual devices in CMOS circuits. These pulses are used to directly observe 90 ps gate delays in a ring oscillator as well as the logic switching and gate delays of a counter. By use of a detector with both space- and time-resolution, the

J. A. Kash; J. C. Tsang

1997-01-01

445

CMOS Integrating Amplifier for the PHENIX Ring Imaging Cherenkov detector.  

National Technical Information Service (NTIS)

A CMOS integrating amplifier has been developed for use in the PHENIX Ring Imaging Cherenkov (RICH) detector. The amplifier, consisting of a charge-integrating amplifier followed by a variable gain amplifier (VGA), is an element of a photon measurement sy...

A. L. Wintenberg J. P. Jones G. R. Young C. G. Moscone

1997-01-01

446

CMOS current source for shortened square wave waveforms  

Microsoft Academic Search

In many practical cases sinusoidal signals can be replaced with suitable approximations. Well-known alternative is the three level shortened square wave. By introducing more equally spaced levels, higher harmonics can be further reduced. This multilevel signal is easy to generate digitally and enables simple digital processing involving only additions and shifting. An efficient CMOS technology based current source can be

A. Kasemaa; P. Annus

2008-01-01

447

One time programming (OTP) with Zener diodes in CMOS processes  

Microsoft Academic Search

This article describes a lateral Zener diode in standard CMOS processes, without extra masks or technology steps, for one time programming (OTP) applications. The diode is adapted for programming (=zapping) requirements. The optimization of the device for low zapping currents and high yield is shown. The zapping process is evaluated in detail and follows an optimized layout and zapping conditions.

J. Teichmann; K. Burger; W. Hasche; J. Herrfurth; G. Taschner

2003-01-01

448

QE reduction due to pixel vignetting in CMOS image sensors  

NASA Astrophysics Data System (ADS)

CMOS image sensor designers take advantage of technology scaling either by reducing pixel size or by adding more transistors to the pixel. In both cases, the distance from the chip surface to the photodiode increases relative to the photodiode planar dimensions. As a result, light must ravel through an increasingly deeper and narrower `tunnel' before it reaches the photodiode. This is especially problematic for light incident at oblique angles; the narrow tunnel walls cast a shadow on the photodiode, which in turn severely reduces its effective QE. We refer to this phenomenon as pixel vignetting. The paper presents experimental results from a 640 X 512 CMOS image sensor fabricated using a 0.35(mu) 4-layer metal CMOs process that shows significant QE reduction of up to 50% for off-axis relative to on-axis pixels. Using simple geometric models of the sensor and the imaging optics, we compare the QE for on and off-axis pixels. We find that our analysis results support the hypothesis that the experimentally observed QE reduction is indeed due to pixel vignetting. We show that pixel vignetting becomes more severe as CMOS technology scales, even for a 2-layer metal APS pixel. Finally, we briefly discuss several potential solutions to the pixel vignetting problem.

Catrysse, Peter B.; Liu, Xinqiao; El Gamal, Abbas

2000-05-01

449

High voltage bipolar-CMOS structure using porous silicon  

DOEpatents

A method for integrating a silicon-on-insulator device and a bulk bipolar device on a semiconductor body. The invention simultaneously forms the two regions for the silicon-on-insulator device and the bipolar device. The invention enables a high voltage CMOS power device to be located on the same chip as a bipolar logic device enabling smart power devices.

Guilinger, T.R.; Kelly, M.J.; Tsao, S.S.

1990-12-31

450

High voltage bipolar-CMOS structure using porous silicon  

DOEpatents

A method for integrating a silicon-on-insulator device and a bulk bipolar device on a semiconductor body. The invention simultaneously forms the two regions for the silicon-on-insulator device and the bipolar device. The invention enables a high voltage CMOS power device to be located on the same chip as a bipolar logic device enabling smart power devices.

Guilinger, T.R.; Kelly, M.J.; Tsao, S.S.

1990-01-01

451

NATURE: a hybrid nanotube\\/CMOS dynamically reconfigurable architecture  

Microsoft Academic Search

Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future cir- cuit design. However, nanofabrication techniques are not yet mature, making implementation of such circuits, at least on a large scale, in the near future infeasible. However, if photo- lithography could be used to implement circuits using these nanodevices, then hybrid nano\\/CMOS chips could

Wei Zhang; Niraj K. Jha; Li Shang

2006-01-01

452

A novel multi-actuation CMOS RF MEMS switch  

NASA Astrophysics Data System (ADS)

This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

2008-12-01

453

Feasibility study of a latchup-based particle detector exploiting commercial CMOS technologies  

NASA Astrophysics Data System (ADS)

The stimulated ignition of latchup effects caused by external radiation has so far proved to be a hidden hazard. Here this effect is described as a novel approach to detect particles by means of a solid-state device susceptible to latchup effects. In addition, the device can also be used as a circuit for reading sensors devices, leaving the capability of sensing to external sensors. The paper first describes the state-of-the-art of the project and its development over the latest years, then the present and future studies are proposed. An elementary cell composed of two transistors connected in a thyristor structure is shown. The study begins using traditional bipolar transistors since the latchup effect is originated as a parasitic circuit composed of such devices. Then, an equivalent circuit built up of MOS transistors is exploited, resulting an even more promising and challenging configuration than that obtained via bipolar transistors. As the MOS transistors are widely used at present in microelectronics devices and sensors, a latchup-based cell is proposed as a novel structure for future applications in particle detection, amplification of signal sensors and radiation monitoring.

Gabrielli, A.; Matteucci, G.; Civera, P.; Demarchi, D.; Villani, G.; Weber, M.

2009-12-01

454

Development of a novel thermal switch through CMOS MEMS fabrication process  

NASA Astrophysics Data System (ADS)

This paper focuses on implementing two novel CMOS-MEMS type switches: buckling type and thermal type, by using commercially available TSMC 0.35 ?m two-poly four-metal (2P4M) CMOS process. There are two novel designs in these two type switches: first, the soft contact structure with post-processing fabrication; second, using residual stress to achieve large structural deformation in buckling type and thermal type switches. To create the soft contact structure, residual gradient stress effect has been utilized to make bending-down curvatures. According to the experiments, the layer Metal1 has the largest negative residual gradient stress effect that can achieve the largest negative deflection in z-axis. Because the structure will bend down after post-processing release, larger lateral contact area are set up to gain the lower contact miss ability. In the post-processing fabrication, 0.3?m thickness gold will be deposited on the contact tips. Due to the essence of gold, comparing with aluminum, has no oxidation issue, gold also has the advantage of higher conductivity to reduce the electrical power loss. In the buckling type design, the switch uses residual stress to achieve lateral buckling effect to solve long distance problem. In the thermal type design, this paper design a folded-flexure with the electro-thermal excitation to turn the switch on or off. In the prototype, the device size is 500 ?m x 400 ?m and the gap between two contact pads is 9 ?m in off-state. on the experimental results, the switch can work stably at 3 volts, and the displacement of the thermal type switch can achieve 2.7?m, which is sufficient for the mechanism of switching-on or switching-off.

Lai, You-Liang; Chou, Lei-Chun; Juang, Ying-Zong; Tsai, Hann-Huei; Huang, Sheng-Chieh; Chiou, Jin-Chern

2011-02-01

455

256×256 CMOS active pixel sensor camera-on-a-chip  

Microsoft Academic Search

A CMOS imaging sensor is described that uses active pixel sensor (APS) technology and permits the integration of the detector array with on-chip timing, control, and signal chain electronics. This sensor technology has been used to implement a CMOS APS camera-on-a-chip. The camera-on-a-chip features a 256×256 APS sensor integrated on a CMOS chip with the timing and control circuits, and

R. H. Nixon; S. E. Kemeny; B. Pain; C. O. Staller; E. R. Fossum

1996-01-01

456

An ultra-low dark current CMOS image sensor cell using n+ ring reset  

Microsoft Academic Search

We present in this letter for the first time a new CMOS image sensor cell using n+-ring-reset structure, which can isolate the photon-sensing area from the defective field oxide edge. The experimental results demonstrate that the severe dark current degradation of the conventional CMOS active pixel image sensor fabricated by a standard CMOS logic process is significantly alleviated. Through optimizing

Hsiu-Yu Cheng; Ya-Chin King

2002-01-01

457

A CMOS image sensor with dark-current cancellation and dynamic sensitivity operations  

Microsoft Academic Search

An ultralow dark-signal and high-sensitivity pixel has been developed for an embedded active-pixel CMOS image sensor by using a standard 0.35-?m CMOS logic process. To achieve in-pixel dark-current cancellation, we developed a combined photogate\\/photodiode photon-sensing device with a novel operation scheme. The experimental results demonstrate that the severe dark signal degradation of a CMOS active pixel sensor is reduced more

Hsiu-Yu Cheng; Ya-Chin King

2003-01-01

458

Cache design for high performance computers with BiCMOS VLSIs  

Microsoft Academic Search

Cache memory architectures and BiCMOS circuit technologies for high-speed access time that take advantage of the high integration level are discussed. Proposed is a VLSI-oriented cache memory architecture, which reduces the penalty of chip-crossings, and a functional BiCMOS RAM with gate-array suited to the associative function of the cache memory. BiCMOS cache chip sets are developed for high-performance computers with

M. Moriokat; K. Kurita; H. Kobayashi; H. Sawamoto

1990-01-01

459

Optimal fabrication process for mems pressure sensor by 8inch CMOS  

Microsoft Academic Search

We have developed the MEMS piezo pressure sensor by utilizing CMOS process modules and tool-sets to challenge faster time to market and faster time to volume with high yield. The MEMS device has the commonality of process, tools, material, and design system and qualification method with 0.35um CMOS device. The CMOS integration approach also showed the high quality as small

Tadashi Kai; Katsuyuki Inoue; Y. Adachi

2010-01-01

460

Design and characteristics measurement of a high-speed CMOS imaging system  

Microsoft Academic Search

This paper introduces the design of a high-speed 2K times 2K CMOS imaging system that is part of a Wide Field Monitor System proposed in China recent years. The CMOS sensor used in this imaging system is LUPA-4000 from Cypress corp. This CMOS camera is composed of an analogue system and a digital embedded system. The digital embedded system integrated

Yuanyuan Shang; Yong Guan; Xiaoxu Zhao; Shudong Zhang; Hui Liu

2009-01-01

461

Integration of Solar Cells on Top of CMOS Chips Part I: aSi Solar Cells  

Microsoft Academic Search

We present the monolithic integration of deep- submicrometer complementary metal-oxide-semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values above 7%. The yield of photovoltaic cells on planarized CMOS chips is 92%. This integration allows integrated energy harvesting using established process

Jiwu Lu; Alexey Y. Kovalgin; Karine H. M. van der Werf; Ruud E. I. Schropp; Jurriaan Schmitz

2011-01-01

462

Low-cost epoxy packaging of CMOS Hall-effect compasses  

Microsoft Academic Search

For the first time, a compass using CMOS Hall-sensors in a low-cost epoxy package is presented. Due to the high mechanical stress sensitivity of CMOS Hall-sensors, such low-cost plastic or epoxy mold packages have not been a viable option for low-offset applications like the compass application. Instead, expensive ceramic packages have been used. A recently developed, stress insensitive, CMOS Hall-sensor,

Jeroen van der Meer; Frank Riedijk; E. van Kampen; K. Makinwa; J. Huijsing

2005-01-01

463

Low-power logic styles: CMOS versus pass-transistor logic  

Microsoft Academic Search

Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with

Reto Zimmermann; Wolfgang Fichtner

1997-01-01

464

System-on-package ultra-wideband transmitter using CMOS impulse generator  

Microsoft Academic Search

In this paper, a low-cost CMOS ultra-wideband (UWB) impulse transmitter module with a compact form factor is proposed for impulse-radio communications. The module consists of a CMOS impulse generator, a compact bandpass filter (BPF), and a printed planar UWB antenna. The impulse generator is designed using a Samsung 0.35-?m CMOS process for low-cost and low-power fabrication. The measurement shows the

Junwoo Lee; Young-Jin Park; Myunghoi Kim; Changwook Yoon; Joungho Kim; Kwan-Ho Kim

2006-01-01

465

Development and characterization of CMOS-based monolithic X-ray imager sensor  

Microsoft Academic Search

We proposed a new design of CMOS-based X-ray image sensor with monolithically grown pixelated CsI(Tl) on photosensor area for securing the maximally achievable spatial resolution for a given sensitivity determined by the CsI(Tl) thickness at a certain X-ray energy. The test version of a CMOS image sensor (CIS) was designed and fabricated using AMIS 0.5 mum standard CMOS process. The

Gyuseong Cho; Bo Kyung Cha; Jun Hyung Bae; Byoung-Jik Kim; Sung Chae Jeon; Young-Hee Kim; Gyu-Ho Lim

2007-01-01

466

Design and implementation of a novel CMOS MEMS condenser microphone with corrugated diaphragm  

Microsoft Academic Search

This study reports a CMOS-MEMS condenser microphone implemented using the standard thin films stacking of 0.35?m UMC CMOS 3.3\\/5.0V logic process, and followed by post-CMOS micromachining steps without introducing any special materials. The corrugated diaphragm for microphone is designed and implemented using the metal layer to reduce the influence of thin film residual stresses. Moreover, silicon substrate is employed to

Chien-Hsin Huang; Ming-Han Tsai; Chien-Hsing Lee; Tsung-Min Hsieh; Jhyy-Cheng Liou; Li-Che Chen; Ming-Chuen Yip; Weileun Fang

2011-01-01

467

Development of a RF Bipolar Transistor in a Standard 0.35µm CMOS Technology  

Microsoft Academic Search

A RF Bipolar Transistor integrated to a standard 0.35µm CMOS process is presented. This BiCMOS technology features a single-poly NPN transistor with simulated performance of f? = 16GHz and BVCEO = 6.4V. With implanted base and no trench isolation, this device offers full compatibility with standard CMOS technology at the cost of three additional mask layers, while demonstrates good performance

I-Shan Michael Sun; Wai Tung Ng; Philip K. T. Mok; Hidenori Mochizuki; Katsumi Shinomura; Hisaya Imai; Akira Ishikawa; Nobuo Saito; Kiyoshi Miyashita; Satoru Tamura; Kaoru Takasuka

468

Current status and future trends of SiGe BiCMOS technology  

Microsoft Academic Search

The silicon germanium (SiGe) heterojunction bipolar transistor (HBT) marketplace covers a wide range of products and product requirements, particularly when combined with CMOS in a BiCMOS technology. A new base integration approach is presented which decouples the structural and thermal features of the HBT from the CMOS. The trend is to use this approach for future SiGe technologies for easier

David L. Harame; David C. Ahlgren; Douglas D. Coolbaugh; James S. Dunn; Gregory G. Freeman; John D. Gillis; Robert A. Groves; Gregory N. Hendersen; Robb A. Johnson; Alvin J. Joseph; Seshardi Subbanna; Alan M. Victor; Kimball M. Watson; Charles S. Webster; Peter J. Zampardi

2001-01-01

469

A CMOS Norton amplifier-based digitally controlled VGA for low-power wireless applications  

Microsoft Academic Search

A CMOS variable-gain amplifier (VGA) for use in the baseband section of integrated wireless receivers is presented. The VGA circuit is based on a new CMOS realization of the Norton transresistance amplifier. The proposed CMOS realization operates from a 3-V supply voltage with rail-to-rail swing and class AB input and output stages. The standby current of the class AB stages

Hassan Elwan; Ahmed M. Soliman; Mohammed Ismail

2001-01-01

470

Self-Calibrated Humidity Sensor in CMOS without Post-Processing  

PubMed Central

A 1.1 ?W power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2012-01-01

471

Self-calibrated humidity sensor in CMOS without post-processing.  

PubMed

A 1.1 ?W power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry. PMID:22368466

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2011-12-27

472

Post-CMOS Compatible Micromachining Technique for On-Chip Passive RF Filter Circuits  

Microsoft Academic Search

This paper reports on a post-CMOS compatible micromachining technology for passive RF circuit integration. The micromachining technology combines the formation of high performance microelectromechanical systems solenoid inductors and metal-insulator-metal (MIM) capacitors by using a post CMOS process on standard CMOS substrate. Utilizing this process, novel on-chip 3-D configured RF filters for 5 GHz band are integrated on-chip. Two types of

Zhengzheng Wu; Lei Gu; Xinxin Li

2009-01-01

473

Ultra-low-power radiation hard ADC for particle detector readout applications  

NASA Astrophysics Data System (ADS)

Radiation hard analog to digital converter (ADC) has been designed for future high energy physics experiments. The ADC has been designed in a commercial 130 nm CMOS process and it achieves 12-bit resolution, 25 MS/s sampling speed, 15 mW power consumption and hardness to at least 1.8 Megarad(Si) of total ionizing dose (TID). 16 ADC channels will be placed on one packaged silicon chip. The readout of the Liquid Argon Calorimeter of the ATLAS detector in the planned High-Luminosity Large Hadron Collider is one possible application for this ADC.

Mikkola, E. O.; Swaminathan, V.; Sivakumar, B.; Barnaby, H. J.

2013-04-01

474

Development of a CMOS SOI Pixel Detector  

SciTech Connect

We have developed a monolithic radiation pixel detector using silicon on insulator (SOI) with a commercial 0.15 {micro}m fully-depleted-SOI technology and a Czochralski high resistivity silicon substrate in place of a handle wafer. The SOI TEG (Test Element Group) chips with a size of 2.5 x 2.5 mm{sup 2} consisting of 20 x 20 {micro}m{sup 2} pixels have been designed and manufactured. Performance tests with a laser light illumination and a {beta} ray radioactive source indicate successful operation of the detector. We also briefly discuss the back gate effect as well as the simulation study.

Arai, Y.; Hazumi, M.; Ikegami, Y.; Kohriki, T.; Tajima, O.; Terada, S.; Tsuboyama, T.; Unno, Y.; Ushiroda, Y.; /KEK, Tsukuba; Ikeda, H.; /JAXA, Sagamihara; Hara, K.; /Tsukuba U.; Ishino, H.; /Tokyo Inst. Tech.; Kawasaki, T.; /Niigata U.; Miyake, H.; /Osaka U.; Martin, E.; Varner, G.; /Hawaii U.; Tajima, H.; /SLAC; Ohno, M.; Fukuda, K.; Komatsubara, H.; Ida, J.; /NONE - OKI ELECTR INDUST TOKYO

2008-08-19

475

Performance evaluation of a digital intraoral imaging device based on the CMOS photosensor array coupled with an integrated X-ray conversion fiber-optic faceplate  

NASA Astrophysics Data System (ADS)

As a continuation of our digital X-ray imaging sensor R&D, we have developed a cost-effective, intraoral imaging device based on the complementary-metal oxide semiconductor (CMOS) photosensor array coupled with an integrated X-ray conversion fiber-optic faceplate. It consists of a commercially available CMOS photosensor of a 35×35 ?m2 pixel size and a 688×910 pixel array dimension, and a high-efficiency columnar CsI(Tl) scintillator of a 90 ?m thickness directly deposited on a fiber-optic faceplate of a 6 ?m core size and an 1.46 mm thickness with 85/15 core cladding ratio (NA˜1.0 in air). The fiber-optic faceplate is a highly X-ray attenuating material that minimizes X-ray absorption on the end CMOS photosensor array, thus, minimizing X-ray induced noise at the photosensor array. It uses a high light-output columnar CsI(Tl) scintillator with a peak spectral emission at 545 nm, giving better spatial resolution, but attenuates some of this light due to interfacial and optical attenuation factors. In this paper, we presented the performance analysis of the intraoral imaging device with experimental measurements and acquired X-ray images in terms of modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE).

Cho, Hyosung; Choi, Sungil; Kim, Jongguk; Koo, Yangseo; Kim, Taewoo; Ro, Changjoon; Lee, Bongsoo; Kim, Sin; Kim, Hokyung

2007-08-01

476

Radiation-hardened bulk CMOS technology for space and weapon systems  

NASA Astrophysics Data System (ADS)

The CMOS technology that furnishes significant power, performance, and severe environment operation advantages for space and weapon systems is nevertheless vulnerable to a variety of radiation-induced problems; these include functional failure, latch-up, and single-event logic and memory upsets. Attention is presently given to the development of radiation-hardened 4- and 2-micron feature size bulk-CMOS technologies which can overcome these irradiation problems in LSI and VLSI chips. Both a CMOS microprocessor family and a 16-K CMOS static RAM are presented as representative cases of this technology.

Anderson, R. E.

477

SiGe BiCMOS technologies for power amplifier applications  

Microsoft Academic Search

Silicon-germanium (SiGe) BiCMOS technology has advanced in many areas. In this paper, we discuss and illustrate the key device design issues for SiGe BiCMOS HBTs suitable for wireless power amplifier applications. The experimental results for high-breakdown SiGe HBTs built in several generations of BiCMOS technology are presented with focus on the 0.5 ?m SiGe BiCMOS node. Implications of recent high-performance

Jeffrey B. Johnson; Alvin J. Joseph; D. Sheridan; R. M. Malladi

2003-01-01

478

CMOS photonics for optical manipulation of particles and biosensing  

NASA Astrophysics Data System (ADS)

We will discuss the latest progress in our work on using complementary metal-oxide semiconductor (CMOS) photonics for optical manipulation of dielectric microparticles and submicrometer particles in a microfluidic channel. Specifically, we will review optical trapping and routing of particles using silicon nitride waveguide-based directional couplers and multimode-interference (MMI)-based couplers. Our experiments reveal that microparticles can be directionally coupled from one waveguide to another waveguide via evanescent light coupling over submicrometer gap spacing. We also observe that microparticles can be preferentially transported to the larger field-intensity output-port of a 1×2 MMI optical power splitter. We thus envision that these photonic components, along with other photonic components that have previously been demonstrated with functionalities of optical manipulation of particles in fluids, constitute basic building blocks of CMOS optofluidic "particle circuits" for particle manipulation and biosensing.

Poon, Andrew W.; Cai, Hong

2012-05-01

479

Digital autoradiography using room temperature CCD and CMOS imaging technology.  

PubMed

CCD (charged coupled device) and CMOS imaging technologies can be applied to thin tissue autoradiography as potential imaging alternatives to using conventional film. In this work, we compare two particular devices: a CCD operating in slow scan mode and a CMOS-based active pixel sensor, operating at near video rates. Both imaging sensors have been operated at room temperature using direct irradiation with images produced from calibrated microscales and radiolabelled tissue samples. We also compare these digital image sensor technologies with the use of conventional film. We show comparative results obtained with (14)C calibrated microscales and (35)S radiolabelled tissue sections. We also present the first results of (3)H images produced under direct irradiation of a CCD sensor operating at room temperature. Compared to film, silicon-based imaging technologies exhibit enhanced sensitivity, dynamic range and linearity. PMID:17671349

Cabello, Jorge; Bailey, Alexis; Kitchen, Ian; Prydderch, Mark; Clark, Andy; Turchetta, Renato; Wells, Kevin

2007-08-01

480

A high precision CMOS weak current readout circuit  

NASA Astrophysics Data System (ADS)

This paper presents a high precision CMOS weak current readout circuit. This circuit is capable of converting a weak current into a frequency signal for amperometric measurements with high precision and further delivering a 10-bit digital output. A fast stabilization-enhanced potentiostat has been proposed in the design, which is used to maintain a constant bias potential for amperometric biochemical sensors. A technique based on source voltage shifting that reduces the leakage current of the MOS transistor to the reverse diode leakage level at room temperature was employed in the circuit. The chip was fabricated in the 0.35 ?m chartered CMOS process, with a single 3.3 V power supply. The interface circuit maintains a dynamic range of more than 100 dB. Currents from 1 pA to 300 nA can be detected with a maximum nonlinearity of 0.3% over the full scale.

Qisong, Wu; Haigang, Yang; Tao, Yin; Chong, Zhang

2009-07-01

481

A CMOS integrated timing discriminator circuit for fast scintillation counters  

SciTech Connect

Based on a zero-crossing discriminator using a CR differentiation network for pulse shaping, a new CMOS integrated timing discriminator circuit is proposed for fast (t{sub r} {ge} 2 ns) scintillation counters at the cooler synchrotron COSY-Juelich. By eliminating the input signal`s amplitude information by means of an analog continuous-time divider, a normalized pulse shape at the zero-crossing point is gained over a wide dynamic input amplitude range. In combination with an arming comparator and a monostable multivibrator this yields in a highly precise timing discriminator circuit, that is expected to be useful in different time measurement applications. First measurement results of a CMOS integrated logarithmic amplifier, which is part of the analog continuous-time divider, agree well with the corresponding simulations. Moreover, SPICE simulations of the integrated discriminator circuit promise a time walk well below 200 ps (FWHM) over a 40 dB input amplitude dynamic range.

Jochmann, M.W. [Forschungszentrum Juelich (Germany). Zentrallabor fuer Elektronik

1998-06-01

482

An electrochemical dopamine sensor with a CMOS detection circuit  

NASA Astrophysics Data System (ADS)

This paper presents the integration of interdigitated microelectrodes and a CMOS circuit for electrochemical sensing of the neurotransmitter dopamine. Gold electrodes with a gap of 3 µm are fabricated by the lift-off technique. The CMOS sensing circuit has a current gain of 10, an integrating capacitor of 4 pF, and a measured dynamic range of 60 dB. The applied reduction and oxidation potentials are determined by voltammetry at about -0.2 V and 0.6 V, respectively. The measured collection efficiency can reach up to 84%. The produced oxidation current with respect to dopamine concentration averages 0.44 nA µM-1.

Chan, Feng-Lin; Chang, Wen-Ying; Kuo, Li-Min; Lin, Chih-Heng; Wang, Shi-Wei; Yang, Yuh-Shyong; S-C Lu, Michael

2008-07-01

483

Linearisation for analogue optical links using integrated CMOS predistortion circuits  

NASA Astrophysics Data System (ADS)

The demand for high-speed communications is growing exponentially. Recent trends in the integration of entire systems-on-chip have spurred the development of Fibre-To-The-Home (FTTH) network for high-speed data and video services. This paper presents a predistortion circuit that integrates all of the functions necessary to implement a high linearity distribution point system for broadband optical fibre communications. The single CMOS chip includes a variable gain amplifier and a predistortion circuit. The circuits have been implemented with 0.35?m CMOS technology and simulation shows that the power consumption is 86mW with a 3.3V supply. The systems and circuits are detailed and their application to analogue optical links discussed.

Lin, Fu-Chuan; Holburn, David M.

2005-06-01

484

Nanophotonic integration in state-of-the-art CMOS foundries.  

PubMed

We demonstrate a monolithic photonic integration platform that leverages the existing state-of-the-art CMOS foundry infrastructure. In our approach, proven XeF2 post-processing technology and compliance with electronic foundry process flows eliminate the need for specialized substrates or wafer bonding. This approach enables intimate integration of large numbers of nanophotonic devices alongside high-density, high-performance transistors at low initial and incremental cost. We demonstrate this platform by presenting grating-coupled, microring-resonator filter banks fabricated in an unmodified 28 nm bulk-CMOS process by sharing a mask set with standard electronic projects. The lithographic fidelity of this process enables the high-throughput fabrication of second-order, wavelength-division-multiplexing (WDM) filter banks that achieve low insertion loss without post-fabrication trimming. PMID:21369052

Orcutt, Jason S; Khilo, Anatol; Holzwarth, Charles W; Popovi?, Milos A; Li, Hanqing; Sun, Jie; Bonifield, Thomas; Hollingsworth, Randy; Kärtner, Franz X; Smith, Henry I; Stojanovi?, Vladimir; Ram, Rajeev J

2011-01-31

485

Radiation Hard 0.25 Micron CMOS Library at IHP  

NASA Astrophysics Data System (ADS)

To support space applications we have produced a test chip with our in house 0.25 micron BiCMOS- Technology. Then the chips were radiated and measured. During measurements no threshold voltage shift and no single event latchup (SEL) were obtained up to a level of 200 krad. As conclusion of the measurement we developed new radiation hard design rules and according to these rules we created a new radiation hard CMOS library. With this new library we produced a Leon3 chip with triple module redundancy. Single event upsets did occur. Therefore we upgrade the library to make the flip flops more resistant against single event upset (SEU) by adding two p-MOS transistors.

Jagdhold, U.

2008-08-01

486

Design of prototype high speed CMOS image sensors  

NASA Astrophysics Data System (ADS)

Large size photodiode used in high speed CMOS image sensor pixel suffers from slow signal charges transfer speed and large image lag. To solve these problems, in this paper, we present a new device structure for high speed CMOS image sensor pixel with lateral graded-doping profile pinned photodiode and non-uniform doped channel transfer gate. Theory analysis and TCAD simulation results indicate that the proposed pixel can increase the signal charges transfer speed and reduce the image lag effectively. The measurement results show that, the proposed pixel is able to achieve 40ns readout time and 0.44% image lag. Compare to conventional pixels, 64 times higher readout speed enhancement and five times lower image lag were achieved.

Cao, Zhong-xiang; Zhou, Yang-fan; Li, Quan-liang; Qin, Qi; Wu, Nan-jian

2013-08-01

487

Forced Chaos Generator with CMOS Variable Active Inductor Circuit  

NASA Astrophysics Data System (ADS)

We propose a forced chaos generator with a CMOS variable active inductor circuit. The equivalent inductance of the variable active inductor in the proposed circuit can be controlled by an external voltage. Therefore, the oscillation frequencies of the circuit can be altered by applying an external periodic square waveform. As a result, we can generate chaos from the circuit. We then confirm the folding-and-stretching mechanism of the chaotic motion in the circuit. Complex phenomena, observed in the proposed circuit, are analyzed through the Poincaré sections from the SPICE simulations with TSMC 0.35?m CMOS semiconductor process parameters. In addition, we define a return map on the Poincaré section to examine the properties of the observed attractors. Moreover, we investigate the bifurcation phenomena when the amplitude and period of the external signal are changed as bifurcation parameters.

Tsubaki, Yusuke; Sekikawa, Munehisa; Horio, Yosihiko

488

A novel noise optimization technique for inductively degenerated CMOS LNA  

NASA Astrophysics Data System (ADS)

This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 ?m CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.

Zhiqing, Geng; Haiyong, Wang; Nanjian, Wu

2009-10-01

489

A pixel readout chip for 10-30 Mrad in standard 0.25{micro}m CMOS  

SciTech Connect

A radiation tolerant pixel detector readout chip has been developed in a commercial 0.25 {micro}m CMOS process. The chip is a matrix of two columns of 65 identical cells. Each readout cell comprises a preamplifier, a shaper filter, a discriminator, a delay line and readout logic. The chip occupies 10 mm{sup 2}, and contains about 50,000 transistors. Electronic noise ({approximately}220 e{sup {minus}} rms) and threshold dispersion ({approximately}160 e{sup {minus}} rms) allow operation at 1,500 e{sup {minus}} average threshold. The radiation tolerance of this mixed mode analog-digital circuit has been enhanced by designing NMOS transistors in enclosed geometry and introducing guardrings wherever necessary. The chip, which was developed at CERN for the ALICE and LHCb experiments, was still operational after receiving 3.6 {times} 10{sup 13} protons over an area of 2 mm x 2 mm. Other chips were irradiated with X-rays and remained fully functional up to 30 Mrad (SiO2) with only minor changes in analog parameters. These results indicate that careful use of deep submicron CMOS technologies can lead to circuits with high radiation tolerance.

Campbell, M.; Anelli, G.; Burns, M. [CERN, Geneva (Switzerland)] [and others

1999-06-01

490

A perforated CMOS microchip for immobilization and activity monitoring of electrogenic cells  

NASA Astrophysics Data System (ADS)

CMOS-based microelectrode systems offer decisive advantages over conventional micro-electrode arrays, which include the possibility to perform on-chip signal conditioning or to efficiently use larger numbers of electrodes to obtain statistically relevant data, e.g., in pharmacological drug screening. A larger number of electrodes can only be realized with the help of on-chip multiplexing and readout schemes, which require integrated electronics. Another fundamental issue in performing high-fidelity recordings from electrogenic cells is a good electrical coupling between the cells and the microelectrodes, in particular, since the recorded extracellular signals are in the range of only 10-1000 µV. In this paper we present the first CMOS microelectrode system with integrated micromechanical cell-placement features fabricated in a commercial CMOS process with subsequent post-CMOS bulk micromachining. This new microdevice aims at enabling the precise placement of single cells in the center of the electrodes to ensure an efficient use of the available electrodes, even for low-density cell cultures. Small through-chip holes have been generated at the metal-electrode sites by using a combination of bulk micromachining and reactive-ion etching. These holes act as orifices so that cell immobilization can be achieved by means of pneumatic anchoring. The chip additionally hosts integrated circuitry, i.e., multiplexers to select the respective readout electrodes, an amplifier with selectable gain (2×, 10×, 100×), and a high-pass filter (100 Hz cut-off). In this paper we show that electrical signals from most of the electrodes can be recorded, even in low-density cultures of neonatal rat cardiomyocytes, by using perforated metal electrodes and by applying a small underpressure from the backside of the chip. The measurements evidenced that, in most cases, about 90% of the electrodes were covered with single cells, approximately 4% were covered with more than one cell due to clustering and approximately 6% were not covered with any cell, mostly as a consequence of orifice clogging. After 4 days of culturing, the cells were still in place on the electrodes so that the cell electrical activity could be measured using the on-chip circuitry. Measured signal amplitudes were in the range of 500-700 µV, while the input-referred noise of the readout was below 15 µVrms (100 Hz-4 kHz bandwidth). We report on the development and fabrication of this new cell-biological tool and present first results collected during the characterization and evaluation of the chip. The recordings of electrical potentials of neonatal rat cardiomyocytes after several days in vitro, which, on the one hand, were conventionally cultured (no pneumatic anchoring) and, on the other hand, were anchored and immobilized, will be detailed.

Greve, F.; Lichtenberg, J.; Kirstein, K.-U.; Frey, U.; Perriard, J.-C.; Hierlemann, A.

2007-03-01

491

Light-emitting polymer on CMOS: a new photonic technology?  

NASA Astrophysics Data System (ADS)

A new hybrid optoelectronic technology has been developed which utilizes a very thin layer of light emitting polymer material on a CMOS silicon active-matrix substrate to create a 2-D array of independently programmable optical emitters. The technology has been developed thus far primarily for its use as a microdisplay. Here we detail aspects of device design and characterization. We consider the relevance of the new technology to optical and photonic systems other than displays.

Underwood, Ian; Gourlay, James

2003-11-01

492

CMOS bandgap references and temperature sensors and their applications  

Microsoft Academic Search

Two main parts have been presented in this thesis: device characterization and circuit. \\u000aIn integrated bandgap references and temperature sensors, the IC(VBE, characteristics of bipolar transistors are used to generate the basic signals with high accuracy. To investigate the possibilities to fabricate high-precision bandgap references and temperature sensors in low-cost CMOS technology, the electrical characteristics of substrate bipolar pnp transistors

G. Wang

2005-01-01

493

DESIGN AND EVALUATION OF A COMPARATOR IN CMOS SOI  

Microsoft Academic Search

The purpose of this work is to find good design tech- niques for the analog\\/mixed-signal parts of a system-on- chip in SOI. A comparator has therefore been designed and manufactured in a 0.13 ?m partially depleted SOI CMOS technology. The comparator is a first step towards the design of a complete 6-bit flash analog-to-digital con- verter, with a sampling frequency

Erik Säll; Mark Vesterbacka

494

A triple metal interconnection process for CMOS technology  

Microsoft Academic Search

A triple interconnection process suitable for a CMOS 1.2-?m technology device is described. As far as process technology is concerned, planarization was applied at contacts and via I and II levels. In order to avoid silicon grains in the contact and to improve contact resistance, the metallization scheme requires the use of a metallization barrier. The AlSi(1%)Cu(0.5%) alloy was used

P. Cagnoni; F. Gualandris; L. Masini

1989-01-01

495

An advanced triple level metal CMOS technology for ASIC applications  

Microsoft Academic Search

An advanced triple-level metal CMOS technology (TRIM), which uses a twin-well approach to achieve optimal device performance, is described in detail with emphasis on novel process like borophosphosilicate glass wet\\/dry etch, barrier metal, and boron-doped silica glass. Degradation of device reliability due to the triple-level metal (TLM) is also discussed. A 100 K gate array has been successfully manufactured utilizing

J. Schmiesing; K. Y. Chang; F. Pintchovski; J. Klein; K. Baker; C. S. Meyer; S. Lai; D. Hoang; D. Tang

1988-01-01

496

A submicron CMOS triple level metal technology for ASIC applications  

Microsoft Academic Search

A submicrometer CMOS triple-level metal technology has been demonstrated. The process features include: self-aligned twin-well, improved LOCOS (local oxidation of silicon)-like isolation, scaled gate-oxide thickness, and enhanced channel implants. In addition, an advanced straight wall plug technology has been used which allows the stacking of contact, via 1, and via 2 in the layout. Inverter gate delays of 103 ps

D. Fisher; K. Y. Chang; F. Pintchovski; J. Klein; K.-Y. Fu; S. Lai; R. Dillard

1989-01-01

497

Manufacturable triple level metal technology for submicron CMOS  

Microsoft Academic Search

The triple-level-metal (TLM) module of a submicron CMOS technology with (titanium) salicided devices is discussed. The key technology features of the module include the use of conformal BPSG for enhanced planarization, a TiN barrier layer under M1, plasma-dry-tapered contacts and vias, and TiN antireflection coatings for metal patterning. Large-area test structures for each TLM component were used to develop and

W. Paulson; J. Klein; M. Woo; T. Kobayashi; R. Hendrix; E. Travis; F. Pintchovski; Y.-C. See

1990-01-01

498

A fully differential CMOS transconductance-transimpedance wideband amplifier  

Microsoft Academic Search

A high-speed wideband amplifier using a transconductance-transimpedance circuit technique is presented. The proposed circuit configuration results in more reliable performances than are typically obtained from designs using conventional pole-zero, cancellation or peaking technique. With a 0.8 ?m, double poly, double metal, n-well CMOS technology and single 5-V power supply, the prelayout simulation of this amplifier shows a -3 dB frequency

Chorng-Kuang Wang; Po-Chiun Huang; Chen-Yi Huang

1995-01-01

499

An Ultra-Wideband CMOS Receiver Front-End  

Microsoft Academic Search

A CMOS receiver front-end for ultra-wideband (UWB) wireless communications based on multi-band OFDM -Alliance (MBOA) \\/ WiMedia standard proposal is presented. Employing a direct conversion architecture, the RF front-end chip integrates a single-ended wideband low-noise amplifier (LNA) and two double-balanced downconversion mixers. To reduce power consumption, the conversion of single ended LNA output to differential is embedded in the RF

Bo Shi; Michael Yan; Wah Chia

2007-01-01

500

An ultra-wideband CMOS receiver front-end  

Microsoft Academic Search

A CMOS receiver front-end for ultra-wideband (UWB) wireless communications based on multi-band OFDM alliance (MBOA)\\/WiMedia standard proposal is presented. Employing a direct conversion architecture, the RF front-end chip integrates a single-ended wideband low-noise amplifier (LNA) and two double-balanced downconversion mixers. To reduce power consumption, the conversion of single ended LNA output to differential is embedded in the RF transconductance circuit

Bo Shi; M. Y. W. Chia

2007-01-01