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1

Development of front-end electronics for LumiCal detector in CMOS 130 nm technology  

NASA Astrophysics Data System (ADS)

The design and the preliminary measurements results of a multichannel, variable gain front-end electronics for luminosity detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier with pole-zero cancellation circuit and a CR-RC shaper with 50 ns peaking time. The measurements results confirm full functionality of the prototype and compliance with the requirements imposed by the detector specification. The power consumption of the front-end is in the range 0.6–1.5 mW per channel and the noise ENC around 900 e - at 10 pF input capacitance.

Firlej, M.; Fiutowski, T.; Idzik, M.; Moro?, J.; ?wientek, K.; Terlecki, P.

2015-01-01

2

Radiation hardness evaluation of a 130 nm SiGe BiCMOS technology for high energy physics applications  

NASA Astrophysics Data System (ADS)

Final results for a comprehensive radiation hardness evaluation of a high performance, low cost, 130 nm SiGe BiCMOS technology are presented. After a survey of several available SiGe technologies, one was chosen in terms of performance, power consumption, radiation hardness, and cost and it is presented as a suitable technology for the future upgrades of the ATLAS detector of the High Luminosity LHC. Bipolar devices of different sizes and geometries have been evaluated, along with a prototype Front-End readout ASIC designed for binary readout of silicon microstrip detectors. Gamma, neutron and proton irradiations have been performed up to the expected doses and fluences of the experiment.

Díez, S.; Clark, T.; Grillo, A. A.; Kononenko, W.; Martinez-McKinney, F.; Newcomer, F. M.; Norgren, M.; Rescia, S.; Spencer, E.; Spieler, H.; Ullán, M.; Wilder, M.

2013-10-01

3

Traveling wave electrode design for ultra compact carrier-injection HBT-based electroabsorption modulator in a 130nm BiCMOS process  

NASA Astrophysics Data System (ADS)

Silicon photonic system, integrating photonic and electronic signal processing circuits in low-cost silicon CMOS processes, is a rapidly evolving area of research. The silicon electroabsorption modulator (EAM) is a key photonic device for emerging high capacity telecommunication networks to meet ever growing computing demands. To replace traditional large footprint Mach-Zehnder Interferometer (MZI) type modulators several small footprint modulators are being researched. Carrier-injection modulators can provide large free carrier density change, high modulation efficiency, and compact footprint. The large optical bandwidth and ultra-fast transit times of 130nm HBT devices make the carrierinjection HBT-based EAM (HBT-EAM) a good candidate for ultra-high-speed optical networks. This paper presents the design and 3D full-wave simulation results of a traveling wave electrode (TWE) structure to increase the modulation speed of a carrier-injection HBT-EAM device. A monolithic TWE design for an 180um ultra compact carrier-injection-based HBT-EAM implemented in a commercial 130nm SiGe BiCMOS process is discussed. The modulator is electrically modeled at the desired bias voltage and included in a 3D full-wave simulation using CST software. The simulation shows the TWE has a S11 lower than -15.31dB and a S21 better than -0.96dB covering a bandwidth from DC-60GHz. The electrical wave phase velocity is designed close to the optical wave phase velocity for optimal modulation speed. The 3D TWE design conforms to the design rules of the BiCMOS process. Simulation results show an overall increase in modulator data rate from 10Gbps to 60Gbps using the TWE structure.

Fu, Enjin; Joyner Koomson, Valencia; Wu, Pengfei; Huang, Z. Rena

2014-03-01

4

A 5th generation SPARC64 processor is fabricated in 130nm SOI CMOS process with 8 layers of Cu metallization. It runs at  

E-print Network

is the worst thing to happen that cast doubt on all outputs from the server. Since high end serv- ers use many this goal, a new 130nm partially depleted SOI CMOS process is selected. Minimizing the risk of using the new

Koppelman, David M.

5

A fully-integrated 130nm CMOS DC-DC step-down converter, regulated by a constant on\\/off-time control system  

Microsoft Academic Search

A fully-integrated DC-DC step-down converter in a 130 nm 1.2 V CMOS technology is realized, with an integrated metal-track inductor and integrated MOS and MIM capacitors. The converter is designed to generate an output voltage of 1.2 V out of a 2.6 V power supply. No external components are required. The maximum power conversion efficiency is 52%, for a voltage

Mike Wens; Michiel Steyaert

2008-01-01

6

An 800mW fully-integrated 130nm CMOS DC-DC step-down multi-phase converter, with on-chip spiral inductors and capacitors  

Microsoft Academic Search

A fully-integrated DC-DC step-down four-phase converter in a 130 nm 1.2 V CMOS technology is realized. Integrated metal-track inductors and integrated MOS and MIM capacitors are used for the output filter. No external components are required. The converter is designed to generate an output voltage of 1.2 V out of a 2.6 V supply voltage. Stacked transistors are used to

M. Wens; M. Steyaert

2009-01-01

7

Analysis and Design of Reduced-Size Marchand Rat-Race Hybrid for Millimeter-Wave Compact Balanced Mixers in 130-nm CMOS Process  

Microsoft Academic Search

The analysis and design flow for reduced-size Marchand rat-race hybrids are presented in this paper. A simplified single-to-differential mode is used to analyze the Marchand balun, and the methodology to reduce the size of Marchand balun is developed. The 60-GHz CMOS singly balanced gate mixer and diode mixer using the reduced-size Marchand rat-race hybrid are implemented to verify the design

Chun-Hsien Lien; Chi-Hsueh Wang; Chin-Shen Lin; Pei-Si Wu; Kun-You Lin; Huei Wang

2009-01-01

8

Thermoelectric power sensor for microwave applications by commercial CMOS fabrication  

Microsoft Academic Search

This work describes an implementation of a thermoelectric microwave power sensor fabricated through commercial CMOS process with additional maskless etching. The sensor combines micromachined coplanar waveguide and contact pads, a microwave termination which dissipates heat proportionally to input microwave power, and many aluminum-polysilicon thermocouples. The device was designed and fabricated in standard CMOS technology, including the appropriate superimposed dielectric openings

V. Milanovic; M. Gaitan; E. D. Bowen; N. H. Tea; M. E. Zaghloul

1997-01-01

9

A 60 GHz CMOS balanced downconversion mixer with a layout efficient 90° hybrid coupler  

Microsoft Academic Search

This paper presents the design and realization of a downconversion mixer fabricated in a standard 130 nm commercial CMOS process and aimed at applications in the 60 GHz ISM band. A balanced mixer configuration was implemented using a layout efficient 90deg hybrid coupler which serves as a diplexer to inject the LO signal while also providing two outputs with 3

R. E. Amaya; Cornelius J. Verver

2009-01-01

10

A 130 nm ASIC prototype for the NA62 Gigatracker readout  

NASA Astrophysics Data System (ADS)

One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27 mm×60 mm. While the maximum pixel size is fairly large, 300 ?m×300 ?m the system has to sustain a very high particle rate, 1.5 MHz/mm 2, which corresponds to 800 MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150 ps (rms). Therefore the front-end ASIC should provide for each pixel a 200 ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130 nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Converter based TDC, both of them implemented on each pixel cell. The End of Column circuit containing only digital logic is responsible for the data readout from the pixel cell. The whole chip works with a system clock of 160 MHz and the digital logic is SEU protected by the use of Hamming codes. The detailed architecture of the ASIC prototype and test results are presented.

Dellacasa, G.; Garbolino, S.; Marchetto, F.; Martoiu, S.; Mazza, G.; Rivetti, A.; Wheadon, R.

2011-09-01

11

A SrRuO 3/IrO 2 top electrode FeRAM with Cu BEOL process for embedded memory of 130 nm generation and beyond  

NASA Astrophysics Data System (ADS)

A damage-robust SrRuO 3/IrO 2 top electrode FeRAM with Cu BEOL process is demonstrated for the first time as a promising device for 130 nm CMOS embedded non-volatile memory. The ferroelectric capacitor with SrRuO 3/IrO 2 top electrode has no degradation during Cu metallization to suppress oxygen and lead vacancies at a top electrode interface. Switching charge ( Qsw) of 40 ?C/cm 2 is achieved for 0.45 × 0.45 ?m 2 top electrode (TE) size capacitor. Ninety percent saturation of Qsw is obtained at 1.1 V that is low enough to drive ferroelectric capacitors at 1.8 V for 130 nm CMOS. Opposite state polarization margin more than 90% is retained against imprint after the high temperature storage at 150 °C for 70 h. The combination of this high reliable capacitor with large Qsw and Chain FeRAM™ architecture with a small bit line capacitance [Ozaki T, Iba J, Yamada Y, Kanaya H, Morimoto T, Hidaka O, et al. In: Symposium on VLSI technologies technical digest; 2001. p. 113] drastically increases signal window for 1T1 C operation. A sharp signal distribution and a large peak-to-peak signal window of 730 mV at 1.8 V on the test device with 0.20 ?m 2 area capacitors using three-level Cu metallization on 32 Mb Chain FeRAM™ are obtained. This technology realizes reliable embedded FeRAM of 130 nm generation and beyond.

Kumura, Y.; Ozaki, T.; Kanaya, H.; Hidaka, O.; Shimojo, Y.; Shuto, S.; Yamada, Y.; Tomioka, K.; Yamakawa, K.; Yamazaki, S.; Takashima, D.; Miyakawa, T.; Shiratake, S.; Ohtsuki, S.; Kunishima, I.; Nitayama, A.

2006-04-01

12

Packaging commercial CMOS chips for lab on a chip integration.  

PubMed

Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems. PMID:24682025

Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

2014-05-21

13

Radiation hardness evaluation of the commercial 150 nm CMOS process using 60Co source  

NASA Astrophysics Data System (ADS)

We present a study of radiation effects on MOSFET transistors irradiated with a 60Co source to a total absorbed dose of 1.5 Mrad. The transistor test structures were manufactured using a commercial 150 nm CMOS process and are composed of transistors of different types (NMOS and PMOS), dimensions and insulation from the bulk material by means of deep n-wells. We have observed a degradation of electrical characteristics of both PMOS and NMOS transistors, namely a large increase of the leakage current of the NMOS transistors after irradiation.

Carna, M.; Havranek, M.; Hejtmanek, M.; Janoska, Z.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

2014-06-01

14

A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects  

Microsoft Academic Search

A leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported. Dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V. High Vt transistors have drive currents of 1.03 mA\\/?m and 0.5 mA\\/?m for NMOS and PMOS respectively, while low Vt transistors have currents of 1.17 mA\\/?m

S. Tyagi; M. Alavi; R. Bigwood; T. Bramblett; J. Brandenburg; W. Chen; B. Crew; M. Hussein; P. Jacob; C. Kenyon; C. Lo; B. McIntyre; Z. Ma; P. Moon; P. Nguyen; L. Rumaner; R. Schweinfurth; S. Sivakumar; M. Stettler; S. Thompson; B. Tufts; J. Xu; S. Yang; M. Bohr

2000-01-01

15

Micro Ethanol Sensors with a Heater Fabricated Using the Commercial 0.18 ?m CMOS Process  

PubMed Central

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

16

Micro ethanol sensors with a heater fabricated using the commercial 0.18 ?m CMOS process.  

PubMed

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 µm complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

17

Commercial CMOS image sensors as X-ray imagers and particle beam monitors  

NASA Astrophysics Data System (ADS)

CMOS image sensors are widely used in several applications such as mobile handsets webcams and digital cameras among others. Furthermore they are available across a wide range of resolutions with excellent spectral and chromatic responses. In order to fulfill the need of cheap systems as beam monitors and high resolution image sensors for scientific applications we exploited the possibility of using commercial CMOS image sensors as X-rays and proton detectors. Two different sensors have been mounted and tested. An Aptina MT9v034, featuring 752 × 480 pixels, 6?m × 6?m pixel size has been mounted and successfully tested as bi-dimensional beam profile monitor, able to take pictures of the incoming proton bunches at the DeFEL beamline (1–6 MeV pulsed proton beam) of the LaBeC of INFN in Florence. The naked sensor is able to successfully detect the interactions of the single protons. The sensor point-spread-function (PSF) has been qualified with 1MeV protons and is equal to one pixel (6 mm) r.m.s. in both directions. A second sensor MT9M032, featuring 1472 × 1096 pixels, 2.2 × 2.2 ?m pixel size has been mounted on a dedicated board as high-resolution imager to be used in X-ray imaging experiments with table-top generators. In order to ease and simplify the data transfer and the image acquisition the system is controlled by a dedicated micro-processor board (DM3730 1GHz SoC ARM Cortex-A8) on which a modified LINUX kernel has been implemented. The paper presents the architecture of the sensor systems and the results of the experimental measurements.

Castoldi, A.; Guazzoni, C.; Maffessanti, S.; Montemurro, G. V.; Carraresi, L.

2015-01-01

18

An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V  

Microsoft Academic Search

A leading edge 130 nm technology with 6 layers of Cu interconnects and 1.3 V operation has previously been presented (Tyagi et al., 2000). In this work, we enhance the previous technology with the following: transistor improvements which support a 60 nm gate dimension and increased drive current, improved 6-T SRAM device matching to allow low power and high performance

S. Thompson; M. Alavi; R. Arghavani; A. Brand; R. Bigwood; J. Brandenburg; B. Crew; V. Dubin; M. Hussein; P. Jacob; C. Kenyon; E. Lee; B. Mcintyre; Z. Ma; P. Moon; P. Nguyen; M. Prince; R. Schweinfurth; S. Sivakumar; P. Smith; M. Stettler; S. Tyagi; M. Wei; J. Xu; S. Yang; M. Bohr

2001-01-01

19

A Comparative Study of Heavy Ion and Proton Induced Bit Error Sensitivity and Complex Burst Error Modes in Commercially Available High Speed SiGe BiCMOS  

NASA Technical Reports Server (NTRS)

A viewgraph presentation that reviews recent SiGe bit error test data for different commercially available high speed SiGe BiCMOS chips that were subjected to various levels of heavy ion and proton radiation. Results for the tested chips at different operating speeds are displayed in line graphs.

Marshall, Paul; Carts, Marty; Campbell, Art; Reed, Robert; Ladbury, Ray; Seidleck, Christina; Currie, Steve; Riggs, Pam; Fritz, Karl; Randall, Barb

2004-01-01

20

Introducing 65 nm CMOS technology in low-noise read-out of semiconductor detectors  

Microsoft Academic Search

The large scale of integration provided by CMOS processes with minimum feature size in the 100nm range, makes them very attractive in the design of front-end electronics for highly pixelated detectors, where several functions need to be packed inside a relatively small silicon area. Nowadays, processes with 130nm minimum channel length are widely available for Application Specific Integrated Circuits (ASICs)

M. Manghisoni; L. Gaioni; L. Ratti; V. Re; G. Traversi

2010-01-01

21

An Acetone Microsensor with a Ring Oscillator Circuit Fabricated Using the Commercial 0.18 ?m CMOS Process  

PubMed Central

This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is ?-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the ?-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm. PMID:25036331

Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

2014-01-01

22

CMOS monolithic sensors in a homogeneous 3D process for low energy particle imaging  

Microsoft Academic Search

A 3D, through silicon via microelectronic process, capable of face-to-face assembling two 130 nm CMOS tiers in a single bi-layer wafer, has been exploited for the design of monolithic active pixels (MAPS), featuring a deep N-well (DNW) collecting electrode. They are expected to improve on planar CMOS DNW MAPS in terms of charge collection efficiency since most of the PMOS

Lodovico Ratti; Massimo Caccia; Luigi Gaioni; Alessia Manazza; Massimo Manghisoni; Valerio Re; Gianluca Traversi; Stefano Zucca

2010-01-01

23

Radiation Characteristics of a 0.11 Micrometer Modified Commercial CMOS Process  

NASA Technical Reports Server (NTRS)

We present radiation data, Total Ionizing Dose and Single Event Effects, on the LSI Logic 0.11 micron commercial process and two modified versions of this process. Modified versions include a buried layer to guarantee Single Event Latchup immunity.

Poivey, Christian; Kim, Hak; Berg, Melanie D.; Forney, Jim; Seidleck, Christina; Vilchis, Miguel A.; Phan, Anthony; Irwin, Tim; LaBel, Kenneth A.; Saigusa, Rajan K.; Mirabedini, Mohammad R.; Finlinson, Rick; Suvkhanov, Agajan; Hornback, Verne; Sung, Jun; Tung, Jeffrey

2006-01-01

24

CMOS IC Fabrication Issues for High-k Gate Dielectric and Alternate Electrode Materials  

Microsoft Academic Search

Silicon dioxide based dielectrics such as SiO2 and nitrided SiO 2 (SiON) are reaching the limit of their usefulness in complementary metal oxide semiconductor (CMOS) devices principally because of high tunnel currents. The semiconductor industry has adopted SiON at the 130 nm node where equivalent oxide thicknesses less than 2 nm are typically used for the high-performance devices. But SiON

L. Colombo; A. L. P. Rotondaro; M. R. Visokay; J. J. Chambers

25

The Impact of Gate-Oxide Breakdown on Common-Source Amplifiers With Diode-Connected Active Load in Low-Voltage CMOS Processes  

Microsoft Academic Search

The influence of gate-oxide reliability on common-source amplifiers with diode-connected active load is investigated with the nonstacked and stacked structures under analog application in a 130-nm low-voltage CMOS process. The test conditions of this work include the dc stress, ac stress with dc offset, and large-signal transition stress under different frequencies and signals. After overstresses, the small-signal parameters, such as

Jung-Sheng Chen; Ming-Dou Ker

2007-01-01

26

3D monolithically stacked CMOS Active Pixel Sensors for particle position and direction measurements  

NASA Astrophysics Data System (ADS)

In this work we propose a 3D monolithically stacked, multi-layer detectors based on CMOS Active Pixel Sensors (APS) layers which allows at the same time accurate estimation of the impact point and of the incidence angle an ionizing particle. The whole system features two fully-functional CMOS APS matrix detectors, including both sensing area and control/signal elaboration circuitry, stacked in a monolithic device by means of Through Silicon Via (TSV) connections thanks to the capabilities of the CMOS vertical scale integration (3D-IC) 130 nm Chartered/Tezzaron technology. In order to evaluate the suitability of the two layer monolithic active pixel sensor system to reconstruct particle tracks, tests with proton beams have been carried out at the INFN LABEC laboratories in Florence (Italy) with 3 MeV proton beam.

Servoli, L.; Passeri, D.; Morozzi, A.; Magalotti, D.; Piperku, L.

2015-01-01

27

Graphene/Si CMOS Hybrid Hall Integrated Circuits  

PubMed Central

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18?um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

28

Improving CMOS-compatible Germanium photodetectors.  

PubMed

We report design improvements for evanescently coupled Germanium photodetectors grown at low temperature. The resulting photodetectors with 10 ?m Ge length manufactured in a commercial CMOS process achieve >0.8 A/W responsivity over the entire C-band, with a device capacitance of <7 fF based on measured data. PMID:23187489

Li, Guoliang; Luo, Ying; Zheng, Xuezhe; Masini, Gianlorenzo; Mekis, Attila; Sahni, Subal; Thacker, Hiren; Yao, Jin; Shubin, Ivan; Raj, Kannan; Cunningham, John E; Krishnamoorthy, Ashok V

2012-11-19

29

Micromachined coplanar waveguides in CMOS technology  

Microsoft Academic Search

Coplanar waveguides were fabricated in standard complimentary metal-oxide semiconductor (CMOS) with postprocessing micromachining. ICs were designed with commercial CAD tools, fabricated through the MOSIS service, and subsequently suspended by maskless top-side etching. Absence of the lossy silicon substrate after etching results in significantly improved insertion loss characteristics, dispersion characteristics, and phase velocity. Measurements were performed at frequencies from 1 to

Veljko MilanoviC; Michael Gaitan; Edwin D. Bowen; Mona E. Zaghloul

1996-01-01

30

25Gb/s 1V-driving CMOS ring modulator with integrated thermal tuning.  

PubMed

We report a high-speed ring modulator that fits many of the ideal qualities for optical interconnect in future exascale supercomputers. The device was fabricated in a 130 nm SOI CMOS process, with 7.5 ?m ring radius. Its high-speed section, employing PN junction that works at carrier-depletion mode, enables 25 Gb/s modulation and an extinction ratio >5 dB with only 1V peak-to-peak driving. Its thermal tuning section allows the device to work in broad wavelength range, with a tuning efficiency of 0.19 nm/mW. Based on microwave characterization and circuit modeling, the modulation energy is estimated ~7 fJ/bit. The whole device fits in a compact 400 ?m2 footprint. PMID:21997052

Li, Guoliang; Zheng, Xuezhe; Yao, Jin; Thacker, Hiren; Shubin, Ivan; Luo, Ying; Raj, Kannan; Cunningham, John E; Krishnamoorthy, Ashok V

2011-10-10

31

Micromachined microwave transmission lines in CMOS technology  

Microsoft Academic Search

Coplanar waveguides were designed and fabricated through a commercial CMOS process with post-processing micromachining. The transmission-line layouts were designed with commercial computer-aided design (CAD) tools. Integrated circuits (ICs) were fabricated through the MOSIS service, and subsequently suspended by top-side etching. The absence of the lossy silicon substrate after etching results in significantly improved insertion-loss characteristics, dispersion characteristics, and phase velocity.

V. Milanovic; M. Gaitan; E. D. Bowen; M. E. Zaghloul

1997-01-01

32

High voltage vs. high integration: a comparison between CMOS technologies for SPAD cameras  

NASA Astrophysics Data System (ADS)

In the last years the fabrication of SPAD cameras has become one of the main fields of interest in 3-D imaging and bioapplications. In this paper we present the comparison between two standard CMOS technologies to fabricate SPADs cameras. The two technologies used in the comparison are a high voltage 0.35?m technology from AMS and a high integration 130nm technology from STM. The advantage of using a standard CMOS technology among a dedicated is the possibility of integrating the control/reading electronics into the same die. Neither of the processes is optimized for optical applications, and no post-processing has been applied to improve the features. The technologies have been selected due to the different integration density, and different intrinsic process parameters with similar cost. Comparison has been done by fabricating several structures in both technologies which allow analyzing sensibility, noise, and time response. Experimental results show that the high voltage technology has a lower level of dark counts than the 130nm. Instead, the high integration technology has a shorter quenching time, 1.5ns, which reduces the afterpulsing events to a negligible level. In optical applications it is important to have a high integration of the camera reducing the pitch of the pixel, while noise effects can be corrected in post-processing. For low frequency events, such as high energetic particle tracking, the noise frequency has to be lower, but it is also required a high fill factor. Depending on the specific application this analysis allows to opt for the most suitable technology.

Arbat, A.; Comerma, A.; Trenado, J.; Gascon, D.; Vilà, A.; Garrido, L.; Dieguez, A.

2010-08-01

33

Ion traps fabricated in a CMOS foundry  

NASA Astrophysics Data System (ADS)

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

Mehta, K. K.; Eltony, A. M.; Bruzewicz, C. D.; Chuang, I. L.; Ram, R. J.; Sage, J. M.; Chiaverini, J.

2014-07-01

34

Ion traps fabricated in a CMOS foundry  

E-print Network

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, in any modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

K. K. Mehta; A. M. Eltony; C. D. Bruzewicz; I. L. Chuang; R. J. Ram; J. M. Sage; J. Chiaverini

2014-06-13

35

Wanlass's CMOS circuit  

Microsoft Academic Search

The invention of complementary-MOS (CMOS) logic circuitry by Frank Wanlass in 1963 is recounted. The difficulties encountered by Wanlass in an attempt to make stable silicon MOSFETs and how they led him to the CMOS circuit are described. The first demonstration circuit, a two-transistor inverter, consumed just a few nanowatts of standby power and exhibited propagation delay times on the

M. J. Riezenman

1991-01-01

36

CMOS active pixel image sensors for highly integrated imaging systems  

Microsoft Academic Search

A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-?m CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression

Sunetra K. Mendis; Sabrina E. Kemeny; Russell C. Gee; Bedabrata Pain; Craig O. Staller; Quiesup Kim; Eric R. Fossum

1997-01-01

37

Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis  

Microsoft Academic Search

FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0\\/1 fault model. Faults

John Paul Shen; F. Joel Ferguson

1988-01-01

38

All-CMOS night vision viewer with integrated microdisplay  

NASA Astrophysics Data System (ADS)

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 ?m CMOS process, with no process alterations or post processing. The display features a 25 ?m pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

2014-02-01

39

Monolithic CMUT on CMOS Integration for Intravascular Ultrasound Applications  

PubMed Central

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array. PMID:23443701

Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F. Levent

2012-01-01

40

Test structures to measure the Seebeck coefficient of CMOS IC polysilicon  

Microsoft Academic Search

We report on two thermal characterization structures to measure the Seebeck coefficient ? of CMOS IC polysilicon thin films relevant for integrated thermal microtransducers. The test structures were fabricated using a commercial 1.2 ?m CMOS process of Austria Mikro Systeme (AMS). The fabrication of the first structure relies on silicon micromachining. In contrast the second, planar, structure is ready for

M. Von Arx; O. Paul; Henry Baltes

1997-01-01

41

Characterization of broad-band transmission for coplanar waveguides on CMOS silicon substrates  

Microsoft Academic Search

This paper presents characteristics of microwave transmission in coplanar waveguides (CPW's) on silicon (Si) substrates fabricated through commercial CMOS foundries. Due to the CMOS fabrication, the metal strips of the CPW are encapsulated in thin films of Si dioxide. Many test sets were fabricated with different line dimensions, all on p-type substrates with resistivities in the range from 0.4 ?·cm

Veljko Milanovic; Mehmet Ozgur; Donald C. DeGroot; Jeffrey A. Jargon; Michael Gaitan; Mona E. Zaghloul

1998-01-01

42

High-speed multicolour photometry with CMOS cameras  

NASA Astrophysics Data System (ADS)

We present the results of testing the commercial digital camera Nikon D90 with a CMOS sensor for high-speed photometry with a small telescope Celestron 11'' at the Peak Terskol Observatory. CMOS sensor allows to perform photometry in 3 filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system of CMOS sensors is close to the Johnson BVR system. The results of testing show that one can carry out photometric measurements with CMOS cameras for stars with the V-magnitude up to ?14^{m} with the precision of 0.01^{m}. Stars with the V-magnitude up to ˜10 can be shot at 24 frames per second in the video mode.

Pokhvala, S. M.; Zhilyaev, B. E.; Reshetnyk, V. M.

2012-11-01

43

CMOS MEMS capacitive absolute pressure sensor  

NASA Astrophysics Data System (ADS)

This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal-oxide-semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa-1 in the pressure range of 0-300 kPa.

Narducci, M.; Yu-Chia, L.; Fang, W.; Tsai, J.

2013-05-01

44

Advances in CMOS solid-state photomultipliers for scintillation detector applications  

Microsoft Academic Search

Solid-state photomultipliers (SSPMs) are a compact, lightweight, potentially low-cost alternative to a photomultiplier tube for a variety of scintillation detector applications, including digital-dosimeter and medical-imaging applications. Manufacturing SSPMs with a commercial CMOS process provides the ability for rapid prototyping, and facilitates production to reduce the cost. RMD designs CMOS SSPM devices that are fabricated by commercial foundries. This work describes

James F. Christian; Christopher J. Stapels; Erik B. Johnson; Mickel McClish; Purushotthom Dokhale; Kanai S. Shah; Sharmistha Mukhopadhyay; Eric Chapman; Frank L. Augustine

2010-01-01

45

CMOS Bridging Fault Detection  

Microsoft Academic Search

The authors compare the performance of two test generation techniques, stuck fault testing and current testing, when applied to CMOS bridging faults. Accurate simulation of such faults mandated the development of several new design automation tools, including an analog-digital fault simulator. The results of this simulation are analyzed. It is shown that stuck fault test generation, while inherently incapable of

Thomas M. Storey; Wojciech Maly

1990-01-01

46

Implantable CMOS Biomedical Devices  

PubMed Central

The results of recent research on our implantable CMOS biomedical devices are reviewed. Topics include retinal prosthesis devices and deep-brain implantation devices for small animals. Fundamental device structures and characteristics as well as in vivo experiments are presented. PMID:22291554

Ohta, Jun; Tokuda, Takashi; Sasagawa, Kiyotaka; Noda, Toshihiko

2009-01-01

47

Total-Ionizing-Dose Effects in Modern CMOS Technologies  

Microsoft Academic Search

This review paper discusses several key issues associated with deep submicron CMOS devices as well as advanced semiconductor materials in ionizing radiation environments. There are, as outlined in the ITRS roadmap, numerous challenges ahead for commercial industry in its effort to track Moore's Law down to the 45 nm node and beyond. While many of the classical threats posed by

H. J. Barnaby

2006-01-01

48

CMOS Gates Demonstration  

NSDL National Science Digital Library

This website, hosted by the University of Hamburg, provides an in depth description of the basic operation of CMOS circuits including inverters, NAND gates, and NOR gates. Circuit simulations are shown and power dissipation is discussed. Some of these include: inverters, NAND and NOR gates, transmission gates, D-latch with T-gates, power consumption, complex gates and SRAM cells. Overall, the site is perfect for undergraduate computer science majors to learn more about the exciting topic of semiconductors.

49

Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments  

E-print Network

CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Castro, Xitzel Sanchez; Winter, Marc

2014-01-01

50

Characterization of a CMOS sensing core for ultra-miniature wireless implantable temperature sensors with application to cryomedicine.  

PubMed

In effort to improve thermal control in minimally invasive cryosurgery, the concept of a miniature, wireless, implantable sensing unit has been developed recently. The sensing unit integrates a wireless power delivery mechanism, wireless communication means, and a sensing core-the subject matter of the current study. The current study presents a CMOS ultra-miniature PTAT temperature sensing core and focuses on design principles, fabrication of a proof-of-concept, and characterization in a cryogenic environment. For this purpose, a 100 ?m × 400 ?m sensing core prototype has been fabricated using a 130 nm CMOS process. The senor has shown to operate between -180°C and room temperature, to consume power of less than 1 ?W, and to have an uncertainty range of 1.4°C and non-linearity of 1.1%. Results of this study suggest that the sensing core is ready to be integrated in the sensing unit, where system integration is the subject matter of a parallel effort. PMID:25001173

Khairi, Ahmad; Thaokar, Chandrajit; Fedder, Gary; Paramesh, Jeyanandh; Rabin, Yoed

2014-09-01

51

Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.  

SciTech Connect

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materials integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.

Sumant, A.V.; Auciello, O.; Yuan, H.-C; Ma, Z.; Carpick, R. W.; Mancini, D. C.; Univ. of Wisconsin; Univ. of Pennsylvania

2009-05-01

52

Design and Fabrication of Vertically-Integrated CMOS Image Sensors  

PubMed Central

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Skorka, Orit; Joseph, Dileepan

2011-01-01

53

CMOS Avalanche Photodiode Embedded in a Phase-Shift Laser Rangefinder  

Microsoft Academic Search

This paper presents the design and the characterization of a CMOS avalanche photodiode (APD) working as an optoelectronic mixer. The P+N photodiode has been implemented in a commercial 0.35-mum CMOS technology after optimization with SILVACO. The surface of the active region is 3.78 middot10-3 cm2. An efficient guard-ring structure has been created using the lateral diffusion of two n-well regions

Emmanuel R. Moutaye; Hélène Tap-Beteille

2008-01-01

54

CMOS-Based Biosensor Arrays  

E-print Network

CMOS-based sensor array chips provide new and attractive features as compared to today's standard tools for medical, diagnostic, and biotechnical applications. Examples for molecule- and cell-based approaches and related circuit design issues are discussed.

Thewes, R; Schienle, M; Hofmann, F; Frey, A; Brederlow, R; Augustyniak, M; Jenkner, M; Eversmann, B; Schindler-Bauer, P; Atzesberger, M; Holzapfl, B; Beer, G; Haneder, T; Hanke, H -C

2011-01-01

55

Micro FET pressure sensor manufactured using CMOS-MEMS technique  

Microsoft Academic Search

The fabrication of a micro field effect transistor (FET) pressure sensor using the commercial 0.35?m complementary metal oxide semiconductor (CMOS) process and a post-process has been investigated. The pressure sensor is composed of 16 sensing cells in parallel, and each sensing cell includes a suspended membrane and an NMOS. The suspended membrane is the movable gate of the NMOS. The

Ching-Liang Dai; Pin-Hsu Kao; Yao-Wei Tai; Chyan-Chyi Wu

2008-01-01

56

CMOS foundry implementation of Schottky diodes for RF detection  

Microsoft Academic Search

Schottky diodes for RF power measurement were designed and fabricated using a commercial n-well CMOS foundry process through the MOSIS service. The Schottky diodes are implemented by modifying the SCMOS technology file of the public-domain graphics layout editor, MAGIC, or by explicitly implementing the appropriate CIF layers. The modifications allow direct contact of first-layer metal to the low-doped substrate. Current-voltage

Veljko MilanoviC; Michael Gaitan; Janet C. Marshall; Mona E. Zaghloul

1996-01-01

57

Large Format CMOS-based Detectors for Diffraction Studies  

NASA Astrophysics Data System (ADS)

Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 ?m × 100 ?m are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 ?m × 100 ?m pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at reasonable cost.

Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

2013-03-01

58

Proof of principle study of the use of a CMOS active pixel sensor for proton radiography  

SciTech Connect

Purpose: Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). Methods: A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissue contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Results: Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Conclusion: Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The development and use of CMOS in proton radiography could allow in vivo proton range checks, patient setup QA, and real-time tumor tracking.

Seco, Joao; Depauw, Nicolas [Francis H. Burr Proton Therapy Center, Department of Radiation Oncology, Massachusetts General Hospital (MGH), Boston, Massachusetts 02114 (United States)

2011-02-15

59

Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators  

PubMed Central

This work presents a thermoelectric micro generator fabricated by the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 ?V at the temperature difference of 1 K. PMID:22205869

Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

2010-01-01

60

CMOS passive pixel image design techniques  

E-print Network

CMOS technology provides an attractive alternative to the currently dominant CCD technology for implementing low-power, low-cost imagers with high levels of integration. Two pixel configurations are possible in CMOS ...

Fujimori, Iliana L. (Iliana Lucia)

2002-01-01

61

Ge technology beyond Si CMOS  

NASA Astrophysics Data System (ADS)

To save energy, low voltage operation is the most important criterion for CMOS ICs. To reach this goal, high mobility new channel materials are required for CMOS ICs at <= 14 nm technology nodes. The high electron mobility InGaAs nMOSFET and high hole mobility Ge pMOSFET were proposed for CMOS at 0.5 V operation, since the poor hole mobility of InGaAs makes it unsuitable for all InGaAs CMOS. However, the epitaxial InGaAs nMOSFET on Si faces fundamental material challenges with large defects and high leakage current. Although dislocation-defects-free Ge-on-Insulator (GeOI), ultra-thin-body (UTB) InGaAs IIIV-on-Insulator (IIIVOI), and selective GeOI on Si were pioneered by us, it is still difficult to reach InGaAs-nMOS/Ge-pMOS CMOS targeting to <= 14 nm CMOS. In contrast, Ge is the ideal candidate for all Ge CMOS logic due to both higher electron and hole mobility than Si. Significantly higher (2.6X) hole mobility of GeOI pMOSFET than universal SiO2/Si value was reached at a medium 0.5 MV/cm effective electric field (Eejf) and 1.4 nm equivalent-oxide-thickness (EOT). Nevertheless, the Ge nMOSFET suffers from large EOT and fast mobility degradation with increasing Eeff, due to the surface Fermi-level pinning to valance band, poor high-?/Ge interface and low dopant activation. Using novel laser annealing and proper gate stack, small EOT of 0.95 nm, small sub-threshold swing of 106 mV/dec, and 40% better high-field mobility than universal SiO2/Si data were achieved in Ge nMOSFET. Such all-Ge CMOS has irreplaceable merits of much simpler process, lower cost, and potentially higher yield than the InGaAs-nMOS/Ge-pMOS CMOS platform.

Chin, Albert

2012-12-01

62

CMOS Circuit Speed and Buffer Optimization  

Microsoft Academic Search

An improved timing model for CMOS combinational logic is presented. The model is based on an analytical solution for the CMOS inverter output response to an input ramp. This model yields a better understanding of the switching behavior of the CMOS inverter than the step-response model by considering the slope of the input waveform. Essentially, the propagation delay is shown

Nils Hedenstierna; Kjell O. Jeppson

1987-01-01

63

A back-illuminated megapixel CMOS image sensor  

NASA Technical Reports Server (NTRS)

In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

2005-01-01

64

Low Power CMOS Digital Design  

Microsoft Academic Search

: Motivated by emerging battery operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit and technology optimizations. An architectural based scaling strategy is presented which

Anantha P. Chandrakasan; Samuel Sheng; Robert W. Brodersen

1995-01-01

65

Integration of solid-state nanopores in a 0.5 ?m CMOS foundry process  

NASA Astrophysics Data System (ADS)

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Uddin, A.; Yemenicioglu, S.; Chen, C.-H.; Corigliano, E.; Milaninia, K.; Theogarajan, L.

2013-04-01

66

Integration of solid-state nanopores in a 0.5 ?m CMOS foundry process.  

PubMed

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

67

TDC-based frequency synthesizer for wireless applications  

Microsoft Academic Search

We analyze phase noise performance and further discuss details of an all-digital PLL that is used in a commercial 130 nm CMOS single-chip Bluetooth radio. The frequency synthesizer uses a digitally controlled oscillator with a digital loop filter and a time-to-digital converter that acts as a phase\\/frequency detector. When implemented in a deep-submicron CMOS, the presented architecture appears more advantageous

Robert Bogdan Staszewski; D. Leipold; Chih-Ming Hung; P. T. Balsara

2004-01-01

68

3180 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 21, NO. 12, DECEMBER 2003 Adaptive CMOS Predistortion Linearizer for  

E-print Network

3180 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 21, NO. 12, DECEMBER 2003 Adaptive CMOS Predistortion is commercially deployed in cable television (CATV), the cost of devices used in such links is an order to the following: 1) static nonlinearity; 2) dynamic nonlinearity; 3) nonlinearity due to overmodulation. Dynamic

Jalali. Bahram

69

Process-dependent thin-film thermal conductivities for thermal CMOS MEMS  

Microsoft Academic Search

The thermal conductivities ? of the dielectric and conducting thin films of three commercial CMOS processes were determined in the temperature range from 120 to 400 K. The measurements were performed using micromachined heatable test structures containing the layers to be characterized. The ? values of thermally grown silicon oxides are reduced from bulk fused silica by roughly 20%. The

Martin von Arx; Oliver Paul; Henry Baltes

2000-01-01

70

Digital-Centric RF CMOS Technologies  

NASA Astrophysics Data System (ADS)

Analog-centric RFCMOS technology has played an important role in motivating the change of technology from conventional discrete device technology or bipolar IC technology to CMOS technology. However it introduces many problems such as poor performance, susceptibility to PVT fluctuation, and cost increase with technology scaling. The most important advantage of CMOS technology compared with legacy RF technology is that CMOS can use more high performance digital circuits for very low cost. In fact, analog-centric RF-CMOS technology has failed the FM/AM tuner business and the digital-centric CMOS technology is becoming attractive for many users. It has many advantages; such as high performance, no external calibration points, high yield, and low cost. From the above facts, digital-centric CMOS technology which utilizes the advantages of digital technology must be the right path for future RF technology. Further investment in this technology is necessary for the advancement of RF technology.

Matsuzawa, Akira

71

Evolving Variability-Tolerant CMOS Designs  

Microsoft Academic Search

As the size of CMOS devices is approaching the atomic level, the increasing intrinsic device variability is leading to higher\\u000a failure rates in conventional CMOS designs. In this paper, two approaches are proposed for evolving unconventional variability-tolerent\\u000a CMOS designs: one uses a simple Genetic Algorithm, whilst the other uses Cartesian Genetic Programming. Both approaches successfully\\u000a evolve unconventional designs for logic

James Alfred Walker; James A. Hilder; Andy M. Tyrrell

2008-01-01

72

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices  

NASA Technical Reports Server (NTRS)

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

73

SPICE macromodel and CMOS emulator for memristors.  

PubMed

In this paper, a new SPICE macromodel and CMOS emulator for memristors are proposed and verified to fit to the memristor's model equation very well in the entire range of memristor's resistance from the RESET state to the SET state. Compared with the memristor's model equation, average percentage errors in the new SPICE macromodel and in the 4-bit CMOS emulator are less than 0.5% and 0.9%, respectively. In addition, the CMOS emulator for memristors which can be implemented by a CMOS circuit will be very useful to design and verify various peripheral circuits for memristor applications particularly when the memristor fabrication process is not ready. PMID:22629985

Jung, Chul-Moon; Jo, Kwan-Hee; Min, Kyeong-Sik

2012-02-01

74

Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics  

SciTech Connect

Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm{sup 2} with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensors are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.

Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka; Pithawa, C. K. [Centre for Microelectronics, Prabhadevi, Mumbai-400028 (India)

2011-10-20

75

Thermoelectric infrared sensors by CMOS technology  

Microsoft Academic Search

The authors report two integrated thermoelectric infrared sensors on thin silicon oxide\\/nitride microstructures realized by industrial CMOS IC technology, followed by one compatible single maskless anisotropic etching step. No additional material is needed to enhance infrared absorption since the passivation layer, as provided by the CMOS process, is sufficient for certain spectral bands. The responsivities are between 12 and 28

Rene Lenggenhager; Henry Baltes; Jon Peer; Martin Forster

1992-01-01

76

A CMOS surface micromachined pressure sensor  

Microsoft Academic Search

A capacitive pressure sensor has been implemented by the industrial standard 0.8?m CMOS (Complementary metal oxide semiconductor) process. The device layout follows the entire set of CMOS IC (Integrated circuit) design rules. The sensing capacitor of the capacitive pressure sensor is composed of the upper metal (metal 2) and the polysilicon layer. The lower metal layer (metal 1) serves as

1999-01-01

77

RF MEMS components using CMOS technology  

Microsoft Academic Search

Recently microelectromechanical systems (MEMS) devices have become an important technology that is used in many applications. We describe post-processing steps of CMOS technology to implement a MEMS structure suitable for RF systems. We describe CMOS-based monolithic MEMS structures suitable for realizing passive RF components operating at frequencies of up to 60 GHz. Examples of RF MEMS components - inductors, switches

Mehmet Ozgur; Mona E. Zaghloul

2001-01-01

78

CMOS foveal image sensor chip  

NASA Technical Reports Server (NTRS)

A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

2002-01-01

79

CMOS Imaging Detectors as X-ray Detectors for Synchrotron Radiation Experiments  

NASA Astrophysics Data System (ADS)

CMOS imagers are matrix-addressed photodiode arrays, which have been utilized in devices such as commercially available digital cameras. The pixel size of CMOS imagers is usually larger than that of CCD and smaller than that of TFT, giving them a unique position. Although CMOS x-ray imaging devices have already become commercially available, they have not been used as an x-ray area detector in synchrotron radiation experiments. We tested performance of a CMOS detector from Rad-icon (Shad-o-Box1024) in medical imaging, small-angle scattering, and protein crystallography experiments. It has pixels of 0.048 mm square, read-out time of 0.45 sec, 12-bit ADC, and requires a frame grabber for image acquisition. The detection area is 5-cm square. It uses a Kodak Min-R scintillator screen as a phosphor. The sensitivity to x-rays with an energy less than 15 keV was low because of the thick window materials. Since the readout noise is high, the dynamic range is limited to 2000. The biggest advantages of this detector are cost-effectiveness (about 10,000 US dollars) and compactness (thickness < 3 cm, weight < 2 kg).

Yagi, Naoto; Yamamoto, Masaki; Uesugi, Kentaro; Inoue, Katsuaki

2004-05-01

80

Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments  

E-print Network

CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity epitaxial layers leads to the better radiation hardness and allows the implementation of accelerated readout circuits. The TowerJazz $0.18 \\mu m$ CMOS process being one of the most relevant examples recently became of interest for several future detector projects. The most imminent of these project is an upgrade of the Inner Tracking System (ITS) of the ALICE detector at LHC. It will be followed by the Micro-Vertex Detector (MVD) of the CBM experiment at FAIR. Other experiments like ILD consider CPS as one of the viable options for flavour tagging and tracking sub-systems.

Serhiy Senyukov; Jerome Baudot; Auguste Besson; Giles Claus; Loic Cousin; Wojciech Dulinski; Mathieu Goffe; Boris Hippolyte; Robert Maria; Levente Molnar; Xitzel Sanchez Castro; Marc Winter

2014-02-10

81

Low-loss and low-crosstalk 8 × 8 silicon nanowire AWG routers fabricated with CMOS technology.  

PubMed

Low-loss and low-crosstalk 8 × 8 arrayed waveguide grating (AWG) routers based on silicon nanowire waveguides are reported. A comparative study of the measurement results of the 3.2 nm-channel-spacing AWGs with three different designs is performed to evaluate the effect of each optimal technique, showing that a comprehensive optimization technique is more effective to improve the device performance than a single optimization. Based on the comprehensive optimal design, we further design and experimentally demonstrate a new 8-channel 0.8 nm-channel-spacing silicon AWG router for dense wavelength division multiplexing (DWDM) application with 130 nm CMOS technology. The AWG router with a channel spacing of 3.2 nm (resp. 0.8 nm) exhibits low insertion loss of 2.32 dB (resp. 2.92 dB) and low crosstalk of -20.5~-24.5 dB (resp. -16.9~-17.8 dB). In addition, sophisticated measurements are presented including all-input transmission testing and high-speed WDM system demonstrations for these routers. The functionality of the Si nanowire AWG as a router is characterized and a good cyclic rotation property is demonstrated. Moreover, we test the optical eye diagrams and bit-error-rates (BER) of the de-multiplexed signal when the multi-wavelength high-speed signals are launched into the AWG routers in a system experiment. Clear optical eye diagrams and low power penalty from the system point of view are achieved thanks to the low crosstalk of the AWG devices. PMID:24787827

Wang, Jing; Sheng, Zhen; Li, Le; Pang, Albert; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Qi, Minghao; Gan, Fuwan

2014-04-21

82

Neutron spectrum and dose in a CMOS  

NASA Astrophysics Data System (ADS)

Using Monte Carlo methods the neutron spectrum in a pacemaker's CMOS has been estimated. A 18 MV LINAC model was used to expose a cell used to define the prostate located in a tissue equivalent phantom model. Neutron fluence at the CMOS is 2.6E(7) n/cm2-Gyx, the spectrum has thermal, epithermal and fast neutrons that will induce secondary, low and high LET, particles whose ionization could induce malfunction and failure of pacemaker in the oncological patient.

Vega-Carrillo, H. R.; Paredes-Gutierrez, L.; Borja-Hernandez, C. G.

2012-10-01

83

CMOS scaling into the nanometer regime  

Microsoft Academic Search

Starting with a brief review on 0.1-?m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect

Yuan Taur; DOUGLAS A. BUCHANAN; Wei Chen; DAVID J. FRANK; KHALID E. ISMAIL; Shih-Hsien Lo; G. A. Sai-Halasz; R. G. Viswanathan; H.-J. C. Wann; S. J. Wind; Hon-Sum Wong

1997-01-01

84

Tin oxide gas sensor fabricated using CMOS micro-hotplates and in-situ processing  

Microsoft Academic Search

A monolithic tin oxide (SnO2) gas sensor realized by commercial CMOS foundry fabrication (MOSIS) and postfabrication processing techniques is reported. The device is composed of a sensing film that is sputter-deposited on a silicon micromachined hotplate. The fabrication technique requires no masking and utilizes in situ process control and monitoring of film resistivity during film growth. Microhotplate temperature is controlled

John S. Suehle; Richard E. Cavicchi; Michael Gaitan; Steve Semancik

1993-01-01

85

A CMOS smart temperature and humidity sensor with combined readout.  

PubMed

A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 ?m CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA. PMID:25230305

Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

2014-01-01

86

A CMOS Smart Temperature and Humidity Sensor with Combined Readout  

PubMed Central

A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 ?m CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 ?A. PMID:25230305

Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

2014-01-01

87

Emitter coupled logic testability analysis and comparison with CMOS & BiCMOS circuits  

Microsoft Academic Search

The logic behavior and performance of an ECL OR\\/NOR gate under a set of defect models are examined. These are compared with equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaining a sufficiently high fault coverage. Performance degradation faults such as delay, current and voltage transfer characteristics (VTC) or noise margin

D. Al-Khalili; M. O. Esonu; C. Rozon

1993-01-01

88

Low-voltage log-domain signal processing in CMOS and BiCMOS  

Microsoft Academic Search

This paper presents the most important properties of log-domain filters for the realization of low-voltage and low power analog signal processing circuits. The noise behavior is discussed and the advantage of the combination of companding and class AB operation is highlighted. Examples of BiCMOS and CMOS realizations operating at supply voltages as low as 1 V are presented

Christian Enz; Manfred Punzenberger; Dominique Python

1999-01-01

89

Radiation Test Challenges for Scaled Commercial Memories  

Microsoft Academic Search

As sub-100 nm CMOS technologies gather interest, the radiation effects performance of these technologies provide a significant challenge. In this paper, we shall discuss the radiation testing challenges as related to commercial memory devices. The focus will be on complex test and failure modes emerging in state-of-the-art flash non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs), which are

Kenneth A. LaBel; Ray L. Ladbury; Lewis M. Cohn; Timothy R. Oldham

2008-01-01

90

Integrating Security Solutions to Support nanoCMOS Electronics Research .  

E-print Network

??The UK Engineering and Physical Sciences Research Council (EPSRC) funded Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS) is developing a research infrastructure for collaborative… (more)

SINNOTT, RICHARD

2008-01-01

91

CMOS image sensors: electronic camera-on-a-chip  

Microsoft Academic Search

CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed

Eric R. Fossum

1997-01-01

92

LOW VOLTAGE ANALOG CIRCUITS USING STANDARD CMOS TECHNOLOGY  

E-print Network

LOW VOLTAGE ANALOG CIRCUITS USING STANDARD CMOS TECHNOLOGY Phillip E. Allen, Benjamin J. Blalock, and Gabriel A. Rincon School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta supply voltages in CMOS integrated circuits. As the channel lengths of CMOS technology decrease

Rincon-Mora, Gabriel A.

93

CMOS Photovoltaic-cell Layout Configurations for Harvesting Microsystems  

E-print Network

CMOS Photovoltaic-cell Layout Configurations for Harvesting Microsystems Rajiv Damodaran Prabha, and radiation, photovoltaic (PV) systems are appealing options. Still, chip-sized CMOS PV cells produce only well in substrate cell are better. Index Terms--Ambient light energy, harvester, CMOS photovoltaic (PV

Rincon-Mora, Gabriel A.

94

Electrostatic Modeling of CMOS sensor array 1 Computing Security  

E-print Network

Electrostatic Modeling of CMOS sensor array 1 1 Computing Security Distributed System to establish 2-way authentication. #12;Electrostatic Modeling of CMOS sensor array 2 4 Port Protection (2 to Hades. #12;Electrostatic Modeling of CMOS sensor array 3 7 Kerberos Tickets Used for authentication

Cukic, Bojan

95

Floating-body effects in partially depleted SOI CMOS circuits  

Microsoft Academic Search

This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on

Pong-Fei Lu; Ching-Te Chuang; Jin Ji; Lawrence F. Wagner; Chang-Ming Hsieh; J. B. Kuang; L. L.-C. Hsu; S.-F. S. Chu; C. J. Anderson

1997-01-01

96

Towards evolving industry-feasible intrinsic variability tolerant CMOS designs  

Microsoft Academic Search

As the size of CMOS devices is approaching the atomic level, the increasing intrinsic device variability is leading to higher failure rates in conventional CMOS designs. This paper introduces a design tool capable of evolving CMOS topologies using a modified form of Cartesian genetic programming and a multi-objective strategy. The effect of intrinsic variability within the design is then analysed

James Alfred Walker; James A. Hilder; Andy M. Tyrrell

2009-01-01

97

Resistor Extends Life Of Battery In Clocked CMOS Circuit  

NASA Technical Reports Server (NTRS)

Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

Wells, George H., Jr.

1991-01-01

98

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors  

PubMed Central

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

99

Optically Addressed CMOS Spatial Light Modulators.  

NASA Astrophysics Data System (ADS)

The thesis focuses on optically addressed spatial light modulators that consist of a complementary-metal -on-silicon (CMOS) backplane and a ferroelectric liquid crystal modulator. The CMOS chip contains combinations of photodetectors, analog/digital electronics, and liquid crystal modulators. In this manner, information is optically written to and from the spatial light modulator. This technology allows custom spatial light modulators to be easily designed and fabricated that can perform specialized functions in optoelectronic computing architectures. Three different optically addressed CMOS spatial light modulators are presented: a thresholding spatial light modulator, a pulse frequency modulated spatial light modulator, and a zero-crossing edge detection spatial light modulator. Experimental results are present for each device along with a discussion of fabrication and system issues.

Jared, David Allen

100

IBM: Scaling CMOS to the Limit  

NSDL National Science Digital Library

This is the latest issue of the IBM Journal of Research and Development. "This double issue contains fifteen papers which address the challenges of scaling CMOS devices as physical limits are approached." Specifically, research teams report on topics such as silicon-on-insulator technology, new CMOS materials and device structures, dynamic random-access memory, and many others. The papers provide views of how far scaling could progress in the future and what constrains further advancement. Several back issues of the journal are also available, and each focuses on a different area of research.

2002-01-01

101

CMOS sensor for face tracking and recognition  

NASA Astrophysics Data System (ADS)

This paper describes the main principles of a vision sensor dedicated to the detecting and tracking faces in video sequences. For this purpose, a current mode CMOS active sensor has been designed using an array of pixels that are amplified by using current mirrors of column amplifier. This circuit is simulated using Mentor Graphics software with parameters of a 0.6 ?m CMOS process. The circuit design is added with a sequential control unit which purpose is to realise capture of subwindows at any location and any size in the whole image.

Ginhac, Dominique; Prasetyo, Eri; Paindavoine, Michel

2005-03-01

102

Optical addressing technique for a CMOS RAM  

NASA Technical Reports Server (NTRS)

Progress on optically addressing a CMOS RAM for a feasibility demonstration of free space optical interconnection is reported in this paper. The optical RAM chip has been fabricated and functional testing is in progress. Initial results seem promising. New design and SPICE simulation of optical gate cell (OGC) circuits have been carried out to correct the slow fall time of the 'weak pull down' OGC, which has been characterized experimentally. Methods of reducing the response times of the photodiodes and the associated circuits are discussed. Even with the current photodiode, it appears that an OGC can be designed with a performance that is compatible with a CMOS circuit such as the RAM.

Wu, W. H.; Bergman, L. A.; Allen, R. A.; Johnston, A. R.

1988-01-01

103

Low-voltage log-domain signal processing in CMOS and BiCMOS  

Microsoft Academic Search

This paper presents the most important properties of log-domain filters for the realization of low-voltage (LV) and low-power (LP) analog signal processing circuits. The noise behavior is briefly discussed and the advantage of the combination of companding and class AB operation is highlighted. Examples of BiCMOS and standard digital CMOS realizations operating at supply voltages as low as 1 V

C. C. Enz; M. Punzenberger; D. Python

1997-01-01

104

CMOS Avalanche Radio-over-Fiber wchoi@yonsei.ac.kr  

E-print Network

#12;#12;CMOS Avalanche Radio-over-Fiber , wchoi@yonsei.ac.kr CMOS Avalanche Photo-detector for Radio-over-Fiber Systems Yonsei Univ. 0.13um CMOS avalanche (avalanche photo-detector, APDF) [1-2]. RoF CMOS . CMOS GaAs responsivity . APD avalanche

Choi, Woo-Young

105

Decoupling capacitor calculations for CMOS circuits  

Microsoft Academic Search

CMOS circuits on printed circuit boards with continuous power planes require decoupling capacitors to keep power supply within specification, provide signal integrity and reduce EMC\\/EMI radiated noise. Capacitor values and quantities are calculated using time and frequency domain techniques

L. D. Smith

1994-01-01

106

Minimizing power consumption in digital CMOS circuits  

Microsoft Academic Search

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology

ANANTHA P. CHANDRAKASAN; ROBERT W. BRODERSEN

1995-01-01

107

Low energy CMOS for space applications  

NASA Technical Reports Server (NTRS)

The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

Panwar, Ramesh; Alkalaj, Leon

1992-01-01

108

Radiation Tolerance of 65nm CMOS Transistors  

E-print Network

We report on the effects of ionizing radiation on 65nm CMOS transistors held at approximately -20C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

Krohn, M; Cumalat, J P; Wagner, S R; Christian, D C; Deptuch, G; Fahim, F; Hoff, J; Shenai, A

2015-01-01

109

Radiation Tolerance of 65nm CMOS Transistors  

E-print Network

We report on the effects of ionizing radiation on 65nm CMOS transistors held at approximately -20C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

M. Krohn; B. Bentele; J. P. Cumalat; S. R. Wagner; D. C. Christian; G. Deptuch; F. Fahim; J. Hoff; A. Shenai

2015-01-23

110

Battery-Powered Digital CMOS Massoud Pedram  

E-print Network

Energy Applications 100 mWh~2 Wh Electric watches, calculators, implanted medical devices Batteries, camcorders, lap-top computers SLI Batteries (starting, lighting and ignition) 100~600 Wh Cars, trucks, buses1 Page 1 USC Low Power CAD Massoud Pedram Battery-Powered Digital CMOS Design Massoud Pedram

Pedram, Massoud

111

Silicon on sapphire CMOS for optoelectronic microsystems  

Microsoft Academic Search

we report on a hybrid integration approach that represents a paradigm shift from traditional optoelectronic integration and packaging methods. A recent metamorphosis and wider availability of silicon on sapphire CMOS VLSI technology is generating a great deal of excitement in the optoelectronic systems community as it offers simple and elegant solutions to the many system integration and packaging challenges that

A. G. Andreou; Z. K. Kalayjian; A. Apsel; P. O. Pouliquen; R. A. Athale; G. Simonis; R. Reedy

2001-01-01

112

Scatterometry measurement method for gate CD control of sub-130nm technology  

NASA Astrophysics Data System (ADS)

Recently, the scatterometry is becoming more and more popular as a inline metrology tool for lithography process control as well as etching process control because of the advantage of fast measurement with high accuracy. Especially, at the gate patterning that fabricates transistors, the scatterometry can be very powerful because it gives massive volume of CD (Critical Dimension) measurement data and gate poly profile, simultaneously. Those results could help to understand and forecast the performance of transistors. In order to achieve accurate and consistent measurement results by scatterometry, the setup of stable model and library is very crucial since it has nature of indirect measurement. For example, as defining of substrate conditions, modeling range of parameters, target values and type of models, scatterometry (in this paper, we call as OCD; Optical CD) gives different results even if we use same data basis. In this paper we have shown the best practice how to optimize variables of scatterometry to get accurate and stable results. We used the OCD(Optic CD: Accent CDS200) angular scatterometry system which can rotate HeNe laser light source from -47 to +47 degree. In order to investigate the substrate dependency, various silicon wafer substrates having periodic patterned with different materials such as photoresist, BARC, poly silicon, and thermal oxide film has been used. Finally, we observed OCD has the excellent capability for inline process controllability.

Jang, Jeongyeol; Kwak, Sungho; Lee, Karl; Kim, Keeho; Park, Heongsu; Youn, James; Sohn, Lucas

2005-05-01

113

Silicon Deformable Mirrors and CMOS-based Wavefront Sensors Justin D. Mansell, Peter B. Catrysse, Eric K. Gustafson, and Robert L. Byer  

E-print Network

Silicon Deformable Mirrors and CMOS-based Wavefront Sensors Justin D. Mansell, Peter B. Catrysse potential commercial applications for adaptive optics like laser beam control and ophthalmology. Silicon have implemented a new architecture of silicon deformable mirror designed to be low cost, have low

Byer, Robert L.

114

Ultra-low power high temperature and radiation hard complementary metal-oxide-semiconductor (CMOS) silicon-on-insulator (SOI) voltage reference.  

PubMed

This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of -40-200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage V(REF) depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 ?W at room temperature and only 75 ?W at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of V(REF) and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2. PMID:24351635

Boufouss, El Hafed; Francis, Laurent A; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

2013-01-01

115

Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference  

PubMed Central

This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of ?40–200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage VREF depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 ?W at room temperature and only 75 ?W at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of VREF and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2. PMID:24351635

Boufouss, El Hafed; Francis, Laurent A.; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

2013-01-01

116

77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...  

Federal Register 2010, 2011, 2012, 2013, 2014

...337-TA-846] Certain CMOS Image Sensors and Products Containing Same; Institution...after importation of certain CMOS image sensors and products containing same by reason...after importation of certain CMOS image sensors and products containing same that...

2012-06-06

117

77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...  

Federal Register 2010, 2011, 2012, 2013, 2014

...Docket No. 2895] Certain CMOS Image Sensors and Products Containing Same; Notice...complaint entitled Certain CMOS Image Sensors and Products Containing Same, DN 2895...after importation of certain CMOS image sensors and products containing same. The...

2012-05-07

118

A 0.13-?m CMOS serializer for data and trigger optical links in particle physics experiments  

Microsoft Academic Search

A 3.2-Gbit\\/s serializer prototype has been fabricated in a 0.13-?m CMOS technology to demonstrate its applicability within future Large Hadron Collider (LHC) data readout and trigger systems. The IC includes a clock-multiplying phase-locked-loop (PLL), a 50-? line driver, internal self-testing features, and data pattern generation. The serial output stream is 8 B\\/10 B encoded for compatibility with commercial receivers. Radiation

Giovanni Cervelli; Alessandro Marchioro; Paulo Moreira

2004-01-01

119

Ultra-fast high-resolution hybrid and monolithic CMOS imagers in multi-frame radiography  

NASA Astrophysics Data System (ADS)

A new burst-mode, 10-frame, hybrid Si-sensor/CMOS-ROIC FPA chip has been recently fabricated at Teledyne Imaging Sensors. The intended primary use of the sensor is in the multi-frame 800 MeV proton radiography at LANL. The basic part of the hybrid is a large (48×49 mm2) stitched CMOS chip of 1100×1100 pixel count, with a minimum shutter speed of 50 ns. The performance parameters of this chip are compared to the first generation 3-frame 0.5-Mpixel custom hybrid imager. The 3-frame cameras have been in continuous use for many years, in a variety of static and dynamic experiments at LANSCE. The cameras can operate with a per-frame adjustable integration time of ~ 120ns-to- 1s, and inter-frame time of 250ns to 2s. Given the 80 ms total readout time, the original and the new imagers can be externally synchronized to 0.1-to-5 Hz, 50-ns wide proton beam pulses, and record up to ~1000-frame radiographic movies typ. of 3-to-30 minute duration. The performance of the global electronic shutter is discussed and compared to that of a high-resolution commercial front-illuminated monolithic CMOS imager.

Kwiatkowski, Kris; Douence, Vincent; Bai, Yibin; Nedrow, Paul; Mariam, Fesseha; Merrill, Frank; Morris, Christopher L.; Saunders, Andy

2014-09-01

120

Analysis and optimization of BiCMOS digital circuit structures  

Microsoft Academic Search

Circuit analyses and performance optimization are presented of three basic BiCMOS digital circuit structures: BiCMOS buffer, NMOS\\/CML (coupled-mode logic), and ECL (emitter-coupled logic)\\/CMOS interface circuits. The analytical modeling of the transient behavior offers insight into the critical circuit and device parameters that affect the performance of these circuits. Techniques to improve the speed of each structure and the tradeoff factors

S. H. K. Embabi; A. Bellaouar; M. I. Elmasry

1991-01-01

121

Fundamental performance differences of CMOS and CCD imagers: part V  

NASA Astrophysics Data System (ADS)

Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

2013-02-01

122

Biomimetic sampling architectures for CMOS image sensors  

NASA Astrophysics Data System (ADS)

We demonstrate a non-orthogonal architecture for a CMOS active pixel image sensor, called here pyramid architecture, for improved two-dimensional spatial sampling. In the pyramid architecture 2D sampling using concentric rings replaces the 1D row sampling in the classical imager architecture, and diagonal output busses replace the conventional vertical column busses. Moreover, we propose a scanning scheme in which, instead of rolling over to the first ring (or row) at the end of image capture, the scan returns from the outer ring towards the first inner ring at the centre of the sensor. This leads to two scenes of differing integration times that, after being fused, results in a foveated increase in intra-scene dynamic range. Results from a sensor fabricated in 0.18?m CMOS technology are presented and discussed. We will also present a multi-resolution architecture which is based on the pixel structures as building block to control the acquired image resolution.

Saffih, Faycal; Hornsey, Richard

2004-06-01

123

Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL  

E-print Network

This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. A common CMOS FPGA-based logic core provides flexibility, adaptability, and communication with controlling computers while customized positive emitter-coupled logic (PECL) achieves multi-gigahertz data rates with about $\\pm$25ps timing accuracy.

Keezer, D C; Majid, A; Taher, N

2011-01-01

124

OPASYN: a compiler for CMOS operational amplifiers  

Microsoft Academic Search

A silicon compilation system for CMOS operational amplifiers (OPASYN) is discussed. The synthesis system takes as inputs system-level specifications, fabrication-dependent technology parameters, and geometric layout rules. It produces a design-rule-correct compact layout of an optimized operational amplifier. The synthesis proceeds in three stages: (1) heuristic selection of a suitable circuit topology; (2) parametric circuit optimization based on analytic models; and

Han Young Koh; Carlo H. Séquin; Paul R. Gray

1990-01-01

125

Thermoelectric AC power sensor by CMOS technology  

Microsoft Academic Search

The authors report the development of a thermoelectric AC power sensor (thermoconverter) realized by industrial CMOS IC technology in combination with postprocessing micromachining. The sensor is based on a polysilicon heating resistor and a polysilicon\\/aluminum thermopile integrated on an oxide microbridge. The thermopile sensitivity is 9.9 mV\\/mW and the burn-out power of the sensor is 50 mW. The time constant

Dominik Jaeggi; Henry Baltes; David Moser

1992-01-01

126

Advanced CMOS Radiation Effects Testing Analysis  

NASA Technical Reports Server (NTRS)

Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, Kenneth P.; Gordon, Michael S.; LaBel, Kenneth A.; Schwank, James R.; Dodds, Nathaniel A.; Castaneda, Carlos M.; Berg, Melanie D.; Kim, Hak S.; Phan, Anthony M.; Seidleck, Christina M.

2014-01-01

127

Monolithic high-speed CMOS-photoreceiver  

Microsoft Academic Search

Results of optoelectronic integrated CMOS receivers for applications in optical data transmission and in optical interconnects are presented. The rise and fall times of the integrated p-i-n photodiodes (PDs) are 0.19 and 0.24 ns, respectively, corresponding to -3 dB bandwidths in excess of 1.4 GHz. These PDs combine this high speed with a high quantum efficiency. Rise and fall times

H. Zimmermann; T. Heide; A. Ghazi

1999-01-01

128

Advanced CMOS Radiation Effects Testing and Analysis  

NASA Technical Reports Server (NTRS)

Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

2014-01-01

129

CMOS Camera Array With Onboard Memory  

NASA Technical Reports Server (NTRS)

A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

Gat, Nahum

2009-01-01

130

Single-chip CMOS optical microspectrometer  

Microsoft Academic Search

Numerous applications, e.g., systems for chemical analysis by optical absorption and emission line characterization, will benefit from the availability of low-cost single-chip spectrometers. A single-chip CMOS optical microspectrometer containing an array of 16 addressable Fabry–Perot etalons (each one with different resonance cavity length), photodetectors and circuits for read-out, multiplexing and driving a serial bus interface has been fabricated. The result

J. H. Correia; G. de Graaf; S. H. Kong; M. Bartek; R. F. Wolffenbuttel

2000-01-01

131

High-speed CMOS circuit technique  

Microsoft Academic Search

Ahtract -We have demonstrated that clock frequencies in ewes5 of 200 MHz are feasible in a 3-pm CMOS process. This is obtained by mean5 of clocking strategj, device sizing, and logic style selection. We use a precharge technique with a true single-phase clock, which remarkably increases the clock frequent) and reduces the skew problems, Device sizing with the help of

JIREN YUAN; CHRISTER SVENSSON

1989-01-01

132

Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design  

NASA Astrophysics Data System (ADS)

In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.

Shin, SangHak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

2013-11-01

133

Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design  

PubMed Central

In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory. PMID:24180626

2013-01-01

134

Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.  

PubMed

In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory. PMID:24180626

Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

2013-01-01

135

Envelope tracking CMOS power amplifier with high-speed CMOS envelope amplifier for mobile handsets  

NASA Astrophysics Data System (ADS)

A high-efficiency CMOS power amplifier (PA) based on envelope tracking (ET) has been reported for a wideband code division multiple access (W-CDMA) and long term evolution (LTE) application. By adopting a high-speed CMOS envelope amplifier with current direction sensing, a 5% improvement in total power-added efficiency (PAE) and a 11 dB decrease in adjacent channel leakage ratio (ACLR) are achieved with a W-CDMA signal. Moreover, the proposed PA achieves a PAE of 25.4% for a 10 MHz LTE signal at an output power (Pout) of 25.6 dBm and a gain of 24 dB.

Yoshida, Eiji; Sakai, Yasufumi; Oishi, Kazuaki; Yamazaki, Hiroshi; Mori, Toshihiko; Yamaura, Shinji; Suto, Kazuo; Tanaka, Tetsu

2014-01-01

136

Hardness variability in commercial technologies  

SciTech Connect

The radiation hardness of commercial Floating Gate 256K E{sup 2}PROMs from a single diffusion lot was observed to vary between 5 to 25 krad(Si) when irradiated at a low dose rate of 64 mrad(Si)/s. Additional variations in E{sup 2}PROM hardness were found to depend on bias condition and failure mode (i.e., inability to read or write the memory), as well as the foundry at which the part was manufactured. This variability is related to system requirements, and it is shown that hardness level and variability affect the allowable mode of operation for E{sup 2}PROMs in space applications. The radiation hardness of commercial 1-Mbit CMOS SRAMs from Micron, Hitachi, and Sony irradiated at 147 rad(Si)/s was approximately 12, 13, and 19 krad(Si), respectively. These failure levels appear to be related to increases in leakage current during irradiation. Hardness of SRAMs from each manufacturer varied by less than 20%, but differences between manufacturers are significant. The Qualified Manufacturer`s List approach to radiation hardness assurance is suggested as a way to reduce variability and to improve the hardness level of commercial technologies.

Shaneyfelt, M.R.; Winokur, P.S.; Meisenheimer, T.L.; Sexton, F.W.; Roeske, S.B.; Knoll, M.G. [Sandia National Labs., Albuquerque, NM (United States)] [Sandia National Labs., Albuquerque, NM (United States)

1994-12-01

137

CMOS chip for biomedical telemetry with hf power supply  

Microsoft Academic Search

This paper aims at describing a miniaturized CMOS implant- circuit for human medical telemetry. The chip includes a silicon antenna working on the principle of inductive coil coupling through the skin, an rf rectifier for power supply, an hf filter and logic circuitry for chip control. A CMOS compatible temperature sensor is included in the same chip. The obtained measurements

Sonia Delmas; Marcin Kaluza; Fabrice Caignet; Etienne Sicard

1996-01-01

138

Performance computation for precharacterized CMOS gates with RC loads  

Microsoft Academic Search

For efficiency, the performance of digital CMOS gates is often expressed in terms of empirical models. Both delay and short-circuit power dissipation are sometimes characterized as a function of load capacitance and input signal transition time. However, gate loads can no longer be modeled by purely capacitive loads for high performance CMOS due to the RC metal interconnect effects. This

Florentin Dartu; Noel Menezes; Lawrence T. Pileggi

1996-01-01

139

Contactless fluorescence imaging with a CMOS image sensor  

Microsoft Academic Search

In this work, we utilize a CMOS active pixel sensor in a fluorescence imaging setup. The ability to sense small light intensity changes on top of a large baseline with spatial resolution at the subcellular scale is required in fluorescence imaging. The CMOS imager presented in (1) is perfect for this application with the ability to resolve fine features coupled

Andreas G. Andreou; Zhaonian Zhang; Recep Ozgun; Edward T. Choi; Zaven K. Kalayjian; Miriam A. Marwick; Jennifer Blain Christen; Leslie Tung

2011-01-01

140

A CMOS fault extractor for inductive fault analysis  

Microsoft Academic Search

The inductive fault analysis (IFA) method is presented and a description is given of the CMOS fault extraction program FXT. The IFA philosophy is to consider the causes of faults (manufacturing defects) and then simulate these causes to find the faults that are likely to occur in a circuit. FXT automates IFA for a CMOS technology by generating a list

F. Joel Ferguson; John Paul Shen

1988-01-01

141

GaAs MQW modulators integrated with silicon CMOS  

Microsoft Academic Search

We demonstrate integration of GaAs-AlGaAs multiple quantum well modulators to silicon CMOS circuitry via flip-chip solder-bonding followed by substrate removal. We obtain 95% device yield for 32×32 arrays of devices with 15 micron solder pads. We show operation of a simple circuit composed of a modulator and a CMOS transistor

K. W. Goossen; J. A. Walker; L. A. D'Asaro; S. P. Hui; B. Tseng; R. Leibenguth; D. Kossives; D. D. Bacon; D. Dahringer; L. M. F. Chirovsky; A. L. Lentine; D. A. B. Miller

1995-01-01

142

Process Compensated CMOS Temperature Sensor for Microprocessor Application  

E-print Network

Process Compensated CMOS Temperature Sensor for Microprocessor Application Yaesuk Jeong and Farrokh consumption is 478uW. I. INTRODUCTION With microprocessors scaling to higher performance and faster speed in the microprocessor to monitor its thermal distribution. Many CMOS based temperature sensors have been reported

Ayazi, Farrokh

143

RF power potential of 45 nm CMOS technology  

E-print Network

This paper presents the first measurements of the RF power performance of 45 nm CMOS devices with varying device widths and layouts. We find that 45 nm CMOS can deliver a peak output power density of around 140 mW/mm with ...

Putnam, Christopher

144

Quiescent power supply current measurement for CMOS IC defect detection  

Microsoft Academic Search

Quiescent power supply current (IDDQ) measurement is a very effective technique for detecting in CMOS integrated circuits (ICs). This technique uniquely detects certain CMOS IC defects such as gate oxide shorts, defective p-n junctions, and parasitic transistor leakage. In addition, IDDQ monitoring will detect all stuck-at faults with the advantage of using a node toggling test set that has fewer

CHARLES F. HAWKINS; JERRY M. SODEN; RONALD R. FRITZEMEIER; LUTHER K. HORNING

1989-01-01

145

Autonomous mobile mini-robot with embedded CMOS vision system  

Microsoft Academic Search

This paper presents a prototype of a mobile minirobot with an embedded vision system. The robot control is implemented in a low cost microcontroller and the vision system is based in a proprietary CMOS imaging array. The proposed vision sensor has enough flexibility to be incorporated directly to most microcontroller-based systems without any additional electronics. The CMOS camera sensor has

J. Palacin; A. Sanuy; X. Clua; G. Chapinal; S. Bota; M. Moreno; A. Herms

2002-01-01

146

Silicon CMOS based Vertical Multimode Interference Optical Taps  

Microsoft Academic Search

A compact, low loss, optical tap technology is critical for the incorporation of optical interconnects into mainstream CMOS processes. A recently introduced multimode interference effect based device has the potential for very high speed performance in a compact geometry and in a CMOS compatible process. For this work, 2-D and 3-D device simulations confirm a low excess optical loss on

Vincent Stenger; Fred R. Beyette Jr

147

Fundamental performance differences between CMOS and CCD imagers: Part 1  

NASA Astrophysics Data System (ADS)

In depth characterization of CMOS arrays is unveiling many characteristics not observed in CCD imagers. This paper is the first of a series of papers that will discuss unique CMOS characteristics related to fundamental performance differences between CMOS and CCD imagers with emphasis on scientific arrays. The first topic will show that CMOS read noise is ultimately limited by a phenomenon referred to as random telegraph signal (RTS) noise. RTS theory and experimental data discuss its creation, time and frequency domain characteristics, wide variance from pixel to pixel and magnitude on the sensor's overall read noise floor. Specific operating parameters that control and lower RTS noise are identified. It is shown how correlated double sampling (CDS) signal processing responds to RTS noise and demonstrate that sub electron CMOS read noise performance is possible. The paper also discusses CMOS sensitivity (V/e-) nonlinearity, an effect not familiar to CCD users. The problem plays havoc on conventional photon transfer analysis that leads to serious measurement errors. New photon transfer relations are developed to deal with the problem. Nonlinearity for custom CMOS pixels is shown to be beneficial for lowering read noise and extending dynamic range. The paper closes with a section on the high performance CMOS array used to generated data products presented.

Janesick, James; Andrews, James T.; Elliott, Tom

2006-06-01

148

High-performance monolithic CMOS detectors for space applications  

Microsoft Academic Search

During the last 10 years, research about CMOS image sensors (also called APS - Active Pixel Sensors) has been intensively carried out, in order to offer an alternative to CCDs as image sensors. This is particularly the case for space applications as CMOS image sensors feature characteristics which are obviously of interest for flight hardware: parallel or semi-parallel architecture, on

Olivier Saint-Pe; Michel Tulet; Robert Davancens; Franck Larnaudie; Bruno Vignon; Pierre Magnan; Jean A. Farre; Franck Corbiere; Philippe Martin-Gonthier

2001-01-01

149

Simultaneous switching ground noise calculation for packaged CMOS devices  

Microsoft Academic Search

Here, it is assumed that the internal switching current is small compared to the output driver switching current. In the past, it was assumed that simultaneous switching noise created by CMOS outputs was directly proportional to the number of outputs switching simultaneously. Recent studies indicate that CMOS circuits exhibit sublinear behavior (due to the negative feedback influence) of power\\/ground noise

R. Senthinathan; J. L. Prince

1991-01-01

150

A 1-V CMOS log-domain integrator  

Microsoft Academic Search

A novel circuit implementation of a CMOS log-domain integrator is presented. Unlike most other implementations, it does not require placing of MOSFETs in separated wells, and therefore allows very compact filters, which are fully compatible with modern standard CMOS technologies. Besides the saving of chip area, this also helps to reduce parasitic capacitances. The most important advantage of this circuit

Dominique Python; Manfred Punzenberger; Christian C. Enz

1999-01-01

151

Electrostatically driven micro resonator with a CMOS capacitive read out  

Microsoft Academic Search

An electrostatically driven micro resonator is fabricated from single-crystal silicon, using micromachining techniques. The displacement amplitude is measured through differential capacitance measurement, implemented on a CMOS interface circuit, which also provides the excitation clocks for the resonator. The unique feature of this micromechanical system is the integration method applied for attaching the resonator to the CMOS chip. The integration is

Yinon Satuby; Uri Ben-Yehuda; Claudio G. Jakobson; Jacob Shneider; D. Lavie; Y. Nemirovsky; S. Kaldor; M. Hershkovitz; E. Netzer

1995-01-01

152

High responsivity CMOS imager pixel implemented in SOI technology  

NASA Technical Reports Server (NTRS)

Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

2000-01-01

153

CMOS temperature sensor utilizing interface-trap charge pumping  

E-print Network

Silicon Temperature Sensors Three devices used in CMOS technology for temperature sensing are lateral bipo- lar transistors, vertical bipolar transistors, and CMOS transistors operating in weak inversion [9]. These sensors usually rely on proportional... . . . . . . . . . . . . . . . . . . . . 27 V TESTING AND CHARACTERIZATION . . . . . . . . . . . . . 32 A. ITCP Current Source Characterization . . . . . . . . . . . 33 1. Temperature Sensitivity . . . . . . . . . . . . . . . . . 39 B. Leakage Device Characterization...

Berber, Feyza

2006-10-30

154

Cryogenic CMOS avalanche diodes for nuclear physics research  

NASA Astrophysics Data System (ADS)

Exploration in nuclear physics may require extreme conditions, such as temperatures down to a few Kelvin, high magnetic fields of several Tesla, or the small physical dimensions of a few centimeters. As a standard technique for radiation detection using scintillation materials, it is desirable to develop photodetectors that can operate under these harsh conditions. Though photomultiplier tubes (PMTs) have been used for most applications for readout of scintillation materials, they are bulky, highly susceptible to magnetic fields, and present a large heat load in cryogenic environments. Avalanche photodiodes are a reasonable alternative to PMTs in that they are extremely compact and less susceptible to magnetic fields. Avalanche photodiodes have been developed in a commercial CMOS process for operation at temperatures below 100 Kelvin. Here we present the overall operation of the photodiodes at 5 Kelvin. The diodes show a quantum efficiency of at least 30% at 532 nm at 5 Kelvin. At about 30 Kelvin, the diodes exhibit an internal resistive term, which generates a second breakdown point. The prototype diode shows a proportional response to the intensity of light pulses down to 150 detected photons with a hole to electron ionization ratio, k, of 2.3x10-13 at 5 Kelvin. The properties of the photodiodes and the readout electronics will be discussed for general photon detection below 100 K.

Chen, Xiao Jie; Johnson, Erik B.; Stapels, Christopher J.; Whitney, Chad; Chapman, Eric; Alberghini, Guy; Augustine, Frank; Miskimen, Rory; Christian, James F.

2011-09-01

155

Space Commercialization  

NASA Technical Reports Server (NTRS)

A robust and competitive commercial space sector is vital to continued progress in space. The United States is committed to encouraging and facilitating the growth of a U.S. commercial space sector that supports U.S. needs, is globally competitive, and advances U.S. leadership in the generation of new markets and innovation-driven entrepreneurship. Energize competitive domestic industries to participate in global markets and advance the development of: satellite manufacturing; satellite-based services; space launch; terrestrial applications; and increased entrepreneurship. Purchase and use commercial space capabilities and services to the maximum practical extent Actively explore the use of inventive, nontraditional arrangements for acquiring commercial space goods and services to meet United States Government requirements, including measures such as public-private partnerships, . Refrain from conducting United States Government space activities that preclude, discourage, or compete with U.S. commercial space activities. Pursue potential opportunities for transferring routine, operational space functions to the commercial space sector where beneficial and cost-effective.

Martin, Gary L.

2011-01-01

156

Fundamental performance differences between CMOS and CCD imagers, part IV  

NASA Astrophysics Data System (ADS)

This paper is a continuation of past papers written on fundamental performance differences of scientific CMOS and CCD imagers. New characterization results presented below include: 1). a new 1536 × 1536 × 8?m 5TPPD pixel CMOS imager, 2). buried channel MOSFETs for random telegraph noise (RTN) and threshold reduction, 3) sub-electron noise pixels, 4) 'MIM pixel' for pixel sensitivity (V/e-) control, 5) '5TPPD RING pixel' for large pixel, high-speed charge transfer applications, 6) pixel-to-pixel blooming control, 7) buried channel photo gate pixels and CMOSCCDs, 8) substrate bias for deep depletion CMOS imagers, 9) CMOS dark spikes and dark current issues and 10) high energy radiation damage test data. Discussions are also given to a 1024 × 1024 × 16 um 5TPPD pixel imager currently in fabrication and new stitched CMOS imagers that are in the design phase including 4k × 4k × 10 ?m and 10k × 10k × 10 um imager formats.

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Grygon, Mark; Keller, Dave

2010-07-01

157

Fundamental performance differences between CMOS and CCD imagers: part III  

NASA Astrophysics Data System (ADS)

This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff.

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Cheng, John; Bishop, Jeanne

2009-08-01

158

An advanced 0.8 ?m complementary BiCMOS technology for ultra-high speed circuit performance  

Microsoft Academic Search

An 0.8-?m fully complementary BiCMOS (CBiCMOS) process has been developed which offers superior drive capability and low-voltage performance compared to standard BiCMOS technologies. The CBiCMOS process was developed by the successful integration of a high-performance, poly emitter vertical PNP (Ft=17 GHz, emitter coupled logic gate delay=65 ps) and CMOS transistors (CMOS gate delay=68 ps). A CBiCMOS push-pull ring oscillator has

W. R. Burger; C. Lage; B. Landau; M. DeLong; J. Small

1990-01-01

159

Post-CMOS Parylene Packaging for On-chip Biosensor Arrays  

E-print Network

Post-CMOS Parylene Packaging for On-chip Biosensor Arrays Lin Li Department of Electrical as an open challenge. This paper presents a robust and reliable packaging scheme for on-CMOS biosensors CMOS die. Photos of a packaged CMOS biosensor array chip and electrochemical measurements in potassium

Mason, Andrew

160

Advances in CMOS Solid-state Photomultipliers for Scintillation Detector Applications  

PubMed Central

Solid-state photomultipliers (SSPMs) are a compact, lightweight, potentially low-cost alternative to a photomultiplier tube for a variety of scintillation detector applications, including digital-dosimeter and medical-imaging applications. Manufacturing SSPMs with a commercial CMOS process provides the ability for rapid prototyping, and facilitates production to reduce the cost. RMD designs CMOS SSPM devices that are fabricated by commercial foundries. This work describes the characterization and performance of these devices for scintillation detector applications. This work also describes the terms contributing to device noise in terms of the excess noise of the SSPM, the binomial statistics governing the number of pixels triggered by a scintillation event, and the background, or thermal, count rate. The fluctuations associated with these terms limit the resolution of the signal pulse amplitude. We explore the use of pixel-level signal conditioning, and characterize the performance of a prototype SSPM device that preserves the digital nature of the signal. In addition, we explore designs of position-sensitive SSPM detectors for medical imaging applications, and characterize their performance.

Christian, James F.; Stapels, Christopher J.; Johnson, Erik B.; McClish, Mickel; Dokhale, Purushotthom; Shah, Kanai S.; Mukhopadhyay, Sharmistha; Chapman, Eric; Augustine, Frank L.

2014-01-01

161

Terahertz Imaging Detectors in CMOS Technology  

Microsoft Academic Search

Square-law power detection circuits with on-chip antennas and amplifiers are presented for the detection of 0.65-THz radiation\\u000a in a low-cost 0.25-?m CMOS technology. The circuit architecture combines metal-insulator-metal (MIM) coupling capacitors with NMOS transistors\\u000a to facilitate self-mixing in a resistive mixer. A low-frequency (quasi-static) and a high-frequency (non-quasi-static) analysis\\u000a of the broad-band circuit is presented. Current and voltage readout techniques

Erik Öjefors; Alvydas Lisauskas; Diana Glaab; Hartmut G. Roskos; Ullrich R. Pfeiffer

2009-01-01

162

Vertical Isolation for Photodiodes in CMOS Imagers  

NASA Technical Reports Server (NTRS)

In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

Pain, Bedabrata

2008-01-01

163

High Efficiency 3-Phase Cmos Rectifier with Step Up and Regulated  

E-print Network

This paper presents several design issues related to the monolithic integration of a 3-phase AC to DC low voltage, low power rectifier for 3-phase micro source electrical conditioning. Reduced input voltage operation (down to 1V), high efficiency, and output voltage regulations are implemented, based on commercially available CMOS technology. Global design and system issues are detailed. The management of start-up sequences under self supplied conditions as well as output voltage regulations are specifically addressed. Simulation results, practical implementation and validation are presented. They are based on the association of three micro elements : a 3-phase micro-generator, a stand alone 3-phase AC to DC integrated rectifier, and an output voltage conditioner based on a commercially available IC.

Crebier, J -C; Raisigel, H; Deleage, O; Delamare, J; Cugat, O

2008-01-01

164

Enhancing CMOS Using Nanoelectronic Devices: A Perspective on Hybrid Integrated Systems  

Microsoft Academic Search

In this paper, we present a vision for the cointegration of deeply scaled complementary metal-oxide-semiconductor (CMOS) and emerging nanoelectronic devices into CMOS-hybrid systems. These hybrid systems will create new functionality, modality and add value to existing CMOS integrated circuits. We describe several new nanoelectronic devices which may enable new dimensions to traditional CMOS circuits and systems that build on CMOS

David S. Ricketts; James A. Bain; Yi Luo; R. D. Blanton; Kenneth Mai; Gary K. Fedder

2010-01-01

165

Far ultraviolet sensitivity of silicon CMOS sensors  

NASA Astrophysics Data System (ADS)

We describe vacuum ultraviolet sensitivity measurements of a new high performance silicon-based CMOS sensor from Teledyne Imaging Sensors. These sensors do not require the high voltages of MCP detectors, making them a lower mass and power alternative to the more mature MCP technology. These devices demonstrate up to 40 percent quantum efficiency at vacuum ultraviolet wavelengths, either meeting or greatly exceeding 10 percent quantum efficiency across the entire 100-200 nm wavelength region. As with similar visible sensitive devices, backside illumination results in a higher quantum efficiency than frontside illumination. Measurements of the vacuum ultraviolet sensitivity of the Teledyne silicon PIN detectors were made by directing a known intensity of ultraviolet light at discrete wavelengths onto the test detectors and reading out the resulting photocurrent. The sensitivity of the detector at a given wavelength was then calculated from the intensity and wavelength of the incoming light and the relative photodiode to NIST-traceable calibration diode active areas. A custom electromechanical interface was developed to make these measurements within the SwRI Vacuum Radiometric Calibration Chamber. While still in the single pixel stage, full 1K × 1K focal plane arrays are possible using existing CMOS readout electronics and hold great promise for inclusion in future spaceflight instrument concepts.

Davis, Michael W.; Greathouse, Thomas K.; Retherford, Kurt D.; Winters, Gregory S.; Bai, Yibin; Beletic, James W.

2012-07-01

166

The 1.2 micron CMOS technology  

NASA Technical Reports Server (NTRS)

A set of test structures was designed using the Jet Propulsion Laboratory (JPL) test chip assembler and was used to evaluate the first CMOS-bulk foundry runs with feature sizes of 1.2 microns. In addition to the problems associated with the physical scaling of the structures, this geometry provided an additional set of problems, since the design files had to be generated in such a way as to be capable of being processed through p-well, n-well, and twin-well processing lines. This requirement meant that the files containing the geometric design rules as well as the structure design files had to produce process-insensitive designs, a requirement that does not apply to the more mature 3.0-micron CMOS feature size technology. Because of the photolithographic steps required with this feature size, the maximum allowable chip size was 10 x 10 mm, and this chip was divided into 24 project areas, with each area being 1.6 x 1.6 mm in size. The JPL-designed structures occupied 13 out of the 21 allowable project sizes and provided the only test information obtained from these three preliminary runs. The structures were used to successfully evaluate three different manufacturing runs through two separate foundries.

Pina, C. A.

1985-01-01

167

Commercial applications  

NASA Technical Reports Server (NTRS)

Viewgraphs on commercial applications of fuzzy logic in Japan are presented. Topics covered include: suitable application area of fuzzy theory; characteristics of fuzzy control; fuzzy closed-loop controller; Mitsubishi heavy air conditioner; predictive fuzzy control; the Sendai subway system; automatic transmission; fuzzy logic-based command system for antilock braking system; fuzzy feed-forward controller; and fuzzy auto-tuning system.

Togai, Masaki

1990-01-01

168

Packaged CMOS-MEMS free-free beam oscillator  

NASA Astrophysics Data System (ADS)

In this paper a self-oscillator based on a polysilicon free-free beam resonator monolithically integrated and packaged in a 0.35 µm complementary metal-oxide-semiconductor (CMOS) technology is presented. The oscillator is capable of providing a 350 mVPP sinusoidal signal at 25.6 MHz, with a bias polarization voltage of 7 V. The microelectromechanical systems (MEMS) resonator is packaged using only the back-end-of-line metal layers of the CMOS technology, providing a complete low-cost CMOS-MEMS processing for on-chip frequency references.

Marigó, E.; Verd, J.; López, J. L.; Uranga, A.; Barniol, N.

2013-11-01

169

Lower-Dark-Current, Higher-Blue-Response CMOS Imagers  

NASA Technical Reports Server (NTRS)

Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

2008-01-01

170

An electrostatic CMOS/BiCMOS Lithium ion vibration-based harvester-charger IC  

NASA Astrophysics Data System (ADS)

Self-powered microsystems, such as wireless transceiver microsensors, appeal to an expanding application space in monitoring, control, and diagnosis for commercial, industrial, military, space, and biomedical products. As these devices continue to shrink, their microscale dimensions allow them to be unobtrusive and economical, with the potential to operate from typically unreachable environments and, in wireless network applications, deploy numerous distributed sensing nodes simultaneously. Extended operational life, however, is difficult to achieve since their limited volume space constrains the stored energy available, even with state-of-the-art technologies, such as thin-film lithium-ion batteries (Li Ion) and micro-fuel cells. Harvesting ambient energy overcomes this deficit by continually replenishing the energy reservoir and, as a result, indefinitely extending system lifetime. In this work, an electrostatic harvester that harnesses ambient kinetic energy from vibrations to charge an energy-storage device (e.g., a battery) is investigated, developed, and evaluated. The proposed harvester charges and holds the voltage across a vibration-sensitive variable capacitor so that vibrations can induce it to generate current into the battery when capacitance decreases (as its plates separate). The challenge is that energy is harnessed at relatively slow rates, producing low output power, and the electronics required to transfer it to charge a battery can easily demand more than the power produced. To this end, the system reduces losses by time-managing and biasing its circuits to operate only when needed and with just enough energy while charging the capacitor through an efficient quasi-lossless inductor-based precharger. As result, the proposed energy harvester stores a net energy gain in the battery during every vibration cycle. Two energy-harvesting integrated circuits (IC) were analyzed, designed, developed, and validated using a 0.7-im BiCMOS process and a 30-Hz mechanical variable capacitor. The precharger, harvester, monitoring, and control microelectronics of the first prototype draw sufficient power to operate and at the same time produce experimentally 1.27, 2.14, and 2.87 nJ per vibration cycle for battery voltages at 2.7, 3.5, and 4.2 V, which with 30-Hz vibrations produce 38.1, 64.2, and 86.1 nW. By incorporating into the system a self-tuning loop that adapts optimally the inductor-based precharger to varying battery voltages, the second prototype harnessed and gained 1.93, 2.43, and 3.89 nJ per vibration cycle at battery voltages 2.7, 3.5, and 4.2 V, generating 57.89, 73.02, and 116.55 nW at 30 Hz. The harvester ultimately charges from 2.7 to 4.2 V a 1-muF capacitor (which emulates a small thin-film Li Ion) in approximately 69 s, harnessing in the same length of time 47.9% more energy than with a non-adapting harvester.

Torres, Erick Omar

171

Multichannel lens-free CMOS sensors for real-time monitoring of cell growth.  

PubMed

A low-cost platform is proposed for the growth and real-time monitoring of biological cells. The main components of the platform include a PMMA cell culture microchip and a multichannel lens-free CMOS (complementary metal-oxide-semiconductor) / LED imaging system. The PMMA microchip comprises a three-layer structure and is fabricated using a low-cost CO2 laser ablation technique. The CMOS / LED monitoring system is controlled using a self-written LabVIEW program. The platform has overall dimensions of just 130 × 104 × 115 mm(3) and can therefore be placed within a commercial incubator. The feasibility of the proposed system is demonstrated using HepG2 cancer cell samples with concentrations of 5000, 10?000, 20?000, and 40?000 cells/mL. In addition, cell cytotoxicity tests are performed using 8, 16, and 32 mM cyclophosphamide. For all of the experiments, the cell growth is observed over a period of 48 h. The cell growth rate is found to vary in the range of 44?52% under normal conditions and from 17.4?34.5% under cyclophosphamide-treated conditions. In general, the results confirm the long-term cell growth and real-time monitoring ability of the proposed system. Moreover, the magnification provided by the lens-free CMOS / LED observation system is around 40× that provided by a traditional microscope. Consequently, the proposed system has significant potential for long-term cell proliferation and cytotoxicity evaluation investigations. PMID:25224658

Chang, Ko-Tung; Chang, Yu-Jen; Chen, Chia-Ling; Wang, Yao-Nan

2015-02-01

172

Commercial Norms, Commercial Codes, and International Commercial Arbitration  

E-print Network

The article defends the incorporation of commercial norms into commercial codes, through provisions such as statute 1-205 of the Uniform Commercial Code. It finds significant reliance on trade usages in international ...

Drahozal, Christopher R.

2000-01-01

173

Circuits and algorithms for pipelined ADCs in scaled CMOS technologies  

E-print Network

CMOS technology scaling is creating significant issues for analog circuit design. For example, reduced signal swing and device gain make it increasingly difficult to realize high-speed, high-gain feedback loops traditionally ...

Brooks, Lane Gearle, 1975-

2008-01-01

174

A study of CMOS technologies for image sensor applications  

E-print Network

CMOS (Complementary Metal-Oxide-Silicon) imager technology, as compared with mature CCD (Charge-Coupled Device) imager technology, has the advantages of higher circuit integration, lower power consumption, and potentially ...

Wang, Ching-Chun, 1969-

2001-01-01

175

Strain-engineered CMOS-compatible Ge photodetectors  

E-print Network

The development of CMOS-compatible photodetectors capable of operating throughout the entire telecommunications wavelength spectrum will aid in the integration of photodetectors with Si microelectronics, thus offering a ...

Cannon, Douglas Dale, 1974-

2004-01-01

176

Fabrication and simulation of CMOS-compatible photodiodes  

E-print Network

CMOS-compatible photodiodes are becoming increasinging important devices to study because of their application in combined electronic-photonic systems. They are already used as inexpensive optical transceivers in fiber ...

DiLello, Nicole Ann

2008-01-01

177

A silicon avalanche photodetector fabricated with standard CMOS technology  

E-print Network

A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain a silicon avalanche photodetector (APD) fabricated with standard complementary metal-well junction, and its current-voltage characteristics, responsivity, avalanche gain, and photodetection

Choi, Woo-Young

178

Formal specification of a high speed CMOS correlator  

NASA Technical Reports Server (NTRS)

The formal specification of a high speed CMOS correlator is presented. The specification gives the high-level behavior of the correlator and provides a clear, unambiguous description of the high-level architecture of the device.

Windley, P. J.

1991-01-01

179

CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology  

NASA Technical Reports Server (NTRS)

This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

2006-01-01

180

CMOS image sensors optimised for GEO observation  

NASA Astrophysics Data System (ADS)

CMOS Image Sensors (CIS) arrays have well proven their capabilities to address the growing need of space imaging from the GEO orbit within the visible and near infrared spectral bands. The main interesting features of CIS detectors for such applications are smearing-free capability, small pixel pitches even with large charge handling capacity, fine tuning of QE and MTF, low power dissipation, exposure control and good radiation behaviour. This paper will present new results obtained by our team in the field of development of such 2D arrays, including large format detectors (up to 12 million pixels), front and back side illuminations, 3T and 4T pixels, microlenses and different types of epitaxial layers/thicknesses. Radiometric and geometric characterisation results obtained for various devices will be presented.

Bréart de Boisanger, Michel; Larnaudie, Franck; Saint-Pé, Olivier

2013-10-01

181

CMOS digital pixel sensors: technology and applications  

NASA Astrophysics Data System (ADS)

CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

Skorka, Orit; Joseph, Dileepan

2014-04-01

182

Log polar image sensor in CMOS technology  

NASA Astrophysics Data System (ADS)

We report on the design, design issues, fabrication and performance of a log-polar CMOS image sensor. The sensor is developed for the use in a videophone system for deaf and hearing impaired people, who are not capable of communicating through a 'normal' telephone. The system allows 15 detailed images per second to be transmitted over existing telephone lines. This framerate is sufficient for conversations by means of sign language or lip reading. The pixel array of the sensor consists of 76 concentric circles with (up to) 128 pixels per circle, in total 8013 pixels. The interior pixels have a pitch of 14 micrometers, up to 250 micrometers at the border. The 8013-pixels image is mapped (log-polar transformation) in a X-Y addressable 76 by 128 array.

Scheffer, Danny; Dierickx, Bart; Pardo, Fernando; Vlummens, Jan; Meynants, Guy; Hermans, Lou

1996-08-01

183

Latchup in CMOS devices from heavy ions  

NASA Technical Reports Server (NTRS)

It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

Soliman, K.; Nichols, D. K.

1983-01-01

184

CMOS imager for pointing and tracking applications  

NASA Technical Reports Server (NTRS)

Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

2006-01-01

185

Nano-CMOS Technology for Next Fifteen Years  

Microsoft Academic Search

Complementary metal-oxide-semiconductor (CMOS) technology has been developed into the sub-100 nm range. It is expected that the nano-CMOS technology will govern the IC manufacturing for at least another couple of decades. Though there are many challenges ahead, further down-sizing the device to a few nanometers is still on the schedule of International Technology Roadmap for Semiconductors (ITRS). Several technological options

H. Iwai; H. Wong

2006-01-01

186

A statistical MOSFET modeling method for CMOS integrated circuit simulation  

E-print Network

A STATISTICAL MOSFET MODELING METHOD FOR CMOS IN'I'EGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Submitted to the Office of Graduate Studies of Texas AE~M University in partial fulfillment of the requirements for the degree of MASTER... OF SCIENCE August l 99'2 Major Sub ject: Electrical Engineering A STATISTICAL MOSFET MODELING METHOD FOR CMOS INTEGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Approved as to style and content by: H. Maciej . Styblinski ) (Chair of Committee...

Chen, Jian

2012-06-07

187

CMOS\\/LCOS-based image transceiver device: II  

Microsoft Academic Search

A CMOS-liquid crystal-based image transceiver device (ITD) is under development at the Holon Institute of Technology. The device combines both functions of imaging and display in a single array configuration. This unique structure allows the combination of see-through, aiming, imaging and the displaying of a superposed image to be combined in a single, compact, head mounted display. The CMOS-based pixel

Uzi Efron; Isak Davidov; Vladimir Sinelnikov; Asher A. Friesem

2001-01-01

188

CMOS-liquid-crystal-based image transceiver device  

Microsoft Academic Search

A CMOS-Liquid Crystal-Based Image Transceiver Device (ITD) is under development at the Holon Institute of Technology. The device combines both functions of imaginary and display in a single array structure. This unique structure allows the combination of see-through, aiming, imaging and the displaying of a superposed image to be combined in a single, compact, head mounted display. The CMOS-based pixel

Uzi Efron; Isak Davidov; Vladimir Sinelnikov; Ilya Levin

2001-01-01

189

CMOS Monolithic Metal–Oxide Gas Sensor Microsystems  

Microsoft Academic Search

This paper presents two mixed-signal monolithic gas sensor microsystems fabricated in standard 0.8-$muhbox m$CMOS technology combined with post-CMOS micromachining to form the microhotplates. The on-chip microhotplates provide very high temperatures (between 200$^circ$C and 400$^circ$C), which are necessary for the normal operation of metal–oxide sensing layers. The first microsystem has a single-ended architecture comprising a microhotplate (diameter of 300$muhbox m$) and

Diego Barrettino; Markus Graf; Stefano Taschini; Sadik Hafizovic; Christoph Hagleitner; Andreas Hierlemann

2006-01-01

190

An Energy-Efficient CMOS Line Driver Using Adiabatic Switching  

Microsoft Academic Search

The energy recovery principle used in high-efficiency power supplies can be applied to digital CMOS logic to reduce dynamic power dissipation. We describe experiments with a custom line- driver chip and resonant power supply that can switch eight 100pF loads at 1MHz over 6 times more efficiently than conventional CMOS. The paper describes the adiabatic charging principle underlying this class

W. C. Athas; J. G. Koller

1993-01-01

191

A monolithic CMOS step-down DC-DC converter  

Microsoft Academic Search

A monolithic CMOS switch-mode step-down power converter, with on-chip PWM technique, has been designed and implemented. Also, a micropower bandgap reference generator is developed for the dc-dc converter. This power converter occupied a chip area of 880times1040 mum2 is fabricated in a 2P4M 0.35-mum CMOS process. The simulation results show that the converter is well regulated over an output range

Yeong-Tsair Lin; Wen-Yaw Chung; Dong-Shiu Wu; Hung-Chan Wang; Hung-Yih Lin; Jiann-Jong Chen

2005-01-01

192

Electrical properties and detection methods for CMOS IC defects  

Microsoft Academic Search

CMOS failure modes and mechanisms and the test vector and parametric test requirements for the detection are reviewed. The CMOS stuck-open fault is discussed from a physical viewpoint, with results given from failure analysis of ICs having this failure mode. The results show that among functional, stuck-at, stuck-open, and IDDQ test strategies, no single method guarantees detection of all types

Jerry M. Soden; Charles F. Hawkins

1989-01-01

193

Advancement of CMOS Doping Technology in an External Development Framework  

NASA Astrophysics Data System (ADS)

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

194

Modeling and simulation of TDI CMOS image sensors  

NASA Astrophysics Data System (ADS)

In this paper, a mathematical model of TDI CMOS image sensors was established in behavioral level through MATLAB based on the principle of a TDI CMOS image sensor using temporal oversampling rolling shutter in the along-track direction. The geometric perspective and light energy transmission relationships between the scene and the image on the sensor are included in the proposed model. A graphical user interface (GUI) of the model was also established. A high resolution satellitic picture was used to model the virtual scene being photographed. The effectiveness of the proposed model was verified by computer simulations based on the satellitic picture. In order to guide the design of TDI CMOS image sensors, the impacts of some parameters of TDI CMOS image sensors including pixel pitch, pixel photosensitive size, and integration time on the performance of the sensors were researched through the proposed model. The impacts of the above parameters on the sensors were quantified by sensor's modulation transfer function (MTF) of the along-track direction, which was calculated by slanted-edge method. The simulation results indicated that the TDI CMOS image sensor can get a better performance with smaller pixel photosensitive size and shorter integration time. The proposed model is useful in the process of researching and developing a TDI CMOS image sensor.

Nie, Kai-ming; Yao, Su-ying; Xu, Jiang-tao; Gao, Jing

2013-09-01

195

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.  

PubMed

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18? ?m TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 ?m TSMC CMOS technology. PMID:24782680

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

196

Real-time video rate imaging with a 1k-pixel THz CMOS focal plane array  

NASA Astrophysics Data System (ADS)

Future submillimeter-wave and THz (300GHz-3THz) imaging applications will require low-cost portable systems operating at room-temperature with a video-rate speed and capable of delivering acceptable sensitivity at the very low-power consumption levels to become attractive for truly commercial applications. In particular, CMOS technologies are of interest due to their high integration level offered at a high yield that is capable of massive cost reduction of currently existing THz systems. It has been recently demonstrated that CMOS direct detectors achieve the performance comparable or even superior to the today's existing classical THz devices for active imaging operating at room-temperature. So far, however, only single pixels have been used, allowing only a raster-scan operation. To address this obstacle, we present the very initial work on a 1k-pixel camera chip with a completely integrated readout circuitry and with a full video-rate capability at a power consumption of 2.5?W/pixel. The chip is fully compliant with an industrial bulk CMOS technology and it is intended for active imaging applications. It exhibits a pixel pitch of 80?m, defined by a novel on-chip wire ring antenna, and is designed to accommodate silicon hyper-hemispherical lens for a wide operation bandwidth of at least 0.7-1.1 THz.

Grzyb, J.; Sherry, H.; Zhao, Y.; Al Hadi, R.; Cathelin, A.; Kaiser, A.; Pfeiffer, U.

2012-06-01

197

CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) Circuit Design for Nanosecond Quantum-Bit Read-out  

Microsoft Academic Search

Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling

Thomas M. Gurrieri; Malcolm S. Carroll; Michael P. Lilly; James E. Levy

2008-01-01

198

77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...  

Federal Register 2010, 2011, 2012, 2013, 2014

...COMMISSION [Investigation No. 337-TA-846] Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...within the United States after importation of certain CMOS image sensors and products containing the same based on infringement of...

2012-12-14

199

Design Considerations for CMOS-Integrated Hall-Effect Magnetic Bead Detectors for Biosensor Applications  

PubMed Central

We describe a design methodology for on-chip magnetic bead label detectors based on Hall-effect sensors. Signal errors caused by the label-binding process and other factors that limit the minimum detection area are quantified and adjusted to meet typical assay accuracy standards. The methodology is demonstrated by designing an 8192 element Hall sensor array, implemented in a commercial 0.18 ?m CMOS process with single-mask postprocessing. The array can quantify a 1% surface coverage of 2.8 ?m beads in 30 seconds with a coefficient of variation of 7.4%. This combination of accuracy and speed makes this technology a suitable detection platform for biological assays based on magnetic bead labels. PMID:25031503

Skucha, K.; Gambini, S.; Liu, P.; Megens, M.; Kim, J.; Boser, BE

2014-01-01

200

Teledyne Imaging Sensors: silicon CMOS imaging technologies for x-ray, UV, visible, and near infrared  

Microsoft Academic Search

Teledyne Imaging Sensors develops and produces high performance silicon-based CMOS image sensors, with associated electronics and packaging for astronomy and civil space. Teledyne's silicon detector sensors use two technologies: monolithic CMOS, and silicon PIN hybrid CMOS. Teledyne's monolithic CMOS sensors are large (up to 59 million pixels), low noise (2.8 e- readout noise demonstrated, 1-2 e- noise in development), low

Yibin Bai; Jagmohan Bajaj; James W. Beletic; Mark C. Farris; Atul Joshi; Stefan Lauxtermann; Anders Petersen; George Williams

2008-01-01

201

Heavy ion radiation damage simulations for CMOS image sensors Henok Mebrahtua  

E-print Network

Heavy ion radiation damage simulations for CMOS image sensors Henok Mebrahtua , Wei Gaoa , Paul J, University of Toronto, Toronto, Ontario, Canada ABSTRACT Damage in CMOS image sensors caused by heavy ions and range of ions in matter) simulation results of heavy ion radiation damage to CMOS image sensors

Hornsey, Richard

202

VLSI scaling methods and low power CMOS buffer circuit  

NASA Astrophysics Data System (ADS)

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.

Sharma, Vijay Kumar; Pattanaik, Manisha

2013-09-01

203

CMOS Cell Sensors for Point-of-Care Diagnostics  

PubMed Central

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

204

NSC 800, 8-bit CMOS microprocessor  

NASA Technical Reports Server (NTRS)

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Suszko, S. F.

1984-01-01

205

Commercial applications  

NASA Astrophysics Data System (ADS)

The near term (one to five year) needs of domestic and foreign commercial suppliers of radiochemicals and radiopharmaceuticals for electromagnetically separated stable isotopes are assessed. Only isotopes purchased to make products for sale and profit are considered. Radiopharmaceuticals produced from enriched stable isotopes supplied by the Calutron facility at ORNL are used in about 600,000 medical procedures each year in the United States. A temporary or permanent disruption of the supply of stable isotopes to the domestic radiopharmaceutical industry could curtail, if not eliminate, the use of such diagnostic procedures as the thallium heart scan, the gallium cancer scan, the gallium abscess scan, and the low radiation dose thyroid scan. An alternative source of enriched stable isotopes exist in the USSR. Alternative starting materials could, in theory, eventually be developed for both the thallium and gallium scans. The development of a new technology for these purposes, however, would take at least five years and would be expensive. Hence, any disruption of the supply of enriched isotopes from ORNL and the resulting unavailability of critical nuclear medicine procedures would have a dramatic negative effect on the level of health care in the United States.

206

Operation and biasing for single device equivalent to CMOS  

DOEpatents

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

2001-01-01

207

VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications  

NASA Astrophysics Data System (ADS)

This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 ?m long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

2014-10-01

208

A CMOS humidity sensor for passive RFID sensing applications.  

PubMed

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 ?m CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

209

Electroplated solenoid-type inductors for CMOS rf CO  

NASA Astrophysics Data System (ADS)

A Solenoid-type Inductors have been realized using electroplating technique mainly used for 2 Ghz band CMOS RF VCO applications. The integrated spiral inductor has low Q factor due to substrate loss and skin effects. And it also occupies large area compared to solenoid-type inductor. The direction of flux of the solenoid-type inductor is parallel to the substrate, which can lower substrate loss and other interference with integrated passive components. In this research, Solenoid-type inductors are simulated and modeled as equivalent circuit for CMOS RF VCO based on extracted S- parameters. The electroplated solenoid-type inductors are fabricated on both a standard silicon substrate and glass substrate by thick PR photolithography and copper electroplating. The achieved inductance varies range from 1 nH to 5 nH, and maximum Q factor over 10. The inductors are scheduled to be integrated on CMOS RF VCO with RF MEMS capacitor for future.

Nam, Chul; Choi, Wonseo; Chun, KukJin

2000-10-01

210

CMOS APS digital camera based on enhanced parallel port  

NASA Astrophysics Data System (ADS)

CMOS APS become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor analogue circuitry, and digital processing functions. This paper discusses a CMOS digital camera based on EPP interface. A CMOS APS (OV7110) with VGA resolution (640 x 480) was selected as the image sensor, it can generate digital output of typically an 8 or 16 bit data bus in YUV or RGB mode, all the image controllling, e.g. frame rate, white balance, gamma control and exposure control all can be adjusted through 12C bus. The 12C bus control unit, FIFO and EPP interface, etc. are all integrated within a CPLD. The overall structure, working scheme and performance analyses of the camera were discussed in detail. Several images taken by the camera are provided and a detailed discussion of its quality, processing of image data, etc. is also given.

Liu, Zhi; Yang, Jingyi; Wang, Yefan; Hao, Zhihang

2002-09-01

211

A high performance 0.25 mu m CMOS technology  

Microsoft Academic Search

A high-performance 0.25- mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented. A loaded ring oscillator (NAND FI=FO=3. Cw=0.2 pF) delay per stage of 280 ps achieved (Weff\\/Leff=15 mu m\\/0.25 mu m), which is a 1.7 X improvement over 0.5- mu m CMOS technology. At shorter channel lengths (0.18 mu m),

B. Davari; W. H. Chang; M. R. Wordeman; C. S. Oh; Y. Taur; K. E. Petrillo; D. Moy; J. J. Bucchignano; H. Y. Ng; M. G. Rosenfield; F. J. Hohn; M. D. Rodriguez

1988-01-01

212

Statistical circuit design for yield improvement in CMOS circuits  

NASA Technical Reports Server (NTRS)

This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.

Kamath, H. J.; Purviance, J. E.; Whitaker, S. R.

1990-01-01

213

Modifications in CMOS Dynamic Logic Style: A Review Paper  

NASA Astrophysics Data System (ADS)

Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper, an overview and classification of these techniques are first presented and then compared according to their performance.

Meher, Preetisudha; Mahapatra, Kamalakanta

2014-11-01

214

Novel neuromorphic CMOS device array for biochemical charge sensing.  

PubMed

Novel neuromorphic CMOS device is proposed as a biochemical charge sensor. The basic architecture of an extended floating-gate field-effect transistor (FET) is modified to be suited for large-array applications. The FET has a floating-gate that is umbrella-shaped (UGFET), maximizing its charge sensing area in a much reduced transistor area. Compared to previous chemoreceptive FET-based charge sensors, the UGFET shows improved scalability and sensitivity. 3-D device simulations validate the UGFET model. The design is fabricated in a standard CMOS process and characterized. Experimental results on biochemical charge sensing are presented employing the transconductance and subthreshold measurement schemes. PMID:19163158

Pandey, Santosh; Daryanani, Michelle; Chen, Baozhen; Tao, Chengwu

2008-01-01

215

Associate Program, Commercial Banking Commercial Banking  

E-print Network

Associate Program, Commercial Banking Commercial Banking Job Code 0203 ­ Level 6 CIBC is a leading Banking, Wealth Management and Wholesale Banking ­ we provide a full range of financial products Group of Companies please visit CIBC.com. Job Overview The Commercial Banking Associate Program provides

Northern British Columbia, University of

216

SRAM Design Techniques for Sub-nano CMOS Technology  

Microsoft Academic Search

The scaling of CMOS technology has significant impacts on SRAM cell ? random fluctuation of electrical characteristics and substantial leakage current. The random fluctuation of electrical property causes the symmetrical 6T cell to have huge mismatch in transistor threshold voltage. Consequently, the static noise margin (Read Margin) and the write margin are degraded dramatically. The SRAM cell tends to be

Jordan Lai

2006-01-01

217

Thin Film on CMOS Active Pixel Sensor for Space Applications  

PubMed Central

A 664 × 664 element Active Pixel image Sensor (APS) with integrated analog signal processing, full frame synchronous shutter and random access for applications in star sensors is presented and discussed. A thick vertical diode array in Thin Film on CMOS (TFC) technology is explored to achieve radiation hardness and maximum fill factor.

Schulze Spuentrup, Jan Dirk; Burghartz, Joachim N.; Graf, Heinz-Gerd; Harendt, Christine; Hutter, Franz; Nicke, Markus; Schmidt, Uwe; Schubert, Markus; Sterzel, Juergen

2008-01-01

218

A unified model for integrated resistors in CMOS technologies  

Microsoft Academic Search

In the present work we present a compact model, oriented to the SPICE-like simulation, that pictures the electrical behavior of integrated resistors fabricated in CMOS technologies. The model accounts for the main electrical features of integrated resistors such as the depletion effects, the head resistance contribution, the velocity saturation and the temperature behavior also including possible self-heating phenomena. It has

I. Aureli; D. Ventrice; C. Codegoni; P. Fantini

2007-01-01

219

Testing for bridging faults (shorts) in CMOS circuits  

Microsoft Academic Search

The stuck-at fault model, which is commonly used with fault simulation, does not adequately evaluate the effects of bridging faults (shorts between adjacent signal lines) in CMOS circuits. Tests for bridging faults can be performed on automatic test equipment, and the test vectors can be evaluated using logic simulation.

John M. Acken

1983-01-01

220

Variable threshold voltage CMOS (VTCMOS) in series connected circuits  

Microsoft Academic Search

Characteristics of variable threshold voltage CMOS (VTCMOS) in series connected circuits are investigated by means of device simulation. It is found that the performance degradation due to the body effect in series connected circuits is suppressed by utilizing VTCMOS. Lowering the threshold voltage (Vth) enhances the drive current and alleviates the degradation due to the series connected configuration. Therefore, larger

T. Inukai; T. Hiramoto; T. Sakurai

2001-01-01

221

Variable threshold CMOS (VTCMOS) in series connected circuits  

Microsoft Academic Search

Characteristics of variable threshold voltage CMOS (VTCMOS) in the series connected circuits are investigated by means of device simulation. It is newly found that the performance degradation due to the body effect in series connected circuit is suppressed by utilizing VTCMOS. Lowering the threshold voltage (Vth) enhances the drive current and alleviates the degradation due to the series connected configuration.

Takashi Inukai; Toshiro Hiramoto; Takayasu Sakurai

2001-01-01

222

Bridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess  

E-print Network

Bridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess Tracy Larrabee \\Lambda present a theorem for detecting feedback bridge faults. We discuss two different methods of bridge fault of the two methods. We con­ clude that the new simulation method, Wire Memory bridge fault simulation

Larrabee, Tracy

223

Ultrabroadband supercontinuum generation in a CMOS-compatible platform  

E-print Network

Ultrabroadband supercontinuum generation in a CMOS-compatible platform R. Halir,1,5, * Y. Okawachi 162267); published May 10, 2012 We demonstrate supercontinuum generation spanning 1.6 octaves in silicon Optical Society of America OCIS codes: 190.4390, 320.7110, 320.6629, 230.7370. Supercontinuum generation

Lipson, Michal

224

CMOS imager microsystem for multi-bacteria detection  

Microsoft Academic Search

The paper presents the design and implementation of a Complementary Metal-Oxide Semiconductor (CMOS) based imaging microsystem that can monitor multiple bacteria and viruses simultaneously. The sensor microsystem uses bacteriophages or phage organisms as recognition elements to detect deadly bacteria such as Anthrax, Salmonella, and E-Coli. The genetically engineered phages are viruses that recognize specific receptors on the bacteria surface to

Lei Yao; Mohamad Hajj Hassan; Vamsy Chodavarapu; Arghavan Shabani; Beatrice Allain; Mohammed Zourob; Rosemonde Mandeville

2008-01-01

225

CMOS Conductometric System for Growth Monitoring and Sensing of Bacteria  

Microsoft Academic Search

We present the design and implementation of a pro- totype complementary metal-oxide semiconductor (CMOS) con- ductometric integrated circuit (IC) for colony growth monitoring and specific sensing of Escherichia coli (E. coli) bacteria. The de- tection of E. coli is done by employing T4 bacteriophages as re- ceptor organisms. The conductometric system operates by mea- suring the resistance of the test

Lei Yao; Philippe Lamarche; Nancy Tawil; Rifat Khan; Amir M. Aliakbar; Mohamad H. Hassan; Vamsy P. Chodavarapu; Rosemonde Mandeville

2011-01-01

226

Total dose testing of a CMOS charged particle spectrometer  

Microsoft Academic Search

A first-generation CMOS Charged Particle Spectrometer chip was designed at JPL for flight on the STRV-2 spacecraft. These devices will collect electron and proton spectra in low Earth orbit as part of an experiment to demonstrate Active Pixel Sensor (APS) technology in space. This paper presents the results of total dose testing on these chips and, where possible, attempts to

B. R. Hancock; G. A. Soli

1997-01-01

227

CCD AND PIN-CMOS DEVELOPMENTS FOR LARGE OPTICAL TELESCOPE.  

SciTech Connect

Higher quantum efficiency in near-IR, narrower point spread function and higher readout speed than with conventional sensors have been receiving increased emphasis in the development of CCDs and silicon PIN-CMOS sensors for use in large optical telescopes. Some key aspects in the development of such devices are reviewed.

RADEKA, V.

2006-04-03

228

A low power CMOS adaptive line equalizer for fast Ethernet  

Microsoft Academic Search

An analog adaptive line equalizer has been developed for 155 Mbps fast Ethernet data communication up to 100 m UTP (unshielded twisted pair) cable. The proposed adaptive equalizer is designed for the 0.35 ?m CMOS process. The designed equalizer has low power consumption (19 mW) and small silicon area (0.07 mm2).

Kwisung Yoo; Hoon Lee; Gunhee Han

2002-01-01

229

A CMOS GENERAL-PURPOSE SAMPLED-DATA ANALOGUE MICROPROCESSOR  

E-print Network

A CMOS GENERAL-PURPOSE SAMPLED-DATA ANALOGUE MICROPROCESSOR Piotr Dudek and Peter J. Hicks functions as an analogue microprocessor (AµP). The AµP executes software programs, in a way akin to a digital microprocessor, while nevertheless operating on analogue sampled data values. This enables

Dudek, Piotr

230

An integrated CMOS micromechanical resonator high-Q oscillator  

Microsoft Academic Search

A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator with the intent of achieving high stability. The operation and performance of micromechanical resonators are modeled, with emphasis on circuit and noise modeling of multiport resonators. A series resonant oscillator design is

Clark T.-C. Nguyen; Roger T. Howe

1999-01-01

231

Measurements of Si hybrid CMOS x-ray detector characteristics  

Microsoft Academic Search

The recent development of active pixel sensors as X-Ray focal plane arrays will place them in contention with CCDs on future satellite missions. Penn State University (PSU) is working with Teledyne Imaging Sensors (TIS) to develop X-Ray Hybrid CMOS devices (HCDs), a type of active pixel sensor with fast frame rates, adaptable readout timing and geometry, low power consumption, and

Stephen D. Bongiorno; Abraham D. Falcone; David N. Burrows; Robert Cook

2010-01-01

232

A CMOS Potentiostat for Control of Integrated MEMS Actuators  

E-print Network

. The fabricated chip has been employed for the control of off-chip electroactive polymer films and micro-actuatorsA CMOS Potentiostat for Control of Integrated MEMS Actuators Somashekar Bangalore Prakash, Pamela-- We describe a potentiostat designed for in situ electrochemical control of MEMS actuators

Maryland at College Park, University of

233

Effects Of Dose Rates On Radiation Damage In CMOS Parts  

NASA Technical Reports Server (NTRS)

Report describes measurements of effects of ionizing-radiation dose rate on consequent damage to complementary metal oxide/semiconductor (CMOS) electronic devices. Depending on irradiation time and degree of annealing, survivability of devices in outer space, or after explosion of nuclear weapons, enhanced. Annealing involving recovery beyond pre-irradiation conditions (rebound) detrimental. Damage more severe at lower dose rates.

Goben, Charles A.; Coss, James R.; Price, William E.

1990-01-01

234

Effect of a polywell leometry on a CMOS photodiode array  

Microsoft Academic Search

The effect of a polywell geometry hybridized with a stacked gradient poly-homojunction architecture, on the response of a CMOs compatible photodiode array was simulated. Crosstalk and sensitivity improved compared to the polywell geometry alone, for both back and front illumination.

Paul V. Jansz; Steven Hinckley; Graham Wild

2010-01-01

235

Effect of a Polywell geometry on a CMOS Photodiode Array  

Microsoft Academic Search

The effect of a polywell geometry hybridized with a stacked gradient poly-homojunction architecture, on the response of a CMOs compatible photodiode array was simulated. Crosstalk and sensitivity improved compared to the polywell geometry alone, for both back and front illumination

Paul V Jansz; Steven Hinckley; Graham Wild

2010-01-01

236

Research-grade CMOS image sensors for demanding space applications  

NASA Astrophysics Data System (ADS)

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

2004-06-01

237

Research-grade CMOS image sensors for remote sensing applications  

NASA Astrophysics Data System (ADS)

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding space applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this paper will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments and performances of CIS prototypes built using an imaging CMOS process will be presented in the corresponding section.

Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Martin-Gonthier, Philippe; Corbiere, Franck; Belliot, Pierre; Estribeau, Magali

2004-11-01

238

A foveated image sensor in standard CMOS technology  

Microsoft Academic Search

We describe the design and implementation of a CMOS foveated image sensor for use in mobile robotic and machine vision applications. The sensor is biologically motivated and performs a spatial image transformation from Cartesian to log-polar coordinates. As opposed to traditional approaches, the sensor benefits from a high degree of integration, minimal power consumption and ease of manufacture due to

Robert Wodnicki; Gordon W. Roberts; Martin D. Levine

1995-01-01

239

CMOS foveated image sensor: signal scaling and small geometry effects  

Microsoft Academic Search

A new foveated (log-polar) image sensor using standard CMOS technology has been designed and fabricated. The pixel distribution follows the log polar transform having more resolution in the center than in the periphery. For the fovea or central part, a different but also polar distribution has been adopted to fit the inner pixels. The particular problem of foveated image sensors

Fernando Pardo; Bart Dierickx; Danny Scheffer

1997-01-01

240

Low cost CMOS multi-electrode arrays Alex Lyakhov1  

E-print Network

significantly better corrosion immunity under stress. However, several tested electrodes have performed very of the recording probes and the amplifying circuitry can also enhance noise immunity in CMOS MEAs. Finally, entire electric stress. To facilitate stimulation in low cost MEAs, we investigate simple post-processing steps

Ginosar, Ran

241

CMOS Ultra Low Power Radiation Tolerant (CULPRiT) Microelectronics  

NASA Technical Reports Server (NTRS)

Space Electronics needs Radiation Tolerance or hardness to withstand the harsh space environment: high-energy particles can change the state of the electronics or puncture transistors making them disfunctional. This viewgraph document reviews the use of CMOS Ultra Low Power Radiation Tolerant circuits for NASA's electronic requirements.

Yeh, Penshu; Maki, Gary

2007-01-01

242

Photocurrent estimation from multiple nondestructive samples in CMOS image sensor  

Microsoft Academic Search

CMOS image sensors generally suffer form lower dynamic range than CCDs due to their higher readout noise. Their high speed readout capability and the potential of integrating memory and signal processing with the sensor on the same chip, open up many possibilities for enhancing their dynamic range. Earlier work have demonstrated the use of multiple non-destructive samples to enhance dynamic

Xinqiao Liu; Abbas El Gamal

2001-01-01

243

Low-power 2-D fully integrated CMOS fluxgate magnetometer  

Microsoft Academic Search

In this paper, we present a low-power, two-axis fluxgate magnetometer. The planar sensor is integrated in a standard CMOS process, which provides metal layers for the coils and electronics for the signal extraction and processing. The ferromagnetic core is placed diagonally above the four excitation coils by a compatible photolithographic post process, performed on a whole wafer. The sensor works

Predrag M. Drljaca; Pavel Kejik; Franck Vincent; Dominique Piguet; Radivoje S. Popovic

2005-01-01

244

CMOS Active-Pixel Image Sensor With Simple Floating Gates  

NASA Technical Reports Server (NTRS)

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

245

Integrated imaging sensor systems with CMOS active pixel sensor technology  

NASA Technical Reports Server (NTRS)

This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

2002-01-01

246

Quasi-TEM characteristic impedance of micromachined CMOS coplanar waveguides  

Microsoft Academic Search

Micromachined coplanar waveguides (CPW's) fabricated in CMOS technology consist of glass-encapsulated metal conductor strips, fully suspended by selective etching of the silicon substrate. The minimum amount of etching necessary for proper operation of the micromachined waveguides is determined by using an isolation criterion. In this paper, the quasi-TEM characteristic impedance of a CPW is derived, including the finite conductor thickness

Mehmet Ozgur; V. Milanov; Christian Zincke; Michael Gaitan; Mona E. Zaghloul

2000-01-01

247

Hybrid postprocessing etching for CMOS-compatible MEMS  

Microsoft Academic Search

A major limitation in the fabrication of microstructures as a postCMOS (complimentary metal oxide semiconductor) process has been overcome by the development of a hybrid processing technique, which combines both an isotropic and anisotropic etch step. Using this hybrid technique, microelectromechanical structures with sizes ranging from 0.05 to ~1 mm in width and up to 6 mm in length were

Nim H. Tea; V. Milanovic; Christian A. Zincke; John S. Suehle; Michael Gaitan; Mona E. Zaghloul; Jon Geist

1997-01-01

248

Performance of PHOTONIS' low light level CMOS imaging sensor for long range observation  

NASA Astrophysics Data System (ADS)

Identification of potential threats in low-light conditions through imaging is commonly achieved through closed-circuit television (CCTV) and surveillance cameras by combining the extended near infrared (NIR) response (800-10000nm wavelengths) of the imaging sensor with NIR LED or laser illuminators. Consequently, camera systems typically used for purposes of long-range observation often require high-power lasers in order to generate sufficient photons on targets to acquire detailed images at night. While these systems may adequately identify targets at long-range, the NIR illumination needed to achieve such functionality can easily be detected and therefore may not be suitable for covert applications. In order to reduce dependency on supplemental illumination in low-light conditions, the frame rate of the imaging sensors may be reduced to increase the photon integration time and thus improve the signal to noise ratio of the image. However, this may hinder the camera's ability to image moving objects with high fidelity. In order to address these particular drawbacks, PHOTONIS has developed a CMOS imaging sensor (CIS) with a pixel architecture and geometry designed specifically to overcome these issues in low-light level imaging. By combining this CIS with field programmable gate array (FPGA)-based image processing electronics, PHOTONIS has achieved low-read noise imaging with enhanced signal-to-noise ratio at quarter moon illumination, all at standard video frame rates. The performance of this CIS is discussed herein and compared to other commercially available CMOS and CCD for long-range observation applications.

Bourree, Loig E.

2014-05-01

249

Contact CMOS imaging of gaseous oxygen sensor array.  

PubMed

We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3](2+)) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-10-01

250

Contact CMOS imaging of gaseous oxygen sensor array  

PubMed Central

We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

2014-01-01

251

Improved Space Object Orbit Determination Using CMOS Detectors  

NASA Astrophysics Data System (ADS)

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario a sensor in a sun-synchronous LEO orbit, always pointing in the anti-sun direction to achieve optimum illumination conditions for small LEO debris, was simulated. For the space-based scenario the simulations showed a 20 130 % improvement of the accuracy of all orbital parameters when varying the frame rate from 1/3 fps, which is the fastest rate for a typical CCD detector, to 50 fps, which represents the highest rate of scientific CMOS cameras. Changing the epoch registration accuracy from a typical 20.0 ms for a mechanical shutter to 0.025 ms, the theoretical value for the electronic shutter of a CMOS camera, improved the orbit accuracy by 4 to 190 %. The ground-based scenario also benefit from the specific CMOS characteristics, but to a lesser extent.

Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

2014-09-01

252

CMOS VLSI Active-Pixel Sensor for Tracking  

NASA Technical Reports Server (NTRS)

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The diagonal-switch and memory addresses would be generated by the on-chip controller. The memory array would be large enough to hold differential signals acquired from all 8 windows during a frame period. Following the rapid sampling from all the windows, the contents of the memory array would be read out sequentially by use of a capacitive transimpedance amplifier (CTIA) at a maximum data rate of 10 MHz. This data rate is compatible with an update rate of almost 10 Hz, even in full-frame operation

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

253

Integration of Solar Cells on Top of CMOS Chips Part I: aSi Solar Cells  

Microsoft Academic Search

We present the monolithic integration of deep- submicrometer complementary metal-oxide-semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values above 7%. The yield of photovoltaic cells on planarized CMOS chips is 92%. This integration allows integrated energy harvesting using established process

Jiwu Lu; Alexey Y. Kovalgin; Karine H. M. van der Werf; Ruud E. I. Schropp; Jurriaan Schmitz

2011-01-01

254

An image identification system of seal with fingerprint based on CMOS image sensor  

Microsoft Academic Search

CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analog signal conditioning circuits, A\\/D converter and digital processing functions. Furthermore, CMOS sensors are the best choices for low-cost imaging systems. An image identification system based on CMOS image

Xu-cheng Xue; Shu-yan Zhang; Yong-fei Guo

2006-01-01

255

A low-power CMOS compatible integrated gas sensor using maskless tin oxide sputtering  

Microsoft Academic Search

This paper describes a CMOS compatible integrated gas sensor. The device was designed so that the front-end fabrication is fully compatible with the standard CMOS process. The non-CMOS compatible fabrication steps were carried out as post-processing steps. This included the silicon anisotropic etch to create the thermally isolated micro-hotplate (MHP) and the deposition of gas-sensitive thin films using maskless r.f.

Lie-yi Sheng; Zhenan Tang; Jian Wu; Philip C. H. Chan; Johnny K. O. Sin

1998-01-01

256

Heterogeneously Integrated 10Gb\\/s CMOS Optoelectronic Receiver for Long Haul Telecommunication  

Microsoft Academic Search

A fully integrated 10 Gb\\/s 1.3 to 1.55 mum CMOS optoelectronic receiver is demonstrated for the first time. By heterogeneously integrating of a CMOS transimpedance amplifier (TIA) with an InGaAs\\/InP PIN photodiode using a recently developed self-aligned wafer-level integration technology (SAWLIT), operation at 10 Gb\\/s is achieved. The CMOS transimpedance amplifier exhibits a transimpedance gain of 51 dBOmega and a

Hasan Sharifi; Saeed Mohammadi

2007-01-01

257

Digital pixel CMOS focal plane array with on-chip multiply accumulate units for low-latency image processing  

NASA Astrophysics Data System (ADS)

A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization occurs at the pixel level, enabling in-pixel DSP and noiseless data transfer from the pixel array to the peripheral processing units. The pipelined processing of row and column image data prior to off chip readout reduces the required output bandwidth of the image sensor, thus reducing the latency of computations necessary to implement various image processing systems. Data volume reductions of over 80% lead to sub 10?s latency for completing various tracking and sensor algorithms. This paper details the architecture of the pixel-processing imager (PPI) and presents some initial results from a prototype device fabricated in a standard 65nm CMOS process hybridized to a commercial off-the-shelf short-wave infrared (SWIR) detector array.

Little, Jeffrey W.; Tyrrell, Brian M.; D'Onofrio, Richard; Berger, Paul J.; Fernandez-Cull, Christy

2014-06-01

258

Nanophotonic integration in state-of-the-art CMOS foundries.  

PubMed

We demonstrate a monolithic photonic integration platform that leverages the existing state-of-the-art CMOS foundry infrastructure. In our approach, proven XeF2 post-processing technology and compliance with electronic foundry process flows eliminate the need for specialized substrates or wafer bonding. This approach enables intimate integration of large numbers of nanophotonic devices alongside high-density, high-performance transistors at low initial and incremental cost. We demonstrate this platform by presenting grating-coupled, microring-resonator filter banks fabricated in an unmodified 28 nm bulk-CMOS process by sharing a mask set with standard electronic projects. The lithographic fidelity of this process enables the high-throughput fabrication of second-order, wavelength-division-multiplexing (WDM) filter banks that achieve low insertion loss without post-fabrication trimming. PMID:21369052

Orcutt, Jason S; Khilo, Anatol; Holzwarth, Charles W; Popovi?, Milos A; Li, Hanqing; Sun, Jie; Bonifield, Thomas; Hollingsworth, Randy; Kärtner, Franz X; Smith, Henry I; Stojanovi?, Vladimir; Ram, Rajeev J

2011-01-31

259

65 nm CMOS Sensors Applied to Mathematically Exact Colorimetric Reconstruction  

E-print Network

Extracting colorimetric image information from the spectral characteristics of image sensors is a key issue in accurate image acquisition. Technically feasible filter/sensor combinations usually do not replicate colorimetric responses with sufficient accuracy to be directly applicable to color representation. A variety of transformations have been proposed in the literature to compensate for this. However, most of those rely on heuristics and/or introduce a reconstruction dependent on the composition of the incoming illumination. In this work, we present a spectral reconstruction method that is independent of illumination and is derived in a mathematically strict way. It provides a deterministic method to arrive at a least mean squared error approximation of a target spectral characteristic from arbitrary sensor response curves. Further, we present a new CMOS sensor design in a standard digital 65nm CMOS technology. Novel circuit techniques are used to achieve performance comparable with much larger-sized spe...

Mayr, C; Krause, A; Schlüßler, J -U; Schüffny, R

2014-01-01

260

Diffuse reflectance measurements using lensless CMOS imaging chip  

NASA Astrophysics Data System (ADS)

To assess superficial epithelial microcirculation, a diagnostic tool should be able to detect the heterogeneity of microvasculature, and to monitor qualitative derangement of perfusion in a diseased condition. Employing a lensless CMOS imaging chip with an RGB Bayer filter, experiments were conducted with a microfluidic platform to obtain diffuse reflectance maps. Haemoglobin (Hb) solution (160 g/l) was injected in the periodic channels (grooves) of the microfluidic phantom which were covered with ~250 ?m thick layer of intralipid to obtain a diffusive environment. Image processing was performed on data acquired on the surface of the phantom to evaluate the diffuse reflectance from the subsurface periodic pattern. Thickness of the microfluidic grooves, the wavelength dependent contrast between Hb and the background, and effective periodicity of the grooves were evaluated. Results demonstrate that a lens-less CMOS camera is capable of capturing images of subsurface structures with large field of view.

Schelkanova, I.; Pandya, A.; Shah, D.; Lilge, L.; Douplik, A.

2014-10-01

261

324GHz CMOS VCO Using Linear Superimposition Technique  

NASA Technical Reports Server (NTRS)

Terahertz (frequencies ranged from 300GHz to 3THz) imaging and spectroscopic systems have drawn increasing attention recently due to their unique capabilities in detecting and possibly analyzing concealed objects. The generation of terahertz signals is nonetheless nontrivial and traditionally accomplished by using either free-electron radiation, optical lasers, Gunn diodes or fundamental oscillation by using III-V based HBT/HEMT technology[1-3]... We have substantially extended the operation range of deep-scaled CMOS by using a linear superimposition method, in which we have realized a 324GHz VCO in 90nm digital CMOS with 4GHz tuning range under 1V supply voltage. This may also pave the way for ultra-high data rate wireless communications beyond that of IEEE 802.15.3c and reach data rates comparable to that of fiber optical communications, such as OC768 (40Gbps) and beyond.

Daquan, Huang; LaRocca, Tim R.; Samoska, Lorene A; Fung, Andy; Chang, Frank

2007-01-01

262

A Low-Cost CMOS Programmable Temperature Switch  

PubMed Central

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 ?m CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45—120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 ?A at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

Li, Yunlong; Wu, Nanjian

2008-01-01

263

CMOS Silicon Physical Unclonable Functions Based on Intrinsic Process Variability  

Microsoft Academic Search

This paper presents an extreme-low-power mixed-signal CMOS integrated circuit for product identifi- cation and anti-counterfeiting, which implements a physical unclonable function operating with a challenge-response scheme. We devise a series of circuits and algorithmic solutions based on the use of a process monitor and on the prediction of the erratic response bits which allow to suppress the effects of temperature,

Stefano Stanzione; Daniele Puntin; Giuseppe Iannaccone

2011-01-01

264

Development of a silicon gate CMOS technology with small structures  

NASA Astrophysics Data System (ADS)

The development of HCMOS technology for 3 to 4 microns structures in order to improve packing density and performance for very large scale integration CMOS circuits, operating at 1,5V, is outlined. Design rule definition, photolithography/contact and projection, layout techniques, and process development (high value polysilicon resistors) are discussed. The technology developed was successfully demonstrated on an advanced 4 MHz (1,5V) watch circuit.

Milosevic, I.; Tilenschi, L.; Luft, R.; Cornwell, D.

1982-09-01

265

High Speed Smart CMOS Sensor for Adaptive Optics - Poster Paper  

Microsoft Academic Search

We describe the design and experimental performance of a smart Shack-Hartmann wavefront sensor based on a high speed CMOS imager chip and a Field Programmable Gate Array (FPGA) capable of full frame operation at 500 frames\\/s and operated via simple USB2.0 interface. Two FPGA firmware designs are described. The serial version is most suited to modest speed (100 frames\\/s) high

T. D. Raymond; Daniel R. Neal; A. Whitehead; G. Wirth

2008-01-01

266

A generation of CMOS readout ASICs for CZT detectors  

Microsoft Academic Search

As a result of a cooperation between Brookhaven National Laboratory and eV Products a generation of high performance readout ASICs was developed. The ASICs, realized in CMOS 0.5 ?m technology, are available in several different versions, single or multi-channel and with unipolar or bipolar shaper, in view of their use in research, spectroscopy, medical, safeguard and industrial applications. Four innovative

G. De Geronimo; P. O'Connor; J. Grosholz

1999-01-01

267

A low-phase-noise K-band CMOS VCO  

Microsoft Academic Search

A novel circuit topology for low-phase-noise voltage controlled oscillators (VCOs) is presented in this letter. By employing a PMOS cross-coupled pair with a capacitive feedback, superior circuit performance can be achieved especially at higher frequencies. Based on the proposed architecture, a prototype VCO implemented in a 0.18-mum CMOS process is demonstrated for K-band applications. From the measurement results, the VCO

Hsieh-Hung Hsieh; Liang-Hung Lu

2006-01-01

268

CMOS metal replacement gate transistors using tantalum pentoxide gate insulator  

Microsoft Academic Search

This paper reports a full CMOS process using a combination of a TiN\\/W Metal Replacement Gate Transistor design with a high dielectric constant gate insulator of tantalum pentoxide over thin remote plasma nitrided gate oxide. MOS devices with high gate capacitances equivalent to that for <2 nm SiO2 but having relatively low gate leakage are reported. Transistors with gate lengths

A. Chatterjee; R. A. Chapman; K. Joyner; M. Otobe; S. Hattangady; M. Bevan; G. A. Brown; H. Yang; Q. He; D. Rogers; S. J. Fang; R. Kraft; A. L. P. Rotondaro; M. Terry; K. Brennan; S.-W. Aur; J. C. Hu; H.-L. Tsai; P. Jones; G. Wilk; M. Aoki; M. Rodder; I.-C. Chen

1998-01-01

269

Transient irradiation effect on 4000 series CMOS circuits  

Microsoft Academic Search

Various CMOS devices from the 4000 series were studied as to the effects on circuit performance of exposure to an X-ray burst. The functional characteristics of the equipment were determined before irradiation, then compared with electrical measurements made on the same equipment after exposure. The radiative beam was produced by an X-ray emitter which generates 20 billion rad\\/sec. Total dosage

G. Goeransson; P. Zamuhl; B. Danielsson

1981-01-01

270

High-Voltage CMOS ESD and the Safe Operating Area  

Microsoft Academic Search

Established methods for testing ESD robustness of high-voltage pins in smart power CMOS can lead to erroneous results. This paper investigates both LDNMOS and certain types of SCRLDMOS (SCRs embedded in LDNMOS) high-voltage clamps for safe-operating-area collapse due to trigger voltage (V t1) walk-in after transmission-line pulsing (TLP) corresponding to leakage-current increase below I t2. For the first time, the

Andrew J. Walker; Helmut Puchner; Sai Prashanth Dhanraj

2009-01-01

271

Total dose testing of a CMOS charged particle spectrometer  

SciTech Connect

A first-generation CMOS Charged Particle Spectrometer chip was designed at JPL for flight on the STRV-2 spacecraft. These devices will collect electron and proton spectra in low Earth orbit as part of an experiment to demonstrate Active Pixel Sensor (APS) technology in space. This paper presents the results of total dose testing on these chips and, where possible, attempts to extend the results to other Active Pixel Sensors.

Hancock, B.R.; Soli, G.A. [California Inst. of Tech., Pasadena, CA (United States). Jet Propulsion Lab.] [California Inst. of Tech., Pasadena, CA (United States). Jet Propulsion Lab.

1997-12-01

272

High performance CMOS integrated circuits for optical receivers  

E-print Network

to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Approved by: Chair of Committee, Aydin Karsilayan Committee Members, Jose Silva-Martinez Reza Langari... Prasad Enjeti Head of Department, Costas Georghiades December 2006 Major Subject: Electrical Engineering iii ABSTRACT High Performance CMOS Integrated Circuits for Optical Receivers. (December 2006) MohammadReza SamadiBoroujeni, B...

SamadiBoroujeni, MohammadReza

2009-05-15

273

RF CMOS UWB transmitter and receiver front-end design  

E-print Network

, Cam Nguyen Committee Members, Steven Wright Laszlo Kish Reza Langari Head of Department, Costas Georghiades May 2008 Major Subject: Electrical Engineering iii ABSTRACT Radio Frequency (RF) Complementary Metal-Oxide Semiconductor (CMOS... advice, encouragement and support throughout this research. I would also like to thank my committee members, Dr. Steven Wright, Dr. Laszlo Kish, and Dr. Reza Langari for their valuable time and advice. I am also grateful to my wife, Qingmei Lu...

Miao, Meng

2009-05-15

274

A 200MHz 64-b dual-issue CMOS microprocessor  

Microsoft Academic Search

A 400-MIPS\\/200-MFLOPS (peak) custom 64-b VLSI CPU is described. The chip is fabricated in a 0.75-?m CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm×13.9 mm and contains 1.68 M transistors. The chip includes separate 8-kbyte instruction and data caches and a fully pipelined floating-point unit (FPU) that can handle both

D. W. Dobberpuhl; R. T. Witek; R. Allmon; R. Anglin; D. Bertucci; S. Britton; L. Chao; R. A. Conrad; D. E. Dever; B. Gieseke; S. M. N. Hassoun; G. W. Hoeppner; K. Kuchler; M. Ladd; B. M. Leary; L. Madden; E. J. McLellan; D. R. Meyer; J. Montanaro; D. A. Priore; V. Rajagopalan; S. Samudrala; S. Santhanam

1992-01-01

275

Monolithic CMOS detector module for photon counting and picosecond timing  

Microsoft Academic Search

A monolithic optoelectronic module for counting and timing single optical photons has been designed and fabricated in CMOS technology. It integrates a single-photon avalanche diode (SPAD) of 12 ?m-diameter with a complete active-quenching and active-reset circuit. The detector operates in Geiger-mode biased above breakdown level, with overvoltage adjustable up to 20 V. The on-chip electronics detects the rise of the

F. Zappa; S. Tisa; A. Gulinatti; A. Gallivanoni; S. Cova

2004-01-01

276

Mask Programmable CMOS Transistor Arrays for Wideband RF Integrated Circuits  

Microsoft Academic Search

A mask programmable technology to implement RF and microwave integrated circuits using an array of standard 90-nm CMOS transistors is presented. Using this technology, three wideband amplifiers with more than 15-dB forward transmission gain operating in different frequency bands inside a 4-22-GHz range are implemented. The amplifiers achieve high gain-bandwidth products (79-96 GHz) despite their standard multistage designs. These amplifiers

Laleh Rabieirad; Edgar J. Martinez; Saeed Mohammadi

2009-01-01

277

A BiCMOS integrated charge to amplitude converter  

SciTech Connect

This paper describes a fast two channel gated charge to amplitude converter (QAC) which has been designed with the 1.2 {mu}m BiCMOS technology from AMS (Austria Mikro Systeme). It can integrate fast negative impulse currents up to 100 mA. Associated with an audio 18 bit low cost ADC, it can easily be used to make a 12 to 13 bit QDC. The problems of current to current conversion, pedestal and offset stability are discussed.

Gallin-Martel, L.; Pouxe, J.; Rossetto, O. [Institut des Sciences Nucleaires, Grenoble (France)

1996-12-31

278

A 1-V piecewise curvature-corrected CMOS bandgap reference  

Microsoft Academic Search

A 1-V piecewise curvature-corrected CMOS bandgap reference (BGR) is proposed. It features in utilizing piecewise corrected current to a conventional first-order current-mode BGR. The corrected current is zero, exponential with temperature and proportional to the squared temperature in the lower, middle and upper temperature range (TR). Simulated results indicate that proposed BGR achieves temperature coefficient (TC) of 1.18ppm\\/°C in the

Jing-hu Li; Yu-nan Fu; Yong-sheng Wang

2008-01-01

279

A comprehensive varactor study for advanced CMOS RFIC design  

Microsoft Academic Search

The key performance index related to RF circuit design for a portfolio of varactor structures, N+\\/Nwell MOS varactor (N+\\/NW MOSVAR). P+\\/Pwell MOSVAR (P+\\/PW MOSVAR) and junction varactor (JVAC) were studied using advanced 0.18?m to 90nm RF-CMOS technologies. The engineering and trade-offs for quality factor (Q-factor), tuning ratio (TR = Cmax \\/ Cmin), capacitance mismatch and flicker noise for different device

C. F. Huang; C. C. Wu; C. H. Chen; C. C. Ho; Y. J. Chan; C. S. Chang; C. P. Chao; G. J. Chern

2005-01-01

280

Radiation effects in a CMOS active pixel sensor  

Microsoft Academic Search

A CMOS active pixel sensor has been evaluated with Co60, 10 MeV proton and heavy-ion irradiation. Permanent displacement damage effects were seen but total ionizing dose-induced dark current and increase in power supply current annealed at 100°C. Large changes in responsivity were seen after proton irradiation, which subsequently annealed. Mechanisms for these responsivity changes are discussed, but a definitive cause

Gordon R. Hopkinson

2000-01-01

281

CMOS bandgap references and temperature sensors and their applications  

Microsoft Academic Search

Two main parts have been presented in this thesis: device characterization and circuit. \\u000aIn integrated bandgap references and temperature sensors, the IC(VBE, characteristics of bipolar transistors are used to generate the basic signals with high accuracy. To investigate the possibilities to fabricate high-precision bandgap references and temperature sensors in low-cost CMOS technology, the electrical characteristics of substrate bipolar pnp transistors

G. Wang

2005-01-01

282

A linear fully balanced CMOS OTA for VHF filtering applications  

Microsoft Academic Search

A linear, fully balanced, voltage-tunable CMOS operational transconductance amplifier (OTA) with large dc gain and wide bandwidth is described. The approach uses a two-differential-pair transconductor with a cross-coupled input stage together with a negative resistance load for compensating the parasitic output resistance of the OTA. Since no additional internal nodes are generated, dc gain enhancement is obtained without bandwidth limitation.

S. Szczepanski; Jacek Jakusz; Rolf Schaumann

1997-01-01

283

CMOS low-noise amplifier design optimization techniques  

Microsoft Academic Search

This paper reviews and analyzes four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-constrained simultaneous noise and input matching (PCSNIM) techniques. Very simple and insightful sets of noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques.

Trung-Kien Nguyen; Chung-Hwan Kim; Gook-Ju Ihm; Moon-Su Yang; Sang-Gug Lee

2004-01-01

284

DARWIN: CMOS opamp synthesis by means of a genetic algorithm  

Microsoft Academic Search

Abstract—DARWIN is a ,tool that is able ,to synthesize CMOS opamps, on the basis of a genetic algorithm. A ran- domly generated initial set of opamps,evolves to a set in which the topologies as well as the transistor sizes of the,opamps ,are adapted to the ,required performance ,specifications. Several design examples illustrate the behavior of DARWIN. I. INTRODUCTION The analog

Wim Kruiskamp; Domine Leenaerts

1995-01-01

285

Single core fully integrated CMOS micro-fluxgate magnetometer  

Microsoft Academic Search

A new fully integrated 2D micro-fluxgate magnetometer is presented. This magnetometer is integrated in a standard CMOS process and uses a ferromagnetic core integrated on the chip by a photolithographic post-process compatible with the integrated circuit technology. The cross-shaped ferromagnetic core is placed diagonally above four excitation coils, two for each measurement axis. A novel electronic signal extraction technique is

Predrag M. Drlja?a; Pavel Kejik; Franck Vincent; Dominique Piguet; François Gueissaz; Radivoje S. Popovi?

2004-01-01

286

Phase Noise and Jitter in CMOS Ring Oscillators  

Microsoft Academic Search

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker (1\\/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise,

Asad A. Abidi

2006-01-01

287

Radiation Detectors for HEP Applications Using Standard CMOS Technology  

Microsoft Academic Search

The suitability of standard CMOS technology featuring no epitaxial layer for particle detection has been investigated through extensive experimental characterization. Different pixel layout and read-out schemes have been devised and implemented, as well as different test strategies. In this work test results are reported concerning the response of the detector to IR laser, beta-particles and X-rays stimuli, thus confirming the

D. Passeri; A. Marras; P. Placidi; P. Delfanti; D. Biagetti; L. Servoli; G. M. Bilei; P. Ciampolini

2006-01-01

288

Linear dynamic range enhancement in a CMOS imager  

NASA Technical Reports Server (NTRS)

A CMOS imager with increased linear dynamic range but without degradation in noise, responsivity, linearity, fixed-pattern noise, or photometric calibration comprises a linear calibrated dual gain pixel in which the gain is reduced after a pre-defined threshold level by switching in an additional capacitance. The pixel may include a novel on-pixel latch circuit that is used to switch in the additional capacitance.

Pain, Bedabrata (Inventor)

2008-01-01

289

Commercial Buildings Characteristics, 1992  

SciTech Connect

Commercial Buildings Characteristics 1992 presents statistics about the number, type, and size of commercial buildings in the United States as well as their energy-related characteristics. These data are collected in the Commercial Buildings Energy Consumption Survey (CBECS), a national survey of buildings in the commercial sector. The 1992 CBECS is the fifth in a series conducted since 1979 by the Energy Information Administration. Approximately 6,600 commercial buildings were surveyed, representing the characteristics and energy consumption of 4.8 million commercial buildings and 67.9 billion square feet of commercial floorspace nationwide. Overall, the amount of commercial floorspace in the United States increased an average of 2.4 percent annually between 1989 and 1992, while the number of commercial buildings increased an average of 2.0 percent annually.

Not Available

1994-04-29

290

An integrated CMOS detection system for optical short-pulse  

NASA Astrophysics Data System (ADS)

We present design of a front-end readout system consisting of charge sensitive amplifier (CSA) and pulse shaper for detection of stochastic and ultra-small semiconductor scintillator signal. The semiconductor scintillator is double sided silicon detector (DSSD) or avalanche photo detector (APD) for high resolution and peak signal reliability of ?-ray or X-ray spectroscopy. Such system commonly uses low noise multichannel CSA. Each CSA in multichannel includes continuous reset system based on tens of M? and charge-integrating capacitor in feedback loop. The high value feedback resistor requires large area and huge power consumption for integrated circuits. In this paper, we analyze these problems and propose a CMOS short pulse detection system with a novel CSA. The novel CSA is composed of continuous reset system with combination of diode connected PMOS and 100 fF. This structure has linearity with increased input charge quantity from tens of femto-coulomb to pico-coulomb. Also, the front-end readout system includes both slow and fast shapers for detecting CSA output and preventing pile-up distortion. Shaping times of fast and slow shapers are 150 ns and 1.4 ?s, respectively. Simulation results of the CMOS detection system for optical short-pulse implemented in 0.18 ?m CMOS technology are presented.

Kim, Chang-Gun; Hong, Nam-Pyo; Choi, Young-Wan

2014-03-01

291

Development of CMOS Imager Block for Capsule Endoscope  

NASA Astrophysics Data System (ADS)

This paper presents the development of imager block to be associated in a capsule endoscopy system. Since the capsule endoscope is used to diagnose gastrointestinal diseases, the imager block must be in small size which is comfortable for the patients to swallow. In this project, a small size 1.5V button battery is used as the power supply while the voltage supply requirements for other components such as microcontroller and CMOS image sensor are higher. Therefore, a voltage booster circuit is proposed to boost up the voltage supply from 1.5V to 3.3V. A low power microcontroller is used to generate control pulses for the CMOS image sensor and to convert the 8-bits parallel data output to serial data to be transmitted to the display panel. The results show that the voltage booster circuit was able to boost the voltage supply from 1.5V to 3.3V. The microcontroller precisely controls the CMOS image sensor to produce parallel data which is then serialized again by the microcontroller. The serial data is then successfully translated to 2fps image and displayed on computer.

Shafie, S.; Fodzi, F. A. M.; Tung, L. Q.; Lioe, D. X.; Halin, I. A.; Hasan, W. Z. W.; Jaafar, H.

2014-04-01

292

Cryogenic CMOS circuits for single charge digital readout.  

SciTech Connect

The readout of a solid state qubit often relies on single charge sensitive electrometry. However the combination of fast and accurate measurements is non trivial due to large RC time constants due to the electrometers resistance and shunt capacitance from wires between the cold stage and room temperature. Currently fast sensitive measurements are accomplished through rf reflectrometry. I will present an alternative single charge readout technique based on cryogenic CMOS circuits in hopes to improve speed, signal-to-noise, power consumption and simplicity in implementation. The readout circuit is based on a current comparator where changes in current from an electrometer will trigger a digital output. These circuits were fabricated using Sandia's 0.35 {micro}m CMOS foundry process. Initial measurements of comparators with an addition a current amplifier have displayed current sensitivities of < 1nA at 4.2K, switching speeds up to {approx}120ns, while consuming {approx}10 {micro}W. I will also discuss an investigation of noise characterization of our CMOS process in hopes to obtain a better understanding of the ultimate limit in signal to noise performance.

Gurrieri, Thomas M.; Longoria, Erin Michelle; Eng, Kevin; Carroll, Malcolm S.; Hamlet, Jason R.; Young, Ralph Watson

2010-03-01

293

CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.  

SciTech Connect

Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

2008-08-01

294

Packaged X-band Phased-Arrays and High Data-Rate Switching Matrices in Advanced CMOS Processes  

E-print Network

s transimpedance amplifier,” IEEE J. Solid-State Circuits,for CMOS amplifiers,” IEEE J. Solid-State Circuits, vol. 41,amplifier and ESD protection circuit in 0.18-µm CMOS technology,” IEEE J. Solid-State

Shin, Donghyup

295

1-V Linear CMOS Transconductor with 65 dB THD in Nano-Scale CMOS Technology  

Microsoft Academic Search

This paper presents a high linearity MOSFET-only transconductor based on differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. Transconductance tuning could be achieved by transistors operating in the linear region. The simulated total harmonic distortion (THD) under 1-V power supply voltage shows 12 dB improvement of

Tien-yu Lo; Chung-chih Hung

2007-01-01

296

Pressure Sensor Monolithically Integrating MEMS and CMOS-LSI with CMOS Compatible ``Back-end-of-line MEMS processes''  

Microsoft Academic Search

Back-end-of-line (BEOL) MEMS processes for a compact, high-precision pressure sensor was developed. A CMOS-LSI-integrated capacitive pressure-sensor was fabricated with a chip size of 0.72 mm2 using developed BEOL MEMS processes. Multi-sensor chip (with a size of 1.7 by 1.9 mm2) which consists of pressure sensor, temperature sensor and high-precision measurement circuits was also fabricated, and precise atmospheric pressure measurement (~

Tsukasa Fujimori; Hideaki Takano; Yuko Hanaoka; Yasushi Goto

2010-01-01

297

High gain CMOS image sensor design and fabrication on SOI and bulk technology  

NASA Astrophysics Data System (ADS)

The CMOS imager is now competing with the CCD imager, which still dominates the electronic imaging market. By taking advantage of the mature CMOS technology, the CMOS imager can integrate AID converters, digital signal processing (DSP) and timing control circuits on the same chip. This low cost and high-density integration solution to the image capture is the strong driving force in industry. Silicon on insulator (SOI) is considered as the coming mainstream technology. It challenges the current bulk CMOS technology because of its reduced power consumption, high speed, radiation hardness etc. Moving the CMOS imager from the bulk to the SOI substrate will benefit from these intrinsic advantages. In addition, the blooming and the cross-talk between the pixels of the sensor array can be ideally eliminated, unlike those on the bulk technology. Though there are many advantages to integrate CMOS imager on SOI, the problem is that the top silicon film is very thin, such as 2000Å. Many photons can just pass through this layer without being absorbed. A good photo-detector on SOI is critical to integrate SOI CMOS imagers. In this thesis, several methods to make photo-detectors on SOI substrate are investigated. A floating gate MOSFET on SOI substrate, operating in its lateral bipolar mode, is photon sensitive. One step further, the SOI MOSFET gate and body can be tied together. The positive feedback between the body and gate enables this device have a high responsivity. A similar device can be found on the bulk CMOS technology: the gate-well tied PMOSFET. A 32 x 32 CMOS imager is designed and characterized using such a device as the light-sensing element. I also proposed the idea of building hybrid active pixels on SOI substrate. Such devices are fabricated and characterized. The work here represents my contribution on the CMOS imager, especially moving the CMOS imager onto the SOI substrate.

Zhang, Weiquan

2000-12-01

298

Determining the thermal expansion coefficient of thin films for a CMOS MEMS process using test cantilevers  

NASA Astrophysics Data System (ADS)

Many standard CMOS processes, provided by existing foundries, are available. These standard CMOS processes, with stacking of various metal and dielectric layers, have been extensively applied in integrated circuits as well as micro-electromechanical systems (MEMS). It is of importance to determine the material properties of the metal and dielectric films to predict the performance and reliability of micro devices. This study employs an existing approach to determine the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. Test cantilevers with different stacking of metal and dielectric layers for standard CMOS processes have been designed and implemented. The CTEs of standard CMOS films can be determined from measurements of the out-of-plane thermal deformations of the test cantilevers. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacture Company 0.35??m 2P4M CMOS process are characterized. Eight test cantilevers with different stacking of CMOS layers and an auxiliary Si cantilever on a SOI wafer are fabricated. The equivalent elastic moduli and CTEs of the CMOS thin films including the metal and dielectric layers are determined, respectively, from the resonant frequency and static thermal deformation of the test cantilevers. Moreover, thermal deformations of cantilevers with stacked layers different to those of the test beams have been employed to verify the measured CTEs and elastic moduli.

Cheng, Chao-Lin; Tsai, Ming-Han; Fang, Weileun

2015-02-01

299

Analog CMOS Design for Optical Coherence Tomography Signal Detection and Processing  

Microsoft Academic Search

A CMOS circuit was designed and fabricated for optical coherence tomography (OCT) signal detection and processing. The circuit includes a photoreceiver, differential gain stage and lock-in amplifier based demodulator. The photoreceiver consists of a CMOS photodetector and low noise differential transimpedance amplifier which converts the optical interference signal into a voltage. The differential gain stage further amplifies the signal. The

Wei Xu; David L. Mathine; Jennifer K. Barton

2008-01-01

300

Resizing Methodology for CMOS Analog Circuits Timothe Levi, Jean Tomas, Nolle Lewis, Pascal Fouillat  

E-print Network

Resizing Methodology for CMOS Analog Circuits Timothée Levi, Jean Tomas, Noëlle Lewis, Pascal This paper proposes a CMOS resizing methodology for analog circuits during a technology migration smaller minimum length, we expect to obtain a decrease of area. This methodology is applied to both linear

Paris-Sud XI, Université de

301

CMOS-compatible Titanium Dioxide Deposition for Athermalization of Silicon Photonic Waveguides  

E-print Network

CMOS-compatible Titanium Dioxide Deposition for Athermalization of Silicon Photonic Waveguides@ucdavis.edu , sbyoo@ucdavis.edu Abstract: We discuss titanium dioxide material development for CMOS compatible fabrication and integration of athermal silicon photonic components. Titanium dioxide overclad ring modulators

Yoo, S. J. Ben

302

Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study  

E-print Network

Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study Oleg Garitselov1 , Saraju P. Mohanty2 , Elias Kougianos3 , and Priyadarsan Patra4 NanoSystem Design Laboratory (NSDL, http Abstract--Fast design space exploration of complex nano- CMOS mixed-signal circuits is an important problem

Mohanty, Saraju P.

303

A 1.1 V SOI CMOS frequency divider using body-inputting SCL circuit technology  

Microsoft Academic Search

SOI CMOS technology is one of the most effective candidates for realization of low power and high performance digital\\/RF circuits, with demand for single-chip LSI in portable communications equipment. By optimizing the threshold voltage, the CMOS logic in digital circuits can operate at less than 1 V (Fujii et al, 1999; Fuse et al, 1997). In the series gating ECL

T. Fuse; M. Tokumasu; S. Kawanaka; H. Fujii; A. Kameyama; M. Yoshimi; S. Watanabe

2000-01-01

304

A LOW-POWER CMOS NEURAL AMPLIFIER WITH AMPLITUDE MEASUREMENTS FOR SPIKE SORTING  

E-print Network

A LOW-POWER CMOS NEURAL AMPLIFIER WITH AMPLITUDE MEASUREMENTS FOR SPIKE SORTING T. Horiuchi 1 College, PA 16801, USA ABSTRACT Integrated, low-power, low-noise CMOS neural amplifiers have recently are developing low- power neural amplifiers with integrated pre-filtering and measurements of the spike signal

Maryland at College Park, University of

305

CMOS On-Chip Optoelectronic Neural Interface Device with Integrated Light Source for Optogenetics  

Microsoft Academic Search

A novel optoelectronic neural interface device is proposed for target applications in optogenetics for neural science. The device consists of a light emitting diode (LED) array implemented on a CMOS image sensor for on-chip local light stimulation. In this study, we designed a suitable CMOS image sensor equipped with on-chip electrodes to drive the LEDs, and developed a device structure

Y Sawadsaringkarn; H Kimura; Y Maezawa; A Nakajima; T Kobayashi; K Sasagawa; T Noda; T Tokuda; J Ohta

2012-01-01

306

CMOS circuit testing via time-resolved luminescence measurements and simulations  

Microsoft Academic Search

The continuous trend in modern CMOS technology toward smaller devices and faster clock frequency is challenging the picosecond imaging circuit analysis technique. In this paper we discuss the role of the single-photon avalanche diode with very sharp time resolution in testing CMOS circuits. Thanks to the 30 ps-time resolution, innovative measurements regarding delays and jitter are presented, along with a

Franco Stellari; Alberto Tosi; Franco Zappa; Sergio Cova

2004-01-01

307

A Redox-Enzyme-Based Electrochemical Biosensor with a CMOS Integrated Bipotentiostat  

E-print Network

A Redox-Enzyme-Based Electrochemical Biosensor with a CMOS Integrated Bipotentiostat Yue Huang enzymes and a supporting CMOS bipotentiostat. The bipotentiostat architecture supports redox recycling was created on a microfabricated interdigitated electrode array as an example redox-enzyme-based biosensor

Mason, Andrew

308

Robust Intermediate Read-Out for Deep Submicron Technology CMOS Image Sensors  

Microsoft Academic Search

In this paper, a CMOS image sensor featuring a novel spiking pixel design and a robust digital intermediate read-out is proposed for deep submicron CMOS technologies. The proposed read-out scheme exhibits a relative insensitivity to the ongoing aggressive scaling of the supply voltage. It is based on a novel compact spiking pixel circuit, which combines digitizing and memory functions. Illumination

Chen Shoushun; Farid Boussaid; Amine Bermak

2008-01-01

309

Novel color processing architecture for digital cameras with CMOS image sensors  

Microsoft Academic Search

This paper presents a color processing architecture for digital color cameras utilizing complementary metal oxide semiconductor (CMOS) image sensors. The proposed architecture gives due consideration to the peculiar aspects of CMOS image sensors and the human visual perception related to the particular application of digital color photography. A main difference between the proposed method arid the conventional systems is the

Chaminda Weerasinghe; Wanqing Li; Igor Kharitonenko; Magnus Nilsson; Sue Twelves

2005-01-01

310

A CMOS Delayed Locked Loop (DLL) for Reducing Clock Skew to Under 500ps  

E-print Network

]. Tgta1 I 44.000 Before the DLL circuit was mapped on to a 0.8 pm CMOS process, a detailed analysis on the stabili- ty characteristics of the DLL loop was carried out to determine the component valuesA CMOS Delayed Locked Loop (DLL) for Reducing Clock Skew to Under 500ps Element Phase detector

Ayers, Joseph

311

A single poly EEPROM cell structure for use in standard CMOS processes  

Microsoft Academic Search

A single poly EEPROM cell structure implemented in a standard CMOS Process is developed. It consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysilicon gate. The common gate works as a “floating gate”. The inversion layer as “control node (gate)”. Test chips which were fabricated in a 0.8 ?m\\/150 Å standard CMOS logic process showed

Katsuhiko Ohsaki; Noriaki Asamoto; Shunichi Takagaki

1994-01-01

312

Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs  

Microsoft Academic Search

This paper examines the reliability of gate oxide shorts in CMOS ICs. Gate oxide shorts cause increased quiescent IDD but may not initially affect functionality. These shorts can subsequently change due to thermal and electric field stress during operation and cause functional failure. Therefore, gate oxide defects can significantly degrade CMOS IC reliability. 14 refs.

Jerry M. Soden; Charles F. Hawkins

1986-01-01

313

A CMOS MIXED-SIGNAL MAGNITUDE AND PHASE DETECTOR RAJESH SATYAVADA, B.Tech  

E-print Network

A CMOS MIXED-SIGNAL MAGNITUDE AND PHASE DETECTOR BY RAJESH SATYAVADA, B.Tech A technical report Mexico March 2011 #12;"A CMOS Mixed-Signal Magnitude and Phase detector," a project report pre- pared six semester we shared many a memorable moments which made my student life fun here. iv #12;I would

Furth, Paul

314

CMOS A-D Interface Circuits Lecture 25 Oversampling ADC Prof. Y. Chiu  

E-print Network

CMOS A-D Interface Circuits Lecture 25 ­ Oversampling ADC Prof. Y. Chiu ECE 598YC Fall 2005 ­ 1 ­ Oversampling ADC #12;CMOS A-D Interface Circuits Lecture 25 ­ Oversampling ADC Prof. Y. Chiu ECE 598YC Fall. Y. Chiu ECE 598YC Fall 2005 ­ 3 ­ Antialiasing Filter (AAF) · Input signal must be band

Allen, Jont

315

Scaled CMOS Technology Reliability Users Guide  

NASA Technical Reports Server (NTRS)

The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. A methodology on how to accomplish this and techniques for deriving the expected product-level reliability on commercial memory products are provided.Competing mechanism theory and the multiple failure mechanism model are applied to the experimental results of scaled SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope (beta)=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is presented revealing a power relationship. General models describing the soft error rates across scaled product generations are presented. The analysis methodology may be applied to other scaled microelectronic products and their key parameters.

White, Mark

2010-01-01

316

Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor  

NASA Astrophysics Data System (ADS)

The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 ?m CMOS technology. The flux of neutron beams was about 1.33 × 108 n/cm2s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 1011, 5 × 1011, and 1 × 1012 n/cm2, respectively. The mean dark signal (KD), dark signal spike, dark signal non-uniformity (DSNU), noise (VN), saturation output signal voltage (VS), and dynamic range (DR) versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike.

Wang, Zujun; Huang, Shaoyan; Liu, Minbo; Xiao, Zhigang; He, Baoping; Yao, Zhibin; Sheng, Jiangkun

2014-07-01

317

Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.  

PubMed

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200?mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

Kazior, Thomas E

2014-03-28

318

The SDC cellA novel design methodology for high-speed arithmetic modules using CMOS\\/BiCMOS precharged circuits  

Microsoft Academic Search

The shielded dynamic complex-gate (SDC) cell is a cell-based design methodology for generating high-speed modules or macrocells using precharged circuit technology. In order to achieve ultrafast operation, a BiCMOS precharged circuit has been developed. This circuit is about 1.5 to 2.0 times faster than the conventional CMOS precharged circuit. The effect of alpha-particle injection under low-voltage operation has been studied,

T. Hayashi; T. Doi; M. Asai; K. Ishibashi; S. Shukuri; A. Watanabe; M. Suzuki

1990-01-01

319

Improving manufacturing variability control in advanced CMOS technology by using TCAD methodology  

NASA Astrophysics Data System (ADS)

Rapid development of a well controlled manufacturing process is a key component of marketplace success. Accomplishing this requires a thorough understanding of the effects of process variations on parametric yield. Use of Technology Computer Assisted Design (TCAD) simulations and statistical analysis can decrease the time needed to assess the manufacturability of various transistor design options, and identify the key process parameters that cause the largest variations. This paper covers a new methodology that combines Design of Experiments (DOE) with process and device simulations to generate transistor parametric statistical models. Monte-Carlo simulations are performed to generate transistor parametric sensitivities and statistical distributions. Examples of applying this methodology to 130nm technology will be given.

Chen, Jihong; Wu, Jeff; Liu, Kaiping; Yang, Hong; Scott, David

2004-04-01

320

Double junction photodiode for X-ray CMOS sensor IC  

NASA Astrophysics Data System (ADS)

A CMOS compatible P+/Nwell/Psub double junction photodiode pixel was proposed, which can efficiently detect fluorescence from CsI(Tl) scintillation in an X-ray sensor. Photoelectric and spectral responses of P+/Nwell, Nwell/Psub and P+/Nwell/Psub photodiodes were analyzed and modeled. Simulation results show P+/Nwell/Psub photodiode has larger photocurrent than P+/Nwell photodiode and Nwell/Psub photodiode, and its spectral response is more in accordance with CsI(Tl) fluorescence spectrum. Improved P+/Nwell/Psub photodiode detecting CsI(Tl) fluorescence was designed in CSMC 0.5 ?m CMOS process, CTIA (capacitive transimpedance amplifier) architecture was used to readout photocurrent signal. CMOS X-ray sensor IC prototype contains 8 × 8 pixel array and pixel pitch is 100 × 100 ?m2. Testing results show the dark current of the improved P+/Nwell/Psub photodiode (6.5 pA) is less than that of P+/Nwell and P+/Nwell/Psub photodiodes (13 pA and 11 pA respectively). The sensitivity of P+/Nwell/Psub photodiode is about 20 pA/lux under white LED. The spectrum response of P+/Nwell/Psub photodiode ranges from 400 nm to 800 nm with a peak at 532 nm, which is in accordance with the fluorescence spectrum of CsI(Tl) in an indirect X-ray sensor. Preliminary testing results show the sensitivity of X-ray sensor IC under Cu target X-ray is about 0.21 V·m2/W or 5097e-/pixel @ 8.05 keV considering the pixel size, integration time and average energy of X-ray photons.

Chaoqun, Xu; Ying, Sun; Yan, Han; Dazhong, Zhu

2014-07-01

321

NV-CMOS HD camera for day/night imaging  

NASA Astrophysics Data System (ADS)

SRI International (SRI) has developed a new multi-purpose day/night video camera with low-light imaging performance comparable to an image intensifier, while offering the size, weight, ruggedness, and cost advantages enabled by the use of SRI's NV-CMOS HD digital image sensor chip. The digital video output is ideal for image enhancement, sharing with others through networking, video capture for data analysis, or fusion with thermal cameras. The camera provides Camera Link output with HD/WUXGA resolution of 1920 x 1200 pixels operating at 60 Hz. Windowing to smaller sizes enables operation at higher frame rates. High sensitivity is achieved through use of backside illumination, providing high Quantum Efficiency (QE) across the visible and near infrared (NIR) bands (peak QE <90%), as well as projected low noise (<2h+) readout. Power consumption is minimized in the camera, which operates from a single 5V supply. The NVCMOS HD camera provides a substantial reduction in size, weight, and power (SWaP) , ideal for SWaP-constrained day/night imaging platforms such as UAVs, ground vehicles, fixed mount surveillance, and may be reconfigured for mobile soldier operations such as night vision goggles and weapon sights. In addition the camera with the NV-CMOS HD imager is suitable for high performance digital cinematography/broadcast systems, biofluorescence/microscopy imaging, day/night security and surveillance, and other high-end applications which require HD video imaging with high sensitivity and wide dynamic range. The camera comes with an array of lens mounts including C-mount and F-mount. The latest test data from the NV-CMOS HD camera will be presented.

Vogelsong, T.; Tower, J.; Sudol, Thomas; Senko, T.; Chodelka, D.

2014-06-01

322

SOI CMOS Imager with Suppression of Cross-Talk  

NASA Technical Reports Server (NTRS)

A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

2009-01-01

323

Defect classes - an overdue paradigm for CMOS IC testing  

SciTech Connect

The IC test industry has struggled for more than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the test strategy match the defect electrical properties, while fault models require that IC defects match the fault definition. We use data from Sandia Labs failure analysis and test facilities and from public literature. We describe test pattern requirements for each defect class and propose a test paradigm.

Hawkins, C.F. [Univ. of New Mexico, Albuquerque, NM (United States); Soden, J.M.; Righter, A.W. [Sandia National Labs., Albuquerque, NM (United States); Ferguson, F.J. [Univ. of California, Santa Cruz, CA (United States)

1994-09-01

324

120-MHz BiCMOS superscalar RISC processor  

NASA Astrophysics Data System (ADS)

A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm x 16.5 mm, and utilizes 3.3 V/0.5 micron BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design.

Tanaka, Shigeya; Hotta, Takashi; Murabayashi, Fumio; Yamada, Hiromichi; Yoshida, Shoji; Shimamura, Kotaro; Katsura, Koyo; Bandoh, Tadaaki; Ikeda, Koichi; Matsubara, Kenji

1994-04-01

325

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg  

NASA Technical Reports Server (NTRS)

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

2014-01-01

326

Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS)  

PubMed Central

The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 ?m pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50–1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems. PMID:24353389

Loughran, Brendan; Swetadri Vasan, S. N.; Singh, Vivek; Ionita, Ciprian N.; Jain, Amit; Bednarek, Daniel R.; Titus, Albert; Rudin, Stephen

2013-01-01

327

Design considerations for a new high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS)  

NASA Astrophysics Data System (ADS)

The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 ?m pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

Loughran, Brendan; Swetadri Vasan, S. N.; Singh, Vivek; Ionita, Ciprian N.; Jain, Amit; Bednarek, Daniel R.; Titus, Albert H.; Rudin, Stephen

2013-03-01

328

Lighting in Commercial Buildings  

EIA Publications

Lighting is a major consumer of electricity in commercial buildings and a target for energy savings through use of energy-efficient light sources along with other advanced lighting technologies. The Commercial Buildings Energy Consumption Survey (CBECS) collects information on types of lighting equipment, the amount of floorspace that is lit, and the percentage of floorspace lit by each type. In addition, CBECS data are used to model end-use consumption, including energy consumed for lighting in commercial buildings.

2009-01-01

329

Lunar Commercialization Workshop  

NASA Technical Reports Server (NTRS)

This slide presentation describes the goals and rules of the workshop on Lunar Commercialization. The goal of the workshop is to explore the viability of using public-private partnerships to open the new space frontier. The bulk of the workshop was a team competition to create a innovative business plan for the commercialization of the moon. The public private partnership concept is reviewed, and the open architecture as an infrastructure for potential external cooperation. Some possible lunar commercialization elements are reviewed.

Martin, Gary L.

2008-01-01

330

COMMERCIAL SPACE ACCOMPLISHMENTS Commercial Cargo Space Accomplishments  

E-print Network

to the International Space Station (ISS), bringing this important work back to the United States where it belongs requirements for transporting NASA's crew to the International Space Station. Unfunded Space Act Agreements by the extension of International Space Station operations to 2020, enabling expanded commercial and research

Waliser, Duane E.

331

A low voltage CMOS low drop-out voltage regulator  

NASA Astrophysics Data System (ADS)

A low voltage implementation of a CMOS Low Drop-Out voltage regulator (LDO) is presented. The requirement of low voltage devices is crucial for portable devices that require extensive computations in a low power environment. The LDO is implemented in 90nm generic CMOS technology. It generates a fixed 0.8V from a 2.5V supply which on discharging goes to 1V. The buffer stage used is unity gain configured unbuffered OpAmp with rail-to-rail swing input stage. The simulation result shows that the implemented circuit provides load regulation of 0.004%/mA and line regulation of -11.09mV/V. The LDO provides full load transient response with a settling time of 5.2?s. Further, the dropout voltage is 200mV and the quiescent current through the pass transistor (Iload=0) is 20?A. The total power consumption of this LDO (excluding bandgap reference) is only 80?W.

Bakr, Salma Ali; Abbasi, Tanvir Ahmad; Abbasi, Mohammas Suhaib; Aldessouky, Mohamed Samir; Abbasi, Mohammad Usaid

2009-05-01

332

Single phase dynamic CMOS PLA using charge sharing technique  

NASA Technical Reports Server (NTRS)

A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

Dhong, Y. B.; Tsang, C. P.

1991-01-01

333

High-Q CMOS-integrated photonic crystal microcavity devices  

PubMed Central

Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10?s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300–9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31?A/W), 3?GHz bandwidth, and 30?nA dark current at a reverse bias of 30?V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems. PMID:24518161

Mehta, Karan K.; Orcutt, Jason S.; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J.

2014-01-01

334

CMOS-TDI detector technology for reconnaissance application  

NASA Astrophysics Data System (ADS)

The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

2014-10-01

335

High-Q CMOS-integrated photonic crystal microcavity devices.  

PubMed

Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300-9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems. PMID:24518161

Mehta, Karan K; Orcutt, Jason S; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J

2014-01-01

336

A CMOS variable gain LNA for UWB receivers  

NASA Astrophysics Data System (ADS)

A CMOS variable gain low noise amplifier (LNA) is presented for 4.2-4.8 GHz ultra-wideband application in accordance with Chinese standard. The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated. A three-bit digital programmable gain control circuit is exploited to achieve variable gain. The design was implemented in 0.13-?m RF CMOS process, and the die occupies an area of 0.9 mm2 with ESD pads. Totally the circuit draws 18 mA DC current from 1.2 V DC supply, the LNA exhibits minimum noise figure of 2.3 dB, S(1,1) less than -9 dB and S(2,2) less than -10 dB. The maximum and the minimum power gains are 28.5 dB and 16 dB respectively. The tuning step of the gain is about 4 dB with four steps in all. Also the input 1 dB compression point is -10 dBm and input third order intercept point (IIP3) is -2 dBm.

Feihua, Chen; Lingyun, Li; Xinzhong, Duo; Tong, Tian; Xiaowei, Sun

2011-02-01

337

A CMOS integrated circuit for pulse-shaped discrimination  

NASA Astrophysics Data System (ADS)

A CMOS integrated circuit (IC) for pulse-shape discrimination (PSD) has been developed. The IC performs discrimination of gamma-rays and neutrons as part of a system monitoring stored nuclear materials. The method implemented extracts the pulse tail decay time constant using a leading edge trigger for identifying the start of the pulse and a constant fraction discriminator (CFD) to determine the zero crossing of the shaped signal. The circuit is designed to interface with two photomultiplier tubes -- one for pulse processing and one for coincidence detection. Two Outputs from the IC, a start and stop, can be used with a high speed timing system for pulse characterization with minimal external control. The circuit was fabricated in Orbit 1.2 micrometer CMOS and operates from a 5-V supply. Specifics of the design including overall topology, charge sensitive preamplifier and CFD characteristics, shaping method and time constant selections, system timing, and implementation are discussed. Circuit performance is presented including dynamic range, timing walk, system dead time, and power consumption.

Frank, S. S.; Ericson, M. N.; Simpson, M. L.; Todd, R. A.; Hutchinson, D. P.

338

Review of radiation damage studies on DNW CMOS MAPS  

NASA Astrophysics Data System (ADS)

Monolithic active pixel sensors fabricated in a bulk CMOS technology with no epitaxial layer and standard resistivity (10 ? cm) substrate, featuring a deep N-well as the collecting electrode (DNW MAPS), have been exposed to ?-rays, up to a final dose of 10 Mrad (SiO2), and to neutrons from a nuclear reactor, up to a total 1 MeV neutron equivalent fluence of about 3.7·1013 cm-2. The irradiation campaign was aimed at studying the effects of radiation on the most significant parameters of the front-end electronics and on the charge collection properties of the sensors. Device characterization has been carried out before and after irradiations. The DNW MAPS irradiated with 60Co ?-rays were also subjected to high temperature annealing (100 °C for 168 h). Measurements have been performed through a number of different techniques, including electrical characterization of the front-end electronics and of DNW diodes, laser stimulation of the sensors and tests with 55Fe and 90Sr radioactive sources. This paper reviews the measurement results, their relation with the damage mechanisms underlying performance degradation and provides a new comparison between DNW devices and MAPS fabricated in a CMOS process with high resistivity (1 k? cm) epitaxial layer.

Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.; Zucca, S.; Bettarini, S.; Rizzo, G.; Morsani, F.; Bosisio, L.; Rashevskaya, I.; Cindro, V.

2013-12-01

339

An integrated CMOS high data rate transceiver for video applications  

NASA Astrophysics Data System (ADS)

This paper presents a 5 GHz CMOS radio frequency (RF) transceiver built with 0.18 ?m RF-CMOS technology by using a proprietary protocol, which combines the new IEEE 802.11n features such as multiple-in multiple-out (MIMO) technology with other wireless technologies to provide high data rate robust real-time high definition television (HDTV) distribution within a home environment. The RF frequencies cover from 4.9 to 5.9 GHz: the industrial, scientific and medical (ISM) band. Each RF channel bandwidth is 20 MHz. The transceiver utilizes a direct up transmitter and low-IF receiver architecture. A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration. The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude (EVM) at -3 dBm output power.

Yaping, Liang; Dazhi, Che; Cheng, Liang; Lingling, Sun

2012-07-01

340

CMOS low data rate imaging method based on compressed sensing  

NASA Astrophysics Data System (ADS)

Complementary metal-oxide semiconductor (CMOS) technology enables the integration of image sensing and image compression processing, making improvements on overall system performance possible. We present a CMOS low data rate imaging approach by implementing compressed sensing (CS). On the basis of the CS framework, the image sensor projects the image onto a separable two-dimensional (2D) basis set and measures the corresponding coefficients obtained. First, the electrical current output from the pixels in a column are combined, with weights specified by voltage, in accordance with Kirchhoff's law. The second computation is performed in an analog vector-matrix multiplier (VMM). Each element of the VMM considers the total value of each column as the input and multiplies it by a unique coefficient. Both weights and coefficients are reprogrammable through analog floating-gate (FG) transistors. The image can be recovered from a percentage of these measurements using an optimization algorithm. The percentage, which can be altered flexibly by programming on the hardware circuit, determines the image compression ratio. These novel designs facilitate image compression during the image-capture phase before storage, and have the potential to reduce power consumption. Experimental results demonstrate that the proposed method achieves a large image compression ratio and ensures imaging quality.

Xiao, Long-long; Liu, Kun; Han, Da-peng

2012-07-01

341

CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics  

PubMed Central

Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art. PMID:25365460

Guo, Nan; Cheung, Ka Wai; Wong, Hiu Tung; Ho, Derek

2014-01-01

342

Algorithmic Design of CMOS LNAs and PAs for 60GHz Radio  

Microsoft Academic Search

Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor fT\\/fMAX of 120 GHz\\/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB

Terry Yao; Michael Q. Gordon; Keith K. W. Tang; Kenneth H. K. Yau; Ming-Ta Yang; Peter Schvan; Sorin P. Voinigescu

2007-01-01

343

Algae Biodiesel: Commercialization  

E-print Network

Algae Biodiesel: A Path to Commercialization Algae Biodiesel: A Path to Commercialization Center conservation and biomonitoring · Algae biodiesel is largest CEHMM project #12;Project Overview: The Missing replace petroleum #12;Project Overview: Local Resources for Algae Biodiesel Project Overview: Local

Tullos, Desiree

344

Commercial Real Estate Returns  

Microsoft Academic Search

In the commercial real estate market, which is perceived to be relatively inefficient, investors have comparative advantages; hence there are significant costs to diversification. This paper presents for the first time a series of market (or quasi-market) returns for a large data base. This data base is believed to be the most complete commercial real estate data base yet constructed.

Mike Miles; Tom McCue

1984-01-01

345

Commercialism@Schools.  

ERIC Educational Resources Information Center

The Center for the Analysis of Commercialism in Schools found that the number of press citations from 1990 to 2000 discussing seven types of commercializing activities (program sponsorship, exclusive agreements, incentive programs, appropriation of space, sponsored educational materials, electronic marketing, privatization, and fund raising)…

Molnar, Alex; Morales, Jennifer

2000-01-01

346

High-performance VGA-resolution digital color CMOS imager  

NASA Astrophysics Data System (ADS)

This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be suitable for a variety of color imaging applications including still/full motion imaging, security/surveillance, and teleconferencing/multimedia among other high performance, cost sensitive, low power consumer applications.

Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

1999-04-01

347

Commercial Biomedical Experiments Payload  

NASA Technical Reports Server (NTRS)

Experiments to seek solutions for a range of biomedical issues are at the heart of several investigations that will be hosted by the Commercial Instrumentation Technology Associates (ITA), Inc. The biomedical experiments CIBX-2 payload is unique, encompassing more than 20 separate experiments including cancer research, commercial experiments, and student hands-on experiments from 10 schools as part of ITA's ongoing University Among the stars program. Here, Astronaut Story Musgrave activates the CMIX-5 (Commercial MDA ITA experiment) payload in the Space Shuttle mid deck during the STS-80 mission in 1996 which is similar to CIBX-2. The experiments are sponsored by NASA's Space Product Development Program (SPD).

2003-01-01

348

Monolithic electronic-photonic integration in state-of-the-art CMOS processes  

E-print Network

As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. ...

Orcutt, Jason S. (Jason Scott)

2012-01-01

349

Prediction and measurement of radiation damage to CMOS devices on board spacecraft  

NASA Technical Reports Server (NTRS)

The CMOS Radiation Effects Measurement (CREM) experiment is presently being flown on the Explorer-55. The purpose of the experiment is to evaluate device performance in the actual space radiation environment and to correlate the respective measurements to on-the-ground laboratory irradiation results. The experiment contains an assembly of C-MOS and P-MOS devices shielded in front by flat slabs of aluminum and by a practically infinite shield in the back. Predictions of radiation damage to C-MOS devices are based on standard environment models and computational techniques. A comparison of the shifts in CMOS threshold potentials, that is, those measured in space to those obtained from the on-the-ground simulation experiment with Co-60, indicates that the measured space damage is smaller than predicted by about a factor of 2-3 for thin shields, but agrees well with predictions for thicker shields.

Cliff, R. A.; Danchenko, V.; Stassinopoulos, E. G.; Sing, M.; Brucker, G. J.; Ohanian, R. S.

1976-01-01

350

Long term ionization response of several BiCMOS VLSIC technologies  

SciTech Connect

BiCMOS is emerging as a strong competitor to CMOS for gate arrays and memories because of its performance advantages for the same feature size. In this paper, the authors examine the long term ionization response of five BiCMOS technologies by characterizing test structures which emphasize the various failure modes of CMOS and bipolar. The primary failure modes are found to be associated with the recessed field oxide isolation; edge leakage in the n channel MOSFETs and buried layer to buried layer leakage in the bipolar. The ionization failure thresholds for worst case bias were in the range of 5-20 Krad(Si) for both failure modes in all five technologies.

Pease, R.L. (Mission Research Corp., Albuquerque, NM (US)); Combs, W.; Clark, S. (Naval Weapons Support Center, Crane, IN (US))

1992-06-01

351

Nano-scale metal contacts for future III-V CMOS  

E-print Network

As modem transistors continue to scale down in size, conventional Si CMOS is reaching its physical limits and alternative technologies are needed to extend Moore's law. Among different candidates, MOSFETs with a III-V ...

Guo, Alex

2012-01-01

352

''Normal'' tissues from humans exposed to radium contain an alteration in the c-mos locus  

SciTech Connect

The structures of a number of human proto-oncogenes from persons with internal systemic exposure to radium were analyzed by restriction enzyme digestion and southern blotting of their DNA. Two extra c-mos Eco R1 restriction-fragment-length bands of 5.0 kb and 5.5 kb were found in tissue DNA from six of seven individuals. The extra c-mos bands were detected in DNA from many, but not all, of the tissues of the individuals exposed to radium. Our results suggest that the c-mos restriction-fragment-length alterations (RFLA) found in individuals exposed to radium were induced rather than inherited, are epigenetic in origin, and most likely result from changes in the methylation of bases surrounding the single exon of the c-mos proto-oncogene. 7 refs., 3 figs., 2 tabs.

Huberman, E.; Schlenker, R.A.; Hardwick, J.P.

1989-01-01

353

Discovery of heavy-ion induced latchup in CMOS/epi devices  

NASA Technical Reports Server (NTRS)

The observance of latchup in CMOS/epi devices upon exposure to krypton ions is reported. The effect of epi layer thickness on latchup susceptibility is discussed. An approach to eliminating this effect is indicated.

Nichols, D. K.; Price, W. E.; Shoga, M. A.; Duffey, J.; Kolasinsky, W. A.

1986-01-01

354

Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design  

NASA Astrophysics Data System (ADS)

Hybrid Nano (e.g. Nanotube and Nanowire) /CMOS circuits combine both the advantages of Nano-devices and CMOS technologies; they have thus become the most promising candidates to relax the intrinsic drawbacks of CMOS circuits beyond Moore’s law. A functional simulation model for an hybrid Nano/CMOS design is presented in this paper. It is based on Optically Gated Carbon NanoTube Field Effect Transistors (OG-CNTFET), which can be used as 2-terminal programmable resistors. Their resistance can be adjusted precisely, reproducibly and in a non-volatile way, over three orders of magnitude. These interesting behaviors of OG-CNTFET promise great potential for developing the non-volatile memory and neuromorphic adaptive computing circuits. The model is developed in Verilog-A language and implemented on Cadence Virtuoso platform with Spectre 5.1.41 simulator. Many experimental parameters are included in this model to improve the simulation accuracy.

Zhao, Weisheng; Agnus, Guillaume; Derycke, Vincent; Filoramo, Ariana; Gamrat, Christian; Bourgoin, Jean-Philippe

355

Leakage Current Reduction in CMOS VLSI Circuits by Input Vector Afshin Abdollahi  

E-print Network

and cooling technology. Historically, the primary contributor to power dissipation in CMOS circuits has been has been accompanied by an increase in power dissipation; thus, requiring more expensive packaging

Pedram, Massoud

356

SI-based unreleased hybrid MEMS-CMOS resonators in 32nm technology  

E-print Network

This work presents the first unreleased Silicon resonators fabricated at the transistor level of a standard CMOS process, and realized without any release steps or packaging. These unreleased bulk acoustic resonators are ...

Marathe, Radhika A.

357

Current mode integrators and their applications in low-voltage high frequency CMOS signal processing  

E-print Network

Low voltage CMOS fully differential integrators for high frequency continuous-time filters using current-mode techniques are presented.. Current mode techniques are employed to avoid the use of the floating differential pair, in order to achieve...

Smith, Sterling Lane

1993-01-01

358

45 nm/32 nm CMOS - Challenge and perspective  

NASA Astrophysics Data System (ADS)

Production of 45 nm node CMOS has already started. However, difficulty of new technology development is increasing and some company dropped off from the competition. The big challenge for 45 nm node is the introduction of ArF immersion lithography. Most of the other technologies used for 45 nm node are the extension of those used for 65 nm node. On the other hand, there will be a big jump for 32 nm node technology. The biggest item is metal gate and high- k gate insulator system. Self barrier layer formation for BEOL is also the promising item. Variability is the biggest concern for 32 nm node SRAM. To overcome these difficulties, collaboration between device and circuit engineer is important.

Ishimaru, Kazunari

2008-09-01

359

A new visible watermarking technique applied to CMOS image sensor  

NASA Astrophysics Data System (ADS)

This paper presents a new visible watermarking solution for CMOS image sensor which can enhance secure features of captured images. Visible watermarks are embedded in the Bayer format image data and can be transferred by the subsequent interpolation process. A piecewise function is setup based on the gray scale resolution characteristics of human eyes. Watermark stretch factor can be adaptively chosen according to the gray value of the current pixel. The advantage of this algorithm is that the watermark has the same visibility in different image brightness region. A number of color images have been used to test the method. In order to check the robustness of watermarked images, we conducted adding noise and filtering experiments, results show that the visibility of watermark is also good after the experiments. The approach allows a digital watermark to be embedded in an image immediately upon its capture, before leaving the imaging chip.

Yu, Pingping; Shang, Yan; Li, Chunming

2013-10-01

360

A 20 MHz CMOS reorder buffer for a superscalar microprocessor  

NASA Technical Reports Server (NTRS)

Superscalar processors can achieve increased performance by issuing instructions out-of-order from the original sequential instruction stream. Implementing an out-of-order instruction issue policy requires a hardware mechanism to prevent incorrectly executed instructions from updating register values. A reorder buffer can be used to allow a superscalar processor to issue instructions out-of-order and maintain program correctness. This paper describes the design and implementation of a 20MHz CMOS reorder buffer for superscalar processors. The reorder buffer is designed to accept and retire two instructions per cycle. A full-custom layout in 1.2 micron has been implemented, measuring 1.1058 mm by 1.3542 mm.

Lenell, John; Wallace, Steve; Bagherzadeh, Nader

1992-01-01

361

Failure analysis of a half-micron CMOS IC technology  

SciTech Connect

We present the results of recent failure analysis of an advanced, 0.5 {mu}m, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.

Liang, A.Y.; Tangyunyong, P.; Bennett, R.S.; Flores, R.S. [and others

1996-08-01

362

CMOS detector cells for holographic optical interconnects in microcircuits  

NASA Technical Reports Server (NTRS)

This paper reports on the characterization of CMOS detectors for holographic optical interconnects in micro circuits. A VLSI temporal response system has been built, which has high-magnification viewing capabilities to facilitate the identification of the sample area under investigation. An isolated photodiode and load circuit has been characterized to determine responsivity, response time, and light spot positioning effects. The threshold of optical gate cells incorporating the above detectors and a transistor inverter stage to couple to other circuitry has been determined. The rise time and fall time of the optical gate cells have also been determined experimentally. The results were compared with the results of SPICE simulation, and show satisfactory agreement. The time delay of optical gate cell output was thus determined to be 70 ns at 10 microW light input. Threshold power was 0.5 microW light input.

Wu, W. H.; Johnston, A. R.

1987-01-01

363

An Approach for Self-Timed Synchronous CMOS Circuit Design  

NASA Technical Reports Server (NTRS)

In this letter we present a timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modi@ the circuit clock period. This letter is concluded with an example of the proposed approach applied to a static CMOS ripple-carry adder.

Walker, Alvernon; Lala, Parag K.

2001-01-01

364

Improving TCSPC data acquisition from CMOS SPAD arrays  

NASA Astrophysics Data System (ADS)

We present a digital architecture for fast acquisition of time correlated single photon counting (TCSPC) timestamps from 32×32 CMOS SPAD array. Custom firmware was written to select 64 pixels out of 1024 available for fast transfer of TCSPC timestamps. Our 64 channel TCSPC is capable of acquiring up to 10 million TCSPC timestamps per second over a USB2 link. We describe the TCSPC camera (Megaframe), camera interface to the PC and the microscope setup. We characterize the Megaframe camera for fluorescence lifetime imaging (FLIM) including instrument response function, time resolution and variability of both across the array. We show a fluorescence lifetime image of a plant specimen (Convallaria majalis) from a custom-built multifocal multiphoton microscope. The image was acquired in 20 seconds (with average timestamp acquisition rate of 4.7 million counts per second).

Krstaji?, Nikola; Poland, Simon; Tyndall, David; Walker, Richard; Coelho, Simao; Li, David D.; Richardson, Justin; Ameer-Beg, Simon; Henderson, Robert

2013-06-01

365

Thirty megarad CMOS gate array for spacecraft applications  

SciTech Connect

The recent development, testing, qualification and integration for spacecraft applications of a general purpose, 30 Megarad-hard, CMOS logic gate array having 3000 transistors is reported. Fabricated on the National Semiconductor, Inc. class S radation-hard line, the gate array operates at >3 MHz (10V) after 10/sup 7/ rad(Si) total dose from a Co/sup 60/ source. The threshold voltage change is 0.2 volts (0.5 volts) for the n-channel (p-channel) devices under 10V bias conditions. The rad-hard process of the CDI gate array family is mask compatible with the conventional process for cost effective semicustom design. The rad-hard array is presently operating in-orbit on the AMPTE satellite and is planned for instruments to be flown on the CRRES and UARS satellites.

Voss, H.D.; Hardage, C.; Jones, F.C.; Roffelsen, L.

1984-12-01

366

Accelerated life testing effects on CMOS microcircuit characteristics  

NASA Technical Reports Server (NTRS)

The 250 C, 200C and 125C accelerated tests are described. The wear-out distributions from the 250 and 200 C tests were used to estimate the activation energy between the two test temperatures. The duration of the 125 C test was not sufficient to bring the test devices into the wear-out region. It was estimated that, for the most complex of the three devices types, the activation energy between 200 C and 125 C should be at least as high as that between 250 C and 200 C. The practicality of the use of high temperature for the accelerated life tests from the point of view of durability of equipment is assessed. Guidlines for the development of accelerated life-test conditions are proposed. The use of the silicon nitride overcoat to improve the high temperature accelerated life-test characteristics of CMOS microcircuits is described.

1980-01-01

367

Development of a radiation-hard CMOS process  

NASA Technical Reports Server (NTRS)

It is recommended that various techniques be investigated which appear to have the potential for improving the radiation hardness of CMOS devices for prolonged space flight mission. The three key recommended processing techniques are: (1) making the gate oxide thin. It has been shown that radiation degradation is proportional to the cube of oxide thickness so that a relatively small reduction in thickness can greatly improve radiation resistance; (2) cleanliness and contamination control; and (3) to investigate different oxide growth (low temperature dry, TCE and HCL). All three produce high quality clean oxides, which are more radiation tolerant. Technique 2 addresses the reduction of metallic contamination. Technique 3 will produce a higher quality oxide by using slow growth rate conditions, and will minimize the effects of any residual sodium contamination through the introduction of hydrogen and chlorine into the oxide during growth.

Power, W. L.

1983-01-01

368

Triple inverter pierce oscillator circuit suitable for CMOS  

DOEpatents

An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

Wessendorf; Kurt O. (Albuquerque, NM)

2007-02-27

369

An ultra-wideband CMOS low noise amplifier for 3-5GHz UWB system  

Microsoft Academic Search

Abstract—An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18- m CMOS technology for a

Chang-Wan Kim; Min-Suk Kang; Phan Tuan Anh; Hoon-Tae Kim; Sang-Gug Lee

2005-01-01

370

A low-noise CMOS instrumentation amplifier for thermoelectric infrared detectors  

Microsoft Academic Search

A low-noise CMOS instrumentation amplifier for low-frequency thermoelectric infrared sensor applications is described which uses a chopper technique to reduce low-frequency noise and offset. The offset reduction efficiency of the band-pass filter, implemented to reduce residual offset due to clock feedthrough, has been analyzed and experimentally verified. The circuit has been integrated in a transistor-only 1-?m single-poly n-well CMOS process.

Christian Menolfi; Qiuting Huang

1997-01-01

371

Hybrid CMOS-MQCA Logic Architectures using Multi-Layer Spintronic Devices  

E-print Network

We present a novel hybrid CMOS-MQCA architecture using multi-layer Spintronic devices as computing elements. A feasibility study is presented with 22nm CMOS where new approaches for spin transfer torque induced clocking and read-out scheme for variability-tolerance are introduced. A first-of-its-kind Spintronic device model enables circuit simulation using existing CAD infrastructure. Approximately 70% reduction in energy consumption is observed when compared against conventional field-induced clocking scheme.

Das, Jayita; Rajaram, Srinath; Bhanja, Sanjukta

2011-01-01

372

Low-power CMOS at Vdd=4kT\\/q  

Microsoft Academic Search

Summary form only given. This paper reports a CMOS inverter active power-delay product of less than 0.1 fJ\\/stage at 25°C and at Vdd=0.1 V. We believe this is the lowest reported. This is accomplished by using a novel technique to match NFET and PFET subthreshold currents and, thus, enable operation of a standard 1.5 V 180 nm CMOS technology in

A. Bryant; J. Brown; P. Cottrell; M. Ketchen; J. Ellis-Monaghan; E. J. Nowak

2001-01-01

373

60 nm gate length dual-Vt CMOS for high performance applications  

Microsoft Academic Search

In this work, we present a 60 nm gate length CMOS for high performance applications at the 0.13 ?m CMOS node. The technology utilizes 193 nm gate lithography, dual spacers with thin spacer before drain extension implant and L-shaped nitride spacer after drain extensions, and remote-plasma nitrided dielectric with 1.75 nm EOT. 10-15% improvement in drive current is achieved with

M. Mehrotra; J. Wu; A. Jain; T. Laaksonen; K. Kim; W. Bather; R. Koshy; J. Chen; J. Jacobs; V. Ukraintsev; L. Olsen; J. DeLoach; J. Mehigan; R. Agarwal; S. Walsh; D. Sekel; L. Tsung; M. Vaidyanathan; B. Trentman; K. Liu; S. Aur; R. Khamankar; P. Nicollian; Q. Jiang; Y. Xu; B. Campbell; P. Tiner; R. Wise; D. Scott; M. Rodder

2002-01-01

374

0.5 micron CMOS for high performance at 3.3 V  

Microsoft Academic Search

In addition to higher packing density, the scaling of CMOS technology to the half-micron regime must provide improved circuit performance at a reduced supply voltage without increased process complexity. These goals have been met with a 0.5- mu m CMOS technology with 12-nm gate oxide thickness that gives at least a 20% speed improvement at a 3.3-V supply voltage compared

R. A. Chapman; C. C. Wei; D. A. Bell; S. Aur; G. A. Brown; R. A. Haken

1988-01-01

375

High performance and low power transistors integrated in 65nm bulk CMOS technology  

Microsoft Academic Search

This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated an astonishing 35 %

Z. Luo; A. Steegen; M. Eller; R. Mann; C. Baiocco; P. Nguyen; L. Kim; M. Hoinkis; V. Ku; V. Klee; F. Jamin; P. Wrschka; P. Shafer; W. Lin; S. Fang; A. Ajmera; W. Tan; R. Mo; J. Lian; D. Vietzke; C. Coppock; A. Vayshenker; T. Hook; V. Chan; K. Kim; A. Cowley; S. Kim; E. Kaltalioglu; B. Zhang; S. Marokkey; Y. Lin; K. Lee; H. Zhu; M. Weybright; R. Rengarajan; J. Ku; T. Schiml; J. Sudijono; I. Yang; C. Wann

2004-01-01

376

Transient Response and Fixed Pattern Noise in Logarithmic CMOS Image Sensors  

Microsoft Academic Search

Logarithmic CMOS image sensors are appealing for their high-contrast and high-speed response but they require postprocessing to achieve high-quality images. Previously published work has explained the fixed pattern noise (FPN) in these image sensors using a steady-state analysis. This paper explains how the transient response of the readout circuit may also contribute to FPN. Thus, the performance of these CMOS

Dileepan Joseph; Steve Collins

2007-01-01

377

Nano\\/CMOS architectures using a field-programmable nanowire interconnect  

Microsoft Academic Search

A field-programmable nanowire interconnect (FPNI) enables a family of hybrid nano\\/CMOS circuit architectures that generalizes the CMOL (CMOS\\/molecular hybrid) approach proposed by Strukov and Likharev, allowing for simpler fabrication, more conservative process parameters, and greater flexibility in the choice of nanoscale devices. The FPNI improves on a field-programmable gate array (FPGA) architecture by lifting the configuration bit and associated components

Gregory S Snider; R Stanley Williams

2007-01-01

378

Possibilities of deep-submicrometer CMOS for very-high-speed computer logic  

Microsoft Academic Search

It is shown that room-temperature CMOS, which has rarely been considered suitable for very-high-speed computer logic, can have sufficient performance to be the post-ECL (emitter-coupled logic) high-speed device when deep-submicrometer technology is available. The possibilities of CMOS are evaluated in the context of the very many factors related to computer logic. In a case study, it is shown that system

AKIRA MASAKI

1993-01-01

379

Current mode BiCMOS folded source-coupled logic circuits  

Microsoft Academic Search

A new BiCMOS Folded Source-Coupled Logic (Bi-FSCL) circuit is proposed. This is an improved version of CMOS Folded Source-Coupled Logic (C-FSCL). An Emitter Follower (EF) is implemented at the output of C-FSCL to obtain the Bi-FSCL gate. It has been shown that by using this EF, the output of the BiFSCL is faster than C-FSCL and capable of driving higher

Jayabalan Kundan; S. M. R. Hasan

1997-01-01

380

Time-Domain CMOS Temperature Sensors With Dual Delay-Locked Loops for Microprocessor Thermal Monitoring  

Microsoft Academic Search

We report on CMOS temperature sensors that work by measuring temperature-dependent delays in CMOS inverters. Two new features distinguish this work from the prior delay-based temperature sensors. First, our sensor operates with simple, low-cost one-point calibration. Second, it uses delay-locked loops (DLLs) to convert inverter delays to digital temperature outputs: the use of DLLs enables low energy (0.24 $\\\\mu$ J\\/sample)

Dongwan Ha; Kyoungho Woo; Scott Meninger; Thucydides Xanthopoulos; Ethan Crain; Donhee Ham

2012-01-01

381

Challenges in Designing Low-Power CMOS Wireless Systems-on-a-Chip  

Microsoft Academic Search

This paper describes the challenges in designing low-power CMOS systems-on-a-chip for wireless communications. RF transceiver building blocks for signal amplification, frequency translation, and frequency selectivity are examined with special emphasis on low noise amplifier, power amplifier, mixer, and frequency synthesizer. System-on-a-chip integration issues to relevant to a low-power CMOS design are also discussed

David Su

2006-01-01

382

Lens-integrated THz imaging arrays in 65nm CMOS technologies  

Microsoft Academic Search

THz CMOS imagers integrated with hyperhemi­ spherical Si-Ienses are presented and characterized. FPAs are implemented in 65nm CMOS bulk and SOl technologies. Lens­ integrated detectors at 0.65 THz show an increase of 15dB and 20dB in SNR compared to front-side illumination for SOl and bulk respectively. The responsivities Rv are increased and a min­ imum noise-equivalent power NEP of 17pWI.JilZ;

Hani Sherryl; Richard Al Hadi; Janusz Grzyb; Erik Ojefors; Andreia Cathelin; Andreas Kaiser; Ullrich R. Pfeiffer

2011-01-01

383

Low-noise silicon avalanche photodiodes fabricated in conventional CMOS technologies  

Microsoft Academic Search

We present a simple design technique that allows the fabrication of UV\\/blue-selective avalanche photodiodes in a conventional CMOS process. The photodiodes are fabricated in a twin tub 0.8 ?m CMOS technology. An efficient guard-ring structure is created using the lateral diffusion of two n-well regions separated by a gap of 0.6 ?m. When operated at a multiplication gain of 20,

Alexis Rochas; Alexandre R. Pauchard; P.-A. Besse; D. Pantic; Z. Prijic; R. S. Popovic

2002-01-01

384

Demonstration of a free-space optical interconnect in a CMOS chip  

NASA Astrophysics Data System (ADS)

We have developed a hybrid optoelectronic circuit to demonstrate a free-space optical interconnect in a CMOS chip. Discrete GaAs-based optical devices are hybridly integrated with a 0.8 micrometers CMOS chip fabricated by a MOSIS foundry. The CMOS chip consists of two separate digital modules, an ALU and a ROM, communicating via a pair of optical interconnects. Each interconnect consists of a CMOS laser driver that converts full CMOS logic-level data into a suitable laser drive current, a laser-photodetector pair, and a CMOS transimpedance amplifier that converts a photocurrent from the photodetector into logic-level data. An on-chip clock is used to time the serialization and deserialization of 4-bit words of data across each interconnect at a data rate of 40 Mb/s. In order to account for limitations of the hybrid design as well as process variations, pads are provided for off-chip clock signals to override the built-in clock and therefore operate the interconnect at a transmission rate different from the design value. Each laser-photodetector pair is fabricated from a single laser structure epitaxially grown on semi-insulating GaAs substrate. Similar to a laser-photomonitor arrangement, a dry etch is used to divide the laser structure into a separate laser and photodiode. This device is then hybridly integrated with the CMOS chip to implement the proof-of-principle free-space optical interconnect. Experimental results for the optical elements and simulation results for the CMOS design are presented to demonstrate the operation of the chip.

Mena, Pablo V.; Lammert, Robert M.; Kang, Steve M.; Coleman, James J.

1995-04-01

385

A single-chip CMOS optical microspectrometer with light-to-frequency converter and bus interface  

Microsoft Academic Search

A single-chip CMOS optical microspectrometer con- taining an array of 16 addressable Fabry-Perot etalons (each one with a different resonance cavity length), photodetectors, and cir- cuits for readout, multiplexing, and driving a serial bus interface has been fabricated in a standard 1.6- m CMOS technology (chip area 3.9 4.2 mm ). The result is a chip that can operate using

José Higino Correia; Ger de Graaf; Marian Bartek; Reinoud F. Wolffenbuttel

2002-01-01

386

Process technology for the modular integration of CMOS and polysilicon microstructures  

Microsoft Academic Search

Modular fabrication of polysilicon surface-micromachined structures after completion of a conventional CMOS electronic process is described. Key process steps include tungsten metallization with contact diffusion barriers, LPCVD oxide and nitride passivation of the CMOS, rapid thermal processing for stress-relief annealing of the structural polysilicon film, implementation of a sacrificial spin-on-glass planarization, and the final microstructure release in hydrofluoric acid. Modularity

James M. Bustillo; Gary K. Fedder; Clark T.-C. Nguyen; Roger T. Howe

1994-01-01

387

Degradation Characteristics of n- and p-Channel Polycrystalline-Silicon TFTs Under CMOS Inverter Operation  

Microsoft Academic Search

The degradation characteristics of n- and p-channel polysilicon thin-film transistors (TFTs) under circuit operation were investigated by using CMOS inverter circuits consisting of n-channel TFTs with a lightly doped drain (LDD) structure and p-channel TFTs with a single-drain (SD) structure. A new test element made it possible to separately evaluate the degradation characteristics of each type of TFT during CMOS

Yoshiaki Toyota; Mieko Matsumura; Mutsuko Hatano; Takeo Shiba; Makoto Ohkura

2010-01-01

388

A Sub W Embedded CMOS Temperature Sensor for RFID Food Monitoring Application  

Microsoft Academic Search

An ultra-low power embedded CMOS temperature sensor based on serially connected subthreshold MOS operation is implemented in a 0.18 ?m CMOS process for passive RFID food monitoring applications. Employing serially connected subthreshold MOS as sensing element enables reduced minimum supply voltage for further power reduction, which is of utmost importance in passive RFID applications. Both proportional-to-absolute-temperature (PTAT) and complimentary-to-absolute-temperature (CTAT)

Man Kay Law; Amine Bermak; Howard C. Luong

2010-01-01

389

An ultra-low power operating technique for mega-pixels current-mediated CMOS imagers  

Microsoft Academic Search

A novel ultra-low power operating technique is presented for mega-pixels current-mediated CMOS imagers. In the proposed technique, the reset and read-out phases occur simultaneously: as a single pixel is being read-out another pixel is being reset. Such a strategy reduces power consumption by more than 2 orders of magnitude for current- mediated mega-pixels CMOS imagers, while still allowing for on-read-out

Farid Boussaid; Amine Bermak; Abdesselam Bouzerdoum

2004-01-01

390

SQI-CMOS based single crystal silicon micro-heaters for gas sensors  

Microsoft Academic Search

Here we report on novel high temperature gas sensors that have been fabricated using an SOI (silicon-on-insulator) -CMOS process and deep RIE back-etching. These sensors offer ultra-low power consumption, low unit cost, and excellent thermal stability. The highly-doped single crystal silicon (SCS) layer of a standard SOI-CMOS process, which is traditionally used to form the source and drain regions of

T. Iwaki; J. A. Covington; J. W. Gardner; F. Udrea; C. S. Blackman; I. P. Parkin

2006-01-01

391

UltraSensitive Capacitive Detection Based on SGMOSFET Compatible With Front-End CMOS Process  

Microsoft Academic Search

Capacitive measurement of very small displacement of nano-electro-mechanical systems (NEMS) presents some issues that are discussed in this article. It is shown that performance is fairly improved when integrating on a same die the NEMS and CMOS electronics. As an initial step toward full integration, an in-plane suspended gate MOSFET (SGMOSFET) compatible with a front-end CMOS has been developed. The

Eric Colinet; CÉdric Durand; Laurent Duraffourg; Patrick Audebert; Guillaume Dumas; Fabrice Casset; Eric Ollier; Pascal Ancey; Jean-FranÇois Carpentier; Lionel Buchaillot; Adrian M. Ionescu

2009-01-01

392

A 1.9GHz Single-Chip CMOS PHS Cellphone  

Microsoft Academic Search

A single-chip CMOS PHS cellphone, fabricated in a 0.18mum CMOS process, implements all handset functions including radio, voice, audio, CPU, and digital interfaces. The IC has +4dBm EVM-compliant transmit power, -106dBm receiver sensitivity, and 15mus synthesizer settling time. It draws 81 mA from a 1.8V supply while occupying 35mm2 of chip area

S. Mehta; W. W. Si; H. Samavati; M. Terrovitis; M. Mack; K. Onodera; S. Jen; S. Luschas; J. Hwang; S. Mendis; D. Su; B. Wooley

2006-01-01

393

A 1.9GHz Single-Chip CMOS PHS Cellphone  

Microsoft Academic Search

A single-chip CMOS PHS cellphone, integrated in a 0.18-mum CMOS technology, implements all handset functions including radio, voice, audio, MODEM, TDMA controller, CPU, and digital interfaces. Both the receiver and transmitter are based on a direct conversion architecture. The RF transceiver achieves -106 dBm receive sensitivity and +4 dBm EVM-compliant transmit power. The local oscillator, based on a sigma-delta fractional-N

William W. Si; Srenik Mehta; Hirad Samavati; Manolis Terrovitis; Michael Mack; Keith Onodera; Steve Jen; Susan Luschas; Justin Hwang; Suni Mendis; David Su; Bruce Wooley

2006-01-01

394

A Monolithic CMOS 5V\\/1V Switched Capacitor DC-DC Step-down Converter  

Microsoft Academic Search

A 5V\\/1V Switched Capacitor DC-DC converter is designed and fabricated in a 0.35mum CMOS technology. The high side and low side driver circuits and control circuit for the converter are integrated. A folded cascode high speed CMOS operational amplifier is designed as an integral part of the control circuit. Test structures are fabricated as part of the main chip to

A. K. P. Viraj; G. A. J. Amaratunga

2007-01-01

395

Design of a 3 ?m pixel linear CMOS sensor for earth observation  

NASA Astrophysics Data System (ADS)

A visible wavelength linear photosensor featuring a pixel size of 3 ?m has been designed for fabrication using commercial 0.25 ?m CMOS technology. For the photo-sensing element, the design uses a special "deep N-well" in P-epi diode offered by the foundry for imaging devices. Pixel reset is via an adjacent p-FET, thus allowing high reset voltages for a wide pixel voltage swing. The pixel voltage is buffered using a voltage-follower op-amp and a sampling scheme is used to allow correlated double sampling (CDS) for removal of reset noise. Reset and signal levels are buffered through a 16:1 multiplexer to a switched capacitor amplifier which performs the CDS function. Incorporated in the CDS circuit is a programmable gain of 1-8 for increased signal-to-noise ratio at low signal levels. Data output is via 4 analogue output drivers for off-chip conversion. Each driver supplies a differential output voltage with a ±1 V swing for improved power supply noise rejection. The readout circuitry is designed for 12 bit accuracy at frame rates of up to 6.25 kHz. This gives a peak data rate at each output driver of 10 M samples/s. The device will operate on a 3.3 V supply and will dissipate approximately 950 mW. Simulations indicate an equivalent noise charge at the pixel of 66.3 e - for a full well capacity of 255,000 e -, giving a dynamic range of 71.7 dB.

Morrissey, Q. R.; Waltham, N. R.; Turchetta, R.; French, M. J.; Bagnall, D. M.; Al-Hashimi, B. M.

2003-10-01

396

COMMERCIALIZATION OF BIOCONTROL  

Technology Transfer Automated Retrieval System (TEKTRAN)

Successful commercialization of biocontrol products requires the marriage of science and industry. From a science perspective, some of the issues to be addressed include knowledge of efficacy under various environmental conditions, inoculum density relationships, formulation, and when, where and ho...

397

Comparing Commercial WWW Browsers.  

ERIC Educational Resources Information Center

Four commercial World Wide Web browsers are evaluated for features such as handling of WWW protocols and different URLs: FTP, Telnet, Gopher and WAIS, and e-mail and news; bookmark capabilities; navigation features; file management; and security support. (JKP)

Notess, Greg R.

1995-01-01

398

NASA commercial programs  

NASA Technical Reports Server (NTRS)

Highlights of NASA-sponsored and assisted commercial space activities of 1989 are presented. Industrial R and D in space, centers for the commercial development of space, and new cooperative agreements are addressed in the U.S. private sector in space section. In the building U.S. competitiveness through technology section, the following topics are presented: (1) technology utilization as a national priority; (2) an exploration of benefits; and (3) honoring Apollo-Era spinoffs. International and domestic R and D trends, and the space sector are discussed in the section on selected economic indicators. Other subjects included in this report are: (1) small business innovation; (2) budget highlights and trends; (3) commercial programs management; and (4) the commercial programs advisory committee.

1990-01-01

399

Commercial Actors Stage Strike  

NSDL National Science Digital Library

On May 1, 2000, 75,000 members of the Screen Actors Guild (SAG) and the American Federation of Television and Radio Artists staged a walk-out in protest of advertisers's proposed changes to the ways in which actors get paid for work in commercials. According to the current pay scheme, principle on-screen actors appearing in network commercials earn $479 in base pay as well as a residual payment ranging from $47 to $123. Over a standard thirteen-week run, actors earn an average of $13,000 per commercial. However, actors in cable commercials make a flat fee of $479 to $1,014 for the same thirteen-week run. SAG and the American Federation of Television and Radio Artists are demanding a fourteen percent pay raise for both types of commercials. However, the advertisers would like to pay the actors only $2,575 for an unlimited thirteen-week network run. While this amount may seem like a lot of money, the average income for members of the SAG members is only $7000 a year, reflecting the possibility that actors may only appear in one or two commercials a year. This is the first major strike in the entertainment industry since 1988.

Missner, Emily D.

400

ERC commercialization activities  

SciTech Connect

The ERC family of companies is anticipating market entry of their first commercial product, a 2.8-MR power plant, in the second quarter of 1999. The present Cooperative Agreement provides for: (1) Commercialization planning and organizational development, (2) Completion of the pre-commercial DFC technology development, (3) Systems and plant design, (4) Manufacturing processes` scale-up to full- sized stack components and assemblies, (5) Upgrades to ERC`s test facility for full-sized stack testing, and (6) Sub-scale testing of a DFC Stack and BOP fueled with landfill gas. This paper discusses the first item, that of preparing for commercialization. ERC`s formal commercialization program began in 1990 with the selection of the 2-MR Direct Fuel Cell power plant by the American Public Power Association (APPA) for promotion to the over 2000 municipal utilities comprising APPA`s segment of the utility sector. Since that beginning, the APPA core group expanded to become the Fuel Cell Commercialization Group (FCCG) which includes representation from all markets - utilities and other power generation equipment buyers.

Maru, H.C.

1995-12-01

401

An array-based CMOS biochip for electrical detection of DNA with multilayer self-assembly gold nanoparticles  

Microsoft Academic Search

This paper presents an array-based CMOS biochip for DNA detection using self-assembly multilayer gold nanoparticles (AuNPs). The biochip is fabricated by a TSMC 0.35?m standard CMOS process and post-CMOS micromachining processes. Before taking DNA detection measurements, self-assembly monolayer of AuNPs is established on SiO2 surface between two microelectrodes. The gap distance between the two microelectrodes in this study is less

Yi-Ting Cheng; Ching-Chin Pun; Chien-Ying Tsai; Ping-Hei Chen

2005-01-01

402

A CMOS-compatible poly-Si nanowire device with hybrid sensor/memory characteristics for System-on-Chip applications.  

PubMed

This paper reports a versatile nano-sensor technology using "top-down" poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically V(th)-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady V(th) adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording. PMID:22666012

Chen, Min-Cheng; Chen, Hao-Yu; Lin, Chia-Yi; Chien, Chao-Hsin; Hsieh, Tsung-Fan; Horng, Jim-Tong; Qiu, Jian-Tai; Huang, Chien-Chao; Ho, Chia-Hua; Yang, Fu-Liang

2012-01-01

403

Low threshold vertical cavity surface emitting lasers integrated onto Si-CMOS ICs using novel hybrid assembly techniques  

E-print Network

A new heterogeneous integration technique has been developed and demonstrated to integrate vertical cavity surface emitting lasers (VCSELs) on silicon CMOS integrated circuits for optical interconnect applications. Individual ...

Perkins, James Michael, 1978-

2007-01-01

404

Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance  

NASA Technical Reports Server (NTRS)

Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

White, Mark; Cooper, Mark; Johnston, Allan

2011-01-01

405

Integrated RF-DC converter and PCB antenna for UHF wireless powering applications  

NASA Astrophysics Data System (ADS)

In this work, a broadband differential RF-DC CMOS converter realized in CMOS 130 nm technology with a customized PCB antenna with inductive coupling feeding for RF energy scavenging is presented. Experimental results show that output DC voltage higher than 1V from 800MHz to 970MHz can be obtained with a load of 1k?.

Vincetti, L.; Maini, M.; Scorcioni, S.; Larcher, L.; Bertacchini, A.; Tacchini, A.

2014-10-01

406

A Fine Resolution TDC Architecture for Next Generation PET Imaging  

Microsoft Academic Search

A fine resolution and process scalable CMOS time-to-digital converter (TDC) architecture is presented. A 6-bit fine resolution TDC design using the new architecture is evaluated for positron emission tomography (PET) imaging application. The TDC architecture uses a hierarchical delay processing structure to achieve single cycle latency and high speed of operation. The fine resolution converter, realized in 130 nm CMOS,

Abdel S. Yousif; James W. Haslett

2007-01-01

407

Commercial Fisheries Surveys  

USGS Publications Warehouse

In this chapter, we describe methods for sampling commercial fisheries and identify factors affecting the design of sampling plans. When sampled properly, commercial fisheries can provide important information on the response of aquatic organisms to exploitation; such information can be used by management agencies to develop regulations for ensuring long-term production of the resource and long-term economic benefit. Fishery statistics are typically used to estimate abundance, mortality, recruitment, growth, and other vital characterisitcs of populations. Fishery statistics can also be used to study changes in fish community composition resulting from differential exploitation of species.

Fabrizio, Mary C.; Richards, R. Anne

1996-01-01

408

Commercial Biomedical Experiments  

NASA Technical Reports Server (NTRS)

Experiments to seek solutions for a range of biomedical issues are at the heart of several investigations that will be hosted by the Commercial Instrumentation Technology Associates (ITA), Inc. Biomedical Experiments (CIBX-2) payload. CIBX-2 is unique, encompassing more than 20 separate experiments including cancer research, commercial experiments, and student hands-on experiments from 10 schools as part of ITA's ongoing University Among the Stars program. Valerie Cassanto of ITA checks the Canadian Protein Crystallization Experiment (CAPE) carried by STS-86 to Mir in 1997. The experiments are sponsored by NASA's Space Product Development Program (SPD).

2003-01-01

409

Commercial aircraft wake vortices  

Microsoft Academic Search

This paper discusses the problem of wake vortices shed by commercial aircraft. It presents a consolidated European view on the current status of knowledge of the nature and characteristics of aircraft wakes and of technical and operational procedures of minimizing and predicting the vortex strength and avoiding wake encounters.Methodological aspects of data evaluation and interpretation, like the description of wake

Thomas Gerz; Frank Holzäpfel; Denis Darracq

2002-01-01

410

Commercial aircraft wake vortices  

Microsoft Academic Search

This paper discusses the problem of wake vortices shed by commercial aircraft. It presents a consolidated European view on the current status of knowledge of the nature and characteristics of aircraft wakes and of technical and operational procedures of minimizing and predicting the vortex strength and avoiding wake encounters. Methodological aspects of data evaluation and interpretation, like the description of

Thomas Gerza; Frank Holz

411

Commercialization of the Internet.  

ERIC Educational Resources Information Center

Traces the growth of the Internet from its beginnings as the Defense Advanced Research Project Agency's ARPAnet. Discusses key issues facing network service providers including: acceptable use policies, liability exposure, the integration of research and production networks, the commercialization of the networks, and the need for global planning.…

Weis, Allan H.

1992-01-01

412

Commercial Vehicles Collaboration for  

E-print Network

hospitalized with chemical-induced pneumonia (which could have been fatal) ·January 1986 Shuttle (Challenger provide astronaut transportation to the International Space Station (ISS), reducing the sole reliance: Provide description of the challenges and opportunities associated with potential commercial crew

Waliser, Duane E.

413

COMMERCIAL TRUCKS MARINE MODES  

E-print Network

COMMERCIAL TRUCKS AVIATION MARINE MODES RAILROADS PIPELINES OFF-ROAD EQUIPMENT Potential for Energy Efficiency Improvement Beyond the Light-Duty-Vehicle Sector #12;#12;TRANSPORTATION ENERGY FUTURES SERIES: Potential for Energy Efficiency Improvement Beyond the Light-Duty-Vehicle Sector A Study Sponsored by U

414

Lunar Commercial Mining Logistics  

NASA Astrophysics Data System (ADS)

Innovative commercial logistics is required for supporting lunar resource recovery operations and assisting larger consortiums in lunar mining, base operations, camp consumables and the future commercial sales of propellant over the next 50 years. To assist in lowering overall development costs, ``reuse'' innovation is suggested in reusing modified LTS in-space hardware for use on the moon's surface, developing product lines for recovered gases, regolith construction materials, surface logistics services, and other services as they evolve, (Kistler, Citron and Taylor, 2005) Surface logistics architecture is designed to have sustainable growth over 50 years, financed by private sector partners and capable of cargo transportation in both directions in support of lunar development and resource recovery development. The author's perspective on the importance of logistics is based on five years experience at remote sites on Earth, where remote base supply chain logistics didn't always work, (Taylor, 1975a). The planning and control of the flow of goods and materials to and from the moon's surface may be the most complicated logistics challenges yet to be attempted. Affordability is tied to the innovation and ingenuity used to keep the transportation and surface operations costs as low as practical. Eleven innovations are proposed and discussed by an entrepreneurial commercial space startup team that has had success in introducing commercial space innovation and reducing the cost of space operations in the past. This logistics architecture offers NASA and other exploring nations a commercial alternative for non-essential cargo. Five transportation technologies and eleven surface innovations create the logistics transportation system discussed.

Kistler, Walter P.; Citron, Bob; Taylor, Thomas C.

2008-01-01

415

Measurements of Si hybrid CMOS x-ray detector characteristics  

NASA Astrophysics Data System (ADS)

The recent development of active pixel sensors as X-Ray focal plane arrays will place them in contention with CCDs on future satellite missions. Penn State University (PSU) is working with Teledyne Imaging Sensors (TIS) to develop X-Ray Hybrid CMOS devices (HCDs), a type of active pixel sensor with fast frame rates, adaptable readout timing and geometry, low power consumption, and inherent radiation hardness. CCDs have been used with great success on the current generation of X-Ray telescopes (e.g. Chandra, XMM, Suzaku, and Swift). However, their bucket-brigade readout architecture, which transfers charge across the chip with discrete component readout electronics, results in clockrate limited readout speeds that cause pileup (saturation) of bright sources and an inherent susceptibility to radiation induced displacement damage that limits mission lifetime. In contrast, HCDs read pixels through the detector substrate with low power, on-chip readout integrated circuits. Faster frame rates, achieved with adaptable readout timing and geometry, will allow the next generation's larger effective area telescopes to observe brighter sources free of pileup. In HCDs, radiation damaged lattice sites affect a single pixel instead of an entire row. The PSU X-ray group is currently testing 4 Teledyne HCDs, with low cross-talk CTIA devices in development. We will report laboratory measurements of HCD readnoise, interpixel-capacitance and its impact on event selection, linearity, and energy resolution as a function of energy.

Bongiorno, Stephen D.; Falcone, Abraham D.; Burrows, David N.; Cook, Robert

2010-07-01

416

Measurements of Si hybrid CMOS x-ray detector characteristics  

NASA Astrophysics Data System (ADS)

The development of Hybrid CMOS Detectors (HCDs) for X-Ray telescope focal planes will place them in contention with CCDs on future satellite missions due to their faster frame rates, flexible readout scenarios, lower power consumption, and inherent radiation hardness. CCDs have been used with great success on the current generation of X-Ray telescopes (e.g. Chandra, XMM, Suzaku, and Swift). However their bucket-brigade readout architecture, which transfers charge across the chip with discrete component readout electronics, results in clockrate limited readout speeds that cause pileup (saturation) of bright sources and an inherent susceptibility to radiation induced displacement damage that limits mission lifetime. In contrast, HCDs read pixels with low power, on-chip multiplexer electronics in a random access fashion. Faster frame rates achieved with multi-output readout design will allow the next generation's larger effective area telescopes to observe bright sources free of pileup. Radiation damaged lattice sites effect a single pixel instead of an entire row. Random access, multi-output readout will allow for novel readout modes such as simultaneous bright-source-fast/whole-chip-slow readout. In order for HCDs to be useful as X-Ray detectors, they must show noise and energy resolution performance similar to CCDs while retaining advantages inherent to HCDs. We will report on readnoise, conversion gain, and energy resolution measurements of an X-Ray enhanced Teledyne HAWAII-1RG (H1RG) HCD and describe techniques of H1RG data reduction.

Bongiorno, Stephen D.; Falcone, Abe D.; Burrows, David N.; Cook, Robert; Bai, Yibin; Farris, Mark

2009-08-01

417

Novel integrated CMOS pixel structures for vertex detectors  

SciTech Connect

Novel CMOS active pixel structures for vertex detector applications have been designed and tested. The overriding goal of this work is to increase the signal to noise ratio of the sensors and readout circuits. A large-area native epitaxial silicon photogate was designed with the aim of increasing the charge collected per struck pixel and to reduce charge diffusion to neighboring pixels. The photogate then transfers the charge to a low capacitance readout node to maintain a high charge to voltage conversion gain. Two techniques for noise reduction are also presented. The first is a per-pixel kT/C noise reduction circuit that produces results similar to traditional correlated double sampling (CDS). It has the advantage of requiring only one read, as compared to two for CDS, and no external storage or subtraction is needed. The technique reduced input-referred temporal noise by a factor of 2.5, to 12.8 e{sup -}. Finally, a column-level active reset technique is explored that suppresses kT/C noise during pixel reset. In tests, noise was reduced by a factor of 7.6 times, to an estimated 5.1 e{sup -} input-referred noise. The technique also dramatically reduces fixed pattern (pedestal) noise, by up to a factor of 21 in our tests. The latter feature may possibly reduce pixel-by-pixel pedestal differences to levels low enough to permit sparse data scan without per-pixel offset corrections.

Kleinfelder, Stuart; Bieser, Fred; Chen, Yandong; Gareus, Robin; Matis, Howard S.; Oldenburg, Markus; Retiere, Fabrice; Ritter, Hans Georg; Wieman, Howard H.; Yamamoto, Eugene

2003-10-29

418

Passive radiation detection using optically active CMOS sensors  

NASA Astrophysics Data System (ADS)

Recently, there have been a number of small-scale and hobbyist successes in employing commodity CMOS-based camera sensors for radiation detection. For example, several smartphone applications initially developed for use in areas near the Fukushima nuclear disaster are capable of detecting radiation using a cell phone camera, provided opaque tape is placed over the lens. In all current useful implementations, it is required that the sensor not be exposed to visible light. We seek to build a system that does not have this restriction. While building such a system would require sophisticated signal processing, it would nevertheless provide great benefits. In addition to fulfilling their primary function of image capture, cameras would also be able to detect unknown radiation sources even when the danger is considered to be low or non-existent. By experimentally profiling the image artifacts generated by gamma ray and ? particle impacts, algorithms are developed to identify the unique features of radiation exposure, while discarding optical interaction and thermal noise effects. Preliminary results focus on achieving this goal in a laboratory setting, without regard to integration time or computational complexity. However, future work will seek to address these additional issues.

Dosiek, Luke; Schalk, Patrick D.

2013-05-01

419

High resolution, high bandwidth global shutter CMOS area scan sensors  

NASA Astrophysics Data System (ADS)

Global shuttering, sometimes also known as electronic shuttering, enables the use of CMOS sensors in a vast range of applications. Teledyne DALSA Global shutter sensors are able to integrate light synchronously across millions of pixels with microsecond accuracy. Teledyne DALSA offers 5 transistor global shutter pixels in variety of resolutions, pitches and noise and full-well combinations. One of the recent generations of these pixels is implemented in 12 mega pixel area scan device at 6 um pitch and that images up to 70 frames per second with 58 dB dynamic range. These square pixels include microlens and optional color filters. These sensors also offer exposure control, anti-blooming and high dynamic range operation by introduction of a drain and a PPD reset gate to the pixel. The state of the art sense node design of Teledyne DALSA's 5T pixel offers exceptional shutter rejection ratio. The architecture is consistent with the requirements to use stitching to achieve very large area scan devices. Parallel or serial digital output is provided on these sensors using on-chip, column-wise analog to digital converters. Flexible ADC bit depth combined with windowing (adjustable region of interest, ROI) allows these sensors to run with variety of resolution/bandwidth combinations. The low power, state of the art LVDS I/O technology allows for overall power consumptions of less than 2W at full performance conditions.

Faramarzpour, Naser; Sonder, Matthias; Li, Binqiao

2013-10-01

420

A CMOS ASIC Design for SiPM Arrays.  

PubMed

Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

2011-12-01

421

CMOS monolithic active pixel sensors for high energy physics  

NASA Astrophysics Data System (ADS)

Monolithic pixel detectors integrating sensor matrix and readout in one piece of silicon are only now starting to make their way into high energy physics. Two major requirements are radiation tolerance and low power consumption. For the most extreme radiation levels, signal charge has to be collected by drift from a depletion layer onto a designated collection electrode without losing the signal charge elsewhere in the in-pixel circuit. Low power consumption requires an optimization of Q/C, the ratio of the collected signal charge over the input capacitance [1]. Some solutions to combine sufficient Q/C and collection by drift require exotic fabrication steps. More conventional solutions up to now require a simple in-pixel readout circuit. Both high voltage CMOS technologies and Monolithic Active Pixel Sensors (MAPS) technologies with high resistivity epitaxial layers offer high voltage diodes. The choice between the two is not fundamental but more a question of how much depletion can be reached and also of availability and cost. This paper tries to give an overview.

Snoeys, W.

2014-11-01

422

Multi-Aperture CMOS Sun Sensor for Microsatellite Attitude Determination  

PubMed Central

This paper describes the high precision digital sun sensor under development at the University of Naples. The sensor determines the sun line orientation in the sensor frame from the measurement of the sun position on the focal plane. It exploits CMOS technology and an original optical head design with multiple apertures. This allows simultaneous multiple acquisitions of the sun as spots on the focal plane. The sensor can be operated either with a fixed or a variable number of sun spots, depending on the required field of view and sun-line measurement precision. Multiple acquisitions are averaged by using techniques which minimize the computational load to extract the sun line orientation with high precision. Accuracy and computational efficiency are also improved thanks to an original design of the calibration function relying on neural networks. Extensive test campaigns are carried out using a laboratory test facility reproducing sun spectrum, apparent size and distance, and variable illumination directions. Test results validate the sensor concept, confirming the precision improvement achievable with multiple apertures, and sensor operation with a variable number of sun spots. Specifically, the sensor provides accuracy and precision in the order of 1 arcmin and 1 arcsec, respectively. PMID:22408538

Rufino, Giancarlo; Grassi, Michele

2009-01-01

423

Design of a CMOS Potentiostat Circuit for Electrochemical Detector Arrays  

PubMed Central

High-throughput electrode arrays are required for advancing devices for testing the effect of drugs on cellular function. In this paper, we present design criteria for a potentiostat circuit that is capable of measuring transient amperometric oxidation currents at the surface of an electrode with submillisecond time resolution and picoampere current resolution. The potentiostat is a regulated cascode stage in which a high-gain amplifier maintains the electrode voltage through a negative feedback loop. The potentiostat uses a new shared amplifier structure in which all of the amplifiers in a given row of detectors share a common half circuit permitting us to use fewer transistors per detector. We also present measurements from a test chip that was fabricated in a 0.5-?m, 5-V CMOS process through MOSIS. Each detector occupied a layout area of 35?m × 15?m and contained eight transistors and a 50-fF integrating capacitor. The rms current noise at 2kHz bandwidth is ? 110fA. The maximum charge storage capacity at 2kHz is 1.26 × 106 electrons. PMID:20514150

Ayers, Sunitha; Gillis, Kevin D.; Lindau, Manfred; Minch, Bradley A.

2010-01-01

424

Noise limits of CMOS current interfaces for biosensors: a review.  

PubMed

Current sensing readout is one of the most frequent techniques used in biosensing due to the charge-transfer phenomena occurring at solid-liquid interfaces. The development of novel nanodevices for biosensing determines new challenges for electronic interface design based on current sensing, especially when compact and efficient arrays need to be organized, such as in recent trends of rapid label-free electronic detection of DNA synthesis. This paper will review the basic noise limitations of current sensing interfaces with particular emphasis on integrated CMOS technology. Starting from the basic theory, the paper presents, investigates and compares charge-sensitive amplifier architectures used in both continuous-time and discrete-time approaches, along with their design trade-offs involving noise floor, sensitivity to stray capacitance and bandwidth. The ultimate goal of this review is providing analog designers with helpful design rules and analytical tools. Also, in order to present a comprehensive overview of the state-of-the-art, the most relevant papers recently appeared in the literature about this topic are discussed and compared. PMID:24875287

Crescentini, Marco; Bennati, Marco; Carminati, Marco; Tartagni, Marco

2014-04-01

425

Improved Signal Chains for Readout of CMOS Imagers  

NASA Technical Reports Server (NTRS)

An improved generic design has been devised for implementing signal chains involved in readout from complementary metal oxide/semiconductor (CMOS) image sensors and for other readout integrated circuits (ICs) that perform equivalent functions. The design applies to any such IC in which output signal charges from the pixels in a given row are transferred simultaneously into sampling capacitors at the bottoms of the columns, then voltages representing individual pixel charges are read out in sequence by sequentially turning on column-selecting field-effect transistors (FETs) in synchronism with source-follower- or operational-amplifier-based amplifier circuits. The improved design affords the best features of prior source-follower-and operational- amplifier-based designs while overcoming the major limitations of those designs. The limitations can be summarized as follows: a) For a source-follower-based signal chain, the ohmic voltage drop associated with DC bias current flowing through the column-selection FET causes unacceptable voltage offset, nonlinearity, and reduced small-signal gain. b) For an operational-amplifier-based signal chain, the required bias current and the output noise increase superlinearly with size of the pixel array because of a corresponding increase in the effective capacitance of the row bus used to couple the sampled column charges to the operational amplifier. The effect of the bus capacitance is to simultaneously slow down the readout circuit and increase noise through the Miller effect.

Pain, Bedabrata; Hancock, Bruce; Cunningham, Thomas

2009-01-01

426

Auto-zero stabilized CMOS amplifiers for very low voltage or current offset Daniel Dzahini (1), Hamid Ghazlane (2)  

E-print Network

Auto-zero stabilized CMOS amplifiers for very low voltage or current offset Daniel Dzahini (1 Rabat Principal 10001 Morocco Abstract---In this paper, we present two amplifiers designed in CMOS precision operational amplifier focusing on the voltage offset. It is a continuous time auto-zero stabilized

Boyer, Edmond

427

A Low Voltage, Rail-to-Rail, Class AB CMOS Amplifier With High Drive and Low Output Impedance Characteristics  

E-print Network

1 A Low Voltage, Rail-to-Rail, Class AB CMOS Amplifier With High Drive and Low Output Impedance describes a CMOS rail-to-rail class AB operational amplifier designed to have extremely low output impedance for low voltage battery-powered applications. Index Terms-- Class AB, rail-to-rail, low output impedance

Rincon-Mora, Gabriel A.

428

A 3-Pin 1.5 V 550 W 176 x 144 Self-Clocked CMOS Active Pixel Image Sensor  

E-print Network

and row driver with a reset bootstrapping circuit so that all pixels in the row are read out into column), and DATAOUT). The die occupies 4 mm2 of silicon. Keywords Active Pixel Sensor, Image Sensor, CMOS, Low miniaturized systems-on-a-chip (SoCs) which integrate these multiple functions on the single imaging chip. CMOS

Fossum, Eric R.

429

A 0.18 ?m CMOS low-power radiation sensor for asynchronous event-driven UWB wireless transmission  

NASA Astrophysics Data System (ADS)

The paper describes the design of a readout element, proposed as a radiation monitor, which implements an embedded sensor based on a floating-gate transistor. The paper shows the design of a microelectronic circuit composed of a sensor, an oscillator, a modulator, a transmitter and an integrated antenna. A prototype chip has recently been fabricated and tested exploiting a commercial 180 nm, four metal CMOS technology. Simulation results of the entire behavior of the circuit before submission are presented along with some measurements of the actual chip response. In addition, preliminary tests of the performance of the Ultra-Wide Band transmission via the integrated antenna are summarized. As the complete chip prototype area is less than 1 mm2, the chip fits a large variety of applications, from spot radiation monitoring systems in medicine to punctual measurements of radiation level in High-Energy Physics experiments. A sensitivity of 1 mV/rad was estimated within an absorbed dose range up to 10 krad and a total power consumption of about 165 ?W.

Bastianini, S.; Crepaldi, M.; Demarchi, D.; Gabrielli, A.; Lolli, M.; Margotti, A.; Villani, G.; Zhang, Z.; Zoccoli, G.

2013-12-01

430

A scalable neural chip with synaptic electronics using CMOS integrated memristors  

NASA Astrophysics Data System (ADS)

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73?728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Cruz-Albrecht, Jose M.; Derosier, Timothy; Srinivasa, Narayan

2013-09-01

431

A scalable neural chip with synaptic electronics using CMOS integrated memristors.  

PubMed

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73?728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. PMID:23999447

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-27

432

60-GHz array antenna with standard CMOS technology on Schott Borofloat  

NASA Astrophysics Data System (ADS)

This design is presented of a 2 × 2 planar array, with a half-wave dipole antenna to be its element, on a new substrate material, Schott Borofloat, with CMOS technology in the 60 GHz band. In the proposed structure, all the designs are based on the CMOS technology and similar performance could be achieved with the same size in contrast to the design on low-temperature co-fired ceramic (LTCC). This could lead to the improving of the compatibility with the CMOS IC process, the design cost and the design precision which is restricted in the LTCC process. The simulated -10 dB bandwidth of the array is from 58 to 64 GHz. A peak gain of 9.4 dBi is achieved. Good agreement on return loss is achieved between simulations and measurements.

Jun, Luo; Yan, Wang; Ruifeng, Yue

2013-11-01

433

An arrayed accelerometer device of a wide range of detection for integrated CMOS-MEMS technology  

NASA Astrophysics Data System (ADS)

This paper reports the design and experimental results of an arrayed accelerometer device in 3 × 3 format that can detect wide range of acceleration between 1G and 20G (1G = 9.8 m/s2). Implemented in a single chip has been performed by gold electroplating for integrated complementary metal oxide semiconductor-microelectromechanical systems (CMOS-MEMS) technology. An equivalent circuit of a MEMS accelerometer has been developed with an electrical circuit simulator to demonstrate the mixed-behavior of the arrayed sensor device and sensing CMOS circuits. Mechanical and electrical crosstalk between the arrayed elements is analyzed on the electrical field distributions. Experimental results show that the resonant frequency and readout capacitance as a function of applied acceleration have been well explained by the results of the multi-physics simulation. As a result, it is confirmed that the proposed device is applicable to an integrated CMOS-MEMS arrayed accelerometer.

Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

2014-02-01

434

Composite-CMOS integrated photonics for high bandwidth WDM optical interconnects  

NASA Astrophysics Data System (ADS)

Bandwidth requirements continue to drive the need for low-power, high speed interconnects. Harnessing the mature CMOS technology for high volume manufacturing, Silicon Photonics is a top candidate for providing a viable solution for high bandwidth, low cost, low power, and high packing density, optical interconnects. The major drawback of silicon, however, is that it is an indirect bandgap material, and thus cannot produce coherent light. Consequently, different integration schemes of III/V materials on silicon are being explored. An integrated CMOS tunable laser is demonstrated as part of a composite-CMOS integration platform that enables high bandwidth optical interconnects. The integration platform embeds III-V into silicon chips using a metal bonding technique that provides low thermal resistance and avoids lattice mismatch problems. The performance of the laser including side mode suppression ratio, relative intensity noise, and linewidth is summarized.

Creazzo, Timothy; Marchena, Elton; Krasulick, Stephen B.; Yu, Paul K. L.; Van Orden, Derek; Spann, John Y.; Blivin, Christopher C.; He, Lina; Cai, Hong; Dallesasse, John M.; Stone, Robert J.; Mizrahi, Amit

2014-03-01

435

CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results  

NASA Astrophysics Data System (ADS)

The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400 ? cm, which is at least one order of magnitude greater than the typical value (1-10 ? cm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported.

Rivetti, A.; Battaglia, M.; Bisello, D.; Caselle, M.; Chalmet, P.; Costa, M.; Demaria, N.; Giubilato, P.; Ikemoto, Y.; Kloukinas, K.; Mansuy, C.; Marchioro, A.; Mugnier, H.; Pantano, D.; Potenza, A.; Rousset, J.; Silvestrin, L.; Wyss, J.

2013-12-01

436

CMOS compatible silicon-based Mach-Zehnder optical modulators with improved extinction ratio  

NASA Astrophysics Data System (ADS)

Improved Extinction Ratio of 25 dB was demonstrated in silicon based optical modulators on CMOS platform in China. The measurement results agree with the simulation, followed by a discussion about the effects of both propagation loss in Mach-Zehnder arms and power ratio at beam splitters and combiners. The analyses indicate that many considerations have to be taken into design and development of the compatible fabrication of these integrated silicon photonics, especially for the improved extinction ratio of optical modulators. In this summary, we propose the integrated optical modulators in SOI by use of the compatible CMOS processes under the modern CMOS foundry in Chinese homeland. And the measured results were shown, the fast response modulator with the data transmission rate of 10 Gbps.

Li, Zhiyong; Zhou, Liang; Hu, Yingtao; Xiao, Xi; Yu, Yude; Yu, Jinzhong

2012-02-01

437

High-level numerical simulations of noise in CCD and CMOS photosensors: review and tutorial  

E-print Network

In many applications, such as development and testing of image processing algorithms, it is often necessary to simulate images containing realistic noise from solid-state photosensors. A high-level model of CCD and CMOS photosensors based on a literature review is formulated in this paper. The model includes photo-response non-uniformity, photon shot noise, dark current Fixed Pattern Noise, dark current shot noise, offset Fixed Pattern Noise, source follower noise, sense node reset noise, and quantisation noise. The model also includes voltage-to-voltage, voltage-to-electrons, and analogue-to-digital converter non-linearities. The formulated model can be used to create synthetic images for testing and validation of image processing algorithms in the presence of realistic images noise. An example of the simulated CMOS photosensor and a comparison with a custom-made CMOS hardware sensor is presented. Procedures for characterisation from both light and dark noises are described. Experimental results that confirm...

Konnik, Mikhail

2014-01-01

438

Application of CMOS image sensor OV9620 in number recognition system  

NASA Astrophysics Data System (ADS)

An image acquisition system is introduced, which consists of a color CMOS image sensor (OV9620), SRAM (CY62148), CPLD (EPM7128AE) and DSP (TMS320VC5509A). The CPLD implements the logic and timing control to the system. SRAM stores the image data, and DSP controls the image acquisition system through the SCCB (Omni Vision Serial Camera Control Bus). The timing sequence of the CMOS image sensor OV9620 is analyzed. The imaging part and the high speed image data memory unit are designed. The system structure and its application of CMOS image sensor OV9620 in paper currency number recognition are also introduced. The hardware and software design of the image acquisition and recognition system is given. In this system, we use the template matching character recognition method to guarantee fast recognition speed and high correct recognition probability.

Li, Yu-feng; Liang, Fei; Xue, Rong-kun

2009-11-01

439

Recent Design Development in Molecular Imaging for Breast Cancer Detection Using Nanometer CMOS Based Sensors  

PubMed Central

As one of the key clinical imaging methods, the computed X-ray tomography can be further improved using new nanometer CMOS sensors. This will enhance the current technique's ability in terms of cancer detection size, position, and detection accuracy on the anatomical structures. The current paper reviewed designs of SOI-based CMOS sensors and their architectural design in mammography systems. Based on the existing experimental results, using the SOI technology can provide a low-noise (SNR around 87.8?db) and high-gain (30 v/v) CMOS imager. It is also expected that, together with the fast data acquisition designs, the new type of imagers may play important roles in the near-future high-dimensional images in additional to today's 2D imagers. PMID:23319947

Nguyen, Dung C.; Ma, Dongsheng (Brian); Roveda, Janet M. W.

2012-01-01

440

A novel single-poly floating-gate UV sensor using standard CMOS process  

NASA Astrophysics Data System (ADS)

This paper proposes a novel single-poly floating gate (FG) UV sensor in standard CMOS process. The sensor cell is based on PMOS FG and only adopts four transistors including sensitive component and readout amplifier. The architecture is compact and feasible for future high density array chip implementation. A theoretical analysis of sensor sensitivity is described in detail. As the sensor is compatible with standard single poly CMOS process, it has the merits of low cost, more sensitive, and be integrated with signal processing system. A prototype chip is manufactured in a 0.18?m single-poly standard CMOS logic process. The tested results indicate that the sensor is sensitive to the incoming UV irradiation.

Li, Guike; Li, Yunlong; Feng, Peng; Wu, Nanjian

2009-07-01

441

New generation CMOS 2D imager evaluation and qualification for semiconductor inspection applications  

NASA Astrophysics Data System (ADS)

Semiconductor fabrication process defect inspection industry is always driven by inspection resolution and through-put. With fabrication technology node advances to 2X ~1Xnm range, critical macro defect size approaches to typical CMOS camera pixel size range, therefore single pixel defect detection technology becomes more and more essential, which is fundamentally constrained by camera performance. A new evaluation model is presented here to specifically describe the camera performance for semiconductor machine vision applications, especially targeting at low image contrast high speed applications. Current mainline cameras and high-end OEM cameras are evaluated with this model. Camera performances are clearly differentiated among CMOS technology generations and vendors, which will facilitate application driven camera selection and operation optimization. The new challenges for CMOS detectors are discussed for semiconductor inspection applications.

Zhou, Wei; Hart, Darcy

2013-09-01

442

Commercial jet transport crashworthiness  

NASA Technical Reports Server (NTRS)

The results of a study to identify areas of research and approaches that may result in improved occupant survivability and crashworthiness of transport aircraft are given. The study defines areas of structural crashworthiness for transport aircraft which might form the basis for a research program. A 10-year research and development program to improve the structural impact resistance of general aviation and commercial jet transport aircraft is planned. As part of this program parallel studies were conducted to review the accident experience of commercial transport aircraft, assess the accident performance of structural components and the status of impact resistance technology, and recommend areas of research and development for that 10-year plan. The results of that study are also given.

Widmayer, E.; Brende, O. B.

1982-01-01

443

European commercial aeronautics  

NASA Technical Reports Server (NTRS)

During the months of June to September, 1924, I personally visited the principal airports of Europe and traveled as a passenger some 6500 air miles on English, French, Romanian, Polish, German and Dutch air lines in order to investigate the development of commercial aviation abroad. The results of the investigation are embodied in a series of reports, of which a summary of the general findings is given below.

Van Zandt, J Parker

1925-01-01

444

Fabrication and characterization of a charge-biased CMOS-MEMS resonant gate field effect transistor  

NASA Astrophysics Data System (ADS)

A high-frequency charge-biased CMOS-MEMS resonant gate field effect transistor (RGFET) composed of a metal-oxide composite resonant-gate structure and an FET transducer has been demonstrated utilizing the TSMC 0.35??m CMOS technology with Q > 1700 and a signal-to-feedthrough ratio greater than 35?dB under a direct two-port measurement configuration. As compared to the conventional capacitive-type MEMS resonators, the proposed CMOS-MEMS RGFET features an inherent transconductance gain (gm) offered by the FET transduction capable of enhancing the motional signal of the resonator and relaxing the impedance mismatch issue to its succeeding electronics or 50 ?-based test facilities. In this work, we design a clamped-clamped beam resonant-gate structure right above a floating gate FET transducer as a high-Q building block through a maskless post-CMOS process to combine merits from the large capacitive transduction areas of the large-width beam resonator and the high gain of the underneath FET. An analytical model is also provided to simulate the behavior of the charge-biased RGFET; the theoretical prediction is in good agreement with the experimental results. Thanks to the deep-submicrometer gap spacing enabled by the post-CMOS polysilicon release process, the proposed resonator under a purely capacitive transduction already attains motional impedance less than 10?k?, a record-low value among CMOS-MEMS capacitive resonators. To go one step further, the motional signal of the proposed RGFET is greatly enhanced through the FET transduction. Such a strong transmission and a sharp phase transition across 0° pave a way for future RGFET-type oscillators in RF and sensor applications. A time-elapsed characterization of the charge leakage rate for the floating gate is also carried out.

Chin, C. H.; Li, C. S.; Li, M. H.; Wang, Y. L.; Li, S. S.

2014-09-01

445

Integration hybride de transistors a un electron sur un noeud technologique CMOS  

NASA Astrophysics Data System (ADS)

This study deals with the hybrid integration of single electron transistors (SET) on a CMOS technology nod. SET devices possess a high potential, especially regarding energy efficiency, but aren't fit to completely replace CMOS components in electrical circuits. However, this problem can be solved through hybrid combination of SETs and MOS, leading to very low operating power circuits, and high integration density. This thesis investigates the use of the nanodamascene process, developed by C. Dubuc, for back-end-of-line (BEOL) SET fabrication, meaning creation of SETs in the oxide encapsulating CMOS devices. The assets the nanodamascene process presents are quite interesting: fabrication of SETs with a large operation margin, high repeatability, and potential for BEOL fabrication. This last point, in particular, makes this process promising. Indeed, it opens the path to the fabrication of numerous layers of SETs, stacked one upon the other, and forming 3D circuits, created on top of 2D CMOS layer. Thus a high gain to existing CMOS wafers could be generated. Devices created through the use of the nanodamascene process, adapted for BEOL SET fabrication, are presented. Limits and improvement perspectives of the technique's transfer are discussed. Electrical characterizations of the devices are also presented. They have demonstrated the created devices functionality, thus validating the successful adaption of the nanodamascene process. They have also allowed for the identification of numerous traps located at the heart of fabricated devices. Fabricated SET devices potential for hybrid SET-CMOS circuits was studied through simulations. Possible architectures showing good potential for early hybrid circuits' realization were identified. Keywords: MOSFET, single electron transistor (SET), nanotechnology, microfabrication, nanodamascene, electrical characterization.

Jouvet, Nicolas

446

High throughput single-ion-channel array microsystem with CMOS instrumentation.  

PubMed

Ion channels play critical roles in transporting chemical species into and out of cells. Ion channels are also targets for drug discovery and new receptor-based analytical technologies. To better understand ion channel structure and function, a high throughput membrane protein characterization microsystem is being developed. This microsystem integrates a 1024-element array of planar bilayer lipid membrane (pBLM) chambers with microfluidics and embedded CMOS electrochemical instrumentation circuits. This paper introduces the CMOS instrumentation circuits that support readout of 1024 pBLM elements in parallel and provide current pixel amplifiers within each cell for local amplification of the weak ion channel response currents. PMID:25570564

Xiaowen Liu; Lin Li; Mason, Andrew J

2014-08-01

447

Prediction and measurement of radiation damage to CMOS devices on board spacecraft  

NASA Technical Reports Server (NTRS)

The initial results obtained from the Complementary Metal Oxide Semiconductors Radiation Effects Measurement experiment are presented. Predictions of radiation damage to C-MOS devices are based on standard environment models and computational techniques. A comparison of the shifts in CMOS threshold potentials, that is, those measured in space to those obtained from the on the ground simulation experiment with Co 60, indicated that the measured space damage is greater than predicted by a factor of two for shields thicker than 100 mils (2.54 mm), but agrees well with predictions for the thinner shields.

Cliff, R. A.; Danchenko, V.; Stassinopoulos, E. G.; Sing, M.; Brucker, G. J.; Ohanian, R. S.

1976-01-01

448

Wideband Matched CMOS LNA Design Using R-L-C Loading Network  

NASA Astrophysics Data System (ADS)

This paper proposes a new methodology for designing and analyzing wideband matched CMOS LNA with R-L-C loading network, where validity of this new approach is supported by the agreement between the simulated input impedance of the LNA and its calculated counterpart. To demonstrate its feasibility, two wideband matched LNA’s are designed using TSMC 0.18-?m RF-CMOS process. One is for 3-8 GHz application and the second one targets at 8-25 GHz frequency range. The measured results of both circuits will then be presented.

Wu, Hui-I.; Horng, Qi-Yuan; Hu, Robert; Jou, Christina F.

2010-09-01

449

180 Degree Hybrid (Rat-Race) Junction on CMOS Grade Silicon with a Polyimide Interface Layer  

NASA Technical Reports Server (NTRS)

180-degree hybrid junctions can be used to equally divide power between two output ports with either a 0 or 180-degree phase difference. Alternatively, they can be used to combine signals from two sources and output a sum and difference signal. The main limitation of implementing; these on CMOS grade silicon is the high loss associated with the substrate. In this paper, we present a low loss 180-degree hybrid junction on CMOS grade (15 omega-cm) silicon with a polyimide interface layer for the first time. The divider utilizes Finite Ground Coplanar (FGC) line technology, and operates at a center frequency of 15 GIIz.

Ponchak, George E.; Papapolymerou, John

2003-01-01

450

A novel 3D stacking method for Opto-electronic dies on CMOS ICs.  

PubMed

A high speed, high density and potentially low cost solution for realizing a compact transceiver module is presented in this paper. It is based on directly bonding an Opto-electronic die on top of CMOS IC chip and creating a photoresist ramp to bridge the big step (around 220 ?m) from Opto-electronic pads to CMOS IC pads. The required electrical connection between them is realized lithographically with a process than can be scaled to full wafer production. A 12-channel transmitter based on the technique was fabricated and test shows good performance up to 12.5 Gb/s/ch. PMID:23262878

Duan, Pinxiang; Raz, Oded; Smalbrugge, Barry E; Duis, Jeroen; Dorren, Harm J S

2012-12-10

451

A high performance epitaxial SiGe-base ECL BiCMOS technology  

Microsoft Academic Search

In this work we present a high speed, self-aligned SiGe epitaxial-base ECL BiCMOS technology in which we achieved a record 18.9 ps ECL gate delay at 7.7 mW, 59 GHz peak fmax, 50 GHz peak f T, and 0.25 ?m-channel CMOS devices with transconductances of 240 mS\\/mm for the nFET and 140 mS\\/mm for the pFET. Key technology features include

D. L. Harame; E. F. Crabbe; J. D. Cressler; J. H. Comfort; J. Y.-C. Sun; S. R. Stiffler; E. Kobeda; J. N. Burghartz; M. M. Gilbert; J. C. Malinowski; A. J. Dally; S. Ratanaphanyarat; M. J. Saccamango; W. Rausch; J. Cotte; C. Chu; J. M. C. Stork

1992-01-01

452

A novel CMOS sensor with in-pixel auto-zeroed discrimination for charged particle tracking  

NASA Astrophysics Data System (ADS)

With the aim of developing fast and granular Monolithic Active Pixels Sensors (MAPS) as new charged particle tracking detectors for high energy physics experiments, a new rolling shutter binary pixel architecture concept (RSBPix) with in-pixel correlated double sampling, amplification and discrimination is presented. The discriminator features auto-zeroing in order to compensate process-related transistor mismatches. In order to validate the pixel, a first monolithic CMOS sensor prototype, including a pixel array of 96 × 64 pixels, has been designed and fabricated in the Tower-Jazz 0.18 ?m CMOS Image Sensor (CIS) process. Results of laboratory tests are presented.

Degerli, Y.; Guilloux, F.; Orsini, F.

2014-05-01

453

Characterization of an x-ray hybrid CMOS detector with low interpixel capacitive crosstalk  

NASA Astrophysics Data System (ADS)

We present the results of x-ray measurements on a hybrid CMOS detector that uses a H2RG ROIC and a unique bonding structure. The silicon absorber array has a 36?m pixel size, and the readout array has a pitch of 18?m but only one readout circuit line is bonded to each 36x36?m absorber pixel. This unique bonding structure gives the readout an effective pitch of 36?m. We find the increased pitch between readout bonds significantly reduces the interpixel capacitance of the CMOS detector reported by Bongiorno et al. 20101 and Kenter et al. 2005.2

Griffith, Christopher V.; Bongiorno, Stephen D.; Burrows, David N.; Falcone, Abraham D.; Prieskorn, Zachary R.

2012-07-01

454

A Smart Single-Chip Micro-Hotplate-Based Gas Sensor System in CMOS-Technology  

Microsoft Academic Search

This paper presents a monolithic chemical gas sensor system fabricated in industrial CMOS-technology combined with post-CMOS micromachining. The system comprises metal-oxide-covered (SnO2) micro-hotplates and the necessary driving and signal-conditioning circuitry. The SnO2 sensitive layer is operated at temperatures between 200 and 350°C. The on-chip temperature controller regulates the temperature of the membrane up to 350°C with a resolution of 0.5°C.

Diego Barrettino; Markus Graf; Martin Zimmermann; Christoph Hagleitner; Andreas Hierlemann; Henry Baltes

2004-01-01

455

sCMOS detector for imaging VNIR spectrometry  

NASA Astrophysics Data System (ADS)

The facility Optical Information Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the scientific results of the institute of leading edge instruments and focal plane designs for EnMAP VIS/NIR spectrograph. EnMAP (Environmental Mapping and Analysis Program) is one of the selected proposals for the national German Space Program. The EnMAP project includes the technological design of the hyper spectral space borne instrument and the algorithms development of the classification. The EnMAP project is a joint response of German Earth observation research institutions, value-added resellers and the German space industry like Kayser-Threde GmbH (KT) and others to the increasing demand on information about the status of our environment. The Geo Forschungs Zentrum (GFZ) Potsdam is the Principal Investigator of EnMAP. DLR OS and KT were driving the technology of new detectors and the FPA design for this project, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generations of space borne sensor systems are focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large swath and high spectral resolution with intelligent synchronization control, fast-readout ADC chains and new focal-plane concepts open the door to new remote-sensing and smart deep space instruments. The paper gives an overview over the detector verification program at DLR on FPA level, new control possibilities for sCMOS detectors in global shutter mode and key parameters like PRNU, DSNU, MTF, SNR, Linearity, Spectral Response, Quantum Efficiency, Flatness and Radiation Tolerance will be discussed in detail.

Eckardt, Andreas; Reulke, Ralf; Schwarzer, Horst; Venus, Holger; Neumann, Christian

2013-09-01

456

Integrating silicon photonic interconnects with CMOS: Fabrication to architecture  

NASA Astrophysics Data System (ADS)

While it was for many years the goal of microelectronics to speed up our daily tasks, the focus of today's technological developments is heavily centered on electronic media. Anyone can share their thoughts as text, sound, images or full videos, they can even make phone calls and download full movies on their computers, tablets and phones. The impact of this upsurge in bandwidth is directly on the infrastructure that carries this data. Long distance telecom lines were long ago replaced by optical fibers; now shorter and shorter distance connections have moved to optical transmission to keep up with the bandwidth requirements. Yet microprocessors that make up the switching nodes as well as the endpoints are not only stagnant in terms of processing speed, but also unlikely to continue Moore's transistor-doubling trend for much longer. Silicon photonics stands to make a technical leap in microprocessor technology by allowing monolithic communication speeds between arbitrarily spaced processing elements. The improvement in on-chip communication could reduce power and enable new improvements in this field. This work explores a few aspects involved in making such a leap practical in real life. The first part of the thesis develops process techniques and materials to make silicon photonics truly compatible with CMOS electronics, for two different stack layouts, including a glimpse into multilayerd photonics. Following this is an evaluation of the limitations of integrated devices and a post-fabrication/stabilizing solution using thermal index shifting. In the last parts we explore higher level device design and architecture on the SOI platform.

Sherwood, Nicholas Ramsey

457

Compact CMOS Camera Demonstrator (C3D) for Ukube-1  

NASA Astrophysics Data System (ADS)

The Open University, in collaboration with e2v technologies and XCAM Ltd, have been selected to fly an EO (Earth Observation) technology demonstrator and in-orbit radiation damage characterisation instrument on board the UK Space Agency's UKube-1 pilot Cubesat programme. Cubesat payloads offer a unique opportunity to rapidly build and fly space hardware for minimal cost, providing easy access to the space environment. Based around the e2v 1.3 MPixel 0.18 micron process eye-on-Si CMOS devices, the instrument consists of a radiation characterisation imager as well as a narrow field imager (NFI) and a wide field imager (WFI). The narrow and wide field imagers are expected to achieve resolutions of 25 m and 350 m respectively from a 650 km orbit, providing sufficient swathe width to view the southern UK with the WFI and London with the NFI. The radiation characterisation experiment has been designed to verify and reinforce ground based testing that has been conducted on the e2v eye-on-Si family of devices and includes TEC temperature control circuitry as well as RADFET in-orbit dosimetry. Of particular interest are SEU and SEL effects. The novel instrument design allows for a wide range of capabilities within highly constrained mass, power and space budgets providing a model for future use on similarly constrained missions, such as planetary rovers. Scheduled for launch in December 2011, this 1 year low cost programme should not only provide valuable data and outreach opportunities but also help to prove flight heritage for future missions.

Harriss, R. D.; Holland, A. D.; Barber, S. J.; Karout, S.; Burgon, R.; Dryer, B. J.; Murray, N. J.; Hall, D. J.; Smith, P. H.; Grieg, T.; Tutt, J. H.; Endicott, J.; Jerram, P.; Morris, D.; Robbins, M.; Prevost, V.; Holland, K.

2011-09-01

458

130nm InP DHBTs with ft >0.52THz and fmax >1.1THz M. Urteaga1  

E-print Network

, E. Lobisser2 , M.J.W. Rodwell2 1 Teledyne Scientific Company, Thousand Oaks, CA 93160. 2 Department of ECE, University of California, Santa Barbara, CA 93106. E-mail: murteaga@teledyne-si.com We report

Rodwell, Mark J. W.

459

A Single-Chip 630 GHz Transmitter with 210 GHz Sub-Harmonic PLL Local Oscillator in 130 nm InP HBT  

E-print Network

, chemical/bio sensors, and high-rate data communications. Various THz transceiver building blocks up to 670 , and Mark Rodwell 3 1 Teledyne Scientific Company, Thousand Oaks, CA 91360 USA 2 Jet Propulsion Laboratory the implementation of dense arrays of THz imager/sensor. In this paper, a 630 GHz transmitter IC with integrated sub

Rodwell, Mark J. W.

460

Overview of Commercial Buildings, 2003  

EIA Publications

The Energy Information Administration conducts the Commercial Buildings Energy Consumption Survey (CBECS) to collect information on energy-related building characteristics and types and amounts of energy consumed in commercial buildings in the United States.

2008-01-01

461

Accelerating Commercial Remote Sensing  

NASA Technical Reports Server (NTRS)

Through the Visiting Investigator Program (VIP) at Stennis Space Center, Community Coffee was able to use satellites to forecast coffee crops in Guatemala. Using satellite imagery, the company can produce detailed maps that separate coffee cropland from wild vegetation and show information on the health of specific crops. The data can control coffee prices and eventually may be used to optimize application of fertilizers, pesticides and irrigation. This would result in maximal crop yields, minimal pollution and lower production costs. VIP is a mechanism involving NASA funding designed to accelerate the growth of commercial remote sensing by promoting general awareness and basic training in the technology.

1995-01-01

462

Aerocapacitor commercialization plan  

SciTech Connect

The purpose of the Power-One Aerocapacitor Commercialization Plan is to communicate to members of management and to all employees the overall objectives of the corporation. Power-One, Inc., has participated in a US Federal Government Technology Reinvestment Project (TRP), entitled {open_quotes}Advanced Power Conversion based on the Aerocapacitor{close_quotes}: the project is a group effort, with Lawrence Livermore National Labs, GenCorp/Aerojet, PolyStor Corp. (a start-up company), and Power-One forming the consortium. The expected resulting technology is the {open_quotes}Aerocapacitor{close_quotes}, which possesses much higher performance levels than the usual capacitors on the market today. Power-One hopes to incorporate the Aerocapacitor into some of its products, hence enhancing their performance, as well as market privately-labeled aerocapacitors through its distribution channels. This document describes the details of Power-One`s plan to bring to market and commercialize the Aerocapacitor and Aerocapacitor-based products. This plan was formulated while Power-One was part of the Oerocap project. It has since pulled out of this project. What is presented in this plan is the work which was developed prior to the business decision to terminate this work.

NONE

1995-09-12

463

Commercial Zone Melting Ingots  

NASA Astrophysics Data System (ADS)

Bismuth telluride-based compounds have been extensively utilized for commercial application. However, thermoelectric materials must suffer numerous mechanical vibrations and thermal stresses while in service, making it equally important to discuss the mechanical properties, especially at high temperature. In this study, the compressive and bending strengths of Bi0.5Sb1.5Te3 commercial zone melting (ZM) ingots were investigated at 25, 100, and 200 °C, respectively. Due to the obvious anisotropy of materials prepared by ZM method, the effect of anisotropy on the strengths was also explored. Two-parameter Weibull distribution was employed to fit a series of values acquired by a universal testing machine. And digital speckle photography was applied to record the strain field evolution, providing visual observation of surface strain. The compressive and bending strengths along ZM direction were approximately three times as large as those perpendicular to the ZM direction independent of the temperature, indicating a weak van der Waals bond along the c axis.

Zheng, Yun; Xie, Hongyao; Shu, Shengcheng; Yan, Yonggao; Li, Han; Tang, Xinfeng

2014-06-01

464

Inverter models of CMOS gates for supply current and delay evaluation  

Microsoft Academic Search

The subject of this paper is the reduction of transistor-level models of CMOS logic gates to equivalent inverters, for the purpose of computing the supply current in digital circuits. No restrictions are applied to either the number of switching inputs or the transition times and relative delays of the input voltages. The relative positions of the switching inputs are also

Abdolreza Nabavi-lishi; Nicholas C. Rumin

1994-01-01

465

Comprehensive Analysis and Optimization of CMOS Neural Amplifiers for Wireless Recording  

E-print Network

Comprehensive Analysis and Optimization of CMOS Neural Amplifiers for Wireless Recording Implants, {lihaitao, mason}@msu.edu Abstract--Neural amplifiers play a critical role in the bandwidth, power comprehensive analysis of neural amplifier design to optimize these performance characteristics. Amplifier

Mason, Andrew

466

Design and fabrication of a CMOS-compatible MHP gas sensor  

SciTech Connect

A novel micro-hotplate (MHP) gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO{sub 2} film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ?19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3%) in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.

Li, Ying; Yu, Jun, E-mail: junyu@dlut.edu.cn; Wu, Hao; Tang, Zhenan [College of Electronic Science and Technology, Dalian University of Technology, Dalian 116024 (China)] [College of Electronic Science and Technology, Dalian University of Technology, Dalian 116024 (China)

2014-03-15

467

A 512×512 CMOS Monolithic Active Pixel Sensor with integrated ADCs for space science  

Microsoft Academic Search

In the last few years, CMOS sensors have become widely used for consumer applications, but little has been done for scientific instruments. In this paper we present the design and experimental characterisation of a Monolithic Active Pixel Sensor (MAPS) intended for a space science application. The sensor incorporates a 525×525 array of pixels on a 25?m pitch. Each pixel contains

M. L Prydderch; N. J Waltham; R. Turchetta; M. J French; R. Holt; A. Marshall; D. Burt; R. Bell; P. Pool; C. Eyles; H. Mapson-Menard

2003-01-01

468

III-V/Ge Channel Engineering for Future CMOS M. A. Wisteya,b  

E-print Network

field effect transistors (MOSFETs) because current flows along the surface of the semiconductor. However replaced by high-k gate dielectrics such as HfO2 in CMOS field effect transistors. The higher dielectric, and straightforward heterostructure confinement for vertical scaling, and additional degrees of freedom in composition

Rodwell, Mark J. W.

469

The use of light emission in failure analysis of CMOS ICs  

SciTech Connect

The use of photon emission for analyzing failure mechanisms and defects in CMOS ICs is presented. Techniques are given for accurate identification and spatial localization of failure mechanisms and physical defects, including defects such as short and open circuits which do not themselves emit photons.

Hawkins, C.F. (New Mexico Univ., Albuquerque, NM (USA). Dept. of Electrical and Computer Engineering); Soden, J.M.; Cole, E.I. Jr.; Snyder, E.S. (Sandia National Labs., Albuquerque, NM (USA))

1990-01-01

470

Micropower, 150mA Low-Noise Ultra Low-Dropout CMOS Voltage Regulator  

E-print Network

indicate micro SMD package. * Optional Noise Reduction Capacitor. August 2005 LP3985Micropower,150mALow-NoiseUltraLP3985 Micropower, 150mA Low-Noise Ultra Low-Dropout CMOS Voltage Regulator General Description requirements. The LP3985 is stable with a small 1µF ±30% ceramic or high-quality tantalum output capacitor

Berns, Hans-Gerd

471

High Q CMOS-compatible microwave inductors using double-metal interconnection silicon technology  

Microsoft Academic Search

The authors' aim is to demonstrate the possibility of building high quality factor (Q) integrated inductors in the conventional complementary metal-oxide semiconductor (CMOS) process without any additional processes of previous papers, such as thick gold layer or multilayer interconnection. The comparative analysis is extensively carried out to investigate the detailed variation of Q performance according to inductor shape and substrate

Min Park; Seonghearn Lee; Hyun Kyu Yu; Jin Gun Koo; Kee Soo Nam

1997-01-01

472

An integrated CMOS high voltage supply for lab-on-a-chip systems.  

PubMed

Electrophoresis is a mainstay of lab-on-a-chip (LOC) implementations of molecular biology procedures and is the basis of many medical diagnostics. High voltage (HV) power supplies are necessary in electrophoresis instruments and are a significant part of the overall system cost. This cost of instrumentation is a significant impediment to making LOC technologies more widely available. We believe one approach to overcoming this problem is to use microelectronic technology (complementary metal-oxide semiconductor, CMOS) to generate and control the HV. We present a CMOS-based chip (3 mm x 2.9 mm) that generates high voltages (hundreds of volts), switches HV outputs, and is powered by a 5 V input supply (total power of 28 mW) while being controlled using a standard computer serial interface. Microchip electrophoresis with laser induced fluorescence (LIF) detection is implemented using this HV CMOS chip. With the other advancements made in the LOC community (e.g. micro-fluidic and optical devices), these CMOS chips may ultimately enable 'true' LOC solutions where essentially all the microfluidics, photonics and electronics are on a single chip. PMID:18818808

Behnam, M; Kaigala, G V; Khorasani, M; Marshall, P; Backhouse, C J; Elliott, D G

2008-09-01

473

A novel approach to cost-effective estimate of power dissipation in CMOS ICs  

Microsoft Academic Search

An approach to the estimate of power dissipation in CMOS ICs based on the current limited model of MOS transistors able to accurately evaluate current waveforms for all types of digital circuits is presented. The efficiency of the tool developed is such that ICs with up to 104-105 transistors can be cost-effectively treated without any need of arbitrary partitioning. In

L. Benini; M. Favalli; P. Olivo; B. Ricco

1993-01-01

474

Cite this: Lab Chip, 2013, 13, 3929 Lab-on-CMOS integration of microfluidics and  

E-print Network

Cite this: Lab Chip, 2013, 13, 3929 Lab-on-CMOS integration of microfluidics and electrochemical* and Andrew J. Mason This paper introduces a CMOS­microfluidics integration scheme for electrochemical of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device

Mason, Andrew

475

Real Time CMOS Optical Processor for a Shack Hartmann Wav efront Sensor  

Microsoft Academic Search

A real time VLSI optical centroid processor has been d e- veloped as part of a larger Shack -Hartmann wavefront sensor system for applications in adaptive optics. The i m- plementation of the optical centroid detection system was demonstrated successfully using a hardware emulation system. Subsequently, the d esign has been implemented as a CMOS single -chip solution. This has

Barrie Hayes; Matt Clark; Steve Morgan; Alan Ng

476

X-ray characterization of CMOS imaging detector with high resolution for fluoroscopic imaging application  

NASA Astrophysics Data System (ADS)

This paper introduces complementary metal-oxide semiconductor (CMOS) active pixel sensor (APS)-based X-ray imaging detectors with high spatial resolution for medical imaging application. In this study, our proposed X-ray CMOS imaging sensor has been fabricated by using a 0.35 ?m 1 Poly 4 Metal CMOS process. The pixel size is 100 ?m×100 ?m and the pixel array format is 24×96 pixels, which provide a field-of-view (FOV) of 9.6 mm×2.4 mm. The 14.3-bit extend counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. Both thallium-doped CsI (CsI:Tl) and Gd2O2S:Tb scintillator screens were used as converters for incident X-rays to visible light photons. The optical property and X-ray imaging characterization such as X-ray to light response as a function of incident X-ray exposure dose, spatial resolution and X-ray images of objects were measured under different X-ray energy conditions. The measured results suggest that our developed CMOS-based X-ray imaging detector has the potential for fluoroscopic imaging and cone-beam computed tomography (CBCT) imaging applications.

Cha, Bo Kyung; Kim, Cho Rong; Jeon, Seongchae; Kim, Ryun Kyung; Seo, Chang-Woo; Yang, Keedong; Heo, Duchang; Lee, Tae-Bum; Shin, Min-Seok; Kim, Jong-Boo; Kwon, Oh-Kyung

2013-12-01

477

Design and characterization of a signal insulation coreless transformer integrated in a CMOS gate driver chip  

E-print Network

Design and characterization of a signal insulation coreless transformer integrated in a CMOS gate the implementation of numerous distinct power transistor gate drivers, the control signal insulation is becoming more results will be shown in order to validate the functionality. I. INTRODUCTION An insulation system

Paris-Sud XI, Université de

478

Power distribution system design methodology and capacitor selection for modern CMOS technology  

Microsoft Academic Search

Power systems for modern complementary metal-oxide-semiconductor (CMOS) technology are becoming harder to design. One design methodology is to identify a target impedance to be met across a broad frequency range and specify components to meet that impedance. The impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic

Larry D. Smith; Raymond E. Anderson; Douglas W. Forehand; Thomas J. Pelc; Tanmoy Roy

1999-01-01

479

Bulk CMOS Device Optimization for High-Speed and Ultra-Low Power Operations  

E-print Network

MOSFET (DTMOS) [5], multi- threshold CMOS (MTCMOS) [6], and swapped body biasing (SBB) [7] just to name. In addition body biasing techniques that could facilitate bridging the speed gap are presented. Device sizing subthreshold and super-threshold circuits, a novel body biasing technique termed tunable body biasing (TBB

Nyathi, Jabulani

480

SI-BASED UNRELEASED HYBRID MEMS-CMOS RESONATORS IN 32NM TECHNOLOGY  

E-print Network

body. FET sensing using the high , high performance transistors in CMOS amplifies the mechanical signal monolithic integration have been motivated primarily by improved size, weight and power (SWaP), reduced it difficult to detect RF and mm-wave signals. The authors have previously demonstrated the Resonant Body

Williams, Brian C.

481

Page 1 of 20 Catalyst preparation for CMOS-compatible silicon  

E-print Network

-11 . Gold has been the historic catalyst1 for silicon nanowire synthesis as it allows excellent yieldsPage 1 of 20 Catalyst preparation for CMOS-compatible silicon nanowire synthesis Vincent T. Renard (complementary metal oxide semiconductor) fabrication processes. Nanowire synthesis with those metals which

Paris-Sud XI, Université de

482

A Study on Differential Type Monostable Multivibrator Using CMOS-XOR/XNOR Gate  

NASA Astrophysics Data System (ADS)

In the differential type monostabel multivibirator using CMOS-XOR/XNOR gates, there is a circuit configuration that the operation of two elements becomes the same in stable sate and the metastable state. And, these circuits has the up mode and down mode operations. Furthermore, the metastable state is not influenced trigger repetition rate, and it is shown by a simple formula expression.

Sasaki, Hirotoshi; Julsereewong, Amphawan; Isoguchi, Hiroshi; Yahara, Mitsutoshi; Fujimoto, Kuniaki; Sasaki, Hirofumi

483

Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks  

NASA Technical Reports Server (NTRS)

The objective of this work is to design and develop Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks. We briefly report on the accomplishments in this work. We also list the impact of this work on graduate student research training/involvement.

Dogan, Numan S.

2003-01-01

484

CMOS-compatible, athermal silicon ring modulators clad with titanium dioxide  

E-print Network

CMOS-compatible, athermal silicon ring modulators clad with titanium dioxide Stevan S. Djordjevic,1-optic contribution with that from the amorphous titanium dioxide (a-TiO2) overcladding with a negative thermo-compatible Titanium Dioxide Deposition for Athermalization of Silicon Waveguides," accepted for publication

Yoo, S. J. Ben

485

Integrated Inductors for RF Transmitters in CMOS/MEMS Smart Microsensor Systems  

PubMed Central

This paper presents the integration of an inductor by complementary metal-oxide-semiconductor (CMOS) compatible processes for integrated smart microsensor systems that have been developed to monitor the motion and vital signs of humans in various environments. Integration of radio frequency transmitter (RF) technology with complementary metal-oxide-semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize the wireless smart microsensors system. The essential RF components such as a voltage controlled RF-CMOS oscillator (VCO), spiral inductors for an LC resonator and an integrated antenna have been fabricated and evaluated experimentally. The fabricated RF transmitter and integrated antenna were packaged with subminiature series A (SMA) connectors, respectively. For the impedance (50 ?) matching, a bonding wire type inductor was developed. In this paper, the design and fabrication of the bonding wire inductor for impedance matching is described. Integrated techniques for the RF transmitter by CMOS compatible processes have been successfully developed. After matching by inserting the bonding wire inductor between the on-chip integrated antenna and the VCO output, the measured emission power at distance of 5 m from RF transmitter was -37 dBm (0.2 ?W).

Kim, Jong-Wan; Takao, Hidekuni; Sawada, Kazuaki; Ishida, Makoto

2007-01-01

486

The impact of RTN on performance fluctuation in CMOS logic circuits  

Microsoft Academic Search

In this paper, the impact of Random Telegraph Noise (RTN) on CMOS logic circuits observed in a Circuit Matrix Array is reported. We discuss the behavior of RTN under circuit operation, and reveal that the impact of RTN, which is much smaller than that of within-die variation in a 65nm process, can have a severe effect on the performance of

Kyosuke Ito; Takashi Matsumoto; Shinichi Nishizawa; Hiroki Sunagawa; Kazutoshi Kobayashi; Hidetoshi Onodera

2011-01-01

487

Ka-Band, RF MEMS Switches on CMOS Grade Silicon with a Polyimide Interface Layer  

NASA Technical Reports Server (NTRS)

For the first time, RF MEMS switcbes on CMOS grade Si witb a polyimide interface layer are fabricated and characterized. At Ka-Band (36.6 GHz), an insertion loss of 0.52 dB and an isolation of 20 dB is obtained.

Ponchak, George E.; Varaljay, Nicholas C.; Papapolymerou, John

2003-01-01

488

Few Graphene layer/Carbon-Nanotube composite Grown at CMOS-compatible Temperature  

E-print Network

method to produce CNT/graphene hybrid sys- tems. Here, we show that such composite is composed of CNTsFew Graphene layer/Carbon-Nanotube composite Grown at CMOS-compatible Temperature V. Jousseaume1 capped by few graphene layers. We show that the carbon nanotubes grow epitaxially under the few graphene

Paris-Sud XI, Université de

489

A fully integrated 60GHz distributed transformer power amplifier in bulky CMOS 45nm  

Microsoft Academic Search

This paper describes a fully integrated differential power amplifier (PA) operating at 60 GHz ISM band and implemented in 45nm CMOS technology. The PA is based on a distributed active transformer (DAT) topology which enables simultaneous power combining and realization of an efficient impedance matching. To cope with the asymmetric nature of DAT, resulting in common-mode and unequal differential voltage-

Jaap Essing; Reza Mahmoudi; Yu Pei; Arthur van Roermund

2011-01-01

490

1.25Gb\\/s Regulated Cascode CMOS Transimpedance Amplifier for Gigabit Ethernet Applications  

Microsoft Academic Search

A transimpedance amplifier (TIA) has been realized in a 0.6- m digital CMOS technology for Gigabit Ethernet applications. The amplifier exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capac- itance including photodiode capacitance from the

Hoi-Jun Yoo; H.-J. Yoo

2004-01-01

491

Polymer Mass Loading of CMOS\\/MEMS Microslot Cantilever for Gravimetric Sensing  

Microsoft Academic Search

A post CMOS\\/MEMS fabrication method using inkjet printing of mass sensitive polymer into slotted microcantilevers is explored with the goal of increasing the polymer to cantilever mass ratio. This method involves wicking the dissolved polymer, poly(butyl methacrylate) (PBMA), into a microslot cantilever via a capillary slot running its length using surface tension forces. This is done by jetting into a

Sarah S. Bedair; Gary K. Fedder

2007-01-01

492

On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz  

NASA Technical Reports Server (NTRS)

The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.

Samoska, Lorene; Man Fung, King; Gaier, Todd; Huang, Daquan; Larocca, Tim; Chang, M. F.; Campbell, Richard; Andrews, Michael

2008-01-01

493

Membrane Protein Biosensor with Multi-Channel CMOS Impedance Extractor and Digitizer  

E-print Network

Membrane Protein Biosensor with Multi-Channel CMOS Impedance Extractor and Digitizer Chao Yang the development of biosensor arrays that harness the unique sensitivity and selectivity of membrane proteins frequency spectrum. This paper described the design and characterization of a biosensor array microsystem

Mason, Andrew

494

A high speed and low power CMOS current comparator for photon counting systems  

Microsoft Academic Search

In this paper a CMOS current comparator for a photon count- ing system is proposed. The device can be used in satellite ac- quisition systems for UV free space studies. The circuit features a 4 bit programmable threshold, to avoid wrong counting due to the dark current of the detector and a four bits counter, to perform a post acquisition

Fausto Borghetti; Lorenzo Farina; Piero Malcovati; Franco Maloberti

2004-01-01

495

9-11 April 2008 Integrated RF MEMS/CMOS Devices  

E-print Network

the dc tuning voltage exceeds the pull-in voltage, and the top plate snaps down on the bottom plate, smaller size and zero dc power consumption using electrostatic actuation mechanism. The CMOS-MEMS post. Three maskless post-processing steps are required to construct the tunable capacitors. They also include

Paris-Sud XI, Université de

496

Integrated micro- and nano-optical biosensor silicon devices CMOS compatible  

Microsoft Academic Search

We show the design, fabrication and testing of micro\\/nanobiosensor devices based on optical waveguides in a highly sensitive interferometric configuration and by using evanescent wave detection. The devices are fabricated by standard Silicon CMOS microelectronics technology after a precise design for achieving a high sensitivity for biosensing applications. Two integrated Mach-Zehnder interferometric (MZI) devices, using two technologies, have been developed:

Laura M. Lechuga; Borja Sepulveda; Jose Sanchez del Rio; Francisco Blanco; Ana Calle; Carlos Dominguez

2004-01-01

497

Integrated micro- and nano-optical biosensor Silicon devices CMOS compatible  

Microsoft Academic Search

We show the design, fabrication and testing of micro\\/nanobiosensor devices based on optical waveguides in a highly sensitive interferometric configuration and by using evanescent wave detection. The devices are fabricated by standard Silicon CMOS microelectronics technology after a precise design for achieving a high sensitivity for biosensing applications. Two integrated Mach-Zehnder interferometric (MZI) devices, using two technologies, have been developed:

L. M. Lechuga; B. Sepúlveda; J. Sánchez del Río; F. Blanco; A. Calle; C. Domínguez

498

New input\\/output designs for high speed static CMOS RAM  

Microsoft Academic Search

New input and output schematics and optimum design for cell and array are proposed, and applied to a 256×4 bit CMOS static RAM. Simplified decoder circuit with effective decoder control circuit has a high speed and a wide timing margin. Simple sense amplifier and compact output circuit bring higher speed and reduction in pattern area. Using p-channel transfer gate for

MASAHIRO AKIYA; MAMORU OHARA

1979-01-01

499

A compact CMOS biochip immunosensor towards the detection of a single bacteria  

Microsoft Academic Search

Recent use of biological warfare (BW) agents has led to a growing interest in the rapid and sensitive detection of pathogens. Therefore, the development of field-usable detection devices for sensitive and selective detection of BW agents is an important issue. In this work, we report a portable biochip system based on complementary metal oxide semiconductor (CMOS) technology that has great

Joon Myong Song; Mustafa Culha; Paul M. Kasili; Guy D. Griffin; Tuan Vo-Dinh

2005-01-01

500

Gamma radiation damage study of 0.18 µm process CMOS image sensors  

NASA Astrophysics Data System (ADS)

A 0.18 ?m process CMOS image sensor has recently been developed by e2v technologies plc. with a 0.5 megapixel imaging area consisting of 6 × 6 ?m 5T pixels. The sensor is able to provide high performance in a diverse range of applications including machine vision and medical imaging, offering good low-light performance at a video rate of up to 60 fps. The CMOS sensor has desirable characteristics which make it appealing for a number of space applications. Following on from previous tests of the radiation hardness of the image sensors to proton radiation, in which the increase in dark-current and appearance of bright and RTS pixels was quantified, the sensors have now been subjected to a dose of gamma radiation. Knowledge of the performance after irradiation is important to judge suitability for space applications and radiation sensitive medical imaging applications. This knowledge will also enable image correction to mitigate the effects and allow for future CMOS devices to be designed to improve upon the findings in this paper. One device was irradiated to destruction after 120 krad(Si) while biased, and four other devices were irradiated between 5 and 20 krad(Si) while biased. This paper explores the resulting radiation damage effects on the CMOS image sensor such as increased dark current, and a central brightening effect, and discusses the implications for use of the sensor in space applications.

Dryer, Ben; Holland, Andrew; Murray, N. J.; Jerram, Paul; Robbins, Mark; Burt, David

2010-07-01