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1

High density radiation hardened FeRAMs on a 130 nm CMOS\\/FRAM process  

Microsoft Academic Search

Using hardened-by-design techniques previously demonstrated on a 1-kbit prototype 0.35-micron ferroelectric semiconductor memory, an 8-kbit FeRAM memory segment has been designed for fabrication on a Texas Instruments 130nm commercial CMOS\\/FRAM process. The 8-kbit segment can be arrayed to provide radiation hardened ferroelectric memory densities up to 64 Mbit with reasonable chip sizes and radiation hardness vastly superior to that of

David A. Kamp; Alan D. DeVilbiss; Gerald R. Haag; Kirk E. Russell; Gary F. Derbenwick

2005-01-01

2

Optimal design of phase change random access memory based on 130nm CMOS technology  

NASA Astrophysics Data System (ADS)

An 8Mb phase change random access memory (PCRAM) has been developed by a 130nm 4-ML standard CMOS technology based on the Resistor-on-Via-stacked-Plug (RVP) storage cell structure. This phase change resistor is formed after CMOS logic fabrication. PCRAM can be embedded without changing any logic device and process. The memory cell selector is implemented by a standard 1.2V NMOS device. Aimed at the resistance distributions, lowering the operation current and improving the bit yield, some methods are used to optimize the design of the chip.

Cai, Daolin; Chen, Houpeng; Wang, Qian; Hong, Xiao; Chen, Yifeng; Xu, Linhai; Li, Xi; Wang, Zhaomin; Zhang, Yiyun; Song, Zhitang

3

A 12 GHz low-jitter LC-VCO PLL in 130 nm CMOS  

NASA Astrophysics Data System (ADS)

We present a wideband low-jitter LC-VCO phase-locked loop in 130 nm CMOS technology for high speed serial link applications. The PLL covers a 5.6 GHz to 13.4 GHz frequency range by using two LC-VCO cores with an RMS jitter of 370 fs. The single event effects testing is performed with a neutron beam at Los Alamos National Laboratory and no frequency disturbance is found over the test period. The PLL consumes 50.88 mW of power under a 1.2 V power supply.

You, Y.; Chen, J.; Feng, Y.; Tang, Y.; Huang, D.; Rui, W.; Gong, D.; Liu, T.; Ye, J.

2015-03-01

4

Development of front-end electronics for LumiCal detector in CMOS 130 nm technology  

NASA Astrophysics Data System (ADS)

The design and the preliminary measurements results of a multichannel, variable gain front-end electronics for luminosity detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier with pole-zero cancellation circuit and a CR-RC shaper with 50 ns peaking time. The measurements results confirm full functionality of the prototype and compliance with the requirements imposed by the detector specification. The power consumption of the front-end is in the range 0.6–1.5 mW per channel and the noise ENC around 900 e - at 10 pF input capacitance.

Firlej, M.; Fiutowski, T.; Idzik, M.; Moro?, J.; ?wientek, K.; Terlecki, P.

2015-01-01

5

Development of scalable frequency and power Phase-Locked Loop in 130 nm CMOS technology  

NASA Astrophysics Data System (ADS)

The design and measurements results of a prototype very low power Phase-Locked Loop (PLL) ASIC for applications in readout systems of particle physics detectors are presented. The PLL was fabricated in 130 nm CMOS technology. It was designed and simulated for frequency range 10 MHz-3.5 GHz. Four division factors i.e. 6, 8, 10 and 16 were implemented in the PLL feedback loop. The main PLL block-voltage controlled oscillator (VCO) should work in 16 frequency ranges/modes, switched either manually or automatically. Preliminary measurements done in frequency range 20 MHz-1.6 GHz showed that the ASIC is functional and generates proper clock signal. The automatic VCO mode switching, one of the main design goals, was positively verified. Power consumption of around 0.6 mW was measured at 1 GHz for a division factor equal to 10.

Firlej, M.; Fiutowski, T.; Idzik, M.; Moro?, J.; ?wientek, K.

2014-02-01

6

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS  

Microsoft Academic Search

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The trans- ceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase\\/frequency detector and charge-pump

Robert Bogdan Staszewski; Khurram Muhammad; Dirk Leipold; Chih-Ming Hung; Yo-Chuol Ho; John L. Wallberg; Chan Fernando; Ken Maggio; Roman Staszewski; Tom Jung; Jinseok Koh; Soji John; Irene Yuanying Deng; Vivek Sarda; Oscar Moreira-Tamayo; Valerian Mayega; Ofer Friedman; Oren Eytan Eliezer; Poras T. Balsara; E. de-Obaldia

2004-01-01

7

High-speed short-wavelength silicon photodetectors fabricated in 130-nm CMOS process  

NASA Astrophysics Data System (ADS)

We have integrated several optoelectronic devices into deep-submicron silicon fabrication process. The main results for monolithic integration of silicon planar interdigitated P-I-N photodiodes with transimpedance amplifiers and waveguide grating couplers will be reviewed. The integration process was carried out in an unmodified 130nm CMOS process flow, on SOI substrates. Photodetectors that were fabricated on 200nm-thick SOI exhibited a 3dB electrical bandwidth of 10GHz for -5V bias while the photodetectors fabricated on 2000nm-thick SOI had 8GHz 3dB electrical bandwidth for -28V bias. The external quantum efficiency of the 2000nm-thick photodetectors at 835nm was 14%. The 200nm-thick photodetectors were integrated with waveguide grating couplers. For 835nm, the external quantum efficiency of the photodetector improved from 3% to 12% when a diffraction grating with 265nm period was integrated on top of the photodiode. The 3dB electrical bandwidth of these photodetectors was 4.1GHz (RC limited). The dark current for these devices was 10pA at -3V bias for an area of 2500mm2. The photodetectors fabricated on 2000nm-thick SOI substrates were wire-bonded to SiGe transimpedance amplifiers with 184W transimpedance gain. When the photodiode was used in avalanche operation mode the sensitivity of -7dBm (BER<10-9) was achieved at 10Gb/s. The multiplication gain for the avalanche photodetector was in this case M=4. This is the highest speed reported for an all-silicon optical receiver.

Csutak, Sebastian M.; Schaub, Jeremy D.; Yang, Bo; Campbell, Joe C.

2003-06-01

8

Radiation hardness evaluation of a 130 nm SiGe BiCMOS technology for high energy physics applications  

NASA Astrophysics Data System (ADS)

Final results for a comprehensive radiation hardness evaluation of a high performance, low cost, 130 nm SiGe BiCMOS technology are presented. After a survey of several available SiGe technologies, one was chosen in terms of performance, power consumption, radiation hardness, and cost and it is presented as a suitable technology for the future upgrades of the ATLAS detector of the High Luminosity LHC. Bipolar devices of different sizes and geometries have been evaluated, along with a prototype Front-End readout ASIC designed for binary readout of silicon microstrip detectors. Gamma, neutron and proton irradiations have been performed up to the expected doses and fluences of the experiment.

Díez, S.; Clark, T.; Grillo, A. A.; Kononenko, W.; Martinez-McKinney, F.; Newcomer, F. M.; Norgren, M.; Rescia, S.; Spencer, E.; Spieler, H.; Ullán, M.; Wilder, M.

2013-10-01

9

A 10 Gb/s laser driver in 130 nm CMOS technology for high energy physics applications  

NASA Astrophysics Data System (ADS)

The GigaBit Laser Driver (GBLD) is a key on-detector component of the GigaBit Transceiver (GBT) system at the transmitter side. As part of the design efforts towards the upgrade of the electrical components of the LHC experiments, a 10 Gb/s GBLD (GBLD10) has been developed in a 130 nm CMOS technology. The GBLD10 is based on the distributed-amplifier (DA) architecture and achieves data rates up to 10 Gb/s. It is capable of driving VCSELs with modulation currents up to 12 mA. Moreover, a pre-emphasis function has been included in the proposed laser driver in order to compensate for the capacitive load and channel losses.

Zhang, T.; Tavernier, F.; Moreira, P.; Gui, P.

2015-02-01

10

Design on Power-Rail ESD Clamp Circuit for 3.3-V I\\/O Interface by Using Only 1-V\\/2.5-V Low-Voltage Devices in a 130-nm CMOS Process  

Microsoft Academic Search

A new power-rail electrostatic discharge (ESD) clamp circuit for application in 3.3-V mixed-voltage input-output (I\\/O) interface is proposed and verified in a 130-nm 1-V\\/2.5-V CMOS process. The devices in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage nMOS\\/pMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I\\/O interface applications. A special ESD

Ming-Dou Ker; Wen-Yi Chen; Kuo-Chun Hsu

2006-01-01

11

Charge Signal Processors in a 130 nm CMOS Technology for the Sparse Readout of Small Pitch Monolithic and Hybrid Pixel Sensors  

Microsoft Academic Search

Hybridpixeldetectorsarenowadaysarobustandma- ture technology for particle detection as well as for medical and X-ray imaging, but the demands for improved performance for the next generation high energy physics experiments ask for the development of novel devices. Monolithic CMOS pixels have the potential to provide high granularity thin detectors as the sensor and the readout electronics are integrated in the same substrate.

Gianluca Traversi

2011-01-01

12

The eCDR, a Radiation-Hard 40/80/160/320 Mbit/s CDR with internal VCO frequency calibration and 195 ps programmable phase resolution in 130 nm CMOS  

NASA Astrophysics Data System (ADS)

A clock and data recovery IP, the eCDR, is presented which is intended to be implemented on the detector front-end ASICs that need to communicate with the GBTX by means of e-links. The programmable CDR accepts data at 40, 80, 160 or 320Mbit/s and generates retimed data as well as 40, 80, 160 and 320MHz clocks that are aligned to the retimed data. Moreover, all the outputs have a programmable phase with a resolution of 195ps. An internal calibration mechanism enables the eCDR to lock on incoming data even without the availability of any form of reference clock. The radiation-hard design, integrated in a 130nm CMOS technology, operates at a supply voltage between 1.2V and 1.5V. The power consumption is between 28.5mW and 34.5mW, depending on the settings. The eCDR can achieve a very low RMS jitter below 10ps.

Tavernier, F.; Francisco, R.; Bonacini, S.; Poltorak, K.; Moreira, P.

2013-12-01

13

Development of passive devices in 130 nm RFCMOS technology and PDK implementation for RF VCO designs  

Microsoft Academic Search

This paper focuses on the design of RF component design such as MOSFETs, varactors, capacitors and inductors in SMIC 0.13 ¿m RFCMOS technology. Modeling results of these passives devices and associated PDK are implemented in a 0.13 ¿m RFCMOS VCO design. The RF building block has been fabricated from 130 nm CMOS technology and achieved a phase noise of -140.8

Xinzhong Duo; Tinghuang Lee; Paul Wen; Lindsay Kang; Tweeg Chen; Paul Zhu; Li-Wu Yang

2008-01-01

14

Micromachined thermal radiation emitter from a commercial CMOS process  

Microsoft Academic Search

Fabrication of thermally isolated micromechanical structures capable of generating thermal radiation for dynamic thermal scene simulation (DTSS) is described. Complete compatibility with a commercial CMOS process is achieved through design of a novel, but acceptable, layout for implementation by the CMOS foundry using its regular process sequence. Following commercial production and delivery of the CMOS chips, a single maskless etch

M. Parameswaran; Alexander M. Robinson; David L. Blackburn; Michael Gaitan; Jon Geist

1991-01-01

15

Tests of commercial colour CMOS cameras for astronomical applications  

NASA Astrophysics Data System (ADS)

We present some results of testing commercial colour CMOS cameras for astronomical applications. Colour CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in colour CMOS sensors is close to the astronomical Johnson BVR system. The basic camera characteristics: read noise (e^{-}/pix), thermal noise (e^{-}/pix/sec) and electronic gain (e^{-}/ADU) for the commercial digital camera Canon 5D MarkIII are presented. We give the same characteristics for the scientific high performance cooled CCD camera system ALTA E47. Comparing results for tests of Canon 5D MarkIII and CCD ALTA E47 show that present-day commercial colour CMOS cameras can seriously compete with the scientific CCD cameras in deep astronomical imaging.

Pokhvala, S. M.; Reshetnyk, V. M.; Zhilyaev, B. E.

2013-12-01

16

A Commercial 65 nm CMOS Technology for Space Applications: Heavy Ion, Proton and Gamma Test Results and Modeling  

Microsoft Academic Search

This paper presents new experimental and modeling evidences that advanced commercial CMOS technologies get intrinsically harder against space radiations with technology downscaling. A 65 nm commercial bulk CMOS process can deliver improved radiation-tolerance without sacrificing electrical performance.

Philippe Roche; Gilles Gasiot; Slawosz Uznanski; Jean-Marc Daveau; Josep Torras-Flaquer; Sylvain Clerc; Reno Harboe-Sorensen

2010-01-01

17

Embedded ferroelectric memory using a 130-nm 5 metal layer Cu \\/ FSG logic process  

Microsoft Academic Search

An embedded ferroelectric memory (FRAM) has been developed using a 1.5V, 130nm 5 metal layer Cu \\/ FSG logic process. The only modification to the logic process was the addition of a ferroelectric process consisting of two additional masks (FECAP, VIA0) immediately before MET1. The ferroelectric was 70nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The bit distribution

S. Summerfelt; S. Aggarwal; K. Boku; F. Celii; L. Hall; L. Matz; S. Martin; H. McAdams; K. Remack; J. Rodriguez; K. Taylor; K. R. Udayakumar; T. Moise; R. Bailey; M. Depner; G. Fox; J. Eliason

2004-01-01

18

Lifetime studies of 130nm nMOS transistors intended for long-duration, cryogenic high-energy physics experiments.  

SciTech Connect

Future neutrino physics experiments intend to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. To increase performance, integrated readout electronics should work inside the cryostat. Due to the scale and cost associated with evacuating and filling the cryostat, the electronics will be unserviceable for the duration of the experiment. Therefore, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is via hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130nm nMOS transistors operating at cryogenic temperatures are investigated. The results show that the difference in lifetime for room temperature operation and cryogenic operation for this process are not great and the lifetimes at both 300K and at 77K can be projected to more than 20 years at the nominal voltage (1.5V) for this technology.

Hoff, J.R.; /Fermilab; Arora, R.; Cressler, J.D.; /Georgia Tech; Deptuch, G.W.; /Fermilab; Gui, P.; /Southern Methodist U.; Lourenco, N.E.; /Georgia Tech; Wu, G.; /Southern Methodist U.; Yarema, R.J.; /Fermilab

2011-12-01

19

Improved gate process control at the 130-nm node using spectroscopic-ellipsometry-based profile metrology  

NASA Astrophysics Data System (ADS)

The ability to control the cross-sectional profile of polysilicon gate structures on semiconductor devices is paramount to maximize product yield and transistor performance. Tighter control of gate profile parameters leads to a tighter distribution of transistor speeds, resulting in more optimized and consistent device performance. Furthermore, the ability to correlate physical in-line profile measurements taken at gate patterning process steps, to back-end-of-line device parametric test results, enables semiconductor manufacturers to minimize the cost per good die produced, by accurately screening out-of-spec product early in the process flow. The significant increase in the number of chips on today's 300mm wafers heightens the importance of obtaining reliable in-line data. In addition, the reduction of design rules to 130nm and below is driving precision requirements on metrology to <1nm, in order to maintain acceptable precision-to-tolerance (P/T) ratios. Historical methods of in-line metrology (Low Voltage Scanning Electron Microscopy, Atomic Force Microscopy, Electrical Critical Dimension Measurement) all face limitations with regards to precision, correlation, or throughput. This paper will demonstrate the use of Spectroscopic Ellipsometry to provide fast, accurate, and precise two-dimensional profile information on polysilicon gate structures. This metrology technique is currently being utilized for in-line process control and product disposition, at the gate lithography and etch process steps, on 130nm generation logic devices manufactured in Texas Instruments' DMOS 6 300mm wafer fabrication facility. A brief description of the measurement theory and gate profile measurement solution for both dense and isolated structures will be given. This will be followed by data generated from DMOS 6 production material. Using Spectroscopic Ellipsometry, precision results of <0.5nm for CD and height, and <0.25 degrees for profile sidewall angle were obtained at both the lithography and etch measurement steps. The use of CD and sidewall angle information in an APC loop to improve control over the gate trim etch process will also be discussed. Data will be presented showing univariate and multivariate correlation of gate etch profile parameters to post-metalization transistor drive current (IDrive) that is equivalent or superior to existing metrology techniques. Finally, examples of where Spectroscopic Ellipsometry has both increased sensitivity and shortened response time to gate etch process excursions will be presented.

Hodges, J. Scott; Lin, Yu-Lun C.; Burrows, Dale R.; Chiao, Ray H.; Peters, Robert M.; Rangarajan, Srinivasan; Bhatia, Kamal N.; Lakkapragada, Suresh

2003-05-01

20

Packaging commercial CMOS chips for lab on a chip integration.  

PubMed

Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems. PMID:24682025

Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

2014-05-21

21

A 64 Mbit embedded FeRAM utilizing a 130 nm, 5LM Cu\\/FSG logic process  

Microsoft Academic Search

A low-voltage (1.3V), 64 Mbit Ferroelectric Random Access Memory using a 1-transistor, 1-capacitor (1T1C) cell is demonstrated. This is the largest FRAM memory demonstrated to date. The memory is constructed using a state-of-the-art 130 nm transistor and a five-level Cu\\/FSG interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate oxide, low-voltage logic

H. McAdams; R. Acklin; T. Blake; J. Fong; D. Liu; S. Madan; T. Moise; S. Natarajan; N. Qian; Y. Qui; J. Roscher; A. Seshadri; S. Summerfelt; X. Du; J. Eliason; W. Kraus; R. Lanham; F. Li; C. Pietrzyk; J. Rickes

2003-01-01

22

Radiation-enhanced gate-induced-drain-leakage current in the 130 nm partially-depleted SOI pMOSFET  

NASA Astrophysics Data System (ADS)

The total ionizing dose (TID) effect of the pMOSFET from 130 nm partially-depleted silicon-on-insulator (PDSOI) is investigated. The data obtained from 60Co ?-ray irradiation experiments indicate that input/output (I/O) device is more susceptible to TID effect than the core device. An anomalous off-state leakage increase is observed for I/O pMOSFET when drain is biased at a high voltage after irradiation. It is proved that this radiation-induced leakage relates to the enhanced gate-induce-drain-leakage (GIDL). Both the radiation-induced interface traps at the gate-oxide/body interface and the oxide trapped charges in the buried oxide (BOX) are responsible for the growth of the leakage current. These conclusions are also verified by the TCAD simulations. The isothermal annealing can recover the leakage current to the pre-irradiation level.

Peng, Chao; Hu, Zhiyuan; Ning, Bingxu; Dai, Lihua; Bi, Dawei; Zhang, Zhengxuan

2015-04-01

23

Commercial CMOS image sensors as X-ray imagers and particle beam monitors  

NASA Astrophysics Data System (ADS)

CMOS image sensors are widely used in several applications such as mobile handsets webcams and digital cameras among others. Furthermore they are available across a wide range of resolutions with excellent spectral and chromatic responses. In order to fulfill the need of cheap systems as beam monitors and high resolution image sensors for scientific applications we exploited the possibility of using commercial CMOS image sensors as X-rays and proton detectors. Two different sensors have been mounted and tested. An Aptina MT9v034, featuring 752 × 480 pixels, 6?m × 6?m pixel size has been mounted and successfully tested as bi-dimensional beam profile monitor, able to take pictures of the incoming proton bunches at the DeFEL beamline (1–6 MeV pulsed proton beam) of the LaBeC of INFN in Florence. The naked sensor is able to successfully detect the interactions of the single protons. The sensor point-spread-function (PSF) has been qualified with 1MeV protons and is equal to one pixel (6 mm) r.m.s. in both directions. A second sensor MT9M032, featuring 1472 × 1096 pixels, 2.2 × 2.2 ?m pixel size has been mounted on a dedicated board as high-resolution imager to be used in X-ray imaging experiments with table-top generators. In order to ease and simplify the data transfer and the image acquisition the system is controlled by a dedicated micro-processor board (DM3730 1GHz SoC ARM Cortex-A8) on which a modified LINUX kernel has been implemented. The paper presents the architecture of the sensor systems and the results of the experimental measurements.

Castoldi, A.; Guazzoni, C.; Maffessanti, S.; Montemurro, G. V.; Carraresi, L.

2015-01-01

24

Investigating the degradation mechanisms caused by the TID effects in 130 nm PDSOI I/O NMOS  

NASA Astrophysics Data System (ADS)

This paper evaluates the radiation responses of 3.3 V I/O NMOSFETs from 130 nm partially-depleted silicon-on-insulator (PDSOI) technology. The data obtained from 60Co ionizing radiation experiments indicate that charge trapped in the shallow trench isolation, particularly at the bottom region of the trench oxide, should be the dominant contributor to the off-state drain-to-source leakage current under ON bias. The body doping profile and device dimension are two key factors affecting the performance degradation of the PDSOI transistors after radiation. Significant front gate threshold voltage shift is observed in the T-shape gate device, which is well known as the Radiation Induced Narrow Channel Effect (RINCE). The charge trapped in the buried oxide can induce large threshold voltage shift in the front gate transistor through coupling effect in the low body doping device. The coupling effect is evaluated through three-dimensional simulation. A degradation of the carrier mobility which relates to shallow trench isolation (STI) oxide trapped charge in the narrow channel device is also discussed.

Peng, Chao; Hu, Zhiyuan; Zhang, Zhengxuan; Huang, Huixiang; Ning, Bingxu; Bi, Dawei

2014-06-01

25

Shallow-trench-isolation bounded single-photon avalanche diodes in commercial deep submicron CMOS technologies  

NASA Astrophysics Data System (ADS)

This dissertation describes the first single-photon detection device to be manufactured in a commercial deep-submicron CMOS technology. It also describes novel self-timed peripheral circuits which optimize the performance of the new device. An extension of the new device for dual-color single-photon detection is investigated. Finally, an area- and power-efficient method for single-photon frequency upconversion is presented, analyzed, and experimentally examined. Single-photon avalanche diodes have been used in diverse applications, including three-dimensional laser radar, three-dimensional facial mapping, fluorescence-correlation techniques and time-domain tomography. Due to the high electric fields which these devices must sustain, they have traditionally been manufactured in custom processes, severely limiting their speed and the ability to integrate them in high-resolution imagers. By utilizing a process module originally designed to enhance the performance of CMOS transistors, we achieve highly planar junctions in an area-efficient manner. This results in SPADs exhibiting high fill factors, small pitch and ultrafast operation. Device miniaturization is accompanied by excessive noise, which was shown to emanate from trapped avalanche charges. Due to the fast recharging of the device, these charges are released in a subsequent charged phase of the device, causing correlated after-pulses. We present electrostatic and electrical simulation results, as well as a comprehensive characterization of the new device. We also show for the first time that by utilizing the two junctions included in the device, we can selectively detect photons of different wavelengths in the same pixel, as is desirable in cross-correlation experiments. This dissertation also describes an efficient new method for single-photon frequency upconversion. This is desirable for applications including quantum-key distribution and high-resolution near-infrared imaging. The new technique is based on electroluminescence in or near the multiplication region of the device, resulting from hot-carrier recombination. We model a proposed hybrid device and deduce the critical parameters for efficient upconversion. Lastly, we experimentally demonstrate that the electroluminescence yield from an InGaAs/InAlAs avalanche diode is sufficient for highly-efficient upconversion.

Finkelstein, Hod

26

Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu\\/FSG logic process  

Microsoft Academic Search

We demonstrate the bit functionality of a low-voltage, embedded ferroelectric random-access memory constructed using a 130 nm gate and five-level Cu\\/FSG interconnect process. By inserting the two additional masks required for the eFRAM module into this logic flow, we have co-integrated ferroelectric memory and SRAM on a single wafer.

T. S. Moise; S. R. Summerfelt; H. McAdams; S. Aggarwal; K. R. Udayakumar; F. G. Celii; J. S. Martin; G. Xing; L. Hall; K. J. Taylor; T. Hurd; J. Rodriguez; K. Remack; M. D. Khan; K. Boku; G. Stacey; M. Yao; M. G. Albrecht; E. Zielinski; M. Thakre; S. Kuchimanchi; A. Thomas; B. McKee; J. Rickes; A. Wang; J. Grace; J. Fong; D. Lee; C. Pietrzyk; R. Lanham; S. R. Gilbert; D. Taylor; J. Amano; R. Bailey; F. Chu; G. Fox; S. Sun; T. Davenport

2002-01-01

27

High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments  

NASA Astrophysics Data System (ADS)

High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 1015 neq/cm2, nearly 100% detection efficiency and a spatial resolution of about 3 ?m were demonstrated. Since 2011 the HV detectors have first applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process.

Peri?, Ivan; Fischer, Peter; Kreidl, Christian; Hanh Nguyen, Hong; Augustin, Heiko; Berger, Niklaus; Kiehn, Moritz; Perrevoort, Ann-Kathrin; Schöning, André; Wiedner, Dirk; Feigl, Simon; Heim, Timon; Meng, Lingxin; Münstermann, Daniel; Benoit, Mathieu; Dannheim, Dominik; Bompard, Frederic; Breugnon, Patrick; Clemens, Jean-Claude; Fougeron, Denis; Liu, Jian; Pangaud, Patrick; Rozanov, Alexandre; Barbero, Marlon; Backhaus, Malte; Hügging, Fabian; Krüger, Hans; Lütticke, Florian; Mariñas, Carlos; Obermann, Theresa; Garcia-Sciveres, Maurice; Schwenker, Benjamin; Dierlamm, Alexander; La Rosa, Alessandro; Miucci, Antonio

2013-12-01

28

An Acetone Microsensor with a Ring Oscillator Circuit Fabricated Using the Commercial 0.18 ?m CMOS Process  

PubMed Central

This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is ?-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the ?-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm. PMID:25036331

Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

2014-01-01

29

Radiation Characteristics of a 0.11 Micrometer Modified Commercial CMOS Process  

NASA Technical Reports Server (NTRS)

We present radiation data, Total Ionizing Dose and Single Event Effects, on the LSI Logic 0.11 micron commercial process and two modified versions of this process. Modified versions include a buried layer to guarantee Single Event Latchup immunity.

Poivey, Christian; Kim, Hak; Berg, Melanie D.; Forney, Jim; Seidleck, Christina; Vilchis, Miguel A.; Phan, Anthony; Irwin, Tim; LaBel, Kenneth A.; Saigusa, Rajan K.; Mirabedini, Mohammad R.; Finlinson, Rick; Suvkhanov, Agajan; Hornback, Verne; Sung, Jun; Tung, Jeffrey

2006-01-01

30

Development of a Radiation Tolerant 2.0 V standard cell library using a commercial deep submicron CMOS technology for the LHC experiments  

Microsoft Academic Search

A standard cell library was developed using a commercial 0.24 µm, 2.5 V CMOS technology. Radiation tolerant design techniques have been employed on the layout of the cells to achieve the total dose hardness levels required by LHC experiments. The library consists of digital core cell elements as well as a number of I\\/O pad cells. Additionally, it includes a

K. Kloukinas; F. Faccio; A. Marchioro; P. Moreira

31

Color recognition sensor in standard CMOS technology  

NASA Astrophysics Data System (ADS)

Two integrated color detectors are presented as a solution for low cost color sensing applications. The color detection is based on lateral carrier diffusion and wavelength-dependent absorption-depth. The proposed detectors are implemented in a standard 130 nm CMOS technology without process modification or color filters. Three independent output signals are obtained with spectral responsivities optimized to short, middle and long wavelengths. R, G, B or X, Y, Z standard color representation can be realized by a linear transformation of the output signals.

Batistell, Graciele; Zhang, Vincent Chi; Sturm, Johannes

2014-12-01

32

Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications  

NASA Technical Reports Server (NTRS)

JPL, under sponsorship from the NASA Office of Advanced Concepts and Technology, has been developing a second-generation solid-state image sensor technology. Charge-coupled devices (CCD) are a well-established first generation image sensor technology. For both commercial and NASA applications, CCDs have numerous shortcomings. In response, the active pixel sensor (APS) technology has been under research. The major advantages of APS technology are the ability to integrate on-chip timing, control, signal-processing and analog-to-digital converter functions, reduced sensitivity to radiation effects, low power operation, and random access readout.

Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Staller, C.; Zhou, Z; Fossum, E.

1994-01-01

33

Visible and ultraviolet /800-130 nm/ extinction of vapor-condensed silicate, carbon, and silicon carbide smokes and the interstellar extinction curve  

NASA Technical Reports Server (NTRS)

The extinction curves from 800 to 130 nm (1.25-7.7/micron) of amorphous silicate smokes nominally of olivine and pyroxene composition, carbon smokes, and crystalline SiC smokes are presented. The SiC smoke occurred in the low-temperature (beta) cubic structural form. The SiC smoke showed an absorption edge which occurred at significantly longer wavelengths than the calculated extinction profile of the hexagonal SiC form previously used to calculate the interstellar extinction profile. Neither SiC nor amorphous silicates show an extinction band similar to the observed 6.6/micron astronomical extinction band. The infrared absorption peaks for the silicate and SiC samples near 10 microns and 11-13 microns, respectively, were also measured. The ultraviolet to infrared extinction ratio for the amorphous silicate samples is similar to the observed astronomical extinction ratio. The measured extinction ratios for SiC smokes are significantly below the interstellar extinction ratio. The extinction peak of the carbon smokes occurred at 4.0 and 4.25/micron, for samples of mean radii 13 and 6 nm, respectively. The extinction profile is distinctly different from that predicted for graphite grains of the same size, and is similar to that predicted for glassy carbon grains.

Stephens, J. R.

1980-01-01

34

A Fully-Integrated Quad-Band GSM\\/GPRS CMOS Power Amplifier  

Microsoft Academic Search

Concentric distributed active transformers (DAT) are used to implement a fully-integrated quad-band power amplifier (PA) in a standard 130 nm CMOS process. The DAT enables the power amplifier to integrate the input and output matching networks on the same silicon die. The PA integrates on-chip closed- loop power control and operates under supply voltages from 2.9 V to 5.5 V

Ichiro Aoki; Scott Kee; Rahul Magoon; Roberto Aparicio; Florian Bohn; Jeff Zachan; Geoff Hatcher; Donald McClymont; Ali Hajimiri

2008-01-01

35

Aerial image degradation effects due to imperfect sidewall profiles of EAPSM mask for 130-nm device node: 3D EMF simulations and wafer printing results  

NASA Astrophysics Data System (ADS)

As our chip producing industry gearing up for mass production of 130nm device technology node, use of EAPSM (Embedded Attenuated Phase Shift Mask) technology in the critical pattern levels became unavoidable because of the low k1 factor lithography involved. However, this 2-layer EAPSM material (attenuator material covered with Chrome) requires two distinctively separate lithography/etch processes needed to be carried out. These added complexities of processes are prone to degradation of the absorber material's (MoSi) sidewall leading to imperfect sidewall profiles (top corner rounding, off-normal sidewall angle, etching intrusion into quartz substrate, footing, . . . etc.). These imperfections of sidewall cause aerial image degradations thus reduce effectiveness of full benefits of PSM technology. In this paper, we discuss our findings of mask level aerial image degradation dependency on EAPSM material sidewall imperfections, which result from immature mask making processes, and assessments of its effects on pattern transfer onto wafer level using 3&2D EMF and subsequent lithography simulations. The results were then, compared to actual wafer results for the wafer level printing confirmation to the simulation results. We distinguish consequence of resulting aerial image differences between EMF simulations vs. Kirchhoff approximation (treatment of absorber to be infinitely thin layer; normally used in conventional lithography simulations) in the KrF EAPSM material (MoSi). Furthermore, we have carried out look-ahead assessments for ArF (193nm) lithography using ArF EAPSM material (MoSiON) and made association between the sidewall profile variations and CD uniformity performance of EAPSM. We will make case that 3D EMF capability consideration is important in the low k1 factor lithography simulations.

Kim, Won D.; Rathsack, Benjamen M.

2002-07-01

36

Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker  

NASA Astrophysics Data System (ADS)

In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10-15 ?m in both coordinates, low material budget <1%X0, and the ability to withstand a background hit rate of several tens of MHz/cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.

Rizzo, G.; Comott, D.; Manghisoni, M.; Re, V.; Traversi, G.; Fabbri, L.; Gabrielli, A.; Giorgi, F.; Pellegrini, G.; Sbarra, C.; Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Berra, A.; Lietti, D.; Prest, M.; Bevan, A.; Wilson, F.; Beck, G.; Morris, J.; Gannaway, F.; Cenci, R.; Bombelli, L.; Citterio, M.; Coelli, S.; Fiorini, C.; Liberali, V.; Monti, M.; Nasri, B.; Neri, N.; Palombo, F.; Stabile, A.; Balestri, G.; Batignani, G.; Bernardelli, A.; Bettarini, S.; Bosi, F.; Casarosa, G.; Ceccanti, M.; Forti, F.; Giorgi, M. A.; Lusiani, A.; Mammini, P.; Morsani, F.; Oberhof, B.; Paoloni, E.; Perez, A.; Petragnani, G.; Profeti, A.; Soldani, A.; Walsh, J.; Chrzaszcz, M.; Gaioni, L.; Manazza, A.; Quartieri, E.; Ratti, L.; Zucca, S.; Alampi, G.; Cotto, G.; Gamba, D.; Zambito, S.; Dalla Betta, G.-F.; Fontana, G.; Pancheri, L.; Povoli, M.; Verzellesi, G.; Bomben, M.; Bosisio, L.; Cristaudo, P.; Lanceri, L.; Liberti, B.; Rashevskaya, I.; Stella, C.; Vitale, L.

2013-08-01

37

3D monolithically stacked CMOS Active Pixel Sensors for particle position and direction measurements  

NASA Astrophysics Data System (ADS)

In this work we propose a 3D monolithically stacked, multi-layer detectors based on CMOS Active Pixel Sensors (APS) layers which allows at the same time accurate estimation of the impact point and of the incidence angle an ionizing particle. The whole system features two fully-functional CMOS APS matrix detectors, including both sensing area and control/signal elaboration circuitry, stacked in a monolithic device by means of Through Silicon Via (TSV) connections thanks to the capabilities of the CMOS vertical scale integration (3D-IC) 130 nm Chartered/Tezzaron technology. In order to evaluate the suitability of the two layer monolithic active pixel sensor system to reconstruct particle tracks, tests with proton beams have been carried out at the INFN LABEC laboratories in Florence (Italy) with 3 MeV proton beam.

Servoli, L.; Passeri, D.; Morozzi, A.; Magalotti, D.; Piperku, L.

2015-01-01

38

High-temperature Complementary Metal Oxide Semiconductors (CMOS)  

NASA Technical Reports Server (NTRS)

The results of an investigation into the possibility of using complementary metal oxide semiconductor (CMOS) technology for high temperature electronics are presented. A CMOS test chip was specifically developed as the test bed. This test chip incorporates CMOS transistors that have no gate protection diodes; these diodes are the major cause of leakage in commercial devices.

Mcbrayer, J. D.

1981-01-01

39

CMOS RF modeling for GHz communication IC's  

Microsoft Academic Search

With the advent of submicron technologies, GHz RF circuits can now be realized in a standard CMOS process. A major barrier to the realization of robust commercial CMOS RF components is the lack of adequate models which accurately predict MOSFET device behavior at high frequencies. The conventional microwave table-lookup-based approach requires a large database obtained from numerous device measurements and

Jia-Jiunn Ou; Xiaodong Jin; Ingrid Ma; Chenming Hu; Paul R. Gray

1998-01-01

40

A CMOS readout circuit for microstrip detectors  

NASA Astrophysics Data System (ADS)

In this work, we present the design and the results of a CMOS analog channel for silicon microstrips detectors. The readout circuit was initially conceived for the outer layers of the SuperB silicon vertex tracker (SVT), but can serve more generally other microstrip-based detection systems. The strip detectors considered show a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been investigated. The ASIC is composed by a preamplifier, shaping amplifier and a Time over Threshold (T.o.T) block for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit includes the possibility to select the peaking time of the shaper output from four values: 250 ns, 375 ns, 500 ns and 750 ns. In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The ASIC prototype has been fabricated in the 130 nm IBM technology which is considered intrinsically radiation hard. The results of the experimental characterization of a produced prototype are satisfactorily matched with simulation.

Nasri, B.; Fiorini, C.

2015-03-01

41

Monolithic multiple axis accelerometer design in standard CMOS  

Microsoft Academic Search

Using a single maskless postprocessing step we have developed an accelerometer in a standard commercial CMOS process capable of a sensitive axis parallel or perpendicular to the die surface. Out postprocess is realized using xenon difluoride (XeF2) as a bulk etchant. The combination of this etchant and the standard CMOS process allows realization of cantilevers with piezoresistive sensors in all

Brett Warneke; Eric G. Hoffman; Kristofer S. Pister

1995-01-01

42

Monolithic multiple axis accelerometer design in standard CMOS  

Microsoft Academic Search

Using a single maskless postprocessing step we have developed an accelerometer in a standard commercial CMOS process capable of a sensitive axis parallel or perpendicular to the die surface. Our postprocess is realized using xenon difluoride (XeF2) as a bulk etchant. The combination of this etchant and the standard CMOS process allows realization of cantilevers with piezoresistive sensors in all

Brett Warneke; Eric Hoffman; Kristofer S. J. Pister

1995-01-01

43

A 2x2 MIMO TriBand Dual-Mode Direct-Conversion CMOS Transceiver for Worldwide WiMAX\\/WLAN Applications  

Microsoft Academic Search

This paperdescribesafullyintegrated 130nmCMOS 2x2 MIMO tri-band dual-mode transceiver for fixed and mobile WiMAX and IEEE 802.11a\\/b\\/g\\/n applications. The proposed transceiver features reduced RF interface (only 4 RF pins) with the wideband circuit topology of the LNA and drive amplifier that minimizes the performance degradation. With carefully chosen LO frequency planning, the transceiver is capable of operating at 2.3-2.7 GHz, 3.3-3.9

Kyoohyun Lim; Sunki Min; Sanghoon Lee; Jaewoo Park; Kisub Kang; Hwahyeong Shin; Hyunchul Shim; Sechang Oh; Sungho Kim; Jongryul Lee; Changsik Yoo; Kukjin Chun

2011-01-01

44

A two-tier monolithically stacked CMOS Active Pixel Sensor to measure charged particle direction  

NASA Astrophysics Data System (ADS)

In this work we present an innovative approach to particle tracking based on CMOS Active Pixel Sensors (APS) layers, monolithically integrated in an all-in-one chip featuring multiple, stacked, fully functional detector layers capable to provide momentum measurement (particle direction) within a single detector by using multiple layer impact point coordinates. The whole system will results in a very low material detector, since each layer can be thinned down to tens of micrometres, thus dramatically reducing multiple scattering issues. To build such a detector, we rely on the capabilities of the CMOS vertical scale integration (3D-IC) 130 nm Chartered/Tezzaron technology, used to integrate two fully-functional CMOS APS matrix detectors, including both sensing area and control/signal elaboration circuitry, stacked in a monolithic device by means of Through Silicon Via (TSV) connections. Such a detector would allow accurate estimation of the impact point of an ionizing particle and of its incidence angle. Two batches of the first chip prototype have been produced and characterized using particle beams (e.g. protons) demonstrating the suitability of particle direction measurement with a single, multiple layers, 3D vertically stacked APS CMOS detector.

Passeri, D.; Servoli, L.; Meroli, S.; Magalotti, D.; Placidi, P.; Marras, A.

2014-05-01

45

A Wideband Low-Phase-Noise CMOS VCO Axel D. Berny, Ali M. Niknejad and Robert G. Meyer  

E-print Network

, Berkeley, CA 94720 Abstract A CMOS VCO has been designed and fabricated in a commercial 0.25µm CMOS process sensitivity. Circuit Design An LC VCO topology is chosen mainly for its potential to achieve good phase noiseA Wideband Low-Phase-Noise CMOS VCO Axel D. Berny, Ali M. Niknejad and Robert G. Meyer Berkeley

California at Berkeley, University of

46

Reliability of CMOS/SOS integrated circuits  

NASA Astrophysics Data System (ADS)

Reliability data for silicon-gate integrated circuits of various types are summarized. Included are failure rates for devices ranging from plastic-encapsulated commercial products to high-reliability hermetically-sealed integrated circuits for military and aerospace applications. Data are presented on devices fabricated by the original CMOS/SOS silicon-gate process and on devices prepared by advanced processes. These include lower wafer-process temperatures and improved wafer-processing techniques that permit thinner gate dielectrics and smaller feature sizes. Because they have fewer possible failure modes, CMOS/SOS integrated circuits have demonstrated a reliability at least equal to that achieved by bulk-MOS ICs.

Veloric, H.; Dugan, M. P.; Morris, W.; Denning, R.; Schnable, G.

1984-06-01

47

The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector  

NASA Astrophysics Data System (ADS)

This work presents the characterization of Deep N-well (DNW) active pixel sensors fabricated in a vertically integrated technology. The DNW approach takes advantage of the triple well structure to lay out a sensor with relatively large charge collecting area (as compared to standard three transistor MAPS), while the readout is performed by a classical signal processing chain for capacitive detectors. This new 3D design relies upon stacking two homogeneous tiers fabricated in a 130 nm CMOS process where the top tier is thinned down to about 12 ?m to expose through silicon vias (TSV), therefore making connection to the buried circuits possible. This technology has been used to design a fine pitch 3D CMOS sensor with sparsification capabilities, in view of vertexing applications to the International Linear Collider (ILC) experiments. Results from the characterization of different kind of test structures, including single pixels, 3×3 and 8×8 matrices, are presented.

Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.

2013-12-01

48

Ion traps fabricated in a CMOS foundry  

E-print Network

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, in any modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

Mehta, K K; Bruzewicz, C D; Chuang, I L; Ram, R J; Sage, J M; Chiaverini, J

2014-01-01

49

Ion traps fabricated in a CMOS foundry  

NASA Astrophysics Data System (ADS)

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

Mehta, K. K.; Eltony, A. M.; Bruzewicz, C. D.; Chuang, I. L.; Ram, R. J.; Sage, J. M.; Chiaverini, J.

2014-07-01

50

Ion traps fabricated in a CMOS foundry  

SciTech Connect

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

Mehta, K. K.; Ram, R. J. [Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Eltony, A. M.; Chuang, I. L. [Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Bruzewicz, C. D.; Sage, J. M., E-mail: jsage@ll.mit.edu; Chiaverini, J., E-mail: john.chiaverini@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

2014-07-28

51

Ion traps fabricated in a CMOS foundry  

E-print Network

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, in any modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

K. K. Mehta; A. M. Eltony; C. D. Bruzewicz; I. L. Chuang; R. J. Ram; J. M. Sage; J. Chiaverini

2014-06-13

52

CMOS active pixel image sensors for highly integrated imaging systems  

Microsoft Academic Search

A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-?m CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression

Sunetra K. Mendis; Sabrina E. Kemeny; Russell C. Gee; Bedabrata Pain; Craig O. Staller; Quiesup Kim; Eric R. Fossum

1997-01-01

53

Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis  

Microsoft Academic Search

FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0\\/1 fault model. Faults

John Paul Shen; F. Joel Ferguson

1988-01-01

54

A miniature CMOS optoelectronic biosensor for screening skin-whitening agents  

Microsoft Academic Search

A miniature CMOS optoelectronic biosensor is proposed for screening whitening agents. Based on the principle of absorption photometry, this biosensor is mainly composed of a green LED, a CMOS phototransistor, and a slide for performing the biochemical reactions. The requirement of the sample volume is only 10 mul, much less than those in commercial instruments. Melanin assay and MTT assay

Yu-Wei Changi; Yen-Pei Lu; Ming-Yu Lin; Yang-Tung Huangi; Yuh-Shyong Yang

2009-01-01

55

High-speed multicolour photometry with CMOS cameras  

NASA Astrophysics Data System (ADS)

We present the results of testing the commercial digital camera Nikon D90 with a CMOS sensor for high-speed photometry with a small telescope Celestron 11'' at the Peak Terskol Observatory. CMOS sensor allows to perform photometry in 3 filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system of CMOS sensors is close to the Johnson BVR system. The results of testing show that one can carry out photometric measurements with CMOS cameras for stars with the V-magnitude up to ?14^{m} with the precision of 0.01^{m}. Stars with the V-magnitude up to ˜10 can be shot at 24 frames per second in the video mode.

Pokhvala, S. M.; Zhilyaev, B. E.; Reshetnyk, V. M.

2012-11-01

56

CMOS Bridging Fault Detection  

Microsoft Academic Search

The authors compare the performance of two test generation techniques, stuck fault testing and current testing, when applied to CMOS bridging faults. Accurate simulation of such faults mandated the development of several new design automation tools, including an analog-digital fault simulator. The results of this simulation are analyzed. It is shown that stuck fault test generation, while inherently incapable of

Thomas M. Storey; Wojciech Maly

1990-01-01

57

A CMOS triode transconductor  

Microsoft Academic Search

A novel versatile CMOS voltage to current converter is presented. The conversion transistors operate in the triode region. The linearity is high (total harmonic distortion <0.4% for 6 Vpp input signals on a breadboard). The transconductance can be tuned over a wide range (factor 25 on breadboard, factor 100 expected on chip). The input voltages are not restricted to a

Bram Nauta; Eric Klumperink; Wim Kruiskamp

1991-01-01

58

Monolithic multiple axis accelerometer design in standard CMOS  

NASA Astrophysics Data System (ADS)

Using a single maskless postprocessing step we have developed an accelerometer in a standard commercial CMOS process capable of a sensitive axis parallel or perpendicular to the die surface. Out postprocess is realized using xenon difluoride (XeF2) as a bulk etchant. The combination of this etchant and the standard CMOS process allows realization of cantilevers with piezoresistive sensors in all spacial coordinates from a widely-accessible source and at a minimal cost. Fabrication of accelerometers for all three axes and associated electronics on a single piece of silicon reduces the cost of 3D acceleration detection while increasing sensor reliability.

Warneke, Brett; Hoffman, Eric G.; Pister, Kristofer S. J.

1995-09-01

59

Characterization of a CMOS sensing core for ultra-miniature wireless implantable temperature sensors with application to cryomedicine.  

PubMed

In effort to improve thermal control in minimally invasive cryosurgery, the concept of a miniature, wireless, implantable sensing unit has been developed recently. The sensing unit integrates a wireless power delivery mechanism, wireless communication means, and a sensing core-the subject matter of the current study. The current study presents a CMOS ultra-miniature PTAT temperature sensing core and focuses on design principles, fabrication of a proof-of-concept, and characterization in a cryogenic environment. For this purpose, a 100 ?m × 400 ?m sensing core prototype has been fabricated using a 130 nm CMOS process. The senor has shown to operate between -180°C and room temperature, to consume power of less than 1 ?W, and to have an uncertainty range of 1.4°C and non-linearity of 1.1%. Results of this study suggest that the sensing core is ready to be integrated in the sensing unit, where system integration is the subject matter of a parallel effort. PMID:25001173

Khairi, Ahmad; Thaokar, Chandrajit; Fedder, Gary; Paramesh, Jeyanandh; Rabin, Yoed

2014-09-01

60

CMOS micromechanical resonator oscillator  

Microsoft Academic Search

A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator to achieve stability and phase noise performance comparable to those of quartz crystal oscillators. It is shown that the closed-loop, steady-state oscillation amplitude of this oscillator can be controlled through the DC-bias

C. T.-C. Nguyen; R. T. Howe

1993-01-01

61

Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.  

SciTech Connect

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materials integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.

Sumant, A.V.; Auciello, O.; Yuan, H.-C; Ma, Z.; Carpick, R. W.; Mancini, D. C.; Univ. of Wisconsin; Univ. of Pennsylvania

2009-05-01

62

Design and Fabrication of Vertically-Integrated CMOS Image Sensors  

PubMed Central

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Skorka, Orit; Joseph, Dileepan

2011-01-01

63

A Single-Chip 8-Band CMOS Transceiver for 3G Cellular Systems with Digital Interface  

NASA Astrophysics Data System (ADS)

In this paper, a single-chip dual-mode 8-band 130nm CMOS transceiver including A/D/A converters and digital filters with 312MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.

Yoshida, Hiroshi; Toyoda, Takehiko; Tsurumi, Hiroshi; Itoh, Nobuyuki

64

Regenerative switching CMOS system  

DOEpatents

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

1998-01-01

65

Regenerative switching CMOS system  

DOEpatents

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

Welch, J.D.

1998-06-02

66

CMOS RAM cosmic-ray-induced-error-rate analysis  

NASA Technical Reports Server (NTRS)

A significant number of spacecraft operational anomalies are believed to be associated with cosmic-ray-induced soft errors in the LSI memories. Test programs using a cyclotron to simulate cosmic rays have established conclusively that many common commercial memory types are vulnerable to heavy-ion upset. A description is given of the methodology and the results of a detailed analysis for predicting the bit-error rate in an assumed space environment for CMOS memory devices. Results are presented for three types of commercially available CMOS 1,024-bit RAMs. It was found that the HM6508 is susceptible to single-ion induced latchup from argon and krypton ions. The HS6508 and HS6508RH and the CDP1821 apparently are not susceptible to single-ion induced latchup.

Pickel, J. C.; Blandford, J. T., Jr.

1981-01-01

67

Transistor sizing in CMOS circuits  

Microsoft Academic Search

The problem of optimally sizing transistors in a VLSI CMOS circuit is considered. Models and algorithms for performing optimization on a single path using RC-tree approximation are presented. The results of an automatic optimization procedure are discussed.

Mehmet A. Cirit

1987-01-01

68

Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators  

PubMed Central

This work presents a thermoelectric micro generator fabricated by the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 ?V at the temperature difference of 1 K. PMID:22205869

Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

2010-01-01

69

CMOS passive pixel image design techniques  

E-print Network

CMOS technology provides an attractive alternative to the currently dominant CCD technology for implementing low-power, low-cost imagers with high levels of integration. Two pixel configurations are possible in CMOS ...

Fujimori, Iliana L. (Iliana Lucia)

2002-01-01

70

Latest results of the R&D on CMOS MAPS for the Layer0 of the SuperB SVT  

NASA Astrophysics Data System (ADS)

Physics and high background conditions set very challenging requirements on readout speed, material budget and resolution for the innermost layer of the SuperB Silicon Vertex Tracker operated at the full luminosity. Monolithic Active Pixel Sensors (MAPS) are very appealing in this application since the thin sensitive region allows grinding the substrate to tens of microns. Deep N-Well MAPS, developed in the ST 130 nm CMOS technology, achieved in-pixel sparsification and fast time stamping. Further improvements are being explored with an intense R&D program, including both vertical integration and 2D MAPS with the INMAPS quadruple well. We present the results of the characterization with IR laser, radioactive sources and beam of several chips produced with the 3D (Chartered/Tezzaron) process. We have also studied prototypes exploiting the features of the quadruple well and the high resistivity epitaxial layer of the INMAPS 180 nm process. Promising results from an irradiation campaign with neutrons on small matrices and other test-structures, as well as the response of the sensors to high energy charged tracks are presented.

Balestri, G.; Batignani, G.; Beck, G.; Bernardelli, A.; Berra, A.; Bettarini, S.; Bevan, |A.; Bombelli, L.; Bosi, F.; Bosisio, L.; Casarosa, G.; Ceccanti, M.; Cenci, R.; Citterio, M.; Coelli, S.; Comotti, D.; Dalla Betta, G.-F.; Fabbri, L.; Fiorini, C.; Fontana, G.; Forti, F.; Gabrielli, A.; Gaioni, L.; Gannaway, F.; Giorgi, F.; Giorgi, M. A.; Lanceri, L.; Liberali, V.; Lietti, D.; Lusiani, A.; Mammini, P.; Manazza, A.; Manghisoni, M.; Monti, M.; Morris, J.; Morsani, F.; Nasri, B.; Neri, N.; Oberhof, B.; Palombo, F.; Pancheri, L.; Paoloni, E.; Pellegrini, G.; Perez, A.; Petragnani, G.; Prest, M.; Povoli, M.; Profeti, A.; Quartieri, E.; Rashevskaya, I.; Ratti, L.; Re, V.; Rizzo, G.; Sbarra, C.; Semprini-Cesari, N.; Soldani, A.; Stabile, A.; Stella, C.; Traversi, G.; Valentinetti, S.; Verzellesi, G.; Villa, M.; Vitale, L.; Walsh, J.; Wilson, F.; Zoccoli, A.; Zucca, S.

2013-12-01

71

Ge technology beyond Si CMOS  

NASA Astrophysics Data System (ADS)

To save energy, low voltage operation is the most important criterion for CMOS ICs. To reach this goal, high mobility new channel materials are required for CMOS ICs at <= 14 nm technology nodes. The high electron mobility InGaAs nMOSFET and high hole mobility Ge pMOSFET were proposed for CMOS at 0.5 V operation, since the poor hole mobility of InGaAs makes it unsuitable for all InGaAs CMOS. However, the epitaxial InGaAs nMOSFET on Si faces fundamental material challenges with large defects and high leakage current. Although dislocation-defects-free Ge-on-Insulator (GeOI), ultra-thin-body (UTB) InGaAs IIIV-on-Insulator (IIIVOI), and selective GeOI on Si were pioneered by us, it is still difficult to reach InGaAs-nMOS/Ge-pMOS CMOS targeting to <= 14 nm CMOS. In contrast, Ge is the ideal candidate for all Ge CMOS logic due to both higher electron and hole mobility than Si. Significantly higher (2.6X) hole mobility of GeOI pMOSFET than universal SiO2/Si value was reached at a medium 0.5 MV/cm effective electric field (Eejf) and 1.4 nm equivalent-oxide-thickness (EOT). Nevertheless, the Ge nMOSFET suffers from large EOT and fast mobility degradation with increasing Eeff, due to the surface Fermi-level pinning to valance band, poor high-?/Ge interface and low dopant activation. Using novel laser annealing and proper gate stack, small EOT of 0.95 nm, small sub-threshold swing of 106 mV/dec, and 40% better high-field mobility than universal SiO2/Si data were achieved in Ge nMOSFET. Such all-Ge CMOS has irreplaceable merits of much simpler process, lower cost, and potentially higher yield than the InGaAs-nMOS/Ge-pMOS CMOS platform.

Chin, Albert

2012-12-01

72

TDC-based frequency synthesizer for wireless applications  

Microsoft Academic Search

We analyze phase noise performance and further discuss details of an all-digital PLL that is used in a commercial 130 nm CMOS single-chip Bluetooth radio. The frequency synthesizer uses a digitally controlled oscillator with a digital loop filter and a time-to-digital converter that acts as a phase\\/frequency detector. When implemented in a deep-submicron CMOS, the presented architecture appears more advantageous

Robert Bogdan Staszewski; D. Leipold; Chih-Ming Hung; P. T. Balsara

2004-01-01

73

A Brief Discussion of Radiation Hardening of CMOS Microelectronics  

SciTech Connect

Commercial microchips work well in their intended environments. However, generic microchips will not fimction correctly if exposed to sufficient amounts of ionizing radiation, the kind that satellites encounter in outer space. Modern CMOS circuits must overcome three specific concerns from ionizing radiation: total-dose, single-event, and dose-rate effects. Minority-carrier devices such as bipolar transistors, optical receivers, and solar cells must also deal with recombination-generation centers caused by displacement damage, which are not major concerns for majority-carrier CMOS devices. There are ways to make the chips themselves more resistant to radiation. This extra protection, called radiation hardening, has been called both a science and an art. Radiation hardening requires both changing the designs of the chips and altering the ways that the chips are manufactured.

Myers, D.R.

1998-12-18

74

A back-illuminated megapixel CMOS image sensor  

NASA Technical Reports Server (NTRS)

In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

2005-01-01

75

MonoColor CMOS sensor  

NASA Astrophysics Data System (ADS)

A new breed of CMOS color sensor called MonoColor sensor is developed for a barcode reading application in AIDC industry. The RGBW color filter array (CFA) in a MonoColor sensor is arranged in a 8 x 8 pixels CFA with only 4 pixels of them are color (RGB) pixels and the rest of 60 pixels are transparent or monochrome. Since the majority of pixels are monochrome, MonoColor sensor maintains 98% barcode decode performance compared with a pure monochrome CMOS sensor. With the help of monochrome and color pixel fusion technique, the resulting color pictures have similar color quality in terms of Color Semantic Error (CSE) compared with a Bayer pattern (RGB) CMOS color camera. Since monochrome pixels are more sensitive than color pixels, a MonoColor sensor produces in general about 2X brighter color picture and higher luminance pixel resolution.

Wang, Ynjiun P.

2009-02-01

76

CMOS Integrated Carbon Nanotube Sensor  

SciTech Connect

Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A. [Grupo MEMS, Comision Nacional de Energia Atomica, Buenos Aires (Argentina); Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S. [Dpto. de Ing. Electrica y de Computadoras, Universidad Nacional del Sur, Bahia Blanca (Argentina); Buffa, F. A. [INTEMA Facultad de Ingenieria, Universidad Nacional de Mar del Plata, Mar del Plata (Argentina)

2009-05-23

77

A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.  

PubMed

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 ?m CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 ?m CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

78

Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units  

SciTech Connect

One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing. In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.

Smith, J.H.; Ellis, J.R.; Montague, S.; Allen, J.J.

1997-03-01

79

A comparison of electrostatic discharge models and failure signatures for CMOS integrated circuit devices  

Microsoft Academic Search

Six different CMOS device codes were evaluated, according to available test standards, for Electrostatic Discharge (ESD) sensitivity using three ESD models: Human Body Model (HBM), Machine Model (MM), Field-induced Charged Device Model (FCDM). Four commercially available simulators were used: two to perform the HBM ESD evaluations and two to perform the MM ESD evaluations. FCDM stressing was performed using an

M. Kelly; G. Servais; T. Diep; D. Lin; S. Twerefour; G. Shah

1995-01-01

80

A CMOS image sensor for low light applications Honghao Ji, Pamela A. Abshire  

E-print Network

A CMOS image sensor for low light applications Honghao Ji, Pamela A. Abshire Department pixel for high speed, low light imaging applications. The new pixel achieves lower dark current integration node. An image sensor with a 256 × 256 array of these pixels was designed for a commercially

Maryland at College Park, University of

81

Integration of solid-state nanopores in a 0.5 ?m cmos foundry process  

PubMed Central

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

82

RF-CMOS performance trends  

Microsoft Academic Search

The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance

Pierre H. Woerlee; Mathijs J. Knitel; Ronald van Langevelde; Dirk B. M. Klaassen; Luuk F. Tiemeijer; Andries J. Scholten; A. T. A. Zegers-van Duijnhoven

2001-01-01

83

A CMOS Switched Transconductor Mixer  

Microsoft Academic Search

A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled outputs, which are alternatingly activated by the switches. For ideal switching, the operation is equivalent to a

Eric A. M. Klumperink; Simon M. Louwsma; Gerard J. M. Wienk; Bram Nauta

2004-01-01

84

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices  

NASA Technical Reports Server (NTRS)

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

85

Highly linear voltage-controlled CMOS transconductors  

Microsoft Academic Search

A circuit technique for realizing voltage-tunable linear high-frequency CMOS transconductor cells that use two cross-coupled MOS or CMOS transistor pairs operating at saturation is described. The tuning capabilities attained with an adjustable CMOS voltage source are examined. Design trade-offs between linearity and bandwidth are discussed, and a simple operational transconductance amplifier (OTA) example is simulated via SPICE. The simulation results

S. Szczepanski; A. Wyszynski; Rolf Schaumann

1993-01-01

86

A CMOS biquad at VHF  

Microsoft Academic Search

A differential transconductance-C biquad implemented in the digital subset of a 0.9-?m CMOS process operates at frequencies up to 450 MHz and Q-factors to approximately 100 with SNR (signal-to-noise ratio) in the range of 35-45 dB. By switching in capacitors and adjusting control voltages it can be tuned to below 30 MHz, demonstrating the capability of operating over the entire

Martin Snelgrove; Ayal Shoval

1991-01-01

87

Fabrication of CMOS image sensors  

NASA Astrophysics Data System (ADS)

In order to provide its customers with sub-micron CMOS fabrication solutions for imaging applications, Tower Semiconductor initiated a project to characterize the optical parameters of Tower's 0.5-micron process. A special characterization test chip was processed using the TS50 process. The results confirmed a high quality process for optical applications. Perhaps the most important result is the process' very low dark current, of 30-50 pA/cm2, using the entire window of process. This very low dark current characteristic was confirmed for a variety of pixel architectures. Additionally, we have succeeded to reduce and virtually eliminate the white spots on large sensor arrays. As a foundry Tower needs to support fabrication of many different imaging products. Therefore we have developed a fabrication methodology that is adjusted to the special needs of optical applications. In order to establish in-line process monitoring of the optical parameters, Tower places a scribe line optical test chip that enables wafer level measurements of the most important parameters, ensuring the optical quality and repeatability of the process. We have developed complementary capabilities like in house deposition of color filter and fabrication of very large are dice using sub-micron CMOS technologies. Shellcase and Tower are currently developing a new CMOS image sensor optical package.

Malinovich, Yacov; Koltin, Ephie; Choen, David; Shkuri, Moshe; Ben-Simon, Meir

1999-04-01

88

CMOS pulse-code-modulation voice codec  

Microsoft Academic Search

A standard CMOS technology has been employed in LSI realization of a pulse-code-modulation (PCM) encoder and decoder for per-channel applications in telephony. Innovations in the design of an operational amplifier, a comparator, and precision-ratioed capacitor arrays, all in standard CMOS, are reported.

G. Smarandoiu; D. A. Hodges; P. R. Gray; G. F. Landsburg

1978-01-01

89

CMOS pixels for subretinal implantable prothesis  

Microsoft Academic Search

This work reports on the design, fabrication, and characterization of CMOS pixels for subretinal implants, which seems to be an effective way to recover visual capabilities in some types of blindness. Two possible approaches are presented for CMOS pixel implementation: 1) an approach based on a light-controlled oscillator (LICOS) using a ring oscillator with an odd number of inverters and

M. Mazza; P. Renaud; D. C. Bertrand; A. M. Ionescu

2005-01-01

90

JPL CMOS Active Pixel Sensor Technology  

NASA Technical Reports Server (NTRS)

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

Fossum, E. R.

1995-01-01

91

CMOS foveal image sensor chip  

NASA Technical Reports Server (NTRS)

A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

2002-01-01

92

TFSOI complementary BiCMOS technology for low power applications  

Microsoft Academic Search

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 ?m CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure

Wen-Ling Margaret Huang; Kevin M. Klein; M. Grimaldi; Marco Racanelli; Shri Ramaswami; J. Tsao; Juergen Foerstner; Bor-Yuan C. Hwang

1995-01-01

93

Investigation of heavy particle induced latch-up, using a Californium-252 source, in CMOS SRAMs and PROMs  

NASA Astrophysics Data System (ADS)

Heavy ion-induced latch-up, in commercial CMOS SRAMs and PROMs, was examined using a laboratory Californium-252 source, in order to simulate the cosmic environment. The ability to use the CASE system (Californium-252 Assessment of Single-event Effects) enabled detailed electrical measurements to be made of the devices in the latched condition.

Stephen, J. H.; Sanderson, T. K.; Mapper, D.; Hardman, M.; Farren, J.; Adams, L.; Harboe-Sorensen, R.

1984-12-01

94

Tin oxide gas sensor fabricated using CMOS micro-hotplates and in-situ processing  

Microsoft Academic Search

A monolithic tin oxide (SnO2) gas sensor realized by commercial CMOS foundry fabrication (MOSIS) and postfabrication processing techniques is reported. The device is composed of a sensing film that is sputter-deposited on a silicon micromachined hotplate. The fabrication technique requires no masking and utilizes in situ process control and monitoring of film resistivity during film growth. Microhotplate temperature is controlled

John S. Suehle; Richard E. Cavicchi; Michael Gaitan; Steve Semancik

1993-01-01

95

Capacitive micro pressure sensors with underneath readout circuit using a standard CMOS process  

Microsoft Academic Search

A capacitive micropressure sensor with readout circuits on a single chip is fabricated using commercial 0.35?m complementary metal oxide semiconductor (CMOS) process and post?processing. The main break through feature of the chip is the positioning of its readout circuits under the pressure sensor, allowing the chip to be smaller. Post?processing included anisotropic dry etching and wet etching to remove the

2003-01-01

96

A simple and low-cost biofilm quantification method using LED and CMOS image sensor.  

PubMed

A novel biofilm detection platform, which consists of a cost-effective red, green, and blue light-emitting diode (RGB LED) as a light source and a lens-free CMOS image sensor as a detector, is designed. This system can measure the diffraction patterns of cells from their shadow images, and gather light absorbance information according to the concentration of biofilms through a simple image processing procedure. Compared to a bulky and expensive commercial spectrophotometer, this platform can provide accurate and reproducible biofilm concentration detection and is simple, compact, and inexpensive. Biofilms originating from various bacterial strains, including Pseudomonas aeruginosa (P. aeruginosa), were tested to demonstrate the efficacy of this new biofilm detection approach. The results were compared with the results obtained from a commercial spectrophotometer. To utilize a cost-effective light source (i.e., an LED) for biofilm detection, the illumination conditions were optimized. For accurate and reproducible biofilm detection, a simple, custom-coded image processing algorithm was developed and applied to a five-megapixel CMOS image sensor, which is a cost-effective detector. The concentration of biofilms formed by P. aeruginosa was detected and quantified by varying the indole concentration, and the results were compared with the results obtained from a commercial spectrophotometer. The correlation value of the results from those two systems was 0.981 (N = 9, P < 0.01) and the coefficients of variation (CVs) were approximately threefold lower at the CMOS image-sensor platform. PMID:25455019

Kwak, Yeon Hwa; Lee, Junhee; Lee, Junghoon; Kwak, Soo Hwan; Oh, Sangwoo; Paek, Se-Hwan; Ha, Un-Hwan; Seo, Sungkyu

2014-12-01

97

A CMOS-compatible compact display  

E-print Network

Portable information devices demand displays with high resolution and high image quality that are increasingly compact and energy-efficient. Microdisplays consisting of a silicon CMOS backplane integrated with light ...

Chen, Andrew R. (Andrew Raymond)

2005-01-01

98

CMOS BASELINE PROCESS UC BERKELEY MICROFABRICATION LABORATORY  

E-print Network

Flow and Device Cross Sections 2.2 Mask Definitions 3 Process Simulationand Material Characterization, double poly and double metal CMOS processes and while these are.running we embarked upon developing a 1

Healy, Kevin Edward

99

Neutron spectrum and dose in a CMOS  

NASA Astrophysics Data System (ADS)

Using Monte Carlo methods the neutron spectrum in a pacemaker's CMOS has been estimated. A 18 MV LINAC model was used to expose a cell used to define the prostate located in a tissue equivalent phantom model. Neutron fluence at the CMOS is 2.6E(7) n/cm2-Gyx, the spectrum has thermal, epithermal and fast neutrons that will induce secondary, low and high LET, particles whose ionization could induce malfunction and failure of pacemaker in the oncological patient.

Vega-Carrillo, H. R.; Paredes-Gutierrez, L.; Borja-Hernandez, C. G.

2012-10-01

100

Cmos-Compatible High Voltage Integrated Circuits  

Microsoft Academic Search

Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5 mum CMOS process are first studied. High -voltage n- and p-channel transistors with breakdown voltages of 50

Zahir Parpia

1988-01-01

101

CMOS scaling into the nanometer regime  

Microsoft Academic Search

Starting with a brief review on 0.1-?m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect

Yuan Taur; DOUGLAS A. BUCHANAN; Wei Chen; DAVID J. FRANK; KHALID E. ISMAIL; Shih-Hsien Lo; G. A. Sai-Halasz; R. G. Viswanathan; H.-J. C. Wann; S. J. Wind; Hon-Sum Wong

1997-01-01

102

Latch-up CMOS/EPI devices  

SciTech Connect

New space projects tend to use more and more VLSI circuits manufactured in CMOS technology. Assessment of latch-up sensitivity is mandatory in the evaluation plan of a component, and in some cases the result could be considered as a GO/NOGO parameter. The authors present data on several CMOS/EPI devices demonstrating the non-efficiency of an epitaxial layer to achieve latch-up immunity for some latest technologies.

Chapuis, T. (Centre National d'Etudes Spatiales, 18 Av. Edouard Belin, 31055 Toulouse Cedex (FR)); Erems, H.C. (Z.I. Flourens, 31130 Balma (FR)); Rosier, L.H. (Inst. de Physique Nucleaire, BP 1-91406, Orsay Cedex (FR))

1990-12-01

103

Post-CMOS integration of germanium microstructures  

Microsoft Academic Search

Polycrystalline germanium (poly-Ge) microstructures have been fabricated on standard CMOS wafers. Conventional low pressure chemical vapor deposition (LPCVD) and rapid thermal annealing (RTA) processes were used to achieve low-resistivity (2.3 m?-cm) tensile poly-Ge structural films, with a thermal budget which is compatible with Al (2% Si) metallization. The CMOS circuitry was passivated with low-temperature oxide and amorphous Si; the latter

A. E. Franke; D. Bilic; D. T. Chang; P. T. Jones; T.-J. King; R. T. Howe; G. C. Johnson

1999-01-01

104

A CMOS Smart Temperature and Humidity Sensor with Combined Readout  

PubMed Central

A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 ?m CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 ?A. PMID:25230305

Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

2014-01-01

105

Fabrication and Characterization of CMOS-MEMS Magnetic Microsensors  

PubMed Central

This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5–200 mT. PMID:24172287

Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

106

CMOS compatible avalanche photodetector and its application in communications  

NASA Astrophysics Data System (ADS)

CMOS compatible avalanche photodiodes (CMOS APDs) can be fabricated with standard CMOS technology, which make CMOS APDs are considered as a key optoelectronic device for optical communication systems and optical wireless communication systems. The guard-ring (GR) structure in CMOS APDs can alleviate the premature edge breakdown (PEB) effects and greatly improve the device performance. In this paper, the influence of various type GR structure on CMOS APDs performance are discussed, and its important applications in radio-over-fibre (RoF) are reviewed.

Tang, Miangang; Wu, Zhigang; Li, Guohui

2014-11-01

107

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors  

PubMed Central

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

108

CMOS image sensors: electronic camera-on-a-chip  

Microsoft Academic Search

CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed

Eric R. Fossum

1997-01-01

109

Integration of CMOS, single electron transistors, and quantumdot cellular automata  

Microsoft Academic Search

The physical limits associated with CMOS devices require the development of new computational architectures. Quantum-dot cellular automata (QCA) offers a low power, high-speed computational architecture. This paper demonstrates the integration of CMOS, QCA, and SET technologies on a single silicon die. A capacitive voltage divider is used to reduce standard CMOS logic voltage levels to millivolt control voltages for a

Aaron A. Prager; Alexei O. Orlov; Gregory L. Snider

2009-01-01

110

Cascode voltage switch logic: A differential CMOS logic family  

Microsoft Academic Search

A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A CMOS circuit using 10,880 NMOS differential pairs has been developed using this approach.

L. Heller; W. Griffin; J. Davis; N. Thoma

1984-01-01

111

Technology and device scaling considerations for CMOS imagers  

Microsoft Academic Search

This paper presents an analysis of the impact of device and technology scaling on active pixel CMOS image sensors. Using the SLA roadmap as a guideline, we calculate the device characteristics that are germane to the image sensing performance of CMOS imagers, and highlight the areas where the CIMOS imager technology may need to depart from “standard” CMOS technologies. The

Hon-Sum Wong

1996-01-01

112

CMOS Photovoltaic-cell Layout Configurations for Harvesting Microsystems  

E-print Network

CMOS Photovoltaic-cell Layout Configurations for Harvesting Microsystems Rajiv Damodaran Prabha, and radiation, photovoltaic (PV) systems are appealing options. Still, chip-sized CMOS PV cells produce only well in substrate cell are better. Index Terms--Ambient light energy, harvester, CMOS photovoltaic (PV

Rincon-Mora, Gabriel A.

113

Low power, CMOS digital autocorrelator spectrometer for spaceborne applications  

NASA Technical Reports Server (NTRS)

A 128-channel digital autocorrelator spectrometer using four 32 channel low power CMOS correlator chips was built and tested. The CMOS correlator chip uses a 2-bit multiplication algorithm and a full-custom CMOS VLSI design to achieve low DC power consumption. The digital autocorrelator spectrometer has a 20 MHz band width, and the total DC power requirement is 6 Watts.

Chandra, Kumar; Wilson, William J.

1992-01-01

114

New package for CMOS sensors  

NASA Astrophysics Data System (ADS)

Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

2004-02-01

115

A 130-nm RHBD SRAM With High Speed SET and Area Efficient TID Mitigation  

Microsoft Academic Search

A radiation hardened by design 5 kB static random access memory appropriate for embedded system on a chip integrated circuits is presented. High speed dual redundant control logic suppresses single event transients, allowing 500 MHz operation. Dynamic supply modulation, reverse body bias, and array supply collapse are investigated, in place of annular layout, to suppress leakage current increases due to

Karl C. Mohr; Lawrence T. Clark; Keith E. Holbert

2007-01-01

116

Scatterometry measurement method for gate CD control of sub-130nm technology  

NASA Astrophysics Data System (ADS)

Recently, the scatterometry is becoming more and more popular as a inline metrology tool for lithography process control as well as etching process control because of the advantage of fast measurement with high accuracy. Especially, at the gate patterning that fabricates transistors, the scatterometry can be very powerful because it gives massive volume of CD (Critical Dimension) measurement data and gate poly profile, simultaneously. Those results could help to understand and forecast the performance of transistors. In order to achieve accurate and consistent measurement results by scatterometry, the setup of stable model and library is very crucial since it has nature of indirect measurement. For example, as defining of substrate conditions, modeling range of parameters, target values and type of models, scatterometry (in this paper, we call as OCD; Optical CD) gives different results even if we use same data basis. In this paper we have shown the best practice how to optimize variables of scatterometry to get accurate and stable results. We used the OCD(Optic CD: Accent CDS200) angular scatterometry system which can rotate HeNe laser light source from -47 to +47 degree. In order to investigate the substrate dependency, various silicon wafer substrates having periodic patterned with different materials such as photoresist, BARC, poly silicon, and thermal oxide film has been used. Finally, we observed OCD has the excellent capability for inline process controllability.

Jang, Jeongyeol; Kwak, Sungho; Lee, Karl; Kim, Keeho; Park, Heongsu; Youn, James; Sohn, Lucas

2005-05-01

117

Impact of Spacecraft Shielding on Direct Ionization Soft Error Rates for sub-130 nm Technologies  

NASA Technical Reports Server (NTRS)

We use ray tracing software to model various levels of spacecraft shielding complexity and energy deposition pulse height analysis to study how it affects the direct ionization soft error rate of microelectronic components in space. The analysis incorporates the galactic cosmic ray background, trapped proton, and solar heavy ion environments as well as the October 1989 and July 2000 solar particle events.

Pellish, Jonathan A.; Xapsos, Michael A.; Stauffer, Craig A.; Jordan, Michael M.; Sanders, Anthony B.; Ladbury, Raymond L.; Oldham, Timothy R.; Marshall, Paul W.; Heidel, David F.; Rodbell, Kenneth P.

2010-01-01

118

Monolithic optical phased-array transceiver in a standard SOI CMOS process.  

PubMed

Monolithic microwave phased arrays are turning mainstream in automotive radars and high-speed wireless communications fulfilling Gordon Moores 1965 prophecy to this effect. Optical phased arrays enable imaging, lidar, display, sensing, and holography. Advancements in fabrication technology has led to monolithic nanophotonic phased arrays, albeit without independent phase and amplitude control ability, integration with electronic circuitry, or including receive and transmit functions. We report the first monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic circuitry that is tightly integrated with the nanophotonic components on one substrate using a commercial foundry CMOS SOI process. The 8 × 8 phased array chip includes thermo-optical tunable phase shifters and attenuators, nano-photonic antennas, and dedicated control electronics realized using CMOS transistors. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any electronic-photonic system. PMID:25836869

Abediasl, Hooman; Hashemi, Hossein

2015-03-01

119

A capacitor-free high PSR CMOS low dropout voltage regulator  

NASA Astrophysics Data System (ADS)

This paper presents a capacitor-free CMOS low dropout voltage regulator which has high PSR performance and low chip area. Pole splitting and gm boosting techniques are employed to achieve good stability. The capacitor-free chip LDO was fabricated in commercial 0.18 ?m CMOS technology provided by GSMC (Shanghai, China). Measured results show that the capacitor-free LDO has a stable output voltage 1.79 V, when supply voltage changes from 2.5 to 5 V, and the LDO is capable of driving maximum 100 mA load current. The LDO has high power supply rejection about -79 dB at low frequency and -40 dB at 1 MHz frequency, while sacrifice of the LDO's active chip-area is only smaller than 0.02 mm2.

Zhichao, Li; Yuntao, Liu; Zhangqu, Kuang; Jie, Chen

2014-06-01

120

CMOS detectors at Rome "Tor Vergata" University  

NASA Astrophysics Data System (ADS)

The new class of CMOS panoramic detectors represents an innovative tool for the experimental astronomy of the forthcoming years. While current charge-coupled device (CCD) technology can produce nearly ideal detectors for astronomical use, the scientific quality CMOS detectors made today have characteristics similar to those of CCD devices but a simpler electronics and a reduced cost. Moreover, the high frame rate capability and the amplification of each pixel - active pixel - in a CMOS detector, allows the implementation of a specific data management. So, it is possible to design cameras with very high dynamic range suitable for the imaging of solar active regions. In fact, in such regions, the onset of a flare can produce problems of saturation in a CCD-based camera. In this work we present the preliminary result obtained with the Tor Vergata C-Cam APS camera used at the University Solar Station.

Berrilli, F.; Cantarano, S.; Egidi, A.; Giordano, S.

121

IBM: Scaling CMOS to the Limit  

NSDL National Science Digital Library

This is the latest issue of the IBM Journal of Research and Development. "This double issue contains fifteen papers which address the challenges of scaling CMOS devices as physical limits are approached." Specifically, research teams report on topics such as silicon-on-insulator technology, new CMOS materials and device structures, dynamic random-access memory, and many others. The papers provide views of how far scaling could progress in the future and what constrains further advancement. Several back issues of the journal are also available, and each focuses on a different area of research.

2002-01-01

122

Optical addressing technique for a CMOS RAM  

NASA Technical Reports Server (NTRS)

Progress on optically addressing a CMOS RAM for a feasibility demonstration of free space optical interconnection is reported in this paper. The optical RAM chip has been fabricated and functional testing is in progress. Initial results seem promising. New design and SPICE simulation of optical gate cell (OGC) circuits have been carried out to correct the slow fall time of the 'weak pull down' OGC, which has been characterized experimentally. Methods of reducing the response times of the photodiodes and the associated circuits are discussed. Even with the current photodiode, it appears that an OGC can be designed with a performance that is compatible with a CMOS circuit such as the RAM.

Wu, W. H.; Bergman, L. A.; Allen, R. A.; Johnston, A. R.

1988-01-01

123

End-of-fabrication CMOS process monitor  

NASA Technical Reports Server (NTRS)

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

1990-01-01

124

Silicon Deformable Mirrors and CMOS-based Wavefront Sensors Justin D. Mansell, Peter B. Catrysse, Eric K. Gustafson, and Robert L. Byer  

E-print Network

Silicon Deformable Mirrors and CMOS-based Wavefront Sensors Justin D. Mansell, Peter B. Catrysse potential commercial applications for adaptive optics like laser beam control and ophthalmology. Silicon have implemented a new architecture of silicon deformable mirror designed to be low cost, have low

Byer, Robert L.

125

Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference  

PubMed Central

This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of ?40–200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage VREF depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 ?W at room temperature and only 75 ?W at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of VREF and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2. PMID:24351635

Boufouss, El Hafed; Francis, Laurent A.; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

2013-01-01

126

CMOS Avalanche Radio-over-Fiber wchoi@yonsei.ac.kr  

E-print Network

#12;#12;CMOS Avalanche Radio-over-Fiber , wchoi@yonsei.ac.kr CMOS Avalanche Photo-detector for Radio-over-Fiber Systems Yonsei Univ. 0.13um CMOS avalanche (avalanche photo-detector, APDF) [1-2]. RoF CMOS . CMOS GaAs responsivity . APD avalanche

Choi, Woo-Young

127

CMOS image sensors for subretinal implant system  

Microsoft Academic Search

Visual capabilities recovery for some kind of illness is possible through subretinal implantable device stimulation. Two possible approaches for retinal pixel are proposed, fabricated in 0.35?m CMOS, tested and compared including electronic response on a human tissue like interface. In these solutions, power consumption has been proved to he dominated by electrode stimulation and, in normal condition, typical consumption is

M. Mazza; D. Bertrand; P. Renaud; A. M. Ionescu

2003-01-01

128

Radiation Tolerance of 65nm CMOS Transistors  

E-print Network

We report on the effects of ionizing radiation on 65nm CMOS transistors held at approximately -20C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

Krohn, M; Cumalat, J P; Wagner, S R; Christian, D C; Deptuch, G; Fahim, F; Hoff, J; Shenai, A

2015-01-01

129

Radiation Tolerance of 65nm CMOS Transistors  

E-print Network

We report on the effects of ionizing radiation on 65nm CMOS transistors held at approximately -20C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

M. Krohn; B. Bentele; J. P. Cumalat; S. R. Wagner; D. C. Christian; G. Deptuch; F. Fahim; J. Hoff; A. Shenai

2015-01-23

130

Transistor matching in analog CMOS applications  

Microsoft Academic Search

This paper gives an overview of MOSFET mismatch effects that form a performance\\/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit design is discussed. Mismatch effects gain importance as critical dimensions and CMOS power supply voltages decrease

Marcel J. M. Pelgrom; Hans P. Tuinhout; Maarten Vertregt

1998-01-01

131

Complementary Metalâ??Oxideâ??Semiconductor (CMOS) Simulation  

NSDL National Science Digital Library

This resource is an Interactive Complementary metalâ??oxideâ??semiconductor (CMOS) simulation. All the different variables can be modified to represent different aspects of this simulation. Results are presented once the calculations are made. This can be a useful resource for those involved in engineering or physics.

132

Switch level optimization for CMOS circuits  

E-print Network

In this report, 'Input vs Path Matrix 'Techique' and 'Node vs Input Matrix Technique' techniques for reducing transistor count in the pull-up and the pull-down array of CMOS circuits are proposed. Also, algorithms for optimization of both the pull...

Chugh, Pankaj Pravinkumar

1997-01-01

133

Minimizing power consumption in digital CMOS circuits  

Microsoft Academic Search

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology

ANANTHA P. CHANDRAKASAN; ROBERT W. BRODERSEN

1995-01-01

134

Quadrature Generation Techniques in CMOS Relaxation Oscillators  

E-print Network

) A differential VCO running at twice the desired operating frequency followed by a divide-by-2 circuit: Design. These are inspired by similar techniques used to couple LC-VCO's in quadrature. The QRXO's are designed in a UMC 0.4GHz quadrature oscillators are designed and simulated in a UMC 0.18µm CMOS process. The shunt

Krishnapura, Nagendra

135

Neural Networks in CMOS Manufacturing: Some Examples  

Microsoft Academic Search

The focus of this paper will be on two neural network models for plasma aided CMOS manufacturing. Both models were developed with strict statistical cross- validation and applied to real world applications. A plasma neural network gate etch controller has shown a 20% improvement in throughput in wafer processing by eliminating a set-up step, and has reduced the variance of

Edward A. Rietman

1998-01-01

136

Heavy ion induced snapback in CMOS devices  

Microsoft Academic Search

Single-event-snapback (SES) susceptibilities of selected CMOS devices to heavy ions were measured using N, Ne, Ar, Cu, and Kr ion beams. Like latchup, snapback was observed macroscopically by detecting the abnormally high bias current condition. However, the snapback susceptibility characteristics differed from those of latchup, and consequently it was possible to measure the snapback responses unambiguously. The responses are expressed

R. Koga; W. A. Kolasinski

1989-01-01

137

Low energy CMOS for space applications  

NASA Astrophysics Data System (ADS)

The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

Panwar, Ramesh; Alkalaj, Leon

138

77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...  

Federal Register 2010, 2011, 2012, 2013, 2014

...COMMISSION [Docket No. 2895] Certain CMOS Image Sensors and Products Containing Same...received a complaint entitled Certain CMOS Image Sensors and Products Containing Same...States after importation of certain CMOS image sensors and products containing...

2012-05-07

139

77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...  

Federal Register 2010, 2011, 2012, 2013, 2014

...Investigation No. 337-TA-846] Certain CMOS Image Sensors and Products Containing Same...States after importation of certain CMOS image sensors and products containing same...States after importation of certain CMOS image sensors and products containing...

2012-06-06

140

270GHz SiGe BiCMOS manufacturing process platform for mmWave applications  

NASA Astrophysics Data System (ADS)

TowerJazz has been offering the high volume commercial SiGe BiCMOS process technology platform, SBC18, for more than a decade. In this paper, we describe the TowerJazz SBC18H3 SiGe BiCMOS process which integrates a production ready 240GHz FT / 270 GHz FMAX SiGe HBT on a 1.8V/3.3V dual gate oxide CMOS process in the SBC18 technology platform. The high-speed NPNs in SBC18H3 process have demonstrated NFMIN of ~2dB at 40GHz, a BVceo of 1.6V and a dc current gain of 1200. This state-of-the-art process also comes with P-I-N diodes with high isolation and low insertion losses, Schottky diodes capable of exceeding cut-off frequencies of 1THz, high density stacked MIM capacitors, MOS and high performance junction varactors characterized up to 50GHz, thick upper metal layers for inductors, and various resistors such as low value and high value unsilicided poly resistors, metal and nwell resistors. Applications of the SBC18H3 platform for millimeter-wave products for automotive radars, phased array radars and Wband imaging are presented.

Kar-Roy, Arjun; Preisler, Edward J.; Talor, George; Yan, Zhixin; Booth, Roger; Zheng, Jie; Chaudhry, Samir; Howard, David; Racanelli, Marco

2011-11-01

141

Ultra-fast high-resolution hybrid and monolithic CMOS imagers in multi-frame radiography  

NASA Astrophysics Data System (ADS)

A new burst-mode, 10-frame, hybrid Si-sensor/CMOS-ROIC FPA chip has been recently fabricated at Teledyne Imaging Sensors. The intended primary use of the sensor is in the multi-frame 800 MeV proton radiography at LANL. The basic part of the hybrid is a large (48×49 mm2) stitched CMOS chip of 1100×1100 pixel count, with a minimum shutter speed of 50 ns. The performance parameters of this chip are compared to the first generation 3-frame 0.5-Mpixel custom hybrid imager. The 3-frame cameras have been in continuous use for many years, in a variety of static and dynamic experiments at LANSCE. The cameras can operate with a per-frame adjustable integration time of ~ 120ns-to- 1s, and inter-frame time of 250ns to 2s. Given the 80 ms total readout time, the original and the new imagers can be externally synchronized to 0.1-to-5 Hz, 50-ns wide proton beam pulses, and record up to ~1000-frame radiographic movies typ. of 3-to-30 minute duration. The performance of the global electronic shutter is discussed and compared to that of a high-resolution commercial front-illuminated monolithic CMOS imager.

Kwiatkowski, Kris; Douence, Vincent; Bai, Yibin; Nedrow, Paul; Mariam, Fesseha; Merrill, Frank; Morris, Christopher L.; Saunders, Andy

2014-09-01

142

High-performance CMOS image sensors at BAE SYSTEMS Imaging Solutions  

NASA Astrophysics Data System (ADS)

In this paper, we present an overview of high-performance CMOS image sensor products developed at BAE SYSTEMS Imaging Solutions designed to satisfy the increasingly challenging technical requirements for image sensors used in advanced scientific, industrial, and low light imaging applications. We discuss the design and present the test results of a family of image sensors tailored for high imaging performance and capable of delivering sub-electron readout noise, high dynamic range, low power, high frame rates, and high sensitivity. We briefly review the performance of the CIS2051, a 5.5-Mpixel image sensor, which represents our first commercial CMOS image sensor product that demonstrates the potential of our technology, then we present the performance characteristics of the CIS1021, a full HD format CMOS image sensor capable of delivering sub-electron read noise performance at 50 fps frame rate at full HD resolution. We also review the performance of the CIS1042, a 4-Mpixel image sensor which offers better than 70% QE @ 600nm combined with better than 91dB intra scene dynamic range and about 1 e- read noise at 100 fps frame rate at full resolution.

Vu, Paul; Fowler, Boyd; Liu, Chiao; Mims, Steve; Balicki, Janusz; Bartkovjak, Peter; Do, Hung; Li, Wang

2012-07-01

143

Design of an ultra low power CMOS pixel sensor for a future neutron personal dosimeter  

SciTech Connect

Despite a continuously increasing demand, neutron electronic personal dosimeters (EPDs) are still far from being completely established because their development is a very difficult task. A low-noise, ultra low power consumption CMOS pixel sensor for a future neutron personal dosimeter has been implemented in a 0.35 {mu}m CMOS technology. The prototype is composed of a pixel array for detection of charged particles, and the readout electronics is integrated on the same substrate for signal processing. The excess electrons generated by an impinging particle are collected by the pixel array. The charge collection time and the efficiency are the crucial points of a CMOS detector. The 3-D device simulations using the commercially available Synopsys-SENTAURUS package address the detailed charge collection process. Within a time of 1.9 {mu}s, about 59% electrons created by the impact particle are collected in a cluster of 4 x 4 pixels with the pixel pitch of 80 {mu}m. A charge sensitive preamplifier (CSA) and a shaper are employed in the frond-end readout. The tests with electrical signals indicate that our prototype with a total active area of 2.56 x 2.56 mm{sup 2} performs an equivalent noise charge (ENC) of less than 400 e - and 314 {mu}W power consumption, leading to a promising prototype. (authors)

Zhang, Y.; Hu-Guo, C.; Husson, D.; Hu, Y. [Institut Pluridisplinaire Hubert Curien IPHC, Univ. of Strasbourg, CNRS/IN2P3, 23 Rue du Loess, 67037 Strasbourg (France)

2011-07-01

144

Multiple-samples-method enabling high dynamic range imaging for high frame rate CMOS image sensor by FPGA and co-processor  

NASA Astrophysics Data System (ADS)

We present results from a prototype CMOS camera system implementing a multiple sampled pixel level algorithm ("Last Sample Before Saturation") to create High-Dynamic Range (HDR) images that approach the dynamic range of CCDs. The system is built around a commercial 1280 × 1024 CMOS image sensor with 10-bits per pixel and up to 500 Hz full frame rate with higher frame rates available through windowing. We analyze imagery data collected at room temperature for SNR versus photocurrent, among other figures of merit. Results conform to expectations of a model that uses only dark current, read noise, and photocurrent as input parameters.

Jacquot, Blake C.; Johnson-Williams, Nathan

2014-09-01

145

Radiation-hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Technology  

NASA Astrophysics Data System (ADS)

Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown.

Miucci, A.; Gonella, L.; Hemperek, T.; Hügging, F.; Krüger, H.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Backhaus, M.; Capeans, M.; Feigl, S.; Nessi, M.; Pernegger, H.; Ristic, B.; Gonzalez-Sevilla, S.; Ferrere, D.; Iacobucci, G.; La Rosa, A.; Muenstermann, D.; George, M.; Große-Knetter, J.; Quadt, A.; Rieger, J.; Weingarten, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.; Kreidl, C.; Peric, I.; Breugnon, P.; Pangaud, P.; Godiot-Basolo, S.; Fougeron, D.; Bompard, F.; Clemens, J. C.; Liu, J.; Barbero, M.; Rozanov, A.; HV-CMOS Collaboration

2014-05-01

146

Correct CMOS IC defect models for quality testing  

NASA Technical Reports Server (NTRS)

Leading edge, high reliability, and low escape CMOS IC test practices have now virtually removed the stuck-at fault model and replaced it with more defect-orientated models. Quiescent power supply current testing (I(sub DDQ)) combined with strategic use of high speed test patterns is the recommended approach to zero defect and high reliability testing goals. This paper reviews the reasons for the change in CMOS IC test practices and outlines an improved CMOS IC test methodology.

Soden, Jerry M.; Hawkins, Charles F.

1993-01-01

147

Fundamental performance differences of CMOS and CCD imagers: part V  

NASA Astrophysics Data System (ADS)

Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

2013-02-01

148

CMOS compatible nanoscale nonvolatile resistance switching memory.  

PubMed

We report studies on a nanoscale resistance switching memory structure based on planar silicon that is fully compatible with CMOS technology in terms of both materials and processing techniques employed. These two-terminal resistance switching devices show excellent scaling potential well beyond 10 Gb/cm2 and exhibit high yield (99%), fast programming speed (5 ns), high on/off ratio (10(3)), long endurance (10(6)), retention time (5 months), and multibit capability. These key performance metrics compare favorably with other emerging nonvolatile memory techniques. Furthermore, both diode-like (rectifying) and resistor-like (nonrectifying) behaviors can be obtained in the device switching characteristics in a controlled fashion. These results suggest that the CMOS compatible, nanoscale Si-based resistance switching devices may be well suited for ultrahigh-density memory applications. PMID:18217785

Jo, Sung Hyun; Lu, Wei

2008-02-01

149

Advances in fully CMOS integrated photonic devices  

NASA Astrophysics Data System (ADS)

The complete integration of photonic devices into a CMOS process flow will enable low cost photonic functionality within electronic circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, Cornell University, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application specific, electronic-photonic integrated circuit (AS-EPIC). The first phase of the program was dedicated to photonics device designs, CMOS process flow integration, and basic electronic functionality. We will present the latest results on the performance of waveguide integrated detectors, and tunable optical filters.

Michel, Jurgen; Liu, J. F.; Ahn, D. H.; Sparacin, D.; Sun, R.; Hong, C. Y.; Giziewicz, W. P.; Beals, M.; Kimerling, L. C.; Kopa, A.; Apsel, A. B.; Rasras, M. S.; Gill, D. M.; Patel, S. S.; Tu, K. Y.; Chen, Y. K.; White, A. E.; Pomerene, A.; Carothers, D.; Grove, M. J.

2007-02-01

150

Heavy ion induced snapback in CMOS devices  

SciTech Connect

Single event snapback (SES) susceptibilities of selected CMOS devices to heavy ions were measured, first using N, Ne, Ar, Cu and Kr ion beams. Like latchup, snapback was observed macroscopically by detecting the abnormally high bias current condition. However, the snapback susceptibility characteristics differed from those of latchup, and consequently the authors could unambiguously measure the snapback responses. The responses are expressed in terms of the cross-section for varying bias and the stopping power of ions. Test data indicate that CMOS devices with rather long channel lengths (on the order of three microns) are free from SES when operated at about 5 volts. However, present-day theories have predicted that this regenerative breakdown mode of upset may become very important at 5 volts or below for devices with extremely short n-channel lengths.

Koga, R.; Kolasinski, W.A. (Space Sciences Lab., The Aerospace Corp., El Segundo, CA (US))

1989-12-01

151

CMOS active pixel image sensors fabricated using a 1.8-V, 0.25-?m CMOS technology  

Microsoft Academic Search

This paper reports the experimental results of the first CMOS active pixel image sensors (APS) fabricated using a high-performance 1.8-V, 0.25-?m CMOS logic technology. No process modifications were made to the CMOS logic technology so that the impact of device scaling on the image sensing performance can be studied. This paper highlights the device and process design considerations required to

Hon-Sum Philip Wong; Richard T. Chang; E. Crabbe; P. D. Agnello

1998-01-01

152

Analog Circuit Design in Nanoscale CMOS Technologies  

Microsoft Academic Search

As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic

Lanny L. Lewyn; Trond Ytterdal; Carsten Wulff; Kenneth Martin

2009-01-01

153

Extremely scaled silicon nano-CMOS devices  

Microsoft Academic Search

Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key

Leland Chang; Yang-kyu Choi; Daewon Ha; PUSHKAR RANADE; Shiying Xiong; JEFFREY BOKOR; Tsu-Jae King

2003-01-01

154

CMOS pixel for subretinal implantable prothesis  

Microsoft Academic Search

Visual capabilities recovery for some kind of illness is possible through subretinal implantable device stimulation. Two possible architectures for retinal pixel are proposed, fabricated in 0.35 ?m CMOS and compared, including evaluation of electronic response on a human-tissue-like interface. In these solutions, power consumption has been proved to be dominated by electrode stimulation and, in normal light condition, typical consumption

M. Mazza; Philippe Renaud; A. M. Ionescu

2003-01-01

155

CMOS Camera Array With Onboard Memory  

NASA Technical Reports Server (NTRS)

A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

Gat, Nahum

2009-01-01

156

Advanced CMOS Radiation Effects Testing and Analysis  

NASA Technical Reports Server (NTRS)

Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

2014-01-01

157

Advanced CMOS Radiation Effects Testing Analysis  

NASA Technical Reports Server (NTRS)

Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, Kenneth P.; Gordon, Michael S.; LaBel, Kenneth A.; Schwank, James R.; Dodds, Nathaniel A.; Castaneda, Carlos M.; Berg, Melanie D.; Kim, Hak S.; Phan, Anthony M.; Seidleck, Christina M.

2014-01-01

158

New CMOS tunable transconductor for filtering applications  

Microsoft Academic Search

A CMOS high-performance transconductor useful for IC filtering applications is presented. It is based on a feedback source-follower configuration using a resistor to achieve linear voltage-to-current conversion. Tunability is attained through variable-gain current mirrors. A balanced integrator was designed in a 0.8-?m technology and simulations are given which show tunability over a factor of 20 and THD of at most

G. Palmisano; Salvatore Pennisi

2001-01-01

159

CMOS on local SOI using SIMOX technology  

Microsoft Academic Search

A new local SOI technique using SIMOX technology has been developed. Using this technique, it is possible to implement SOI regions and bulk regions selectively on the same chip, starting from a conventional SIMOX substrate, and achieve a planar surface of the substrate. The electrical characteristics of CMOS devices composed of n-MOSFETs\\/bulk and p-MOSFETs\\/SIMOX fabricated with this technique are described.

S. Matsumoto; T. Ohno; K. Izumi

1987-01-01

160

Battery-powered digital CMOS design  

Microsoft Academic Search

In this paper we study tradeoffs between energy dissipation and delay in battery-powered digital CMOS designs. In contrast to previous work, we adopt an integrated model of the VLSI circuit and the battery sub-system that powers it. We show that accounting for the dependence of battery capacity on the average discharge current changes shape of the energy-delay trade-off curve and

Massoud Pedram; Qing Wu

1999-01-01

161

Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design  

PubMed Central

In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory. PMID:24180626

2013-01-01

162

Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design  

NASA Astrophysics Data System (ADS)

In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.

Shin, SangHak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

2013-11-01

163

Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.  

PubMed

In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory. PMID:24180626

Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

2013-01-01

164

Space Commercialization  

NASA Technical Reports Server (NTRS)

A robust and competitive commercial space sector is vital to continued progress in space. The United States is committed to encouraging and facilitating the growth of a U.S. commercial space sector that supports U.S. needs, is globally competitive, and advances U.S. leadership in the generation of new markets and innovation-driven entrepreneurship. Energize competitive domestic industries to participate in global markets and advance the development of: satellite manufacturing; satellite-based services; space launch; terrestrial applications; and increased entrepreneurship. Purchase and use commercial space capabilities and services to the maximum practical extent Actively explore the use of inventive, nontraditional arrangements for acquiring commercial space goods and services to meet United States Government requirements, including measures such as public-private partnerships, . Refrain from conducting United States Government space activities that preclude, discourage, or compete with U.S. commercial space activities. Pursue potential opportunities for transferring routine, operational space functions to the commercial space sector where beneficial and cost-effective.

Martin, Gary L.

2011-01-01

165

CMOS arrays as chemiluminescence detectors on microfluidic devices.  

PubMed

A simple, low-cost process to integrate complementary metal oxide semiconductor array detectors (CMOSAD) for chemiluminescence is presented, evaluated, and applied to the determination of nitrite in ground water samples. CMOS arrays of different brands (obtained from commercial image sensors) were adapted as chemiluminescence detectors on microfluidic devices. The performance of the CMOSADs was evaluated in the visible zone of the spectrum using a tungsten halogen lamp as light source. Intrinsic parameters assessed included signal stability, spectral response, dark current, and signal-to-noise ratio. Thereafter, the CMOSADs were integrated on microfluidic devices and their performances in quantitative analysis were assessed with the chemiluminometric reaction of hydrogen peroxide with luminol, catalyzed with hexacyanoferrate (III). The parameters assessed were sensitivity, linear range, detection limit, reproducibility, correlation coefficient of the calibration curves, and baseline drift during measurements. The CMOSAD with the best performance was selected to assess the applicability of the developed microfluidic devices with the integrated detector. The microfluidic system permitted the determination of nitrite with both good precision and good recovery values in the analysis of ground water samples. Integration was easily achieved and enabled the development of a simple, low-cost, and feasible alternative to conventional detectors. PMID:20177663

Rodrigues, Eunice R G O; Lapa, Rui A S

2010-05-01

166

CMOS solid state photomultipliers for ultra-low light levels  

NASA Astrophysics Data System (ADS)

Detection of single photons is crucial for a number of applications. Geiger photodiodes (GPD) provide large gains with an insignificant amount of multiplication noise exclusively from the diode. When the GPD is operated above the reverse bias breakdown voltage, the diode can avalanche due to charged pairs generated from random noise (typically thermal) or incident photons. The GPD is a binary device, as only one photon is needed to trigger an avalanche, regardless of the number of incident photons. A solid-state photomultiplier (SSPM) is an array of GPDs, and the output of the SSPM is proportional to the incident light intensity, providing a replacement for photomultiplier tubes. We have developed CMOS SSPMs using a commercial fabrication process for a myriad of applications. We present results on the operation of these devices for low intensity light pulses. The data analysis provides a measured of the junction capacitance (~150 fF), which affects the rise time (~2 ns), the fall time (~32 ns), and gain (>106). Multipliers for the cross talk and after pulsing are given, and a consistent picture within the theory of operation of the expected dark current and photodetection efficiency is demonstrate. Enhancement of the detection efficiency with respect to the quantum efficiency at unity gain for shallow UV photons is measured, indicating an effect due to fringe fields within the diode structure. The signal and noise terms have been deconvolved from each other, providing the fundamental model for characterizing the behavior at low-light intensities.

Johnson, Erik B.; Stapels, Christopher J.; Chen, Xaio Jie; Whitney, Chad; Chapman, Eric C.; Alberghini, Guy; Rines, Rich; Augustine, Frank; Christian, James

2011-05-01

167

Process Compensated CMOS Temperature Sensor for Microprocessor Application  

E-print Network

Process Compensated CMOS Temperature Sensor for Microprocessor Application Yaesuk Jeong and Farrokh consumption is 478uW. I. INTRODUCTION With microprocessors scaling to higher performance and faster speed in the microprocessor to monitor its thermal distribution. Many CMOS based temperature sensors have been reported

Ayazi, Farrokh

168

Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors  

PubMed Central

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Huang, Yue; Mason, Andrew J.

2013-01-01

169

CMOS phototransistor device : A total solution for skin whitening assays  

Microsoft Academic Search

Three skin whitening assays combining the semiconductor technology was demonstrated for screening the drug candidate and discussing the mechanisms of melanogenesis in medical cosmetics. We proposed a miniaturized photometric system using complementary metal oxide semiconductor (CMOS) phototransistor as a detector with high sensitivity. The CMOS phototransistor was a small, portable optoelectronic device with enlarged depletion region of the outer Nwell\\/Pwell

Yen-Pei Lui; Yu-Wei Chang; Ming-Yu Lin; Jiann-Shiun Kao; Yang-Tung Huang; Yuh-Shyong Yang

2009-01-01

170

Fully integrated CMOS and high voltage compatible RF MEMS technology  

Microsoft Academic Search

In this paper, a fully integrated CMOS and high voltage compatible RF MEMS (radio frequency microelectromechanical systems) technology is proposed and demonstrated for the first time. The high performance RF MEMS switch, high voltage MOSFET, and CMOS devices are all obtained using a simple process. The fabricated high voltage device has a breakdown voltage of over 35V. The MEMS capacitive

Lingpeng Guan; J. K. O. Sin; Haitao Liu; Zhibin Xiong

2004-01-01

171

GaAs MQW modulators integrated with silicon CMOS  

Microsoft Academic Search

We demonstrate integration of GaAs-AlGaAs multiple quantum well modulators to silicon CMOS circuitry via flip-chip solder-bonding followed by substrate removal. We obtain 95% device yield for 32×32 arrays of devices with 15 micron solder pads. We show operation of a simple circuit composed of a modulator and a CMOS transistor

K. W. Goossen; J. A. Walker; L. A. D'Asaro; S. P. Hui; B. Tseng; R. Leibenguth; D. Kossives; D. D. Bacon; D. Dahringer; L. M. F. Chirovsky; A. L. Lentine; D. A. B. Miller

1995-01-01

172

Low-Power Strategies for High-Performance CMOS Circuits  

Microsoft Academic Search

Power dissipation has become one of the most critical CMOS design parameters. It will be shown that even under constraints on the supply voltage there are effective strategies for the reduction of power dissipation on the different levels of the CMOS design process. Enforcing localization, using redundant number representations and applying an optimal degree of pipelining will be demonstrated as

Tobias G. Noll; RWTH Aachen Rogowski-Institu

1994-01-01

173

Performance review of integrated CMOS VCO circuits for wireless communications  

Microsoft Academic Search

This paper reviews monolithically integrated CMOS voltage controlled oscillators (VCO) for wireless communications. The key challenges in VCO development include: design of a high Q tank on a substrate tailored for CMOS, multiband operation using a single VCO, enhanced manufacturability using digital frequency tuning, and optimization of the overall VCO topology for low power operation. Recent developments in each of

M. Rachedine; D. Kaczman; A. Das; M. Shah; J. Mondal; C. Shurboff

2003-01-01

174

RF power potential of 45 nm CMOS technology  

E-print Network

This paper presents the first measurements of the RF power performance of 45 nm CMOS devices with varying device widths and layouts. We find that 45 nm CMOS can deliver a peak output power density of around 140 mW/mm with ...

Putnam, Christopher

175

CMOS compatible wafer scale adhesive bonding for circuit transfer  

Microsoft Academic Search

Reports on a transfer technique for CMOS circuits based on a newly developed bonding technique, namely wafer scale adhesive bonding using epoxies. The circuit transfer sequence consists of three steps: bonding a CMOS processed SIMOX wafer to a Pyrex glass wafer, thinning the SIMOX wafer down to the buried oxide and exposing the contact pads. A test chip was designed

S. van der Green; Maartein Rosmeulen; Philippe Jansen; Kris Baert; Ludo Deferm

1997-01-01

176

RTD–CMOS Pipelined Networks for Reduced Power Consumption  

Microsoft Academic Search

The incorporation of resonant tunneling diodes (RTDs) into III\\/V transistor technologies has shown an improved circuit performance, producing higher circuit speed, reduced com- ponent count, and\\/or lower power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD- CMOS) is an area of active research. Although some studies have concentrated on evaluating the advantages of this incorporation, more work

Juan Núñez; María J. Avedillo; José M. Quintana

2011-01-01

177

A CMOS fault extractor for inductive fault analysis  

Microsoft Academic Search

The inductive fault analysis (IFA) method is presented and a description is given of the CMOS fault extraction program FXT. The IFA philosophy is to consider the causes of faults (manufacturing defects) and then simulate these causes to find the faults that are likely to occur in a circuit. FXT automates IFA for a CMOS technology by generating a list

F. Joel Ferguson; John Paul Shen

1988-01-01

178

High responsivity CMOS imager pixel implemented in SOI technology  

NASA Technical Reports Server (NTRS)

Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

2000-01-01

179

Quiescent power supply current measurement for CMOS IC defect detection  

Microsoft Academic Search

Quiescent power supply current (IDDQ) measurement is a very effective technique for detecting in CMOS integrated circuits (ICs). This technique uniquely detects certain CMOS IC defects such as gate oxide shorts, defective p-n junctions, and parasitic transistor leakage. In addition, IDDQ monitoring will detect all stuck-at faults with the advantage of using a node toggling test set that has fewer

CHARLES F. HAWKINS; JERRY M. SODEN; RONALD R. FRITZEMEIER; LUTHER K. HORNING

1989-01-01

180

A CMOS Imager for DNA Detection Samir Parikh  

E-print Network

University of Toronto Abstract DNA Microarrays are used to analyse the DNA sequence of an organism at each of the spots on a DNA microarray. This thesis examines the feasibility of using standard CMOS technology for imaging a DNA microarray. It explains the design of a CMOS Imager and the construction

Chow, Paul

181

Plasmonic Color Filters for CMOS Image Sensor Applications Sozo Yokogawa,,,  

E-print Network

Plasmonic Color Filters for CMOS Image Sensor Applications Sozo Yokogawa,,,§ Stanley P. Burgos to requirements for plasmonic color filters designed for state-of-the-art Si CMOS image sensors. The hole arrays at the primary colors of red, green, and blue. Hole array plasmonic filters show peak transmission in the 40

Atwater, Harry

182

Advances in CMOS Solid-state Photomultipliers for Scintillation Detector Applications  

PubMed Central

Solid-state photomultipliers (SSPMs) are a compact, lightweight, potentially low-cost alternative to a photomultiplier tube for a variety of scintillation detector applications, including digital-dosimeter and medical-imaging applications. Manufacturing SSPMs with a commercial CMOS process provides the ability for rapid prototyping, and facilitates production to reduce the cost. RMD designs CMOS SSPM devices that are fabricated by commercial foundries. This work describes the characterization and performance of these devices for scintillation detector applications. This work also describes the terms contributing to device noise in terms of the excess noise of the SSPM, the binomial statistics governing the number of pixels triggered by a scintillation event, and the background, or thermal, count rate. The fluctuations associated with these terms limit the resolution of the signal pulse amplitude. We explore the use of pixel-level signal conditioning, and characterize the performance of a prototype SSPM device that preserves the digital nature of the signal. In addition, we explore designs of position-sensitive SSPM detectors for medical imaging applications, and characterize their performance. PMID:25540471

Christian, James F.; Stapels, Christopher J.; Johnson, Erik B.; McClish, Mickel; Dokhale, Purushotthom; Shah, Kanai S.; Mukhopadhyay, Sharmistha; Chapman, Eric; Augustine, Frank L.

2014-01-01

183

Advances in CMOS solid-state photomultipliers for scintillation detector applications  

NASA Astrophysics Data System (ADS)

Solid-state photomultipliers (SSPMs) are a compact, lightweight, potentially low-cost alternative to a photomultiplier tube for a variety of scintillation detector applications, including digital-dosimeter and medical-imaging applications. Manufacturing SSPMs with a commercial CMOS process provides the ability for rapid prototyping, and facilitates production to reduce the cost. RMD designs CMOS SSPM devices that are fabricated by commercial foundries. This work describes the characterization and performance of these devices for scintillation detector applications. This work also describes the terms contributing to device noise in terms of the excess noise of the SSPM, the binomial statistics governing the number of pixels triggered by a scintillation event, and the background, or thermal, count rate. The fluctuations associated with these terms limit the resolution of the signal pulse amplitude. We explore the use of pixel-level signal conditioning, and characterize the performance of a prototype SSPM device that preserves the digital nature of the signal. In addition, we explore designs of position-sensitive SSPM detectors for medical imaging applications, and characterize their performance.

Christian, James F.; Stapels, Christopher J.; Johnson, Erik B.; McClish, Mickel; Dokhale, Purushotthom; Shah, Kanai S.; Mukhopadhyay, Sharmistha; Chapman, Eric; Augustine, Frank L.

2010-12-01

184

A sampled-data CMOS analog adaptive filter  

NASA Astrophysics Data System (ADS)

A fully analog sampled-data CMOS adaptive filter realizing the LMS (least mean squared) adaptation on a four-tap FIR (finite impulse response) filter has been fabricated. The system uses clocked CMOS sampled-data storage, four-quadrant CMOS analog multipliers, and CMOS op amp-based arithmetic modules. For achieving higher output sampling rates and for allowing modularity, a parallel architecture has been used, implementing each filter tap separately instead of using a single time-multiplexed processing unit. The prototype chip was fabricated using double-metal double-poly 2-micron CMOS P-well technology, occupying an area of 4.0 sq mm and using +/- 5-V power supplies.

Gomez, Gabriel; Siferd, Raymond

185

Development of a RF Bipolar Transistor in a Standard 0.35m CMOS Technology  

E-print Network

Development of a RF Bipolar Transistor in a Standard 0.35µm CMOS Technology I-Shan Michael Sun-0021, Japan ABSTRACT A RF Bipolar Transistor integrated to a standard 0.35µm CMOS process is presented compared to previously published BiCMOS technologies. Key Words 0.35µm CMOS Technology, RF Silicon Bipolar

Ng, Wai Tung

186

A fully integrated programmable dual-band RF filter based on electrically and mechanically coupled CMOS-MEMS resonators  

NASA Astrophysics Data System (ADS)

In this paper, a novel fully integrated CMOS-MEMS filter implemented on a commercial CMOS technology is presented. The combination of mechanical and electrical coupling is used to enhance the response of the band pass filter. In particular, a 20 dB shape factor as low as 2 and a 35 dB stopband rejection are achieved. Moreover, the topology of the device allows obtaining a dual-bandpass filter behavior, presenting a tunable bandwidth and a deep notch between bands. Results show a dual-band filter with a 22 dB inner stopband rejection, center frequencies at 27.5 and 27.8 MHz, respectively, and a 0.6% relative bandwidth.

Giner, J.; Uranga, A.; Muñóz-Gamarra, J. L.; Marigó, E.; Barniol, N.

2012-05-01

187

Theoretical performance analysis for CMOS based high resolution detectors.  

PubMed

High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 ?m thick HL-type CsI phosphor, a 50 ?m-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive. PMID:24353390

Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

2013-03-01

188

Tabasco Commercials  

Microsoft Academic Search

Four commercials for Tabasco green pepper sauce produced in film resolution for cinema release in Europe. Character modelling and animation using 3D Studio Max with Character Studio, compositing of various rendered layers in After Effects and Shake. Copyright held by creator.

2001-01-01

189

Commercial applications  

NASA Technical Reports Server (NTRS)

Viewgraphs on commercial applications of fuzzy logic in Japan are presented. Topics covered include: suitable application area of fuzzy theory; characteristics of fuzzy control; fuzzy closed-loop controller; Mitsubishi heavy air conditioner; predictive fuzzy control; the Sendai subway system; automatic transmission; fuzzy logic-based command system for antilock braking system; fuzzy feed-forward controller; and fuzzy auto-tuning system.

Togai, Masaki

1990-01-01

190

Commercial Art.  

ERIC Educational Resources Information Center

This curriculum guide provides materials for a competency-based course in commercial art at the secondary level. The curriculum design uses the curriculum infused model for the teaching of basic skills as part of vocational education and demonstrates the relationship of vocationally related skills to communication, mathematics, and science…

Vassallo, Thomas

191

Nanomechanical switch for integration with CMOS logic.  

SciTech Connect

We designed, fabricated and measured the performance of nanoelectromechanical (NEMS) switches. Initial data are reported with one of the switch designs having a measured switching time of 400 ns and an operating voltage of 5 V. The switches operated laterally with unmeasurable leakage current in the 'off' state. Surface micromachining techniques were used to fabricate the switches. All processing was CMOS compatible. A single metal layer, defined by a single mask step, was used as the mechanical switch layer. The details of the modeling, fabrication and testing of the NEMS switches are reported.

Nordquist, Christopher Daniel; Wolfley, Steven L.; Baker, Michael Sean; Czaplewski, David A.; Wendt, Joel Robert; Kraus, Garth Merlin; de Boer, Maarten Pieter; Patrizi, Gary A.

2008-11-01

192

CMOS-integrated geometrically tunable optical filters.  

PubMed

We present a method for producing monolithically integrated complementary metal-oxide-semiconductor (CMOS) optical filters with different and customer-specific responses. The filters are constituted by a Fabry-Perot resonator formed by two Bragg mirrors separated by a patterned cavity. The filter response can be tuned by changing the geometric parameters of the patterning, and consequently the cavity effective refractive index. In this way, many different filters can be produced at once on a single chip, allowing multichanneling. The filter has been designed, produced, and characterized. The results for a chip with 24 filters are presented. PMID:23478769

Lerose, Damiana; Hei, Evie Kho Siaw; Ching, Bong Ching; Sterger, Martin; Yaw, Liau Chu; Schulze, Frank Michael; Schmidt, Frank; Schmidt, Andrei; Bach, Konrad

2013-03-10

193

Nanoscale Materials and Structures for CMOS Devices  

NSDL National Science Digital Library

This presentation was given at the Arizona Nanotechnology Conference in March of 2008 by Dr. Stefan Zollner, Freescale Semiconductor, USA. The focus is on problems with planar CMOS and their solutions. These solutions consist of: SOI or FINFET to reduce source and drain leakage, high mobility channel materials to increase drive current, new silicide materials to reduce source and drain contact resistance, metal oxides with high dielectric constants to reduce gate leakage and metal gate electrodes to reduce gate depletion. Overall, the presentation is filled with images and diagrams allowing it to flow easily. This is an excellent resource for anyone looking to learn more about nanotechnology and its applications.

Zollner, Stefan

194

Monolithic CMOS imaging x-ray spectrometers  

NASA Astrophysics Data System (ADS)

The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15?m, high resistivity custom (~30k?-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16?m pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40?V/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9?m epitaxial silicon and have a 1k by 1k format. They incorporate similar 16?m pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and spectrally resolved without saturation. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting x-ray astronomy. These features include read noise, x-ray spectral response and quantum efficiency. Funding for this work has been provided in large part by NASA Grant NNX09AE86G and a grant from the Betty and Gordon Moore Foundation.

Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

2014-07-01

195

Cmos-Compatible High Voltage Integrated Circuits.  

NASA Astrophysics Data System (ADS)

Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5 ?m CMOS process are first studied. High -voltage n- and p-channel transistors with breakdown voltages of 50 V and 190 V respectively, have been fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed and their accuracy verified by comparison with the experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS -bipolar concept, is proposed and implemented. The device, which can be implemented using a standard CMOS process, is capable of handling high current densities without latching. The IBT exhibits a fivefold increase in the current density compared to the lateral DMOS transistor. A simple technique to improve the breakdown voltage and the switching speed of the IBT, without significantly compromising its current carrying capability, is also presented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed. High-voltage lateral DMOS transistors and merged MOS-bipolar devices such as the LIGT and IBT with breakdown voltages of 400 V, have been fabricated using this process. The IBTs, which in addition to having high breakdown voltages have high current handling capabilities as well as high switching speeds, offer better performance than the LIGTs. In addition, the IBT, because it doesn't latch-up, is a more reliable device than the LIGT. The processes and devices developed in this work have potential applications in the telecommunications and display driver fields.

Parpia, Zahir

196

Vertical Isolation for Photodiodes in CMOS Imagers  

NASA Technical Reports Server (NTRS)

In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

Pain, Bedabrata

2008-01-01

197

Commercial Norms, Commercial Codes, and International Commercial Arbitration  

E-print Network

The article defends the incorporation of commercial norms into commercial codes, through provisions such as statute 1-205 of the Uniform Commercial Code. It finds significant reliance on trade usages in international ...

Drahozal, Christopher R.

2000-01-01

198

Far ultraviolet sensitivity of silicon CMOS sensors  

NASA Astrophysics Data System (ADS)

We describe vacuum ultraviolet sensitivity measurements of a new high performance silicon-based CMOS sensor from Teledyne Imaging Sensors. These sensors do not require the high voltages of MCP detectors, making them a lower mass and power alternative to the more mature MCP technology. These devices demonstrate up to 40 percent quantum efficiency at vacuum ultraviolet wavelengths, either meeting or greatly exceeding 10 percent quantum efficiency across the entire 100-200 nm wavelength region. As with similar visible sensitive devices, backside illumination results in a higher quantum efficiency than frontside illumination. Measurements of the vacuum ultraviolet sensitivity of the Teledyne silicon PIN detectors were made by directing a known intensity of ultraviolet light at discrete wavelengths onto the test detectors and reading out the resulting photocurrent. The sensitivity of the detector at a given wavelength was then calculated from the intensity and wavelength of the incoming light and the relative photodiode to NIST-traceable calibration diode active areas. A custom electromechanical interface was developed to make these measurements within the SwRI Vacuum Radiometric Calibration Chamber. While still in the single pixel stage, full 1K × 1K focal plane arrays are possible using existing CMOS readout electronics and hold great promise for inclusion in future spaceflight instrument concepts.

Davis, Michael W.; Greathouse, Thomas K.; Retherford, Kurt D.; Winters, Gregory S.; Bai, Yibin; Beletic, James W.

2012-07-01

199

Lower-Dark-Current, Higher-Blue-Response CMOS Imagers  

NASA Technical Reports Server (NTRS)

Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

2008-01-01

200

A CMOS wireless biomolecular sensing system-on-chip based on polysilicon nanowire technology.  

PubMed

As developments of modern societies, an on-field and personalized diagnosis has become important for disease prevention and proper treatment. To address this need, in this work, a polysilicon nanowire (poly-Si NW) based biosensor system-on-chip (bio-SSoC) is designed and fabricated by a 0.35 ?m 2-Poly-4-Metal (2P4M) complementary metal-oxide-semiconductor (CMOS) process provided by a commercialized semiconductor foundry. Because of the advantages of CMOS system-on-chip (SoC) technologies, the poly-Si NW biosensor is integrated with a chopper differential-difference amplifier (DDA) based analog-front-end (AFE), a successive approximation analog-to-digital converter (SAR ADC), and a microcontroller to have better sensing capabilities than a traditional Si NW discrete measuring system. In addition, an on-off key (OOK) wireless transceiver is also integrated to form a wireless bio-SSoC technology. This is pioneering work to harness the momentum of CMOS integrated technology into emerging bio-diagnosis technologies. This integrated technology is experimentally examined to have a label-free and low-concentration biomolecular detection for both Hepatitis B Virus DNA (10 fM) and cardiac troponin I protein (3.2 pM). Based on this work, the implemented wireless bio-SSoC has demonstrated a good biomolecular sensing characteristic and a potential for low-cost and mobile applications. As a consequence, this developed technology can be a promising candidate for on-field and personalized applications in biomedical diagnosis. PMID:24080725

Huang, C-W; Huang, Y-J; Yen, P-W; Tsai, H-H; Liao, H-H; Juang, Y-Z; Lu, S-S; Lin, C-T

2013-11-21

201

A CAD tool for the power estimation of CMOS, BiCMOS and BiNMOS gates  

E-print Network

of reasons given below. CMOS is the dominant technology in use in VLSI today, but its use in driving large load capacitances is limited. BiCMOS and BiNMOS circuits perform better in this respect because of the higher current capabilities of the bipolar... degradation at lower supply voltages because of a loss in output swing. In this situation, BiNMOS gates combining a bipolar pull-up with a conventional CMOS pull-down provide a remedy. Therefore, as we move towards larger chip size and lower supply voltages...

Islam, Kazi Inamul

1995-01-01

202

Radiation hardness by design for mixed signal infrared readout circuit applications  

NASA Astrophysics Data System (ADS)

Readout integrated circuits (ROICs) to support space-based infrared detection applications often have severe radiation tolerance requirements. Radiation hardness-by-design (RHBD) significantly enhances the radiation tolerance of commercially available CMOS and custom radiation hardened fabrication techniques are not required. The combination of application specific design techniques, enclosed gate architecture nFETs and intrinsic thin oxide radiation hardness of 180 nm process node commercial CMOS allows realization of high performance mixed signal circuits. Black Forest Engineering has used RHBD techniques to develop ROICs with integrated A/D conversion that operate over a wide range of temperatures (40K-300K) to support infrared detection. ROIC radiation tolerance capability for 256x256 LWIR area arrays and 1x128 thermopile linear arrays is presented. The use of 130 nm CMOS for future ROIC RHBD applications is discussed.

Gaalema, Stephen; Gates, James; Dobyns, David; Pauls, Greg; Wall, Bruce

2013-09-01

203

Design of CMOS Cell Libraries for Minimal Leakage Currents  

E-print Network

Design of CMOS Cell Libraries for Minimal Leakage Currents Master's Thesis by Jacob Gregers Hansen Leakage Currents' conducted at Informatics and Mathematical Mod- elling (IMM), Computer Science.3 The problem of leakage currents . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 Possible solutions

204

Dynamically Resizable Static CMOS Logic for Fine-Grain Leakage  

E-print Network

Digital circuits often have a critical path that runs through a smallsubset of the component subblocks, but where the path changes dynamicallyduring operation. Dynamically resizable static CMOS (DRCMOS) logic isproposed ...

Heo, Seongmoo

2004-07-12

205

Circuits and algorithms for pipelined ADCs in scaled CMOS technologies  

E-print Network

CMOS technology scaling is creating significant issues for analog circuit design. For example, reduced signal swing and device gain make it increasingly difficult to realize high-speed, high-gain feedback loops traditionally ...

Brooks, Lane Gearle, 1975-

2008-01-01

206

Formal specification of a high speed CMOS correlator  

NASA Technical Reports Server (NTRS)

The formal specification of a high speed CMOS correlator is presented. The specification gives the high-level behavior of the correlator and provides a clear, unambiguous description of the high-level architecture of the device.

Windley, P. J.

1991-01-01

207

A wide-dynamic-range time-based CMOS imager  

E-print Network

This thesis describes a novel dual-threshold time-based current sensing algorithm suitable for use in wide-dynamic-range CMOS imagers. A prototype 150 x 256 pixel imager employing this algorithm experimentally achieves ...

O'Halloran, Micah G. (Micah Galletta), 1978-

2008-01-01

208

A study of CMOS technologies for image sensor applications  

E-print Network

CMOS (Complementary Metal-Oxide-Silicon) imager technology, as compared with mature CCD (Charge-Coupled Device) imager technology, has the advantages of higher circuit integration, lower power consumption, and potentially ...

Wang, Ching-Chun, 1969-

2001-01-01

209

CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology  

NASA Technical Reports Server (NTRS)

This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

2006-01-01

210

Design of a CMOS compatible, athermal, optical waveguide  

E-print Network

This paper explores a possible design for a CMOS compatible, athermal, optical waveguide. The design explored is a slot waveguide with light guided in the low index material. A design paradigm is proposed which shows the ...

Fernandez, Luis Enrique, S.B. Massachusetts Institute of Technology

2007-01-01

211

Strain-engineered CMOS-compatible Ge photodetectors  

E-print Network

The development of CMOS-compatible photodetectors capable of operating throughout the entire telecommunications wavelength spectrum will aid in the integration of photodetectors with Si microelectronics, thus offering a ...

Cannon, Douglas Dale, 1974-

2004-01-01

212

Photonic Device Layout Within the Foundry CMOS Design Environment  

E-print Network

A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs ...

Orcutt, Jason Scott

213

A silicon avalanche photodetector fabricated with standard CMOS technology  

E-print Network

A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain a silicon avalanche photodetector (APD) fabricated with standard complementary metal-well junction, and its current-voltage characteristics, responsivity, avalanche gain, and photodetection

Choi, Woo-Young

214

Fabrication and simulation of CMOS-compatible photodiodes  

E-print Network

CMOS-compatible photodiodes are becoming increasinging important devices to study because of their application in combined electronic-photonic systems. They are already used as inexpensive optical transceivers in fiber ...

DiLello, Nicole Ann

2008-01-01

215

A CMOS Capacitance Sensor for Cell Adhesion Characterization  

E-print Network

Abshire Department of Electrical and Computer Engineering University of Maryland College Park, Maryland 20742, USA Mario Urdaneta, Elisabeth Smela Department of Mechanical Engineering University of Maryland College Park, Maryland 20742, USA Abstract-- We describe a CMOS capacitance sensor for measuring

Maryland at College Park, University of

216

Commercial Capaciflector  

NASA Technical Reports Server (NTRS)

A capacitive proximity/tactile sensor with unique performance capabilities ('capaciflector' or capacitive reflector) is being developed by NASA/Goddard Space Flight Center (GSFC) for use on robots and payloads in space in the interests of safety, efficiency, and ease of operation. Specifically, this sensor will permit robots and their attached payloads to avoid collisions in space with humans and other objects and to dock these payloads in a cluttered environment. The sensor is simple, robust, and inexpensive to manufacture with obvious and recognized commercial possibilities. Accordingly, NASA/GSFC, in conjunction with industry, is embarking on an effort to 'spin' this technology off into the private sector. This effort includes prototypes aimed at commercial applications. The principles of operation of these prototypes are described along with hardware, software, modelling, and test results. The hardware description includes both the physical sensor in terms of a flexible printed circuit board and the electronic circuitry. The software description will include filtering and detection techniques. The modelling will involve finite element electric field analysis and will underline techniques used for design optimization.

Vranish, John M.

1991-01-01

217

SOI for digital CMOS VLSI: design considerations and advances  

Microsoft Academic Search

This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAMs), dynamic random access memories (DRAMs), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting from the unique SOI device structure. The impact of floating-body in partially depleted

Ching-Te Chuang; PONG-FEI LU; CARL J. ANDERSON

1998-01-01

218

Low voltage CMOS transconductors using the series composite transistor  

Microsoft Academic Search

In this paper, low voltage CMOS transconductors using the series composite transistors are presented. The minimum input voltage of the designed circuits is VTn, which is suitable for low supply voltage. The designed circuits have been simulated by HSPICE using 0.25 ?m n-well CMOS process. Simulation results show that THD is less than 1.2% for the differential input signal of

Young-Gyu Yu; Geun-Ho Lee; Chang-Hun Yun; Seok-Woo Choi; Hong-Kyu Shin

2000-01-01

219

Study on sub-pixel measurement accuracy of CMOS imager  

Microsoft Academic Search

There are two main image sensors that are now being widely used in image capture system: CCD and CMOS imager. The fill-factor of CMOS imager is lower than that of CCD, so it is of great importance to consider the influence of the fill-factor on sub-pixel measurement accuracy. the main purpose of this paper is to give a discussion of

Zhi Liu

2005-01-01

220

Deep submicron CMOS based on silicon germanium technology  

Microsoft Academic Search

The advantages to be gained by using SiGe in CMOS technology are examined, Conventional MOSFETs are compared with SiGe heterojunction MOSFETs suitable for CMOS technology and having channel lengths between 0.5 and 0.1 ?m. Two-dimensional computer simulation demonstrates that the improved mobility in the SiGe devices, due to higher bulk mobility and the elimination of Si\\/SiO2 interface scattering by the

A. G. O'Neill; D. A. Antoniadis

1996-01-01

221

OLED-on-CMOS integration for optoelectronic sensor applications  

NASA Astrophysics Data System (ADS)

Highly-efficient, low-voltage organic light emitting diodes (OLEDs) are well suitable for post-processing integration onto the top metal layer of CMOS devices. This has been proven for OLED microdisplays so far. Moreover, OLEDon- CMOS technology may also be excellently suitable for various optoelectronic sensor applications by combining highly efficient emitters, use of low-cost materials and cost-effective manufacturing together with silicon-inherent photodetectors and CMOS circuitry. The use of OLEDs on CMOS substrates requires a top-emitting, low-voltage and highly efficient OLED structure. By reducing the operating voltage for the OLED below 5V, the costs for the CMOS process can be reduced, because a process without high-voltage option can be used. Red, orange, white, green and blue OLED-stacks with doped charge transport layers were prepared on different dualmetal layer CMOS test substrates without active transistor area. Afterwards, the different devices were measured and compared with respect to their performance (current, luminance, voltage, luminance dependence on viewing angle, optical outcoupling etc.). Low operating voltages of 2.4V at 100cd/m2 for the red p-i-n type phosphorescent emitting OLED stack, 2.5V at 100cd/m2 for the orange phosphorescent emitting OLED stack and 3.2V at 100cd/m2 for the white fluorescent emitting OLED have been achieved here. Therefore, those OLED stacks are suitable for use in a CMOS process even within a regular 5V process option. Moreover, the operating voltage achieved so far is expected to be reduced further when using different top electrode materials. Integrating such OLEDs on a CMOS-substrate provide a preferable choice for silicon-based optical microsystems targeted towards optoelectronic sensor applications, as there are integrated light barriers, optocouplers, or lab-onchip devices.

Vogel, Uwe; Kreye, Daniel; Reckziegel, Sven; Törker, Michael; Grillberger, Christiane; Amelung, Jörg

2007-02-01

222

An Energy-Efficient CMOS Line Driver Using Adiabatic Switching  

Microsoft Academic Search

The energy recovery principle used in high-efficiency power supplies can be applied to digital CMOS logic to reduce dynamic power dissipation. We describe experiments with a custom line- driver chip and resonant power supply that can switch eight 100pF loads at 1MHz over 6 times more efficiently than conventional CMOS. The paper describes the adiabatic charging principle underlying this class

W. C. Athas; J. G. Koller

1993-01-01

223

A statistical MOSFET modeling method for CMOS integrated circuit simulation  

E-print Network

A STATISTICAL MOSFET MODELING METHOD FOR CMOS IN'I'EGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Submitted to the Office of Graduate Studies of Texas AE~M University in partial fulfillment of the requirements for the degree of MASTER... OF SCIENCE August l 99'2 Major Sub ject: Electrical Engineering A STATISTICAL MOSFET MODELING METHOD FOR CMOS INTEGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Approved as to style and content by: H. Maciej . Styblinski ) (Chair of Committee...

Chen, Jian

1992-01-01

224

Hafnium oxide and hafnium aluminum oxide for CMOS applications  

Microsoft Academic Search

The continued scaling of the CMOS gate dielectric to its fundamental limit governed by the large gate leakage current requires the introduction of high-k material for sub-100-nm technology nodes. This dissertation research deals with the physical and electrical properties of a promising high-k candidate, hafnium oxide, as a gate dielectric for CMOS applications. Hafnium oxide made by the Jet-Vapor-Deposition process

Wenjuan Zhu

2003-01-01

225

Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects  

Microsoft Academic Search

This paper deals in crosstalk analysis of a CMOS-gate-driven capacitively and inductively coupled interconnect. Alpha power-law model of a MOS transistor is used to represent a CMOS driver. This is combined with a transmission-line-based coupled-interconnect model to develop a composite driver-interconnect-load model for analytical purposes. On this basis, a transient analysis of crosstalk noise is carried out. Comparison of the

Brajesh Kumar Kaushik; Sankar Sarkar

2008-01-01

226

A compact tunable CMOS transconductor with high linearity  

Microsoft Academic Search

A novel CMOS linear transconductor is presented. The use of simple and accurate voltage buffers to drive two MOS transistors operating in the triode region leads to a highly linear voltage-to-current conversion. Transconductance gain can be continuously and precisely adjusted using dc level shifters. Measurement results of a balanced transconductor fabricated in a 0.5-?m CMOS technology show a total harmonic

Meghraj Kachare; Antonio J. López-Martín; Jaime Ramirez-Angulo; Ramon G. Carvajal

2005-01-01

227

Wideband VGAs Using a CMOS Transconductor in Triode region  

Microsoft Academic Search

Wideband variable gain amplifiers (VGAs) fabricated using 0.18 mum CMOS process are presented. A scheme with a CMOS triode transconductor is proposed to achieve linear-in-dB characteristics of VGAs for ultra wideband (UWB) systems. The implemented transmitter (TX) VGA shows a highly linear gain range of 28.4 dB (7 dB to -21.4 dB) and a bandwidth of 1200 MHz, while drawing

Hui Dong Lee; Kyung Ai Lee; Songcheol Hong

2006-01-01

228

CMOS balanced output transconductor and applications for analog VLSI  

Microsoft Academic Search

A new CMOS programmable balanced output transconductor (BOTA) is introduced. The BOTA is a useful block for continuous-time analog signal processing. A new CMOS realization based on MOS transistors operating in the saturation region is given. Application of the BOTA in realizing bandpass–lowpass–allpass–notch biquad mixed mode filter using four BOTAs and two grounded capacitors and in realizing current mode MOS-C

Soliman A. Mahmound; Ahmed M. Soliman

1999-01-01

229

Electrical properties and detection methods for CMOS IC defects  

Microsoft Academic Search

CMOS failure modes and mechanisms and the test vector and parametric test requirements for the detection are reviewed. The CMOS stuck-open fault is discussed from a physical viewpoint, with results given from failure analysis of ICs having this failure mode. The results show that among functional, stuck-at, stuck-open, and IDDQ test strategies, no single method guarantees detection of all types

Jerry M. Soden; Charles F. Hawkins

1989-01-01

230

Wide intrascene dynamic range CMOS APS using dual sampling  

Microsoft Academic Search

A CMOS active pixel sensor (APS) that achieves wide intrascene dynamic range using dual sampling is reported. A 64×64 element prototype sensor with dual output architecture was fabricated using a 1.2 ?m n-well CMOS process with 20.4 ?m pitch photodiode-type active pixels. The sensor achieves an intrascene dynamic range of 109 dB without nonlinear companding

Orly Yadid-Pecht; Eric R. Fossum

1997-01-01

231

CMOS Image Sensors: Electronic Camera On A Chip  

NASA Technical Reports Server (NTRS)

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

Fossum, E. R.

1995-01-01

232

Sub60 nm physical gate length SOI CMOS  

Microsoft Academic Search

This work addresses the design and optimization of high performance CMOS devices in the sub-60 nm regime. Aggressive scaling of the poly gate length is achieved by controlling the short-channel effects in partially-depleted SOI (Silicon-On-Insulator) CMOS devices. In addition, SOI specific design issues are examined to reduce device parasitics such as junction capacitance and history effect through the optimization of

I. Y. Yang; K. Chen; P. Smeys; J. Sleight; L. Lin; M. Leong; E. Nowak; S. Fung; E. Maciejewski; P. Varekamp; W. Chu; P. Agnello; S. Crowder; F. Assaderaghi; L. Su

1999-01-01

233

Depleted Monolithic Active Pixel Sensors (DMAPS) implemented in LF-150 nm CMOS technology  

NASA Astrophysics Data System (ADS)

We present the recent development of Depleted Monolithic Active Pixel Sensors (DMAPS), implemented with an LFoundry (LF) 150 nm CMOS process. MAPS detectors based on an epi-layer have been matured in recent years and have attractive features in terms of reducing material budget and handling cost compared to conventional hybrid pixel detectors. However, the obtained signal is relatively small (~1000 e?) due to the thin epi-layer, and charge collection time is relatively slow, e.g., in the order of 100 ns, because charges are mainly collected by diffusion. Modern commercial CMOS technology, however, offers advanced process options to overcome such difficulties and enable truly monolithic devices as an alternative to hybrid pixel sensors and charge coupled devices. Unlike in the case of the standard MAPS technologies with epi-layers, the LF process provides a high-resistivity substrate that enables large signal and fast charge collection by drift in a ~50 ?m thick depleted layer. Since this process also enables the use of deep n- and p-wells to isolate the collection electrode from the thin active device layer, PMOS and NMOS transistors are available for the readout electronics in each pixel cell. In order to evaluate the sensor and transistor characteristics, several collection electrodes variants and readout architectures have been implemented. In this report, we focus on its design aspect of the LF-DMAPS prototype chip.

Kishishita, T.; Hemperek, T.; Krüger, H.; Wermes, N.

2015-03-01

234

Latchup in CMOS devices from heavy ions  

NASA Technical Reports Server (NTRS)

It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

Soliman, K.; Nichols, D. K.

1983-01-01

235

CMOS imager for pointing and tracking applications  

NASA Technical Reports Server (NTRS)

Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

2006-01-01

236

Modeling and Manufacturing of a Micromachined Magnetic Sensor Using the CMOS Process without Any Post-Process  

PubMed Central

The modeling and fabrication of a magnetic microsensor based on a magneto-transistor were presented. The magnetic sensor is fabricated by the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process without any post-process. The finite element method (FEM) software Sentaurus TCAD is utilized to analyze the electrical properties and carriers motion path of the magneto-transistor. A readout circuit is used to amplify the voltage difference of the bases into the output voltage. Experiments show that the sensitivity of the magnetic sensor is 354 mV/T at the supply current of 4 mA. PMID:24732100

Tseng, Jian-Zhi; Wu, Chyan-Chyi; Dai, Ching-Liang

2014-01-01

237

Advancement of CMOS Doping Technology in an External Development Framework  

NASA Astrophysics Data System (ADS)

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

238

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor  

PubMed Central

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18??m TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18??m TSMC CMOS technology. PMID:24782680

Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

239

CMOS Integrated Circuit Design for Ultra-Wideband Transmitters and Receivers  

E-print Network

radar, distance sensor, through wall radar to high speed, short distance communications. The CMOS integrated circuit is an attractive, low cost approach for implementing UWB technology. The improving cut-off frequency of the transistor in CMOS process...

Xu, Rui

2010-10-12

240

Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips  

E-print Network

We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS ...

Wade, Mark T.

241

77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...  

Federal Register 2010, 2011, 2012, 2013, 2014

...COMMISSION [Investigation No. 337-TA-846] Certain CMOS Image Sensors and Products Containing Same; Investigations...within the United States after importation of certain CMOS image sensors and products containing the same based on...

2012-12-14

242

c-mos Variation in Songbirds: Molecular Evolution, Phylogenetic Implications, and Comparisons with Mitochondrial Differentiation  

Microsoft Academic Search

Nucleotide sequences from the c-mos proto-oncogene have previously been used to reconstruct the phylogenetic relationships between distantly related vertebrate taxa. To explore c-mos variation at shallower levels of avian divergence, we compared c-mos sequences from representative passerine taxa that span a range of evolutionary differentiation, from basal passerine lineages to closely allied genera. Phylogenetic reconstructions based on these c-mos sequences

Irby J. Lovette; Eldredge Bermingham

243

Integration of Single-Walled Carbon Nanotubes on to CMOS Circuitry with Parylene-C Encapsulation  

E-print Network

Integration of Single-Walled Carbon Nanotubes on to CMOS Circuitry with Parylene-C Encapsulation-level post processing. The chip was fabricated using the AMI 0.5µm CMOS Technology. An electroless zincation process was performed over the Aluminum assembly electrodes (Metal 3 of CMOS technology) to clean

Dokmeci, Mehmet

244

The Implementation of Retinal Functions on CMOS ICs and Their Applications  

Microsoft Academic Search

In this talk, three main topics including the CMOS implementation of neuromorphic chips, focal-plane motion sensors, and implantable retinal chips for visual prostheses are addressed. A CMOS design methodology for implementing CMOS neuromorphic chips which imitate the ON brisk transient ganglion cell (GC) set of rabbits' retinas is presented in the first part. Retina is the most important preprocessor in

Chung-Yu Wu

2007-01-01

245

Del 2: Enkel elektrisk transistor modell og introduksjon til CMOS prosess  

E-print Network

Del 2: Enkel elektrisk transistor modell og introduksjon til CMOS prosess YNGVAR BERG I. Innhold GJ ennomgang av CMOS prosess, tverrsnitt av nMOS- og pMOS transistor og tverrsnitt av CMOS inverter. Enkel forklaring p°a begreper som akkumulasjon, deplesjon og inver- sjon. Enkel fysikalsk forklaring p°a transistor

Sahay, Sundeep

246

Heavy ion radiation damage simulations for CMOS image sensors Henok Mebrahtua  

E-print Network

Heavy ion radiation damage simulations for CMOS image sensors Henok Mebrahtua , Wei Gaoa , Paul J, University of Toronto, Toronto, Ontario, Canada ABSTRACT Damage in CMOS image sensors caused by heavy ions and range of ions in matter) simulation results of heavy ion radiation damage to CMOS image sensors

Hornsey, Richard

247

Architecture and Performance Evaluation of 3D CMOS-NEM FPGA  

E-print Network

Architecture and Performance Evaluation of 3D CMOS-NEM FPGA Chen Dong*, Chen Chen+, Subhasish Mitra In this paper, we introduce a reconfigurable architecture, named 3D CMOS-NEM FPGA, which utilizes include: hybrid CMOS-NEM FPGA look-up tables (LUTs) and configurable logic blocks (CLBs), NEM-based switch

Chen, Deming

248

Impact of Gate Leakage on Mixed Signal Design and Simulation of Nano-CMOS Circuits  

E-print Network

issues in modern nanometer CMOS processes are discussed in this work. Several VCO and PLL designs have been already presented in the literature [6]. High performance CMOS based VCO designs have beenImpact of Gate Leakage on Mixed Signal Design and Simulation of Nano-CMOS Circuits Saraju P

Mohanty, Saraju P.

249

CMOS Cell Sensors for Point-of-Care Diagnostics  

PubMed Central

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

250

A 130 nm radiation hardened flip—flop with an annular gate and a C-element  

NASA Astrophysics Data System (ADS)

This paper presents a radiation hardened flip—flop with an annular gate and a Muller C-element. The proposed cell has multiple working modes which can be used in different situations. Each part of the cell can be verified easily and completely by using different modes. This cell has been designed under an SMIC 0.13 ?m process and 3-D simulated by using Synopsys TCAD. Heavy-ion testing has been done on the cell and its counterparts. The test results demonstrate that the presented cell reduces the cell's saturation cross section by approximately two orders of magnitude with little penalty on performance.

Lei, Wang; Jianhua, Jiang; Yiming, Xiang; Yumei, Zhou

2014-01-01

251

NSC 800, 8-bit CMOS microprocessor  

NASA Technical Reports Server (NTRS)

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Suszko, S. F.

1984-01-01

252

Feasibility study of CMOS detectors for mammography  

NASA Astrophysics Data System (ADS)

We investigated the potential use of CMOS (complementary metal-oxide-semiconductor) imaging detectors with a pixel pitch of 48 ?m for mammography. Fundamental imaging characteristics were evaluated in terms of modulation-transfer function (MTF), noise-power spectrum (NPS), and detective quantum efficiency (DQE). The magnitudes of various image noise sources, such as optical photons, direct x rays unattenuated and scattered x rays from the scintillator, and additive electronic noise, were measured and analyzed. For the analysis of the measurement results, we applied a model describing the signal and noise transfer based on the cascaded linear-systems approach. The direct x-ray was very harmful to the detector noise performance with white noise characteristics in the spatial frequency domain, and which significantly degraded the spatial-frequency-dependent DQE at higher frequencies. Although the use of a fiber-optic plate (FOP) reduces the detector sensitivity and the MTF performance, it enhances the DQE performance by preventing the direct x-ray photons from the absorption within the photodiode array.

Han, Jong Chul; Yun, Seungman; Lim, Chang Hwy; Kim, Tae Woo; Kim, Ho Kyung

2009-02-01

253

A New CMOS Posicast Pre-shaper for Vibration Reduction of CMOS Op-Amps  

NASA Astrophysics Data System (ADS)

Posicast-based control is a widely used method in vibration reduction of lightly damped oscillatory systems especially in mechanical fields. The target systems to apply Posicast method are the systems which are excited by pulse inputs. Using the Posicast idea, the input pulse is reshaped into a new pulse, which is called Posicast pulse. Applying the generated Posicast pulse reduces the undesired oscillatory manner of under-test systems. In this paper, a fully CMOS Pulse pre-shaper circuit for realization of Posicast command is proposed. Our design is based on delay-and-add approach for the incoming pulses. The delay is done via a modified Schmitt Trigger-like circuit. The adder circuit is implemented by a simple non-binary analog adder terminated by a passive element. Our proposed design has a reasonable flexibility in configuration of time delay and amplitude of the desired pulse-like shapes. The delay is controlled via the delay unit and the pre-shaped pulse's amplitudes are controlled by an analog adder unit. The overall system has 18 MOS transistors, one small capacitor, and one resistor. To verify the effectiveness of the recommended method, it is experienced on a real CMOS Op-Amp. HSPICE simulation results, on 0.25u technology, show a significant reduction on overshoot and settling time of the under-test Op-Amp. The mentioned reduction is more than 95% in overshoot and more than 60% in settling time of the system.

Rasoulzadeh, M.; Ghaznavi-Ghoushchi, M. B.

2010-06-01

254

Radiation imaging with a new scintillator and a CMOS camera  

NASA Astrophysics Data System (ADS)

A new imaging system consisting of a high-sensitivity complementary metal-oxide semiconductor (CMOS) sensor, a microscope and a new scintillator, Ce-doped Gd3(Al,Ga)5O12 (Ce:GAGG) grown by the Czochralski process, has been developed. The noise, the dark current and the sensitivity of the CMOS camera (ORCA-Flash4.0, Hamamatsu) was revised and compared to a conventional CMOS, whose sensitivity is at the same level as that of a charge coupled device (CCD) camera. Without the scintillator, this system had a good position resolution of 2.1 ± 0.4 ?m and we succeeded in obtaining the alpha-ray images using 1-mm thick Ce:GAGG crystal. This system can be applied for example to high energy X-ray beam profile monitor, etc.

Kurosawa, S.; Shoji, Y.; Pejchal, J.; Yokota, Y.; Yoshikawa, A.

2014-07-01

255

Operation and biasing for single device equivalent to CMOS  

DOEpatents

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

2001-01-01

256

A CMOS humidity sensor for passive RFID sensing applications.  

PubMed

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 ?m CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

257

A CMOS Humidity Sensor for Passive RFID Sensing Applications  

PubMed Central

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 ?m CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 ?W at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

258

COMMERCIAL SPACE ACCOMPLISHMENTS Commercial Cargo Space Accomplishments  

E-print Network

11/13/2013 COMMERCIAL SPACE ACCOMPLISHMENTS Commercial Cargo Space Accomplishments The Obama Administration's ambitious commercial space program, which has bipartisan support in Congress, has enabled NASA's successful partnership with two American companies now able to resupply the station - SpaceX and Orbital

Waliser, Duane E.

259

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems  

NASA Technical Reports Server (NTRS)

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

1993-01-01

260

Digital architectures for hybrid CMOS/nanodevice circuits  

NASA Astrophysics Data System (ADS)

This dissertation describes architectures of digital memories and reconfigurable Boolean logic circuits for the prospective hybrid CMOS/nanowire/nanodevice ("CMOL") technology. The basic idea of CMOL circuits is to combine the advantages of CMOS technology (including its flexibility and high fabrication yield) with those of molecular-scale nanodevices. Two-terminal nanodevices would be naturally incorporated into nanowire crossbar fabric, enabling very high function density at acceptable fabrication costs. In order to overcome the CMOS/nanodevice interface problem, in CMOL circuits the interface is provided by sharp-tipped pins that are distributed all over the circuit area, on top of the CMOS stack. The most straightforward possible application of CMOL circuits is terabit-scale "resistive" memories, in which nanodevices (e.g., single molecules) would be used as single-bit, memory cells, while the semiconductor subsystem would perform all the peripheral (input/output, coding/decoding, line driving, and sense amplification) functions. Using bad-bit exclusion and error-correcting codes synergistically we show that CMOL memories with a nano/CMOS pitch ratio close to 1/3 may overcome purely semiconductor memories in useful density if the fraction of bad nanodevices is below ˜ 15%, even for the 30 ns upper bound on the total access time. As the nanotechnology matures, and the pitch ratio approaches an order of magnitude, the CMOL memories may be far superior to the densest semiconductor memories by providing, e.g., 1 Tbit/cm2 density even for the plausible defect fraction of 2%. Even greater defect tolerance (about 20% for 99% circuit yield) can be achieved in uniform a cell-FPGA-like CMOL circuits. In such circuits, two-terminal nanodevices provide programmable diode functionality for logic circuit operation, and allow circuit mapping and reconfiguration around defective nanodevices, while CMOS subsystem is used for signal restoration and latching. The cell-based architecture is based on a uniform CMOL fabric of "tiles", while each tile consists of 12 four-transistor basic cells and one latch cell. To evaluate the potential performance of CMOL FPGA we have developed a completely custom design automation tools. Using these tools we have successfully mapped on CMOL FPGA the well known Toronto 20 benchmark circuits and estimated their performance. The results have shown that, in addition to high defect tolerance, CMOL FPGA circuits may have extremely high density (more than two orders of magnitude higher that of usual CMOS FPGA with the same CMOS design rules) while operating at higher speed at acceptable power consumption.

Strukov, Dmitri B.

261

A 0.5-GHz CMOS digital RF memory chip  

NASA Astrophysics Data System (ADS)

Digital RF memories (DRFM's) are key elements for modern radar jamming. An RF signal is sampled, stored in random access memory (RAM), and later recreated from the stored data. Here the first CMOS DRFM chip, integrating static RAM, control circuitry, and two channels of shift registers, on a single chip is described. The sample rate achieved was 0.5 GHz, VLSI density was made possible by the low-power dissipation of quiescent CMOS circuits. An 8K RAM prototype chip has been built and tested.

Schnaitter, W. M.; Lewis, E. T.; Gordon, B. E.

1986-10-01

262

CMOS sensor as charged particles and ionizing radiation detector  

NASA Astrophysics Data System (ADS)

This paper reports results of CMOS sensor suitable for use as charged particles and ionizing radiation detector. The CMOS sensor with 640 × 480 pixels area has been integrated into an electronic circuit for detection of ionizing radiation and it was exposed to alpha particle (Am-241, Unat), beta (Sr-90), and gamma photons (Cs-137). Results show after long period of time (168 h) irradiation the sensor had not loss of functionality and also the energy of the charge particles and photons were very well obtained.

Cruz-Zaragoza, E.; Piña López, I.

2015-01-01

263

Radiation tolerant back biased CMOS VLSI  

NASA Technical Reports Server (NTRS)

A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

2003-01-01

264

604 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 4, APRIL 1997 Low-Power BiCMOS Circuits for High-Speed Interchip Communication  

E-print Network

for High-Speed Interchip Communication M. S. Elrabaa, M. I. Elmasry, and D. S. Malhi Abstract--A universal] and CMOS pseudo ECL or CMOS 100 K ECL [8]­[9], to CMOS Gunning transceiver logic (GTL) [10]. The CMOS reduced-swing trans- ceivers have limited speed, and the CMOS true or pseudo ECL are complicated to design

Elrabaa, Muhammad E. S.

265

Performance of PHOTONIS' low light level CMOS imaging sensor for long range observation  

NASA Astrophysics Data System (ADS)

Identification of potential threats in low-light conditions through imaging is commonly achieved through closed-circuit television (CCTV) and surveillance cameras by combining the extended near infrared (NIR) response (800-10000nm wavelengths) of the imaging sensor with NIR LED or laser illuminators. Consequently, camera systems typically used for purposes of long-range observation often require high-power lasers in order to generate sufficient photons on targets to acquire detailed images at night. While these systems may adequately identify targets at long-range, the NIR illumination needed to achieve such functionality can easily be detected and therefore may not be suitable for covert applications. In order to reduce dependency on supplemental illumination in low-light conditions, the frame rate of the imaging sensors may be reduced to increase the photon integration time and thus improve the signal to noise ratio of the image. However, this may hinder the camera's ability to image moving objects with high fidelity. In order to address these particular drawbacks, PHOTONIS has developed a CMOS imaging sensor (CIS) with a pixel architecture and geometry designed specifically to overcome these issues in low-light level imaging. By combining this CIS with field programmable gate array (FPGA)-based image processing electronics, PHOTONIS has achieved low-read noise imaging with enhanced signal-to-noise ratio at quarter moon illumination, all at standard video frame rates. The performance of this CIS is discussed herein and compared to other commercially available CMOS and CCD for long-range observation applications.

Bourree, Loig E.

2014-05-01

266

An integrated CMOS micromechanical resonator high-Q oscillator  

Microsoft Academic Search

A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator with the intent of achieving high stability. The operation and performance of micromechanical resonators are modeled, with emphasis on circuit and noise modeling of multiport resonators. A series resonant oscillator design is

Clark T.-C. Nguyen; Roger T. Howe

1999-01-01

267

Hybrid postprocessing etching for CMOS-compatible MEMS  

Microsoft Academic Search

A major limitation in the fabrication of microstructures as a postCMOS (complimentary metal oxide semiconductor) process has been overcome by the development of a hybrid processing technique, which combines both an isotropic and anisotropic etch step. Using this hybrid technique, microelectromechanical structures with sizes ranging from 0.05 to ~1 mm in width and up to 6 mm in length were

Nim H. Tea; V. Milanovic; Christian A. Zincke; John S. Suehle; Michael Gaitan; Mona E. Zaghloul; Jon Geist

1997-01-01

268

A CMOS GENERAL-PURPOSE SAMPLED-DATA ANALOGUE MICROPROCESSOR  

E-print Network

A CMOS GENERAL-PURPOSE SAMPLED-DATA ANALOGUE MICROPROCESSOR Piotr Dudek and Peter J. Hicks functions as an analogue microprocessor (AµP). The AµP executes software programs, in a way akin to a digital microprocessor, while nevertheless operating on analogue sampled data values. This enables

Dudek, Piotr

269

2210 Experiment 13 CMOS Logic T. Roppel Nov. 2009 1  

E-print Network

as a function of the input voltage over the range of 0 to +5 V. Use the Bit-Bucket variable DC source to provide) does your inverter switch logic levels? (b) What are the output logic level voltages? (c) What logic inverter circuit is shown in Fig. 1. Figure 1. CMOS logic inverter. When MP is on, MN is off

Niu, Guofu

270

Intensity Histogram CMOS Image Sensor for Adaptive Optics  

E-print Network

Intensity Histogram CMOS Image Sensor for Adaptive Optics Yu M. Chi, Gary Carhart , Mikhail A imaging mode and 4.6mW in high-speed histogram mode. Applications include real-time adaptive optics control for laser communications. I. INTRODUCTION Adaptive optical systems are highly useful

Cauwenberghs, Gert

271

A CMOS integrated infrared radiation detector for flame monitoring  

Microsoft Academic Search

This paper presents an integrated infrared radiation detector for flame monitoring applications, fabricated in CMOS technology. The system discriminates the radiation of the flickering flame in an oil burner from the steady background radiation generated by the furnace by considering only the harmonic components of the infrared signal in the band from 50 Hz to 250 Hz. In order to

P. Bendiscioli; F. Francesconi; P. Malcovati; F. Maloberti; M. Poletti; R. Valacca

1998-01-01

272

Recent development on CMOS monolithic active pixel sensors  

Microsoft Academic Search

Vertex Detectors for future high energy physics experiments will need to fulfill more stringent requirements with respect to presently operating tracking detectors. Existing pixel devices (such as hybrid pixel sensors and charge-coupled-devices) have yet to strike an appropriate balance among granularity, material budget, radiation tolerance and readout speed. On the contrary, CMOS Monolithic Active Pixel Sensors (MAPS) are a promising

G. Rizzo

2007-01-01

273

Radiation-induced dark current in CMOS active pixel sensors  

Microsoft Academic Search

Degradation behavior of CMOS active pixel sensors\\u000d\\u000a(APS) exposed to protons and Cobalt60 is presented. The most sensitive\\u000d\\u000aparameter is the dark current: the mean value of the degradation\\u000d\\u000ais always dominated by ionizing effects.

Michael Cohen; Jean-Pierre David

2000-01-01

274

Design of CMOS Cell Libraries for Minimal Leakage Currents  

E-print Network

Design of CMOS Cell Libraries for Minimal Leakage Currents Master's Thesis by Jacob Gregers Hansen for Minimal Leakage Currents' conducted at Informatics and Mathematical Mod­ elling (IMM), Computer Science.3 The problem of leakage currents . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 Possible solutions

275

Computation-Efficient Image Signal Processing for CMOS Image Sensors  

Microsoft Academic Search

This paper presents an efficient image signal processing method proposed for CMOS image sensors. In the proposed method, the color correction is moved to the front of the color demosaic to reduce the arithmetic complexity required in the color correction to one third, and a new color correction method is suggested to achieve good images with less data. In spite

Ki-Seok Kwon; Eun-Joo Bae; Seokho Lee; Jinook Song; In-Cheol Park

276

Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications  

Microsoft Academic Search

A single chip frequency synthesizer compliant with the ZigBee standard is designed in a standard 0.18? CMOS process. Integer N topology is chosen for the implementation. Synthesizer consists of third order passive loop filter; a CML based programmable frequency divider, a standard tristate PFD, a switch on source topology based charge pump and an on chip quadrature VCO. Simulated settling

Saurabh Kumar Singh; T. K. Bhattacharyya; Ashudeb Dutta

2005-01-01

277

3D integration of sub-surface photonics with CMOS  

Microsoft Academic Search

The integration of photonics and electronics on a single silicon substrate requires technologies that can add optical functionalities without significantly sacrificing valuable wafer area. To this end, we have developed an innovative fabrication process, called SIMOX 3-D Sculpting, that enables monolithic optoelectronic integration in a manner that does not compromise the economics of CMOS manufacturing. In this technique, photonic devices

Bahram Jalali; Tejaswi Indukuri; Prakash Koonath

2006-01-01

278

Pulse frequency modulation based CMOS image sensor for subretinal stimulation  

Microsoft Academic Search

We have developed a CMOS image sensor based on pulse frequency modulation for subretinal implantation. The sensor chip forms part of the proposed intraocular retinal prosthesis system where data and power transmission are provided wirelessly from an extraocular unit. Image sensing and electrical stimulus are integrated onto the same chip. Image of sufficient resolution has been demonstrated using 16times16 pixels.

David C. Ng; Tetsuo Furumiya; Koutaro Yasuoka; Akihiro Uehara; Keiichiro Kagawa; Takashi Tokuda; Masahiro Nunoshita; Jun Ohta

2006-01-01

279

CMOS Transistor Mismatch Model valid from Weak to Strong Inversion  

E-print Network

CMOS Transistor Mismatch Model valid from Weak to Strong Inversion Teresa Serrano and PMOS transistors for 30 different geometries has been done with this continuos model. The model is able of transistor mismatch is crucial for precision analog design. Using very reduced transistor geometries produces

Barranco, Bernabe Linares

280

Investigation of hot carrier effects on RF CMOS integrated circuits  

Microsoft Academic Search

With the continual down-scaling of the channel length of MOSFETs, CMOS technology is being increasingly used for the implementation of radio frequency (RF) circuits and systems. However, with technological scale down of dimensions, the supply voltage is not reduced in the same proportion as the channel length, leading to the presence of strong electric fields in the device. Carriers which

Sasan Naseh

2005-01-01

281

IBM Systems and Technology Electronics IBM CMOS 7HV for  

E-print Network

companies can significantly improve these metrics today by using IBM technology in smart solar- panel to improve effi- ciency, cost per kilowatt and reliability of solar modules IBM CMOS 7HV is the industry, cost per kilowatt and reliability of solar modules. While this research is critical, photovoltaics

282

Novel integrated CMOS pixel structures for vertex detectors  

Microsoft Academic Search

Novel CMOS active pixel structures for vertex detector applications have been designed and tested. The overriding goal of this work is to increase the signal to noise ratio of the sensors and readout circuits. A large-area native epitaxial silicon photogate was designed with the aim of increasing the charge collected per struck pixel and to reduce charge diffusion to neighboring

Stuart Kleinfelder; Fred Bieser; Yandong Chen; Robin Gareus; Howard S. Matis; Markus Oldenburg; F. Retierc; Hans Georg Ritter; Howard H. Wieman; Eugene Yamamoto

2003-01-01

283

Effects Of Dose Rates On Radiation Damage In CMOS Parts  

NASA Technical Reports Server (NTRS)

Report describes measurements of effects of ionizing-radiation dose rate on consequent damage to complementary metal oxide/semiconductor (CMOS) electronic devices. Depending on irradiation time and degree of annealing, survivability of devices in outer space, or after explosion of nuclear weapons, enhanced. Annealing involving recovery beyond pre-irradiation conditions (rebound) detrimental. Damage more severe at lower dose rates.

Goben, Charles A.; Coss, James R.; Price, William E.

1990-01-01

284

Integrating Conjugated Polymer Microactuators with CMOS Sensing Circuitry  

E-print Network

, but it is also an advantage for cell clinics because there is negligible electrolysis of water near the cells of polypyrrole actuators as well as the wide range of CMOS sensors that can be created. System integration of the whole system, along with any opportunities that present themselves. In this paper, we discuss some

Maryland at College Park, University of

285

Accurate thermal noise model for deep-submicron CMOS  

Microsoft Academic Search

Extensive measurements of drain current thermal noise are presented for 3 different CMOS technologies and for gate lengths ranging from 2 ?m down to 0.17 ?m. Using a surface-potential-based compact MOS model with improved descriptions of carrier mobility and velocity saturation, all the experimental results can be described accurately without invoking carrier heating effects or introducing additional parameters

A. J. Scholten; H. J. Tromp; L. F. Tiemeijer; R. Van Langevelde; R. J. Havens; P. W. H. De Vreede; R. F. M. Roes; P. H. Woerlee; A. H. Montreen; D. B. M. Klaassen

1999-01-01

286

Schottky Diode RF Detectors RF Pulse Effects on CMOS Logic  

E-print Network

Schottky Diode RF Detectors and RF Pulse Effects on CMOS Logic Boise State University: (Schottky diodes) -- diodes fabricated and tested (DC and RF) -- diodes for high freq. operation, preliminary fab and test at DC, RF structures designed -- integrated circuits designed with diodes connected

Anlage, Steven

287

Shallow trench isolation for advanced ULSI CMOS technologies  

Microsoft Academic Search

This paper reviews the requirements and challenges in designing a Shallow Trench Isolation (STI) process flow for 0.1 ?m CMOS technologies. Various processing techniques are described for the steps in the STI flow viz. trench definition, corner rounding, gapfill, planarization and well implants. The current capability and scaling requirements for each process step, discussed in the paper, are as follows:

M. Nandakumar; A. Chatterjee; S. Sridhar; K. Joyner; M. Rodder; I.-C. Chen

1998-01-01

288

Testing for bridging faults (shorts) in CMOS circuits  

Microsoft Academic Search

The stuck-at fault model, which is commonly used with fault simulation, does not adequately evaluate the effects of bridging faults (shorts between adjacent signal lines) in CMOS circuits. Tests for bridging faults can be performed on automatic test equipment, and the test vectors can be evaluated using logic simulation.

John M. Acken

1983-01-01

289

Process flow innovations for photonic device integration in CMOS  

NASA Astrophysics Data System (ADS)

Multilevel thin film processing, global planarization and advanced photolithography enables the ability to integrate complimentary materials and process sequences required for high index contrast photonic components all within a single CMOS process flow. Developing high performance photonic components that can be integrated with electronic circuits at a high level of functionality in silicon CMOS is one of the basic objectives of the EPIC program sponsored by the Microsystems Technology Office (MTO) of DARPA. Our research team consisting of members from: BAE Systems, Alcatel-Lucent, Massachusetts Institute of Technology, Cornell University and Applied Wave Research reports on the latest developments of the technology to fabricate an application specific, electronic-photonic integrated circuit (AS_EPIC). Now in its second phase of the EPIC program, the team has designed, developed and integrated fourth order optical tunable filters, both silicon ring resonator and germanium electro-absorption modulators and germanium pin diode photodetectors using silicon waveguides within a full 150nm CMOS process flow for a broadband RF channelizer application. This presentation will review the latest advances of the passive and active photonic devices developed and the processes used for monolithic integration with CMOS processing. Examples include multilevel waveguides for optical interconnect and germanium epitaxy for active photonic devices such as p-i-n photodiodes and modulators.

Beals, Mark; Michel, J.; Liu, J. F.; Ahn, D. H.; Sparacin, D.; Sun, R.; Hong, C. Y.; Kimerling, L. C.; Pomerene, A.; Carothers, D.; Beattie, J.; Kopa, A.; Apsel, A.; Rasras, M. S.; Gill, D. M.; Patel, S. S.; Tu, K. Y.; Chen, Y. K.; White, A. E.

2008-02-01

290

GPCAD: a tool for CMOS op-amp synthesis  

Microsoft Academic Search

We present a method for optimizing and automating compo- nent and transistor sizing for CMOS operational amplifiers. We observe that a wide variety of performance measures can be formulated as posynomial functions of the design variables. As a result, amplifier design problems can be formulated as a ge- ometric program, a special type of convex optimization problem for which very

Maria del Mar Hershenson; Stephen P. Boyd; Thomas H. Lee

1998-01-01

291

Low Power CMOS Electronic Central Pattern Generator Design  

E-print Network

1 Low Power CMOS Electronic Central Pattern Generator Design for a Biomimetic Underwater Robot-based analog controller for an autonomous robot. The operation of a neuronal circuit formed of electronic programs to control the legs of autonomous robots. Index Terms-- subthreshold operation, Central Pattern

Ayers, Joseph

292

Integrated imaging sensor systems with CMOS active pixel sensor technology  

NASA Technical Reports Server (NTRS)

This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

2002-01-01

293

Thin Film on CMOS Active Pixel Sensor for Space Applications  

PubMed Central

A 664 × 664 element Active Pixel image Sensor (APS) with integrated analog signal processing, full frame synchronous shutter and random access for applications in star sensors is presented and discussed. A thick vertical diode array in Thin Film on CMOS (TFC) technology is explored to achieve radiation hardness and maximum fill factor.

Schulze Spuentrup, Jan Dirk; Burghartz, Joachim N.; Graf, Heinz-Gerd; Harendt, Christine; Hutter, Franz; Nicke, Markus; Schmidt, Uwe; Schubert, Markus; Sterzel, Juergen

2008-01-01

294

Low-Voltage CMOS Comparators With Programmable Hysteresis  

E-print Network

............................................................28 3.2.2 High-swing cascode current source.....................................29 3.2.3 OperationLow-Voltage CMOS Comparators With Programmable Hysteresis BY VISHNU B. KULKARNI Master of Science of comparators with programmable hysteresis. Optimizations are done in order to obtain minimum DC offsets

Furth, Paul

295

Built-In Current Sensor for IDDQ Test in CMOS  

Microsoft Academic Search

This paper presents a current sensor circuit which can be built into a CMOS logic circuit to perform a self test for leakage current. The distinct features of the current sensor circuitry are described in detail. The circuit is verified by using the SPICE2 simulator

Ching-wen Hsue; Chih-jen Lin

1993-01-01

296

Compact CMOS linear transconductor and four-quadrant analogue multiplier  

Microsoft Academic Search

This paper describes a low voltage\\/low power MOS linear transconductor which can be configured to realize a square-law function circuit and a four quadrant analogue multiplier. The compact analogue computation cells described are particularly suited to parallel processing systems. The circuits were fabricated using a 0.8 ?m CMOS process and operate from a 2 V power supply.

Mladen Panovic; Andreas Demosthenous

2004-01-01

297

Test Considerations for Gate Oxide Shorts in CMOS ICs  

Microsoft Academic Search

Gate oxide shorts are defects that must be detected to produce high-reliability ICs. These problems will continue as devices are scaled down and oxide thicknesses are reduced to the 100-?? range. Complete detection of gate oxide shorts and other CMOS failure mechanisms requires measuring the IDD current during the quiescent state after each test vector is applied to the IC.

Jerry M. Soden; Charles Hawkins

1986-01-01

298

Defect classes-an overdue paradigm for CMOS IC testing  

Microsoft Academic Search

The IC test industry has struggled for move than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the rest

Charles F. Hawkins; Jerry M. Soden; A. W. Righter; F. Joel Fergusonti

1994-01-01

299

Nested Miller compensation in low-power CMOS design  

Microsoft Academic Search

First, new stability conditions for low-power CMOS nested Miller compensated amplifiers are given in this brief. Then, an improved structure, which takes the advantages of a feedforward transconductance stage and a nulling resistor, is introduced. Experimental results prove that the proposed structure improves the frequency response, transient response, and power supply rejection ratio without increasing the power consumption and circuit

Ka Nang Leung; Philip K. T. Mok

2001-01-01

300

Energy Efficient Implementation of Parallel CMOS Multipliers with Improved Compressors  

E-print Network

Energy Efficient Implementation of Parallel CMOS Multipliers with Improved Compressors Dursun Baran targets. In addition, novel 3:2 and 4:2 compressors are pre- sented to save energy at the same target delay. The proposed compressors provide up to 20% energy reduction depending on the target delay at 65nm

California at Davis, University of

301

Dynamic internal testing of CMOS circuits using hot luminescence  

Microsoft Academic Search

Subnanosecond pulses of hot electron luminescence are shown to be generated coincident with logic state switching of individual devices in CMOS circuits. These pulses are used to directly observe 90 ps gate delays in a ring oscillator as well as the logic switching and gate delays of a counter. By use of a detector with both space- and time-resolution, the

J. A. Kash; J. C. Tsang

1997-01-01

302

Stochastic Gradient Descent Optimization for Low Power Nano-CMOS  

E-print Network

Contributions Design flow methodology incorporating SGD for nano-CMOS design optimization Modification of SGD the gradient descent approach SGD reiteratively steps through the gradient descent until it converges At each is randomly chosen ­ also referred as training set Modified SGD restarts at random points to mitigate local

Mohanty, Saraju P.

303

CMOS VLSI Layout and Verification of a SIMD Computer  

NASA Technical Reports Server (NTRS)

A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

Zheng, Jianqing

1996-01-01

304

CMOS image sensors as an efficient platform for glucose monitoring.  

PubMed

Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications. PMID:23900281

Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

2013-10-01

305

CMOS Active-Pixel Image Sensor With Simple Floating Gates  

NASA Technical Reports Server (NTRS)

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

306

A realization of low-distortion CMOS transconductance amplifier  

Microsoft Academic Search

A new CMOS transconductance amplifier with low-harmonic distortion is proposed. The used technique is based on the parallel connection of two amplifiers. The first transconductor is working in the triode region, the other one is in the saturation. Compared to the known method, the realization of the discussed circuit provides a good value of Gm\\/I parameter and lower power consumption.

D. V. Morozov; A. S. Korotkov

2001-01-01

307

Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs  

Microsoft Academic Search

We analyze a transient current testing technique that measures and computes the charge delivered to the circuit during the transient operation. The method was applied to 0.5 ?m CMOS SRAMs that passed various logic tests. Results indicate that charge based testing (CBT) can successfully test submicron ICs since it tolerates large and variable background currents, can be applied to non-fully

B. Alorda; M. Rosales; Jerry M. Soden; Charles F. Hawkins; Jaume Segura

2002-01-01

308

Single Event Upset Behavior of CMOS Static RAM Cells  

NASA Technical Reports Server (NTRS)

An improved state-space analysis of the CMOS static RAM cell is presented. Introducing theconcept of the dividing line, the critical charge for heavy-ion-induced upset of memory cells can becalculated considering symmetrical as well as asymmetrical capacitive loads. From the criticalcharge, the upset-rate per bit-day for static RAMs can be estimated.

Lieneweg, Udo; Jeppson, Kjell O.; Buehler, Martin G.

1993-01-01

309

X-ray imaging and spectroscopy using low cost COTS CMOS sensors  

NASA Astrophysics Data System (ADS)

Whilst commercial X-ray sensor arrays are capable of both imaging and spectroscopy they are currently expensive and this can limit their widespread use. This study examines the use of very low cost CMOS sensors for X-ray imaging and spectroscopy based on the commercial off the shelf (COTS) technology used in cellular telephones, PC multimedia and children's toys. Some examples of imaging using a 'webcam' and a modified OmniVision OV7411 sensor are presented, as well as a simple energy dispersive X-ray detector based on an OmniVision OV7221 sensor. In each case X-ray sensitivity was enabled by replacing the sensor's front glass window with a 5 ?m thick aluminium foil, with X-rays detected as an increase in a pixel's dark current due to the generation of additional electron-hole pairs within its active region. The exposure control and data processing requirements for imaging and spectroscopy are discussed. The modified OV7221 sensor was found to have a linear X-ray energy calibration and a resolution of approximately 510 eV.

Lane, David W.

2012-08-01

310

Radiation-hard active CMOS pixel sensors for HL-LHC detector upgrades  

NASA Astrophysics Data System (ADS)

The luminosity of the Large Hadron Collider (LHC) will be increased during the Long Shutdown of 2022 and 2023 (LS3) in order to increase the sensitivity of its experiments. A completely new inner detector for the ATLAS experiment needs to be developed to withstand the extremely harsh environment of the upgraded, so-called High-Luminosity LHC (HL-LHC). High radiation hardness as well as granularity is mandatory to cope with the requirements in terms of radiation damage as well as particle occupancy. A new silicon detector concept that uses commercial high voltage and/or high resistivity full complementary metal-oxide-semiconductor (CMOS) processes as active sensor for pixel and/or strip layers has risen high attention, because it potentially provides high radiation hardness and granularity and at the same time reduced price due to the commercial processing and possibly relaxed requirements for the hybridization technique. Results on the first prototypes characterized in a variety of laboratory as well as test beam environments are presented.

Backhaus, Malte

2015-02-01

311

Supporting Information Packaging Commercial CMOS Chips for Lab on a Chip Integration  

E-print Network

with photoresist to permit selective deposition of PEDOT:PSS onto the recording and reference electrodes. (The exposure.) Figure 5. The electrodeposition setup for PEDOT:PSS, which occurs after the handle wafer. Close-up of the chip surface after selective PEDOT:PSS deposition. Figure 7. The edge of a chip after

Shapiro, Benjamin

312

Practicality of Evaluating Soft Errors in Commercial sub-90 nm CMOS for Space Applications  

NASA Technical Reports Server (NTRS)

The purpose of this presentation is to: Highlight space memory evaluation evolution, Review recent developments regarding low-energy proton direct ionization soft errors, Assess current space memory evaluation challenges, including increase of non-volatile technology choices, and Discuss related testing and evaluation complexities.

Pellish, Jonathan A.; LaBel, Kenneth A.

2010-01-01

313

Dark Current Characterization of the CMOS APS Imagers with Test Patterns Fabricated Using a 0.18 CMOS Technology  

E-print Network

#12;Dark Current Characterization of the CMOS APS Imagers with Test Patterns Fabricated Using a 0. of Electronics, Sejong University, Seoul 143-747, KOREA Abstracts - The characteristics of dark currents have found that the peripheral contribution of the photo-diode is the dominant source of dark currents in our

Lee, Jong Duk

314

A new characterization method for accurate capacitor matching measurements using pseudo-floating gate test structures in submicron CMOS and BiCMOS technologies  

Microsoft Academic Search

In deep submicron CMOS and BiCMOS technologies, antenna effects affect the floating gate charge of conventional floating gate test structures, dedicated to capacitor matching measurement. In this paper, a new pseudo-floating gate test structure is designed. After test structure and modeling presentation, the testing method and results are given for several capacitor layouts (poly-poly and metal-metal)

O. Roux dit Buisson; G. Morin; F. Paillardet; E. Mazaleyrat

1998-01-01

315

Commercial Buildings Characteristics, 1992  

SciTech Connect

Commercial Buildings Characteristics 1992 presents statistics about the number, type, and size of commercial buildings in the United States as well as their energy-related characteristics. These data are collected in the Commercial Buildings Energy Consumption Survey (CBECS), a national survey of buildings in the commercial sector. The 1992 CBECS is the fifth in a series conducted since 1979 by the Energy Information Administration. Approximately 6,600 commercial buildings were surveyed, representing the characteristics and energy consumption of 4.8 million commercial buildings and 67.9 billion square feet of commercial floorspace nationwide. Overall, the amount of commercial floorspace in the United States increased an average of 2.4 percent annually between 1989 and 1992, while the number of commercial buildings increased an average of 2.0 percent annually.

Not Available

1994-04-29

316

Radiation-hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Technology  

E-print Network

Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. 1Corresponding author. c CERN 2014, published under the terms of the Creative Commons Attribution 3.0 License by IOP Publishing Ltd and Sissa Medialab srl. Any further distribution of this work must maintain attribution to the author(s) and the published article’s title, journal citation and DOI. doi:10.1088/1748-0221/9/05/C050642014 JINST 9 C05064 A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation a...

Miucci, A et al.

2014-01-01

317

Digital pixel CMOS focal plane array with on-chip multiply accumulate units for low-latency image processing  

NASA Astrophysics Data System (ADS)

A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization occurs at the pixel level, enabling in-pixel DSP and noiseless data transfer from the pixel array to the peripheral processing units. The pipelined processing of row and column image data prior to off chip readout reduces the required output bandwidth of the image sensor, thus reducing the latency of computations necessary to implement various image processing systems. Data volume reductions of over 80% lead to sub 10?s latency for completing various tracking and sensor algorithms. This paper details the architecture of the pixel-processing imager (PPI) and presents some initial results from a prototype device fabricated in a standard 65nm CMOS process hybridized to a commercial off-the-shelf short-wave infrared (SWIR) detector array.

Little, Jeffrey W.; Tyrrell, Brian M.; D'Onofrio, Richard; Berger, Paul J.; Fernandez-Cull, Christy

2014-06-01

318

Development of a CMOS SOI Pixel Detector  

SciTech Connect

We have developed a monolithic radiation pixel detector using silicon on insulator (SOI) with a commercial 0.15 {micro}m fully-depleted-SOI technology and a Czochralski high resistivity silicon substrate in place of a handle wafer. The SOI TEG (Test Element Group) chips with a size of 2.5 x 2.5 mm{sup 2} consisting of 20 x 20 {micro}m{sup 2} pixels have been designed and manufactured. Performance tests with a laser light illumination and a {beta} ray radioactive source indicate successful operation of the detector. We also briefly discuss the back gate effect as well as the simulation study.

Arai, Y.; Hazumi, M.; Ikegami, Y.; Kohriki, T.; Tajima, O.; Terada, S.; Tsuboyama, T.; Unno, Y.; Ushiroda, Y.; /KEK, Tsukuba; Ikeda, H.; /JAXA, Sagamihara; Hara, K.; /Tsukuba U.; Ishino, H.; /Tokyo Inst. Tech.; Kawasaki, T.; /Niigata U.; Miyake, H.; /Osaka U.; Martin, E.; Varner, G.; /Hawaii U.; Tajima, H.; /SLAC; Ohno, M.; Fukuda, K.; Komatsubara, H.; Ida, J.; /NONE - OKI ELECTR INDUST TOKYO

2008-08-19

319

High-Voltage-Input Level Translator Using Standard CMOS  

NASA Technical Reports Server (NTRS)

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

2011-01-01

320

CMOS VLSI Active-Pixel Sensor for Tracking  

NASA Technical Reports Server (NTRS)

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The diagonal-switch and memory addresses would be generated by the on-chip controller. The memory array would be large enough to hold differential signals acquired from all 8 windows during a frame period. Following the rapid sampling from all the windows, the contents of the memory array would be read out sequentially by use of a capacitive transimpedance amplifier (CTIA) at a maximum data rate of 10 MHz. This data rate is compatible with an update rate of almost 10 Hz, even in full-frame operation

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

321

An ultra-low dark current CMOS image sensor cell using n+ ring reset  

Microsoft Academic Search

We present in this letter for the first time a new CMOS image sensor cell using n+-ring-reset structure, which can isolate the photon-sensing area from the defective field oxide edge. The experimental results demonstrate that the severe dark current degradation of the conventional CMOS active pixel image sensor fabricated by a standard CMOS logic process is significantly alleviated. Through optimizing

Hsiu-Yu Cheng; Ya-Chin King

2002-01-01

322

A CMOS image sensor with dark-current cancellation and dynamic sensitivity operations  

Microsoft Academic Search

An ultralow dark-signal and high-sensitivity pixel has been developed for an embedded active-pixel CMOS image sensor by using a standard 0.35-?m CMOS logic process. To achieve in-pixel dark-current cancellation, we developed a combined photogate\\/photodiode photon-sensing device with a novel operation scheme. The experimental results demonstrate that the severe dark signal degradation of a CMOS active pixel sensor is reduced more

Hsiu-Yu Cheng; Ya-Chin King

2003-01-01

323

Dark current reduction in stacked-type CMOS-APS for charged particle imaging  

Microsoft Academic Search

A stacked CMOS-active pixel sensor (APS) with a newly devised pixel structure for charged particle detection has been developed. At low operation temperatures (<200 K), the dark current of the CMOS-APS is determined by the hot carrier effect. A twin well CMOS pixel with a p-MOS readout and n-MOS reset circuit achieves low leakage current as low as 5×10-8 V\\/s

Isao Takayanagi; Junichi Nakamura; Eric R. Fossum; Kazuhide Nagashima; Takuya Kunihoro; Hisayoshi Yurimoto

2003-01-01

324

Low-power logic styles: CMOS versus pass-transistor logic  

Microsoft Academic Search

Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with

Reto Zimmermann; Wolfgang Fichtner

1997-01-01

325

Laminated high-aspect-ratio microstructures in a conventional CMOS process  

Microsoft Academic Search

Electrostatically actuated microstructures with high-aspect-ratio laminated-beam suspensions have been fabricated using a 0.8 ?m three-metal CMOS process followed by a sequence of three maskless dry-etching steps. Laminated structures are etched of the CMOS silicon oxide, silicon nitride, and aluminum layers. The key to the process is the use of the CMOS metallization as an etch-resistant mask to define the microstructures.

G. K. Fedder; S. Santhanam; M. L. Reed; S. C. Eagle; D. F. Guillou; M. S.-C. Lu; L. R. Carley

1996-01-01

326

A new readout circuit for an ultrahigh sensitivity CMOS image sensor  

Microsoft Academic Search

We have developed a new readout circuit for highly sensitive CMOS image sensors. The circuit makes it possible to obtain a high signal-to-noise ratio by effectively transferring signal charges accumulated in the photodiode to a small capacitance. We fabricated and tested a CMOS image sensor with the readout circuit, and confirmed that it has higher sensitivity than conventional passive-pixel CMOS

Toshihisa Watabe; Masahide Goto; Hiroshi Ohtake; Hirotaka Maruyama; Kenkichi Tanioka

2002-01-01

327

Post-CMOS Compatible Micromachining Technique for On-Chip Passive RF Filter Circuits  

Microsoft Academic Search

This paper reports on a post-CMOS compatible micromachining technology for passive RF circuit integration. The micromachining technology combines the formation of high performance microelectromechanical systems solenoid inductors and metal-insulator-metal (MIM) capacitors by using a post CMOS process on standard CMOS substrate. Utilizing this process, novel on-chip 3-D configured RF filters for 5 GHz band are integrated on-chip. Two types of

Zhengzheng Wu; Lei Gu; Xinxin Li

2009-01-01

328

Tournament-Shaped Magnetically Coupled Power-Combiner Architecture for RF CMOS Power Amplifier  

Microsoft Academic Search

A tournament-shaped magnetically coupled power-combiner architecture for a fully integrated RF CMOS power amplifier is proposed. Various 1 : 1 transmission line transformers are used to design the power combiner. To demonstrate the new architecture, a 1.81-GHz CMOS power amplifier using the tournament-shaped power combiner was implemented with a 0.18-mum RF CMOS process. All of the matching components, including the

Dong Ho Lee; Jeonghu Han; Songcheol Hong

2007-01-01

329

Development and characterization of CMOS-based monolithic X-ray imager sensor  

Microsoft Academic Search

We proposed a new design of CMOS-based X-ray image sensor with monolithically grown pixelated CsI(Tl) on photosensor area for securing the maximally achievable spatial resolution for a given sensitivity determined by the CsI(Tl) thickness at a certain X-ray energy. The test version of a CMOS image sensor (CIS) was designed and fabricated using AMIS 0.5 mum standard CMOS process. The

Gyuseong Cho; Bo Kyung Cha; Jun Hyung Bae; Byoung-Jik Kim; Sung Chae Jeon; Young-Hee Kim; Gyu-Ho Lim

2007-01-01

330

Algae Biodiesel: Commercialization  

E-print Network

Algae Biodiesel: A Path to Commercialization Algae Biodiesel: A Path to Commercialization Center conservation and biomonitoring · Algae biodiesel is largest CEHMM project #12;Project Overview: The Missing replace petroleum #12;Project Overview: Local Resources for Algae Biodiesel Project Overview: Local

Tullos, Desiree

331

Pennsylvania Commercial Vegetable  

E-print Network

Pennsylvania Commercial Vegetable Production Recommendations #12;NOT TO BE USED BY HOME GARDENERS This copy of the Pennsylvania Commercial Vegetable Production Recommendations for 2014 replaces all previous decisions. Although the proper choice of the variety, application, pesticide, equipment, fertilizer

Guiltinan, Mark

332

A triple gate oxide CMOS technology using fluorine implant for system-on-a-chip  

Microsoft Academic Search

We have developed a triple gate oxide CMOS technology that integrates 0.10-?m gate length 1.2-V high-speed CMOS (tox of 1.9 nm), low-power CMOS (tox of 2.5 nm) and 2.5-V I\\/O transistors (tox of 5.0 nm). The key technology is fluorine implantation in order to fabricate 1.9-nm and 2.5-nm gate oxide simultaneously. We selectively implanted fluorine into low-power CMOS area and

Y. Goto; K. Imai; E. Hasegawa; T. Ohashi; N. Kimizuka; T. Toda; N. Hamanaka; T. Horiuchi

2000-01-01

333

NASA commercial programs  

NASA Technical Reports Server (NTRS)

An expanded role for the U.S. private sector in America's space future has emerged as a key national objective, and NASA's Office of Commercial Programs is providing a focus for action. The Office supports new high technology commercial space ventures, the commercial application of existing aeronautics and space technology, and expanded commercial access to available NASA capabilities and services. The progress NASA has made in carrying out its new assignment is highlighted.

1988-01-01

334

Development of CMOS-compatible membrane projection lithography  

NASA Astrophysics Data System (ADS)

Recently we have demonstrated membrane projection lithography (MPL) as a fabrication approach capable of creating 3D structures with sub-micron metallic inclusions for use in metamaterial and plasmonic applications using polymer material systems. While polymers provide several advantages in processing, they are soft and subject to stress-induced buckling. Furthermore, in next generation active photonic structures, integration of photonic components with CMOS electronics is desirable. While the MPL process flow is conceptually simple, it requires matrix, membrane and backfill materials with orthogonal processing deposition/removal chemistries. By transitioning the MPL process flow into an entirely inorganic material set based around silicon and standard CMOS-compatible materials, several elements of silicon microelectronics can be integrated into photonic devices at the unit-cell scale. This paper will present detailed fabrication and characterization data of these materials, emphasizing the processing trade space as well as optical characterization of the resulting structures.

Burckel, D. Bruce; Samora, Sally; Wiwi, Mike; Wendt, Joel R.

2013-09-01

335

Static power saving TTL-to-CMOS input buffer  

NASA Astrophysics Data System (ADS)

This paper describes a TTL-to-CMOS input buffer that has no static power consumption for the typical TTL voltage level. The input buffer utilizes a feedback configuration to eliminate static power consumption that renders hysteresis characteristic. The hysteresis characteristic is equivalent to that of a Schmitt trigger and thus provides good noise immunity. A prototype circuit was implemented in a 0.8 micron CMOS process, and the through current is measured to be only 8.9 mu A and 11.7 mu A for the input of 0.8 V and 2.2 V (the worst case TTL level), respectively. The input buffer gives full-swing output up to 170 MHz when driving a minimum sized inverter with the worst case TTL level according to SPICE simulation (left bracket) 1 (right bracket).

Yoo, Changsik; Kim, Min-Kyu; Kim, Wonchan

1995-05-01

336

High dynamic range CMOS (HDRC) imagers for safety systems  

NASA Astrophysics Data System (ADS)

The first part of this paper describes the high dynamic range CMOS (HDRC®) imager - a special type of CMOS image sensor with logarithmic response. The powerful property of a high dynamic range (HDR) image acquisition is detailed by mathematical definition and measurement of the optoelectronic conversion function (OECF) of two different HDRC imagers. Specific sensor parameters will be discussed including the pixel design for the global shutter readout. The second part will give an outline on the applications and requirements of cameras for industrial safety. Equipped with HDRC global shutter sensors SafetyEYE® is a high-performance stereo camera system for safe three-dimensional zone monitoring enabling new and more flexible solutions compared to existing safety guards.

Strobel, Markus; Döttling, Dietmar

2013-04-01

337

Thermally controlled electrochemical CMOS microsystem for protein array biosensors.  

PubMed

Because many proteins useful in biosensors exhibit temperature dependent activity, this paper explores the opportunity to integrate thermal control within a protein array biosensor microsystem. A CMOS microhotplate array tailored to protein interfaces was developed for thermoregulation in a liquid sample environment. The microhotplates were shown to provide suitable thermal control for biosensor temperature ranges without the process complexity of most previously reported microhotplates. When combined with a CMOS analog thermal controller, the on-chip array was shown to set and hold temperatures for each protein site within ±1(°) C, and array elements were found to be almost completely thermally isolated from each other at distances beyond 0.4 mm. The compact size and low power of this controller enable it to be combined with the thermal control structures and instantiated for every element in a sensor array to increase biosensor interrogation throughput. PMID:24681917

Liu, Xiaowen; Li, Lin; Mason, Andrew J

2014-02-01

338

Monolithic CMOS-MEMS integration for high-g accelerometers  

NASA Astrophysics Data System (ADS)

This paper highlights work-in-progress towards the conceptualization, simulation, fabrication and initial testing of a silicon-germanium (SiGe) integrated CMOS-MEMS high-g accelerometer for military, munition, fuze and shock measurement applications. Developed on IMEC's SiGe MEMS platform, the MEMS offers a dynamic range of 5,000 g and a bandwidth of 12 kHz. The low noise readout circuit adopts a chopper-stabilization technique implementing the CMOS through the TSMC 0.18 µm process. The device structure employs a fully differential split comb-drive set up with two sets of stators and a rotor all driven separately. Dummy structures acting as protective over-range stops were designed to protect the active components when under impacts well above the designed dynamic range.

Narasimhan, Vinayak; Li, Holden; Tan, Chuan Seng

2014-10-01

339

Heavy-ion-induced snapback in CMOS devices. Technical report  

SciTech Connect

Single-event snapback (SES) susceptibilities of selected complementary metal-oxide semiconductor (CMOS) devices to heavy ions were measured, first using N, NE, Ar, Cu and Kr ion beams. Like latchup, snapback was observed macroscopically by detecting the abnormally high bias current condition. However, the snapback susceptibility characteristics differed from those of latchup, and consequently we could unambiguously measure the snapback responses. The responses are expressed in terms of the cross section for varying bias and the stopping power of ions. Test data indicate that CMOS devices with rather long channel lengths (on the order of 3 um) are free from SES when operated about 5 V. However, present-day theories have predicted that this regenerative breakdown mode of upset may become very important at 5 V below for devices with extremely short n-channel lengths.

Koga, R.; Kolasinski, W.A.

1990-08-15

340

Smart CMOS image sensor for lightning detection and imaging.  

PubMed

We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 ?m pixel pitch has been fabricated using a 0.35 ?m 2P 5M technology and tested to validate the selected detection approach. PMID:23458812

Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

2013-03-01

341

Diffuse reflectance measurements using lensless CMOS imaging chip  

NASA Astrophysics Data System (ADS)

To assess superficial epithelial microcirculation, a diagnostic tool should be able to detect the heterogeneity of microvasculature, and to monitor qualitative derangement of perfusion in a diseased condition. Employing a lensless CMOS imaging chip with an RGB Bayer filter, experiments were conducted with a microfluidic platform to obtain diffuse reflectance maps. Haemoglobin (Hb) solution (160 g/l) was injected in the periodic channels (grooves) of the microfluidic phantom which were covered with ~250 ?m thick layer of intralipid to obtain a diffusive environment. Image processing was performed on data acquired on the surface of the phantom to evaluate the diffuse reflectance from the subsurface periodic pattern. Thickness of the microfluidic grooves, the wavelength dependent contrast between Hb and the background, and effective periodicity of the grooves were evaluated. Results demonstrate that a lens-less CMOS camera is capable of capturing images of subsurface structures with large field of view.

Schelkanova, I.; Pandya, A.; Shah, D.; Lilge, L.; Douplik, A.

2014-10-01

342

Commercial Banking Industry Survey.  

ERIC Educational Resources Information Center

Work and family programs are becoming increasingly important in the commercial banking industry. The objective of this survey was to collect information and prepare a commercial banking industry profile on work and family programs. Fifty-nine top American commercial banks from the Fortune 500 list were invited to participate. Twenty-two…

Bright Horizons Children's Centers, Cambridge, MA.

343

Commercialization of space  

Microsoft Academic Search

Space-commercialization activities are grouped into five categories: private sector development from existing technology for private sector use; pure privatization; private sector development for US government use; private sector development from novel technology for private sector use; and, finally, full commercialization. The authors define the commercialization of space categories and highlight the key issues in each. A description of key NASA

J. T. Rose; B. A. Stone

1988-01-01

344

Commercialism in Schools.  

ERIC Educational Resources Information Center

This document gives voice to concerns raised by critics and supporters of commercialism in schools and provides brief descriptions of several important resources on this topic. "Commercial Activities in School" (U.S. General Accounting Office) reports on the nature and frequency of commercial activities in public schools, as well as the laws and…

Larson, Kirstin

2001-01-01

345

Radiation-hardened bulk Si-gate CMOS microprocessor family  

Microsoft Academic Search

RCA and Sandia Laboratories jointly developed a radiation-hardened bulk Si-gate CMOS technology which is used to fabricate the CDP-1800 series microprocessor family. Total dose hardness of 1 x 10 rads (Si) and transient upset hardness of 5 x 10 rads (Si)\\/sec with no latch up at any transient level was achieved. Radiation-hardened parts manufactured to date include the CDP-1802 microprocessor,

R. E. Stricker; A. G. F. Dingwall; S. Cohen; J. R. Adams; W. C. Slemmer

1979-01-01

346

Standard CMOS piezoresistive sensor to quantify heart cell contractile forces  

Microsoft Academic Search

A MEMS force transducer system, with a volume less than one cubic millimeter, is being developed to measure forces generated by living, isolated cardiac muscle cells. Cell attachment and measurement of contractile forces have been demonstrated with prototype hinged polysilicon devices. A new transducer system has been fabricated using a standard CMOS process with a post-processing XeF2 etch step. The

Gisela Lin; Kristofer S. J. Pister; Kenneth P. Roos

1996-01-01

347

A 200MHz 64-b dual-issue CMOS microprocessor  

Microsoft Academic Search

A 400-MIPS\\/200-MFLOPS (peak) custom 64-b VLSI CPU is described. The chip is fabricated in a 0.75-?m CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm×13.9 mm and contains 1.68 M transistors. The chip includes separate 8-kbyte instruction and data caches and a fully pipelined floating-point unit (FPU) that can handle both

D. W. Dobberpuhl; R. T. Witek; R. Allmon; R. Anglin; D. Bertucci; S. Britton; L. Chao; R. A. Conrad; D. E. Dever; B. Gieseke; S. M. N. Hassoun; G. W. Hoeppner; K. Kuchler; M. Ladd; B. M. Leary; L. Madden; E. J. McLellan; D. R. Meyer; J. Montanaro; D. A. Priore; V. Rajagopalan; S. Samudrala; S. Santhanam

1992-01-01

348

Accelerated life testing effects on CMOS microcircuit characteristics, phase 1  

NASA Technical Reports Server (NTRS)

An accelerated life test of sufficient duration to generate a minimum of 50% cumulative failures in lots of CMOS devices was conducted to provide a basis for determining the consistency of activation energy at 250 C. An investigation was made to determine whether any thresholds were exceeded during the high temperature testing, which could trigger failure mechanisms unique to that temperature. The usefulness of the 250 C temperature test as a predictor of long term reliability was evaluated.

Maximow, B.

1976-01-01

349

Linear dynamic range enhancement in a CMOS imager  

NASA Technical Reports Server (NTRS)

A CMOS imager with increased linear dynamic range but without degradation in noise, responsivity, linearity, fixed-pattern noise, or photometric calibration comprises a linear calibrated dual gain pixel in which the gain is reduced after a pre-defined threshold level by switching in an additional capacitance. The pixel may include a novel on-pixel latch circuit that is used to switch in the additional capacitance.

Pain, Bedabrata (Inventor)

2008-01-01

350

Diagnosing CMOS bridging faults with stuck-at fault dictionaries  

Microsoft Academic Search

It is shown that the traditional approach to diagnosing stuck-at faults with fault dictionaries generated for stuck-at faults is not appropriate for diagnosing CMOS bridging faults. A novel technique for using stuck-at-fault dictionaries to diagnose bridging faults is described. Teradyne's LASAR was used to simulate bridging and stuck-at faults in a number of combinational circuits, including parity trees, multiplexers, and

Steven D. Millman; Edward J. McCluskey; John M. Acken

1990-01-01

351

Comparison of CMOS microprocessors and single chip microcomputers  

Microsoft Academic Search

Three CMOS (Complimentary Metal Oxide Semiconductor) 8 bit microprocessors (CPU) and eleven versions of three single chip microcomputers (MCU) have been compared regarding hardware features, assembly language, bus architecture, and internal register architecture. They are the Intersil IM6100, National Semiconductor NSC-800, RCA CDP1802, Motorola MC146805E2, National Semiconductor NS80C35, and the RCA CDP1805. Several power reduction techniques for microcomputer systems are

T. Fryberger

1982-01-01

352

Towards ultimate CMOS performance with new stressor materials  

Microsoft Academic Search

In this paper, new technology options for boosting the performance of CMOS transistors pioneered by our group will be discussed. We focus on several new strain engineering techniques that were recently demonstrated for enhancing electron and hole mobilities in n-FET and p-FET, respectively. New applications of materials such as diamond-like carbon high-stress liner, silicon-carbon (Si:C or Si1-yCy) source\\/drain, and silicon-germanium-tin

Yee-Chia Yeo

2008-01-01

353

High performance fully-depleted tri-gate CMOS transistors  

Microsoft Academic Search

Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate

B. S. Doyle; S. Datta; M. Doczy; S. Hareland; B. Jin; J. Kavalieros; T. Linton; A. Murthy; R. Rios; R. Chau

2003-01-01

354

TFSOI CMOS technology for sub-1 V microcontroller circuits  

Microsoft Academic Search

For the first time, a sub-1 V microcontroller CPU core is demonstrated using Thin-Film-Silicon-On-Insulator (TFSOI) CMOS technology. Yield sensitivity of the microcontroller circuit blocks (including the CPU, SRAM and ROM) to variations of the 0.5 ?m process technology is investigated. The low-voltage circuit yield of the CPU is found to be more sensitive to isolation stress-induced device defect leakage than

W. M. Huang; K. Papworth; M. Racanelli; J. P. John; J Foerrstner; H. C. Shin; B. Y. Hwang; T. Wetteroth; S. Hong; S. Wilson; S. Cheng

1995-01-01

355

Reconfigurable CMOS LNA for software defined radio using variable inductor  

Microsoft Academic Search

This paper proposes a novel wide-tunable CMOS low noise amplifier (LNA) using on-chip variable inductor. The proposed tunable LNA can be utilized for multi-band RF front-end of software defined radio (SDR) and realizes a handheld terminal to enable global roaming. The LNA achieves power gain (PG) of over 10dB at 1.7-3.2 GHz tuning range.

Hirotaka Sugawara; Yoshiaki Yoshihara; Kenichi Okada; Kazuya Masu

2005-01-01

356

Manufacturable triple level metal technology for submicron CMOS  

Microsoft Academic Search

The triple-level-metal (TLM) module of a submicron CMOS technology with (titanium) salicided devices is discussed. The key technology features of the module include the use of conformal BPSG for enhanced planarization, a TiN barrier layer under M1, plasma-dry-tapered contacts and vias, and TiN antireflection coatings for metal patterning. Large-area test structures for each TLM component were used to develop and

W. Paulson; J. Klein; M. Woo; T. Kobayashi; R. Hendrix; E. Travis; F. Pintchovski; Y.-C. See

1990-01-01

357

A CMOS receiver with single RF channel for SMILE applications  

Microsoft Academic Search

This letter describes a single RF channel using a fully integrated multiplex LNA (Low Noise Amplifier) with four input channels and a double-balanced mixer in a 0.35 mum CMOS technology for SMILE (Spatial MultIplexing of Local Elements) applications. This technique is a front-end architecture which uses only one RF channel, carrying multiplexed information from multiple antennas. The performance characteristics of

C. E. Capovilla; A. Tavora de Albuquerque Silva; L. C. Kretly

2009-01-01

358

A high performance CMOS readout integrated circuit for IRFPA  

Microsoft Academic Search

A high performance, 128×128 pixel, snapshot Readout Integrated Circuit (ROIC) for IRFPA has been fabricated with 0.5mum Double Poly Double Metal (DPDM) n-well CMOS process. The pixel cell circuit uses an improved direct injection structure with only four transistors to maintain large enough integration capacitror. One pixel cell occupies an area of 50×50mum2. Each row's pixel signals are readout to

Xiaojuan Xia; Liang Xie; Weifeng Sun

2008-01-01

359

Radiation hardening of ASICs in deep submicron CMOS technologies  

NASA Astrophysics Data System (ADS)

The radiation hardness is a critical issue for a number of ASIC applications. The ASICs used in space, physics experiments or in medical instrumentations have to deal with the radiation and its effects. The paper gives a short overview of the radiation-induced effects in the CMOS devices and presents design and system aspects of the ASIC radiation hardening. Examples of chips designed for heavy radiation environment are presented.

Szczygiel, Robert

2005-02-01

360

CMOS floating-point vector-arithmetic unit  

NASA Astrophysics Data System (ADS)

This work describes a floating-point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine, hyperbolic (co)sine, square root, natural logarithm, inverse (hyperbolic) tangent, vector norm, and phase. The chip has been integrated in 1.6 micron double-metal n-well CMOS technology and achieves a normalized peak performance of 220 MFLOPS.

Timmermann, D.; Rix, B.; Hahn, H.; Hosticka, B. J.

1994-05-01

361

Capacitive sensors in CMOS technology with polymer coating  

Microsoft Academic Search

In this paper we report the fabrication of a new integrated capacitive chemical sensor by industrial CMOS technology, followed by a single maskless polymer-coating step. An on-chip sigma-delta modulator measures the difference between the sensing and reference capacitors, performs offset and gain calibration and provides a digital output signal. Experimental data have been obtained in a series of measurements, in

C. Cornila; A. Hierlemann; R. Lenggenhager; P. Malcovati; H. Baltes; G. Noetzel; U. Weimar

1995-01-01

362

Development of a silicon gate CMOS technology with small structures  

NASA Astrophysics Data System (ADS)

The development of HCMOS technology for 3 to 4 microns structures in order to improve packing density and performance for very large scale integration CMOS circuits, operating at 1,5V, is outlined. Design rule definition, photolithography/contact and projection, layout techniques, and process development (high value polysilicon resistors) are discussed. The technology developed was successfully demonstrated on an advanced 4 MHz (1,5V) watch circuit.

Milosevic, I.; Tilenschi, L.; Luft, R.; Cornwell, D.

1982-09-01

363

Beta-CMOS Artificial Neuron and Implementability Limits  

Microsoft Academic Search

The paper is focused on the functional possibilities (class of representable threshold functions), parameter stability and\\u000a learnability of the artificial learnable neuron implemented on the base of CMOS ?-driven threshold element. A neuron ?-comparator\\u000a circuit is suggested with a very high sensitivity to input current change that allows us to sharply increase the threshold\\u000a value of the functions. The SPICE

Victor Varshavsky I; Vyacheslav Marakhovsky

1999-01-01

364

A CMOS high-speed wide-range programmable counter  

Microsoft Academic Search

A CMOS high speed wide-range programmable divide-by-N counter was designed and the performance was verified by SPICE simulations and the measurements on the fabricated chip. A new reloading scheme and the use of simplified circuits for three least significant bit flip-flops enabled the high-speed operation of the proposed counter, independently of the number of counter stages. The proposed and Chang's

Sang-Hoon Lee; Hong June Park

2002-01-01

365

A novel Voltage-mode CMOS quaternary logic design  

Microsoft Academic Search

This brief presents a novel kind of voltage-mode CMOS design that uses multiple threshold voltage transistors and three power supply lines to implement quaternary logic gates, showing lower power dissipation and using less area than the present voltage-mode quaternary circuits. Inverter, NMIN, and NMAX gates are simulated with the Spice tool using TSMC 0.18-?m technology. The proposed logic circuits overcome

R. C. G. da Silva; H. Boudinov; L. Carro

2006-01-01

366

Fabrication of a miniature CMOS-based optical biosensor  

Microsoft Academic Search

This work presents a novel, miniature optical biosensor by immobilizing horseradish peroxidase (HRP) or the HRP\\/glucose oxidase (GOx) coupled enzyme pair on a CMOS photosensing chip with a detection area of 0.5mm×0.5mm. A highly transparent TEOS\\/PDMS Ormosil is used to encapsulate and immobilize enzymes on the surface of the photosensor. Interestingly, HRP-catalyzed luminol luminescence can be detected in real time

Wei-Jen Ho; Jung-Sheng Chen; Ming-Dou Ker; Tung-Kung Wu; Chung-Yu Wu; Yuh-Shyong Yang; Yaw-Kuen Li; Chiun-Jye Yuan

2007-01-01

367

Fully differential CMOS CCII based on differential difference transconductor  

Microsoft Academic Search

This paper presents a new CMOS fully differential second-generation current conveyor (FDCCII). The proposed FDCCII is based\\u000a on a fully differential difference transconductor as an input stage and two class AB output stages. Besides the proposed FDCCII\\u000a circuit is operating at supply voltages of 1.5 V, it has a total standby current of 380 ?A. The application of the FDCCII\\u000a to realize

Soliman A. Mahmoud

2007-01-01

368

Linearization Technique for Source-Degenerated CMOS Differential Transconductors  

Microsoft Academic Search

A supplementary linearization technique for CMOS differential pairs with resistive source degeneration is proposed. The approach exploits an auxiliary (degenerated) differential pair to drive the bulk terminals of the main pair. Transistor-level simulations on a design using a 0.25-mum process and powered with 2.5 V and 1 mA, show that total harmonic distortion (THD) in the voltage-to-current conversion is decreased

Pietro Monsurro; Salvatore Pennisi; Giuseppe Scotti; Alessandro Trifiletti

2007-01-01

369

Digitally programmable CMOS transconductor for very high frequency  

Microsoft Academic Search

This paper describes a new approach for realizing digitally programmable VHF\\/UHF transconductors compatible with pure digital CMOS technologies. A programmable\\/tunable transconductor, based on a parallel connection of unit cascode cells, is used to implement a fully balanced current-mode Gm–C integrator to operate over the 30–200 MHz range with more than 70 dB of dynamic range for 1% of THD.

Aránzazu Otín; Santiago Celma; Concepción Aldea

2004-01-01

370

CMOS low-noise amplifier design optimization techniques  

Microsoft Academic Search

This paper reviews and analyzes four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-constrained simultaneous noise and input matching (PCSNIM) techniques. Very simple and insightful sets of noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques.

Trung-Kien Nguyen; Chung-Hwan Kim; Gook-Ju Ihm; Moon-Su Yang; Sang-Gug Lee

2004-01-01

371

A low noise, 2.0 GHz CMOS VCO design  

Microsoft Academic Search

In this paper, a new delay cell of the voltage-controlled oscillator (VCO) is proposed. The circuit is designed and fabricated in TSMC 0.25?m Ip5m CMOS process with a 2.5 V supply voltage. It utilizes the skill that decreases the transient time to achieve the wider operating frequencies, lower phase noise and lower power supply noise. The structure of the VCO

Kuo-Hsing Cheng; Shu-Chang Kuo; Chia-Ming Tu

2003-01-01

372

An application specific PSD implemented using standard CMOS technology  

Microsoft Academic Search

A 2-axis optical position sensitive detector (PSD) suitable for a single chip application-specific implementation of CMOS position sensing systems is reported. The PSD is comprised of an area array of discrete p-n photodiodes and two arrays of MOS transistors. The test results show that besides providing the possibility to optimize position-sensing resolution for a particular application, the linearity of a

A. Makynen; J. Kostamovaara

1998-01-01

373

Testing oriented analysis of CMOS ICs with opens  

Microsoft Academic Search

In a typical approach to VLSI testing, open faults are modeled by the transistor-stuck-open fault model or are not explicitly covered at all. It is shown that functional faults caused by opens, i.e. by regions with missing material, cannot be modeled well by a transistor stuck-open. It is also shown that the majority of opens which occur in CMOS static

Wojciech Maly; Pranab K. Nag; Phil Nigh

1988-01-01

374

Analysis of Timing Jitter in CMOS Ring Oscillators  

Microsoft Academic Search

in this paper the effects of thermal noise in transistors on timing jitter in CMOS ring-oscillators composed of source-coupled differential resistively-loaded delay cells is investigated. The relationship between delay element design parameters and the inherent thermal noise-induced jitter of the generated waveform are analyzed. These results are compared with simulated results from a Monte-Carlo analysis with good agreement. The analysis

Todd C. Weigandt; Beomsup Kim; Paul R. Gray

1994-01-01

375

A novel CMOS hairpin resonator using slow-wave structure  

Microsoft Academic Search

A novel hairpin resonator incorporating a defective uniplanar compact photonic bandgap (D-UCPBG) slow-wave structure has been developed using monolithic silicon-based CMOS technology and the impact of the D-UCPBG slow wave feature on the hairpin resonator performance is presented. Two stepped impedance hairpin resonators of equal dimensions, one with a solid ground plane and another with a D-UCPBG structure, were implemented

Mohan K. Chirala; Cam Nguyen

2005-01-01

376

A low voltage CMOS multiplier for high frequency equalization  

Microsoft Academic Search

This paper describes the design of a low power 1.2V CMOS multiplier for 10 Gbit\\/s continuous time finite impulse response (FIR) filter. The multiplier is based on a low noise amplifier (LNA) architecture and has variable gain, which is directly controlled by a 5 bit digital word. This direct control removes the need for a digital to analog converter to

Justin P. Abbott; Calvin Plett; John W. M. Rogers

2005-01-01

377

Process control for 45 nm CMOS logic gate patterning  

NASA Astrophysics Data System (ADS)

This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer, intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay performance with immersion lithography is also presented.

Le Gratiet, Bertrand; Gouraud, Pascal; Aparicio, Enrique; Babaud, Laurene; Dabertrand, Karen; Touchet, Mathieu; Kremer, Stephanie; Chaton, Catherine; Foussadier, Franck; Sundermann, Frank; Massin, Jean; Chapon, Jean-Damien; Gatefait, Maxime; Minghetti, Blandine; de-Caunes, Jean; Boutin, Daniel

2008-03-01

378

A CMOS ADSL codec for central office applications  

Microsoft Academic Search

A CMOS central office codec that supports Full Rate and G.Lite ADSL applications is described. The transmit channel consists of application-dependent digital filters, a 14 bit, 8.832 MSample\\/s current steering DAC, a 1.104 MHz analog filter and a programmable attenuator. The receive channel contains -17.5 to 33.5 dB of programmable gain, a 138 kHz analog low-pass filter, a 14 bit,

Patrick P. Siniscalchi; Jeanne K. Pitz; Richard K. Hester; Stewart DeSoto; Minsheng Wang; S. Sridharan; R. Halbach; D. Richardson; W. Bright; M. Sarraj; J. Hellums; C. Betty; G. Westphal

2000-01-01

379

A high-performance 0.08 ?m CMOS  

Microsoft Academic Search

We demonstrate a 0.08 ?m CMOS suitable for high-performance (V dd=1.8 V) and low-power applications (Vdd<1.5 V) with the best current drive at a given off-current reported in the literature to date. Excellent short-channel effects were obtained for L eff down to 0.06 ?m in the NFET and 0.08 ?m in the PFET. Aggressive lateral and vertical dopant engineering allow

L. Su; S. Subbanna; E. Crabbe; P. Agnello; E. Nowak; R. Schulz; S. Rauch; H. Ng; T. Newman; A. Ray; M. Hargrove; A. Acovic; J. Snare; S. Crowder; B. Chen; J. Sun; B. Davari

1996-01-01

380

A fully-integrated CMOS RFIC for Bluetooth applications  

Microsoft Academic Search

A 4.5×4 mm2 single-chip Bluetooth RF transceiver in a 0.35 ?m standard CMOS technology with minimal external components operates from a 3 V supply. The low-IF receiver achieves -77 dBm sensitivity for 0.1% BER and -17 dBm llP3. The direct up-conversion transmitter has 0 dBm nominal output power

Aruna Ajjikuttira; Chester Leung; Ee-Sze Khoo; Mark Choke; Rajinder Singh; Tian-Hwee Teo; Ban-Chuan Gheong; Jin-Hui See; Hwa-Seng Yap; Poh-Boon Leong; Choon-Tiong Law; M. Itoh; A. Yoshida; Y. Yoshida; A. Tamura; H. Nakamura

2001-01-01

381

Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique  

PubMed Central

This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature. PMID:22399944

Liu, Mao-Chen; Dai, Ching-Liang; Chan, Chih-Hua; Wu, Chyan-Chyi

2009-01-01

382

Organic thin-film transistors for flexible CMOS integration  

NASA Astrophysics Data System (ADS)

In this work a fully photolithographically defined complementary metal oxide semiconductor (CMOS) device is fabricated. Particular focus was on the use of solution based materials for device integration. P-type and n-type materials were evaluated for use in an organic thin film transistor (OTFT) device. The reliability and organic thin-film transistor performance of solution based dielectric polymeric dielectric materials are presented. Fabrication and characterization of integrated hybrid complementary metal oxide semiconductor devices (CMOS) using 6, 13-bis (triisopropylsilylethynyl) pentacene (TIPS-PC) and cadmium sulfide (CdS) as the active layers deposited using solution based processes are demonstrated. The hybrid CMOS technology demonstrated is compatible with large-area and mechanically flexible substrates given the low temperature processing (<100°C) and scalable design. Devices evaluated are diodes, n- and p-type thin film transistors (TFTs), inverters, NAND and NOR gates. The inverters exhibited a DC gain of ?52 V/V with full rail-to-rail switching. The NAND logic gates switch rail-to-rail with a transition point of V DD/2.

Perez, Michael Ramon

383

Aluminum nitride on titanium for CMOS compatible piezoelectric transducers  

PubMed Central

Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d33f, d31 and d33 of up to 2.9, ?1.9 and 6.5 pm V?1, respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals. PMID:20333316

Doll, Joseph C; Petzold, Bryan C; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L

2010-01-01

384

An integrated CMOS detection system for optical short-pulse  

NASA Astrophysics Data System (ADS)

We present design of a front-end readout system consisting of charge sensitive amplifier (CSA) and pulse shaper for detection of stochastic and ultra-small semiconductor scintillator signal. The semiconductor scintillator is double sided silicon detector (DSSD) or avalanche photo detector (APD) for high resolution and peak signal reliability of ?-ray or X-ray spectroscopy. Such system commonly uses low noise multichannel CSA. Each CSA in multichannel includes continuous reset system based on tens of M? and charge-integrating capacitor in feedback loop. The high value feedback resistor requires large area and huge power consumption for integrated circuits. In this paper, we analyze these problems and propose a CMOS short pulse detection system with a novel CSA. The novel CSA is composed of continuous reset system with combination of diode connected PMOS and 100 fF. This structure has linearity with increased input charge quantity from tens of femto-coulomb to pico-coulomb. Also, the front-end readout system includes both slow and fast shapers for detecting CSA output and preventing pile-up distortion. Shaping times of fast and slow shapers are 150 ns and 1.4 ?s, respectively. Simulation results of the CMOS detection system for optical short-pulse implemented in 0.18 ?m CMOS technology are presented.

Kim, Chang-Gun; Hong, Nam-Pyo; Choi, Young-Wan

2014-03-01

385

Polycrystalline Mercuric Iodide Films on CMOS Readout Arrays  

PubMed Central

We have created high-resolution x-ray imaging devices using polycrystalline mercuric iodide (HgI2) films grown directly onto CMOS readout chips using a thermal vapor transport process. Images from prototype 400×400 pixel HgI2-coated CMOS readout chips are presented, where the pixel grid is 30 ?m × 30 ?m. The devices exhibited sensitivity of 6.2 ?C/Rcm2 with corresponding dark current of ?2.7 nA/cm2, and a 80 ?m FWHM planar image response to a 50 ?m slit aperture. X-ray CT images demonstrate a point spread function sufficient to obtain a 50 ?m spatial resolution in reconstructed CT images at a substantially reduced dose compared to phosphor-coated readouts. The use of CMOS technology allows for small pixels (30 ?m), fast readout speeds (8 fps for a 3200×3200 pixel array), and future design flexibility due to the use of well-developed fabrication processes. PMID:20161098

Hartsough, Neal E.; Iwanczyk, Jan S.; Nygard, Einar; Malakhov, Nail; Barber, William C.; Gandhi, Thulasidharan

2009-01-01

386

NASA's commercial space program  

NASA Technical Reports Server (NTRS)

This paper will review the goals, status and progress of NASA's commercial space development program administered by the Office of Commercial Programs (OCP). The technologies and flight programs underway by NASA's Centers for Commercial Development (CCDS), NASA's field centers, and the NASA/Industry Joint Endeavor Programs will be summarized. A summary of completed and upcoming commercial payload activities on Shuttle, suborbital rockets, and orbital ELV's will be provided. The new commercial infrastructure and transportation initiatives will be discussed including the Wake Shield Facility, Consort and Joust suborbital rocket programs, the COMET orbital and recovery program, and the Commercial Middeck Accommodation Module Program with Spacehab Inc. Finally, the Commercial Space Station Freedom Program planned by OCP will be reviewed.

Ott, Richard H.

1992-01-01

387

Shallow Trench Isolation for the 45-nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance  

Microsoft Academic Search

In the present work, a high aspect ratio process (HARP) using a new O3\\/TEOS based sub atmospheric chemical vapor deposition process was implemented as STI gapfill in sub-65-nm CMOS. Good gapfill performance up to aspect ratios greater than 10:1 was demonstrated. Since the HARP process does not attack the STI liner as compared to HDP, a variety of different STI

Armin T. Tilke; Chris Stapelmann; Manfred Eller; Karl-Heinz Bach; Roland Hampp; Richard Lindsay; Richard Conti; William Wille; Rakesh Jaiswal; Maria Galiano; Alok Jain

2007-01-01

388

Top-down fabrication of fully CMOS-compatible silicon nanowire arrays and their integration into CMOS Inverters on plastic.  

PubMed

A route to the top-down fabrication of highly ordered and aligned silicon nanowire (SiNW) arrays with degenerately doped source/drain regions from a bulk Si wafer is presented. In this approach, freestanding n- and p-SiNWs with an inverted triangular cross section are obtained using conventional photolithography, crystal orientation dependent wet etching, size reduction oxidation, and ion implantation doping. Based on these n- and p-SiNWs transferred onto a plastic substrate, simple SiNW-based complementary metal-oxide-semiconductor (CMOS) inverters are constructed for the possible applications of these SiNW arrays in integrated circuits on plastic. The static voltage transfer characteristic of the SiNW-based CMOS inverter exhibits a voltage gain of ?9 V/V and a transition of 0.32 V at an operating voltage of 1.5 V with a full output voltage swing between 0 V and V(DD), and its mechnical bendability indicates good fatigue properties for potential applications of flexible electronics. This novel top-down approach is fully compatible with the current state-of-the-art Si-based CMOS technologies and, therefore, offers greater flexibility in device design for both high-performance and low-power functionality. PMID:21355599

Lee, Myeongwon; Jeon, Youngin; Moon, Taeho; Kim, Sangsig

2011-04-26

389

CMOS compatible thin-film ALD tungsten nanoelectromechanical devices  

NASA Astrophysics Data System (ADS)

This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different WALD fabrication technologies two generations of 2-terminal WALD NEMS switches have been developed. These devices have functional gap heights of 30-50 nm, and actuation voltages typically ranging from 3--5 Volts. Via the extension of a two terminal WALD technology novel 3-terminal WALD NEMS devices were developed. These devices have actuation voltages ranging from 1.5--3 Volts, reliabilities in excess of 2 million cycles, and have been designed to be the fundamental building blocks for WALD NEMS complementary inverters. Through the development of these devices several advancements in the modeling and design of thin-film NEMS devices were achieved. A new model was developed to better characterize pre-actuation currents commonly measured for NEMS switches with nano-scale gate-to-source gap heights. The developed model is an extension of the standard field-emission model and considers the electromechanical response, and electric field effects specific to thin-film NEMS switches. Finally, a multi-physics FEM/FD based model was developed to simulate the dynamic behavior of 2 or 3-terminal electrostatically actuated devices whose electrostatic domains have an aspect ratio on the order of 10-3. The model uses a faux-Lagrangian finite difference method to solve Laplaces equation in a quasi-statatically deforming domain. This model allows for the numerical characterization and design of thin-film NEMS devices not feasible using typical non-specialized BEM/FEM based software. Using this model several novel and feasible designs for fixed-fixed 3-terminal WALD NEMS switches capable for the construction of complementary inverters were discovered.

Davidson, Bradley Darren

390

Investigation of the Radio Frequency Characteristics of CMOS Electrostatic Discharge Protection Devices  

E-print Network

of CMOS and many other integrated circuit technologies is determined mainly by the electrical properties-like characteristics to shunt potentially harmful static charge away from thin gate-oxide insulators. These nonlinear, and a generalized approach to predicting radio-frequency effects in CMOS with electrostatic protection is introduced

Anlage, Steven

391

A transregional CMOS SRAM with single, logic VDD and dynamic power rails  

Microsoft Academic Search

New circuit techniques are reported that enable a single VDD SRAM to operate at logic compatible voltages with a cell read current and cell static noise margin (SNM) typically seen with higher\\/dual VDD SRAMs. Implemented in a 65nm CMOS SOI process with no alterations to the CMOS process or to a conventional, single VT SRAM cell, the voltage across power

A. J. Bhavnagarwala; S. V. Kosonocky; S. P. Kowalczyk; R. V. Joshi; Y. H. Chan; U. Srinivasan; J. K. Wadhwa

2004-01-01

392

CMOS contact imager for monitoring cultured cells Honghao Ji, Pamela A. Abshire  

E-print Network

CMOS contact imager for monitoring cultured cells Honghao Ji, Pamela A. Abshire Department image sensor, called a contact imager, for imaging of a biological specimen directly coupled to the chip on the bench as a normal CMOS image sensor, and then as a contact imager with microbeads (16 µm) placed

Maryland at College Park, University of

393

The analysis of dark signals in the CMOS APS imagers from the characterization of test structures  

Microsoft Academic Search

The characteristics of dark signals have been investigated in the CMOS active pixel sensor (APS) with test structures fabricated using the deep-submicron CMOS technology. It is found that the periphery of the photodiode (PD) is the dominant source of dark currents in our test structure, and this factor is very sensitive to the distance between the sidewall of the shallow

Hyuck In Kwon; In Man Kang; Byung-Gook Park; Jong Duk Lee; Sang Sik Park

2004-01-01

394

Active Area Shape Influence on the Dark Current of CMOS Imagers.  

E-print Network

Active Area Shape Influence on the Dark Current of CMOS Imagers. Igor Shcherback, Alexander Belenky Abstract This work presents an empirical dark current model for CMOS Active Pixel Sensors (APS). The model technology process. This quantitative model determines the pixel dark current dependence on two contributing

395

Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits  

E-print Network

1 Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits Farzan Fallah in the leakage currents in CMOS circuits. This part also distinguishes between the standby and active components of the leakage current. The second part of the article describes a number of circuit optimization techniques

Pedram, Massoud

396

Simultaneous Scheduling and Binding for Low Gate Leakage Nano-CMOS Datapath Circuit Behavioral Synthesis  

E-print Network

-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis power dissipation of a CMOS circuit [2], [3]. Each of the contributing leakage currents has several channel nanometer CMOS transistor, several forms of leakage current exist, such as reverse biased diode

Mohanty, Saraju P.

397

Leakage Current Reduction in CMOS VLSI Circuits by Input Vector Afshin Abdollahi  

E-print Network

1 Leakage Current Reduction in CMOS VLSI Circuits by Input Vector Control Afshin Abdollahi mechanisms for reducing the leakage current of a CMOS circuit. In both cases, it is assumed that the system so as to minimize the total leakage current in the circuit. This minimization is possible because

Pedram, Massoud

398

The effects of deuterium annealing on the reduction of dark currents in the CMOS APS  

Microsoft Academic Search

The effects of low-temperature deuterium annealing on the reduction of dark currents in the CMOS active pixel sensor (APS) have been investigated. Experimental results reveal that deuterium annealing is more effective in reducing dark currents of the CMOS APS than conventional forming gas annealing, because it shows the enhanced passivation efficiency of the interface traps located in the sidewall of

Hyuck In Kwon; O. Jun Kwon; Hyungcheol Shin; Byung-Gook Park; Sang Sik Park; Jong Duk Lee

2004-01-01

399

Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study  

E-print Network

Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study Oleg Garitselov1 , Saraju P. Mohanty2 , Elias Kougianos3 , and Priyadarsan Patra4 NanoSystem Design Laboratory (NSDL, http Abstract--Fast design space exploration of complex nano- CMOS mixed-signal circuits is an important problem

Mohanty, Saraju P.

400

Design of Static and Dynamic Translinear Circuits based on CMOS CCII Translinear Loops  

E-print Network

Design of Static and Dynamic Translinear Circuits based on CMOS CCII Translinear Loops Debashis.a.serdijn@ewi.tudelft.nl ABSTRACT A novel technique to implement static and dynamic translinear circuits based on CMOS CCII is a generalization of the static TL (STL) principle formulated by Gilbert in 1975 [2]. Both static and dynamic TL

Serdijn, Wouter A.

401

Status and Direction of Communication Technologies - SiGe BiCMOS and RFCMOS  

Microsoft Academic Search

We present the status and direction of silicon semiconductor technologies targeted for applications such as wireless, networking, instrumentation, and storage markets. Various technological aspects for multiple branches of RF foundry technologies that are based on the standard foundry compatible CMOS node are discussed - SiGe BiCMOS HP (\\

ALVIN J. JOSEPH; DAVID L. HARAME; BASANTH JAGANNATHAN; DOUG COOLBAUGH; DAVID AHLGREN; JOHN MAGERLEIN; LOUIS LANZEROTTI; NATALIE FEILCHENFELD; J. Dunn; E. Nowak

2005-01-01

402

QUBiC4: a silicon RF-BiCMOS technology for wireless communication ICs  

Microsoft Academic Search

QUBiC4 is a silicon RF-BiCMOS technology with NPN ft\\/f max up to 40\\/100 GHz, 0.25 ?m CMOS, high quality passives, and five metal layers for wireless applications. LNA noise figure of 0.99 dB at 2 GHz has been achieved

D. Szmyd; R. Brock; N. Bell; S. Harker; G. Patrizi; J. Fraser; R. Dondero

2001-01-01

403

Design and characterization of a signal insulation coreless transformer integrated in a CMOS gate driver chip  

E-print Network

Design and characterization of a signal insulation coreless transformer integrated in a CMOS gate transformer integrated in a CMOS silicon die together with the gate driver and other required functions frequency through the coreless transformer. The chosen design methodology will be explained and experimental

Paris-Sud XI, Université de

404

Modeling the current behavior of the digital BiCMOS gate  

E-print Network

and P. Ashburn, "An accurate analytical BiCMOS delay dxpression and its application to optimizing high-speed BiCMOS circuits, " IEEE J. Solid-State Circuits, vol. 27, no. 2, pp. 191-201, Feb. 1992. [12] Meta-Software, Inc. , HSPICE User's Manual...

Tang, Zhilong

1995-01-01

405

Comparison of Total Dose Effects on Micropower Op-Amps: Bipolar and CMOS  

NASA Technical Reports Server (NTRS)

This paper compares low-paper op-amps, OPA241 (bipolar) and OPA336 (CMOS), from Burr-Brown, MAX473 (bipolar) and MAX409 (CMOS), characterizing their total dose response with a single 2.7V power supply voltage.

Lee, C.; Johnston, A.

1998-01-01

406

Technique to Design MLP's Networks in CMOS Technology with Adjustment of the Back-Propagation Algorithm  

Microsoft Academic Search

Conception of structures in CMOS technology that de- mand low power and low silicon area consumption have been widely investigated in the implementation of artifi- cial neural networks in VLSI integrated circuits for signal processing purposes (2), (6). Feedforward MLP networks' building blocks require CMOS multipliers for implement- ing the synapses and the activation function circuits. A larger scale of

Fabio De Albuquerque Pereira; Jés Jesus Fiais Cerqueira

2002-01-01

407

Impact of CMOS technology scaling on the atmospheric neutron soft error rate  

Microsoft Academic Search

We investigated scaling of the atmospheric neutron soft error rate (SER) which affects reliability of CMOS circuits at ground level and airplane flight altitudes. We considered CMOS circuits manufactured in a bulk process with a lightly-doped p-type wafer. One method, based on the empirical model, predicts a linear decrease of SER per bit with decreasing feature size LG. A different

Peter Hazucha; Christer Svensson

2000-01-01

408

Smart CMOS Charge Transfer Readout Circuit for Time Delay and Integration Arrays  

Microsoft Academic Search

This paper presents a novel CMOS charge transfer readout circuit for X-ray time delay and integration (TDI) arrays with a depth of 64. The proposed circuit uses a charge transfer readout similar to CCD; thus, the summing of the signal charges can be implemented easily compared with other typical CMOS readout circuits for TDI arrays. The weakness of TDI arrays

Chul Bum Kim; Byung-Hyuk Kim; Yong Soo Lee; Han Jung; Hee Chul Lee

2006-01-01

409

CMOS On-Chip Optoelectronic Neural Interface Device with Integrated Light Source for Optogenetics  

Microsoft Academic Search

A novel optoelectronic neural interface device is proposed for target applications in optogenetics for neural science. The device consists of a light emitting diode (LED) array implemented on a CMOS image sensor for on-chip local light stimulation. In this study, we designed a suitable CMOS image sensor equipped with on-chip electrodes to drive the LEDs, and developed a device structure

Y Sawadsaringkarn; H Kimura; Y Maezawa; A Nakajima; T Kobayashi; K Sasagawa; T Noda; T Tokuda; J Ohta

2012-01-01

410

Fast range imaging by CMOS sensor array through multiple double short time integration (MDSI)  

Microsoft Academic Search

The presented novel approach for direct range image acquisition is based on a CMOS image sensor with extremely short integration time and a defined flash illumination by fast infrared laser diodes. Determining the light propagation time by the MDSI method on a chip, a single CMOS sensor chip measures simultaneously distances to a net of numerous target points in a

Peter Mengel; Giinter Doemens; L. Listl

2001-01-01

411

Determining the thermal expansion coefficient of thin films for a CMOS MEMS process using test cantilevers  

NASA Astrophysics Data System (ADS)

Many standard CMOS processes, provided by existing foundries, are available. These standard CMOS processes, with stacking of various metal and dielectric layers, have been extensively applied in integrated circuits as well as micro-electromechanical systems (MEMS). It is of importance to determine the material properties of the metal and dielectric films to predict the performance and reliability of micro devices. This study employs an existing approach to determine the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. Test cantilevers with different stacking of metal and dielectric layers for standard CMOS processes have been designed and implemented. The CTEs of standard CMOS films can be determined from measurements of the out-of-plane thermal deformations of the test cantilevers. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacture Company 0.35??m 2P4M CMOS process are characterized. Eight test cantilevers with different stacking of CMOS layers and an auxiliary Si cantilever on a SOI wafer are fabricated. The equivalent elastic moduli and CTEs of the CMOS thin films including the metal and dielectric layers are determined, respectively, from the resonant frequency and static thermal deformation of the test cantilevers. Moreover, thermal deformations of cantilevers with stacked layers different to those of the test beams have been employed to verify the measured CTEs and elastic moduli.

Cheng, Chao-Lin; Tsai, Ming-Han; Fang, Weileun

2015-02-01

412

A CMOS image sensor with a simple FPN-reduction technology and a hole accumulated diode  

Microsoft Academic Search

CMOS image sensors are generally characterized by their low power consumption, single power supply and capability for on-chip system integration in contrast with CCD image sensors. Even though CMOS image sensors have these advantages, they are not yet widely used in image capture applications because of their insufficient image quality due to the difficulty in FPN cancellation. This FPN-reduction technology

Kazuya Yonemoto; Hirofumi Sumi; Ryoji Suzuki; Takahisa Ueno

2000-01-01

413

An Ultra Low Power CMOS pA/V Transconductor and its Application to Wavelet Filters  

E-print Network

An Ultra Low Power CMOS pA/V Transconductor and its Application to Wavelet Filters Peterson R topologies of ultra low-power CMOS triode transconductor are proposed. Its input transistors are kept topology of transconductor equals 51nW and 114nW, respectively. Categories and Subject Descriptors B.7

Serdijn, Wouter A.

414

An ultra low power CMOS pA/V transconductor and its application to wavelet filters  

E-print Network

An ultra low power CMOS pA/V transconductor and its application to wavelet filters Peterson R ultra low-power CMOS triode transconductor topologies denoted VLPT-gm and Delta-gm are proposed. In both. This allows achieving a small-signal transconductance gm down to hundreds of pA/V, making such transconductors

Serdijn, Wouter A.

415

CMOS transconductor VCO with adjust~bia operating and centre frequencies  

E-print Network

',--.. CMOS transconductor VCO with adjust~bia operating and centre frequencies B. Keeth, R-to-frequency oscillator. Vcoin YQQ 2 Fig. 1 Block diagram of CMOS transconductor VCO Transconductor approach: The block the current I.... Two transconductor outputs alternately charge capacitors, CI and C2. Positive feedback

Baker, R. Jacob

416

Hybrid CMOS-STTRAM Non-Volatile FPGA: Design Challenges and Optimization Approaches  

E-print Network

Hybrid CMOS-STTRAM Non-Volatile FPGA: Design Challenges and Optimization Approaches Somnath Paul) as a promising next generation universal memory. However, the prospect of developing a non-volatile FPGA propose a novel CMOS-STTRAM hybrid FPGA framework; identify the key design challenges; and propose

Bhunia, Swarup

417

Fast Optimization of Nano-CMOS Voltage-Controlled Oscillator using Polynomial Regression and Genetic Algorithm  

E-print Network

been developed for power (including leakage) and frequency of the VCO to speedup the design-CMOS), Voltage-Controlled Oscillator (VCO). 1. Introduction Digital design exploration and optimization is highly Fast optimization of CMOS circuits is needed to reduce design cycle time and chip cost and to enhance

Mohanty, Saraju P.

418

Fully integrated low phase noise VCO design in SiGe BiCMOS technology  

Microsoft Academic Search

Fully integrated voltage controlled oscillator (VCO) designs with low phase noise targeted for cellular communication in SiGe (silicon germanium) BiCMOS technology are discussed. The advantages of using IBM SiGe BiCMOS technology for fully integrated VCO designs are addressed in detail. Three fully integrated VCOs for wireless handset applications are reported with design approaches and testing results

Xudong Wang; Dawn Wang; Kurt Schelkle; Peter Bacon

2001-01-01

419

Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs  

Microsoft Academic Search

This paper examines the reliability of gate oxide shorts in CMOS ICs. Gate oxide shorts cause increased quiescent IDD but may not initially affect functionality. These shorts can subsequently change due to thermal and electric field stress during operation and cause functional failure. Therefore, gate oxide defects can significantly degrade CMOS IC reliability. 14 refs.

Jerry M. Soden; Charles F. Hawkins

1986-01-01

420

Design considerations of recent advanced low-voltage low-temperature-coefficient CMOS bandgap voltage reference  

Microsoft Academic Search

The design considerations of CMOS bandgap voltage references, focusing on low-voltage and low-temperature-coefficient methodologies, are discussed in this paper. Some recently reported circuits of bandgap voltage references are included and analyzed. Moreover, a CMOS voltage reference is also addressed.

Philip K. T. Mok; Ka Nang Leung

2004-01-01

421

Analysis of Power-Clocked CMOS with Application to the Design of Energy-Recovery Circuits*  

E-print Network

Analysis of Power-Clocked CMOS with Application to the Design of Energy-Recovery Circuits* Massoud simulations demonstrate the correct operation and energy-saving advantage of the proposed circuits. I. INTRODUCTION It is well known that the power dissipation in CMOS circuits is related to the type of energy

Pedram, Massoud

422

CMOS-compatible Titanium Dioxide Deposition for Athermalization of Silicon Photonic Waveguides  

E-print Network

CMOS-compatible Titanium Dioxide Deposition for Athermalization of Silicon Photonic Waveguides@ucdavis.edu , sbyoo@ucdavis.edu Abstract: We discuss titanium dioxide material development for CMOS compatible fabrication and integration of athermal silicon photonic components. Titanium dioxide overclad ring modulators

Yoo, S. J. Ben

423

Scaled CMOS Technology Reliability Users Guide  

NASA Technical Reports Server (NTRS)

The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. A methodology on how to accomplish this and techniques for deriving the expected product-level reliability on commercial memory products are provided.Competing mechanism theory and the multiple failure mechanism model are applied to the experimental results of scaled SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope (beta)=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is presented revealing a power relationship. General models describing the soft error rates across scaled product generations are presented. The analysis methodology may be applied to other scaled microelectronic products and their key parameters.

White, Mark

2010-01-01

424

Lighting in Commercial Buildings  

EIA Publications

Lighting is a major consumer of electricity in commercial buildings and a target for energy savings through use of energy-efficient light sources along with other advanced lighting technologies. The Commercial Buildings Energy Consumption Survey (CBECS) collects information on types of lighting equipment, the amount of floorspace that is lit, and the percentage of floorspace lit by each type. In addition, CBECS data are used to model end-use consumption, including energy consumed for lighting in commercial buildings.

2009-01-01

425

Lunar Commercialization Workshop  

NASA Technical Reports Server (NTRS)

This slide presentation describes the goals and rules of the workshop on Lunar Commercialization. The goal of the workshop is to explore the viability of using public-private partnerships to open the new space frontier. The bulk of the workshop was a team competition to create a innovative business plan for the commercialization of the moon. The public private partnership concept is reviewed, and the open architecture as an infrastructure for potential external cooperation. Some possible lunar commercialization elements are reviewed.

Martin, Gary L.

2008-01-01

426

Commercializing the Internet  

Microsoft Academic Search

The “commercialization of the Internet” is shorthand for three nearly simultaneous events. They are the removal of restrictions by the National Science Foundation over the use of the Internet for commercial purposes, the founding of Netscape, and the rapid entry of tens of thousands-perhaps hundreds of thousands-of firms into commercial ventures using technologies that employ the suite of TCP\\/IP standards.

S. Greenstein

1998-01-01

427

CMOS digital intra-oral sensor for x-ray radiography  

NASA Astrophysics Data System (ADS)

In this paper, we present a CMOS digital intra-oral sensor for x-ray radiography. The sensor system consists of a custom CMOS imager, custom scintillator/fiber optics plate, camera timing and digital control electronics, and direct USB communication. The CMOS imager contains 1700 x 1346 pixels. The pixel size is 19.5um x 19.5um. The imager was fabricated with a 0.18um CMOS imaging process. The sensor and CMOS imager design features chamfered corners for patient comfort. All camera functions were integrated within the sensor housing and a standard USB cable was used to directly connect the intra-oral sensor to the host computer. The sensor demonstrated wide dynamic range from 5uGy to 1300uGy and high image quality with a SNR of greater than 160 at 400uGy dose. The sensor has a spatial resolution more than 20 lp/mm.

Liu, Xinqiao; Byczko, Andrew; Choi, Marcus; Chung, Lap; Do, Hung; Fowler, Boyd; Ispasoiu, Radu; Joshi, Kumar; Miller, Todd; Nagy, Alex; Reaves, David; Rodricks, Brian; Teeter, Doug; Wang, George; Xiao, Feng

2011-03-01

428

The total dose effects on the 1/f noise of deep submicron CMOS transistors  

NASA Astrophysics Data System (ADS)

Using 0.18 ?m CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI (shallow trench isolation) SiO2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion.

Rongbin, Hu; Yuxin, Wang; Wu, Lu

2014-02-01

429

Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor  

NASA Astrophysics Data System (ADS)

The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 ?m CMOS technology. The flux of neutron beams was about 1.33 × 108 n/cm2s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 1011, 5 × 1011, and 1 × 1012 n/cm2, respectively. The mean dark signal (KD), dark signal spike, dark signal non-uniformity (DSNU), noise (VN), saturation output signal voltage (VS), and dynamic range (DR) versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike.

Wang, Zujun; Huang, Shaoyan; Liu, Minbo; Xiao, Zhigang; He, Baoping; Yao, Zhibin; Sheng, Jiangkun

2014-07-01

430

Closed-loop adaptive optics using a CMOS image quality metric sensor  

NASA Astrophysics Data System (ADS)

When compared to a Shack-Hartmann sensor, a CMOS image sharpness sensor has the advantage of reduced complexity in a closed-loop adaptive optics system. It also has the potential to be implemented as a smart sensor using VLSI technology. In this paper, we present a novel adaptive optics testbed that uses a CMOS sharpness imager built in the New Mexico State University (NMSU) Electro-Optics Research Laboratory (EORL). The adaptive optics testbed, which includes a CMOS image quality metric sensor and a 37-channel deformable mirror, has the capability to rapidly compensate higher-order phase aberrations. An experimental performance comparison of the pinhole image sharpness feedback method and the CMOS imager is presented. The experimental data shows that the CMOS sharpness imager works well in a closed-loop adaptive optics system. Its overall performance is better than that of the pinhole method, and it has a fast response time.

Ting, Chueh; Rayankula, Aditya; Giles, Michael K.; Furth, Paul M.

2006-08-01

431

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg  

NASA Technical Reports Server (NTRS)

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

2014-01-01

432

Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems  

PubMed Central

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200?mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

Kazior, Thomas E.

2014-01-01

433

SOI CMOS Imager with Suppression of Cross-Talk  

NASA Technical Reports Server (NTRS)

A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

2009-01-01

434

NV-CMOS HD camera for day/night imaging  

NASA Astrophysics Data System (ADS)

SRI International (SRI) has developed a new multi-purpose day/night video camera with low-light imaging performance comparable to an image intensifier, while offering the size, weight, ruggedness, and cost advantages enabled by the use of SRI's NV-CMOS HD digital image sensor chip. The digital video output is ideal for image enhancement, sharing with others through networking, video capture for data analysis, or fusion with thermal cameras. The camera provides Camera Link output with HD/WUXGA resolution of 1920 x 1200 pixels operating at 60 Hz. Windowing to smaller sizes enables operation at higher frame rates. High sensitivity is achieved through use of backside illumination, providing high Quantum Efficiency (QE) across the visible and near infrared (NIR) bands (peak QE <90%), as well as projected low noise (<2h+) readout. Power consumption is minimized in the camera, which operates from a single 5V supply. The NVCMOS HD camera provides a substantial reduction in size, weight, and power (SWaP) , ideal for SWaP-constrained day/night imaging platforms such as UAVs, ground vehicles, fixed mount surveillance, and may be reconfigured for mobile soldier operations such as night vision goggles and weapon sights. In addition the camera with the NV-CMOS HD imager is suitable for high performance digital cinematography/broadcast systems, biofluorescence/microscopy imaging, day/night security and surveillance, and other high-end applications which require HD video imaging with high sensitivity and wide dynamic range. The camera comes with an array of lens mounts including C-mount and F-mount. The latest test data from the NV-CMOS HD camera will be presented.

Vogelsong, T.; Tower, J.; Sudol, Thomas; Senko, T.; Chodelka, D.

2014-06-01

435

Autonomous pedestrian localization technique using CMOS camera sensors  

NASA Astrophysics Data System (ADS)

We present a pedestrian localization technique that does not need infrastructure. The proposed angle-only measurement method needs specially manufactured shoes. Each shoe has two CMOS cameras and two markers such as LEDs attached on the inward side. The line of sight (LOS) angles towards the two markers on the forward shoe are measured using the two cameras on the other rear shoe. Our simulation results shows that a pedestrian walking down in a shopping mall wearing this device can be accurately guided to the front of a destination store located 100m away, if the floor plan of the mall is available.

Chun, Chanwoo

2014-09-01

436

Effectiveness of CMOS charge reflection barriers in space radiation environments  

NASA Astrophysics Data System (ADS)

Single-event upsets in microelectronic circuits follow the collection of more than some critical amount of charge at certain reverse-biased junctions. Reducing charge collection at the junctions lowers the upset rate without requiring performance tradeoff. Three mechanisms for reducing the fraction of charge collected at a junction can be incorporated in the use of CMOS-type wells. For illustration, the CHMOS-III-D process used in Intel's P51C256 is shown to lower the error rate to be expected in deep space by an order of magnitude from that calculated for an equivalent dynamic RAM of standard design.

McNulty, P. J.; Lynch, J. E.; Abdel-Kader, W. G.

1987-12-01

437

Measurements with a CMOS pixel sensor in magnetic fields  

NASA Astrophysics Data System (ADS)

CMOS technique, which is the standard process used by most of the semiconductor factories worldwide, allows the production of both cheap and highly integrated sensors. The prototypes MIMOSA -I and MIMOSA-II were designed by the IReS-LEPSI collaboration in order to investigate the potential of this new technique for charged particle tracking (Design and Testing of Monolithic Active Pixel Sensors for Charged Particle Tracking, LEPSI, IN2P3, Strasbourg, France). For this purpose it is necessary to study the effects of magnetic fields as they appear in high-energy physics on these sensors. MIMOSA: Minimum Ionizing particle MOS Active pixel sensor.

de Boer, W.; Bartsch, V.; Bol, J.; Dierlamm, A.; Grigoriev, E.; Hauler, F.; Herz, O.; Jungermann, L.; Koppenhöfer, M.; Sopczak, A.; Schneider, Th.

2002-07-01

438

Widefield heterodyne interferometry using a custom CMOS modulated light camera.  

PubMed

In this paper a method of taking widefield heterodyne interferograms using a prototype modulated light camera is described. This custom CMOS modulated light camera (MLC) uses analogue quadrature demodulation at each pixel to output the phase and amplitude of the modulated light as DC voltages. The heterodyne interference fringe patterns are generated using an acousto-optical frequency shifter (AOFS) in an arm of a Mach-Zehnder interferometer. Widefield images of fringe patterns acquired using the prototype MLC are presented. The phase can be measured to an accuracy of ±6.6°. The added value of this method to acquire widefield images are discussed along with the advantages. PMID:22109482

Patel, Rikesh; Achamfuo-Yeboah, Samuel; Light, Roger; Clark, Matt

2011-11-21

439

Performance of a CMOS Schmitt trigger at liquid nitrogen temperature  

NASA Astrophysics Data System (ADS)

The performance of a typical CMOS Schmitt trigger integrated circuit has been studied at liquid nitrogen temperature. It is shown that the Schmitt trigger parameters V+, V-, ?V+ and ?V- change at lower temperatures due to a change in the MOSFET's threshold voltage. It has been observed that the forward trigger voltage V+ shifts toward the right and the reverse trigger voltage V- shifts toward the left at liquid nitrogen temperature with respect to their corresponding room temperature values. This behaviour results in an increase in forward and reverse hysteresis ranges ?V+ and ?V- of the Schmitt trigger. Experimental results are found to be in good agreement with theory.

Srivastava, A.

440

Single ion channel recordings with CMOS-anchored lipid membranes.  

PubMed

We present single-ion-channel recordings performed with biomimetic lipid membranes which are directly attached to the surface of a complementary metal-oxide-semiconductor (CMOS) preamplifier chip. With this system we resolve single-channel currents from several types of bacterial ion channels, including fluctuations of a single alamethicin channel at a bandwidth of 1 MHz which represent the fastest single-ion-channel recordings reported to date. The platform is also used for high-resolution ?-hemolysin nanopore recordings. These results illustrate the high signal fidelity, fine temporal resolution, small geometry, and multiplexed integration which can be achieved by leveraging integrated semiconductor platforms for advanced ion channel interfaces. PMID:23634707

Rosenstein, Jacob K; Ramakrishnan, Siddharth; Roseman, Jared; Shepard, Kenneth L

2013-06-12

441

A quasi-passive CMOS pipeline D/A converter  

NASA Technical Reports Server (NTRS)

A novel pipeline digital-to-analog converter configuration, based on switched-capacitor techniques, is described. An n-bit D/A conversion can be implemented by cascading n + 1 unit cells. The device count of the circuit increases linearly, not exponentially, with the conversion accuracy. The new configuration can be pipelined. Hence, the conversion rate can be increased without requiring a higher clock rate. An experimental 10-bit DAC prototype has been fabricated using a 3-micron CMOS process. The results show that high-speed, high-accuracy, and low-power operation can be achieved without special process or postprocess trimming.

Wang, Fong-Jim; Temes, Gabor C.; Law, Simon

1989-01-01

442

Silicon nanowires integrated with CMOS circuits for biosensing application  

NASA Astrophysics Data System (ADS)

We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

Jayakumar, G.; Asadollahi, A.; Hellström, P.-E.; Garidis, K.; Östling, M.

2014-08-01

443

Contact CMOS imaging of gaseous oxygen sensor array  

Microsoft Academic Search

We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin

Daisy S. Daivasagaya; Lei Yao; Ka Yi Yung; Mohamad Hajj-Hassan; Maurice C. Cheung; Vamsy P. Chodavarapu; Frank V. Bright

2011-01-01

444

A novel CMOS-compatible high-voltage transistor structure  

NASA Astrophysics Data System (ADS)

A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS-bipolar concept, is described. This device, which can be implemented using a standard CMOS process, is capable of handling high current densities without latching. The IBT exhibits a fivefold increase in current density compared to the lateral DMOS. A simple technique by which the switching speeds of the IBT can be improved by almost an order of magnitude without significantly compromising its current carrying capability is also presented.

Parpia, Zahir; Salama, C. Andre T.; Mena, Jose G.

1986-12-01

445

120-MHz BiCMOS superscalar RISC processor  

NASA Astrophysics Data System (ADS)

A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm x 16.5 mm, and utilizes 3.3 V/0.5 micron BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design.

Tanaka, Shigeya; Hotta, Takashi; Murabayashi, Fumio; Yamada, Hiromichi; Yoshida, Shoji; Shimamura, Kotaro; Katsura, Koyo; Bandoh, Tadaaki; Ikeda, Koichi; Matsubara, Kenji

1994-04-01

446

Commercialism in Intercollegiate Athletics.  

ERIC Educational Resources Information Center

Outlines the history of intercollegiate athletics and the evolution of commercialization in college sports, particularly through television. Argues that few Division I programs could be self-sufficient; the issue is the degree to which sports are commercialized for revenue, and the challenge to balance schools' needs, private sector interests, and…

Delany, James E.

1997-01-01

447

Commercialization of space activities  

Microsoft Academic Search

Commercialization of space activities requires a legal framework for private investors and entrepreneurs in order to promote and develop this sector of industry into a fully-fledged commercial enterprise. Apart from the already existing international public legal framework of space law, rules should be created to provide a level playing field for all interested parties. These rules should point to transparency

Hanneke L. van Traa-Engelman

1996-01-01

448

Commercial photovoltaics measurements workshop  

Microsoft Academic Search

Various topics in the area of commercial photovoltaics measurements are discussed. The topics considered include: the status of measurements for commercial photovoltaics a manufacturer's perspective of measurement equipment needs for the photovoltaics industry the use of test structures in the production of CdS\\/CuâS photovoltaic devices the Semiconductor Equipment and Materials Institute specification for solar cell silicon the role of impurities

S. Hogan; H. A. Schafft

1982-01-01

449

Commercial fertilizers 1991  

SciTech Connect

This document contains consumption data for commercial fertilizers in the USA for 1991. Graphical information on the consumption by class is given for the nation. State by state data for consumption of several types of commercial fertilizers are presented. Only numerical data is included.

Hargett, N.L.; Berry, J.T.; Montgomery, M.H.

1991-12-01

450

Nanotechnology Commercialization in Oregon  

E-print Network

Nanotechnology Commercialization in Oregon February 27, 2012 Portland State University Physics Seminar Robert D. "Skip" Rung President and Executive Director #12;2 Nanotechnology Commercialization on "green" nanotechnology and gap fund portfolio company examples #12;3 Goals of the National Nanotechnology

Moeck, Peter

451

Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS).  

PubMed

The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 ?m pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems. PMID:24353389

Loughran, Brendan; Swetadri Vasan, S N; Singh, Vivek; Ionita, Ciprian N; Jain, Amit; Bednarek, Daniel R; Titus, Albert; Rudin, Stephen

2013-03-01

452

Large-area CMOS SPADs with very low dark counting rate  

NASA Astrophysics Data System (ADS)

We designed and characterized Silicon Single-Photon Avalanche Diodes (SPADs) fabricated in a high-voltage 0.35 ?m CMOS technology, achieving state-of-the-art low Dark Counting Rate (DCR), very large diameter, and extended Photon Detection Efficiency (PDE) in the Near Ultraviolet. So far, different groups fabricated CMOS SPADs in scaled technologies, but with many drawbacks in active area dimensions (just a few micrometers), excess bias (just few Volts), DCR (many hundreds of counts per second, cps, for small 10 ?m devices) and PDE (just few tens % in the visible range). The novel CMOS SPAD structures with 50 ?m, 100 ?m, 200 ?m and 500 ?m diameters can be operated at room temperature and show DCR of 100 cps, 2 kcps, 20 kcps and 100 kcps, respectively, even when operated at 6 V excess bias. Thanks to the excellent performances, these large CMOS SPADs are exploitable in monolithic SPAD-based arrays with on-chip CMOS electronics, e.g. for time-resolved spectrometers with no need of microlenses (thanks to high fillfactor). Instead the smaller CMOS SPADs, e.g. the 10 ?m devices with just 3 cps at room temperature and 6 V excess bias, are the viable candidates for dense 2D CMOS SPAD imagers and 3D Time-of-Flight ranging chips.

Bronzi, D.; Villa, F.; Bellisai, S.; Tisa, S.; Tosi, A.; Ripamonti, G.; Zappa, F.; Weyers, S.; Durini, D.; Brockherde, W.; Paschen, U.

2013-01-01

453

High-Q CMOS-integrated photonic crystal microcavity devices  

PubMed Central

Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10?s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300–9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31?A/W), 3?GHz bandwidth, and 30?nA dark current at a reverse bias of 30?V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems. PMID:24518161

Mehta, Karan K.; Orcutt, Jason S.; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J.

2014-01-01

454

CMOS: Efficient Clustered Data Monitoring in Sensor Networks  

PubMed Central

Tiny and smart sensors enable applications that access a network of hundreds or thousands of sensors. Thus, recently, many researchers have paid attention to wireless sensor networks (WSNs). The limitation of energy is critical since most sensors are battery-powered and it is very difficult to replace batteries in cases that sensor networks are utilized outdoors. Data transmission between sensor nodes needs more energy than computation in a sensor node. In order to reduce the energy consumption of sensors, we present an approximate data gathering technique, called CMOS, based on the Kalman filter. The goal of CMOS is to efficiently obtain the sensor readings within a certain error bound. In our approach, spatially close sensors are grouped as a cluster. Since a cluster header generates approximate readings of member nodes, a user query can be answered efficiently using the cluster headers. In addition, we suggest an energy efficient clustering method to distribute the energy consumption of cluster headers. Our simulation results with synthetic data demonstrate the efficiency and accuracy of our proposed technique. PMID:24459444

2013-01-01

455

CMOS: efficient clustered data monitoring in sensor networks.  

PubMed

Tiny and smart sensors enable applications that access a network of hundreds or thousands of sensors. Thus, recently, many researchers have paid attention to wireless sensor networks (WSNs). The limitation of energy is critical since most sensors are battery-powered and it is very difficult to replace batteries in cases that sensor networks are utilized outdoors. Data transmission between sensor nodes needs more energy than computation in a sensor node. In order to reduce the energy consumption of sensors, we present an approximate data gathering technique, called CMOS, based on the Kalman filter. The goal of CMOS is to efficiently obtain the sensor readings within a certain error bound. In our approach, spatially close sensors are grouped as a cluster. Since a cluster header generates approximate readings of member nodes, a user query can be answered efficiently using the cluster headers. In addition, we suggest an energy efficient clustering method to distribute the energy consumption of cluster headers. Our simulation results with synthetic data demonstrate the efficiency and accuracy of our proposed technique. PMID:24459444

Min, Jun-Ki

2013-01-01

456

Review of radiation damage studies on DNW CMOS MAPS  

NASA Astrophysics Data System (ADS)

Monolithic active pixel sensors fabricated in a bulk CMOS technology with no epitaxial layer and standard resistivity (10 ? cm) substrate, featuring a deep N-well as the collecting electrode (DNW MAPS), have been exposed to ?-rays, up to a final dose of 10 Mrad (SiO2), and to neutrons from a nuclear reactor, up to a total 1 MeV neutron equivalent fluence of about 3.7·1013 cm-2. The irradiation campaign was aimed at studying the effects of radiation on the most significant parameters of the front-end electronics and on the charge collection properties of the sensors. Device characterization has been carried out before and after irradiations. The DNW MAPS irradiated with 60Co ?-rays were also subjected to high temperature annealing (100 °C for 168 h). Measurements have been performed through a number of different techniques, including electrical characterization of the front-end electronics and of DNW diodes, laser stimulation of the sensors and tests with 55Fe and 90Sr radioactive sources. This paper reviews the measurement results, their relation with the damage mechanisms underlying performance degradation and provides a new comparison between DNW devices and MAPS fabricated in a CMOS process with high resistivity (1 k? cm) epitaxial layer.

Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.; Zucca, S.; Bettarini, S.; Rizzo, G.; Morsani, F.; Bosisio, L.; Rashevskaya, I.; Cindro, V.

2013-12-01

457

Single phase dynamic CMOS PLA using charge sharing technique  

NASA Technical Reports Server (NTRS)

A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

Dhong, Y. B.; Tsang, C. P.

1991-01-01

458

CMOS tunable-wavelength multi-color photogate sensor.  

PubMed

A CMOS tunable-wavelength multi-color photogate (CPG) sensor is presented. Sensing of a small set of well-separated wavelengths (e.g., > 50 nm apart) is achieved by tuning the spectral response of the device with a bias voltage. The CPG employs the polysilicon gate as an optical filter, which eliminates the need for an external color filter. A prototype has been fabricated in a standard 0.35 ?m digital CMOS technology and demonstrates intensity measurements of blue (450 nm), green (520 nm), and red (620 nm) illumination with peak signal-to-noise ratios (SNRs) of 34.7 dB , 29.2 dB, and 34.8 dB, respectively. The prototype is applied to fluorescence detection of green-emitting quantum dots (gQDs) and red-emitting quantum dots (rQDs). It spectrally differentiates among multiple emission bands, effectively implementing on-chip emission filtering. The prototype demonstrates single-color measurements of gQD and rQD concentrations to a detection limit of 24 nM, and multi-color measurements of solutions containing both colors of QDs to a detection limit of 90 nM and 120 nM of gQD and rQD, respectively. PMID:24473545

Ho, Derek; Noor, M Omair; Krull, Ulrich J; Gulak, Glenn; Genov, Roman

2013-12-01

459

Commercialization Assistance Program (CAP)  

SciTech Connect

In order to fulfill the objective of Small Business Innovation Research Program (SBIR), the Department of Energy funds an initiative referred to as the Commercialization Assistance Program (CAP). The over-arching purpose of the CAP is to facilitate transition of the SBIR-funded technology to Phase III defined as private sector investment or receipt of non-sbir dollars to further the commercialization of the technology. Phase III also includes increased sales. This report summarizes the stages involved in the implementation of the Commercialization Assistance Program, a program which has been most successful in fulfilling its objectives.

Jenny C. Servo, Ph.D.

2004-07-12

460

CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics  

PubMed Central

Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art. PMID:25365460

Guo, Nan; Cheung, Ka Wai; Wong, Hiu Tung; Ho, Derek

2014-01-01

461

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.  

PubMed

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. PMID:22141918

Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

2012-01-11

462

CHAPTER FIVE COMMERCIAL PROGRAMS  

E-print Network

1970s and through the 1980s. More than once, President Ronald Reagan stated his belief that NASA should to that involvement. In 1984, in response to the Reagan administration's 1984 National Policy on the Commercial Use

463

NASA commercial programs  

NASA Technical Reports Server (NTRS)

Highlights of NASA-sponsored and assisted commercial space activities of 1989 are presented. Industrial R and D in space, centers for the commercial development of space, and new cooperative agreements are addressed in the U.S. private sector in space section. In the building U.S. competitiveness through technology section, the following topics are presented: (1) technology utilization as a national priority; (2) an exploration of benefits; and (3) honoring Apollo-Era spinoffs. International and domestic R and D trends, and the space sector are discussed in the section on selected economic indicators. Other subjects included in this report are: (1) small business innovation; (2) budget highlights and trends; (3) commercial programs management; and (4) the commercial programs advisory committee.

1990-01-01

464

COMMERCIALIZATION OF BIOCONTROL  

Technology Transfer Automated Retrieval System (TEKTRAN)

Successful commercialization of biocontrol products requires the marriage of science and industry. From a science perspective, some of the issues to be addressed include knowledge of efficacy under various environmental conditions, inoculum density relationships, formulation, and when, where and ho...

465

Technology Commercialization Program 1991  

SciTech Connect

This reference compilation describes the Technology Commercialization Program of the Department of Energy, Defense Programs. The compilation consists of two sections. Section 1, Plans and Procedures, describes the plans and procedures of the Defense Programs Technology Commercialization Program. The second section, Legislation and Policy, identifies legislation and policy related to the Program. The procedures for implementing statutory and regulatory requirements are evolving with time. This document will be periodically updated to reflect changes and new material.

Not Available

1991-11-01

466

Commercial Actors Stage Strike  

NSDL National Science Digital Library

On May 1, 2000, 75,000 members of the Screen Actors Guild (SAG) and the American Federation of Television and Radio Artists staged a walk-out in protest of advertisers's proposed changes to the ways in which actors get paid for work in commercials. According to the current pay scheme, principle on-screen actors appearing in network commercials earn $479 in base pay as well as a residual payment ranging from $47 to $123. Over a standard thirteen-week run, actors earn an average of $13,000 per commercial. However, actors in cable commercials make a flat fee of $479 to $1,014 for the same thirteen-week run. SAG and the American Federation of Television and Radio Artists are demanding a fourteen percent pay raise for both types of commercials. However, the advertisers would like to pay the actors only $2,575 for an unlimited thirteen-week network run. While this amount may seem like a lot of money, the average income for members of the SAG members is only $7000 a year, reflecting the possibility that actors may only appear in one or two commercials a year. This is the first major strike in the entertainment industry since 1988.

Missner, Emily D.

467

ERC commercialization activities  

SciTech Connect

The ERC family of companies is anticipating market entry of their first commercial product, a 2.8-MR power plant, in the second quarter of 1999. The present Cooperative Agreement provides for: (1) Commercialization planning and organizational development, (2) Completion of the pre-commercial DFC technology development, (3) Systems and plant design, (4) Manufacturing processes` scale-up to full- sized stack components and assemblies, (5) Upgrades to ERC`s test facility for full-sized stack testing, and (6) Sub-scale testing of a DFC Stack and BOP fueled with landfill gas. This paper discusses the first item, that of preparing for commercialization. ERC`s formal commercialization program began in 1990 with the selection of the 2-MR Direct Fuel Cell power plant by the American Public Power Association (APPA) for promotion to the over 2000 municipal utilities comprising APPA`s segment of the utility sector. Since that beginning, the APPA core group expanded to become the Fuel Cell Commercialization Group (FCCG) which includes representation from all markets - utilities and other power generation equipment buyers.

Maru, H.C.

1995-12-01

468

High-performance VGA-resolution digital color CMOS imager  

NASA Astrophysics Data System (ADS)

This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be suitable for a variety of color imaging applications including still/full motion imaging, security/surveillance, and teleconferencing/multimedia among other high performance, cost sensitive, low power consumer applications.

Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

1999-04-01

469

Compressive Sensing Based Bio-Inspired Shape Feature Detection CMOS Imager  

NASA Technical Reports Server (NTRS)

A CMOS imager integrated circuit using compressive sensing and bio-inspired detection is presented which integrates novel functions and algorithms within a novel hardware architecture enabling efficient on-chip implementation.

Duong, Tuan A. (Inventor)

2015-01-01

470

Hybrid Resistor/FET-Logic Demultiplexer Architecture Design for Hybrid CMOS/Nanodevice Circuits  

E-print Network

nanodevices at each crosspoint, sits on the top of a CMOS circuit. One of the main design issues in hybrid], or field effect transistor (FET) [13­15] at a subset of the microwire-nanowire cross- points. Because

Zhang, Tong

471

Time-based circuits for communication systems in advanced CMOS technology  

E-print Network

As device size scales down, there have been challenges to design conventional analog circuits, such as low voltage headroom and the low intrinsic gain of a device. Although ever-decreasing device channel length in CMOS ...

Park, Min, Ph. D. Massachusetts Institute of Technology

2009-01-01

472

Nano-scale metal contacts for future III-V CMOS  

E-print Network

As modem transistors continue to scale down in size, conventional Si CMOS is reaching its physical limits and alternative technologies are needed to extend Moore's law. Among different candidates, MOSFETs with a III-V ...

Guo, Alex

2012-01-01

473

Monolithic electronic-photonic integration in state-of-the-art CMOS processes  

E-print Network

As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. ...

Orcutt, Jason S. (Jason Scott)

2012-01-01

474

Design of CMOS integrated frequency synthesizers for ultra-wideband wireless communications systems  

E-print Network

Ultra¬wide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used...

Tong, Haitao

2009-05-15

475

Low power RF CMOS phase-shifting dual modulus (16/17) prescaler  

E-print Network

performance is analyzed. The overall system implementation is described at the transistor level and its simulation results are presented. A layout in 0.5u CMOS AMI technology is presented and the important layout considerations are discussed....

Duggal, Abhishek

2000-01-01

476

Post assembly process development for Monolithic OptoPill integration on silicon CMOS  

E-print Network

Monolithic OptoPill integration by means of recess mounting is a heterogeneous technique employed to integrate III-V photonic devices on silicon CMOS circuits. The goal is to create an effective fabrication process that ...

Lei, Yi-Shu Vivian, 1979-

2004-01-01

477

Radiation Performance of 1 Gbit DDR SDRAMs Fabricated in the 90 nm CMOS Technology Node  

NASA Technical Reports Server (NTRS)

We present Single Event Effect (SEE) and Total Ionizing Dose (TID) data for 1 Gbit DDR SDRAMs (90 nm CMOS technology) as well as comparing this data with earlier technology nodes from the same manufacturer.

Ladbury, Raymond L.; Gorelick, Jerry L.; Berg, M. D.; Kim, H.; LaBel, K.; Friendlich, M.; Koga, R.; George, J.; Crain, S.; Yu, P.; Reed, R. A.

2006-01-01

478

Development of monolithic CMOS-compatible visible light emitting diode arrays on silicon  

E-print Network

The synergies associated with integrating Si-based CMOS ICs and III-V-material-based light-emitting devices are very exciting and such integration has been an active area of research and development for quite some time ...

Chilukuri, Kamesh

2006-01-01

479

5GHz CMOS resonant clock buffer with quadrature generation for fiber optic applications  

E-print Network

Clock buffers constitute a major source of power dissipation in VLSI circuits. In CMOS the load is primarily capacitive and hence an inductive shunt can reduce real power needs. This almost-adiabatic topology is referred ...

Brasca, Claudio M. E

2004-01-01

480

Substrate engineering for monolithic integration of III-V semiconductors with Si CMOS technology  

E-print Network

Ge virtual substrates, fabricated using Si1-xGex-.Ge, compositionally graded buffers, enable the epitaxial growth of device-quality GaAs on Si substrates, but monolithic integration of III-V semiconductors with Si CMOS ...

Dohrman, Carl Lawrence

2008-01-01

481

Platform for monolithic integration of III-V devices with Si CMOS technology  

E-print Network

Monolithic integration of III-V compound semiconductors and Si complementary metal-oxide- semiconductor (CMOS) enables the creation of advanced circuits with new functionalities. In order to merge the two technologies, ...

Pacella, Nan Yang

2012-01-01

482

Silicon CMOS Ohmic Contact Technology for Contacting III-V Compound Materials  

E-print Network

Silicon (Si)-encapsulated III-V compound (III-V) device layers enable Si-complementary metal-oxide semiconductor (CMOS) friendly ohmic contact formation to III-V compound devices, allowing for the ultimate seamless planar ...

Pacella, Nan Y.

483

Passive and active circuits in cmos technology for rf, microwave and millimeter wave applications  

E-print Network

The permeation of CMOS technology to radio frequencies and beyond has fuelled an urgent need for a diverse array of passive and active circuits that address the challenges of rapidly emerging wireless applications. While traditional analog based...

Chirala, Mohan Krishna

2009-05-15

484

Integrated RF-DC converter and PCB antenna for UHF wireless powering applications  

NASA Astrophysics Data System (ADS)

In this work, a broadband differential RF-DC CMOS converter realized in CMOS 130 nm technology with a customized PCB antenna with inductive coupling feeding for RF energy scavenging is presented. Experimental results show that output DC voltage higher than 1V from 800MHz to 970MHz can be obtained with a load of 1k?.

Vincetti, L.; Maini, M.; Scorcioni, S.; Larcher, L.; Bertacchini, A.; Tacchini, A.

2014-10-01

485

A Fine Resolution TDC Architecture for Next Generation PET Imaging  

Microsoft Academic Search

A fine resolution and process scalable CMOS time-to-digital converter (TDC) architecture is presented. A 6-bit fine resolution TDC design using the new architecture is evaluated for positron emission tomography (PET) imaging application. The TDC architecture uses a hierarchical delay processing structure to achieve single cycle latency and high speed of operation. The fine resolution converter, realized in 130 nm CMOS,

Abdel S. Yousif; James W. Haslett

2007-01-01

486

Nano\\/CMOS architectures using a field-programmable nanowire interconnect  

Microsoft Academic Search

A field-programmable nanowire interconnect (FPNI) enables a family of hybrid nano\\/CMOS circuit architectures that generalizes the CMOL (CMOS\\/molecular hybrid) approach proposed by Strukov and Likharev, allowing for simpler fabrication, more conservative process parameters, and greater flexibility in the choice of nanoscale devices. The FPNI improves on a field-programmable gate array (FPGA) architecture by lifting the configuration bit and associated components

Gregory S Snider; R Stanley Williams

2007-01-01

487

Leakage current modeling of test structures for characterization of dark current in CMOS image sensors  

Microsoft Academic Search

In this paper, we present an extensive study of leakage current mechanisms in diodes to model the dark current of various pixel architectures for active pixel CMOS image sensors. Dedicated test structures made in 0.35-?m CMOS have been investigated to determine the various contributions to the leakage current. Three pixel variants with different photodiodes-n+\\/pwell, n+\\/nwell\\/p-substrate and p+\\/nwell\\/p-substrate-are described. We found

Natalia V. Loukianova; Hein Otto Folkerts; Joris P. V. Maas; Daniël W. E. Verbugt; Adri J. Mierop; Willem Hoekstra; Edwin Roks; Albert J. P. Theuwissen

2003-01-01

488

RF characterization of deep-submicron DRAM-embedded CMOS process  

Microsoft Academic Search

In this paper rf characteristics of a 0.25 ?m DRAM embedded CMOS process, focused on the n-MOSFET and the spiral inductor of the critical devices in rf CMOS circuit design, have been investigated. An extremely high cutoff frequency of 44 GHz, high maximum operating frequency of 29 GHz, and a de-embedded minimum noise figure of 1.0 dB have been obtained

Seong-Ho Park; Gwang-Hyun Lim; Yong-Hee Lee

1999-01-01

489

CMOS image sensor-based implantable glucose sensor using glucose-responsive fluorescent hydrogel  

PubMed Central

A CMOS image sensor-based implantable glucose sensor based on an optical-sensing scheme is proposed and experimentally verified. A glucose-responsive fluorescent hydrogel is used as the mediator in the measurement scheme. The wired implantable glucose sensor was realized by integrating a CMOS image sensor, hydrogel, UV light emitting diodes, and an optical filter on a flexible polyimide substrate. Feasibility of the glucose sensor was verified by both in vitro and in vivo experiments. PMID:25426316

Tokuda, Takashi; Takahashi, Masayuki; Uejima, Kazuhiro; Masuda, Keita; Kawamura, Toshikazu; Ohta, Yasumi; Motoyama, Mayumi; Noda, Toshihiko; Sasagawa, Kiyotaka; Okitsu, Teru; Takeuchi, Shoji; Ohta, Jun

2014-01-01

490

Integration of Solar Cells on Top of CMOS Chips—Part II: CIGS Solar Cells  

Microsoft Academic Search

We present the monolithic integration of deep- submicrometer complementary metal-oxide-semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance, and the solar cells on top show an efficiency of 8.4 ± 0.8% and a yield of 84%, both values being close to the glass

Jiwu Lu; Wei Liu; Alexey Y. Lu; Yun Sun; Jurriaan Lu

2011-01-01

491

Use bionic microlens array and CMOS image sensor for three-dimensional motion detection  

Microsoft Academic Search

This paper proposed a novel three dimensional motion detection design. This design consists of a bionic microlens array, which integrates an aberration limited four-lens system and a CMOS image sensor to mimic insect compound eye vision. The microlens array, made from time multiplexed SF6\\/O2 plasma and PDMS (polydimethylsiloxane)-molding, is directly placed on the top of CMOS image sensor. A LED

Chung-You Liu; Jun-Fu Chuang; Ting-Chieh Yu; Kerwin Wang

2012-01-01

492

A new readout circuit for an ultra high sensitivity CMOS image sensor  

Microsoft Academic Search

We have developed a new readout circuit for highly sensitive CMOS image sensors. The circuit makes it possible to obtain high signal-to-noise ratio (S\\/N) by effectively transferring signal charges accumulated in the photo-diode (PD) to a smaller capacitance. We fabricated and tested a CMOS image sensor with the readout circuit, and confirmed that it has higher sensitivity than conventional passive-type

T. Watabe; M. Goto; H. Ohtake; H. Maruyama; K. Tanioka

2002-01-01

493

Sub1-V CMOS Image Sensor Using Time-Based Readout Circuit  

Microsoft Academic Search

This paper proposes a sub-1-V CMOS image sensor using a time-based readout (TBR) circuit. The proposed TBR circuit senses the moment of event from the pixel instead of reading the voltage signal. This allows the use of low power-supply voltage in pixel, providing sufficient dynamic range. The prototype chip was fabricated with a 0.13- ¿m standard CMOS logic process, and

Kunhee Cho; Dongmyung Lee; Jeonghwan Lee; Gunhee Han

2010-01-01

494

Imaging and evaluation of latch-up sites in CMOS Integrated Circuits  

E-print Network

&M University Chairman Of Advisory Committee: Dr. Mark H. Weichold The primary objective of this research has been to develop an automated test to evaluate latch-up sites in Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits (ICs... 8 11 CMOS LATCH-UP Introduction Triggering Mechanisms Latch-up Model Conclusion 12 12 13 14 22 IV LATCH-UP PREVENTION Introduction Prevention Goals Guard Ring Structures Well Isolation Lightly Doped Source and Drain Regions...

Antoniou, Nicholas

1988-01-01

495

Optimized biasing technique for high-speed digital circuits with advanced CMOS nanotechnology  

Microsoft Academic Search

This paper presents a biasing optimization technique for high-speed digital circuits design with advanced CMOS nanotechnology. Modern CMOS nanotechnology introduces several new problems in high-speed circuits design. As the fastest signal frequency components approach the peak transition frequency of the MOSFET, which depends heavily on the biasing voltage, the optimized biasing techniques become very important in high-speed circuits. Many trade-offs

Bo Wang; Dianyong Chen; Bangli Liang; Tad Kwasniewski

2008-01-01

496

A 4×64 pixel CMOS image sensor for 3D measurement applications  

Microsoft Academic Search

A 4×64 pixel CMOS image sensor which can capture three-dimensional images has been integrated in a 0.5?m n-well standard CMOS processes. It is based on time-of-flight method and employs an active laser pulse illumination at 900nm optical wavelength. System bandwidth is limited by the refreshing time of the active laser source. The sensor employs the so-called \\

O. M. Schrey; O. Elkhalili; P. Mengel; M. Petermann; W. Brockherde; B. J. Hosticka

2003-01-01

497

A CMOS photosensor array for 3D imaging using pulsed laser  

Microsoft Academic Search

Summary form only given. A 32×2 pixel optical time of flight range sensor in standard 0.5 ?m CMOS acquires up to 20k BD-images\\/s combines CDS, S&H, multiple double short time integration, a high-speed synchronous shutter, and a phase synchronizer enabling exposures <30 ns with <5.2 W\\/m2 NEP. This CMOS imager chip for 3D imaging applications contains a photodiode array and

Ralf Jeremias; Werner Brockherde; Guenter Doemens; B. Hosticka; L. Listl; P. Mengel

2001-01-01

498

BiCMOS high-performance ICs: From DC to mm-wave  

Microsoft Academic Search

Progress with silicon and silicon germanium (SiGe) based BiCMOS technologies over the past few years has been very impressive. This enables the implementation of traditional microwave and emerging mm-wave applications in silicon. The paper gives an overview of several high-performance ICs that have been implemented in a state-of-the-art BiCMOS technology (QUBiC4). Examples of high-performance ICs are described ranging from basic

A. B. Smolders; H. Gul; Heijden van der E; P. Gamand; M. Geurts

2009-01-01

499

A multisampling time-domain CMOS imager with synchronous readout circuit  

Microsoft Academic Search

A novel multisampling time-domain architecture for CMOS imagers with synchronous readout and wide dynamic range is proposed. The architecture was implemented in a prototype of imager with 32x32 pixel array fabricated in AMS CMOS 0.35µm and was characterized for sensitivity and color response. The pixel is composed of an n+\\/psub photodiode, a comparator and a D flip-flop having 16% fill-factor

Fernando De Souza Campos; Ognian Marinov; Naser Faramarzpour; Fayçal Saffih; M. Jamal Deen; Jacobus W. Swart

2007-01-01

500

[The use of c-mos nuclear gene as a phylogenetic marker in tetraonidae birds].  

PubMed

A 480-bp fragment of nuclear c-mos gene was sequenced in nine bird species representing four genera of the family Tetraonidae. It was demonstrated that nuclear genome region examined was highly conservative. The data were used to construct phylogenetic relationships among the c-mos gene sequences in Tetraonidae. The data obtained point to a paraphyletic origin of hazel grouse (Bonasa bonasia) and ruffed grouse (Bonasa umbellus). PMID:15575499

Butorina, O T; Colovenchuk, L L

2004-10-01