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1

Total Ionizing Dose effects in 130-nm commercial CMOS technologies for HEP experiments  

Microsoft Academic Search

The impact of foundry-to-foundry variability and bias conditions during irradiation on the Total Ionizing Dose (TID) response of commercial 130-nm CMOS technologies have been investigated for applications in High Energy Physics (HEP) experiments. n- and p-channel MOSFETs from three different manufacturers have been irradiated with X-rays up to more than 100Mrad (SiO2). Even though the effects of TID are qualitatively

L. Gonella; F. Faccio; M. Silvestri; S. Gerardin; D. Pantano; V. Re; M. Manghisoni; L. Ratti; A. Ranieri

2007-01-01

2

Total Ionizing Dose effects in 130-nm commercial CMOS technologies for HEP experiments  

NASA Astrophysics Data System (ADS)

The impact of foundry-to-foundry variability and bias conditions during irradiation on the Total Ionizing Dose (TID) response of commercial 130-nm CMOS technologies have been investigated for applications in High Energy Physics (HEP) experiments. n- and p-channel MOSFETs from three different manufacturers have been irradiated with X-rays up to more than 100 Mrad (SiO 2). Even though the effects of TID are qualitatively similar, the amount of degradation is shown to vary considerably from foundry to foundry, probably depending on the processing of the STI oxide and/or doping profile in the substrate. The bias during irradiation showed to have a strong impact as well on the TID response, proving that exposure at worst case bias conditions largely overestimates the degradation a device may experience during its lifetime. Overall, our results increase the confidence that 130-nm CMOS technologies can be used in future HEP experiments even without Hardness-By-Design solutions, provided that constant monitoring of the radiation response is carried out during the full manufacturing phase of the circuits.

Gonella, L.; Faccio, F.; Silvestri, M.; Gerardin, S.; Pantano, D.; Re, V.; Manghisoni, M.; Ratti, L.; Ranieri, A.

2007-12-01

3

Noise Characterization of 130 nm and 90 nm CMOS Technologies for Analog Front-end Electronics  

Microsoft Academic Search

Deep-submicron complementary MOS processes have made the development of ASICs for HEP instrumentation possible. In the last few years CMOS commercial technologies of the quarter micron node have been extensively used in the design of the readout electronics for highly granular detection systems in the particle physics environment. IC designers are now moving to 130 nm CMOS technologies, or even

M. Manghisoni; L. Ratti; V. Re; V. Speziali; G. Traversi

2006-01-01

4

Innovative Simulations of Heavy Ion Cross Sections in 130 nm CMOS SRAM  

Microsoft Academic Search

A simulation tool to predict the heavy ion cross section is proposed. A 20% average error between experimental and simulated results is shown for a SRAM in a commercial 130 nm CMOS technology. Input parameters are obtained by device or circuit simulations and no fitting parameters or empirical calibration with previous radiation testings is needed.

Vincent Correas; F. Saigne; B. Sagnes; J. Boch; G. Gasiot; D. Giot; P. Roche

2007-01-01

5

Electron Charge Noise Minimization, in 130 nm CMOS Preamplifiers  

NASA Astrophysics Data System (ADS)

In this paper we present the design aspects for low-power, low-noise CMOS charge sensitive preamplifier that uses a leakage current compensation circuit for use with radiation sensors. The preamplifier has unipolar response with the peaking time of about 45 ns and the gain about 115-145 mV/ke. Equivalent noise charge (ENC) is less than 80 e, when the input charge is 1-20 ke and the sensors capacitance is equal to 30 fF. In this work we present the quality function of the charge sensitive preamplifier, which characterizes best the optimal input transistor width W, with respect to equivalent noise charge and to the power consumptions.

Barzdenas, V.; Navickas, R.

2008-03-01

6

Status and perspectives of deep N-well 130 nm CMOS MAPS  

NASA Astrophysics Data System (ADS)

Deep N-Well (DNW) MAPS were developed in two different flavors to approach the specifications of vertex detectors in dissimilar experimental environments such as the Super B-Factory and the ILC. The first generation of MAPS with on-pixel data sparsification and time stamping capabilities is now available and was tested in a beam for the first time in September 2008. These devices are fabricated in a commercial 130 nm CMOS process, and the triple well structure available in such an ultra-deep submicron technology is exploited by using the deep N-well as the charge-collecting electrode. Because of the high integration density of such a technology, complex digital functions can be included in each pixel, implementing a sparsified readout architecture of the pixel matrix with time stamping. This paper reviews the features of the ``ILC class'' and ``SuperB class'' MAPS devices, discussing their different design in terms of pixel pitch, analog signal processing, and digital readout architecture. For SuperB, a data-driven, continuously operating readout scheme was adopted along with a macropixel matrix arrangement, whereas for the ILC the matrix is read out in the long intertrain period. In both versions, the address of hit pixels is transmitted off-chip along with the time stamp. The experimental performance of the chips provides an assessment of the Deep N-Well MAPS potential in view of future applications. The paper also discusses the way forward in the development of these devices, outlining the issues that have to be tackled to design full size Deep N-Well MAPS for actual experiments. These sensors could take advantage from technological advances in microelectronic industry, such as vertical integration. The impact of these new technologies on the design and performance of DNW pixel sensors could be large, with potential benefit for various device features, from the charge collection properties to the digital readout architecture.

Re, Valerio

2009-03-01

7

Impact of MOSFET gate-oxide reliability on CMOS operational amplifiers in a 130-nm low-voltage CMOS process  

Microsoft Academic Search

The effects of the gate-oxide reliability of MOSFETs on operational amplifiers were investigated with the two-stage and folded-cascode structures in a 130-nm low-voltage CMOS process. The tested operating conditions include unity-gain buffer (close-loop configuration) and comparator (open-loop configuration) under different input frequencies and signals. After overstress, the small-signal parameters, such as small-signal gain, unity-gain frequency, and phase margin, were measured

Jung-Sheng Chen; Ming-Dou Ker

2005-01-01

8

Development of scalable frequency and power Phase-Locked Loop in 130 nm CMOS technology  

NASA Astrophysics Data System (ADS)

The design and measurements results of a prototype very low power Phase-Locked Loop (PLL) ASIC for applications in readout systems of particle physics detectors are presented. The PLL was fabricated in 130 nm CMOS technology. It was designed and simulated for frequency range 10 MHz-3.5 GHz. Four division factors i.e. 6, 8, 10 and 16 were implemented in the PLL feedback loop. The main PLL block-voltage controlled oscillator (VCO) should work in 16 frequency ranges/modes, switched either manually or automatically. Preliminary measurements done in frequency range 20 MHz-1.6 GHz showed that the ASIC is functional and generates proper clock signal. The automatic VCO mode switching, one of the main design goals, was positively verified. Power consumption of around 0.6 mW was measured at 1 GHz for a division factor equal to 10.

Firlej, M.; Fiutowski, T.; Idzik, M.; Moro?, J.; ?wientek, K.

2014-02-01

9

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS  

Microsoft Academic Search

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The trans- ceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase\\/frequency detector and charge-pump

Robert Bogdan Staszewski; Khurram Muhammad; Dirk Leipold; Chih-Ming Hung; Yo-Chuol Ho; John L. Wallberg; Chan Fernando; Ken Maggio; Roman Staszewski; Tom Jung; Jinseok Koh; Soji John; Irene Yuanying Deng; Vivek Sarda; Oscar Moreira-Tamayo; Valerian Mayega; Ofer Friedman; Oren Eytan Eliezer; Poras T. Balsara; E. de-Obaldia

2004-01-01

10

Heavy ion-induced SEEs on 130 nm CMOS technology for LHC application—status and challenges  

NASA Astrophysics Data System (ADS)

This work summarizes the status of the art of electronic designs, using CMOS technologies, to stand LHC and S-LHC radiation-hard environments. Radiation effects can be divided into Single Event Effects and Total Ionizing Dose effects, which are consequences of different interaction effects within the silicon and the electronics. These types of effects are commonly investigated and faced separately. The commercial 130 nm CMOS technology, today primarily proposed for SLHC electronic upgrades, only implements redundancies against the Single Event Effects`. On the contrary, the 250 nm technology node used in the past years for LHC experiments, was also hardened against the Total Ionizing Dose. Hence, the choice of the technology to be used for high-energy experiments is very crucial as it implies huge efforts in the designs of the components. In addition, an unavoidable technology scaling keeps moving toward ever-smaller sizes and this affects the availability of the silicon process for medium and long-term experiments.

Gabrielli, A.

2011-12-01

11

Impact of MOSFET Gate-Oxide Reliability on CMOS Operational Amplifier in a 130-nm Low-Voltage Process  

Microsoft Academic Search

The effect of the MOSFET gate-oxide reliability on operational amplifier is investigated with the two-stage and folded-cascode structures in a 130-nm low-voltage CMOS process. The test operation conditions include unity-gain buffer (close-loop) and comparator (open-loop) configurations under the dc stress, ac stress with dc offset, and large-signal transition stress. After overstress, the small-signal parameters, such as small-signal gain, unity-gain frequency,

Ming-Dou Ker; Jung-Sheng Chen

2008-01-01

12

Radiation hardness evaluation of a 130 nm SiGe BiCMOS technology for high energy physics applications  

NASA Astrophysics Data System (ADS)

Final results for a comprehensive radiation hardness evaluation of a high performance, low cost, 130 nm SiGe BiCMOS technology are presented. After a survey of several available SiGe technologies, one was chosen in terms of performance, power consumption, radiation hardness, and cost and it is presented as a suitable technology for the future upgrades of the ATLAS detector of the High Luminosity LHC. Bipolar devices of different sizes and geometries have been evaluated, along with a prototype Front-End readout ASIC designed for binary readout of silicon microstrip detectors. Gamma, neutron and proton irradiations have been performed up to the expected doses and fluences of the experiment.

Díez, S.; Clark, T.; Grillo, A. A.; Kononenko, W.; Martinez-McKinney, F.; Newcomer, F. M.; Norgren, M.; Rescia, S.; Spencer, E.; Spieler, H.; Ullán, M.; Wilder, M.

2013-10-01

13

Traveling wave electrode design for ultra compact carrier-injection HBT-based electroabsorption modulator in a 130nm BiCMOS process  

NASA Astrophysics Data System (ADS)

Silicon photonic system, integrating photonic and electronic signal processing circuits in low-cost silicon CMOS processes, is a rapidly evolving area of research. The silicon electroabsorption modulator (EAM) is a key photonic device for emerging high capacity telecommunication networks to meet ever growing computing demands. To replace traditional large footprint Mach-Zehnder Interferometer (MZI) type modulators several small footprint modulators are being researched. Carrier-injection modulators can provide large free carrier density change, high modulation efficiency, and compact footprint. The large optical bandwidth and ultra-fast transit times of 130nm HBT devices make the carrierinjection HBT-based EAM (HBT-EAM) a good candidate for ultra-high-speed optical networks. This paper presents the design and 3D full-wave simulation results of a traveling wave electrode (TWE) structure to increase the modulation speed of a carrier-injection HBT-EAM device. A monolithic TWE design for an 180um ultra compact carrier-injection-based HBT-EAM implemented in a commercial 130nm SiGe BiCMOS process is discussed. The modulator is electrically modeled at the desired bias voltage and included in a 3D full-wave simulation using CST software. The simulation shows the TWE has a S11 lower than -15.31dB and a S21 better than -0.96dB covering a bandwidth from DC-60GHz. The electrical wave phase velocity is designed close to the optical wave phase velocity for optimal modulation speed. The 3D TWE design conforms to the design rules of the BiCMOS process. Simulation results show an overall increase in modulator data rate from 10Gbps to 60Gbps using the TWE structure.

Fu, Enjin; Joyner Koomson, Valencia; Wu, Pengfei; Huang, Z. Rena

2014-03-01

14

High-speed digital circuits for a 2.4 GHz all-digital RF frequency synthesizer in 130 nm CMOS  

Microsoft Academic Search

We present high-speed digital circuits that comprise the first ever reported all-digital 2.4 GHz frequency synthesizer and transmitter that meet the Bluetooth specifications. The chip is built in a digital 130 nm CMOS process with no analog extensions and features high logic gate density of 150 kgates per mm2. The transmitter architecture is based on an all-digital phase-locked loop (AD-PLL),

Robert B. Staszewski; John Wallberg; JinseoK Koh; P. T. Balsara

2004-01-01

15

A K-Band nMOS SPDT Switch and Phase Shifter Implemented in 130nm SiGe BiCMOS Technology  

Microsoft Academic Search

The design and performance of optimized K-band nMOS SPDT switches and a switched-line 180deg single-bit phase shifter are presented. The design demonstrates the use of low insertion loss nMOSFET switches in 130 nm silicon-germanium (SiGe) BiCMOS technology. Design and layout optimization approaches for MOSFET based series-shunt, single-pole double-throw (SPDT) switches have been investigated. The designed switches use deep trench substrate

Prabir K. Saha; Jonathan P. Comeau; Wei-Min Lance Kuo; John D. Cressler

2009-01-01

16

Analysis and Design of Reduced-Size Marchand Rat-Race Hybrid for Millimeter-Wave Compact Balanced Mixers in 130-nm CMOS Process  

Microsoft Academic Search

The analysis and design flow for reduced-size Marchand rat-race hybrids are presented in this paper. A simplified single-to-differential mode is used to analyze the Marchand balun, and the methodology to reduce the size of Marchand balun is developed. The 60-GHz CMOS singly balanced gate mixer and diode mixer using the reduced-size Marchand rat-race hybrid are implemented to verify the design

Chun-Hsien Lien; Chi-Hsueh Wang; Chin-Shen Lin; Pei-Si Wu; Kun-You Lin; Huei Wang

2009-01-01

17

A saw-less direct conversion long term evolution receiver with 25% duty-cycle LO in 130 nm CMOS technology  

NASA Astrophysics Data System (ADS)

A CMOS long-term evolution (LTE) direct convert receiver that eliminates the interstage SAW filter is presented. The receiver consists of a low noise variable gain transconductance amplifier (TCA), a quadrature passive current commutating mixer with a 25% duty-cycle LO, a trans-impedance amplifier (TIA), a 7th-order Chebyshev filter and programmable gain amplifiers (PGAs). A wide dynamic gain range is allocated in the RF and analog parts. A current commutating passive mixer with a 25% duty-cycle LO improves gain, noise, and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference. Fabricated in a 0.13 ?m CMOS process, the receiver chain achieves a 107 dB maximum voltage gain, 2.7 dB DSB NF (from PAD port), -11 dBm IIP3, and > +65 dBm IIP2 after calibration, 96 dB dynamic control range with 1 dB steps, less than 2% error vector magnitude (EVM) from 2.3 to 2.7 GHz. The total receiver (total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.

Siyuan, He; Changhong, Zhang; Liang, Tao; Weifeng, Zhang; Longyue, Zeng; Wei, Lü; Haijun, Wu

2013-03-01

18

The eCDR, a Radiation-Hard 40/80/160/320 Mbit/s CDR with internal VCO frequency calibration and 195 ps programmable phase resolution in 130 nm CMOS  

NASA Astrophysics Data System (ADS)

A clock and data recovery IP, the eCDR, is presented which is intended to be implemented on the detector front-end ASICs that need to communicate with the GBTX by means of e-links. The programmable CDR accepts data at 40, 80, 160 or 320Mbit/s and generates retimed data as well as 40, 80, 160 and 320MHz clocks that are aligned to the retimed data. Moreover, all the outputs have a programmable phase with a resolution of 195ps. An internal calibration mechanism enables the eCDR to lock on incoming data even without the availability of any form of reference clock. The radiation-hard design, integrated in a 130nm CMOS technology, operates at a supply voltage between 1.2V and 1.5V. The power consumption is between 28.5mW and 34.5mW, depending on the settings. The eCDR can achieve a very low RMS jitter below 10ps.

Tavernier, F.; Francisco, R.; Bonacini, S.; Poltorak, K.; Moreira, P.

2013-12-01

19

Simulation Tool for the Prediction of Heavy Ion Cross Section of Innovative 130-nm SRAMs  

Microsoft Academic Search

The prediction of heavy ions cross sections of an innovative SRAM is carried out in a 130-nm CMOS technology. The work is realized with a simulation tool generally used to predict standard SRAM sensitivity. This simulation tool needs input parameters to describe both standard and innovative SRAM. From the standard to the innovative structure, input parameters are simply evaluated using

Vincent Correas; Frédéric Saigne; Bruno Sagnes; Jérôme Boch; Gilles Gasiot; Damien Giot; Philippe Roche

2008-01-01

20

Forbidden pitches for 130-nm lithography and below  

NASA Astrophysics Data System (ADS)

Experiments and simulations were done to determine which pitches are forbidden for 130nm and 110nm features. Off axis illumination, annular and Quasar, and different reticle types, binary mask (BIM), 6 percent attenuating phase shift mask (PSM), 18 percent attenuating PSM, and alternating PSM were simulated and were exposed on an ASML PAS5500/700. Except for the 1:1 line to space ratio, Quasar for the BIM and the attenuated PSM had the largest process window without forbidden pitches. By increasing the transmission the exposure latitude increases. Increasing transmission, however, does not improve the depth of focus (DOF). Annular illumination was ineffective in increasing the DOF beyond 0.5micrometers for both the 130nm and 110nm features. The alternating PSM with low sigma had no forbidden pitches and had the largest DOF. Alternating PSM with high sigma however, was unable to resolve the dense pitches with sufficient process window.

Socha, Robert J.; Dusa, Mircea V.; Capodieci, Luigi; Finders, Jo; Chen, Jang Fung; Flagello, Donis G.; Cummings, Kevin D.

2000-07-01

21

Tests of commercial colour CMOS cameras for astronomical applications  

NASA Astrophysics Data System (ADS)

We present some results of testing commercial colour CMOS cameras for astronomical applications. Colour CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in colour CMOS sensors is close to the astronomical Johnson BVR system. The basic camera characteristics: read noise (e^{-}/pix), thermal noise (e^{-}/pix/sec) and electronic gain (e^{-}/ADU) for the commercial digital camera Canon 5D MarkIII are presented. We give the same characteristics for the scientific high performance cooled CCD camera system ALTA E47. Comparing results for tests of Canon 5D MarkIII and CCD ALTA E47 show that present-day commercial colour CMOS cameras can seriously compete with the scientific CCD cameras in deep astronomical imaging.

Pokhvala, S. M.; Reshetnyk, V. M.; Zhilyaev, B. E.

2013-12-01

22

A 60 GHz CMOS balanced downconversion mixer with a layout efficient 90° hybrid coupler  

Microsoft Academic Search

This paper presents the design and realization of a downconversion mixer fabricated in a standard 130 nm commercial CMOS process and aimed at applications in the 60 GHz ISM band. A balanced mixer configuration was implemented using a layout efficient 90deg hybrid coupler which serves as a diplexer to inject the LO signal while also providing two outputs with 3

R. E. Amaya; Cornelius J. Verver

2009-01-01

23

Total dose hardness of three commercial CMOS microelectronics foundries  

Microsoft Academic Search

We have measured the effects of total ionizing dose (TID) on CMOS FETs, ring oscillators and field-oxide transistor test structures fabricated at three different commercial foundries with four different processes. The foundries spanned a range of integration levels and included Hewlett-Packard (HP) 0.5 ?m and 0.8 ?m processes, an Orbit 1.2 ?m process, and an AMI 1.6 ?m process. We

J. V. Osborn; R. C. Lacoe; D. C. Mayer; G. Yabiku

1998-01-01

24

Total dose hardness of a commercial SiGe BiCMOS technology  

Microsoft Academic Search

Over the past decade SiGe HBT technology has progressed from the laboratory to practical commercial applications. When integrated into a CMOS process, this technology has potential applications in low-cost space systems. In this paper, we report results of total ionizing dose testing of a SiGe\\/CMOS process accessible through a commercial foundry

N. van Vonno; Robert Lucas; David Thornberry

1999-01-01

25

130-nm KrF lithography for DRAM production with 0.68-NA scanner  

NASA Astrophysics Data System (ADS)

We have proposed a methodology for 130-nm DRAM patterning. We started by running a simulation to investigate the possibility of 130-nm DRAM production with KrF lithography. We optimized cell array features and isolate lines in the core circuits and peripheral circuits, corresponding to resist performance ((Delta) L). Using a half-tone phase-shift mask, off-axis illumination, and 0.68-NA KrF scanner, we found a high-performance resist of 40-nm (Delta) L that meets the requirement. Then, we screened resist samples using design of experiment. The result was a 40-nm (Delta) L positive resist that has small line edge roughness, a high- contrast resist profile, a small iso-dense bias and a low- blocking level to prevent defects. Finally, we applied this positive resist and OPC-mask to critical layers and achieved a sufficient production margin using a 0.68-NA KrF scanner.

Kawamura, Eiichi; Nagai, Kouichi; Kanemitsu, Hideyuki; Tabata, Yasuko; Inoue, Soichi

2000-07-01

26

Evaluation of a high-dose extended multipass gray writing system for 130-nm pattern generation  

NASA Astrophysics Data System (ADS)

Recent developments in electron-beam (e-beam) systems and mask-writing strategies facilitate pattern generation for the 130-nm IC generation. The MEBESR 5500 pattern generation system incorporates a high-dose electron optical system and a high-throughput writing strategy, Multipass Gray-II (MPG-II). We evaluate the effectiveness of these innovations by three criteria: improved resolution, improved critical dimension (CD) control, and increased throughput. The conclusions of this paper are based on results from extensive modeling, test masks, and factory acceptance masks. Mask resist choice and processing have been optimized for the MEBES 5500 system. A consequence of these improvements is greater productivity for 150 nm devices and early development of 130 nm devices. The MEBES 5500 system uses a high-dose gun and electron optical system. The maximum current density that can be delivered to the mask is 800 A/cm2, twice the value of previous MEBES systems. Without loss of throughput, it is possible to increase the dose deposited in the resist, while using smaller e-beam sizes. These capabilities are exploited to improve printing of submicrometer features, including 200 nm-scale optical proximity correction (OPC) patterns. At small data addresses (<17.1 nm), the MPG-II writing strategy provides twice the throughput of the existing multipass gray (MPG) strategy with the same instrument, and 16X the throughput of traditional single-pass printing (SPP) with the MEBES 4500 system. The fundamentals of the MPG-II strategy are described, as well as throughput and lithographic results.

Chabala, Jan M.; Weaver, Suzanne; Alexander, David; Pearce-Percy, Henry T.; Lu, Maiying; Cole, Damon M.; Abboud, Frank E.

2000-07-01

27

Lifetime studies of 130nm nMOS transistors intended for long-duration, cryogenic high-energy physics experiments.  

SciTech Connect

Future neutrino physics experiments intend to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. To increase performance, integrated readout electronics should work inside the cryostat. Due to the scale and cost associated with evacuating and filling the cryostat, the electronics will be unserviceable for the duration of the experiment. Therefore, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is via hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130nm nMOS transistors operating at cryogenic temperatures are investigated. The results show that the difference in lifetime for room temperature operation and cryogenic operation for this process are not great and the lifetimes at both 300K and at 77K can be projected to more than 20 years at the nominal voltage (1.5V) for this technology.

Hoff, J.R.; /Fermilab; Arora, R.; Cressler, J.D.; /Georgia Tech; Deptuch, G.W.; /Fermilab; Gui, P.; /Southern Methodist U.; Lourenco, N.E.; /Georgia Tech; Wu, G.; /Southern Methodist U.; Yarema, R.J.; /Fermilab

2011-12-01

28

130-nm reticle inspection using multibeam UV-wavelength database inspection  

NASA Astrophysics Data System (ADS)

The TeraStar family of reticle inspection systems were introduced in 2000 with die-to-die and STARlightT capability. These tools set the standard for high-resolution reticle inspection for the 130 nm design rule and below. The latest addition to the TeraStar family is the TeraStar SLF77, which extends the tool platform to include die-to-database inspection capability. Sensitivity for Chrome on Glass is 100 nm with much greater tolerance for inspecting aggressive OPC features such as serifs and assist lines. Many advanced reticles that are not inspectable on previous generation inspection tools are all inspectable on the TeraStar SLF77. Data prep times and file structure have been significantly improved with the average prep time being less than 10 percent of the 365UV-HR and average output file size less than 25 percent of the GigaPrep. The TeraStar SLF77 incorporates all the features of the TeraStar family such as triple-beam optics and TeraPro HP High Productivity Modes with the ability to run STARlight inspections concurrently with either die-to-die or die-to-database pattern inspections. Advanced registration algorithms accommodate subtle plate and machine errors to provide high sensitivity with low false detections. Advanced image overlay inspects small lines and OPC features and is very independent of defect shape and location. The TeraStar SLF77 has removed the barriers that existed with previous generation database inspection tools and made advanced reticle die-to-database inspection cost effective. Last October, KLA-Tencor introduced the TeraStar SLF77 and the three beta sites have recently completed beta evaluation. Here we present the first results from the use of the TeraStar in a production environment triple beam die-to-database inspection system. We have also shipped more than ten systems to customers worldwide. This paper describes the implementation of productivity improvements at the beta sites, performance on 130nm node customer product reticles, and KLA-Tencor's continued development on advanced inspection reticles.

Aquino, Christopher; Schlaffer, Robert

2002-07-01

29

Integration considerations for 130-nm device patterning using ArF lithography  

NASA Astrophysics Data System (ADS)

With the delivery of ful field ArF steppers and scanners to the leading edge IC manufacturers in 1999 for process development work, the industry is poised to implement ArF lithography in volume production in a few years from now. The introduction of ArF lithography in large volume deice manufacturing will be at the 130-nm technology node, with a k1-factor of roughly 0.4. This will represent the first time in the history of the semiconductor industry when the critical feature size of first generation devices for a given technology node is significantly smaller than the lithographic wavelength used in the patterning. Accordingly, there are a number of integration issues that must be resolved to ensure the successful implement of this technology. Such issues include antireflection coatings issues like reflectivity control and thickness, and the tradeoffs between using organic and inorganic ARCs; resist material issues like optical absorption, feature profile, CD uniformity and line edge roughness; and etch issues like resist loss, line edge roughening, endcap pullback, etc. For instance, one of the major problems with most currently available 193-nm resists is their high optical absorption at the exposure wavelength. This necessitates the use of significantly thinner 193-nm resist films than have been the case in earlier lithographic regimes, but etch considerations preclude this option as these materials do not have bey good etch stability. A balance between absorption and etch requirements must therefore be struck to ensure the successful implementation of this lithography. The above outlined integration issues involved in striking this balance are the subject of this paper, and they will be presented from a patterning perspective. Our exposures are made with ASML/900 full field scanner.

Okoroanyanwu, Uzodinma; Levinson, Harry J.; Yang, Chih-Yuh; Pangrle, Suzette K.; Schefske, Jeff A.; Kent, Eric

2000-07-01

30

A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects  

Microsoft Academic Search

A leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported. Dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V. High Vt transistors have drive currents of 1.03 mA\\/?m and 0.5 mA\\/?m for NMOS and PMOS respectively, while low Vt transistors have currents of 1.17 mA\\/?m

S. Tyagi; M. Alavi; R. Bigwood; T. Bramblett; J. Brandenburg; W. Chen; B. Crew; M. Hussein; P. Jacob; C. Kenyon; C. Lo; B. McIntyre; Z. Ma; P. Moon; P. Nguyen; L. Rumaner; R. Schweinfurth; S. Sivakumar; M. Stettler; S. Thompson; B. Tufts; J. Xu; S. Yang; M. Bohr

2000-01-01

31

Millimeter-wave CMOS design  

Microsoft Academic Search

Abstract—This paper describes the design and modeling of CMOS transistors, integrated passives, and circuit blocks at millimeter-wave (mm-wave) frequencies. The effects of parasitics on the high-frequency performance of 130-nm CMOS transistors are investigated, and a peak of 135 GHz has been achieved with optimal device layout. The inductive quality factor is proposed as a more representative metric for transmission lines,

C. H. Doan; S. Emami; A. M. Niknejad; R. W. Brodersen

2005-01-01

32

Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications  

NASA Technical Reports Server (NTRS)

This paper describes ongoing research and development of CMOS active pixel image sensors for low cost commercial applications. A number of sensor designs have been fabricated and tested in both p-well and n-well technologies. Major elements in the development of the sensor include on-chip analog signal processing circuits for the reduction of fixed pattern noise, on-chip timing and control circuits and on-chip analog-to-digital conversion (ADC). Recent results and continuing efforts in these areas will be presented.

Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.; Ackland, B.; Dickinson, A.; Eid, E.; Inglis, D.

1994-01-01

33

Radiation hardness evaluation of the commercial 150 nm CMOS process using 60Co source  

NASA Astrophysics Data System (ADS)

We present a study of radiation effects on MOSFET transistors irradiated with a 60Co source to a total absorbed dose of 1.5 Mrad. The transistor test structures were manufactured using a commercial 150 nm CMOS process and are composed of transistors of different types (NMOS and PMOS), dimensions and insulation from the bulk material by means of deep n-wells. We have observed a degradation of electrical characteristics of both PMOS and NMOS transistors, namely a large increase of the leakage current of the NMOS transistors after irradiation.

Carna, M.; Havranek, M.; Hejtmanek, M.; Janoska, Z.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

2014-06-01

34

Study of total ionizing dose radiation effects on enclosed gate transistors in a commercial CMOS technology  

NASA Astrophysics Data System (ADS)

This paper studies the total ionizing dose radiation effects on MOS (metal-oxide-semiconductor) transistors with normal and enclosed gate layout in a standard commercial CMOS (compensate MOS) bulk process. The leakage current, threshold voltage shift, and transconductance of the devices were monitored before and after ?-ray irradiation. The parameters of the devices with different layout under different bias condition during irradiation at different total dose are investigated. The results show that the enclosed layout not only effectively eliminates the leakage but also improves the performance of threshold voltage and transconductance for NMOS (n-type channel MOS) transistors. The experimental results also indicate that analogue bias during irradiation is the worst case for enclosed gate NMOS. There is no evident different behaviour observed between normal PMOS (p-type channel MOS) transistors and enclosed gate PMOS transistors.

Li, Dong-Mei; Wang, Zhi-Hua; Huangfu, Li-Ying; Gou, Qiu-Jing

2007-12-01

35

Micro Ethanol Sensors with a Heater Fabricated Using the Commercial 0.18 ?m CMOS Process  

PubMed Central

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm.

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

36

Investigating the degradation mechanisms caused by the TID effects in 130 nm PDSOI I/O NMOS  

NASA Astrophysics Data System (ADS)

This paper evaluates the radiation responses of 3.3 V I/O NMOSFETs from 130 nm partially-depleted silicon-on-insulator (PDSOI) technology. The data obtained from 60Co ionizing radiation experiments indicate that charge trapped in the shallow trench isolation, particularly at the bottom region of the trench oxide, should be the dominant contributor to the off-state drain-to-source leakage current under ON bias. The body doping profile and device dimension are two key factors affecting the performance degradation of the PDSOI transistors after radiation. Significant front gate threshold voltage shift is observed in the T-shape gate device, which is well known as the Radiation Induced Narrow Channel Effect (RINCE). The charge trapped in the buried oxide can induce large threshold voltage shift in the front gate transistor through coupling effect in the low body doping device. The coupling effect is evaluated through three-dimensional simulation. A degradation of the carrier mobility which relates to shallow trench isolation (STI) oxide trapped charge in the narrow channel device is also discussed.

Peng, Chao; Hu, Zhiyuan; Zhang, Zhengxuan; Huang, Huixiang; Ning, Bingxu; Bi, Dawei

2014-06-01

37

Implementing Power Management IP for Dynamic and Static Power Reduction in Configurable Microprocessors using the Galaxy Design Platform at 130nm  

Microsoft Academic Search

At 130 nm and 90 nm, power consumption (both dynamic and static) has become a barrier in the roadmap for SoC designs targeting battery powered, mobile applications. This paper presents the results of dynamic and static power reduction achieved implementing Tensilica's 32-bit Xtensa microprocessor core, using Virtual Silicon's Power Management IP in the Galaxy Design Platform (Design Compiler, Physical Compiler,

Dan Hillman

38

An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V  

Microsoft Academic Search

A leading edge 130 nm technology with 6 layers of Cu interconnects and 1.3 V operation has previously been presented (Tyagi et al., 2000). In this work, we enhance the previous technology with the following: transistor improvements which support a 60 nm gate dimension and increased drive current, improved 6-T SRAM device matching to allow low power and high performance

S. Thompson; M. Alavi; R. Arghavani; A. Brand; R. Bigwood; J. Brandenburg; B. Crew; V. Dubin; M. Hussein; P. Jacob; C. Kenyon; E. Lee; B. Mcintyre; Z. Ma; P. Moon; P. Nguyen; M. Prince; R. Schweinfurth; S. Sivakumar; P. Smith; M. Stettler; S. Tyagi; M. Wei; J. Xu; S. Yang; M. Bohr

2001-01-01

39

1Gb\\/s integrated optical detectors and receivers in commercial CMOS technologies  

Microsoft Academic Search

The ability to produce a high-performance monolithic CMOS photoreceiver, including the photodetector, could enable greater use of optics in short-distance communication systems. Such a receiver requires the ability to simultaneously produce a photodetector compatible with a high-volume high-yield CMOS process, as well as the entire receiver circuit. The quest for this element has yet to produce a clear winner, and

T. K. Woodward; Ashok V. Krishnamoorthy

1999-01-01

40

A Reconfigurable, 130 nm CMOS 108 pJ\\/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging  

Microsoft Academic Search

This paper presents a fully integrated flexible ultra-low power UWB impulse radio receiver, capable of cm-accurate ranging. Ultra-low-power consumption is achieved by employing the quadrature analog correlating receiver architecture, by exploiting the duty-cycled nature of the system, by operating in the sub-1 GHz band as well as by careful circuit design. Two pulse rates, 39.0625 Mpulses per second (Mpps) and

Nick Van Helleputte; Marian Verhelst; Wim Dehaene; Georges Gielen

2010-01-01

41

A 60GHz down-converting CMOS single-gate mixer  

Microsoft Academic Search

A quadrature balanced single-gate CMOS mixer, designed to exploit the unlicensed band around 60-GHz, is presented. Also a millimeter-wave (mm-wave) modeling methodology is discussed which is suitable for the design of CMOS mm-wave active mixers. The performance of a fully-integrated mixer fabricated on a standard digital 130-nm CMOS process is given and compared to the simulations. At a radio frequency

Sohrab Emami; Chinh H. Doan; Ali M. Niknejad; Robert W. Brodersen

2005-01-01

42

A Comparative Study of Heavy Ion and Proton Induced Bit Error Sensitivity and Complex Burst Error Modes in Commercially Available High Speed SiGe BiCMOS  

NASA Technical Reports Server (NTRS)

A viewgraph presentation that reviews recent SiGe bit error test data for different commercially available high speed SiGe BiCMOS chips that were subjected to various levels of heavy ion and proton radiation. Results for the tested chips at different operating speeds are displayed in line graphs.

Marshall, Paul; Carts, Marty; Campbell, Art; Reed, Robert; Ladbury, Ray; Seidleck, Christina; Currie, Steve; Riggs, Pam; Fritz, Karl; Randall, Barb

2004-01-01

43

An Acetone Microsensor with a Ring Oscillator Circuit Fabricated Using the Commercial 0.18 ?m CMOS Process.  

PubMed

This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is ?-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the ?-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm. PMID:25036331

Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

2014-01-01

44

Forecasting noise and radiation hardness of CMOS front-end electronics beyond the 100 nm frontier  

NASA Astrophysics Data System (ADS)

The progress of industrial microelectronic technologies has already overtaken the 130 nm CMOS generation that is currently the focus of IC designers for new front-end chips in LHC upgrades and other detector applications. In a broader time span, sub-100 nm CMOS processes may become appealing for the design of very compact front-end systems with advanced integrated functionalities. This is especially true in the case of pixel detectors, both for monolithic devices (MAPS) and for hybrid implementations where a high resistivity sensor is connected to a CMOS readout chip. Technologies beyond the 100 nm frontier have peculiar features, such as the evolution of the device gate material to reduce tunneling currents through the thin dielectric. These new physical device parameters may impact on functional properties such as noise and radiation hardness. On the basis of experimental data relevant to commercial devices, this work studies potential advantages and challenges associated to the design of low-noise and rad-hard analog circuits in these aggressively scaled technologies.

Re, V.; Gaioni, L.; Manghisoni, M.; Ratti, L.; Traversi, G.

2010-05-01

45

Sub-5-pm linewidth, 130-nm-tuning of a coupled-cavity Ti:sapphire oscillator via volume Bragg grating-based feedback  

NASA Astrophysics Data System (ADS)

A novel coupled-cavity Ti:sapphire oscillator architecture featuring a volume Bragg grating as a feedback element is presented. The oscillator provides continuous wave lasing within a spectral linewidth as narrow as 5 pm. The output can be wavelength-tuned over an ultrabroad spectral range of 130 nm, extending from 714 to 842 nm. This unique combination of narrow spectral linewidth and wide tuning range makes the laser suitable for applications such as sensing and Raman and absorption spectroscopy. The laser also displays ideal TEM00 mode operation throughout its tuning range with output powers beyond 300 mW. Detailed studies of the cw lasing dynamics across the wide tuning range are described. The general architecture of this design can be implemented for high resolution tuning across the broad spectral emission bands of other solid state lasers with single mode operation.

Hemmer, M.; Joly, Y.; Glebov, L.; Bass, M.; Richardson, M.

2012-03-01

46

Radiation Characteristics of a 0.11 Micrometer Modified Commercial CMOS Process  

NASA Technical Reports Server (NTRS)

We present radiation data, Total Ionizing Dose and Single Event Effects, on the LSI Logic 0.11 micron commercial process and two modified versions of this process. Modified versions include a buried layer to guarantee Single Event Latchup immunity.

Poivey, Christian; Kim, Hak; Berg, Melanie D.; Forney, Jim; Seidleck, Christina; Vilchis, Miguel A.; Phan, Anthony; Irwin, Tim; LaBel, Kenneth A.; Saigusa, Rajan K.; Mirabedini, Mohammad R.; Finlinson, Rick; Suvkhanov, Agajan; Hornback, Verne; Sung, Jun; Tung, Jeffrey

2006-01-01

47

An Offset Compensated Sampled-Data CMOS Comparator Circuit for Low-Power Implantable Biosensor Applications  

Microsoft Academic Search

This paper proposes a new low-voltage high resolution complementary metal oxide semiconductor (CMOS) comparator circuit suitable\\u000a for biosensor applications. The comparator compensates for differential input offset through single-ended sampled-data preamplification.\\u000a Simulations were carried out using a 130 nm IBM CMOS (CMRF8SF) process technology. Monte Carlo simulations incorporating mismatch\\u000a between devices (based on width and length of devices) indicate that the design

2008-01-01

48

Radiation tolerant circuits designed in 2 commercial 0.25{micro} CMOS processes  

SciTech Connect

Characterization of simple devices as well as complex circuits, in two commercial 0.25{micro} processes, demonstrates a high level (up to 58 Mrad) radiation tolerance of these technologies. They are also very likely to be immune to single event gate damage according to the results from 200 MeV-protons irradiation.

Mekkaoui, A. [and others

2001-03-08

49

Photodissociation dynamics of N2O at 130 nm: the N2(A 3Sigmau +,B 3Pig)+O(3PJ = 2,1,0) channels.  

PubMed

Oxygen Rydberg time-of-flight spectroscopy was used to study the vacuum ultraviolet photodissociation dynamics of N(2)O near 130 nm. The O((3)P(J)) products were tagged by excitation to high-n Rydberg levels and subsequently field ionized at a detector. In agreement with previous work, we find that O((3)P(J)) formation following excitation to the repulsive N(2)O D((1)Sigma(+)) state produces the first two electronically excited states of the N(2) counterfragment, N(2)(A (3)Sigma(u) (+)) and N(2)(B (3)Pi(g)). The O((3)P(J)) translational energy distribution reveals that the overall branching ratio between N(2)(A (3)Sigma(u) (+)) and N(2)(B (3)Pi(g)) formation is approximately 1.0:1.0 for J = 1 and 2, with slightly less N(2)(B (3)Pi(g)) produced in coincidence with O((3)P(0)). The angular distributions were found to be independent of J and highly anisotropic, with beta = 1.5+/-0.2. PMID:15910028

Witinski, Mark F; Ortiz-Suárez, Marivi; Davis, H Floyd

2005-05-01

50

DEVELOPMENT OF CMOS ACTIVE PIXEL IMAGE SENSORS FOR LOW COST COMMERCIAL APPLICATIONS  

Microsoft Academic Search

The Jet Propulsion Laboratory, under sponsorship from the NASA Oflice of Advanced Cmeepts and Technology, has been developing a second-generat ion scdid-state image sensor technology. Charge-coupled devices (CCDS) are a well-establish ed first generation image sensor technology. For both commercial and NASA applications, CCDS have numerous short comings. In response, the active phcl sensor (APS) technology has been under research,

Russell C. Gee; Sabrina E. Kcmcny; Quicsup Kim; Junichi Nakamura; Robert H. Nixon; Monico A. Ortiz; Craig Staller; Zhimin Zhou; Eric R Fossum

2004-01-01

51

Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications  

NASA Technical Reports Server (NTRS)

JPL, under sponsorship from the NASA Office of Advanced Concepts and Technology, has been developing a second-generation solid-state image sensor technology. Charge-coupled devices (CCD) are a well-established first generation image sensor technology. For both commercial and NASA applications, CCDs have numerous shortcomings. In response, the active pixel sensor (APS) technology has been under research. The major advantages of APS technology are the ability to integrate on-chip timing, control, signal-processing and analog-to-digital converter functions, reduced sensitivity to radiation effects, low power operation, and random access readout.

Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Staller, C.; Zhou, Z; Fossum, E.

1994-01-01

52

Enhancement-mode 130 nm InAs p-HEMTs having fT of 403 GHz and fmax of 470 GHz fabricated using atomic-layer-etching technology  

Microsoft Academic Search

High-performance 130 nm E-mode InAs p-HEMTs is fabricated using the Ne-based ALET and the buried Pt gate technology. Results from the combination of the improved gate-to-channel aspect ratio achieved by the buried Pt gate technology show that performance of the device is remarkable and the improved carrier transport property is achieved using the ALET technology.

T.-W. Kim; D.-H. Kim; S. D. Park; S. H. Shin; G. Y. Yeom; J. H. Jang; J.-I. Song

2008-01-01

53

CMOS technologies in the 100 nm range for rad-hard front-end electronics in future collider experiments  

NASA Astrophysics Data System (ADS)

130 nm and 90 nm CMOS processes are going to be used in the design of mixed-signal integrated circuits for the readout of detectors in the future generation of HEP experiments. In applications such as inner SLHC detectors, these ultra-deep submicron systems will have to stand total doses of ionizing radiation of the order of 100 Mrad and beyond. While the scaling of the gate oxide thickness to about 2 nm gives a high degree of radiation tolerance, issues such as the gate tunneling current and the sidewall leakage associated to lateral isolation oxides must be investigated. This paper provides an analysis of an extensive set of irradiation tests carried out on 130 and 90 nm CMOS transistors belonging to commercial technologies. With special focus on the design of analog front-end circuits for silicon pixel and strip detectors, the impact of ionizing radiation on the noise performance is evaluated and the underlying physical degradation mechanisms are pointed out to provide criteria for improving radiation hardness properties.

Re, Valerio; Gaioni, Luigi; Manghisoni, Massimo; Ratti, Lodovico; Speziali, Valeria; Traversi, Gianluca

2008-10-01

54

TID Effects in Deep N-Well CMOS Monolithic Active Pixel Sensors  

Microsoft Academic Search

This paper is devoted to the study of total ionizing dose effects in deep N-well (DNW) CMOS monolithic active pixel sensors (MAPS) for particle tracking fabricated in a STMicroelectronics 130 nm process. DNW-MAPS samples were exposed to gamma-rays up to a final dose of 1100 krad(SiO2) and then subjected to a 100degC annealing cycle. Ionizing radiation tolerance was tested by

Lodovico Ratti; Claudio Andreoli; Luigi Gaioni; Massimo Manghisoni; Enrico Pozzati; Valerio Re; Gianluca Traversi

2009-01-01

55

Single and two-stage OTAs for high-speed CMOS pipelined ADCs  

Microsoft Academic Search

This paper compares one- and two stage operational transconductance amplifiers (OTAs) to be used in an 8-bit high speed (440-MS\\/s) deep submicron CMOS (130nm) low voltage (1.2V) pipelined Analogue to Digital Converter (ADC) based on an 1.5-bit double sampling Multiplying Digital to Analogue Converter (MDAC). The main emphasis is put on the OTA DC- gain, gain-bandwidth (GBW), differential linear output

Tero Nieminen; Kari Halonen

2011-01-01

56

A Fully-Integrated Quad-Band GSM\\/GPRS CMOS Power Amplifier  

Microsoft Academic Search

Concentric distributed active transformers (DAT) are used to implement a fully-integrated quad-band power amplifier (PA) in a standard 130 nm CMOS process. The DAT enables the power amplifier to integrate the input and output matching networks on the same silicon die. The PA integrates on-chip closed- loop power control and operates under supply voltages from 2.9 V to 5.5 V

Ichiro Aoki; Scott Kee; Rahul Magoon; Roberto Aparicio; Florian Bohn; Jeff Zachan; Geoff Hatcher; Donald McClymont; Ali Hajimiri

2008-01-01

57

Schottky barrier diodes for millimeter wave detection in a foundry CMOS process  

Microsoft Academic Search

CoSi2-Si Schottky barrier diodes on an n-well and on a p-well\\/substrate are fabricated without a guard ring in a 130-nm foundry CMOS process. The nand p-type diodes with an area of 16×0.32×0.32 ?m2 achieve cutoff frequencies of ?1.5 and ?1.2 THz at 0-V bias, respectively. These are the highest cutoff frequencies for Schottky diodes fabricated in foundry silicon processes. The

Swaminathan Sankaran; Kenneth K. O

2005-01-01

58

CMOS IC Fabrication Issues for High-k Gate Dielectric and Alternate Electrode Materials  

Microsoft Academic Search

Silicon dioxide based dielectrics such as SiO2 and nitrided SiO 2 (SiON) are reaching the limit of their usefulness in complementary metal oxide semiconductor (CMOS) devices principally because of high tunnel currents. The semiconductor industry has adopted SiON at the 130 nm node where equivalent oxide thicknesses less than 2 nm are typically used for the high-performance devices. But SiON

L. Colombo; A. L. P. Rotondaro; M. R. Visokay; J. J. Chambers

59

A 1.2 V 300 ?W second-order switched-capacitor ?? modulator using ultra incomplete settling with 73 dB SNDR and 300 kHz BW in 130 nm CMOS  

Microsoft Academic Search

This paper presents a ?? modulator ( ?? ?? ?? ?? M) circuit based on the implementation of discrete time filters using ultra incomplete settling (UIS). This approach allows building a ?? M using mostly dynamic elements thus reducing the power dissipation. A prototyped 2 nd -order ?? ?? ?? ?? M circuit, using this technique, was designed in a

Blazej Nowacki; Nuno Paulino; Joao Goes

2011-01-01

60

Integrated tunable CMOS laser.  

PubMed

An integrated tunable CMOS laser for silicon photonics, operating at the C-band, and fabricated in a commercial CMOS foundry is presented. The III-V gain medium section is embedded in the silicon chip, and is hermetically sealed. The gain section is metal bonded to the silicon substrate creating low thermal resistance into the substrate and avoiding lattice mismatch problems. Optical characterization shows high performance in terms of side mode suppression ratio, relative intensity noise, and linewidth that is narrow enough for coherent communications. PMID:24514318

Creazzo, Timothy; Marchena, Elton; Krasulick, Stephen B; Yu, Paul K L; Van Orden, Derek; Spann, John Y; Blivin, Christopher C; He, Lina; Cai, Hong; Dallesasse, John M; Stone, Robert J; Mizrahi, Amit

2013-11-18

61

Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu\\/PECVD low-k BEOL  

Microsoft Academic Search

Integration and development of Cu Back-End of Line (BEOL) with PECVD low-k organosilicate glass (OSG, also called SiCOH, carbon-doped oxide, CDO, etc.) for 130 nm and 90 nm CMOS technologies has been reported by a number of institutions. Here we report on a Cu\\/SiCOH technology which has similarities, but also enhanced integration and reliability characteristics while preserving the R and

D. Edelstein; H. Rathore; C. Davis; L. Clevenger; A. Cowley; T. Nogami; B. Agarwala; S. Arai; A. Carbone; K. Chanda; F. Chen; S. Cohen; W. Cote; M. Cullinan; T. Dalton; S. Das; P. Davis; J. Demarest; D. Dunn; C. Dziobkowski; R. Filippi; J. Fitzsimmons; P. Flaitz; S. Gates; J. Gill; A. Grill; D. Hawken; K. Ida; D. Klaus; N. Klymko; J. Lee; W. Landers; W.-K. Li; Y.-H. Lin; E. Liniger; X.-H. Liu; A. Madan; S. Malhotra; J. Martin; S. Molis; C. Muzzy; D. Nguyen; S. Nguyen; M. Ono; C. Parks; D. Questad; D. Restaino; A. Sakamoto; T. Shaw; Y. Shimooka; A. Simon; E. Simonyi; A. Swift; T. Van Kleeck; S. Vogt; Y.-Y. Wang; W. Wille; J. Wright; C.-C. Yang; M. Yoon; T. Ivers

2004-01-01

62

Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker  

NASA Astrophysics Data System (ADS)

In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10-15?m in both coordinates, low material budget <1%X0, and the ability to withstand a background hit rate of several tens of MHz/cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.

Rizzo, G.; Comott, D.; Manghisoni, M.; Re, V.; Traversi, G.; Fabbri, L.; Gabrielli, A.; Giorgi, F.; Pellegrini, G.; Sbarra, C.; Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Berra, A.; Lietti, D.; Prest, M.; Bevan, A.; Wilson, F.; Beck, G.; Morris, J.; Gannaway, F.; Cenci, R.; Bombelli, L.; Citterio, M.; Coelli, S.; Fiorini, C.; Liberali, V.; Monti, M.; Nasri, B.; Neri, N.; Palombo, F.; Stabile, A.; Balestri, G.; Batignani, G.; Bernardelli, A.; Bettarini, S.; Bosi, F.; Casarosa, G.; Ceccanti, M.; Forti, F.; Giorgi, M. A.; Lusiani, A.; Mammini, P.; Morsani, F.; Oberhof, B.; Paoloni, E.; Perez, A.; Petragnani, G.; Profeti, A.; Soldani, A.; Walsh, J.; Chrzaszcz, M.; Gaioni, L.; Manazza, A.; Quartieri, E.; Ratti, L.; Zucca, S.; Alampi, G.; Cotto, G.; Gamba, D.; Zambito, S.; Dalla Betta, G.-F.; Fontana, G.; Pancheri, L.; Povoli, M.; Verzellesi, G.; Bomben, M.; Bosisio, L.; Cristaudo, P.; Lanceri, L.; Liberti, B.; Rashevskaya, I.; Stella, C.; Vitale, L.

2013-08-01

63

High-temperature Complementary Metal Oxide Semiconductors (CMOS)  

NASA Technical Reports Server (NTRS)

The results of an investigation into the possibility of using complementary metal oxide semiconductor (CMOS) technology for high temperature electronics are presented. A CMOS test chip was specifically developed as the test bed. This test chip incorporates CMOS transistors that have no gate protection diodes; these diodes are the major cause of leakage in commercial devices.

Mcbrayer, J. D.

1981-01-01

64

Front end electronics for silicon strip detectors in 90nm CMOS technology: advantages and challenges  

NASA Astrophysics Data System (ADS)

We present a 16 channel front end prototype implemented in 90nm CMOS IBM process and optimized for 5pF input capacitance. The primary motivation for this project is to study the usefulness of the CMOS technologies below 130nm for front end amplifiers optimized for short strip silicon detectors in Super Large Hadron Collider (SLHC) experiments [1]. In the presented design we show critical aspects of the front end stages implemented in the deep submicron technologies. Particular effort has been put into minimization of the power consumed by the front end electronics. The nominal power consumption providing Equivalent Noise Charge (ENC) level below 1000e- for the chip loaded with 5pF input capacitance is around 220?W per channel.

Kaplon, J.; Noy, M.

2010-11-01

65

A Novel Multilayer Aperture-Coupled Cavity Resonator for Millimeter-Wave CMOS RFICs  

Microsoft Academic Search

A novel millimeter-wave cavity resonator, completely compatible with commercial CMOS fabrication techniques, has been designed and fabricated in a 0.25-mum CMOS process and tested. The resonator employs a capacitively loaded cavity topology effectively implemented using the CMOS multimetal-layer and via-hole structure. The CMOS capacitively loaded cavity resonator, including two coupling apertures and microstrip feed lines, occupies an area of 2

Meng Miao; Cam Nguyen

2007-01-01

66

Graphene/Si CMOS Hybrid Hall Integrated Circuits.  

PubMed

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18?um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

67

Graphene/Si CMOS Hybrid Hall Integrated Circuits  

PubMed Central

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18?um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

68

A two-tier monolithically stacked CMOS Active Pixel Sensor to measure charged particle direction  

NASA Astrophysics Data System (ADS)

In this work we present an innovative approach to particle tracking based on CMOS Active Pixel Sensors (APS) layers, monolithically integrated in an all-in-one chip featuring multiple, stacked, fully functional detector layers capable to provide momentum measurement (particle direction) within a single detector by using multiple layer impact point coordinates. The whole system will results in a very low material detector, since each layer can be thinned down to tens of micrometres, thus dramatically reducing multiple scattering issues. To build such a detector, we rely on the capabilities of the CMOS vertical scale integration (3D-IC) 130 nm Chartered/Tezzaron technology, used to integrate two fully-functional CMOS APS matrix detectors, including both sensing area and control/signal elaboration circuitry, stacked in a monolithic device by means of Through Silicon Via (TSV) connections. Such a detector would allow accurate estimation of the impact point of an ionizing particle and of its incidence angle. Two batches of the first chip prototype have been produced and characterized using particle beams (e.g. protons) demonstrating the suitability of particle direction measurement with a single, multiple layers, 3D vertically stacked APS CMOS detector.

Passeri, D.; Servoli, L.; Meroli, S.; Magalotti, D.; Placidi, P.; Marras, A.

2014-05-01

69

65-nm CMOS Monolithically Integrated Subterahertz Transmitter  

Microsoft Academic Search

This letter presents a transmitter for subterahertz ra- diation (up to 160 GHz), which consists of a nonlinear transmission line (NLTL) and an extremely wideband (EWB) slot antenna on a silicon substrate of low resistivity (10 ? · cm). The fabrication was realized using a commercially available 65-nm CMOS pro- cess. On-wafer characterization of the whole transmitter, of the stand-alone

Xin Hu; Lorenzo Tripodi; Marion K. Matters-Kammerer; Shi Cheng; Anders Rydberg

2011-01-01

70

CMOS image sensors  

Microsoft Academic Search

In this article, we provide a basic introduction to CMOS image-sensor technology, design and performance limits and present recent developments and future directions in this area. We also discuss image-sensor operation and describe the most popular CMOS image-sensor architectures. We note the main non-idealities that limit CMOS image sensor performance, and specify several key performance measures. One of the most

A. El Gamal; H. Eltoukhy

2005-01-01

71

CMOS Imaging Detectors as X-ray Detectors for Synchrotron Radiation Experiments  

Microsoft Academic Search

CMOS imagers are matrix-addressed photodiode arrays, which have been utilized in devices such as commercially available digital cameras. The pixel size of CMOS imagers is usually larger than that of CCD and smaller than that of TFT, giving them a unique position. Although CMOS x-ray imaging devices have already become commercially available, they have not been used as an x-ray

Naoto Yagi; Masaki Yamamoto; Kentaro Uesugi; Katsuaki Inoue

2004-01-01

72

3D monolithically stacked CMOS active pixel sensor detectors for particle tracking applications  

NASA Astrophysics Data System (ADS)

In this work we propose an innovative approach to particle tracking based on CMOS Active Pixel Sensors layers, monolithically integrated in an all-in-one chip featuring multiple, stacked, fully functional detector layers capable to provide momentum measurement (particle impact point and direction) within a single detector. This will results in a very low material detector, thus dramatically reducing multiple scattering issues. To this purpose, we rely on the capabilities of the CMOS vertical scale integration (3D IC) technology. A first chip prototype has been fabricated within a multi-project run using a 130 nm CMOS Chartered/Tezzaron technology, featuring two layers bonded face-to-face. Tests have been carried out on full 3D structures, providing the functionalities of both tiers. To this purpose, laser scans have been carried out using highly focussed spot size obtaining coincidence responses of the two layers. Tests have been made as well with X-ray sources in order to calibrate the response of the sensor. Encouraging results have been found, fostering the suitability of both the adopted 3D-IC vertical scale fabrication technology and the proposed approach for particle tracking applications.

Passeri, D.; Servoli, L.; Meroli, S.; Magalotti, D.; Placidi, P.; Marras, A.

2012-08-01

73

The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector  

NASA Astrophysics Data System (ADS)

This work presents the characterization of Deep N-well (DNW) active pixel sensors fabricated in a vertically integrated technology. The DNW approach takes advantage of the triple well structure to lay out a sensor with relatively large charge collecting area (as compared to standard three transistor MAPS), while the readout is performed by a classical signal processing chain for capacitive detectors. This new 3D design relies upon stacking two homogeneous tiers fabricated in a 130 nm CMOS process where the top tier is thinned down to about 12?m to expose through silicon vias (TSV), therefore making connection to the buried circuits possible. This technology has been used to design a fine pitch 3D CMOS sensor with sparsification capabilities, in view of vertexing applications to the International Linear Collider (ILC) experiments. Results from the characterization of different kind of test structures, including single pixels, 3×3 and 8×8 matrices, are presented.

Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.

2013-12-01

74

Stacked CMOS SRAM cell  

NASA Astrophysics Data System (ADS)

A static random access memory (SRAM) cell with cross-coupled stacked CMOS inverters is demonstrated for the first time. In this approach, CMOS inverters are fabricated with a laser recrystallized p-channel device stacked on top of and sharing the gate with a bulk n-channel device using a modified two-polysilicon n-MOS process. The memory cell has been exercised through the write and read cycles with external signal generators while the output is buffered by an on-chip, stacked-CMOS-inverter-based amplifier.

Chen, C.-E.; Lam, H. W.; Malhi, S. D. S.; Pinizzotto, R. F.

1983-08-01

75

CMOS active pixel image sensors for highly integrated imaging systems  

Microsoft Academic Search

A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-?m CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression

Sunetra K. Mendis; Sabrina E. Kemeny; Russell C. Gee; Bedabrata Pain; Craig O. Staller; Quiesup Kim; Eric R. Fossum

1997-01-01

76

A low-cost uncooled infrared microbolometer detector in standard CMOS technology  

Microsoft Academic Search

This paper reports the development of a low-cost uncooled infrared microbolometer detector using a commercial 0.8 ?m CMOS process, where the CMOS n-well layer is used as the infrared sensitive material. The n-well is suspended by front-end bulk-micromachining of the fabricated CMOS dies using electrochemical etch-stop technique in TMAH. Since this approach does not require any lithography or infrared sensitive

Deniz Sabuncuoglu Tezcan; Selim Eminoglu; Tayfun Akin

2003-01-01

77

Compact CMOS multispectral/polarimetric camera  

NASA Astrophysics Data System (ADS)

A novel, compact visible multispectral, polarimetric camera is under development. The prototype is capable of megapixel imaging with sixteen wavebands and three polarimetric images. The entire system encompasses a volume less than 125mm x 100mm x 75mm. The system is based on commercial megapixel class CMOS sensors and incorporates real time processing of hyperspectral cube data using a proprietary processor system based on state of the art FPGA technology.

Catanzaro, Brian; Lorenz, Jim; Dombrowski, Mark

2006-06-01

78

CMOS-integrated stress sensor systems  

Microsoft Academic Search

Sensor systems based on piezoresistors have found a wide variety of applications whenever mechanical stress due to external mechanical input is to be determined. Such sensor elements are fabricated using commercial CMOS processes enabling the realization of highly integrated systems with electronics for signal amplification and multiplexing. They combine stress-sensing elements such as Wheatstone bridges, 4- and 8-terminal well-based devices,

P. Ruther; M. Baumann; P. Gieschke; M. Herrmann; B. Lemke; K. Seidl; O. Paul

2010-01-01

79

CMOS\\/BiCMOS power amplifier technology trend in Japan  

Microsoft Academic Search

Aiming for 2-5GHz band transceiver system on a chip, the integration of RF section has been developed by using conventional CMOS\\/BiCMOS (SiGeCMOS) process. The attempts to integrate power amplifiers (PA's) have been successful for low transmit power system such as Bluetooth, but these attempts are very limited due to the poor power handling capability of FET's in CMOS and the

Noriharu Suematsu; Shintaro Shinjo

2001-01-01

80

All-CMOS night vision viewer with integrated microdisplay  

NASA Astrophysics Data System (ADS)

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 ?m CMOS process, with no process alterations or post processing. The display features a 25 ?m pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

2014-02-01

81

Electronics and photonics convergence on Si CMOS platform  

NASA Astrophysics Data System (ADS)

The present paper describes Si microphotonics and its current status of electronics and photonics convergence on Si platform based on monolithic integration using CMOS (Complementary Metal Oxide Semiconductor) technologies. The Si CMOS platform is advantageous over III-V semiconductor based platform because of a short time-lag between basic research and commercialization in terms of the standardized materials and processes. To implement photonic devices on the Si CMOS platform, it is important to reduce materials diversity in current photonics devices. Low loss SiNx waveguides with sharp bends, high performance strained Ge photodetectors for C+L band, and demultiplexer/multiplexer for WDM (wavelength division multiplexing) have been successfully implemented on the Si CMOS platform. The current targets are cost-effective OADMs (optical add-drop multiplexers) for optical communication and optical clocking for Si LSIs beyond Cu-low k technologies.

Wada, Kazumi

2004-07-01

82

High-speed multicolour photometry with CMOS cameras  

NASA Astrophysics Data System (ADS)

We present the results of testing the commercial digital camera Nikon D90 with a CMOS sensor for high-speed photometry with a small telescope Celestron 11'' at the Peak Terskol Observatory. CMOS sensor allows to perform photometry in 3 filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system of CMOS sensors is close to the Johnson BVR system. The results of testing show that one can carry out photometric measurements with CMOS cameras for stars with the V-magnitude up to ?14^{m} with the precision of 0.01^{m}. Stars with the V-magnitude up to ˜10 can be shot at 24 frames per second in the video mode.

Pokhvala, S. M.; Zhilyaev, B. E.; Reshetnyk, V. M.

2012-11-01

83

High reliability HV-CMOS transistors in standard CMOS technology  

Microsoft Academic Search

A novel high-reliability HV-CMOS (High Voltage CMOS) compatible with 0.6?m rules standard Bulk-Silicon (BS) CMOS process was proposed. The reliability of the HV-CMOS is greatly improved by adding the p-well to HV-PMOS (High Voltage PMOS) for etching the unwanted thick-gate-oxide film and that to HV-DNMOS (High Voltage Double-Diffusion NMOS) for preventing punch-through. The breakdown voltage of the presented HV-CMOS exceeds

W. F. Sun; L. X. Shi

2003-01-01

84

CMOS Process Monitor  

NASA Astrophysics Data System (ADS)

A CMOS Process Monitor, consisting of eight basic test structures, has been prepared to acquire key CMOS parameters to assist in VLSI wafer acceptance. The test structures can be probed using a 2 by N probe pad array and can be arranged to fit into either the interior or the scribe lane of an integrated circuit chip. In order to facilitate the general use of the monitor, a document is being prepared that describes its design, layout, measurement, and analysis. This paper describes the structures included in the monitor, the methodology used to create the monitor, and test results from the monitor.

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Jenings, G. A.; Hicks, K. A.

1988-02-01

85

Integrated Cmos Linear Dosimeter  

Microsoft Academic Search

This paper presents a review of radiation sensors; their basic principles and a possible use as built-in sensors in Integrated Circuits exposed to ionizing radiation. Two radiation dosimeters are discussed: threshold and linear. All are CMOS circuits compatible with standard technology using pMOSFET sensors. An integrated dosimetry system including microprocessor interface for remote monitoring is described.

O. Calvo; M. González; C. Romero; E. García-Moreno; E. Isern; M. Roca; J. Segura

1998-01-01

86

CMOS Bridging Fault Detection  

Microsoft Academic Search

The authors compare the performance of two test generation techniques, stuck fault testing and current testing, when applied to CMOS bridging faults. Accurate simulation of such faults mandated the development of several new design automation tools, including an analog-digital fault simulator. The results of this simulation are analyzed. It is shown that stuck fault test generation, while inherently incapable of

Thomas M. Storey; Wojciech Maly

1990-01-01

87

Smart 45nm Foundry CMOS with Mask-Lite (trademark) Reduced Mask Costs.  

National Technical Information Service (NTIS)

American Semiconductor has created Mask-Lite which is a layout and fabrication strategy that reduces mask costs and improves access to advanced 45nm bulk CMOS from their ITAR registered and TRUSTED ready on-shore commercial foundry.

D. G. Wilson K. Hebert R. L. Chaney S. D. Hackler

2011-01-01

88

Surface enhanced biodetection on a CMOS biosensor chip  

NASA Astrophysics Data System (ADS)

We present a rigorous electromagnetic theory of the electromagnetic power emitted by a dipole located in the vicinity of a multilayer stack. We applied this formalism to a luminescent molecule attached to a CMOS photodiode surface and report light collection efficiency larger than 80% toward the CMOS silicon substrate. We applied this result to the development of a low-cost, simple, portable device based on CMOS photodiodes technology for the detection and quantification of biological targets through light detection, presenting high sensitivity, multiplex ability, and fast data processing. The key feature of our approach is to perform the analytical test directly on the CMOS sensor surface, improving dramatically the optical detection of the molecule emitted light into the high refractive index semiconductor CMOS material. Based on adequate surface chemistry modifications, probe spotting and micro-fluidics, we performed proof-of-concept bio-assays directed against typical immuno-markers (TNF-? and IFN-?). We compared the developed CMOS chip with a commercial micro-plate reader and found similar intrinsic sensitivities in the pg/ml range.

Belloni, Federico; Sandeau, Laure; Contié, Sylvain; Vicaire, Florence; Owens, Roisin; Rigneault, Hervé

2012-02-01

89

CMOS magnetic sensor arrays  

Microsoft Academic Search

The design of a monolithic 64×64-element array of magnetic sensors, which is implemented in a standard 3-?m CMOS process, is described. The individual magnetic field sensors are split-drain MAGFETS. A split-drain MAGFET is a field-effect transistor that has one source, one gate, and two drains. When current is flowing in the FET in the absence of a magnetic field, both

James J. Clark

1988-01-01

90

Monolithic multiple axis accelerometer design in standard CMOS  

NASA Astrophysics Data System (ADS)

Using a single maskless postprocessing step we have developed an accelerometer in a standard commercial CMOS process capable of a sensitive axis parallel or perpendicular to the die surface. Out postprocess is realized using xenon difluoride (XeF2) as a bulk etchant. The combination of this etchant and the standard CMOS process allows realization of cantilevers with piezoresistive sensors in all spacial coordinates from a widely-accessible source and at a minimal cost. Fabrication of accelerometers for all three axes and associated electronics on a single piece of silicon reduces the cost of 3D acceleration detection while increasing sensor reliability.

Warneke, Brett; Hoffman, Eric G.; Pister, Kristofer S. J.

1995-09-01

91

Large area CMOS image sensors  

Microsoft Academic Search

CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to

R. Turchetta; N. Guerrini; I. Sedgwick

2011-01-01

92

Review of CMOS image sensors  

Microsoft Academic Search

The role of CMOS Image Sensors since their birth around the 1960s, has been changing a lot. Unlike the past, current CMOS Image Sensors are becoming competitive with regard to Charged Couple Device (CCD) technology. They offer many advantages with respect to CCD, such as lower power consumption, lower voltage operation, on-chip functionality and lower cost. Nevertheless, they are still

M. Bigas; Enric Cabruja; Josep Forest; Joaquim Salvi

2006-01-01

93

Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.  

SciTech Connect

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materials integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.

Sumant, A.V.; Auciello, O.; Yuan, H.-C; Ma, Z.; Carpick, R. W.; Mancini, D. C.; Univ. of Wisconsin; Univ. of Pennsylvania

2009-05-01

94

Hybrid CMOS / Microfluidic Systems for Cell Manipulation with Dielectrophoresis  

NASA Astrophysics Data System (ADS)

A hybrid CMOS/microfluidic chip combines the biocompatibility of microfluidics with the built-in logic, programmability, and sensitivity of CMOS integrated circuits (ICs)^1 We have designed a CMOS IC for moving individual cells using dielectrophoresis (DEP). The IC was built in a commercial foundry and we subsequently fabricated a microfluidic chamber on the top surface. The chip consists of a 1.4 by 2.8mm array of over 32,000 individually addressable 11x11 micron pixels. An RF voltage of 5V at 10MHz can be applied to each pixel with respect to the conductive lid of the microfluidic chamber, producing a localized electric field that can trap a cell. By shifting the location of energized pixels, the array can trap and move cells along programmable paths through the microfluidic chamber. We show the design, fabrication, and testing of the hybrid chip. Bringing together the biocompatibility of microfluidics and the power of CMOS chips, hybrid CMOS / microfluidic systems are an exciting technology for biomedical research. Thanks to NSEC NSF grant PHY-0117795 and the NCI MIT-Harvard CCNE. [1] H Lee, Y Liu, RM Westervelt, D Ham, IEEE JSSC 41, 6, pp. 1471-1480, 2006

Hunt, Tom; Issadore, David; Westervelt, Robert M.

2007-03-01

95

Low-light hyperspectral imager for characterization of biological samples based on an sCMOS image sensor  

NASA Astrophysics Data System (ADS)

The new "scientific CMOS" (sCMOS) sensor technology has been tested for use in hyperspectral imaging. The sCMOS offers extremely low readout noise combined with high resolution and high speed, making it attractive for hyperspectral imaging applications. A commercial HySpex hyperspectral camera has been modified to be used in low light conditions integrating an sCMOS sensor array. Initial tests of fluorescence imaging in challenging light settings have been performed. The imaged objects are layered phantoms labelled with controlled location and concentration of fluorophore. The camera has been compared to a state of the art spectral imager based on CCD technology. The image quality of the sCMOS-based camera suffers from artifacts due to a high density of pixels with excessive noise, attributed to the high operating temperature of the array. Image processing results illustrate some of the benefits and challenges of the new sCMOS technology.

Hernandez-Palacios, J.; Randeberg, L. L.; Haug, I. J.; Baarstad, I.; Løke, T.; Skauli, T.

2011-02-01

96

A Single-Chip 8-Band CMOS Transceiver for 3G Cellular Systems with Digital Interface  

NASA Astrophysics Data System (ADS)

In this paper, a single-chip dual-mode 8-band 130nm CMOS transceiver including A/D/A converters and digital filters with 312MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.

Yoshida, Hiroshi; Toyoda, Takehiko; Tsurumi, Hiroshi; Itoh, Nobuyuki

97

Transistor sizing in CMOS circuits  

Microsoft Academic Search

The problem of optimally sizing transistors in a VLSI CMOS circuit is considered. Models and algorithms for performing optimization on a single path using RC-tree approximation are presented. The results of an automatic optimization procedure are discussed.

Mehmet A. Cirit

1987-01-01

98

CMOS array design automation techniques  

NASA Technical Reports Server (NTRS)

The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

Lombardi, T.; Feller, A.

1976-01-01

99

An improved standard total dose test for CMOS space electronics  

SciTech Connect

The postirradiation response of hardened and commercial CMOS devices is investigated as a function of total dose, dose rate, and annealing time and temperature. Cobalt-60 irradiation at {approx equal} 200 rad(SiO{sub 2})/s followed by a 1-week 100{degrees}C biased anneal and testing is shown to be an effective screen of hardened devices for space use. However, a similar screen and single-point test performed after Co-60 irradiation and elevated temperature anneal cannot be generally defined for commercial devices. In the absence of detailed knowledge about device and circuit radiation response, a two-point standard test is proposed to ensure space surviability of CMOS circuits: a Co-60 irradiation and test to screen against oxide-trapped charge related failures, and an additional rebound test to screen against interface-trap related failures. Testing implications for bipolar technologies are also discussed.

Fleetwood, D.M.; Winokur, P.S.; Riewe, L.C. (Sandia National Lab., Albuquerque, NM (US)); Pease, R.L. (Mission Research Corp., Albuquerque, NM (US))

1989-12-01

100

CMOS foundry implementation of Schottky diodes for RF detection  

Microsoft Academic Search

Schottky diodes for RF power measurement were designed and fabricated using a commercial n-well CMOS foundry process through the MOSIS service. The Schottky diodes are implemented by modifying the SCMOS technology file of the public-domain graphics layout editor, MAGIC, or by explicitly implementing the appropriate CIF layers. The modifications allow direct contact of first-layer metal to the low-doped substrate. Current-voltage

Veljko MilanoviC; Michael Gaitan; Janet C. Marshall; Mona E. Zaghloul

1996-01-01

101

CMOS Gate Array Implementation of the SPARC Architecture  

Microsoft Academic Search

A description is given of the MB86900 processor, the first implementation of Sun Microsystems' Scalable Processor Architecture (SPARC). MB86900, referred to here as the integer unit (IU), is a high-performance microprocessor designed with high-speed CMOS gate-array technology. In a typical system, the MB86900 IU works with a companion floating-point controller chip (the MB86910), two commercial floating-point arithmetic processors, and a

Masood Namjoo; Anant Agrawal; Donald Clark Jackson; Lesley Quach

1988-01-01

102

Photon Counting Imager using CMOS Compatible Photodetectors  

Microsoft Academic Search

This work describes a CMOS compatible photodetector purposed for a photon counting imager. Several structures have been designed and implemented using standard industrial CMOS technology. First test results are presented in this paper.

Ville Nieminen; Juha Kostamovaara; Anssi Mäkynen

2006-01-01

103

Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators  

PubMed Central

This work presents a thermoelectric micro generator fabricated by the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 ?V at the temperature difference of 1 K.

Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

2010-01-01

104

Multiemitter BiCMOS logic circuit family  

Microsoft Academic Search

A new multiemitter BiCMOS circuit using half-micrometer BiCMOS technology with a 3.6-V supply provides 85 % improvement in delay over CMOS design and 40 % improvement over conventional BiCMOS. This benefit is demonstrated in a 64-b carry look-ahead adder where most of the gates have a high number of inputs. A complete logic circuit family based on the multiemitter (ME)

Gerard Boudon; Pierre Mollier; Ieng Ong; Jean-Paul Nuez; Daniel Mauchauffee; Dominique Plassat; Jean-Louis Simonet; Frank Wallart

1991-01-01

105

Single Photon CMOS Imaging Through Noise Minimization  

Microsoft Academic Search

\\u000a This chapter presents the theory and circuitry necessary to build CMOS image sensors with single photon detection capability.\\u000a The chapter begins with the basic theory of CMOS image sensor photon detection. Then a discussion about additive noise systems\\u000a and the sources of noise in CMOS image sensors is presented. Signal amplification and bandwidth control in low-noise CMOS\\u000a image sensors are

Boyd Fowler

106

Ge technology beyond Si CMOS  

NASA Astrophysics Data System (ADS)

To save energy, low voltage operation is the most important criterion for CMOS ICs. To reach this goal, high mobility new channel materials are required for CMOS ICs at <= 14 nm technology nodes. The high electron mobility InGaAs nMOSFET and high hole mobility Ge pMOSFET were proposed for CMOS at 0.5 V operation, since the poor hole mobility of InGaAs makes it unsuitable for all InGaAs CMOS. However, the epitaxial InGaAs nMOSFET on Si faces fundamental material challenges with large defects and high leakage current. Although dislocation-defects-free Ge-on-Insulator (GeOI), ultra-thin-body (UTB) InGaAs IIIV-on-Insulator (IIIVOI), and selective GeOI on Si were pioneered by us, it is still difficult to reach InGaAs-nMOS/Ge-pMOS CMOS targeting to <= 14 nm CMOS. In contrast, Ge is the ideal candidate for all Ge CMOS logic due to both higher electron and hole mobility than Si. Significantly higher (2.6X) hole mobility of GeOI pMOSFET than universal SiO2/Si value was reached at a medium 0.5 MV/cm effective electric field (Eejf) and 1.4 nm equivalent-oxide-thickness (EOT). Nevertheless, the Ge nMOSFET suffers from large EOT and fast mobility degradation with increasing Eeff, due to the surface Fermi-level pinning to valance band, poor high-?/Ge interface and low dopant activation. Using novel laser annealing and proper gate stack, small EOT of 0.95 nm, small sub-threshold swing of 106 mV/dec, and 40% better high-field mobility than universal SiO2/Si data were achieved in Ge nMOSFET. Such all-Ge CMOS has irreplaceable merits of much simpler process, lower cost, and potentially higher yield than the InGaAs-nMOS/Ge-pMOS CMOS platform.

Chin, Albert

2012-12-01

107

CMOS Integrated Carbon Nanotube Sensor  

SciTech Connect

Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A. [Grupo MEMS, Comision Nacional de Energia Atomica, Buenos Aires (Argentina); Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S. [Dpto. de Ing. Electrica y de Computadoras, Universidad Nacional del Sur, Bahia Blanca (Argentina); Buffa, F. A. [INTEMA Facultad de Ingenieria, Universidad Nacional de Mar del Plata, Mar del Plata (Argentina)

2009-05-23

108

Hybrid CMOS SiPIN detectors as astronomical imagers  

NASA Astrophysics Data System (ADS)

Charge Coupled Devices (CCDs) have dominated optical and x-ray astronomy since their inception in 1969. Only recently, through improvements in design and fabrication methods, have imagers that use Complimentary Metal Oxide Semiconductor (CMOS) technology gained ground on CCDs in scientific imaging. We are now in the midst of an era where astronomers might begin to design optical telescope cameras that employ CMOS imagers. The first three chapters of this dissertation are primarily composed of introductory material. In them, we discuss the potential advantages that CMOS imagers offer over CCDs in astronomical applications. We compare the two technologies in terms of the standard metrics used to evaluate and compare scientific imagers: dark current, read noise, linearity, etc. We also discuss novel features of CMOS devices and the benefits they offer to astronomy. In particular, we focus on a specific kind of hybrid CMOS sensor that uses Silicon PIN photodiodes to detect optical light in order to overcome deficiencies of commercial CMOS sensors. The remaining four chapters focus on a specific type of hybrid CMOS Silicon PIN sensor: the Teledyne Hybrid Visible Silicon PIN Imager (HyViSI). In chapters four and five, results from testing HyViSI detectors in the laboratory and at the Kitt Peak 2.1m telescope are presented. We present our laboratory measurements of the standard detector metrics for a number of HyViSI devices, ranging from 1k×1k to 4k×4k format. We also include a description of the SIDECAR readout circuit that was used to control the detectors. We then show how they performed at the telescope in terms of photometry, astrometry, variability measurement, and telescope focusing and guiding. Lastly, in the final two chapters we present results on detector artifacts such as pixel crosstalk, electronic crosstalk, and image persistence. One form of pixel crosstalk that has not been discussed elsewhere in the literature, which we refer to as Interpixel Charge Transfer (IPCT), is introduced. This effect has an extremely significant impact on x-ray astronomy. For persistence, a new theory and accompanying simulations are presented to explain latent images in the HyViSI. In consideration of these artifacts and the overall measured performance, we argue that HyViSI sensors are ready for application in certain regimes of astronomy, such as telescope guiding, measurements of fast planetary transits, and x-ray imaging, but not for others, such as deep field imaging and large focal plane astronomical surveys.

Simms, Lance Michael

109

A back-illuminated megapixel CMOS image sensor  

NASA Technical Reports Server (NTRS)

In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

2005-01-01

110

Low Power CMOS Digital Design  

Microsoft Academic Search

: Motivated by emerging battery operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit and technology optimizations. An architectural based scaling strategy is presented which

Anantha P. Chandrakasan; Samuel Sheng; Robert W. Brodersen

1995-01-01

111

Single Photon Imaging in CMOS  

Microsoft Academic Search

CMOS single photon detectors enable large pixel arrays and integrated ancillary circuits. As a consequence, higher timing accuracy and reduced power consumption can be achieved at lower costs. This paper discusses applications and implementation considerations to take into account when designing single photon imagers

Edoardo Charbon

2006-01-01

112

A CMOS enhanced solid-state nanopore based single molecule detection platform.  

PubMed

Solid-state nanopores have emerged as a single molecule label-free electronic detection platform. Existing transimpedance stages used to measure ionic current nanopores suffer from dynamic range limitations resulting from steady-state baseline currents. We propose a digitally-assisted baseline cancellation CMOS platform that circumvents this issue. Since baseline cancellation is a form of auto-zeroing, the 1/f noise of the system is also reduced. Our proposed design can tolerate a steady state baseline current of 10µA and has a usable bandwidth of 750kHz. Quantitative DNA translocation experiments on 5kbp DNA was performed using a 5nm silicon nitride pore using both the CMOS platform and a commercial system. Comparison of event-count histograms show that the CMOS platform clearly outperforms the commercial system, allowing for unambiguous interpretation of the data. PMID:24109650

Chen, Chinhsuan; Yemenicioglu, Sukru; Uddin, Ashfaque; Corgliano, Ellie; Theogarajan, Luke

2013-01-01

113

Development of a portable digital radiographic system based on FOP-coupled CMOS image sensor and its performance evaluation  

Microsoft Academic Search

As a continuation of our digital X-ray imaging sensor R&D, we have developed a cost-effective, portable, digital radiographic system based on a CMOS image sensor coupled with a fiber optic plate (FOP) and selected conventional scintillators. The imaging system consists of a commercially available CMOS image sensor of 48 ?m × 48 ?m pixel size and 49.2 mm × 49.3

H. S. Cho; M. H. Jeong; B. S. Han; S. Kim; B. S. Lee; H. K. Kim; S. C. Lee

2005-01-01

114

A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass  

PubMed Central

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 ?m CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 ?m CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

115

Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units  

SciTech Connect

One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing. In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.

Smith, J.H.; Ellis, J.R.; Montague, S.; Allen, J.J.

1997-03-01

116

Dissection of c-MOS degron  

PubMed Central

c-MOS, a MAP kinase kinase kinase, is a regulator of oocyte maturation. The concentration of c-MOS is controlled in part through its conditional degradation. Previous studies proposed the ‘second-codon rule’, according to which the N-terminal proline (Pro) of c-MOS is a destabilizing residue that targets c-MOS for degradation. We analyzed the degradation signal (degron) of c-MOS in Xenopus oocytes, found it to be a portable degron, and demonstrated that, contrary to the model above, the N-terminal Pro residue of c-MOS is entirely dispensable for its degradation if Ser-2 (encoded Ser-3) of c-MOS is replaced by a small non-phosphorylatable residue such as Gly. The dependence of c-MOS degradation on N-terminal Pro is shown to be caused by a Pro-mediated downregulation of the net phosphorylation of Ser-2, a modification that halts c-MOS degradation in oocytes. Thus, the N-terminal Pro residue of c-MOS is not a recognition determinant for a ubiquitin ligase, in agreement with earlier evidence that Pro is a stabilizing residue in the N-end rule.

Sheng, Jun; Kumagai, Akiko; Dunphy, William G.; Varshavsky, Alexander

2002-01-01

117

Latest results of the R&D on CMOS MAPS for the Layer0 of the SuperB SVT  

NASA Astrophysics Data System (ADS)

Physics and high background conditions set very challenging requirements on readout speed, material budget and resolution for the innermost layer of the SuperB Silicon Vertex Tracker operated at the full luminosity. Monolithic Active Pixel Sensors (MAPS) are very appealing in this application since the thin sensitive region allows grinding the substrate to tens of microns. Deep N-Well MAPS, developed in the ST 130 nm CMOS technology, achieved in-pixel sparsification and fast time stamping. Further improvements are being explored with an intense R&D program, including both vertical integration and 2D MAPS with the INMAPS quadruple well. We present the results of the characterization with IR laser, radioactive sources and beam of several chips produced with the 3D (Chartered/Tezzaron) process. We have also studied prototypes exploiting the features of the quadruple well and the high resistivity epitaxial layer of the INMAPS 180 nm process. Promising results from an irradiation campaign with neutrons on small matrices and other test-structures, as well as the response of the sensors to high energy charged tracks are presented.

Balestri, G.; Batignani, G.; Beck, G.; Bernardelli, A.; Berra, A.; Bettarini, S.; Bevan, |A.; Bombelli, L.; Bosi, F.; Bosisio, L.; Casarosa, G.; Ceccanti, M.; Cenci, R.; Citterio, M.; Coelli, S.; Comotti, D.; Dalla Betta, G.-F.; Fabbri, L.; Fiorini, C.; Fontana, G.; Forti, F.; Gabrielli, A.; Gaioni, L.; Gannaway, F.; Giorgi, F.; Giorgi, M. A.; Lanceri, L.; Liberali, V.; Lietti, D.; Lusiani, A.; Mammini, P.; Manazza, A.; Manghisoni, M.; Monti, M.; Morris, J.; Morsani, F.; Nasri, B.; Neri, N.; Oberhof, B.; Palombo, F.; Pancheri, L.; Paoloni, E.; Pellegrini, G.; Perez, A.; Petragnani, G.; Prest, M.; Povoli, M.; Profeti, A.; Quartieri, E.; Rashevskaya, I.; Ratti, L.; Re, V.; Rizzo, G.; Sbarra, C.; Semprini-Cesari, N.; Soldani, A.; Stabile, A.; Stella, C.; Traversi, G.; Valentinetti, S.; Verzellesi, G.; Villa, M.; Vitale, L.; Walsh, J.; Wilson, F.; Zoccoli, A.; Zucca, S.

2013-12-01

118

Integration of solid-state nanopores in a 0.5 ?m CMOS foundry process  

NASA Astrophysics Data System (ADS)

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Uddin, A.; Yemenicioglu, S.; Chen, C.-H.; Corigliano, E.; Milaninia, K.; Theogarajan, L.

2013-04-01

119

Integration of solid-state nanopores in a 0.5 ?m CMOS foundry process.  

PubMed

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

120

Integration of solid-state nanopores in a 0.5 ?m cmos foundry process  

PubMed Central

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

121

Process-dependent thin-film thermal conductivities for thermal CMOS MEMS  

Microsoft Academic Search

The thermal conductivities ? of the dielectric and conducting thin films of three commercial CMOS processes were determined in the temperature range from 120 to 400 K. The measurements were performed using micromachined heatable test structures containing the layers to be characterized. The ? values of thermally grown silicon oxides are reduced from bulk fused silica by roughly 20%. The

Martin von Arx; Oliver Paul; Henry Baltes

2000-01-01

122

A fast low noise CMOS charge sensitive preamplifier for column parallel CCD readout  

Microsoft Academic Search

A fast, low noise charge sensitive preamplifier for column parallel CCD readout application is presented. This prototype has been implemented on a commercial CMOS 65nm process. This preamplifier consists of a two stage transconductance amplifier with capacitive feedback to accommodate two gain ranges and a second transconductance amplifier to reset the circuit. An equivalent noise charge of 37 electrons for

J. P. Walder; Peter Denes; Carl Grace; Henrik von der Lippe; Bob Zheng

2011-01-01

123

Evaluation of a CMOS/SOS Process Using Process Validation Wafers.  

National Technical Information Service (NTIS)

The objective of this work was to determine baseline electrical parameters that could be used to evaluate a fabrication process. Two lots of wafers containing NBS-16 test chips were fabricated at a commercial vendor in a radiation-hard, CMOS/SOS process. ...

J. S. Suehle L. W. Linholm G. M. Marshall

1982-01-01

124

A comparison of electrostatic discharge models and failure signatures for CMOS integrated circuit devices  

Microsoft Academic Search

Six different CMOS device codes were evaluated, according to available test standards, for electrostatic discharge (ESD) sensitivity using three ESD models: human body model (HBM). machine model (MM), and field-induced charged device model (FCDM). Four commercially available simulators were used: two to perform the HBM ESD evaluations and two to perform the MM ESD evaluations. FCDM stressing was performed using

M. Kelly; G. Servais; T. Diep; D. Lin; S. Twerefour; G. Shah

1996-01-01

125

A comparison of electrostatic discharge models and failure signatures for CMOS integrated circuit devices  

Microsoft Academic Search

Six different CMOS device codes were evaluated, according to available test standards, for Electrostatic Discharge (ESD) sensitivity using three ESD models: Human Body Model (HBM), Machine Model (MM), Field-induced Charged Device Model (FCDM). Four commercially available simulators were used: two to perform the HBM ESD evaluations and two to perform the MM ESD evaluations. FCDM stressing was performed using an

M. Kelly; G. Servais; T. Diep; D. Lin; S. Twerefour; G. Shah

1995-01-01

126

Laser Doppler blood flow imaging with a 64×64 pixel full custom CMOS sensor  

Microsoft Academic Search

Full field laser Doppler perfusion imaging offers advantages over scanning laser Doppler imaging as the effects of movement artifacts are reduced. The increased frame rate allows rapid changes in blood flow to be imaged. A custom made CMOS sensor offers several advantages over commercial cameras as the design can be optimized to the detected signals. For example, laser Doppler signals

D. He; H. C. Nguyen; B. R. Hayes-Gill; Y. Zhu; J. A. Crowe; S. P. Morgan; G. F. Clough; C. A. Gill

2011-01-01

127

Thermally and electrically isolated single crystal silicon structures in CMOS technology  

Microsoft Academic Search

Thermally and electrically isolated single crystal silicon structures have been fabricated using a post-processing anisotropic tetramethyl ammonium hydroxide (TMAH) electrochemical etch. The process was carried out on CMOS circuits fabricated by a commercial foundry. Since the etch consists of a single micromachining step performed on packaged and bonded dice, this technique has the potential for cost-effective prototyping and production of

Richard J. Reay; Erno H. Klaassen; Gregory T. A. Kovacs

1994-01-01

128

High speed CMOS technology for ASIC application  

Microsoft Academic Search

In order to realize high speed and high density CMOS logic LSI's, an advanced two-level metal CMOS technology, having minimum feature size of 1.0 µm, has been developed. The technology has proven very high speed feasibility of CMOS logic arrays of less than half-nsec delay times, in addition to high reliability of 5V operation. BCD3structure is employed for 1.0 µm

H. Ooka; S. Murakami; M. Murayama; K. Yoshida; S. Takao; O. Kudoh

1986-01-01

129

1\\/f noise in advanced CMOS transistors  

Microsoft Academic Search

Complementary metal-oxide-semiconductor (CMOS) technology is dominant in the microelectronics industry for a wide range of applications, including analog, digital, RF, and sensor systems. The advantages of silicon CMOS technology compared to bipolar technology as well as transistors in other semiconductors is well-established. CMOS technology scaling has been a main drive for continuous progress in the silicon based semiconductor industry over

Yael Nemirovsky; Dan Corcos; Igor Brouk; Amikam Nemirovsky; Samir Chaudhry

2011-01-01

130

Performance of downward scaled CMOS\\/SOS  

Microsoft Academic Search

MOS\\/SOS structures have been investigated which suppress various anomalous currents and also adjust threshold voltage to the desired value for downward scaled CMOS\\/ SOS devices. Furthermore, short channel CMOS\\/SOS device performance has been discussed in comparison with the CMOS\\/Bulk. A deeper, boron implant was used for n-channel MOSFET on SOS to suppress the back channel current and the punch through

Sinji TAGUCHI; Hiroyuki TANGO; Kenji MAEGUCHI; Luong Mo Dang

1979-01-01

131

A post-CMOS micromachined lateral accelerometer  

Microsoft Academic Search

In a post-complementary metal-oxide-semiconductor (CMOS) micromachining technology, the process flow enables the integration of micromechanical structures with conventional CMOS circuits which are low-cost and readily available. This paper presents a lateral capacitive sensing accelerometer fabricated in the post-CMOS process. Design advantages include electrically isolated multimetal routing on microstructures to create full-bridge capacitive sensors, and integration to increase transducer sensitivity by

Hao Luo; Gang Zhang; L. Richard Carley; Gary K. Fedder

2002-01-01

132

Seamless integration of CMOS and microfluidics using flip chip bonding  

NASA Astrophysics Data System (ADS)

We demonstrate the microassembly of PDMS (polydimethylsiloxane) microfluidics with integrated circuits made in complementary metal-oxide-semiconductor (CMOS) processes. CMOS-sized chips are flip chip bonded to a flexible polyimide printed circuit board (PCB) with commercially available solder paste patterned using a SU-8 epoxy. The average resistance of each flip chip bond is negligible and all connections are electrically isolated. PDMS is attached to the flexible polyimide PCB using a combination of oxygen plasma treatment and chemical bonding with 3-aminopropyltriethoxysilane. The total device has a burst pressure of 175 kPA which is limited by the strength of the flip chip attachment. This technique allows the sensor area of the die to act as the bottom of the microfluidic channel. The SU-8 provides a barrier between the pad ring (electrical interface) and the fluids; post-processing is not required on the CMOS die. This assembly method shows great promise for developing analytic systems which combine the strengths of microelectronics and microfluidics into one device.

Welch, David; Blain Christen, Jennifer

2013-03-01

133

High current CMOS operational amplifier  

Microsoft Academic Search

This paper describes a low voltage CMOS operational amplifier, which is capable of driving heavy resistive and capacitive loads. Robust and power efficient compensation is achieved by using Miller compensation together with a high bandwidth stage. Measurements show that the amplifier achieves 5.7 MHz unity gain frequency and 61° phase margin when driving 1nF||1k? load, while drawing 2.4mA from 1.5V

Mikko Loikkanen; Juha Kostamovaara

2005-01-01

134

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices  

NASA Technical Reports Server (NTRS)

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

135

TDC-based frequency synthesizer for wireless applications  

Microsoft Academic Search

We analyze phase noise performance and further discuss details of an all-digital PLL that is used in a commercial 130 nm CMOS single-chip Bluetooth radio. The frequency synthesizer uses a digitally controlled oscillator with a digital loop filter and a time-to-digital converter that acts as a phase\\/frequency detector. When implemented in a deep-submicron CMOS, the presented architecture appears more advantageous

Robert Bogdan Staszewski; D. Leipold; Chih-Ming Hung; P. T. Balsara

2004-01-01

136

Study on low noise CMOS image sensor  

Microsoft Academic Search

With the advance of semiconductor technology and the development of multimedia techniques, CMOS image sensor is extensively applied in medical and other industrial areas. Integrator array is the front-end processing circuit of CMOS image sensor, whose performance directly determines the image quality generated by image sensor. Currently, integrator array has become one research hot spot. The main works of this

Xu Wang; Hongyan Yang; Wuchen Wu

2010-01-01

137

Transistor sizing for low power CMOS circuits  

Microsoft Academic Search

A direct approach to transistor sizing for minimizing the power consumption of a CMOS circuit under a delay constraint is presented. In contrast to the existing assumption that the power consumption of a static CMOS circuit is proportional to the active area of the circuit, it is shown that the power consumption is a convex function of the active area.

Manjit Borah; Robert Michael Owens; Mary Jane Irwin

1996-01-01

138

JFET-CMOS microstrip front-end  

Microsoft Academic Search

While the CMOS version of the front-end chip developed for the microstrip vertex detector of the Aleph experiment is ready to go into operation, a new development is being carried on to achieve a reduction in noise. The improvement is related to the use of a JFET-CMOS chip design which is described in the present paper.

W. Buttler; V. Liberali; G. Lutz; F. Maloberti; P. F. Manfredi; V. Re; V. Speziali

1989-01-01

139

On fault detection in CMOS logic networks  

Microsoft Academic Search

This paper considers the problem of detecting faults in CMOS combinational networks. Effects of open and short faults in CMOS networks are analyzed. It is shown that the test sequence must be properly organized if the effects of all open faults are to be observable at the network output terminal. A simple and efficient heuristic method for organizing the test

Kuang-Wei Chiang; Zvonko G. Vranesic

1983-01-01

140

Peak crosstalk noise estimation in CMOS VLSI circuits  

Microsoft Academic Search

Interconnect between a CMOS driver and receiver can be modeled as a lossy transmission line in high speed CMOS VLSI circuits as transition times become comparable to or less than the time of flight delay of the signal through the interconnect. In this paper, a linear resistor model is used to approximate the CMOS driver stage, and the CMOS receiver

Kevin T. Tang; Eby G. Friedman

1999-01-01

141

Accelerated life testing effects on CMOS microcircuit characteristics  

NASA Technical Reports Server (NTRS)

Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

1977-01-01

142

CMOS foveal image sensor chip  

NASA Technical Reports Server (NTRS)

A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

2002-01-01

143

Full field laser Doppler flowmetry with custom made CMOS sensors  

NASA Astrophysics Data System (ADS)

Recently, full field laser Doppler perfusion imaging has been implemented using a commercial CMOS image sensor coupled with a digital signal processor. The advantage over scanning laser Doppler imaging is that movement artifacts are reduced and the scanning speed of the system is increased due to the absence of moving scanning components. A custom made CMOS sensor offers several advantages over commercial cameras as the specifications can be tailored to the signals of interest. An important advantage of custom made sensors is that on-chip processing allows the data bottleneck that exists between the photodetector array and processing electronics to be overcome, as the processed data can be read out from the image sensor to a PC or display at a low data rate. We demonstrate advancements made by our group in this area. In this paper a system is described which combines a 32x32 pixel array with on-chip processing linked to a field programmable gate array. Results are demonstrated using a rotating diffuser, a vibrating test target and blood flow in tissue. Methods for efficiently using silicon when implementing the signal processing on-chip are discussed.

He, Diwei; Hoang, Nguyen; Hayes-Gill, Barrie R.; Crowe, John A.; Zhu, Yiqun; Morgan, Stephen P.

2009-02-01

144

Electrical Characteristics of Intraoral Dental Imaging Devices Based on the CMOS Imager Coupled with Integrated X-ray Conversion Fiber Optics  

Microsoft Academic Search

As a continuation of our digital X-ray imaging sensor R&D, we have developed a cost-effective, intraoral imaging device based on the CMOS photosensor array coupled with an integrated X-ray conversion fiber-optic faceplate. It consists of a commercially available CMOS photosensor of a 35 times 35 mum2 pixel size and a 688 times 910 pixel array dimension, and a high efficiency

Hyosung ChoandSungil Choi; Sungil Choi; Bongsoo Lee; Sin Kim

2006-01-01

145

2 Gbps SerDes design based on IBM Cu11 (130nm) standard cell technology  

Microsoft Academic Search

This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as compared to conventional SerDes Designs, making it very attractive for modest budget multi-core and multi-processor ASICs with wide communication buses that are difficult to accommodate within the pin count of commonly available packaging.

Rashed Zafar Bhatti; Monty Denneau; Jeff Draper

2006-01-01

146

Impact of Spacecraft Shielding on Direct Ionization Soft Error Rates for sub-130 nm Technologies  

NASA Technical Reports Server (NTRS)

We use ray tracing software to model various levels of spacecraft shielding complexity and energy deposition pulse height analysis to study how it affects the direct ionization soft error rate of microelectronic components in space. The analysis incorporates the galactic cosmic ray background, trapped proton, and solar heavy ion environments as well as the October 1989 and July 2000 solar particle events.

Pellish, Jonathan A.; Xapsos, Michael A.; Stauffer, Craig A.; Jordan, Michael M.; Sanders, Anthony B.; Ladbury, Raymond L.; Oldham, Timothy R.; Marshall, Paul W.; Heidel, David F.; Rodbell, Kenneth P.

2010-01-01

147

CMOS \\  

Microsoft Academic Search

Fully integrated imaging receivers present a method of low power free-space optical communication with advantages over radio frequency and single element optical communication for a variety of network scenarios. This paper discusses the theoretical performance of such receivers and the design of a single \\

Brian S. Leibowitz; Bernhard E. Boser; Kristofer S. J. Pister; Berkeley Sensor

2001-01-01

148

Physics of Modern VLSI CMOS  

NASA Astrophysics Data System (ADS)

The Integrated Circuit (IC) was invented in 1958, and modern CMOS was invented in 1980. The semiconductor physics that underlies the IC was discovered in the early part of the past century, and, by the early 60's, it was simplified and codified such that it could be used by engineers to design transistors of ever shrinking size and increasing performance. However, in the past 5-10 years, the ``engineering physics'' of the 60's is becoming increasingly inadequate. Empirical corrections are being made to allow for quantum and non-equilibrium Boltzmann transport effects. Moreover, as features in CMOS transistors reach atomic dimensions, continuum physics is no longer adequate, and devices must be designed increasingly, at the atomic level. In the past 30 years, transistor gate length has shrunk by a factor of 100X: from 10 um to 0.1 um. And it is expected to shrink by about another factor of 10X to 10 nm in the next 10-15 years. However, as transistors approach the end of scaling, the physics to design them will become increasingly complex: *Gate oxide, which is today a few monolayers (10A) thick will be replaced with new materials with high dielectric constant. *Metal gate electrodes will replace poly-Si, and the interface, which sets the effective work-function, needs to be understood. *Carrier scattering in the inversion layer in the presence of increasingly high electric fields (horizontal and vertical) needs to be better understood. *Tunneling will increasingly dominate transistor behavior. *The discrete positioning of dopants will increasingly affect transistor performance. *Transistors will become increasingly ballistic. *Stress in the channel is increasing to the point where it has large impact on device performance. *And new materials will be introduced into the Source/Drain and channel. Each of these issues will be discussed, and the unresolved physics issues will be identified

Buss, Dennis

2005-03-01

149

CMOS scaling into the nanometer regime  

Microsoft Academic Search

Starting with a brief review on 0.1-?m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect

Yuan Taur; DOUGLAS A. BUCHANAN; Wei Chen; DAVID J. FRANK; KHALID E. ISMAIL; Shih-Hsien Lo; G. A. Sai-Halasz; R. G. Viswanathan; H.-J. C. Wann; S. J. Wind; Hon-Sum Wong

1997-01-01

150

CMOS Image Sensors with Video Compression  

Microsoft Academic Search

This paper describes CMOS image sensors integrating video compression circuits. The on-sensor compression is particularly useful for the low-power design of moving picture compression hardware, which is demanded especially in the mobile computing and telephony. Recent progress of the CMOS image sensor technology allows us to realise the integration of high-performance image sensor and computational functions on a chip. An

Shoji Kawahito; Yoshiaki Tadokoro; Akira Matsuzawa

1998-01-01

151

CMOS current-mode multivalued PLAs  

Microsoft Academic Search

A programmable logic array (PLA) structure for implementation of multivalued combinational and sequential systems is proposed. The PLA is integrable by using a conventional CMOS process and makes a NOR\\/TSUM two-level implementation of multivalued functions, which can consume less silicon area than an equivalent binary implementation. Pseudo-nMOS and dynamic CMOS implementations for the proposed PLA are also presented, using current-mode

F. J. Pelayo; A. Prieto; A. Lloris; J. Ortega

1991-01-01

152

Integrated polarization-analyzing CMOS image sensor  

Microsoft Academic Search

A CMOS image sensor with an integrated wire grid polarizer to sense the polarization of light is presented. The chip consists of an array of 128 by 128 pixels, it occupies an area of 5x4 mm 2 and it has been designed and fabricated in a CMOS 180nm process. Extinction ratio of 6.3 and 7.7 were achieved. The sensor is

Mukul Sarkar; David San Segundo Bello; Chris Van Hoof; Albert J. P. Theuwissen

2010-01-01

153

CMOS Photodetectors Integrated With Plasmonic Color Filters  

Microsoft Academic Search

A single-pixel plasmonic complementary metal oxide semiconductor (CMOS) photo sensor consisting of a plasmonic color filter integrated on a CMOS photodiode was fabricated using electron beam lithography and dry etch. The photocurrent measurement results confirmed the three primary color filtering responses that could be achieved in a single layer of nanostructured aluminium film. Finite-difference time-domain simulation demonstrated a good agreement

Qin Chen; Danial Chitnis; Kirsty Walls; Tim D. Drysdale; Steve Collins; David R. S. Cumming

2012-01-01

154

CMOS magnetic sensors with integrated ferromagnetic parts  

Microsoft Academic Search

The paper deals with Hall and flux-gate magnetic field sensors consisting of integrated combination of CMOS ASICs and planar ferromagnetic components. Ferromagnetic parts are made of a soft amorphous alloy, integrated at the CMOS wafer in a post-processing production phase. When the sensors are exposed to an in-plane magnetic field, under the peripheries of ferromagnetic parts appears a strong magnetic

Radivoje S. Popovic; Predrag M. Drljaca; Pavel Kejik

2006-01-01

155

Neutron spectrum and dose in a CMOS  

NASA Astrophysics Data System (ADS)

Using Monte Carlo methods the neutron spectrum in a pacemaker's CMOS has been estimated. A 18 MV LINAC model was used to expose a cell used to define the prostate located in a tissue equivalent phantom model. Neutron fluence at the CMOS is 2.6E(7) n/cm2-Gyx, the spectrum has thermal, epithermal and fast neutrons that will induce secondary, low and high LET, particles whose ionization could induce malfunction and failure of pacemaker in the oncological patient.

Vega-Carrillo, H. R.; Paredes-Gutierrez, L.; Borja-Hernandez, C. G.

2012-10-01

156

CMOS \\/ CMOL architectures for spiking cortical column  

Microsoft Academic Search

We present a spiking cortical column model based on neural associative memory, and demonstrate architectures for emulating the cortical column model with nanogrid molecular circuitry. We investigate a number of options for cost-effective hardware with digital CMOS and mixed-signal CMOL, a hybrid CMOS\\/nanogrid technology. We also give an example of a dynamic learning algorithm that is a suitable match to

Changjian Gao; Mazad S. Zaveri; Dan W. Hammerstrom

2008-01-01

157

Design and defect tolerance beyond CMOS  

Microsoft Academic Search

ABSTRACT It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advance- ment of CMOS-based VLSI circuits and systems. Regardless of the models, devices and technologies, any enhancement\\/replacement to CMOS must show,significant gains in at least one of the key met- rics (including speed, power and cost) for at least a

Xiaobo Sharon Hu; Alexander Khitun; Konstantin K. Likharev; Michael T. Niemier; Mingqiang Bao; Kang L Wang

2008-01-01

158

Bipolar transistor equivalents in CMOS technology  

Microsoft Academic Search

A CMOS circuit element equivalent to a bipolar junction transistor (BJT) which provides symmetrical performances of npn\\/pnp and ideality factor programming is proposed. Simulation showed that the ?, and Early voltage are superior to those of a typical BJT below about 1.65 GHz in a 0.8 ?m CMOS technology and the fabricated prototype has 2.3×10-16 A of IS, 2.4 mA

Gyudong Kim; Min-Kyu Kim; Wonchan Kim; Abdesselam Bouzerdoum

1995-01-01

159

CMOS image sensors for sensor networks  

Microsoft Academic Search

We report on two generations of CMOS image sensors with digital output fabricated in a 0.6 ?m CMOS process. The imagers embed\\u000a an ALOHA MAC interface for unfettered self-timed pixel read-out targeted to energy-aware sensor network applications. Collision\\u000a on the output is monitored using contention detector circuits. The image sensors present very high dynamic range and ultra-low\\u000a power operation. This

Eugenio Culurciello; Andreas G. Andreou

2006-01-01

160

45nm CMOS platform technology (CMOS6) with high density embedded memories  

Microsoft Academic Search

This paper describes the first 45nm Node CMOS technology (CMOS6) with optimized Vdd, EOT and BEOL parameters. For this technology to be applicable from high performance CPU to mobile applications, three sets of core devices are presented which are compatible with 0.069um2 trench capacitor DRAM and 0.247um2 6Tr.SRAM embedded memories.

M. Iwai; A. Oishi; T. Sanuki; Y. Takegawa; T. Komoda; Y. Morimasa; K. Ishimaru; M. Takayanagi; K. Eguchi; D. Matsushita; K. Muraoka; K. Sunouchi; T. Noguchi

2004-01-01

161

Low-loss and low-crosstalk 8 × 8 silicon nanowire AWG routers fabricated with CMOS technology.  

PubMed

Low-loss and low-crosstalk 8 × 8 arrayed waveguide grating (AWG) routers based on silicon nanowire waveguides are reported. A comparative study of the measurement results of the 3.2 nm-channel-spacing AWGs with three different designs is performed to evaluate the effect of each optimal technique, showing that a comprehensive optimization technique is more effective to improve the device performance than a single optimization. Based on the comprehensive optimal design, we further design and experimentally demonstrate a new 8-channel 0.8 nm-channel-spacing silicon AWG router for dense wavelength division multiplexing (DWDM) application with 130 nm CMOS technology. The AWG router with a channel spacing of 3.2 nm (resp. 0.8 nm) exhibits low insertion loss of 2.32 dB (resp. 2.92 dB) and low crosstalk of -20.5~-24.5 dB (resp. -16.9~-17.8 dB). In addition, sophisticated measurements are presented including all-input transmission testing and high-speed WDM system demonstrations for these routers. The functionality of the Si nanowire AWG as a router is characterized and a good cyclic rotation property is demonstrated. Moreover, we test the optical eye diagrams and bit-error-rates (BER) of the de-multiplexed signal when the multi-wavelength high-speed signals are launched into the AWG routers in a system experiment. Clear optical eye diagrams and low power penalty from the system point of view are achieved thanks to the low crosstalk of the AWG devices. PMID:24787827

Wang, Jing; Sheng, Zhen; Li, Le; Pang, Albert; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Qi, Minghao; Gan, Fuwan

2014-04-21

162

Design and Characterization of CMOS Avalanche Photodiode With Charge Sensitive Preamplifier  

Microsoft Academic Search

The CMOS Avalanche Photodiodes (APDs) and Charge Sensitive Preamplifiers (CSAs) were fabricated using the commercially available AMIS 0.7 mum high voltage process without any process modifications. The APDs have an N+\\/P-substrate structure with the diameters of their active areas equal to 25 mum, 50 mum, 100 mum, 400 mum, and 800 mum. The CSAs with three different input transistor sizes

Young Soo Kim; In Sub Jun; Kwang Hyun Kim

2008-01-01

163

Visualization of heavy ion-induced charge production in a CMOS image sensor  

Microsoft Academic Search

A commercial CMOS image sensor was irradiated with heavy ion beams in the several MeV energy range. The image sensor is equipped with a standard video output. The data were collected on-line through frame grabbing and analysed off-line after digitisation. It was shown that the response of the image sensor to the heavy ion bombardment varied with the type and

J. Végh; A. Kerek; W. Klamra; J. Molnár; L.-O Norlin; D. Novák; A. Sanchez-Crespo; J Van der Marel; A. Fenyvesi; I. Valastyán; A. Sipos

2004-01-01

164

Uncooled low-cost thermal imager based on micromachined CMOS integrated sensor array  

Microsoft Academic Search

We present a micromachined 10×10 array of thermoelectric infrared sensors fabricated in a commercial complementary metal-oxide-semiconductor (CMOS) integrated circuit process with subsequent bulk-micromachining on wafer-scale. This array is used to demonstrate the feasibility of a low-cost thermal imager. The imager operates in ambient air, without thermal stabilization or cooling. The thermoelectric sensor principle allows one to measure dc radiation signals

Andri Schaufelbühl; N. Schneeberger; Ulrich Münch; Marc Waelti; Oliver Paul; Oliver Brand; Henry Baltes; Christian Menolfi; Qiuting Huang; Elko Doering; Markus Loepfe

2001-01-01

165

Fabrication and Characterization of CMOS-MEMS Magnetic Microsensors  

PubMed Central

This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5–200 mT.

Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

166

Fabrication and characterization of CMOS-MEMS magnetic microsensors.  

PubMed

This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5-200 mT. PMID:24172287

Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

167

Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique  

PubMed Central

In this study we used the commercial 0.35 ?m CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz.

Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

2009-01-01

168

A 54-mW 8-Gbit/s VCSEL driver in a 65-nm CMOS technology  

NASA Astrophysics Data System (ADS)

We report a VCSEL driver ASIC designed and fabricated in a commercial 65-nm CMOS process. At 8 Gbps, the eye diagram passes the eye mask test and the bit-error-rate is less than 10-12 at the 95% confidence level. The total power consumption (including VCSEL) is about 54 mW, less than 1/4 of our previous VCSEL driver ASIC in a silicon-on-sapphire CMOS technology. The VCSEL driver has been tested in a neutron beam with the maximum energy of 800 MeV and the cross section has been estimated to be less than 3.14 × 10-11 cm2.

Liang, F.; Lu, W.; Chen, J.; Deng, B.; Gong, D.; Guo, D.; Jin, G.; Li, X.; Liang, H.; Liu, C.; Liu, G.; Wang, Z.; Xiang, A.; Xu, T.; Ye, J.; Liu, T.

2014-01-01

169

Impact of CMOS device scaling in ASICs on radiation immunity  

Microsoft Academic Search

Roadmaps for CMOS device technology has shown fast pace scaling in recent years. Mainstream CMOS devices have been produced with feature sizes between 0.1 and 0.25 ?m since the year 2000 and the so called \\

H. Ragaie; S. Kayed

2002-01-01

170

A spatiotemporal CMOS imager for nanosecond low power pulse detections  

Microsoft Academic Search

Nowadays, imagers based on CMOS active pixel sensors (APS) have performances that are competitive with those based on charge-coupled devices (CCD). CMOS imagers offer advantages in on-chip functionalities, system power reduction, cost and miniaturization. The aim of the FAst MOS Imager (FAMOSI) project is to reproduce streak camera functionality with a CMOS imager. We present FAMOSI 2, which has a

F. Morel; J.-P. Le Normand; C.-V. Zint; W. Uhring; Y. Hu

2004-01-01

171

Sensitivity of CMOS based imagers and scaling perspectives  

Microsoft Academic Search

CMOS based imagers are beginning to compete against CCDs in many areas of the consumer market because of their system-on-a-chip capability. Sensitivity, however, is a main weakness of CMOS imagers and enhancements and deviations from standard CMOS processes are necessary to keep up sensitivity with downscaled process generations. In the introductory section several definitions for the sensitivity of image sensors

Tarek Lulé; Stephan Benthien; Holger Keller; Frank Mütze; Peter Rieve; Konstantin Seibel; Michael Sommer; Markus Böhm

2000-01-01

172

Low power, CMOS digital autocorrelator spectrometer for spaceborne applications  

NASA Technical Reports Server (NTRS)

A 128-channel digital autocorrelator spectrometer using four 32 channel low power CMOS correlator chips was built and tested. The CMOS correlator chip uses a 2-bit multiplication algorithm and a full-custom CMOS VLSI design to achieve low DC power consumption. The digital autocorrelator spectrometer has a 20 MHz band width, and the total DC power requirement is 6 Watts.

Chandra, Kumar; Wilson, William J.

1992-01-01

173

Cascode voltage switch logic: A differential CMOS logic family  

Microsoft Academic Search

A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A CMOS circuit using 10,880 NMOS differential pairs has been developed using this approach.

L. Heller; W. Griffin; J. Davis; N. Thoma

1984-01-01

174

Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.  

PubMed

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

2011-01-01

175

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors  

PubMed Central

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

176

End-of-fabrication CMOS process monitor  

NASA Technical Reports Server (NTRS)

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

1990-01-01

177

Optical addressing technique for a CMOS RAM  

NASA Technical Reports Server (NTRS)

Progress on optically addressing a CMOS RAM for a feasibility demonstration of free space optical interconnection is reported in this paper. The optical RAM chip has been fabricated and functional testing is in progress. Initial results seem promising. New design and SPICE simulation of optical gate cell (OGC) circuits have been carried out to correct the slow fall time of the 'weak pull down' OGC, which has been characterized experimentally. Methods of reducing the response times of the photodiodes and the associated circuits are discussed. Even with the current photodiode, it appears that an OGC can be designed with a performance that is compatible with a CMOS circuit such as the RAM.

Wu, W. H.; Bergman, L. A.; Allen, R. A.; Johnston, A. R.

1988-01-01

178

Wafer bonding for MEMS and CMOS integration  

NASA Astrophysics Data System (ADS)

Wafer bonding became during past decade an important technology for MEMS manufacturing and wafer-level 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples.

Dragoi, V.; Pabo, E.; Burggraf, J.; Mittendorfer, G.

2011-05-01

179

CMOS cassette for digital upgrade of film-based mammography systems  

NASA Astrophysics Data System (ADS)

While full-field digital mammography (FFDM) technology is gaining clinical acceptance, the overwhelming majority (96%) of the installed base of mammography systems are conventional film-screen (FSM) systems. A high performance, and economical digital cassette based product to conveniently upgrade FSM systems to FFDM would accelerate the adoption of FFDM, and make the clinical and technical advantages of FFDM available to a larger population of women. The planned FFDM cassette is based on our commercial Digital Radiography (DR) cassette for 10 cm x 10 cm field-of-view spot imaging and specimen radiography, utilizing a 150 micron columnar CsI(Tl) scintillator and 48 micron active-pixel CMOS sensor modules. Unlike a Computer Radiography (CR) cassette, which requires an external digitizer, our DR cassette transfers acquired images to a display workstation within approximately 5 seconds of exposure, greatly enhancing patient flow. We will present the physical performance of our prototype system against other FFDM systems in clinical use today, using established objective criteria such as the Modulation Transfer Function (MTF), Detective Quantum Efficiency (DQE), and subjective criteria, such as a contrast-detail (CD-MAM) observer performance study. Driven by the strong demand from the computer industry, CMOS technology is one of the lowest cost, and the most readily accessible technologies available for FFDM today. Recent popular use of CMOS imagers in high-end consumer cameras have also resulted in significant advances in the imaging performance of CMOS sensors against rivaling CCD sensors. This study promises to take advantage of these unique features to develop the first CMOS based FFDM upgrade cassette.

Baysal, Mehmet A.; Toker, Emre

2006-03-01

180

Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips  

NASA Astrophysics Data System (ADS)

We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

2014-03-01

181

HSST BiCMOS technology with 26 ps ECL and 45 ps 2 V CMOS inverter  

Microsoft Academic Search

HSST\\/BiCMOS technology has been developed by merging a novel 0.3 ?m self-aligned double-poly bipolar process called high-performance super self-aligned process technology (HSST) and the 0.22 ?m CMOS process. The HSST bipolar transistor size is 2.5 times smaller than that of 1 ?m SST-1B with an emitter 0.4 ?m wide. This results from a 0.3 ?m design rule, a collector polysilicon

S. Konaka; T. Kobayashi; T. Matsuda; M. Ugajin; K. Imai; T. Sakai

1990-01-01

182

Two and multi-terminal CMOS\\/BiCMOS Si LED's  

Microsoft Academic Search

Silicon is an indirect bandgap material, but light emission is observed from reverse biased pn junctions. Even though the quantum efficiency is low, it may still be advantageous to use these devices in all-silicon optoelectronic integrated circuits (OICs). In this paper new research results with regard to low-voltage field emission BiCMOS and CMOS two- and multi-terminal Si LEDs are presented.

Monuko Du Plessis; Herzl Aharoni; Lukas W. Snyman

2005-01-01

183

Two and multi-terminal CMOS\\/BiCMOS Si LED’s  

Microsoft Academic Search

Silicon is an indirect bandgap material, but light emission is observed from reverse biased pn junctions. Even though the quantum efficiency is low, it may still be advantageous to use these devices in all-silicon optoelectronic integrated circuits (OICs). In this paper new research results with regard to low-voltage field emission BiCMOS and CMOS two- and multi-terminal Si LEDs are presented.

Monuko du Plessis; Herzl Aharoni; Lukas W. Snyman

2005-01-01

184

A 0.18?m CMOS low-power radiation sensor for UWB wireless transmission  

NASA Astrophysics Data System (ADS)

The paper describes the design of a floating gate MOS sensor embedded in a readout CMOS element, used as a radiation monitor. A maximum sensitivity of 1 mV/rad is estimated within an absorbed dose range from 1 to 10 krad. The paper shows in particular the design of a microelectronic circuit that includes the floating gate sensor, an oscillator, a modulator, a transmitter and an integrated antenna. A prototype of the circuit has recently been simulated, fabricated and tested exploiting a commercial 180 nm, 4 metal CMOS technology. Some simulation results are presented along with a measurement of the readout circuit response to an input voltage swing. Given the small estimated area of the complete chip prototype, that is less than 1 mm2, the chip fits a large variety of applications, from spot radiation monitoring systems in medicine to punctual measurements or radiation level in High-Energy Physics experiments.

Crepaldi, M.; Demarchi, D.; Gabrielli, A.; Khan, A.; Pikhay, E.; Roizin, Y.; Villani, G.; Zhang, Z.

2012-12-01

185

30-Gb/s 90-nm CMOS-driven equalized multimode optical link.  

PubMed

We report an 850-nm vertical cavity surface emitting laser (VCSEL)-based optical link that achieves a new record in speed. The laser driver and receiver ICs are fabricated in standard 90-nm bulk CMOS, and the optoelectronic devices are commercial components. Operation at 30 Gb/s with a bit-error rate < 10(-12) is achieved, representing to the authors' knowledge the highest speed reported to date for a CMOS-based full optical link. Transmitter feed-forward equalization is shown to improve maximum data rate from 25 to 30 Gb/s, timing margin by 17% at 23.5 Gb/s, and receiver sensitivity by 4 dB at 23.5 Gb/s. PMID:23669952

Hamel-Bissell, Brendan H; Proesel, Jonathan E; Lee, Benjamin G; Kuchta, Daniel M; Rylyakov, Alexander V; Schow, Clint L

2013-05-01

186

Low energy CMOS for space applications  

NASA Technical Reports Server (NTRS)

The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

Panwar, Ramesh; Alkalaj, Leon

1992-01-01

187

Monolithic piezoresistive CMOS magnetic field sensors  

Microsoft Academic Search

Two original electromechanical magnetic sensors have been developed using a fully industrial fabrication process that relies on bulk wet etching of CMOS dies. The first device uses the Lorentz force to actuate a U-shaped cantilever beam, while piezoresistive polysilicon gauges convert the beam bending into an electrical signal. A 2?T sensor resolution is demonstrated, making this device suitable for earth

Vincent Beroulle; Yves Bertrand; Laurent Latorre; Pascal Nouet

2003-01-01

188

A modeling technique for CMOS gates  

Microsoft Academic Search

In this paper, a modeling technique for CMOS gates, based on the reduction of each gate to an equivalent inverter, is presented. The proposed method can be incorporated in existing timing simulators in order to improve their accuracy. The conducting and parasitic behavior of parallel and serially connected transistors is accurately analyzed and an equivalent transistor is extracted for each

Alexander Chatzigeorgiou; Spiridon Nikolaidis; Ioannis Tsoukalas

1999-01-01

189

Tunable oscillating CMOS pixel for subretinal implants  

Microsoft Academic Search

Partial visual capabilities for some kind of blindness are still possible through direct electrical stimulation of retinal tissue. In this work, tunable implantable silicon CMOS pixel are presented and experimentally validated. Pulse width, stimulating output current and light sensibility may be regulated by external voltages, making this solution suitable for an auto-adapting artificial retina. Power consumption due to light detection

M. Mazza; P. Renaud; A. M. Ionescu; D. Bertrand

2005-01-01

190

Analysis of noise in CMOS image sensor  

Microsoft Academic Search

CMOS image sensors based on active pixel sensors (APS) are now the preferred technology for most imaging applications. With advanced technology, reduced channel size, novel designs extending the more established pixels based on three transistors (3T design) into four transistors (4T design employing pinned photodiodes), the performance keeps improving [1-2]. Noise sets a limit on image sensor performance, mainly under

I. Brouk; A. Nemirovsky; Y. Nemirovsky

2008-01-01

191

CMOS Equivalent Model of Ferroelectric RAM  

Microsoft Academic Search

The current research work in the paper is the representation of FRAM (Ferroelectric Random Access Memory) as an equivalent Model of Ferroelectric memory cell in Spice Tool. This Equivalent CMOS based model is designed to work at par with the behaviour working of the FRAM. The crux of the design of ferroelectric capacitor in the Ferroelectric Random Access Memory lies

Parvinder S. Sandhu; Iqbaldeep Kaur; Amit Verma; Birinderjit S. Kalyan; Jagdeep Kaur; Sanyam Anand

2010-01-01

192

A fully integrated CMOS nanoscale biosensor microarray  

Microsoft Academic Search

This paper presents a fully integrated CMOS mi- croarray for biosensor applications. A 64-pixel working electrode array with optimized reference and counter electrode structure is proposed to improve symmetry, and the feature sizes of electrodes have been scaled down to 600nm. The circuit utilizes the decoding scheme of memories to simplify the pixel design while shares potentiostat opamp and current

Lei Zhang; Xiangqing He; Yan Wang; Zhiping Yu

2011-01-01

193

Silicon on sapphire CMOS for optoelectronic microsystems  

Microsoft Academic Search

we report on a hybrid integration approach that represents a paradigm shift from traditional optoelectronic integration and packaging methods. A recent metamorphosis and wider availability of silicon on sapphire CMOS VLSI technology is generating a great deal of excitement in the optoelectronic systems community as it offers simple and elegant solutions to the many system integration and packaging challenges that

A. G. Andreou; Z. K. Kalayjian; A. Apsel; P. O. Pouliquen; R. A. Athale; G. Simonis; R. Reedy

2001-01-01

194

Minimizing power consumption in digital CMOS circuits  

Microsoft Academic Search

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology

ANANTHA P. CHANDRAKASAN; ROBERT W. BRODERSEN

1995-01-01

195

Transistor matching in analog CMOS applications  

Microsoft Academic Search

This paper gives an overview of MOSFET mismatch effects that form a performance\\/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit design is discussed. Mismatch effects gain importance as critical dimensions and CMOS power supply voltages decrease

Marcel J. M. Pelgrom; Hans P. Tuinhout; Maarten Vertregt

1998-01-01

196

Low noise monolithic CMOS front end electronics  

Microsoft Academic Search

Design considerations for low noise charge measurement and their application in CMOS electronics are described. The amplifier driver combination whose noise performance has been measured in detail as well as the analog multiplexing silicon strip detector readout electronics are designed with low power consumption and can be operated in pulsed mode so as to reduce heat dissipation even further in

G. Lutz; W. Buttler; H. Bergmann; P. Holl; B. J. Hosticka; P. F. Manfredi; G. Zimmer

1988-01-01

197

High-Performance CMOS Gate Array.  

National Technical Information Service (NTIS)

Mitsubishi Electric's unique gate-isolation configuration, which permits hybrid integration, was employed to develop a CMOS gate array having two gate modes: a 3 micrometer mode (3ns/gate) with 2,600, 1,600, and 1,100 gates; and a 2 micrometer mode (1.5ns...

M. Ueda T. Arakawa Y. Kuramitsu K. Okazaki K. Sugisaki

1984-01-01

198

CMOS-MEMS Downconversion Mixer-Filters.  

National Technical Information Service (NTIS)

The potential use of CMOS-MEMS downconversion mixer-filters in future reconfigurable integrated radios is demonstrated. Analytical and simulation models have been developed to enable mixer-filter design. An array of cantilever mixer-filters is designed an...

U. Arslan

2005-01-01

199

A comparative study of CMOS LNAs  

Microsoft Academic Search

Three CMOS RF low noise amplifier circuits have been designed and simulated. These LNAs are intended for use in 402-405 MHz medical implant communication service transceivers. The inductively degenerated common source LNA (CS-LNA) topology is currently popular because it achieves high gain, low noise figure, and high linearity. In this paper cascode LNA with inductive source degeneration, LC folded cascode

Sherif A. Saleh; Maurits Ortmanns; Yiannos Manoli

2007-01-01

200

Power-delay characteristics of CMOS adders  

Microsoft Academic Search

An approach to designing CMOS adders for both high speed and low power is presented by analyzing the performance of three types of adders - linear time adders, logN time adders and constant time adders. The representative adders used are a ripple carry adder, a blocked carry lookahead adder and several signed-digit adders, respectively. Some of the tradeoffs that are

Chetana Nagendra; Robert Michael Owens; Mary Jane Irwin

1994-01-01

201

Current-Mode CMOS Galois Field Circuits  

Microsoft Academic Search

Use of current-mode CMOS circuits for implementation of multiple-valued logic (MVL) functions has been consid- ered in a number of recent papers. In this paper, we present an application of these circuits in realization of Galois field operations. We also give a new algorithm for determination of polynomial representations for arbitrary functions over a class of Galois fields implementable with

Zeljko Zilic; Zvonko G. Vranesic

1993-01-01

202

Low temperature CMOS-a brief review  

Microsoft Academic Search

Bulk silicon CMOS applications at cryogenic temperatures are considered. It is argued that device improvements obtained from exploiting the dependence of physical characteristics of silicon at low temperature are above and beyond those improvements obtained from the usual geometric scaling of device dimensions. As device geometries continue to shrink into the deep submicrometer regime, second-order effects begin to limit further

William F. Clark; Badih El-Kareh; Renato G. Pires; Stephen L. Titcomb; Richard L. Anderson

1992-01-01

203

Minimizing Power Consumption in CMOS Circuits  

Microsoft Academic Search

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technol- ogy used to implement the digital circuits, the circuit style and topology, the architecture for implement- ing the circuits and at the highest level the algorithms that are being implemented. The most

Anantha P. Chandrakasan; Robert W. Brodersen

204

Low power SEU immune CMOS memory circuits  

NASA Technical Reports Server (NTRS)

The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.

Liu, M. N.; Whitaker, Sterling

1992-01-01

205

SOC CMOS technology for personal Internet products  

Microsoft Academic Search

Worldwide demand for Personal Internet Products is increasing rapidly, and will shape the directions of CMOS technology in the years ahead. Personal Internet Products are loosely defined in this paper as communication, computing and consumer products, which are enabled by the Internet: cell phones, PDAs, WLANs, Internet audio\\/video, ADSL, cable modems etc. Personal Internet Products are based on Digital Signal

Dennis Buss; Brian L. Evans; Jeff Bellay; William Krenik; Baher Haroun; Dirk Leipold; Ken Maggio; Jau-Yuann Yang; Ted Moise

2003-01-01

206

Research directions in beyond CMOS computing  

NASA Astrophysics Data System (ADS)

The International Technology Roadmap for Semiconductors has identified five promising research directions in beyond CMOS computing technology that are discussed here. Alternate state variables beyond electronic charge are introduced. Momentum and spin relaxation times for electrons in GaAs are calculated and show that magnetic systems are less strongly coupled to the thermal environment than systems based on electronic charge.

Bourianoff, George I.; Gargini, Paolo A.; Nikonov, Dmitri E.

2007-11-01

207

An integrated CMOS interface for lambda sensor  

Microsoft Academic Search

Automotive pollution can be reduced by suitably controlling the mixture that is fed to the cylinders. This can be performed by means of a feedback loop including a lambda sond and a processing unit which controls the electronic fuel injectors. This paper describes a CMOS interface which adapts the output signal of a lambda sensor to allow its feeding into

L. Civardi; U. Gatti; F. Maloberti; G. Torelli

1994-01-01

208

Low-Power SOI CMOS Transceiver  

NASA Technical Reports Server (NTRS)

The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS process. Potential advantages of SOI CMOS for deep-space communication electronics include: (1) Radiation hardness, (2) Low-power operation, and (3) System-on-Chip (SOC) solutions.

Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

2003-01-01

209

Bulk CMOS VLSI Technology Studies. Part 1. Scalable CMOS Design Rules. Part 2. CMOS Approaches to PLA (Programmable Logic Array) Design.  

National Technical Information Service (NTIS)

Part 1: Scalable CMOS design rules are developed for the MOSIS community to facilitate fabrication from a single design at 3 microns and 1.3 microns VHSIC dimensions. Part 2: Various Programmable Logic Array (PLA) implementations with clocked CMOS technol...

J. D. Trotter A. K. R. Naini

1985-01-01

210

Multiple Cell Upsets as the Key Contribution to the Total SER of 65 nm CMOS SRAMs and Its Dependence on Well Engineering  

Microsoft Academic Search

Neutron and alpha SER test results are presented for two SRAMs processed in a commercial 65 nm CMOS technology. Devices with the commonly used triple well option have higher rates of multiple cell upsets (MCU) and therefore higher SER. The same behavior is reported for older technologies from 180 nm to 65 nm. Full 3-D device simulations on 65 nm

G. Gasiot; D. Giot; P. Roche

2007-01-01

211

Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers  

NASA Astrophysics Data System (ADS)

This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

Liu, Yu-Chia; Tsai, Ming-Han; Tang, Tsung-Lin; Fang, Weileun

2011-10-01

212

Short-circuit energy dissipation modeling for submicrometer CMOS gates  

Microsoft Academic Search

A significant part of the energy dissipation in static complementary metal-oxide-semiconductor (CMOS) structures is due to short-circuit currents. In this paper, an accurate analytical model for the CMOS short-circuit energy dissipation is presented. First, the short-circuit energy dissipation of the CMOS inverter is modeled. The derived model is based on analytical expressions of the inverter output waveform which include the

L. Bisdounis; O. Koufopavlou

2000-01-01

213

Checkered white-RGB color LOFIC CMOS image sensor  

Microsoft Academic Search

We succeeded in developing a checkered White-RGB color CMOS image sensor based on a lateral overflow integration capacitor (LOFIC) architecture. The LOFIC CMOS image sensor with a 1\\/3.3-inch optical format, 1280H x 480V pixels, 4.2-?m effective pixel pitch along with 45° direction was designed and fabricated through 0.18-?m 2-Poly 3-Metal CMOS technology with buried pinned photodiode (PD) process. The image

Shun Kawada; Shin Sakai; Yoshiaki Tashiro; Shigetoshi Sugawa

2010-01-01

214

CMOS microelectrode array for bidirectional interaction with neuronal networks  

Microsoft Academic Search

A CMOS metal-electrode-based micro system for bidirectional communication (stimulation and recording) with neuronal cells in vitro is presented. The chip overcomes the interconnect challenge that limits today's bidirectional microelectrode arrays. The microsystem has been fabricated in an industrial CMOS technology with several post-CMOS processing steps to realize 128 biocompatible electrodes and to ensure chip stability in physiological saline. The system

Flavio Heer; Sadik Hafizovic; Wendy Franks; Axel Blau; C. Ziegler; A. Hierlemann

2006-01-01

215

Behavior of faulty double BJT BiCMOS logic gates  

NASA Technical Reports Server (NTRS)

Logic Behavior of a Double BJT BiCMOS device under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS, to bring out the testability differences.

Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

1992-01-01

216

Correct CMOS IC defect models for quality testing  

NASA Technical Reports Server (NTRS)

Leading edge, high reliability, and low escape CMOS IC test practices have now virtually removed the stuck-at fault model and replaced it with more defect-orientated models. Quiescent power supply current testing (I(sub DDQ)) combined with strategic use of high speed test patterns is the recommended approach to zero defect and high reliability testing goals. This paper reviews the reasons for the change in CMOS IC test practices and outlines an improved CMOS IC test methodology.

Soden, Jerry M.; Hawkins, Charles F.

1993-01-01

217

A High-Speed Target Tracking CMOS Image Sensor  

Microsoft Academic Search

The paper proposes a high-speed target tracking CMOS image sensor. The target tracking CMOS image sensor consists of an image sensor array, row-parallel processors, a controller and a SRAM. It implements two novel concise algorithms that composed of efficient operations: such as collision detection, separation detection and position extraction. A 64 times 64 pixel array high-speed target tracking CMOS image

Qingyu Lin; Wei Miao; Nanjian Wu

2006-01-01

218

A lateral capacitive CMOS accelerometer with structural curl compensation  

Microsoft Academic Search

We present successful experimental results from the first lateral capacitive accelerometer to be designed and manufactured in a conventional CMOS process. Compatibility with conventional CMOS provides advantages of low cost, high yield and fast prototyping that should be transferable to any CMOS foundry. A fully differential capacitive-bridge interface which cannot be realized in polysilicon technology is designed and implemented. Out-of-plane

Gang Zhang; Huikai Xie; Lauren E. de Rosset; Gary K. Fedder

1999-01-01

219

SiGe HBT X-Band LNAs for Ultra-Low-Noise Cryogenic Receivers  

Microsoft Academic Search

We report results on the cryogenic operation of two different monolithic X-band silicon-germanium (SiGe) heterojunction bipolar transistor low noise amplifiers (LNAs) implemented in a commercially-available 130 nm SiGe BiCMOS platform. These SiGe LNAs exhibit a dramatic reduction in noise temperature with cooling, yielding of less than 21 K (0.3 dB noise figure) across X-band at a 15 K operating temperature.

Tushar K. Thrivikraman; Jiahui Yuan; Joseph C. Bardin; Hamdi Mani; Stanley D. Phillips; Wei-Min Lance Kuo; John D. Cressler; Sander Weinreb

2008-01-01

220

Recent developments with CMOS SSPM photodetectors  

NASA Astrophysics Data System (ADS)

Experiments and simulations using various solid-state photomultiplier (SSPM) designs have been performed to evaluate pixel layouts and explore design choices. SPICE simulations of a design for position-sensing SSPMs showed charge division in the resistor network, and anticipated timing performance of the device. The simulation results predict good position information for resistances in the range of 1-5 k? and 150-? preamplifier input impedance. Back-thinning of CMOS devices can possibly increase the fill factor to 100%, improve spectral sensitivity, and allow for the deposition of anti-reflective coatings after fabrication. We report initial results from back illuminating a CMOS SSPM, and single Geiger-mode avalanche photodiode (GPD) pixels, thinned to 50 ?m.

Stapels, Christopher J.; Barton, Paul; Johnson, Erik B.; Wehe, David K.; Dokhale, Purushottam; Shah, Kanai; Augustine, Frank L.; Christian, James F.

2009-10-01

221

IR CMOS: infrared enhanced silicon imaging  

NASA Astrophysics Data System (ADS)

SiOnyx has developed visible and infrared CMOS image sensors leveraging a proprietary ultrafast laser semiconductor process technology. This technology demonstrates 10 fold improvements in infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Furthermore, these sensitivity enhancements are achieved on a focal plane with state of the art noise performance of 2 electrons/pixel. By capturing light in the visible regime as well as infrared light from the night glow, this sensor technology provides imaging in daytime through twilight and into nighttime conditions. The measured 10x quantum efficiency at the critical 1064 nm laser node enables see spot imaging capabilities in a variety of ambient conditions. The spectral sensitivity is from 400 to 1200 nm.

Pralle, M. U.; Carey, J. E.; Haddad, Homayoon; Vineis, C.; Sickler, J.; Li, X.; Jiang, J.; Sahebi, F.; Palsule, C.; McKee, J.

2013-06-01

222

CMOS compatible nanoscale nonvolatile resistance switching memory.  

PubMed

We report studies on a nanoscale resistance switching memory structure based on planar silicon that is fully compatible with CMOS technology in terms of both materials and processing techniques employed. These two-terminal resistance switching devices show excellent scaling potential well beyond 10 Gb/cm2 and exhibit high yield (99%), fast programming speed (5 ns), high on/off ratio (10(3)), long endurance (10(6)), retention time (5 months), and multibit capability. These key performance metrics compare favorably with other emerging nonvolatile memory techniques. Furthermore, both diode-like (rectifying) and resistor-like (nonrectifying) behaviors can be obtained in the device switching characteristics in a controlled fashion. These results suggest that the CMOS compatible, nanoscale Si-based resistance switching devices may be well suited for ultrahigh-density memory applications. PMID:18217785

Jo, Sung Hyun; Lu, Wei

2008-02-01

223

Study on sub-pixel measurement accuracy of CMOS imager  

NASA Astrophysics Data System (ADS)

There are two main image sensors that are now being widely used in image capture system: CCD and CMOS imager. The fill-factor of CMOS imager is lower than that of CCD, so it is of great importance to consider the influence of the fill-factor on sub-pixel measurement accuracy. the main purpose of this paper is to give a discussion of sub-pixel measurement accuracy of CMOS imager based on a digital camera which is designed and manufactured by ourselves. Conclusion is presented at the end of this paper, that the sub-pixel measurement accuracy of CMOS imager OV7620 can be 1/6 pixel.

Liu, Zhi

2005-02-01

224

Fundamental performance differences of CMOS and CCD imagers: part V  

NASA Astrophysics Data System (ADS)

Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

2013-02-01

225

Design of an ultra low power CMOS pixel sensor for a future neutron personal dosimeter  

SciTech Connect

Despite a continuously increasing demand, neutron electronic personal dosimeters (EPDs) are still far from being completely established because their development is a very difficult task. A low-noise, ultra low power consumption CMOS pixel sensor for a future neutron personal dosimeter has been implemented in a 0.35 {mu}m CMOS technology. The prototype is composed of a pixel array for detection of charged particles, and the readout electronics is integrated on the same substrate for signal processing. The excess electrons generated by an impinging particle are collected by the pixel array. The charge collection time and the efficiency are the crucial points of a CMOS detector. The 3-D device simulations using the commercially available Synopsys-SENTAURUS package address the detailed charge collection process. Within a time of 1.9 {mu}s, about 59% electrons created by the impact particle are collected in a cluster of 4 x 4 pixels with the pixel pitch of 80 {mu}m. A charge sensitive preamplifier (CSA) and a shaper are employed in the frond-end readout. The tests with electrical signals indicate that our prototype with a total active area of 2.56 x 2.56 mm{sup 2} performs an equivalent noise charge (ENC) of less than 400 e - and 314 {mu}W power consumption, leading to a promising prototype. (authors)

Zhang, Y.; Hu-Guo, C.; Husson, D.; Hu, Y. [Institut Pluridisplinaire Hubert Curien IPHC, Univ. of Strasbourg, CNRS/IN2P3, 23 Rue du Loess, 67037 Strasbourg (France)

2011-07-01

226

High-performance CMOS image sensors at BAE SYSTEMS Imaging Solutions  

NASA Astrophysics Data System (ADS)

In this paper, we present an overview of high-performance CMOS image sensor products developed at BAE SYSTEMS Imaging Solutions designed to satisfy the increasingly challenging technical requirements for image sensors used in advanced scientific, industrial, and low light imaging applications. We discuss the design and present the test results of a family of image sensors tailored for high imaging performance and capable of delivering sub-electron readout noise, high dynamic range, low power, high frame rates, and high sensitivity. We briefly review the performance of the CIS2051, a 5.5-Mpixel image sensor, which represents our first commercial CMOS image sensor product that demonstrates the potential of our technology, then we present the performance characteristics of the CIS1021, a full HD format CMOS image sensor capable of delivering sub-electron read noise performance at 50 fps frame rate at full HD resolution. We also review the performance of the CIS1042, a 4-Mpixel image sensor which offers better than 70% QE @ 600nm combined with better than 91dB intra scene dynamic range and about 1 e- read noise at 100 fps frame rate at full resolution.

Vu, Paul; Fowler, Boyd; Liu, Chiao; Mims, Steve; Balicki, Janusz; Bartkovjak, Peter; Do, Hung; Li, Wang

2012-07-01

227

Optimizing electronic standard cell libraries for variability tolerance through the nano-CMOS grid.  

PubMed

The project Meeting the Design Challenges of nano-CMOS Electronics (http://www.nanocmos.ac.uk) was funded by the Engineering and Physical Sciences Research Council to tackle the challenges facing the electronics industry caused by the decreasing scale of transistor devices, and the inherent variability that this exposes in devices and in the circuits and systems in which they are used. The project has developed a grid-based solution that supports the electronics design process, incorporating usage of large-scale high-performance computing (HPC) resources, data and metadata management and support for fine-grained security to protect commercially sensitive datasets. In this paper, we illustrate how the nano-CMOS (complementary metal oxide semiconductor) grid has been applied to optimize transistor dimensions within a standard cell library. The goal is to extract high-speed and low-power circuits which are more tolerant of the random fluctuations that will be prevalent in future technology nodes. Using statistically enhanced circuit simulation models based on three-dimensional atomistic device simulations, a genetic algorithm is presented that optimizes the device widths within a circuit using a multi-objective fitness function exploiting the nano-CMOS grid. The results show that the impact of threshold voltage variation can be reduced by optimizing transistor widths, and indicate that a similar method could be extended to the optimization of larger circuits. PMID:20643688

Walker, James Alfred; Sinnott, Richard; Stewart, Gordon; Hilder, James A; Tyrrell, Andy M

2010-08-28

228

A generalized CMOS-MEMS platform for micromechanical resonators monolithically integrated with circuits  

NASA Astrophysics Data System (ADS)

A generalized foundry-oriented CMOS-MEMS platform well suited for integrated micromechanical resonators alongside IC amplifiers has been developed for commercial multi-user purpose and demonstrated with a fast turnaround time of only 3 months and a variety of design flexibilities for resonator applications. With this platform, different configurations of capacitively-transduced resonators monolithically integrated with their amplifier circuits, spanning frequencies from 500 kHz to 14.5 MHz, have been realized with resonator Q's ranging between 700 and 3500. This platform, specifically featured with various configurations of structural materials, multi-dimensional displacements, different arrangements of mechanical boundary conditions, tiny supports of resonators, large transduction areas, well-defined anchors and performance enhancement scaling with IC fabrication technology, offers a variety of flexible design options targeted for sensor, timing reference, and RF applications. In addition, resonators consisting of metal-oxide composite structures fabricated by this platform offer an effective temperature compensation scheme for the first time in CMOS-MEMS resonators, showing TCf six times better than that of resonators merely made by CMOS metals.

Chen, Wen-Chien; Fang, Weileun; Li, Sheng-Shian

2011-06-01

229

Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference  

PubMed Central

This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of ?40–200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage VREF depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 ?W at room temperature and only 75 ?W at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of VREF and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

Boufouss, El Hafed; Francis, Laurent A.; Kilchytska, Valeriya; Gerard, Pierre; Simon, Pascal; Flandre, Denis

2013-01-01

230

Ultra-low power high temperature and radiation hard complementary metal-oxide-semiconductor (CMOS) silicon-on-insulator (SOI) voltage reference.  

PubMed

This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of -40-200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage V(REF) depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 ?W at room temperature and only 75 ?W at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of V(REF) and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2. PMID:24351635

Boufouss, El Hafed; Francis, Laurent A; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

2013-01-01

231

IDDQ testing in CMOS digital ASICs  

Microsoft Academic Search

IDDQ testing with precision measurement unit (PMU) was used to eliminate early life failures caused by CMOS digital ASICs in our products. Failure analysis of the rejected parts found that bridging faults caused by particles were not detected in incoming tests created by automatic test generation (ATG) for stuck-at-faults (SAF). The nominal 99.6% SAF test coverage required to release a

Roger Perry

1992-01-01

232

Energy recovery for low-power CMOS  

Microsoft Academic Search

Energy recovery, as a means to trade off power dissipation for performance in CMOS logic circuits, is analyzed and investigated. A mathematical model is presented to estimate the efficiency for two energy-recovery approaches under varying conditions of voltage swing, transition time, and MOS device parameters. This model can be directly compared to the well-known model for supply-voltage scaling, which is

William C. Athas; Nestoras Tzartzanis

1995-01-01

233

GaAs on Ge for CMOS  

Microsoft Academic Search

Selective epitaxial growth of GaAs on Ge is a prerequisite for the integration of GaAs and Ge in the sub-22 nm CMOS nodes. The problems encountered for epitaxial growth of GaAs on Ge are described and illustrated. Mainly the problem of anti-phase boundary (APB) formation is addressed. Selective epitaxial growth of GaAs on Ge with a SiO2 mask is discussed and

G. Brammertz; M. Caymax; M. Meuris; M. Heyns; Y. Mols; S. Degroote; M. Leys

2008-01-01

234

Low noise CMOS micro-fluxgate magnetometer  

Microsoft Academic Search

We present a new two-axis fluxgate magnetometer fully integrated in CMOS technology. The magnetometer exhibits excellent sensitivity of 2700 V\\/T and the magnetic equivalent noise spectral density of 6nT\\/?Hz at 1 Hz. The total power consumption is as low as 35 m W from the single 5 V power supply. The low noise characteristic is obtained using the combination of

Predrag M. Drljaca; P. Kejik; F. Vincent; R. S. Popovic

2003-01-01

235

RF-CMOS oscillators with switched tuning  

Microsoft Academic Search

Fully integrated CMOS oscillators are of great interest for use in single-chip wireless transceivers. In most oscillator circuits reported to date that operate in the 0.9 to 2 GHz frequency range, an integrated spiral inductor sets the frequency. It is generally believed that an LC oscillator, even when it uses a low-Q inductor, displays a lower phase noise than a

A. Kral; F. Behbahani; A. A. Abidi

1998-01-01

236

A novel CMOS magnetic field sensor array  

Microsoft Academic Search

A CMOS magnetic field sensor array that can be implemented along with analog and digital signal processing circuitry in the form of a single integrated circuit for instrumentation or measurement is discussed. The design realizes a single sensor device through interconnection of a few n-channel magnetic-field-sensitive MOSFETs (MAGFETs) in one circuit. The experimental measurements suggest that the interconnection, which forms

Durgamadhab Misra

1990-01-01

237

CMOS Current-Mode Companding Divider  

NASA Astrophysics Data System (ADS)

A CMOS current-mode companding divider is presented. Currents of both dividend and divisor are compressed into log-domain. Then the logarithm current of divisor is subtracted from the logarithm current of dividend. After expanding the subtraction result, the division function could be achieved. The simulation results indicate that the proposed divider has with good performance at only 1.8V supply voltage.

Lin, Kuo-Jen

238

CMOS Camera Array With Onboard Memory  

NASA Technical Reports Server (NTRS)

A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

Gat, Nahum

2009-01-01

239

LiB: a CMOS cell compiler  

Microsoft Academic Search

An automatic layout generation system, called LiB, for the small-scale integrated (SSI) cells used in CMOS VLSI design, is presented. LiB takes a transistor-level circuit schematic in SPICE format and outputs a mask layout in CIF. The layout style is a modification of that proposed by T. Uehara, and W. M. van Cleemput (IEEE Trans. Comput., vol.C-30, no.5, p.305-12, 1981).

Yung-ching Hsieh; Chi-yi Hwang; Youn-long Lin; Yu-chin Hsu

1991-01-01

240

Analog Circuit Design in Nanoscale CMOS Technologies  

Microsoft Academic Search

As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic

Lanny L. Lewyn; Trond Ytterdal; Carsten Wulff; Kenneth Martin

2009-01-01

241

Space efficient CMOS nonlinear transmission lines  

Microsoft Academic Search

Nonlinear transmission lines (NLTLs) are used in diverse applications such as edge-sharpening, pulse generation, and frequency conversion, however, length of a useful NLTL can require significant MMIC or RFIC real estate. We present an analytical model for the complex propagation constant of lossy, distributed NLTLs and fabricate several NLTLs in 0.25 mum CMOS for verification. Space-saving layout techniques such as

Keith G. Lyon; Fan Yu; Edwin C. Kan

2009-01-01

242

High-speed CMOS circuit technique  

Microsoft Academic Search

Ahtract -We have demonstrated that clock frequencies in ewes5 of 200 MHz are feasible in a 3-pm CMOS process. This is obtained by mean5 of clocking strategj, device sizing, and logic style selection. We use a precharge technique with a true single-phase clock, which remarkably increases the clock frequent) and reduces the skew problems, Device sizing with the help of

JIREN YUAN; CHRISTER SVENSSON

1989-01-01

243

Broadband esd protection circuits in cmos technology  

Microsoft Academic Search

Abstract, A broadband technique using monolithic T-coils is applied to electrostatic discharge (ESD) structures for both input and output pads. Fabricated in 0.18-m CMOS technology, the prototypes achieve operation at 10 Gb\\/s while providing a return loss of 20 dB at 10 GHz. The human-body model tolerance is 1000 V for the input structure and 800-900 V for the output

Sherif Galal; Behzad Razavi

2003-01-01

244

Architectures and circuits for RF CMOS receivers  

Microsoft Academic Search

This paper presents recent work in receiver architectures and circuits for RF CMOS applications. First, receiver topologies such as heterodyne, direct-conversion, and image-reject configurations together with their trade-offs are described. Next, the design of building blocks, e.g., low-noise amplifiers and mixers, baseband interfaces, and oscillators is studied. Three design examples for ISM, DECT, and cellular applications are then reviewed and

B. Razavi

1998-01-01

245

Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design  

NASA Astrophysics Data System (ADS)

In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.

Shin, SangHak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

2013-11-01

246

CMOS-controlled rapidly tunable photodetectors  

NASA Astrophysics Data System (ADS)

With rapidly increasing data bandwidth demands, wavelength-division-multiplexing (WDM) optical access networks seem unavoidable in the near future. To operate WDM optical networks in an efficient scheme, wavelength reconfigurability and scalability of the network are crucial. Unfortunately, most of the existing wavelength tunable technologies are neither rapidly tunable nor spectrally programmable. This dissertation presents a tunable photodetector that is designed for dynamic-wavelength allocation WDM network environments. The wavelength tuning mechanism is completely different from existing technologies. The spectrum of this detector is programmable through low-voltage digital patterns. Since the wavelength selection is achieved by electronic means, the device wavelength reconfiguration time is as fast as the electronic switching time. In this dissertation work, we have demonstrated a tunable detector that is hybridly integrated with its customized CMOS driver and receiver with nanosecond wavelength reconfiguration time. In addition to its nanosecond wavelength reconfiguration time, the spectrum of this detector is digitally programmable, which means that it can adapt to system changes without re-fabrication. We have theoretically developed and experimentally demonstrated two device operating algorithms based on the same orthogonal device-optics basis. Both the rapid wavelength tuning time and the scalability make this novel device very viable for new reconfigurable WDM networks. By taking advantage of CMOS circuit design, this detector concept can be further extended for simultaneous multiple wavelength detection. We have developed one possible chip architecture and have designed a CMOS tunable optical demux for simultaneous controllable two-wavelength detection.

Chen, Ray

247

A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter  

Microsoft Academic Search

A new operation mode using a partially depleted hybrid lateral BJT-CMOS inverter on SOI, named as unified-BiCMOS (U-BiCMOS) inverter, is proposed. The scheme utilizes the gated lateral npn or pnp BJT inherent of nor p-channel MOSFETs. Forward current is applied to the base terminal of the channel MOSFETs, with a normal pull-up or pull-down MOSFET as a current source, where

Toshiro Akino; Kei Matsuura; Akiyoshi Yasunaga

2005-01-01

248

Radiation Hardening of CMOS Microelectronics  

NASA Astrophysics Data System (ADS)

A unique methodology, silicon transfer to arbitrary substrates, has been developed under this program and is being investigated as a technique for significantly increasing the radiation insensitivity of limited quantities of conventional silicon microelectronic circuits. In this approach, removal of the that part of the silicon substrate not required for circuit operation is carried out, following completion of the circuit fabrication process. This post-processing technique is therefore applicable to state-of-the-art ICs, effectively bypassing the 3-generation technology/performance gap presently separating today's electronics from available radiation-hard electronics. Also, of prime concern are the cost savings that result by eliminating the requirement for costly redesign of commercial circuits for Rad-hard applications. Successful deployment of this technology will result in a major impact on the radiation hard electronics community in circuit functionality, design and software availability and fabrication costs.

McCarthy, A.; Sigmon, T. W.

2000-02-01

249

Low-power CMOS/BiCMOS drivers and receivers for on-chip interconnects  

NASA Astrophysics Data System (ADS)

Novel low-voltage swing CMOS and BiCMOS driver/receiver circuits for low-power VLSI applications are proposed. Interconnect wire drivers with low output signal swing are employed. Special receivers provide single and double level conversion while minimizing the total driver/receiver transmission delay. These level converters have no dc power dissipation. At 3.3 V power supply voltage, the proposed circuits consume less power without delay penalty. The power saving is observed to be as high as 30%. At lower supplies further power and delay improvements are observed.

Bellaouar, A.; Abu-Khater, I. S.; Elmasry, M. I.

1995-06-01

250

Performance evaluation of a digital intraoral imaging device based on the CMOS photosensor array coupled with an integrated X-ray conversion fiber-optic faceplate  

Microsoft Academic Search

As a continuation of our digital X-ray imaging sensor R&D, we have developed a cost-effective, intraoral imaging device based on the complementary-metal–oxide semiconductor (CMOS) photosensor array coupled with an integrated X-ray conversion fiber-optic faceplate. It consists of a commercially available CMOS photosensor of a 35×35?m2 pixel size and a 688×910 pixel array dimension, and a high-efficiency columnar CsI(Tl) scintillator of

Hyosung Cho; Sungil Choi; Jongguk Kim; Yangseo Koo; Taewoo Kim; Changjoon Ro; Bongsoo Lee; Sin Kim; Hokyung Kim

2007-01-01

251

Radiation-hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Technology  

NASA Astrophysics Data System (ADS)

Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown.

Miucci, A.; Gonella, L.; Hemperek, T.; Hügging, F.; Krüger, H.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Backhaus, M.; Capeans, M.; Feigl, S.; Nessi, M.; Pernegger, H.; Ristic, B.; Gonzalez-Sevilla, S.; Ferrere, D.; Iacobucci, G.; La Rosa, A.; Muenstermann, D.; George, M.; Große-Knetter, J.; Quadt, A.; Rieger, J.; Weingarten, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.; Kreidl, C.; Peric, I.; Breugnon, P.; Pangaud, P.; Godiot-Basolo, S.; Fougeron, D.; Bompard, F.; Clemens, J. C.; Liu, J.; Barbero, M.; Rozanov, A.; for HV-CMOS collaboration

2014-05-01

252

Space Commercialization  

NASA Technical Reports Server (NTRS)

A robust and competitive commercial space sector is vital to continued progress in space. The United States is committed to encouraging and facilitating the growth of a U.S. commercial space sector that supports U.S. needs, is globally competitive, and advances U.S. leadership in the generation of new markets and innovation-driven entrepreneurship. Energize competitive domestic industries to participate in global markets and advance the development of: satellite manufacturing; satellite-based services; space launch; terrestrial applications; and increased entrepreneurship. Purchase and use commercial space capabilities and services to the maximum practical extent Actively explore the use of inventive, nontraditional arrangements for acquiring commercial space goods and services to meet United States Government requirements, including measures such as public-private partnerships, . Refrain from conducting United States Government space activities that preclude, discourage, or compete with U.S. commercial space activities. Pursue potential opportunities for transferring routine, operational space functions to the commercial space sector where beneficial and cost-effective.

Martin, Gary L.

2011-01-01

253

Algorithms for automatic transistor sizing in CMOS digital circuits  

Microsoft Academic Search

This paper describes the algorithms for automatic transistor sizing (determination of device width and length) of CMOS digital circuits. In CMOS circuits, since power dissipation is small and not a limiting factor, the sizing algorithm is geared toward minimizing area. The program XTRAS (Xerox TRAnsistor Sizing Program) which determines transistor sizes as well as calculates path delays is described. Equations

William H. Kao; Nader Fathi; Chia-Hao Lee

1985-01-01

254

Pulse generator and BPSK modulator design for CMOS UWB transmitters  

Microsoft Academic Search

This paper presents a tunable Gaussian Pulse Generator and a BPSK modulator topology for use in CMOS UWB transmitters. The Pulse Generator exploits the Voltage Transfer Characteristic of a modified CMOS inverter, while the BPSK modulator guarantees superior matching between positive and negative pulses and supports high data rates at low power consumption, since its functional operation is in the

Michail Papamichail; Dimitrios Mavridis; George Papadopoulos

2009-01-01

255

Test results of various CMOS image sensor pixels  

Microsoft Academic Search

Today, CMOS image sensors are increasingly used in consumer products. Digital cameras, Web cameras, optical mouses, and smart sensors are some examples. One of the most used CMOS image sensor architectures is based on the active pixel sensor (APS). In order to understand more design tradeoffs, a prototype chip was designed to evaluate different pixel architectures. This paper describes the

D. C.-Y. Li; V. C. Gaudet; A. Basu

2005-01-01

256

Research of Noise Suppression for CMOS Image Sensor  

Microsoft Academic Search

Noise problem has a strong impact on the performance of sensor, especially in the field of aviation remote sensing. In this paper, the structure difference of CMOS and CCD image sensor is analyzed, and the noise affection and reasons are researched for CMOS image quality. Then the effective methods for each type of noise suppression are presented to improve the

Bin Luo; Lei Yan; Fuxing Yang

2010-01-01

257

Development of CMOS MEMS thermal bimorph actuator for driving microlens  

Microsoft Academic Search

A CMOS MEMS based thermal actuator is developed by using bimorph with embedded SiO2 and inverted-connected metal line adopted from CMOS materials. Vertical displacement of 47µm and power consumption of 139mW is obtained at 3Vdc.

Kah How Koh; Chengkuo Lee; Jyun-Hong Lu; Chii-Chang Chen

2011-01-01

258

A CMOS rotary encoder using magnetic sensor arrays  

Microsoft Academic Search

A new type of small magnetic rotary encoder is presented. The device detects the magnetic field of a permanent magnet attached to the end of the rotating shaft using complementary metal-oxide semiconductor (CMOS) magnetic sensors [magnetic field effect transistor (MAGFET) arrays] set in a square arrangement. The sensor array is integrated onto a CMOS chip along with angle-detection circuits, leading

Kazuhiro Nakano; Toru Takahashi; Shoji Kawahito

2005-01-01

259

Backside illuminated thinned CMOS image sensors for space imaging  

Microsoft Academic Search

This paper presents two aspects of ongoing research at Imec, to develop high-end CMOS APS sensors, optimized for space-born imaging. Both hybrid and monolithic thinned backside illuminated CMOS imagers with a unique combination of techniques and performance enhancing concepts have been developed. Here we report on their radiation tolerance and UV sensitivity, two critical characteristics for space science imaging instruments.

K. Minoglou; K. De Munck; D. S. Tezcan; C. Van Hoof; P. De Moor; J. Bogaerts; I. F. Veltroni

2008-01-01

260

CMOS OpAmp Resisting to Large Electromagnetic Interferences  

Microsoft Academic Search

A CMOS operational amplifier with high immunity to electromagnetic interferences is presented. It is based on an easy modification of the differential pair with active current load. The proposed input stage can be fabricated in standard CMOS technologies, and it neither requires extra mask levels, such as triple well, nor external components. Analysis and results are provided for very large

Anna Richelli

2010-01-01

261

Optimizing quantum efficiency in a stacked CMOS sensor  

Microsoft Academic Search

Optimizing quantum efficiency of image sensors, whether CCD or CMOS, has usually required backside thinning to bring the photon receiving surface close to the charge generation elements. A new CMOS sensor architecture has been developed that permits high-fill-factor photodiodes to be placed at the silicon surface without the need for backside thinning. The photodiode access provided by this architecture permits

Rob Hannebauer; Sang Keun Yoo; David L. Gilblom; Alexander D. Gilblom

2011-01-01

262

A CMOS Image Sensor for Fluorescence Lifetime Imaging  

Microsoft Academic Search

In this paper, a CMOS image sensor for fluorescence lifetime imaging (FLIM) is presented. The fluorescence lifetime is a powerful tool to analyze molecules because the fluorescence lifetime reflects a molecule's structure, dynamics, and environments. The proposed CMOS FLIM sensor consists of pixel array to realize the sifting ability for fluorescence, noise canceling column readout amplifiers, and output buffers. The

Hyung-June Yoon; Shoji Kawahito

2006-01-01

263

Spectrometer with CMOS demodulation of fiber optic Bragg grating sensors  

Microsoft Academic Search

A CMOS imager based spectrometer is developed to interrogate a network containing a large number of Bragg grating sensors. The spectrometer uses a Prism-Grating- Prism (PGP) to spectrally separate serially multiplexed Bragg reflections on a single fiber. As a result, each Bragg grating produces a discrete spot on the CMOS imager that shifts horizontally as the Bragg grating experiences changes

Martin Brokner Christiansen

2001-01-01

264

A CMOS image sensor for Hyper Omni Vision  

Microsoft Academic Search

This paper proposes and demonstrates a CMOS image sensor for Hyper Omni Vision, which can capture a surrounding image in whole direction at a time. The pixel of the sensor is configured so as to correct a distorted image reflected through a hyperbolic mirror. The sensor with 32 x 32 pixels is fabricated using 0.6 µm CMOS technology and confirmed

Jun Ohta; Hiroshi Wakasa; Keiichiro Kagawa; Masahiro Nunoshita; Mikio Suga; Motonori Doi; Osamu Oshiro; Kotaro Minato; Kunihiro Chihara

2003-01-01

265

Readout architectures for high speed CMOS image sensor  

NASA Astrophysics Data System (ADS)

High speed CMOS image sensors are very widely used in many applications such as machine vision, robotic sensing and scientifically imaging etc. Flexibility in design with CMOS technology allows the invention of various sensor architecture and tricks which can improve the sensor speed. In this paper we discuss several architectures for high speed sensors and their limitations.

Ma, Cheng; Li, Jing; Wang, Xinyang

2013-08-01

266

Sub 1 V CMOS bandgap reference design techniques: a survey  

Microsoft Academic Search

This paper presents a review of constraints, limitation factors and challenges to implement sub 1 V CMOS bandgap voltage reference\\u000a (BVR) circuits in today’s and future submicron technology. Moreover, we provide insight analysis of BVR circuit architectures\\u000a a designer can relay upon when building CMOS voltage reference.

Christian Jésus B. Fayomi; Gilson I. Wirth; Hervé Facpong Achigui; Akira Matsuzawa

2010-01-01

267

High responsivity CMOS imager pixel implemented in SOI technology  

NASA Technical Reports Server (NTRS)

Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

2000-01-01

268

Performance computation for precharacterized CMOS gates with RC loads  

Microsoft Academic Search

For efficiency, the performance of digital CMOS gates is often expressed in terms of empirical models. Both delay and short-circuit power dissipation are sometimes characterized as a function of load capacitance and input signal transition time. However, gate loads can no longer be modeled by purely capacitive loads for high performance CMOS due to the RC metal interconnect effects. This

Florentin Dartu; Noel Menezes; Lawrence T. Pileggi

1996-01-01

269

Supply and threshold voltage scaling for low power CMOS  

Microsoft Academic Search

This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially when the transistors are velocity saturated and the nodes have a high activity factor, In

Ricardo Gonzalez; Benjamin M. Gordon; Mark A. Horowitz

1997-01-01

270

LECTOR: a technique for leakage reduction in CMOS circuits  

Microsoft Academic Search

In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in subthreshold leakage current and hence static power dissipation. We propose a novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. In the proposed technique, we introduce two leakage control transistors (a

Narender Hanchate; Nagarajan Ranganathan

2004-01-01

271

Design of high speed camera based on CMOS technology  

NASA Astrophysics Data System (ADS)

The capacity of a high speed camera in taking high speed images has been evaluated using CMOS image sensors. There are 2 types of image sensors, namely, CCD and CMOS sensors. CMOS sensor consumes less power than CCD sensor and can take images more rapidly. High speed camera with built-in CMOS sensor is widely used in vehicle crash tests and airbag controls, golf training aids, and in bullet direction measurement in the military. The High Speed Camera System made in this study has the following components: CMOS image sensor that can take about 500 frames per second at a resolution of 1280*1024; FPGA and DDR2 memory that control the image sensor and save images; Camera Link Module that transmits saved data to PC; and RS-422 communication function that enables control of the camera from a PC.

Park, Sei-Hun; An, Jun-Sick; Oh, Tae-Seok; Kim, Il-Hwan

2007-12-01

272

CMOS solid state photomultipliers for ultra-low light levels  

NASA Astrophysics Data System (ADS)

Detection of single photons is crucial for a number of applications. Geiger photodiodes (GPD) provide large gains with an insignificant amount of multiplication noise exclusively from the diode. When the GPD is operated above the reverse bias breakdown voltage, the diode can avalanche due to charged pairs generated from random noise (typically thermal) or incident photons. The GPD is a binary device, as only one photon is needed to trigger an avalanche, regardless of the number of incident photons. A solid-state photomultiplier (SSPM) is an array of GPDs, and the output of the SSPM is proportional to the incident light intensity, providing a replacement for photomultiplier tubes. We have developed CMOS SSPMs using a commercial fabrication process for a myriad of applications. We present results on the operation of these devices for low intensity light pulses. The data analysis provides a measured of the junction capacitance (~150 fF), which affects the rise time (~2 ns), the fall time (~32 ns), and gain (>106). Multipliers for the cross talk and after pulsing are given, and a consistent picture within the theory of operation of the expected dark current and photodetection efficiency is demonstrate. Enhancement of the detection efficiency with respect to the quantum efficiency at unity gain for shallow UV photons is measured, indicating an effect due to fringe fields within the diode structure. The signal and noise terms have been deconvolved from each other, providing the fundamental model for characterizing the behavior at low-light intensities.

Johnson, Erik B.; Stapels, Christopher J.; Chen, Xaio Jie; Whitney, Chad; Chapman, Eric C.; Alberghini, Guy; Rines, Rich; Augustine, Frank; Christian, James

2011-05-01

273

A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts  

NASA Technical Reports Server (NTRS)

A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

Quilligan, G.; Aslam, S.; DuMonthier, J.

2012-01-01

274

MBE—Enabling technology beyond Si CMOS  

NASA Astrophysics Data System (ADS)

Achievement of low interfacial densities of states, small equivalent oxide thickness, high ? values, and thermal stability at high temperatures in the high ? dielectrics on high carrier mobility semiconductors, the leading candidates for technology beyond Si CMOS, has been made using MBE. This paper reviews our recent advances in meeting the unprecedented demands in materials and physics for the new technology. Moreover, self-aligned inversion-channel InGaAs and Ge MOSFETs using MBE-Ga 2O 3(Gd 2O 3) as the gate dielectric are compared favorably with those using the gate dielectrics made from other thin film techniques.

Chang, P.; Lee, W. C.; Lin, T. D.; Hsu, C. H.; Kwo, J.; Hong, M.

2011-05-01

275

Diurnal measurements with prototype CMOS Omega receivers  

NASA Technical Reports Server (NTRS)

Diurnal signals from eight omega channels have been monitored at 10.2 KHz for selected station pairs. All eight Omega stations have been received at least 50 percent of the time over a 24 hour period during the month of October 1976. The data presented confirm the expected performance of the CMOS omega sensor processor in being able to digsignals out of a noisy environment. Of particular interest are possibilities for use of antipodal reception phenomena and a need for some ways of correcting for multi-modal propagation effects.

Burhans, R. W.

1976-01-01

276

A CMOS field-programmable analog array  

NASA Astrophysics Data System (ADS)

The design details and test results of a field-programmable analog array (FPAA) prototype chip in 1.2-micron CMOS are presented. The analog array is based on subthreshold circuit techniques and consists of a collection of a homogeneous configurable analog blocks (CABs) and an interconnection network. Interconnections between CABs and the analog functions to be implemented in each block are defined by a set of configuration bits loaded serially into an onboard shift register by the user. Macromodels are developed for the analog functions in order to simulate various neural network applications on the field-programmable analog array.

Lee, Edward K. F.; Gulak, P. G.

1991-12-01

277

Nanoscale Materials and Structures for CMOS Devices  

NSDL National Science Digital Library

This presentation was given at the Arizona Nanotechnology Conference in March of 2008 by Dr. Stefan Zollner, Freescale Semiconductor, USA. The focus is on problems with planar CMOS and their solutions. These solutions consist of: SOI or FINFET to reduce source and drain leakage, high mobility channel materials to increase drive current, new silicide materials to reduce source and drain contact resistance, metal oxides with high dielectric constants to reduce gate leakage and metal gate electrodes to reduce gate depletion. Overall, the presentation is filled with images and diagrams allowing it to flow easily. This is an excellent resource for anyone looking to learn more about nanotechnology and its applications.

Zollner, Stefan

2008-10-27

278

Predictive Technology Model of Enhanced CMOS Devices  

Microsoft Academic Search

\\u000a The scaling of traditional bulk CMOS structure has slowed down in recent years as fundamental physical and process limits\\u000a are rapidly approached. For instance, short-channel effects, such as drain-induced-barrier-lowering (DIBL) and threshold voltage\\u000a (Vth) rolloff, severely increase leakage current and degrade the Ion\\/Ioff ratio (Fig. 2.11) [1]. To overcome these difficulties and continue the path projected by Moore’s law, new materials

Yu Cao

279

Solar XUV Imaging and Non-dispersive Spectroscopy for Solar-C Enabled by Scientific CMOS APS Arrays  

NASA Astrophysics Data System (ADS)

Monolithic CMOS Advanced Pixel Sensor (APS) arrays are showing great promise as eventual replacements for the current workhorse of solar physics focal planes, the scientific CCD. CMOS APS devices have individually addressable pixels, increased radiation tolerance compared to CCDs, and require lower clock voltages, and thus lower power. However, commercially available CMOS chips, while suitable for use with intensifiers or fluorescent coatings, are generally not optimized for direct detection of EUV and X-ray photons. A high performance scientific CMOS array designed for these wavelengths will have significant new capabilities compared to CCDs, including the ability to read out small regions of the solar disk at high (sub sec) cadence, count single X-ray photons with Fano-limited energy resolution, and even operate at room temperature with good noise performance. Such capabilities will be crucial for future solar X-ray and EUV missions such as Solar-C. Sarnoff Corporation has developed scientific grade, monolithic CMOS arrays for X-ray imaging and photon counting. One prototype device, the "minimal" array, has 8 um pixels, is 15 to 25 um thick, is fabricated on high-resistivity ( 10 to 20 kohm-cm) Si wafers, and can be back-illuminated. These characteristics yield high quantum efficiency and high spatial resolution with minimal charge sharing among pixels, making it ideal for the detection of keV X-rays. When used with digital correlated double sampling, the array has demonstrated noise performance as low as 2 e, allowing single photon counting of X-rays over a range of temperatures. We report test results for this device in X-rays, and discuss the implications for future solar space missions.

Stern, Robert A.; Lemen, J. R.; Shing, L.; Janesick, J.; Tower, J.

2009-05-01

280

High-speed CMOS image sensor for high-throughput lensless microfluidic imaging system  

NASA Astrophysics Data System (ADS)

The integration of CMOS image sensor and microfluidics becomes a promising technology for point-of-care (POC) diagnosis. However, commercial image sensors usually have limited speed and low-light sensitivity. One high-speed and high-sensitivity CMOS image sensor chip is introduced in this paper, targeted for high-throughput microfluidic imaging system. Firstly, high speed image sensor architecture is introduced with design of column-parallel single-slope analog-todigital converter (ADC) with digital correlated double sampling (CDS). The frame rate can be achieved to 2400 frames/second (fps) with resolution of 128×96 for high-throughput microfluidic imaging. Secondly, the designed system has superior low-light sensitivity, which is achieved by large pixel size (10?m×10?m, 56% fill factor). Pixel peak signalnoise- ratio (SNR) reaches to 50dB with 10dB improvement compared to the commercial pixel (2.2?m×2.2?m). The degradation of pixel resolution is compensated by super-resolution image processing algorithm. By reconstructing single image with multiple low-resolution frames, we can equivalently achieve 2?m resolution with physical 10?m pixel. Thirdly, the system-on-chip (SoC) integration results in a real-time controlled intelligent imaging system without expensive data storage and time-consuming computer analysis. This initial sensor prototype with timing-control makes it possible to develop high-throughput lensless microfluidic imaging system for POC diagnosis.

Yan, Mei; Huang, Xiwei; Jia, Qixiang; Nadipalli, Revanth; Wang, Tongxi; Shang, Yang; Yu, Hao; Je, Minkyu; Yeo, Kiatseng

2012-02-01

281

Commercial applications  

NASA Technical Reports Server (NTRS)

Viewgraphs on commercial applications of fuzzy logic in Japan are presented. Topics covered include: suitable application area of fuzzy theory; characteristics of fuzzy control; fuzzy closed-loop controller; Mitsubishi heavy air conditioner; predictive fuzzy control; the Sendai subway system; automatic transmission; fuzzy logic-based command system for antilock braking system; fuzzy feed-forward controller; and fuzzy auto-tuning system.

Togai, Masaki

1990-01-01

282

Commercial Art.  

ERIC Educational Resources Information Center

This curriculum guide provides materials for a competency-based course in commercial art at the secondary level. The curriculum design uses the curriculum infused model for the teaching of basic skills as part of vocational education and demonstrates the relationship of vocationally related skills to communication, mathematics, and science…

Vassallo, Thomas

283

A 200 mm SiGe-HBT BiCMOS technology for mixed signal applications  

Microsoft Academic Search

A BiCMOS technology including 0.25 ?m electrical channel length (LEFF) nFET and pFET CMOS devices and 60 GHz fmax SiGe-HBT transistors has been achieved on 200 mm wafers. Both CMOS circuits and SiGe-HBT analog circuits were fabricated on the same chip to demonstrate the high integration capabilities of the technology. The CMOS circuits include CMOS ring oscillators and a 64

D. Nguyen-Ngoc; D. L. Harame; J. C. Malinowski; S. J. Jeng; K. T. Schonenberg; M. M. Gilbert; G. D. Berg; S. Wu; M. Soyuer; K. A. Tallman; K. J. Stein; R. A. Groves; S. Subbanna; D. B. Colavito; D. A. Sunderland; B. S. Meyerson

1995-01-01

284

The 1.2 micron CMOS technology  

NASA Technical Reports Server (NTRS)

A set of test structures was designed using the Jet Propulsion Laboratory (JPL) test chip assembler and was used to evaluate the first CMOS-bulk foundry runs with feature sizes of 1.2 microns. In addition to the problems associated with the physical scaling of the structures, this geometry provided an additional set of problems, since the design files had to be generated in such a way as to be capable of being processed through p-well, n-well, and twin-well processing lines. This requirement meant that the files containing the geometric design rules as well as the structure design files had to produce process-insensitive designs, a requirement that does not apply to the more mature 3.0-micron CMOS feature size technology. Because of the photolithographic steps required with this feature size, the maximum allowable chip size was 10 x 10 mm, and this chip was divided into 24 project areas, with each area being 1.6 x 1.6 mm in size. The JPL-designed structures occupied 13 out of the 21 allowable project sizes and provided the only test information obtained from these three preliminary runs. The structures were used to successfully evaluate three different manufacturing runs through two separate foundries.

Pina, C. A.

1985-01-01

285

Far ultraviolet sensitivity of silicon CMOS sensors  

NASA Astrophysics Data System (ADS)

We describe vacuum ultraviolet sensitivity measurements of a new high performance silicon-based CMOS sensor from Teledyne Imaging Sensors. These sensors do not require the high voltages of MCP detectors, making them a lower mass and power alternative to the more mature MCP technology. These devices demonstrate up to 40 percent quantum efficiency at vacuum ultraviolet wavelengths, either meeting or greatly exceeding 10 percent quantum efficiency across the entire 100-200 nm wavelength region. As with similar visible sensitive devices, backside illumination results in a higher quantum efficiency than frontside illumination. Measurements of the vacuum ultraviolet sensitivity of the Teledyne silicon PIN detectors were made by directing a known intensity of ultraviolet light at discrete wavelengths onto the test detectors and reading out the resulting photocurrent. The sensitivity of the detector at a given wavelength was then calculated from the intensity and wavelength of the incoming light and the relative photodiode to NIST-traceable calibration diode active areas. A custom electromechanical interface was developed to make these measurements within the SwRI Vacuum Radiometric Calibration Chamber. While still in the single pixel stage, full 1K × 1K focal plane arrays are possible using existing CMOS readout electronics and hold great promise for inclusion in future spaceflight instrument concepts.

Davis, Michael W.; Greathouse, Thomas K.; Retherford, Kurt D.; Winters, Gregory S.; Bai, Yibin; Beletic, James W.

2012-07-01

286

SEMICONDUCTOR INTEGRATED CIRCUITS: A full on-chip CMOS low-dropout voltage regulator with VCCS compensation  

NASA Astrophysics Data System (ADS)

A full on-chip CMOS low-dropout (LDO) voltage regulator with high PSR is presented. Instead of relying on the zero generated by the load capacitor and its equivalent series resistance, the proposed LDO generates a zero by voltage-controlled current sources for stability. The compensating capacitor for the proposed scheme is only 0.18 pF, which is much smaller than the capacitor of the conventional compensation scheme. The full on-chip LDO was fabricated in commercial 0.35 ?m CMOS technology. The active chip area of the LDO (including the bandgap voltage reference) is 400 × 270 ?m2. Experimental results show that the PSR of the LDO is -58.7 dB at a frequency of 10 Hz and -20 dB at a frequency of 1 MHz. The proposed LDO is capable of sourcing an output current up to 50 mA.

Leisheng, Gao; Yumei, Zhou; Bin, Wu; Jianhua, Jiang

2010-08-01

287

Packaged CMOS-MEMS free-free beam oscillator  

NASA Astrophysics Data System (ADS)

In this paper a self-oscillator based on a polysilicon free-free beam resonator monolithically integrated and packaged in a 0.35 µm complementary metal-oxide-semiconductor (CMOS) technology is presented. The oscillator is capable of providing a 350 mVPP sinusoidal signal at 25.6 MHz, with a bias polarization voltage of 7 V. The microelectromechanical systems (MEMS) resonator is packaged using only the back-end-of-line metal layers of the CMOS technology, providing a complete low-cost CMOS-MEMS processing for on-chip frequency references.

Marigó, E.; Verd, J.; López, J. L.; Uranga, A.; Barniol, N.

2013-11-01

288

Lower-Dark-Current, Higher-Blue-Response CMOS Imagers  

NASA Technical Reports Server (NTRS)

Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

2008-01-01

289

Scaling trends in SET pulse widths in Sub-100 nm bulk CMOS processes.  

SciTech Connect

Digital single-event transient (SET) measurements in a bulk 65-nm process are compared to transients measured in 130-nm and 90-nm processes. The measured SET widths are shorter in a 65-nm test circuit than SETs measured in similar 90-nm and 130-nm circuits, but, when the factors affecting the SET width measurements (in particular pulse broadening and the parasitic bipolar effect) are considered, the actual SET width trends are found to be more complex. The differences in the SET widths between test circuits can be attributed in part to differences in n-well contact area. These results help explain some of the inconsistencies in SET measurements presented by various researchers over the past few years.

Narasimham, Balaji; Ahlbin, Jonathan R.; Schrimpf, Ronald D.; Gadlage, Matthew J.; Massengill, Lloyd W.; Vizkelethy, Gyorgy; Reed, Robert A.; Bhuva, Bharat L.

2010-07-01

290

Interim Test Status Report for NEPP Scaled CMOS Online Source.  

National Technical Information Service (NTIS)

This document reports the status of the NASA Electronic Parts and Packaging (NEPP) Scaled Complementary Metal Oxide Semiconductor (CMOS) Reliability effort for FY2010. This years work concentrated on the development of a reliability test apparatus for DDR...

J. N. Bowles-Martinez, S. M. Guertin

2010-01-01

291

CMOS compatible chips for applications in nonlinear optics  

NASA Astrophysics Data System (ADS)

We demonstrate a range of novel functions based on a high index doped silica glass CMOS compatible platform. This platform has promise for telecommunications and onchip WDM optical interconnects for computing.

Moss, D. J.; Jackson, S. D.; Pasquazi, A.; Peccianti, M.; Morandotti, R.

2013-10-01

292

CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology  

NASA Technical Reports Server (NTRS)

This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

2006-01-01

293

CMOS Active Pixel Sensors: Design For Scientific Applications.  

National Technical Information Service (NTIS)

Scientific applications demand high performance CMOS Active Pixel Sensors. This paper will discuss where critical improvements are needed and describe how to achieve them. Our current drive in image sensor developments stem from the general needs of low-n...

R. Turchetta A. Clark J. Crooks A. Fant M. J. French

2005-01-01

294

Single Phase Dynamic CMOS PLA Using Charge Sharing Technique.  

National Technical Information Service (NTIS)

A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, mak...

Y. B. Dhong C. P. Tsang

1991-01-01

295

CMOS imager for pointing and tracking applications  

NASA Technical Reports Server (NTRS)

Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

2006-01-01

296

Latchup in CMOS devices from heavy ions  

NASA Technical Reports Server (NTRS)

It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

Soliman, K.; Nichols, D. K.

1983-01-01

297

CMOS digital pixel sensors: technology and applications  

NASA Astrophysics Data System (ADS)

CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

Skorka, Orit; Joseph, Dileepan

2014-04-01

298

CMOS image sensor with contour enhancement  

NASA Astrophysics Data System (ADS)

Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5?m DPTM CMOS process.

Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

2010-05-01

299

SOI for digital CMOS VLSI: design considerations and advances  

Microsoft Academic Search

This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAMs), dynamic random access memories (DRAMs), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting from the unique SOI device structure. The impact of floating-body in partially depleted

Ching-Te Chuang; PONG-FEI LU; CARL J. ANDERSON

1998-01-01

300

CMOS Monolithic Active Pixel Sensors (MAPS): Developments and future outlook  

Microsoft Academic Search

Re-invented in the early 1990s, on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology are today the most sold solid-state imaging devices, overtaking the traditional technology of Charge-Coupled Devices (CCD). The slow uptake of CMOS MAPS started with low-end applications, for example web-cams, and is slowly pervading the high-end applications, for example in prosumer

R. Turchetta; A. Fant; P. Gasiorek; C. Esbrand; J. A. Griffiths; M. G. Metaxas; G. J. Royle; R. Speller; C. Venanzi; P. F. van der Stelt; H. Verheij; G. Li; S. Theodoridis; H. Georgiou; D. Cavouras; G. Hall; M. Noy; J. Jones; J. Leaver; D. Machin; S. Greenwood; M. Khaleeq; H. Schulerud; J. M. Østby; F. Triantis; A. Asimidis; D. Bolanakis; N. Manthos; R. Longo; A. Bergamaschi

2007-01-01

301

High Speed and Low Energy Lateral BJT-CMOS Inverter  

Microsoft Academic Search

A new operation mode for a partially depleted CMOS inverter on SOI is proposed, and a hybrid lateral BJT-CMOS inverter circuit is designed and simulated. The scheme utilizes the gated lateral npn or pnp BJT inherent of n- or p-channel MOSFETs. Forward current is applied to the base terminal of the channel MOSFETs, with a normal pull-up or pull-down MOSFET

Toshiro Akino

302

A linear-control wide-band CMOS attenuator  

Microsoft Academic Search

A fully-CMOS controllable attenuator with a multi-octave bandwidth is presented. The linearity of the attenuation control is ensured by a constant-current reference device in a feedback loop, and another self-adjusting control loop is adopted for matching. Realized with a standard 0.8-?m CMOS process, the circuit has a bandwidth of DC-900 MHz with an attenuation tuning range of >28 dB. The

Risto Kaunisto; Petri Korpi; Jiri Kiraly; Kari Haloneri

2001-01-01

303

AN UNCOOLED MICROBOLOMETER INFRARED DETECTOR IN ANY STANDARD CMOS TECHNOLOGY  

Microsoft Academic Search

This paper reports a new microbolometer structure with the CMOS n-well layer as the active element. The n-well structures are suspended and thermally isolated by post-etching of fabricated and bonded CMOS chips, while the n-well regions are protected from etching by the electrochemical etch-stop technique in a TMAH solution. The characterization results of the fabricated chips show that the n-well

D. S. Tezcan; F. Koçer; T. Akin

1999-01-01

304

Low power CMOS adaptive electronic central pattern generator design  

Microsoft Academic Search

In this paper, low power VLSI implementation of adaptive analog controller for autonomous robot is presented using standard CMOS process with 2V supply voltage. Electronic neuron and synapse circuit are developed based on Hindmarsh-Rose neuron model and first order synapse model. In order to achieve low power consumption, CMOS subthreshold circuit techniques are used. The power consumption is 4.8 mW

Young Jun Lee; Jihyun Lee; Yong-Bin Kim; Joseph Ayers

2005-01-01

305

Quantified Temperature Effect in a CMOS Image Sensor  

Microsoft Academic Search

In recent years, CMOS image sensors (CISs) have increasingly become major players in the solid-state imaging market, a market in which charge-coupled device image sensors were once the dominant product. Exceptional circuit integration capability makes CMOS imagers suitable for implementation in a single-chip imaging system while inducing the temperature variation of an image sensor. In this paper, global and local

Dong-Long Lin; Ching-Chun Wang; Chia-Ling Wei

2010-01-01

306

Characterization and deblurring of lateral crosstalk in CMOS image sensors  

Microsoft Academic Search

Lateral crosstalk in CMOS imaging arrays deter effective utilization of small pixel sizes (e.g., < 5.0 ?m × 5.0 ?m) now permitted by technology scaling. A simple measurement setup for empirical characterization of lateral crosstalk in CMOS image sensors is presented. A demonstration of deblurring operations based on the obtained blur model of lateral crosstalk is also provided. Several well-known

Ji Soo Lee; Joey Shah; M. Ed Jernigan; Richard I. Hornsey

2003-01-01

307

Heavy ion radiation damage simulations for CMOS image sensors  

Microsoft Academic Search

Damage in CMOS image sensors caused by heavy ions with moderate energy (~10MeV) are discussed through the effects on transistors and photodiodes. SRIM (stopping and range of ions in matter) simulation results of heavy ion radiation damage to CMOS image sensors implemented with standard 0.35µm and 0.18µm technologies are presented. Total ionizing dose, displacement damage and single event damage are

Henok Mebrahtu; Wei Gao; Paul J. Thomas; William E. Kieser; Richard I. Hornsey

308

Heavy ion radiation damage simulations for CMOS image sensors  

Microsoft Academic Search

Damage in CMOS image sensors caused by heavy ions with moderate energy (~10MeV) are discussed through the effects on transistors and photodiodes. SRIM (stopping and range of ions in matter) simulation results of heavy ion radiation damage to CMOS image sensors implemented with standard 0.35µm and 0.18µm technologies are presented. Total ionizing dose, displacement damage and single event damage are

Henok T. Mebrahtu; Wei Gao; Paul J. Thomas; William E. Kieser; Richard I. Hornsey

2004-01-01

309

Selenium coated CMOS passive pixel array for medical imaging  

NASA Astrophysics Data System (ADS)

Digital imaging systems for medical applications use amorphous silicon thin-film transistor (TFT) technology due to its ability to be manufactured over large areas. However, TFT technology is far inferior to crystalline silicon CMOS technology in terms of the speed, stability, noise susceptibility, and feature size. This work investigates the feasibility of integrating an imaging array fabricated in CMOS technology with an a-Se detector. The design of a CMOS passive pixel sensor (PPS) array is presented, in addition to how an 8×8 PPS array is integrated with the 75 micron thick stabilized amorphous selenium detector. A non-linear increase in the dark current of 200 pA, 500 pA and 2 nA is observed with 0.27, 0.67 and 1.33 V/micron electric field respectively, which shows a successful integration of selenium layer with the CMOS array. Results also show that the integrated Selenium-CMOS PPS array has good responsivity to optical light and X-rays, leaving the door open for further research on implementing CMOS imaging architectures going forward. Demonstrating that the PPS chips using CMOS technology can use a-Se as a detector is thus the first step in a promising path of research, which should yield substantial and exciting results for the field. Though area may still prove challenging, larger CMOS wafers can be manufactured and tiled to allow for a large enough size for certain diagnostic imaging applications and potentially even large area applications like digital mammography.

Majid, Shaikh Hasibul; Goldan, Amir H.; Hadji, Bahman; Belev, George; Kasap, Safa; Karim, Karim S.

2011-03-01

310

CMOS monolithic pixel sensors research and development at LBNL  

Microsoft Academic Search

This paper summarizes the recent progress in the design and characterization of CMOS pixel sensors at LBNL. Results of lab\\u000a tests, beam tests and radiation hardness tests carried out at LBNL on a test structure with pixels of various sizes are reported.\\u000a The first results of the characterization of back-thinned CMOS pixel sensors are also reported, and future plans and

D. Contarato; J.-M. Bussat; P. Denes; L. Greiner; T. Kim; T. Stezelberger; H. Wieman; M. Battaglia; B. Hooberman; L. Tompkins

2007-01-01

311

CMOS monolithic pixel sensors research and development at LBNL  

NASA Astrophysics Data System (ADS)

This paper summarizes the recent progress in the design and characterization of CMOS pixel sensors at LBNL. Results of lab tests, beam tests and radiation hardness tests carried out at LBNL on a test structure with pixels of various sizes are reported. The first results of the characterization of back-thinned CMOS pixel sensors are also reported, and future plans and activities are discussed.

Contarato, D.; Bussat, J.-M.; Denes, P.; Greiner, L.; Kim, T.; Stezelberger, T.; Wieman, H.; Battaglia, M.; Hooberman, B.; Tompkins, L.

2007-12-01

312

A CMOS smart rotary encoder using magnetic sensor arrays  

Microsoft Academic Search

This paper presents a new concept of small magnetic rotary encoders. The magnetic field induced by a rotatable magnet is detected by integrated CMOS magnetic sensors (MAGFETs) arranged in a square form. This magnetic sensor array is integrated on a CMOS chip with angle detection circuits, leading to the realization of a small-size and cost-effective rotary encoder. Commonly-used magnetic encoders

Kazuhiro Nakano; Toru Takahashi; Shoji Kawahito

2003-01-01

313

Designing 1-V op amps using standard digital CMOS technology  

Microsoft Academic Search

This paper addresses the difficulty of designing 1-V capable analog circuits in standard digital complementary metal-oxide-semiconductor (CMOS) technology, Design techniques for facilitating 1-V operation are discussed and 1-V analog building block circuits are presented. Most of these circuits use the bulk-driving technique to circumvent the metal-oxide-semiconductor field-effect transistor turn-on (threshold) voltage requirement. Finally, techniques are combined within a 1-V CMOS

Benjamin J. Blalock; Phillip E. Allen; Gabriel A. Rincon-Mora

1998-01-01

314

CMOS\\/LCOS-based image transceiver device: II  

Microsoft Academic Search

A CMOS-liquid crystal-based image transceiver device (ITD) is under development at the Holon Institute of Technology. The device combines both functions of imaging and display in a single array configuration. This unique structure allows the combination of see-through, aiming, imaging and the displaying of a superposed image to be combined in a single, compact, head mounted display. The CMOS-based pixel

Uzi Efron; Isak Davidov; Vladimir Sinelnikov; Asher A. Friesem

2001-01-01

315

CMOS-liquid-crystal-based image transceiver device  

Microsoft Academic Search

A CMOS-Liquid Crystal-Based Image Transceiver Device (ITD) is under development at the Holon Institute of Technology. The device combines both functions of imaginary and display in a single array structure. This unique structure allows the combination of see-through, aiming, imaging and the displaying of a superposed image to be combined in a single, compact, head mounted display. The CMOS-based pixel

Uzi Efron; Isak Davidov; Vladimir Sinelnikov; Ilya Levin

2001-01-01

316

A CMOS image sensor for high-speed imaging  

Microsoft Academic Search

Acquisition of the images of fast-moving objects requires imagers with high photoresponsivity at short integration times, synchronous exposure, and high-speed parallel readout. Previous CMOS implementations yield frame rates around 500 frames\\/s at integration times ranging from 75 to 200 ps, and some use rolling shutter only. This CMOS imager achieves more than 1000 frames\\/s with integration time in synchronous exposure

Nenad Stevanovic; Mathias Hillebrand; Bedrich J. Hosticka; Andreas Teuner

2000-01-01

317

Fabrication of the planar angular rotator using the CMOS process  

Microsoft Academic Search

This investigation proposes a novel planar angular rotator fabricated by the conventional CMOS process. Following the 0.6 ?m SPTM (single poly triple metal) CMOS process, the device is completed by a simple post-process with maskless etching. The suspension unit rotates around its geometric center with electrostatic actuation. In addition to having a single rotatory component, 2×2 and 3×3 arrayed components

Hunrzlin Chen; Chienliu Chang; Kaihsiang Yen; Huiwen Huang; Jinhung Chio; Chingyi Wu; Peizen Chang

2000-01-01

318

Delta Doping High Purity CCDs and CMOS for LSST  

NASA Technical Reports Server (NTRS)

A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

2006-01-01

319

Sensing temperature in CMOS circuits for Thermal Testing  

Microsoft Academic Search

Abstract Temperature,is a ,physical ,magnitude ,that can ,be used,as an ,observable ,quantity ,for ,IC testing purposes. The authors ,discuss ,in this ,paper ,the suitability of two ,temperature ,measuring ,strategies applicable to standard ,CMOS integrated circuits: a laser interferometer ,and ,a differential ,fully CMOS built-in temperature,sensor. Keywords: Thermal testing, temperature sensors, analysis failure, built-in self test 1. Introduction:Thermal testing Thermal,testing comprises

Josep Altet; Antonio Rubio; M. Amine Salhi; J. L. Gálvez; Stefan Dilhaire; Ashish Syal; André Ivanov

2004-01-01

320

CMOS varactors in NLTL pulse-compression applications  

Microsoft Academic Search

This paper discusses the feasibility of using CMOS varactors in designing all-silicon pulse-compression nonlinear transmission lines (NLTLs). Six different varactor structures based on CMOS transistors are investigated, and are divided into two groups. One group, with a monotonic C(I) characteristic, can be used in single-edge pulse-compression NLTLs, while the other, having a non-monotonic C(I), is suited for double-edge pulse-compression. After

Ming Li; Robert G. Harrison; Rony E. Amaya; Jean-Marc Duchamp; Philippe Ferrari; N. Garry Tarr

2007-01-01

321

CMOS varactors in NLTL pulse-compression applications  

Microsoft Academic Search

This paper discusses the feasibility of using CMOS varactors in designing all-silicon pulse-compression nonlinear transmission lines (NLTLs). Six different varactor structures based on CMOS transistors are investigated, and are divided into two groups. One group, with a monotonic C(V) characteristic, can be used in single-edge pulse-compression NLTLs, while the other, having a non-monotonic C(V), is suited for double-edge pulse-compression. After

Ming Li; Robert G. Harrison; Rony E. Amaya; Jean-Marc Duchamp; Philippe Ferrari; N. Garry Tarr

2007-01-01

322

A study of phase noise in CMOS oscillators  

Microsoft Academic Search

This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis of a linear oscillatory system leads to a noise shaping function and a new definition of Q. A linear model of CMOS ring oscillators is used to calculate their phase noise, and three phase noise phenomena, namely, additive noise, high-frequency multiplicative noise, and low-frequency multiplicative

Behzad Razavi

1996-01-01

323

A 13.4GHz CMOS frequency divider  

Microsoft Academic Search

This paper describes the design ofa 13.4 GHz 1\\/2-frequency divider fabricated in a partially-scaled 0.1 ?m bulk CMOS technology. The circuit design is heavily influenced by the device structures and layout rules. To reduce both fabrication cost and turnaround time, the CMOS process scales only channel length to 0.1 ?m and gate oxide to 40 Å. Design rules for other

B. Razavi; K. F. Lee; Ran-Hong Yan

1994-01-01

324

A CMOS image sensor with 2.0-e  

Microsoft Academic Search

A low noise CMOS image sensor without degradation of saturation performance has been developed by using column amplifiers of the gains of about 1.0 with a lateral overflow integration capacitor technology. The 1\\/4-inch, SVGA CMOS image sensor has achieved 0.98 column readout gain, 100-¿V\\/e- conversion gain, 2.0-e- total random noise, 0.5-e- in readout circuits, 110,000-e- full well capacity and 95-dB

Takahiro Kohara; Woonghee Lee; Koichi Mizobuchi; Shigetoshi Sugawa

2010-01-01

325

Hafnium oxide and hafnium aluminum oxide for CMOS applications  

Microsoft Academic Search

The continued scaling of the CMOS gate dielectric to its fundamental limit governed by the large gate leakage current requires the introduction of high-k material for sub-100-nm technology nodes. This dissertation research deals with the physical and electrical properties of a promising high-k candidate, hafnium oxide, as a gate dielectric for CMOS applications. Hafnium oxide made by the Jet-Vapor-Deposition process

Wenjuan Zhu

2003-01-01

326

Low-cost uncooled infrared detectors in CMOS process  

Microsoft Academic Search

This paper reports the implementation and comparison of two low-cost uncooled infrared microbolometer detectors that can be implemented using standard n-well CMOS processes. One type is based on a suspended n-well resistor, which is implemented in a 0.8?m CMOS process and has a pixel size of 80?m×80?m with a fill factor of 13%; and the other type is based on

Selim Eminoglu; Deniz Sabuncuoglu Tezcan; M. Yusuf Tanrikulu; Tayfun Akin

2003-01-01

327

A CMOS wireless biomolecular sensing system-on-chip based on polysilicon nanowire technology.  

PubMed

As developments of modern societies, an on-field and personalized diagnosis has become important for disease prevention and proper treatment. To address this need, in this work, a polysilicon nanowire (poly-Si NW) based biosensor system-on-chip (bio-SSoC) is designed and fabricated by a 0.35 ?m 2-Poly-4-Metal (2P4M) complementary metal-oxide-semiconductor (CMOS) process provided by a commercialized semiconductor foundry. Because of the advantages of CMOS system-on-chip (SoC) technologies, the poly-Si NW biosensor is integrated with a chopper differential-difference amplifier (DDA) based analog-front-end (AFE), a successive approximation analog-to-digital converter (SAR ADC), and a microcontroller to have better sensing capabilities than a traditional Si NW discrete measuring system. In addition, an on-off key (OOK) wireless transceiver is also integrated to form a wireless bio-SSoC technology. This is pioneering work to harness the momentum of CMOS integrated technology into emerging bio-diagnosis technologies. This integrated technology is experimentally examined to have a label-free and low-concentration biomolecular detection for both Hepatitis B Virus DNA (10 fM) and cardiac troponin I protein (3.2 pM). Based on this work, the implemented wireless bio-SSoC has demonstrated a good biomolecular sensing characteristic and a potential for low-cost and mobile applications. As a consequence, this developed technology can be a promising candidate for on-field and personalized applications in biomedical diagnosis. PMID:24080725

Huang, C-W; Huang, Y-J; Yen, P-W; Tsai, H-H; Liao, H-H; Juang, Y-Z; Lu, S-S; Lin, C-T

2013-11-21

328

Commercial Capaciflector  

NASA Technical Reports Server (NTRS)

A capacitive proximity/tactile sensor with unique performance capabilities ('capaciflector' or capacitive reflector) is being developed by NASA/Goddard Space Flight Center (GSFC) for use on robots and payloads in space in the interests of safety, efficiency, and ease of operation. Specifically, this sensor will permit robots and their attached payloads to avoid collisions in space with humans and other objects and to dock these payloads in a cluttered environment. The sensor is simple, robust, and inexpensive to manufacture with obvious and recognized commercial possibilities. Accordingly, NASA/GSFC, in conjunction with industry, is embarking on an effort to 'spin' this technology off into the private sector. This effort includes prototypes aimed at commercial applications. The principles of operation of these prototypes are described along with hardware, software, modelling, and test results. The hardware description includes both the physical sensor in terms of a flexible printed circuit board and the electronic circuitry. The software description will include filtering and detection techniques. The modelling will involve finite element electric field analysis and will underline techniques used for design optimization.

Vranish, John M.

1991-01-01

329

Advancement of CMOS Doping Technology in an External Development Framework  

NASA Astrophysics Data System (ADS)

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

330

Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability  

NASA Astrophysics Data System (ADS)

In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 ?m×16 ?m was fabricated in a 0.18 ?m CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

2013-07-01

331

CMOS Hybrid Pixel Detectors for Scientific, Industrial and Medical Applications  

NASA Astrophysics Data System (ADS)

Crystallography is the principal technique for determining macromolecular structures at atomic resolution and uses advantageously the high intensity of 3rd generation synchrotron X-ray sources . Macromolecular crystallography experiments benefit from excellent beamline equipment, recent software advances and modern X-ray detectors. However, the latter do not take full advantage of the brightness of modern synchrotron sources. CMOS Hybrid pixel array detectors, originally developed for high energy physics experiments, meet these requirements. X-rays are recorded in single photon counting mode and data thus are stored digitally at the earliest possible stage. This architecture leads to several advantages over current detectors: No detector noise is added to the signal. Readout time is reduced to a few milliseconds. The counting rates are matched to beam intensities at protein crystallography beamlines at 3rd generation synchrotrons. The detector is not sensitive to X-rays during readout; therefore no mechanical shutter is required. The detector has a very sharp point spread function (PSF) of one pixel, which allows better resolution of adjacent reflections. Low energy X-rays can be suppressed by the comparator At the Paul Scherrer Institute (PSI) in Switzerland the first and largest array based on this technology was constructed: The Pilatus 6M detector. The detector covers an area of 43.1 x 44.8 cm2 , has 6 million pixels and is read out noise free in 3.7 ms. Since June 2007 the detector is in routine operation at the beamline 6S of the Swiss Light Source (SLS). The company DETCRIS Ltd, has licensed the technology from PSI and is commercially offering the PILATUS detectors. Examples of the wide application range of the detectors will be shown.

Broennimann, Christian

2009-03-01

332

Color mixing improvement of CMOS image sensor with air-gap-guard ring in deep-submicrometer CMOS technology  

Microsoft Academic Search

In this letter, color mixings of a CMOS image sensor with air-gap-guard-ring (AGGR) and conventional structures were investigated in 0.18-?m CMOS image sensor technology. As the light incident angle is increased from 0° to 15°, conventional pixel shows serious color mixing. For example, the maximum photo responses of blue, green1, green2, and red pixels are shifted from 490 to 520

T. H. Hsu; Y. K. Fang; D. N. Yaung; S. G. Wuu; H. C. Chien; C. S. Wang; J. S. Lin; C. H. Tseng; S. F. Chen; C. S. Lin

2005-01-01

333

Optical modulation techniques for analog signal processing and CMOS compatible electro-optic modulation  

NASA Astrophysics Data System (ADS)

Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production CMOS electronics will enable new design paradigms for existing system architectures and open new opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint, weight, and power consumption of today's communication systems. While broadband analog system applications represent a smaller volume market than that for digital data transmission, there are significant deployments of analog electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block in optical analog signal processing and also could have significant applications in digital communication systems. Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges and opportunities for analog signal processing since the index and propagation loss change within the waveguide during modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques for optical modulation.

Gill, Douglas M.; Rasras, Mahmoud; Tu, Kun-Yii; Chen, Young-Kai; White, Alice E.; Patel, Sanjay S.; Carothers, Daniel; Pomerene, Andrew; Kamocsai, Robert; Beattie, James; Kopa, Anthony; Apsel, Alyssa; Beals, Mark; Mitchel, Jurgen; Liu, Jifeng; Kimerling, Lionel C.

2008-02-01

334

A Monolithic 5Bit SiGe BiCMOS Receiver for X-Band Phased-Array Radar Systems  

Microsoft Academic Search

This work presents a 5-bit receiver for X-band phased-array radar applications based on a commercially-available silicon-germanium (SiGe) BiCMOS technology. The receiver achieves a gain of 11 dB, an operational bandwidth from 8.0 to 10.7 GHz, an average noise figure of 4.1 dB, and an input-referred third-order intercept point (IIP3) of-13 dBm, while only dissipating 33 mW of power. The receiver

Jonathan P. Comeau; M. A. Morton; Wei-Min Lance Kuo; T. Thrivikraman; J. M. Andrews; C. Grens; J. D. Cressler; J. Papapolymerou; M. Mitchell

2007-01-01

335

Modeling and Manufacturing of a Micromachined Magnetic Sensor Using the CMOS Process without Any Post-Process  

PubMed Central

The modeling and fabrication of a magnetic microsensor based on a magneto-transistor were presented. The magnetic sensor is fabricated by the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process without any post-process. The finite element method (FEM) software Sentaurus TCAD is utilized to analyze the electrical properties and carriers motion path of the magneto-transistor. A readout circuit is used to amplify the voltage difference of the bases into the output voltage. Experiments show that the sensitivity of the magnetic sensor is 354 mV/T at the supply current of 4 mA.

Tseng, Jian-Zhi; Wu, Chyan-Chyi; Dai, Ching-Liang

2014-01-01

336

Commercial applications  

NASA Astrophysics Data System (ADS)

The near term (one to five year) needs of domestic and foreign commercial suppliers of radiochemicals and radiopharmaceuticals for electromagnetically separated stable isotopes are assessed. Only isotopes purchased to make products for sale and profit are considered. Radiopharmaceuticals produced from enriched stable isotopes supplied by the Calutron facility at ORNL are used in about 600,000 medical procedures each year in the United States. A temporary or permanent disruption of the supply of stable isotopes to the domestic radiopharmaceutical industry could curtail, if not eliminate, the use of such diagnostic procedures as the thallium heart scan, the gallium cancer scan, the gallium abscess scan, and the low radiation dose thyroid scan. An alternative source of enriched stable isotopes exist in the USSR. Alternative starting materials could, in theory, eventually be developed for both the thallium and gallium scans. The development of a new technology for these purposes, however, would take at least five years and would be expensive. Hence, any disruption of the supply of enriched isotopes from ORNL and the resulting unavailability of critical nuclear medicine procedures would have a dramatic negative effect on the level of health care in the United States.

337

Performance optimization of a high speed super self-aligned BiCMOS technology  

Microsoft Academic Search

The authors present the process optimization and device characteristics of a half-micron super self-aligned BiCMOS technology. With a new emitter\\/base process in their BiCMOS flow, bipolar transistor power gain cutoff frequency, fmax, has been increased from 25.9 GHz to 33.5 GHz. Since all the process parameters related to CMOS are kept constant, high speed CMOS circuit operation is maintained without

T. M. Liu; G. M. Chin; M. D. Morris; D. Y. Jeon; R. W. Johnson; V. D. Archer; M. J. Tarsia; H. H. Kim; M. Cerullo; K. F. Lee; J. M. Sung; K. Lau; M. D. Feuer; A. M. Voshchenkov; R. G. Swartz

1993-01-01

338

Monolithic integration of 5 V CMOS and high-voltage devices  

Microsoft Academic Search

A fully CMOS-compatible HVIC technology has been developed that features 5 V high-performance digital CMOS with high-voltage devices of more than 400 V. This technology uses only one or two masks in addition to standard p-well CMOS technology. Design optimization has been achieved to meet the needs of both CMOS and high-voltage devices. A large number of different devices are

Qin Huang; Gehan A. J. Amaratunga; Jean Humphrey; E. M. S. Narayanan; W. I. Milne; C. M. Starbuck

1992-01-01

339

NSC 800, 8-bit CMOS microprocessor  

NASA Technical Reports Server (NTRS)

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Suszko, S. F.

1984-01-01

340

Photon detection with CMOS sensors for fast imaging  

NASA Astrophysics Data System (ADS)

Pixel detectors employed in high energy physics aim to detect single minimum ionizing particle with micrometric positioning resolution. Monolithic CMOS sensors succeed in this task thanks to a low equivalent noise charge per pixel of around 10 to 15 e-, and a pixel pitch varying from 10 to a few 10 s of microns. Additionally, due to the possibility for integration of some data treatment in the sensor itself, readout times of 100 ?s have been reached for 100 kilo-pixels sensors. These aspects of CMOS sensors are attractive for applications in photon imaging. For X-rays of a few keV, the efficiency is limited to a few % due to the thin sensitive volume. For visible photons, the back-thinned version of CMOS sensor is sensitive to low intensity sources, of a few hundred photons. When a back-thinned CMOS sensor is combined with a photo-cathode, a new hybrid detector results (EBCMOS) and operates as a fast single photon imager. The first EBCMOS was produced in 2007 and demonstrated single photon counting with low dark current capability in laboratory conditions. It has been compared, in two different biological laboratories, with existing CCD-based 2D cameras for fluorescence microscopy. The current EBCMOS sensitivity and frame rate is comparable to existing EMCCDs. On-going developments aim at increasing this frame rate by, at least, an order of magnitude. We report in conclusion, the first test of a new CMOS sensor, LUCY, which reaches 1000 frames per second.

Baudot, J.; Dulinski, W.; Winter, M.; Barbier, R.; Chabanat, E.; Depasse, P.; Estre, N.

2009-06-01

341

Figures of merit for CMOS SPADs and arrays  

NASA Astrophysics Data System (ADS)

SPADs (Single Photon Avalanche Diodes) are emerging as most suitable photodetectors for both single-photon counting (Fluorescence Correlation Spectroscopy, Lock-in 3D Ranging) and single-photon timing (Lidar, Fluorescence Lifetime Imaging, Diffuse Optical Imaging) applications. Different complementary metal-oxide semiconductor (CMOS) implementations have been reported in literature. We present some figure of merit able to summarize the typical SPAD performances (i.e. Dark Counting Rate, Photo Detection Efficiency, afterpulsing probability, hold-off time, timing jitter) and to identify a proper metric for SPAD comparison, both as single detectors and also as imaging arrays. The goal is to define a practical framework within which it is possible to rank detectors based on their performances in specific experimental conditions, for either photon-counting or photon-timing applications. Furthermore we review the performances of some CMOS and custom-made SPADs. Results show that CMOS SPADs performances improve as the technology scales down; moreover, miniaturization of SPADs and new solutions adopted to counteract issues related with the SPAD design (electric field uniformity, premature edge breakdown, tunneling effects, defect-rich STI interface) along with advances in standard CMOS processes led to a general improvement in all fabricated photodetectors; therefore, CMOS SPADs can be suitable for very dense and cost-effective many-pixels imagers with high performances.

Bronzi, D.; Villa, F.; Bellisai, S.; Tisa, S.; Ripamonti, G.; Tosi, A.

2013-05-01

342

CMOS Cell Sensors for Point-of-Care Diagnostics  

PubMed Central

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies.

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

343

Two- and multi-terminal CMOS/BiCMOS Si LED’s  

NASA Astrophysics Data System (ADS)

Silicon is an indirect bandgap material, but light emission is observed from reverse biased pn junctions. Even though the quantum efficiency is low, it may still be advantageous to use these devices in all-silicon optoelectronic integrated circuits (OICs). In this paper new research results with regard to low-voltage field emission BiCMOS and CMOS two- and multi-terminal Si LEDs are presented. The differences observed between avalanche and low-voltage field emission LED performance are presented. It is shown that the low-voltage devices exhibit a square-law light intensity vs. reverse current non-linearity at low-current levels, but a linear dependency at higher currents, compared to the linear behaviour of avalanche devices at all current levels. The detail spectral characteristics of the field emission devices are investigated, showing that in the non-linear region of operation, the shape of the emitted spectrum changes, with reduced short wavelength generation at lower current levels. Bipolar junction transistor (BJT) multi-terminal devices are also discussed, and the square-law behaviour of these devices is presented.

du Plessis, Monuko; Aharoni, Herzl; Snyman, Lukas W.

2005-02-01

344

A study of the threshold voltage variation for ultra-small bulk and SOI CMOS  

Microsoft Academic Search

This paper addresses the scalability of bulk CMOS, and the feasibility of intrinsic channel SOI (IC-SOI) CMOS, as an alternative to the bulk, in view of the threshold voltage (VTH) fluctuations. The impact of dopant-induced VTH variations on bulk CMOS SRAM operation is evaluated using a newly proposed analytical method. It is estimated that the bulk SRAM performance will be

Kiyoshi Takeuchi; Risho Koh; Tohru Mogami

2001-01-01

345

A fast high-resolution CMOS imager for nanosecond light pulse detections  

Microsoft Academic Search

Nowadays, imagers based on CMOS active pixel sensors (APS) have performances that are competitive with those based on charge-coupled devices (CCD). CMOS imagers offer advantages in on-chip functionalities, system power reduction, cost and miniaturisation. The FAst MOS Imager (FAMOSI) project consists in reproducing the streak camera functionality with a CMOS imager. In this paper, we present the second version of

Frederic Morel; Jean-Pierre Le Normand; Chantal-Virginie Zint; Wilfried Uhring; Yann Hu; Daniel Mathiot

2004-01-01

346

A new process for CMOS MEMS capacitive sensors with high sensitivity and thermal stability  

Microsoft Academic Search

Structure curling induces thermal instability into CMOS MEMS capacitive sensors. The charging effect during reactive ion etching damages the existing on-chip MOS transistors and drastically reduces the yield rate of chips. This paper presents a novel post-CMOS process that solves the problems and leads to CMOS MEMS capacitive sensors with high sensitivity and thermal stability. The novel process was demonstrated

S. S. Tan; C. Y. Liu; L. K. Yeh; Y. H. Chiu; Klaus Y. J. Hsu

2011-01-01

347

High gain CMOS image sensor design and fabrication on SOI and bulk technology  

Microsoft Academic Search

The CMOS imager is now competing with the CCD imager, which still dominates the electronic imaging market. By taking advantage of the mature CMOS technology, the CMOS imager can integrate AID converters, digital signal processing (DSP) and timing control circuits on the same chip. This low cost and high-density integration solution to the image capture is the strong driving force

Weiquan Zhang

2000-01-01

348

BiCMOS process integration and device optimization: Basic concepts and new trends  

Microsoft Academic Search

Contents The process integration issues and the aspects of CMOS and bipolar transistor optimization in BiCMOS technology are reviewed in this article. In one section, a sample BiCMOS fabrication process is discussed to provide an entry to the subject for readers who are not familiar with the details and the nomenclature of semiconductor technology. The remainder of the paper deals

J. N. Burghartz

1996-01-01

349

A 12 mW wide dynamic range CMOS front end for a portable GPS receiver  

Microsoft Academic Search

At submicron channel lengths, CMOS is an attractive alternative to silicon bipolar and GaAs MESFET technologies for use in wireless receivers. A 12mW Global Positioning System (GPS) receiver front-end, comprising a low noise amplifier (LNA) and mixer implemented in a standard 0.35?m digital CMOS process, demonstrates the aptitude of CMOS for portable wireless applications

A. R. Shahani; D. K. Shaeffer; T. H. Lee

1997-01-01

350

On-wafer calibration techniques for giga-hertz CMOS measurements  

Microsoft Academic Search

This paper presents five different methods for performing on-wafer calibration of RF CMOS measurements. All methods are compatible with standard CMOS technology. A comparison of method performance up to 12 GHz is made with measurements on RF CMOS devices. The results verify that substrate and metallization losses must be considered to obtain high accuracy. Fixture design issues are discussed and

Troels Emil Kolding; Fredrik Bajers Vej

1999-01-01

351

Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load  

Microsoft Academic Search

This paper deals with the problem of estimating the performance of a CMOS gate driving RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is used for the representation. The CMOS gate is modeled by an Alpha Power law model, whereas the distributed RLC interconnect is represented by an equivalent ?-model. The output waveform and the

Brajesh Kumar Kaushik; Sankar Sarkar; R. P. Agarwal

2007-01-01

352

Towards a SPR-based biosensing platform incorporating a CMOS active column sensor  

Microsoft Academic Search

A biosensing platform based on surface plasmon resonance and incorporating a CMOS imager is being developed. This work comprises three different tasks towards this goal: a numerical analysis to determine the optimal plasmon resonance conditions, a numerical analysis to select the best CMOS photodiode and the architecture proposal of a CMOS imager. A simulation with COMSOL of a Kretschmann configuration

A. a Salazar; S.a Camacho-Leon; S. O. a Martínez-Chapa; O. b Rossetto

2013-01-01

353

Characterization of a monolithic silicon MEMS technology in standard CMOS process  

Microsoft Academic Search

This paper presents a comparative analysis between two specific post-processing techniques (RIE dry etching and TMAH wet etching) that are suitable for implementing a monolithic CMOS compatible MEMS fabrication technology. Further, an experimental investigation is presented which details the fabrication of MEMS structures by TMAH post etching of a CMOS chip fabricated in a standard AMI 1.5 micrometers CMOS process.

Kuntao Ye; Fred R. Beyette

2001-01-01

354

Design Considerations for CMOS-Integrated Hall-Effect Magnetic Bead Detectors for Biosensor Applications  

PubMed Central

We describe a design methodology for on-chip magnetic bead label detectors based on Hall-effect sensors. Signal errors caused by the label-binding process and other factors that limit the minimum detection area are quantified and adjusted to meet typical assay accuracy standards. The methodology is demonstrated by designing an 8192 element Hall sensor array, implemented in a commercial 0.18 ?m CMOS process with single-mask postprocessing. The array can quantify a 1% surface coverage of 2.8 ?m beads in 30 seconds with a coefficient of variation of 7.4%. This combination of accuracy and speed makes this technology a suitable detection platform for biological assays based on magnetic bead labels.

Skucha, K.; Gambini, S.; Liu, P.; Megens, M.; Kim, J.; Boser, BE

2014-01-01

355

A CMOS Humidity Sensor for Passive RFID Sensing Applications  

PubMed Central

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 ?m CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 ?W at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

356

Design and characterization of avalanche photodiodes in submicron CMOS technologies  

NASA Astrophysics Data System (ADS)

The fabrication of Avalanche Photodiodes (APDs) in CMOS processes can be exploited in several application domains, including telecommunications, time-resolved optical detection and scintillation detection. CMOS integration allows the realization of systems with a high degree of parallelization which are competitive with hybrid solutions in terms of cost and complexity. In this work, we present a linear-mode APD fabricated in a 0.15?m process, and report its gain and noise characterization. The experimental observations can be accurately predicted using Hayat dead-space noise model. Device simulations based on dead-space model are then used to discuss the current status and the perspectives for the integration of high-performance low-noise devices in standard CMOS processes.

Pancheri, L.; Bendib, T.; Dalla Betta, G.-F.; Stoppa, D.

2014-03-01

357

Design of CMOS logic gates for TID radiation  

NASA Technical Reports Server (NTRS)

The rise time, fall time and propagation delay of the logic gates were derived. The effects of total ionizing dose (TID) radiation on the fall and rise times of CMOS logic gates were obtained using C program calculations and PSPICE simulations. The variations of mobility and threshold voltage on MOSFET transistors when subjected to TID radiation were used to determine the dependence of switching times on TID. The results of this work indicate that by increasing the size of P-channel transistor with respect to the N-channel transistors of the CMOS gates, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in TID radiation.

Attia, John Okyere; Sasabo, Maria L.

1993-01-01

358

Recent progress of hybrid CMOS visible focal plane array technology  

NASA Astrophysics Data System (ADS)

Silicon-based hybrid CMOS visible focal plane array technology is emerging as a viable high performance alternative to scientific CCDs. The progress is attributed to the rapid advances in CMOS technology, mature precision flip-chip hybridization of large size and fine pixel arrays, and detector array performance improvements. Its technology readiness level (TRL) for space applications is being enhanced by relevant environmental tests and in-depth characterization of sensor performance. In this paper, we present recent results of Rockwell Scientific's hybrid CMOS silicon focal plane array technology, including large format arrays up to 2048x2048, broadband QE, sensor noise improvement, high radiation hardness, and the higher degree of system integration through on-chip ADCs and companion ASICs.

Bai, Y.; Farris, M. C.; Joshi, A.; Hosack, J. R.; Bajaj, J.; Montroy, J. T.

2005-08-01

359

A CMOS humidity sensor for passive RFID sensing applications.  

PubMed

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 ?m CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

360

IGBT scaling principle toward CMOS compatible wafer processes  

NASA Astrophysics Data System (ADS)

A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed "Structure Oriented" analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies.

Tanaka, Masahiro; Omura, Ichiro

2013-02-01

361

Operation and biasing for single device equivalent to CMOS  

DOEpatents

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

2001-01-01

362

A resistorless CMOS current reference with temperature compensation  

NASA Astrophysics Data System (ADS)

A resistorless CMOS current reference is presented. Temperature compensation is achieved by subtracting two sub-currents with different positive temperature coefficients. The circuit has been implemented with a Chartered 0.35 ?m CMOS process. The output current is 1.5 ?A, and the circuit works properly with a supply voltage down to 2 V. Measurement results show that the temperature coefficient is 98 ppm/°C, and the line regulation is 0.45%/V. The occupied chip area is 0.065 mm2.

Wei, Yan; Xin, Tian; Wenhong, Li; Ran, Liu

2011-03-01

363

A high performance 0.25 mu m CMOS technology  

Microsoft Academic Search

A high-performance 0.25- mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented. A loaded ring oscillator (NAND FI=FO=3. Cw=0.2 pF) delay per stage of 280 ps achieved (Weff\\/Leff=15 mu m\\/0.25 mu m), which is a 1.7 X improvement over 0.5- mu m CMOS technology. At shorter channel lengths (0.18 mu m),

B. Davari; W. H. Chang; M. R. Wordeman; C. S. Oh; Y. Taur; K. E. Petrillo; D. Moy; J. J. Bucchignano; H. Y. Ng; M. G. Rosenfield; F. J. Hohn; M. D. Rodriguez

1988-01-01

364

Low capacitance CMOS silicon photodetectors for optical clock injection  

NASA Astrophysics Data System (ADS)

We have studied the response of CMOS compatible detectors fabricated in a silicon-on-sapphire (SOS) process, operated under short pulse excitation in the blue. These high speed, low capacitance detectors would be suitable for very precise, surface-normal clock injection with silicon CMOS. We characterize the capacitance of the detector structure through a combination of experimental techniques and circuit-level and electromagnetic simulations. The transit-time-limited response of the detectors is validated through pump-probe experiments. Detector response times of ˜35 ps have been measured, and devices have capacitance as low as ˜4 fF.

Latif, S.; Kocabas, S. E.; Tang, L.; Debaes, C.; Miller, D. A. B.

2009-06-01

365

IR CMOS: ultrafast laser-enhanced silicon detection  

NASA Astrophysics Data System (ADS)

SiOnyx has developed a novel silicon processing technology for CMOS sensors that will extend spectral sensitivity into the near/shortwave infrared (NIR/SWIR) and enable a full performance digital night vision capability comparable to that of current image-intensifier based night vision goggles. The process is compatible with established CMOS manufacturing infrastructure and has the promise of much lower cost than competing approaches. The measured thin layer quantum efficiency is as much as 10x that of incumbent imaging sensors with spectral sensitivity from 400 to 1200 nm.

Pralle, M. U.; Carey, J. E.; Homayoon, H.; Sickler, J.; Li, X.; Jiang, J.; Miller, D.; Palsule, C.; McKee, J.

2011-05-01

366

Black silicon enhanced photodetectors: a path to IR CMOS  

NASA Astrophysics Data System (ADS)

SiOnyx has developed a novel silicon processing technology for CMOS sensors that will extend spectral sensitivity into the near/shortwave infrared (NIR/SWIR) and enable a full performance digital night vision capability comparable to that of current image-intensifier based night vision goggles. The process is compatible with established CMOS manufacturing infrastructure and has the promise of much lower cost than competing approaches. The measured thin layer quantum efficiency is as much as 10x that of incumbent imaging sensors with spectral sensitivity from 400 to 1200 nm.

Pralle, M. U.; Carey, J. E.; Homayoon, H.; Alie, S.; Sickler, J.; Li, X.; Jiang, J.; Miller, D.; Palsule, C.; McKee, J.

2010-04-01

367

Organic Field-Effect Transistors for CMOS Devices  

Microsoft Academic Search

\\u000a Organic field-effect transistors (OFETs) are the key elements of future low cost electronics such as radio frequency identification\\u000a tags. In order to take full advantage of organic electronics, low power consumption is mandatory, requiring the use of a complementary\\u000a metal oxide semiconductor (CMOS) like technique. To realize CMOS-devices p-type and n-type organic field-effect transistors\\u000a on one substrate have to be

Christian Melzer; Heinz von Seggern

2010-01-01

368

A 5GHz direct-conversion CMOS transceiver  

Microsoft Academic Search

Abstract—A CMOS transceiver fully compliant with IEEE 802.11a in the unlicensed national information infrastructure (UNII) band (5.15?5.35 GHz) achieves a receiver sensitivity of 5 dBm for 64-QAM (quadrature amplitude modulation) with an error vector magnitude (EVM) of,29.3 dB. A single-sideband mixing technique for local-oscillator signal generation avoids frequency pulling. Realized in 0.18- m,CMOS and operating from 1.8-V power supply, the

Pengfei Zhang; C. Lam; D. Gambetta; T. Soorapanth; Baohong Cheng; S. Hart; I. Sever; T. Bourdi; A. Tham; B. Razavi

2003-01-01

369

Study of BiCMOS logic gate configurations for improved low-voltage performance  

Microsoft Academic Search

A simple BiCMOS configuration employing the source-well tie PMOS\\/n-p-n pull-down combination is proposed for low-voltage, high-performance operations. The improved BiCMOS gate delay time over that of the NMOS\\/n-p-n (conventional) BiCMOS gate is confirmed by means of inverter simulations and measured ring oscillator data. The source-well tie PMOS\\/n-p-n BiCMOS gate outperforms its conventional BiCMOS counterpart in the low-voltage supply range, at

Paul G. Y. Tsui; Bernie Pappert; Shih Wei Sun; John R. Yeargain

1993-01-01

370

Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs  

NASA Astrophysics Data System (ADS)

The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. We compare RTD-CMOS and pure CMOS realizations of a network of logic gates which can be operated in a gate-level pipeline. Significant lower average power is obtained for RTD-CMOS implementations.

Nuñez, Juan; Avedillo, María J.; Quintana, José M.

2011-05-01

371

Timing and power model for CMOS inverters  

NASA Astrophysics Data System (ADS)

Nowadays, the delay, the output transition time and the short circuit power consumption of CMOS gates depend on the load capacitance and the input transition time. In currently used technology libraries, table models with 25 or more samples are used for calculating by interpolation each of these three variables. Previous work deriving analytical models are based on neglecting the short circuit current or approximating currents as piecewise linear. In the beginning of this paper, different mathematical models describing the transistor current are compared with respect to the accuracy of a numerical calculated output waveform. The results show that Sakurai's alpha-Power Model with linear equation in the linear region and exponent alpha=1 serves as a well-fitting model for the underlying 0.35 ?m technology. Based on this transistor model and the assumption of a linear rising input, the differential equation of the output voltage, including both transistor currents and the capacitive load, has to be solved. Splitting the solution into regions, an approximate solution can be derived for the case that the PMOS transistor is working in linear and the NMOS in saturation condition. The rather complex calculation of the point where the PMOS transistor switches from linear to saturation region can be simplified by using curve fitting techniques. The required curve parameters depend on technology constants as in MM9 and the quotient wn/wp. Consequently, one set of parameters allows the analysis of a wide range of inverters as long as wn/wp is kept constant. The accuracy of the results for the delay are typically within 10%, those for output transition time and power consumption within 5% compared to spice simulation.

Geißler, Richard; Pfleiderer, Hans-Jörg

2003-04-01

372

Adiabatic circuits: converter for static CMOS signals  

NASA Astrophysics Data System (ADS)

Ultra low power applications can take great advantages from adiabatic circuitry. In this technique a multiphase system is used which consists ideally of trapezoidal voltage signals. The input signals to be processed will often come from a function block realized in static CMOS. The static rectangular signals must be converted for the oscillating multiphase system of the adiabatic circuitry. This work shows how to convert the input signals to the proposed pulse form which is synchronized to the appropriate supply voltage. By means of adder structures designed for a 0.13µm technology in a 4-phase system there will be demonstrated, which additional circuits are necessary for the conversion. It must be taken into account whether the data arrive in parallel or serial form. Parallel data are all in one phase and therefore it is advantageous to use an adder structure with a proper input stage, e.g. a Carry Lookahead Adder (CLA). With a serial input stage it is possible to read and to process four signals during one cycle due to the adiabatic 4-phase system. Therefore input signals with a frequency four times higher than the adiabatic clock frequency can be used. This reduces the disadvantage of the slow clock period typical for adiabatic circuits. By means of an 8 bit Ripple Carry Adder (8 bit RCA) the serial reading will be introduced. If the word width is larger than 4 bits the word can be divided in 4 bit words which are processed in parallel. This is the most efficient way to minimize the number of input lines and pads. At the same time a high throughput is achieved.

Fischer, J.; Amirante, E.; Bargagli-Stoffi, A.; Schmitt-Landsiedel, D.

2003-05-01

373

Carbon Nanotube-Based CMOS Gas Sensor IC: Monolithic Integration of Pd Decorated Carbon Nanotube Network on a CMOS Chip and Its Hydrogen Sensing  

Microsoft Academic Search

The integration of carbon nanotube (CNT)-based sensor and readout complementary metal-oxide-semiconductor integrated chip (CMOS IC) to detect hydrogen gas in a single chip is presented. First, we have fabricated the CMOS IC us- ing the standard 0.35-µm CMOS process. Then, we have built 8 × 8 CNT-based sensor cells on it using a proposed tractable postprocessing strategy and judicious electrode

Sung Min Seo; Jun Ho Cheon; Seok Hyang Kim; Tae June Kang; Jung Woo Ko; In-Young Chung; Yong Hyup Kim; Young June Park

2011-01-01

374

An ultra-high-speed ECL-BiCMOS technology with silicon fillet self-aligned contacts  

Microsoft Academic Search

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay

Teyin M. Liu; Gen M. Chin; Duk Y. Jeon; Mark D. Morris; Robert W. Johnson; Maurice Tarsia; Helen H. Kim; Marcio Cerullo; Kwing F. Lee; JanMye James Sung; Kei-Shun Lau; Tzu-Yin Chiu; Alexander M. Voshchenkov; Robert G. Swartz

1994-01-01

375

Feasibility study of a latchup-based particle detector exploiting commercial CMOS technologies  

NASA Astrophysics Data System (ADS)

The stimulated ignition of latchup effects caused by external radiation has so far proved to be a hidden hazard. Here this effect is described as a novel approach to detect particles by means of a solid-state device susceptible to latchup effects. In addition, the device can also be used as a circuit for reading sensors devices, leaving the capability of sensing to external sensors. The paper first describes the state-of-the-art of the project and its development over the latest years, then the present and future studies are proposed. An elementary cell composed of two transistors connected in a thyristor structure is shown. The study begins using traditional bipolar transistors since the latchup effect is originated as a parasitic circuit composed of such devices. Then, an equivalent circuit built up of MOS transistors is exploited, resulting an even more promising and challenging configuration than that obtained via bipolar transistors. As the MOS transistors are widely used at present in microelectronics devices and sensors, a latchup-based cell is proposed as a novel structure for future applications in particle detection, amplification of signal sensors and radiation monitoring.

Gabrielli, A.; Matteucci, G.; Civera, P.; Demarchi, D.; Villani, G.; Weber, M.

2009-12-01

376

CMOS Ultra Low Power Radiation Tolerant (CULPRiT) Microelectronics  

NASA Technical Reports Server (NTRS)

Space Electronics needs Radiation Tolerance or hardness to withstand the harsh space environment: high-energy particles can change the state of the electronics or puncture transistors making them disfunctional. This viewgraph document reviews the use of CMOS Ultra Low Power Radiation Tolerant circuits for NASA's electronic requirements.

Yeh, Penshu; Maki, Gary

2007-01-01

377

Photon detection with CMOS sensors for fast imaging  

Microsoft Academic Search

Pixel detectors employed in high energy physics aim to detect single minimum ionizing particle with micrometric positioning resolution. Monolithic CMOS sensors succeed in this task thanks to a low equivalent noise charge per pixel of around 10 to 15 e-, and a pixel pitch varying from 10 to a few 10s of microns. Additionally, due to the possibility for integration

J. Baudot; W. Dulinski; M. Winter; R. Barbier; E. Chabanat; P. Depasse; N. Estre

2009-01-01

378

CCD AND PIN-CMOS DEVELOPMENTS FOR LARGE OPTICAL TELESCOPE.  

SciTech Connect

Higher quantum efficiency in near-IR, narrower point spread function and higher readout speed than with conventional sensors have been receiving increased emphasis in the development of CCDs and silicon PIN-CMOS sensors for use in large optical telescopes. Some key aspects in the development of such devices are reviewed.

RADEKA, V.

2006-04-03

379

Model for CMOS\\/SOI single-event vulnerability  

Microsoft Academic Search

This paper reports a lumped-parameter model derived from transistor characterization data used in SPICE analyses to study and predict the single-event upset thresholds for Texas Instruments SIMOX SOI SRAMs with a variety of cell designs. The modeling of CMOS\\/SOI transistors with fully bottomed sources and drains includes direct representation of the parasitic lateral bipolar structure.

S. E. Kerns; L. W. Massengill; Kerns D. V. Jr; M. L. Alles; T. W. Houston; H. Lu; L. R. Hite

1989-01-01

380

Modelling, calibration and rendition of colour logarithmic CMOS image sensors  

Microsoft Academic Search

Logarithmic CMOS image sensors encode a high dynamic range scene in a manner that roughly approximates human perception whereas linear sensors with equivalent quantisation suffer from saturation or loss of detail. Moreover, the continuous response of logarithmic pixels permit high frame rates and random access, features that are useful in motion detection. This paper describes how to model, calibrate and

Dileepan Joseph; Steve Collins

2002-01-01

381

An ultraminiature CMOS pressure sensor for a multiplexed cardiovascular catheter  

Microsoft Academic Search

A multiplexed ultraminiature pressure sensor designed for use in a cardiovascular catheter is reported. The sensor operates from only two leads, which are shared by two sensors per catheter. The sensing chip is 350 ?m wide by 1.4 mm long by 100 ?m thick. CMOS readout electronics at the sensing site convert applied pressure to a frequency variation in the

Jin Ji; Steve T. Cho; Yafan Zhang; Khalil Najafi; Kensall D. Wise

1991-01-01

382

Predictions of CMOS compatible on-chip optical interconnect  

Microsoft Academic Search

Interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to satisfy the design requirements of delay, power, bandwidth, and noise. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect in the past two decades. In this paper, predictions of the performance

Guoqing Chen; Hui Chen; Mikhail Haurylau; Nicholas Nelson; Philippe M. Fauchet; Eby G. Friedman; David H. Albonesi

2005-01-01

383

Effect of technology scaling on digital CMOS logic styles  

Microsoft Academic Search

In this paper, the main challenges of technology scaling are reviewed in depth. Five popular logic families, namely, conventional CMOS, CPL, Domino, DCVS and MCML are represented highlighting their advantages and drawbacks. The behavior of each logic style in deep submicron technologies is analyzed and predicted for future generations. To verify the qualitative analysis, simulations were performed on the basic

Mohamed Allam; Mohab Anis; Mohamed Elmasry

2000-01-01

384

Delay analysis of CMOS gates using modified logical effort model  

Microsoft Academic Search

In this paper, modified logical effort (MLE) technique is proposed to provide delay estimation for CMOS gates. The model accounts for the behavior of series-connected MOSFET structure (SCMS), the input transition time, and internodal charges. Also, the model takes into account deep submicron effects, such as mobility degradation and velocity saturation. This model exhibits good accuracy when compared with Spectre

Adnan Kabbani; Dhamin Al-khalili; Asim J. Al-khalili

2005-01-01

385

High speed CMOS/SOS standard cell notebook  

NASA Technical Reports Server (NTRS)

The NASA/MSFC high speed CMOS/SOS standard cell family, designed to be compatible with the PR2D (Place, Route in 2-Dimensions) automatic layout program, is described. Standard cell data sheets show the logic diagram, the schematic, the truth table, and propagation delays for each logic cell.

1978-01-01

386

Impact of technology scaling on CMOS logic styles  

Microsoft Academic Search

In this paper, the main challenges of technology scaling are reviewed in depth. Five popular logic families namely; conventional CMOS, complementary pass logic, Domino, differential cascode voltage switch logic, and current mode logic are presented, highlighting their advantages and drawbacks. The behavior of each logic style in deep submicrometer technologies is analyzed and predicted for future technology generations. To verify

Mohab Anis; Mohamed Allam; Mohamed Elmasry

2002-01-01

387

Design, measurement and analysis of CMOS polysilicon TFT operational amplifiers  

Microsoft Academic Search

The small signal properties of polysilicon TFT opamps have been investigated in this paper. A method for the scaling of gm (transconductance) and gds (output conductance) has been proposed, facilitating their estimates for various transistors in operational amplifiers. The analysis of two CMOS opamps fabricated by a low temperature, glass compatible poly-Si TFT process is demonstrated in comparison to the

Hai-Gang Yang; Steve Fluxman; Carlo Reita; Piero Migliorato

1994-01-01

388

Integrated CMOS wireless power transfer for neural implants  

Microsoft Academic Search

Wireless power transfer is commonly realized by means of near-field inductive coupling and is critical to many existing and emerging applications in biomedical engineering. We present simulation results that support the possibility of an integrated receiver coil on a CMOS substrate useful for neural implants. It is shown that by following simple guidelines such structures can deliver power in the

Meysam Zargham; P. Glenn Gulak

2011-01-01

389

CMOS current amplifiers exhibiting independent AC and DC current amplification  

Microsoft Academic Search

A CMOS circuit topology is demonstrated for the amplification of high-frequency AC currents without requiring similar DC current amplification. This technique is useful for current-domain amplification and processing of signals when low DC power consumption is necessary. Large amounts of AC gain can be achieved using this technique without requiring equivalent DC current gain, which would increase power consumption. Two

Drew Guckenberger; Kevin Kornegay

2005-01-01

390

A 900 MHz low phase noise CMOS quadrature oscillator  

Microsoft Academic Search

A novel method for designing quadrature oscillators is presented. The technique is based on differential coupling at the second harmonic frequency of two separate oscillators. The desired coupling is obtained using an integrated transformer which is attached to the common-mode nodes of two differential oscillators. A 900 MHz prototype has been implemented in a 0.35 ?m CMOS process. The oscillator

Josk Cabanillas; Laurent Dussopt; J. M. Lopez-Villegas; G. M. Rebeiz

2002-01-01

391

Thin Film on CMOS Active Pixel Sensor for Space Applications  

PubMed Central

A 664 × 664 element Active Pixel image Sensor (APS) with integrated analog signal processing, full frame synchronous shutter and random access for applications in star sensors is presented and discussed. A thick vertical diode array in Thin Film on CMOS (TFC) technology is explored to achieve radiation hardness and maximum fill factor.

Schulze Spuentrup, Jan Dirk; Burghartz, Joachim N.; Graf, Heinz-Gerd; Harendt, Christine; Hutter, Franz; Nicke, Markus; Schmidt, Uwe; Schubert, Markus; Sterzel, Juergen

2008-01-01

392

New power saving design method for CMOS flash ADC  

Microsoft Academic Search

A new power saving design method for CMOS flash ADC is presented. With an inverter as a comparator along with an NMOS and a PMOS as switches, we use bisection method to let only half of comparators in flash ADC working in every clock cycle. An example of 6-bit flash ADC operates at 200 MHz sampling rate and 3.3 V

Chia-Chun Tsai; Kai-Wei Hong; Yuh-Shyan Hwang; Wen-Ta Lee; Trong-Yen Lee

2004-01-01

393

Upper-Bound Estimates Of SEU in CMOS  

NASA Technical Reports Server (NTRS)

Theory of single-event upsets (SEU) (changes in logic state caused by energetic charged subatomic particles) in complementary metal oxide/semiconductor (CMOS) logic devices extended to provide upper-bound estimates of rates of SEU when limited experimental information available and configuration and dimensions of SEU-sensitive regions of devices unknown. Based partly on chord-length-distribution method.

Edmonds, Larry D.

1990-01-01

394

Testing for bridging faults (shorts) in CMOS circuits  

Microsoft Academic Search

The stuck-at fault model, which is commonly used with fault simulation, does not adequately evaluate the effects of bridging faults (shorts between adjacent signal lines) in CMOS circuits. Tests for bridging faults can be performed on automatic test equipment, and the test vectors can be evaluated using logic simulation.

John M. Acken

1983-01-01

395

Space-variant nonorthogonal structure CMOS image sensor design  

Microsoft Academic Search

A CMOS log-polar image sensor has been designed and fabricated. As a result, a systematic approach has been proposed to design space-variant sensors and layouts. The pixels in this sensor are distributed in a polar fashion; the image plane consists of concentric rings containing the elementary sensing cells. Such a structure, where polygons use any space orientation, does not match

Fernando Pardo; Bart Dierickx; Danny Scheffer

1998-01-01

396

Current-mode CMOS image sensor using lateral bipolar phototransistors  

Microsoft Academic Search

A current-mode image sensor has been designed using current mirrors with amplifying device ratios. Prototype sensors have been fabricated in a standard 0.18-?m CMOS technology. Image capture is demonstrated from two 70 × 48 pixel arrays, using photodiodes and lateral bipolar phototransistors as the photodetectors. The latter type displays a reduced fixed pattern noise, while linearity is similar to that

Ying Huang; Richard I. Hornsey

2003-01-01

397

A CMOS image sensor zero power dynamic range increasing technique  

Microsoft Academic Search

A development of in-pixel dynamic range (DR) increasing technique without charging extra power for CMOS image sensor was realized in this paper. Recently, many researches reported that high dynamic range can be achieved through processing the image signals with ADCs or counters built inside the pixel, and some other methods require adjustable circuit block to maneuver photo-generated charges by a

Tsung-Hsun Tsai; Ching-Chun Wang

2009-01-01

398

Through silicon vias technology for CMOS image sensors packaging  

Microsoft Academic Search

In this paper a low temperature 'via-last' technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. The design rules of the vias will be briefly described and then, the steps of the technology will be presented : glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific

D. Henry; F. Jacquet; M. Neyret; X. Baillin; T. Enot; V. Lapras; C. Brunet-Manquat; J. Charbonnier; B. Aventurier; N. Sillon

2008-01-01

399

di\\/dt Noise in CMOS Integrated Circuits  

Microsoft Academic Search

This is an overview paper presenting di\\/dtnoise from a designer‘s perspective. Analysis and circuit designtechniques are presented taking package parasitics into account.The main focus is on digital CMOS design, but analysis and designsuggestions can easily be extended to mixed-mode design.

Patrik Larsson

1997-01-01

400

QE reduction due to pixel vignetting in CMOS image sensors  

Microsoft Academic Search

CMOS image sensor designers take advantage of technology scaling either by reducing pixel size or by adding more transistors to the pixel. In both cases, the distance from the chip surface to the photodiode increases relative to the photodiode planar dimensions. As a result, light must ravel through an increasingly deeper and narrower `tunnel' before it reaches the photodiode. This

Peter B. Catrysse; Xinqiao Liu; Abbas El Gamal

2000-01-01

401

Band Distributed Microelectromechanical Components Based on CMOS Compatible Fabrication  

Microsoft Academic Search

Microelectromechanical systems (MEMS) technology has been used for realizing G-band (140-220 GHz) distributed MEMS transmission line components. Novel dielectric-less MEMS components, as well as switched MEMS capacitors, have been fabricated with CMOS compatible surface micromachining, and experimental results are presented up to 220 GHz.

Tauno Vaha-Heikkila; Mari Ylonen

2008-01-01

402

Complementary MetalâÂÂOxideâÂÂSemiconductor (CMOS) Simulation  

NSDL National Science Digital Library

This resource is an Interactive Complementary metalâÂÂoxideâÂÂsemiconductor (CMOS) simulation. All the different variables can be modified to represent different aspects of this simulation. Results are presented once the calculations are made. This can be a useful resource for those involved in engineering or physics.

2010-10-26

403

CMOS LSI DSP and its application to voice band signals  

Microsoft Academic Search

This paper describes a newly developed CMOS LSI DSP and its application to a 32 Kbps ADPCM CODEC and a 4,800 bps data MODEM. The paper first analizes the required memory capacities of ROM and RAM as a function of arithmatic operation capability of DSP. Based on the results, the LSI DSP is developed, which has a proper amount of

T. Tsuda; K. Murano; S. Unagami; M. Shimada; H. Kikuchi; S. Sumi; Y. Miwa

1983-01-01

404

Integrated imaging sensor systems with CMOS active pixel sensor technology  

NASA Technical Reports Server (NTRS)

This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

2002-01-01

405

Digitally controlled fully differential current conveyor: CMOS realization and applications  

Microsoft Academic Search

Design and simulation of a digitally controlled CMOS fully differential current conveyor (DCFDCC) is presented. A novel current division network (CDN) is used to provide the digital control of the current gain between terminals X and Z of this DCFDCC. The proposed DCFDCC operates under low supply voltage of ±1.5V. Application of the DCFDCC in realizing second order universal active

Soliman A. Mahmoud; Mohammed A. Hashiesh; Ahmed M. Soliman

2005-01-01

406

A CMOS SLIC with an automatic balancing hybrid  

Microsoft Academic Search

A multifuction CMOS subscriber line interface circuit, which includes an automatic balancing hybrid, a IdB step gain control, a ringing filter with 20dB attenuation at 16Hz, and a switching regulator battery feed control, will be covered.

H. Shirasu; M. Shibukawa; E. Amada; Y. Hasegawa; F. Fujii; K. Yasunari; Y. Toba

1983-01-01

407

Time-Delay-Integration Architectures in CMOS Image Sensors  

Microsoft Academic Search

Difficulty and challenges of implementing time-delay-integration (TDI) functionality in a CMOS technology are studied: synchronization of the samples forming a TDI pixel, adder matrix outside the array, and addition noise. Existing and new TDI sensor architecture concepts with snapshot shutter, rolling shutter, or orthogonal readout are presented. An optimization method is then introduced to inject modulation transfer function and quantum

Gérald Lepage; Jan Bogaerts; Guy Meynants

2009-01-01

408

Total dose effects on CMOS active pixel sensors  

Microsoft Academic Search

Co60 irradiations have been carried out on test structures for the development of CMOS Active Pixel Sensors that can be used in a radiation environment. The basic mechanisms that may cause failure are presented. Ionization induced damage effects such as field leakage currents and dark current increase are discussed in detail. Two different approaches to overcome these problems are considered

Jan Bogaerts; Bart Dierickx

2000-01-01

409

SEMICONDUCTOR INTEGRATED CIRCUITS: All-CMOS temperature compensated current reference  

NASA Astrophysics Data System (ADS)

This paper presents a novel temperature independent current reference based on the theory of mutual compensation of mobility and threshold voltage. It is completely compatible with standard CMOS-technology. The experiment results indicate that the temperature coefficient of this current reference is less than 290 ppm/°C over a temperature range from -20 to 110°C.

Zhe, Zhao; Feng, Zhou; Shengzhuan, Huang

2010-06-01

410

A CMOS RISC CPU with on-chip parallel cache  

Microsoft Academic Search

This CMOS CPU in a 0.55 ?m, 3-metal process integrates over 1.2 M transistors on a single chip. All circuitry on-chip operates at 140 MHz under typical conditions. All off-chip interfaces are cycled at the same frequency (with the exception of system bus interface, which is cycled at 120 MHz). Chip parameters are given

Ehsan Rashid; Eric Delano; Ken Chan; Michael Buckley; J. Zheng; F. Schumacher; G. Kurpanek; J. Shelton; T. Alexander; N. Noordeen; M. Ludwig; A. Scherer; C. Amir; D. Cheung; P. Sabada; R. Rajamani; N. Fiduccia; B. Ches; K. Eshghi; F. Eatock; D. Renfrow; J. Keller; P. Ilgenfritz; I. Krashinsky; D. Weatherspoon; S. Ranade; D. Goldberg; W. Bryg

1994-01-01

411

Effect of a polywell leometry on a CMOS photodiode array  

Microsoft Academic Search

The effect of a polywell geometry hybridized with a stacked gradient poly-homojunction architecture, on the response of a CMOs compatible photodiode array was simulated. Crosstalk and sensitivity improved compared to the polywell geometry alone, for both back and front illumination.

Paul V. Jansz; Steven Hinckley; Graham Wild

2010-01-01

412

Effect of a Polywell geometry on a CMOS Photodiode Array  

Microsoft Academic Search

The effect of a polywell geometry hybridized with a stacked gradient poly-homojunction architecture, on the response of a CMOs compatible photodiode array was simulated. Crosstalk and sensitivity improved compared to the polywell geometry alone, for both back and front illumination

Paul V Jansz; Steven Hinckley; Graham Wild

2010-01-01

413

Design and performance of a 10 MHz cmos analog pipeline  

Microsoft Academic Search

The development of an analog pipeline which will be used for the readout of the ZEUS high-resolution calorimeter is described. The pipeline will be built in CMOS-technology and will use the switched capacitor technique. Performance tests of a test chip which incorporates the main features of the pipeline are presented. The following results on the main parameters have been achieved:

W. Buttler; A. Caldwell; C. Hayes; L. Hervas; A. Hofmann; B. Hosticka; R. Klanner; U. Kötz; P. Malecki; J. Möschen; J. del Peso; U. Schöneberg; W. Sippach

1989-01-01

414

Indirect feedback compensation of CMOS op-amps  

Microsoft Academic Search

This paper presents the design of CMOS op-amps using indirect feedback compensation technique. The indirect feedback compensation results in much faster and low power op-amps, significant reduction in the layout size and better power supply noise rejection

Vishal Saxena; R. Jacob Baker

2006-01-01

415

Hybrid cascode compensation for two-stage CMOS operational amplifiers  

Microsoft Academic Search

This paper presents the analysis of hybrid cascode compensation scheme which is used in two-stage CMOS operational transconductance amplifiers (OTAs). The open loop signal transfer function is derived to allow the accurate estimation of the poles and zeros. This analytical approach shows that the non- dominant poles and zeros of the hybrid cascode compensation are about 40 percent greater than

Mohammad Yavari; Omid Shoaei; Francesco Svelto

2005-01-01

416

Design and CAD challenges in 45nm CMOS and beyond  

Microsoft Academic Search

With semiconductor industry's aggressive march towards 45nm CMOS technology and introduction of new materials and device structures in sight for 32nm and 22nm nodes, it is crucial for the IC design and CAD community to understand the challenges posed by these potential technology changes. This tutorial will focus on these challenges starting from front end of line (devices) to the

David J. Frank; Ruchir Puri; Dorel Toma

2006-01-01

417

A fuzzy optimization method for CMOS operational amplifier design  

Microsoft Academic Search

The aim of the paper is to present a fuzzy method for the optimization of the CMOS operational amplifier design. Our method uses fuzzy systems or fuzzy sets in all stages involved in the optimization process. In order to reduce the time spent for circuit performance evaluation, we use fuzzy system to model each circuit performance. The optimization problem formulation

Gabriel OLTEAN; Costin MIRON; S. Zahan; Mihaela GORDAN

2000-01-01

418

CMOS Active-Pixel Image Sensor With Simple Floating Gates  

NASA Technical Reports Server (NTRS)

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

419

Low-power 2-D fully integrated CMOS fluxgate magnetometer  

Microsoft Academic Search

In this paper, we present a low-power, two-axis fluxgate magnetometer. The planar sensor is integrated in a standard CMOS process, which provides metal layers for the coils and electronics for the signal extraction and processing. The ferromagnetic core is placed diagonally above the four excitation coils by a compatible photolithographic post process, performed on a whole wafer. The sensor works

Predrag M. Drljaca; Pavel Kejik; Franck Vincent; Dominique Piguet; Radivoje S. Popovic

2005-01-01

420

A CMOS integrated circuit for pulse-shaped discrimination  

Microsoft Academic Search

A CMOS integrated circuit (IC) for pulse-shape discrimination (PSD) has been developed. The IC performs discrimination of gamma-rays and neutrons as part of a system monitoring stored nuclear materials. The method implemented extracts the pulse tail decay time constant using a leading edge trigger for identifying the start of the pulse and a constant fraction discriminator (CFD) to determine the

S. S. Frank; M. N. Ericson; M. L. Simpson; R. A. Todd; D. P. Hutchinson

1995-01-01

421

CMOS Chemical and Biochemical Sensors using Nanostructured Materials  

Microsoft Academic Search

A review of the recent progress in complementary metal oxide semiconductor (CMOS) biological and chemical optical sensors using nanostructured materials is presented. Fabrication details of a xerogel based glucose sensor and a photonic bandgap based chemical vapor sensor are also demonstrated.

Sung Jin Kim; Vamsy P. Chodavarapu; A. H. Titus; Frank V. Bright; Venu Govindaraju; A. N. Cartwright

2007-01-01

422

A new design of the CMOS full adder  

Microsoft Academic Search

By using the transmission function theory, two CMOS full adders are designed, both of which have simpler circuits than the conventional full adder. Computer simulations with SPICE2G5 show that they can realize the expected logic functions and they have desirable transfer characteristics

Nan Zhuang; Haomin Wu

1992-01-01

423

Mitigation of pixel scaling effects in CMOS image sensors  

Microsoft Academic Search

Over the last decade, the pixels that make up CMOS image sensors have steadily decreased in size. This scaling has two effects: first, the amount of light incident on each pixel decreases, reducing the photodiode signal and making optical efficiency, i.e., the collection of each photon, more important. Second, spatial optical crosstalk increases because diffraction comes into play when pixel

Christian C. Fesenmaier; Peter B. Catrysse

2008-01-01

424

Modeling, calibration, and rendition of color logarithmic CMOS image sensors  

Microsoft Academic Search

Logarithmic CMOS image sensors encode a high dynamic range scene in a manner that roughly approximates human perception whereas linear sensors with equivalent quantization suffer from saturation or loss of detail. Moreover, the continuous response of logarithmic pixels permit high frame rates and random access, features that are useful in motion detection. This paper describes how to model, calibrate, and

Dileepan Joseph; Steve Collins

2003-01-01

425

Integrated Polarization Analyzing CMOS Image Sensor for Material Classification  

Microsoft Academic Search

Material classification is an important application in computer vision. The inherent property of materials to partially polarize the reflected light can serve as a tool to classify them. In this paper, a real-time polarization sensing CMOS image sensor using a wire grid polarizer is proposed. The image sensor consist of an array of 128 128 pixels, occupies an area of

Mukul Sarkar; David San Segundo San Segundo Bello; Chris van Hoof; Albert Theuwissen

2011-01-01

426

Fabrication of PVA Micropolarizer Arrays for a CMOS Image Sensor  

Microsoft Academic Search

Most image sensors ignore the polarity of light signals, primarily because the human eye is not sensitive to polarization. However, it is possible to gather valuable information about geometry and composition based on the polarity of light reflecting off of an object. A polarization sensor has been designed combining a CMOS image sensor with micropolarizers fabricated out of polarizing polyvinyl

Jan Van der Spiegel; Viktor Gruev

427

A CMOS analog front end for 9600BPS facsimile modem  

Microsoft Academic Search

A chip containing a bandpass filter with a dynamic fange of 81dB, and a zero crossing detector capable of operating with a -50dB signal, will be presented. The 15mm2IC implemented in 2?m CMOS dissipates 35mW at 5V.

Cheng-Chung Shih; Kwai-Kwong Lam; Kuang-Lu Lee; R. Schalk

1987-01-01

428

CMOS VLSI Layout and Verification of a SIMD Computer  

NASA Technical Reports Server (NTRS)

A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

Zheng, Jianqing

1996-01-01

429

Predictions of CMOS compatible on-chip optical interconnect  

Microsoft Academic Search

Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect

Guoqing Chen; Hui Chen; Mikhail Haurylau; Nicholas A. Nelson; David H. Albonesi; Philippe M. Fauchet; Eby G. Friedman

430

Development of an integrated CMOS DNA detection biochip  

Microsoft Academic Search

This paper presents a CMOS DNA detection biochip using an electrical detection method with self-assembly multilayer gold nanoparticles (AuNPs). Each measuring spot of this biochip consists of three major parts; a pair of electrodes with a nanogap, a current amplifier circuit, and a heater with an embedded temperature sensor. The biochip is first fabricated by a TSMC (Taiwan Semiconductor Manufacturing

Yi-Ting Cheng; Chien-Ying Tsai; Ping-Hei Chen

2007-01-01

431

CMOS Programmable Imager Implementing Pre-Processing Operations  

Microsoft Academic Search

The CMOS Imager presented integrates a 2D photoreceptor array with a nine input analog processor on the same focal plane. The analog processor is fully programmable, performing multiply-accumulate operations. A VLSI implementation of spatial convolution operations performed on images is presented. A modified photoreceptor is presented that is based on current mode for signal transmission, thus decreasing the effect of

Khaled N. Salama; Ahmed M. El-Tawil; Ahmed M. Soliman; Hassan O. Elwan

1999-01-01

432

Fast-Recovery CMOS Voltage Regulator for Large Capacitive Loads  

Microsoft Academic Search

This paper presents a CMOS voltage regulator that ensures very fast output voltage recovery when a large capacitive load is connected to its output node. The presented scheme has been developed to allow accurate sensing without degrading memory access time in a Phase-Change Memory (PCM) device. Nevertheless, the scheme is suitable for other applications in which large capacitive loads are

F. Bedeschi; C. Boffino; E. Bonizzoni; O. Khouri; C. Resta; G. Torelli

433

A low voltage CMOS constant current-voltage reference circuit  

Microsoft Academic Search

The proposed CMOS current-voltage reference circuit consists of a traditional bandgap circuit based on the use of PMOS transistors in weak inversion. Its current is stabilized by an on-chip resistor with positive temperature coefficient. The voltage reference is produced by compensating the positive temperature coefficient of a resistor by the negative temperature coefficient of the diode connected PMOS transistor by

Ilkka Nissinen; Juha Kostamovaara

2004-01-01

434

Novel Ferroelectric CMOS Circuits as a Nonvolatile Logic  

NASA Astrophysics Data System (ADS)

We propose a novel and promising nonvolatile-logic circuit constructed by p channel type (Pch) and n channel type (Nch) ferroelectric gate field effect transistors (FeFETs), which we named a ferroelectric CMOS (FeCMOS) circuit. The circuit works as both logic and memory. We fabricated a NOT logic FeCMOS device which have Pt metal gates and gate oxides of ferroelectric SrBi2Ta2O9 (SBT) and high-k HfAlO on Si. Key technology was adjusting threshold voltages of the FeFETs as well as preparing those of high quality. We demonstrate basic operations of the NOT-logic response, memory writing, holding and non-destructive reading. The memory writing is done by amplifying the input node voltage to a higher level when the node was logically high and to a lower one when it was logically low just before the writing operation. The data retention was also measured. The retained high and low voltages were almost unchanged for 1.2 days. The idea of this FeCMOS will enhance flexibility of circuit designing by merging logic and memory functions. This work was partially supported by NEDO.

Takahashi, M.; Horiuchi, T.; Li, Q.-H.; Wang, S.; Yun, K. Y.; Sakai, S.

2008-03-01

435

Research-grade CMOS image sensors for demanding space applications  

NASA Astrophysics Data System (ADS)

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

2004-06-01

436

Research-grade CMOS image sensors for remote sensing applications  

NASA Astrophysics Data System (ADS)

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding space applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this paper will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments and performances of CIS prototypes built using an imaging CMOS process will be presented in the corresponding section.

Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Martin-Gonthier, Philippe; Corbiere, Franck; Belliot, Pierre; Estribeau, Magali

2004-11-01

437

Fabrication of a grating light modulator using standard CMOS processes  

Microsoft Academic Search

A deformable grating light modulator (GLM) also known as a grating light valve TM (GLV) offers fast switching time, low loss, and potential simplicity in fabrication, which are desirable for free-space optical switching systems. The purpose of this paper is to report on the fabrication of a GLM using standard CMOS technology and its simulation results, for use as both

Araya Pothisorn; Alex J Hariz; Bruce Wedding; Opas Trithaveesak

2011-01-01

438

An implantable CMOS circuit interface for multiplexed microelectrode recording arrays  

Microsoft Academic Search

A second-generation multichannel probe designed for measuring single-unit activity in neural structures is described. The probe includes CMOS circuitry for electronically positioning the recording sites with respect to the active neurons and for amplifying and multiplexing the recorded signals. The probe selects eight active recording sites from among 32 on the probe shank using a static input channel selector. The

Jin Ji; Kensall D. Wise

1992-01-01

439

CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)  

Microsoft Academic Search

Perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated. The unique process used to fabricate these devices allow them to be integrated with FinFET devices. Device and circuit simulations have been used to explain the device and explore new applications using this device. A novel application of the MIGFET as a signal mixer

L. Mathew; Y. Du; A. V.-Y. Thean; M. Sadd; A. Vandooren; C. Parker; T. Stephens; R. Mora; R. Rai; M. Zavala; D. Sing; S. Kalpat; J. Hughes; R. Shimer; S. Jallepalli; G. Workman; W. Zhang; J. G. Fossum; B. E. White; B.-Y. Nguyen; J. Mogab

2004-01-01

440

Advanced gate dielectrics for thin film and CMOS transistors  

Microsoft Academic Search

As semiconductor device technology evolves, the industry continues to place more stringent limits on the acceptable physical and electrical properties of materials used to make transistors. Of these materials, the gate dielectric is one of the most critical to thin film and CMOS transistor performance. We have investigated very low temperature (<150°C) plasma enhanced chemical vapor deposited hydrogenated silicon nitride,

Tonya Micah Klein

1999-01-01

441

Power estimation tool for sub-micron CMOS VLSI circuits  

Microsoft Academic Search

Accurate and fast time-domain current waveform simulation is important for the design of reliable CMOS VLSI circuits. Previous approaches for switch level current simulations used simple current models that did not match accurately the supply current. In this paper, we present a detailed current model that resulted in a maximum of 10% deviation from the current waveforms as obtained by

F. Rouatbi; Baher Haroun; Asim J. Al-Khalili

1992-01-01

442

A High Temperature SOI CMOS NO2 Sensor  

NASA Astrophysics Data System (ADS)

For more than 20 years researchers have been interested in developing micro-gas sensors based on silicon technology. Most of the reported devices are based on micro-hotplates, however they use materials that are not CMOS compatible, and therefore are not suitable for large volume manufacturing. Furthermore, they do not allow the circuitry to be integrated on to the chip. CMOS compatible devices have been previously reported. However, these use polysilicon as the heater material, which has long term stability problems at high temperatures. Here we present low power, low cost SOI CMOS NO2 sensors, based on high stability single crystal silicon P+ micro-heaters platforms, capable of measuring gas concentrations down to 0.1 ppm. We have integrated a thin tungsten molybdenum oxide layer as a sensing material with a foundry-standard SOI CMOS micro-hotplate and tested this to NO2. We believe these devices have the potential for use as robust, very low power consumption, low cost gas sensors.

Ali, S. Z.; Ho, W. O.; Chowdhury, M. F.; Covington, J. A.; Moseley, P.; Saffell, J.; Gardner, J. W.; Udrea, F.

2011-09-01

443

A 60GHz direct-conversion CMOS receiver  

Microsoft Academic Search

A direct-conversion receiver incorporates folded microstrip lines to create resonance at 60GHz in a common-gate LNA and active mixers. Realized in 0.13 ?m CMOS technology, it provides a voltage gain of 28dB with 12.5dB NF while consuming 9mW from a 1.2V supply.

B. Razavi

2005-01-01

444

CMOS technology characterization for analog and RF design  

Microsoft Academic Search

The design of analog and radio-frequency (RF) circuits in CMOS technology becomes increasingly more difficult as device modeling faces new challenges in deep submicrometer processes and emerging circuit applications. The sophisticated set of characteristics used to represent today's “digital” technologies often proves inadequate for analog and RF design, mandating many additional measurements and iterations to arrive at an acceptable solution.

Behzad Razavi

1999-01-01

445

Demonstration of a Frequency-Demodulation CMOS Image Sensor  

Microsoft Academic Search

A frequency-demodulation CMOS image sensor for capturing images only by the modulated light is proposed and demonstrated. The pixel circuit has two FD (floating diffusion) for accumulating signal charges and one photo-gate for detecting the modulated light and the background light. By operating the image sensor synchronously with a frequency and a phase of the modulated light, signal charges generated

Koji Yamamoto; Keiichiro Kagawa; Jun Ohta; Masahiro Nunoshita

446

Design of a CMOS Tapered Cascaded Multistage Distributed Amplifier  

Microsoft Academic Search

This paper presents the design and measurement of a distributed amplifier (DA) in a standard 90-nm CMOS process. To improve the gain and bandwidth (BW) of the DA, the use of an elevated coplanar waveguide line and also impedance tapering in the synthesized sections are proposed. The effects of elevation and shielding filaments on the impedance, loss, and effective dielectric

Amin Arbabian; Ali M. Niknejad

2009-01-01

447

Contact CMOS imaging of gaseous oxygen sensor array  

PubMed Central

We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

2014-01-01

448

CMOS VLSI Active-Pixel Sensor for Tracking  

NASA Technical Reports Server (NTRS)

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The diagonal-switch and memory addresses would be generated by the on-chip controller. The memory array would be large enough to hold differential signals acquired from all 8 windows during a frame period. Following the rapid sampling from all the windows, the contents of the memory array would be read out sequentially by use of a capacitive transimpedance amplifier (CTIA) at a maximum data rate of 10 MHz. This data rate is compatible with an update rate of almost 10 Hz, even in full-frame operation

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

449

High-Voltage-Input Level Translator Using Standard CMOS  

NASA Technical Reports Server (NTRS)

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

2011-01-01

450

A Merged CBi-CMOS Gate Array With Emitter Follower Buffers  

Microsoft Academic Search

A new Merged Complementary Emitter Follower BiCMOS (C-EF-BiCMOS) circuit with a double Darlingtcn diode, permits the use of FET!: below a quarter of micron, while keeping 3.6V power supply. A loaded speed of 180ps is possible with teff = 0.35um in one of the simplest BiCMOS technology. A complete circuit family implemented in a gate array structure with very high

G. Boudon; Seiki Ogura; Pascal Tannhof; F. Wallart; P. Mollier; J. P. Nuez; D. Omet; R. Cullet; D. Plassat; Robert Trauet; D. Mauchaufee

1991-01-01

451

X-ray laminographic application of lens-coupled CMOS detector for PCB inspection  

Microsoft Academic Search

A lens-coupled CMOS detector has been tested for the application in X-ray laminography, which is a tomographic technique recently popular in the nondestructive inspection of printed circuit boards (PCBs). The lens-coupled CMOS detector is extremely cost-effective because of the simple configuration and the well-known CMOS technology. For the feasibility test, we have acquired X-ray images at various imaging conditions and

Ho Kyung Kim; Sung Chae Jeon; Gyuseong Cho; Seong-Hoon Lim

2001-01-01

452

Stacked silicon CMOS circuits with a 40Mb\\/s through-silicon optical interconnect  

Microsoft Academic Search

Optical interconnection through stacked silicon foundry complementary metal-oxide-semiconductor (CMOS) circuitry has been demonstrated at a data rate of over 40 Mb\\/s with an open eye diagram. The system consists of a 0.8-?m transmitter and receiver realized in foundry digital CMOS. The use of digital CMOS enables on-chip integration with more complex digital systems, such as a microprocessor. Two layers of

Olivier Vendier; Steven W. Bond; Myunghee Lee; Sungyung Jung; Martin Brooke; Nan Marie Jokerst; Richard P. Leavitt

1998-01-01

453

Performance predictions of scaled BiCMOS gates using physical simulation  

Microsoft Academic Search

The necessary reduction in supply voltage for future scaled-down BiCMOS technologies will cause a degradation in speed because the base-emitter forward voltage drop is not scaled. The analysis of how the performance difference between BiCMOS and CMOS changes with scaling has been ambiguous in previous work because of insufficient model accuracy. In this work, mixed-level device-circuit simulation with accurate numerical

T. Arnborg

1992-01-01

454

1.5 ?m NOVA BiCMOS for Gb\\/s system application  

Microsoft Academic Search

BiCMOS technology which merges optimal CMOS and bipolar device structure is reported. Based on a nonoverlapping super-self-aligned structure (NOVA), the latest 1.5-?m CMOS and ECL (emitter-coupled logic) ring oscillators have minimum delays of 110 ps\\/stage and 87 ps\\/stage, respectively. A frequency divider operating up to 4.6 GHz has been fabricated. A multiplexer and demultiplexer function up to 5.1 Gb\\/s. In

T.-Y. Chiu; G. M. Chin; M. Y. Lau; R. C. Hanson; M. D. Morris; K. F. Lee; A. M. Voshchenkov; R. G. Swartz; V. D. Archer; M. T. Y. Liu; S. N. Finegan; M. D. Feuer

1989-01-01

455

Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation  

Microsoft Academic Search

A novel low-power CMOS synchronous counter whose clock-gating logic is embedded into a carry propagation circuit is proposed. The proposed synchronous counter operates with no redundant transitions and requires fewer transistors, minimizing the switching power consumption and silicon area as compared with conventional CMOS synchronous counters. The proposed synchronous counter consisting of 16 bits was fabricated in 0.18-mum CMOS technology.

Young-Won Kim; Joo-Seong Kim; Jae-Hyuk Oh; Yoon-Suk Park; Jong-Woo Kim; Kwang-Il Park; Bai-Sun Kong; Young-Hyun Jun

2009-01-01

456

Optical sources, integrated optical detectors, and optical waveguides in standard silicon CMOS integrated circuitry  

Microsoft Academic Search

A series of light emitting devices were designed and realized with a standard 2 micron CMOS technology, 1.2 micron CMOS technology and 0.8 micron Bi-CMOS integrated circuit fabrication technology. The devices operated in the reverse breakdown avalanche mode, at voltage levels of 8 - 20 V and in the current range 80 (mu) A - 10 mA. The devices emit

Lukas W. Snyman; Herzl Aharoni; Alice Biber; Alfons Bogalecki; Lyndsay Canning; Monuko du Plessis; Petrus Maree

2000-01-01

457

Optimal fabrication process for mems pressure sensor by 8inch CMOS  

Microsoft Academic Search

We have developed the MEMS piezo pressure sensor by utilizing CMOS process modules and tool-sets to challenge faster time to market and faster time to volume with high yield. The MEMS device has the commonality of process, tools, material, and design system and qualification method with 0.35um CMOS device. The CMOS integration approach also showed the high quality as small

Tadashi Kai; Katsuyuki Inoue; Y. Adachi

2010-01-01

458

Self-calibrated humidity sensor in CMOS without post-processing.  

PubMed

A 1.1 ?W power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry. PMID:22368466

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2012-01-01

459

A new readout circuit for an ultrahigh sensitivity CMOS image sensor  

Microsoft Academic Search

We have developed a new readout circuit for highly sensitive CMOS image sensors. The circuit makes it possible to obtain a high signal-to-noise ratio by effectively transferring signal charges accumulated in the photodiode to a small capacitance. We fabricated and tested a CMOS image sensor with the readout circuit, and confirmed that it has higher sensitivity than conventional passive-pixel CMOS

Toshihisa Watabe; Masahide Goto; Hiroshi Ohtake; Hirotaka Maruyama; Kenkichi Tanioka

2002-01-01

460

INVITED PAPER: Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs  

Microsoft Academic Search

We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite

Harry Contopanagos

2005-01-01

461

A high-frequency fully differential BiCMOS operational amplifier  

Microsoft Academic Search

A high-frequency fully differential BiCMOS operational amplifier design for use in switched-capacitor circuits is presented. The operational amplifier is integrated in a 3.0-GHz, 2-?m BiCMOS process with an active die area of 1.0 mm×1.2 mm. This BiCMOS op amp offers an infinite input resistance, a DC gain of 100 dB, a unity-gain frequency of 90 MHz with 45° phase margin,

Andrew N. Karanicolas; Kenneth K. O; John Y. A. Wang; Hae-Seung Lee; R. L. Reif

1991-01-01

462

Integration of Solar Cells on Top of CMOS Chips Part I: aSi Solar Cells  

Microsoft Academic Search

We present the monolithic integration of deep- submicrometer complementary metal-oxide-semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values above 7%. The yield of photovoltaic cells on planarized CMOS chips is 92%. This integration allows integrated energy harvesting using established process

Jiwu Lu; Alexey Y. Kovalgin; Karine H. M. van der Werf; Ruud E. I. Schropp; Jurriaan Schmitz

2011-01-01

463

Integration of Single-Walled Carbon Nanotubes on to CMOS Circuitry with Parylene-C Encapsulation  

Microsoft Academic Search

This paper presents heterogeneous integration of single-walled carbon nanotubes (SWNTs) with CMOS integrated circuits using die-level post processing. The chip was fabricated using the AMI 0.5 mum CMOS Technology. An electroless zincation process was performed over the Aluminum assembly electrodes (Metal 3 of CMOS technology) to clean and to coat the electrodes with a thin Zinc layer. Low temperature dielectrophoretic

Chia-Ling Chen; Vinay Agarwal; Sameer Sonkusale; Mehmet R. Dokmeci

2008-01-01

464

Projection-reflection ultrasound images using PE-CMOS sensor: a preliminary bone fracture study  

Microsoft Academic Search

In this study, we investigated the characteristics of the ultrasound reflective image obtained by a CMOS sensor array coated with piezoelectric material (PE-CMOS). The laboratory projection-reflection ultrasound prototype consists of five major components: an unfocused ultrasound transducer, an acoustic beam splitter, an acoustic compound lens, a PE-CMOS ultrasound sensing array (Model I400, Imperium Inc. Silver Spring, MD), and a readout

Shih-Chung B. Lo; Chu-Chuan Liu; Matthew T. Freedman; Seong-Ki Mun; John Kula; Marvin E. Lasser; Bob Lasser; Yue Joseph Wang

2008-01-01

465

A CMOS image sensor with dark-current cancellation and dynamic sensitivity operations  

Microsoft Academic Search

An ultralow dark-signal and high-sensitivity pixel has been developed for an embedded active-pixel CMOS image sensor by using a standard 0.35-?m CMOS logic process. To achieve in-pixel dark-current cancellation, we developed a combined photogate\\/photodiode photon-sensing device with a novel operation scheme. The experimental results demonstrate that the severe dark signal degradation of a CMOS active pixel sensor is reduced more

Hsiu-Yu Cheng; Ya-Chin King

2003-01-01

466

Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS  

Microsoft Academic Search

In this letter, we investigate a novel vertical silicon nanowire-based (NW) complementary metal-oxide- semiconductor (CMOS) technology for logic applications. The performance and the behavior of two- and single-wire CMOS inverters are simulated and analyzed. We show that vertical NW based CMOS offers a reduction of up to 50% in layout area, along with delay reductions of 50% (two wire) and

Satish Maheshwaram; S. K. Manhas; Gaurav Kaushal; Bulusu Anand; Navab Singh

2011-01-01

467

Low-power logic styles: CMOS versus pass-transistor logic  

Microsoft Academic Search

Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with

Reto Zimmermann; Wolfgang Fichtner

1997-01-01

468

Development and characterization of CMOS-based monolithic X-ray imager sensor  

Microsoft Academic Search

We proposed a new design of CMOS-based X-ray image sensor with monolithically grown pixelated CsI(Tl) on photosensor area for securing the maximally achievable spatial resolution for a given sensitivity determined by the CsI(Tl) thickness at a certain X-ray energy. The test version of a CMOS image sensor (CIS) was designed and fabricated using AMIS 0.5 mum standard CMOS process. The

Gyuseong Cho; Bo Kyung Cha; Jun Hyung Bae; Byoung-Jik Kim; Sung Chae Jeon; Young-Hee Kim; Gyu-Ho Lim

2007-01-01

469

Monolithic 28.3 THz thermal image sensor incorporating 0.18-um CMOS foundry  

Microsoft Academic Search

This paper presents a fully monolithic approach to the design and fabrication of THz CMOS image sensor operating at 28.3 THz using the mass-producible 0.18-um 1P6M CMOS foundry. The CMOS sensor consists of antenna-coupled transducer, linearly transforming the intercepted THz (terahertz) electromagnetic energy into voltage representation. The THz image sensor adopts PTAT (Proportional To Absolute Temperature) sensing circuit configuration. The

S. Yang; L. Su; I. Huang; C. Ting; C. C. Tzuang

2010-01-01

470

Monolithic 28.3 THz thermal image sensor incorporating 0.18-µm CMOS foundry  

Microsoft Academic Search

This paper presents a fully monolithic approach to the design and fabrication of THz CMOS image sensor operating at 28.3 THz using the mass-producible 0.18-?m 1P6M CMOS foundry. The CMOS sensor consists of antenna-coupled transducer, linearly transforming the intercepted THz (terahertz) electromagnetic energy into voltage representation in the region of interest. The THz image sensor adopts PTAT (Proportional To Absolute

Sin-Han Yang; Li Su; I-Chun Huang; Chueh Ting; C.-K. C. Tzuang

2010-01-01

471

Smart CMOS image sensor for lightning detection and imaging.  

PubMed

We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 ?m pixel pitch has been fabricated using a 0.35 ?m 2P 5M technology and tested to validate the selected detection approach. PMID:23458812

Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

2013-03-01

472

Radiation Hard 0.25 Micron CMOS Library at IHP  

NASA Astrophysics Data System (ADS)

To support space applications we have produced a test chip with our in house 0.25 micron BiCMOS- Technology. Then the chips were radiated and measured. During measurements no threshold voltage shift and no single event latchup (SEL) were obtained up to a level of 200 krad. As conclusion of the measurement we developed new radiation hard design rules and according to these rules we created a new radiation hard CMOS library. With this new library we produced a Leon3 chip with triple module redundancy. Single event upsets did occur. Therefore we upgrade the library to make the flip flops more resistant against single event upset (SEU) by adding two p-MOS transistors.

Jagdhold, U.

2008-08-01

473

Development of CMOS-compatible membrane projection lithography  

NASA Astrophysics Data System (ADS)

Recently we have demonstrated membrane projection lithography (MPL) as a fabrication approach capable of creating 3D structures with sub-micron metallic inclusions for use in metamaterial and plasmonic applications using polymer material systems. While polymers provide several advantages in processing, they are soft and subject to stress-induced buckling. Furthermore, in next generation active photonic structures, integration of photonic components with CMOS electronics is desirable. While the MPL process flow is conceptually simple, it requires matrix, membrane and backfill materials with orthogonal processing deposition/removal chemistries. By transitioning the MPL process flow into an entirely inorganic material set based around silicon and standard CMOS-compatible materials, several elements of silicon microelectronics can be integrated into photonic devices at the unit-cell scale. This paper will present detailed fabrication and characterization data of these materials, emphasizing the processing trade space as well as optical characterization of the resulting structures.

Burckel, D. Bruce; Samora, Sally; Wiwi, Mike; Wendt, Joel R.

2013-09-01

474

Digital autoradiography using room temperature CCD and CMOS imaging technology  

NASA Astrophysics Data System (ADS)

CCD (charged coupled device) and CMOS imaging technologies can be applied to thin tissue autoradiography as potential imaging alternatives to using conventional film. In this work, we compare two particular devices: a CCD operating in slow scan mode and a CMOS-based active pixel sensor, operating at near video rates. Both imaging sensors have been operated at room temperature using direct irradiation with images produced from calibrated microscales and radiolabelled tissue samples. We also compare these digital image sensor technologies with the use of conventional film. We show comparative results obtained with 14C calibrated microscales and 35S radiolabelled tissue sections. We also present the first results of 3H images produced under direct irradiation of a CCD sensor operating at room temperature. Compared to film, silicon-based imaging technologies exhibit enhanced sensitivity, dynamic range and linearity.

Cabello, Jorge; Bailey, Alexis; Kitchen, Ian; Prydderch, Mark; Clark, Andy; Turchetta, Renato; Wells, Kevin

2007-08-01

475

Pre-layout Delay Calculation Specification for CMOS ASIC Libraries  

Microsoft Academic Search

This paper describes the delay calculation method and the accuracy analysis of its interpolation for CMOS ASIC libraries which contain cell-based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification, and logic synthesis. The delay calculation method addressed in this paper is specified as IEC CDV 61523-2 standard which consists of the estimation

Hisakazu Edamatsu; Katsumi Homma; Masaru Kakimoto; Yutaka Koike; Kinya Tabuchi

1998-01-01

476

A 167Processor Computational Platform in 65 nm CMOS  

Microsoft Academic Search

A 167-processor computational platform consists of an array of simple programmable processors capable of per-pro- cessor dynamic supply voltage and clock frequency scaling, three algorithm-specific processors, and three 16 KB shared memories; and is implemented in 65 nm CMOS. All processors and shared memories are clocked by local fully independent, dynamically haltable, digitally-programmable oscillators and are intercon- nected by a

Dean N. Truong; Wayne H. Cheng; Tinoosh Mohsenin; Zhiyi Yu; ANTHONY T. JACOBSON; Michael J. Meeuwsen; Anh T. Tran; Zhibin Xiao; Eric W. Work; Jeremy W. Webb; Paul Mejia; Bevan M. Baas

2009-01-01

477

An X-Band CMOS Multifunction-Chip FMCW Radar  

Microsoft Academic Search

A fully integrated, miniaturized, low-power frequency-modulated continuous wave (FMCW) multifunction chip realized by typical 1P6M 0.18 mum deep n-well CMOS technology is presented for the first time. The multifunction chip consists of VCO, buffer amplifier, 3-dB power divider, isolators, driving amplifiers, mixer, low-noise amplifier, attenuator, etc., necessary for carrying out the X-band RF signal processing of the FMCW signals interfaced

C. K. C. Tzuang; Chi-Ho Chang; Hsien-Shun Wu; Sen Wang; Si-Xian Lee; Chih-Chia Chen; Chi-Yang Hsu; Kun-Hung Tsai; Johnsea Chen

2006-01-01

478

Design of Band RF CMOS Transceiver for FMCW Monopulse Radar  

Microsoft Academic Search

In this paper, an X-band CMOS single chip integrating 16 building blocks is developed for frequency modulation continuous wave radar application. The quadrature and monopulse transceiver consists of a voltage-controlled oscillator, amplifiers, Wilkinson power dividers, 90deg hybrid low-noise amplifiers, rat-race hybrid, a single-pole double-throw switch, an active bandpass filter (BPF), and mixers. The transceiver is fabricated in a standard mixed-signal\\/RF

Sen Wang; Kun-Hung Tsai; Kuo-Ken Huang; Si-Xian Li; Hsien-Shun Wu; Ching-Kuang C. Tzuang

2009-01-01

479

Flip-chip packaging solution for CMOS image sensor device  

Microsoft Academic Search

Chip scaled opto-electronic packaging is introduced as a cost and size effective packaging solution for mobile phone with built in camera. The chip scaled assembly includes gold bumped CMOS image sensor device and its flip-chip bonding on substrate using the anisotropic conductive material. Two types of flip-chip module were designed to have flip-chip on flex and flip-chip on glass. It

Jong-heon Kim; In-soo Kang; Chi-jung Song; Young-jik Hur; Hak-nam Kim; Esdy Baek; Tae-jun Seo

2004-01-01

480

Class-G headphone driver in 65nm CMOS technology  

Microsoft Academic Search

A 65 nm CMOS Class-G headphone driver operates from ±1.4 V, ±0.35 V supplies. At low power level it uses the low voltage supply to reduce the dissipation to 1.63 mW @ Pout = 0.5 mW into 32 ¿. At higher power level, the smooth transition between the voltage supply rails allows a THD+N better than -80 dB for Pout

Alex Lollio; Giacomino Bollati; Rinaldo Castello

2010-01-01

481

Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors  

Microsoft Academic Search

We demonstrate, for the first time, the fabrication of vertically stacked SiGe nanowire (NW) arrays with a fully CMOS compatible technique. Our method uses the phenomenon of Ge condensation onto Si and the faster oxidation rate of SiGe than Si to realize the vertical stacking of NWs. Gate-all-around nand p-FETs, fabricated using these stacked NW arrays as the channel (Lgges0.35

W. W. Fang; N. Singh; L. K. Bera; H. S. Nguyen; S. C. Rustagi; G. Q. Lo; N. Balasubramanian; D.-L. Kwong

2007-01-01

482

High performance fully-depleted tri-gate CMOS transistors  

Microsoft Academic Search

Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate

B. S. Doyle; S. Datta; M. Doczy; S. Hareland; B. Jin; J. Kavalieros; T. Linton; A. Murthy; R. Rios; R. Chau

2003-01-01

483

Development of CMOS-Compatible Integrated Silicon Photonics Devices  

Microsoft Academic Search

This paper surveys technical challenges involved in designing and manufacturing integrated optoelectronic devices in a high-volume complementary metal–oxide–semiconductor (CMOS) microelectronic fabrication facility. The paper begins by introducing the motivations for building these devices in silicon. We discuss the advantages and challenges of both hybrid and monolithic strategies for optoelectronic integration. We then discuss the issues involved in building the devices

Nahum Izhaky; Michael T. Morse; Sean Koehl; Oded Cohen; Doron Rubin; Assia Barkai; Gadi Sarid; Rami Cohen; Mario J. Paniccia

2006-01-01

484

CMOS inverters based positive type second generation current conveyor  

Microsoft Academic Search

A new versatile class AB low-voltage second generation current conveyor based on CMOS inverters operating in transconductance\\u000a mode is presented in this letter. Against traditional design based on CCII+, the circuit is able to operate at low supply\\u000a voltages and offers numerous advantages like class AB operation, large voltage and current swing, synthesis from digital inverters.\\u000a Simulation results from a

Hervé Barthélemy; Matthieu Fillaud; Sylvain Bourdel; Jean Gaubert

2007-01-01

485

5GHz CMOS LC VCOs with wide tuning ranges  

Microsoft Academic Search

A 4.8-GHz LC voltage-controlled oscillator (VCO) optimized for maximum tuning range was designed and fabricated using 0.25-?m 1P5M CMOS process. The optimized design used an inverse proportionality between the two parasitic capacitances of the inductor and the MOS transistors for minimizing the parasitic capacitance at the oscillation node. The fabricated LC VCO has a wide tuning range of 20.3% from

Byunghun Min; Hanggeun Jeong

2005-01-01

486

A reconfigurable op-amp\\/DDA CMOS amplifier architecture  

Microsoft Academic Search

A simple architecture for a configurable op-amp or differential difference amplifier (DDA) is presented. The circuitry can be configured as an input\\/output rail to rail high-speed op-amp, or as a DDA. The circuit was simulated using SPICE and fabricated in a 2-?m CMOS process through MOSIS. Configured as an op-amp, it achieves a positive and negative slew rate of 16

Seyed R. Zarabadi; Frode Larsen; Mohammed Ismail

1992-01-01

487

Total dose radiation response of CMOS compatible SOI MESFETs  

Microsoft Academic Search

Metal semiconductor field effect transistors (MESFETs) have been fabricated using a silicon-on-insulator (SOI) CMOS process. The MESFETs make use of a TiSi2 Schottky gate and display good depletion mode characteristics with a threshold voltage of -0.5 V. The drain current can also be controlled by a voltage applied to the substrate, which then behaves as a MOS back gate. The

John Spann; Vadim Kushner; Trevor J. Thornton; Jinman Yang; A. Balijepalli; H. J. Barnaby; Xiao Jie Chen; D. Alexander; W. T. Kemp; S. J. Sampson; M. E. Wood

2005-01-01

488

On-chip p-MOSFET dosimetry [CMOS ICs  

Microsoft Academic Search

On-chip p-FETs were developed to monitor the radiation dose of n-well CMOS ICs by monitoring threshold voltage shifts due to radiation-induced oxide and interface charge. The design employs closed-geometry FETs and a zero-biased n-well to eliminate leakage currents. The FETs are operated using a constant current chosen to greatly reduce the FET's temperature sensitivity. The dose sensitivity of these p-FETs

M. G. Buehler; B. R. Blaes; G. A. Soli; G. R. Tardio

1993-01-01

489

A high-speed dynamically reconfigurable 32-bit CMOS adder  

Microsoft Academic Search

A high-speed, compact three-way dynamically reconfigurable 32-bit CMOS adder is reported. The design of this adder uses an enhanced organization for 32-bit carry lookahead and uses an area-speed efficient dynamic circuit technique, called multiple-output domino logic. The reconfigurability is achieved without significant overhead on the basis of these combined techniques. The 248×1454-?m2 adder, fabricated in a standard 0.9-?m two-level metal

Inseok S. Hwang; P. S. Magarschack

1988-01-01

490

Diagnosing CMOS bridging faults with stuck-at fault dictionaries  

Microsoft Academic Search

It is shown that the traditional approach to diagnosing stuck-at faults with fault dictionaries generated for stuck-at faults is not appropriate for diagnosing CMOS bridging faults. A novel technique for using stuck-at-fault dictionaries to diagnose bridging faults is described. Teradyne's LASAR was used to simulate bridging and stuck-at faults in a number of combinational circuits, including parity trees, multiplexers, and

Steven D. Millman; Edward J. McCluskey; John M. Acken

1990-01-01

491

Bridging Defects Resistance Measurements in a CMOS Process  

Microsoft Academic Search

Measurements on process-related defect nionitwing ,wcijers are presented in order to euuluute the i,csisluiict. ,ualu,e of b ridyzng deJects zn CMOS VLSI circu~ts. 'I'he inethodoloyy u sed is dlustrated and statzstics OIL the 1.esistance values are p resented. As a result, the vast niajoi-zty of the measured brzdges have a 1o.w 7.eszsta.nce. Only a small percentage of the brzdges has

Rosa Rodríguez-montañés; Joan Figueras; Eric Bruls

1992-01-01

492

Limitations on the maximum operating voltage of CMOS integrated circuits  

Microsoft Academic Search

A one-dimensional model has been developed to study the breakdown voltage behavior of an n-channel IGFET in a conventional CMOS integrated circuit. Two parasitic npn bipolar transistors intrinsic to the circuit which shunt the IGFET are found to limit the breakdown voltage below the intrinsic value of the drain\\/p-tub junction. Turn-on of the parasitics occurs as a result of hole

J. M. Dishman

1975-01-01

493

Comparison of Global Shutter Pixels for CMOS Image Sensors  

Microsoft Academic Search

In this paper we are presenting preliminary results from 4T technology based CMOS image sensors with global shutter, i.e. all pixels in the active array integrate light simultaneously. The global shutter operation mode is particularly important for high-speed video applications, where the more commonly implemented rolling line shutter creates motion blur. Our chips were fabricated using a 0.18 micron 4T,

Stefan Lauxtermann; Adam Lee; John Stevens; Atul Joshi

494

CMOS planar 2D micro-fluxgate sensor  

Microsoft Academic Search

An electronic compass made of a new planar 2D micro-fluxgate sensor is presented. The magnetometer is integrated in a standard CMOS process, and uses a post-processed cross-shaped ferromagnetic amorphous core. This core is diagonally placed above a single square excitation coil common to both measurement axes. The silicon chip includes the driving and readout electronics, the excitation and pick-up coils

L. Chiesi; P. Kejik; B. Janossy; R. S. Popovic

2000-01-01

495

Linear dynamic range enhancement in a CMOS imager  

NASA Technical Reports Server (NTRS)

A CMOS imager with increased linear dynamic range but without degradation in noise, responsivity, linearity, fixed-pattern noise, or photometric calibration comprises a linear calibrated dual gain pixel in which the gain is reduced after a pre-defined threshold level by switching in an additional capacitance. The pixel may include a novel on-pixel latch circuit that is used to switch in the additional capacitance.

Pain, Bedabrata (Inventor)

2008-01-01

496

CMOS resistive fuses for image smoothing and segmentation  

Microsoft Academic Search

A two-terminal nonlinear element called a resistive fuse is described. Its application in image smoothing and segmentation is explained. Two types of CMOS resistive fuses were designed, fabricated, and tested. The first implementation employs four depletion-mode NMOS and PMOS transistors, occupying a minimum area of 30 ?m×38 ?m. The second implementation uses seven or 11 standard enhancement-mode transistors on an

Paul C. Yu; Steven J. Decker; Hae-Seung Lee; Charles G. Sodini

1992-01-01

497

A high-swing CMOS telescopic operational amplifier  

Microsoft Academic Search

A high-swing, high-performance CMOS telescopic operational amplifier is described. The high swing of the op-amp is achieved by employing the tail and current source transistors in the deep linear region. The resulting degradation in differential gain, common-mode rejection ratio (CMRR), and other amplifier characteristics are compensated by applying regulated-cascode differential gain enhancement and a replica-tail feedback technique. A prototype of

Kush Gulati; Hae-Seung Lee

1998-01-01

498

CMOS Alcohol Sensor Employing ZnO Nanowire Sensing Films  

NASA Astrophysics Data System (ADS)

This paper reports on the utilization of zinc oxide nanowires (ZnO NWs) on a silicon on insulator (SOI) CMOS micro-hotplate for use as an alcohol sensor. The device was designed in Cadence and fabricated in a 1.0 ?m SOI CMOS process at XFAB (Germany). The basic resistive gas sensor comprises of a metal micro-heater (made of aluminum) embedded in an ultra-thin membrane. Gold plated aluminum electrodes, formed of the top metal, are used for contacting with the sensing material. This design allows high operating temperatures with low power consumption. The membrane was formed by using deep reactive ion etching. ZnO NWs were grown on SOI CMOS substrates by a simple and low-cost hydrothermal method. A few nanometer of ZnO seed layer was first sputtered on the chips, using a metal mask, and then the chips were dipped in a zinc nitrate hexahydrate and hexamethylenetramine solution at 90° C to grow ZnO NWs. The chemical sensitivity of the on-chip NWs were studied in the presence of ethanol (C2H5OH) vapour (with 10% relative humidity) at two different temperatures: 200 and 250° C (the corresponding power consumptions are only 18 and 22 mW). The concentrations of ethanol vapour were varied from 175-1484 ppm (pers per million) and the maximum response was observed 40% (change in resistance in %) at 786 ppm at 250° C. These preliminary measurements showed that the on-chip deposited ZnO NWs could be a promising material for a CMOS based ethanol sensor.

Santra, S.; Ali, S. Z.; Guha, P. K.; Hiralal, P.; Unalan, H. E.; Dalal, S. H.; Covington, J. A.; Milne, W. I.; Gardner, J. W.; Udrea, F.

2009-05-01

499

CMOS low-noise amplifier design optimization techniques  

Microsoft Academic Search

This paper reviews and analyzes four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-constrained simultaneous noise and input matching (PCSNIM) techniques. Very simple and insightful sets of noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques.

Trung-Kien Nguyen; Chung-Hwan Kim; Gook-Ju Ihm; Moon-Su Yang; Sang-Gug Lee

2004-01-01

500

Accelerated life testing effects on CMOS microcircuit characteristics, phase 1  

NASA Technical Reports Server (NTRS)

An accelerated life test of sufficient duration to generate a minimum of 50% cumulative failures in lots of CMOS devices was conducted to provide a basis for determining the consistency of activation energy at 250 C. An investigation was made to determine whether any thresholds were exceeded during the high temperature testing, which could trigger failure mechanisms unique to that temperature. The usefulness of the 250 C temperature test as a predictor of long term reliability was evaluated.

Maximow, B.

1976-01-01