Sample records for 130-nm commercial cmos

  1. Low-noise design issues for analog front-end electronics in 130 nm and 90 nm CMOS technologies

    E-print Network

    Manghisoni, M; Re, V; Speziali, V; Traversi, G

    2007-01-01

    Deep sub-micron CMOS technologies provide wellestablished solutions to the implementation of low-noise front-end electronics in various detector applications. The IC designers’ effort is presently shifting to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In this work the results of noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. The behavior of the 1/f and white noise terms is studied as a function of the device polarity and of the gate length and width. The study is focused on low current density applications where devices are biased in weak or moderate inversion. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends in LHC upgrades.

  2. A 280GHz Schottky Diode Detector in 130-nm Digital CMOS

    Microsoft Academic Search

    Ruonan Han; Yaming Zhang; Dominique Coquillat; Hadley Videlier; Wojciech Knap; Elliott Brown; Kenneth K. O

    2011-01-01

    A2 2 array of 280-GHz Schottky-barrier diode detectors with an on-chip patch antenna (255 250 m )i s fab- ricated in a 130-nm logic CMOS process. The series resistance of diode is minimized using poly-gate separation (PGS), and exhibits a cut-off frequency of 2 THz. Each detector unit can detect an incident carrier with 100-Hz 2-MHz amplitude modulation. At 1-MHz

  3. A CMOS 130nm Evaluation digitzer chip for silicon strips readout

    E-print Network

    Da Silva, W; Dhellot, M; Fougeron, D; Genat, J F; Hermel, R; Huppert, J f; Kapusta, F; Lebbolo, H; Pham, T H; Rossel, F; Savoy-navarro, A; Sefri, R; Vilalte

    2007-01-01

    A CMOS 130nm evaluation chip intended to read Silicon strip detectors at the ILC has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of charge integration, pulse shaping, a 16-deep analogue sampler triggered on input analogue sums, and parallel analogue to digital conversion. Tests results of the full chain are reported, demonstrating the behaviour and performance of the full sampling process and analogue to digital conversion. Each channel dissipates less than one milli-Watt static power.

  4. Temperature-Dependence of Off-State Drain Leakage in X-Ray Irradiated 130 nm CMOS Devices

    Microsoft Academic Search

    Bongim Jun; Ryan M. Diestelhorst; Marco Bellini; Gustavo Espinel; Aravind Appaswamy; A. P. Gnana Prakash; John D. Cressler; Dakai Chen; Ronald D. Schrimpf; Daniel M. Fleetwood; Marek Turowski; Ashok Raman

    2006-01-01

    The off-state drain current leakage characteristics of 130 nm CMOS technology are investigated using x-ray irradiation and operating temperature as variables. Radiation-induced interface traps in the gate oxide to gate-drain overlap region strongly enhance the off-state leakage as a function of gate bias. Due to the thin gate oxide in these 130 nm devices, we find that drain-edge direct tunneling

  5. Development of front-end electronics for LumiCal detector in CMOS 130 nm technology

    NASA Astrophysics Data System (ADS)

    Firlej, M.; Fiutowski, T.; Idzik, M.; Moro?, J.; ?wientek, K.; Terlecki, P.

    2015-01-01

    The design and the preliminary measurements results of a multichannel, variable gain front-end electronics for luminosity detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier with pole-zero cancellation circuit and a CR-RC shaper with 50 ns peaking time. The measurements results confirm full functionality of the prototype and compliance with the requirements imposed by the detector specification. The power consumption of the front-end is in the range 0.6–1.5 mW per channel and the noise ENC around 900 e - at 10 pF input capacitance.

  6. Development of scalable frequency and power Phase-Locked Loop in 130 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Firlej, M.; Fiutowski, T.; Idzik, M.; Moro?, J.; ?wientek, K.

    2014-02-01

    The design and measurements results of a prototype very low power Phase-Locked Loop (PLL) ASIC for applications in readout systems of particle physics detectors are presented. The PLL was fabricated in 130 nm CMOS technology. It was designed and simulated for frequency range 10 MHz-3.5 GHz. Four division factors i.e. 6, 8, 10 and 16 were implemented in the PLL feedback loop. The main PLL block-voltage controlled oscillator (VCO) should work in 16 frequency ranges/modes, switched either manually or automatically. Preliminary measurements done in frequency range 20 MHz-1.6 GHz showed that the ASIC is functional and generates proper clock signal. The automatic VCO mode switching, one of the main design goals, was positively verified. Power consumption of around 0.6 mW was measured at 1 GHz for a division factor equal to 10.

  7. All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

    Microsoft Academic Search

    Robert Bogdan Staszewski; Khurram Muhammad; Dirk Leipold; Chih-Ming Hung; Yo-Chuol Ho; John L. Wallberg; Chan Fernando; Ken Maggio; Roman Staszewski; Tom Jung; Jinseok Koh; Soji John; Irene Yuanying Deng; Vivek Sarda; Oscar Moreira-Tamayo; Valerian Mayega; Ofer Friedman; Oren Eytan Eliezer; Poras T. Balsara; E. de-Obaldia

    2004-01-01

    We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The trans- ceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase\\/frequency detector and charge-pump

  8. Heavy ion-induced SEEs on 130 nm CMOS technology for LHC application—status and challenges

    NASA Astrophysics Data System (ADS)

    Gabrielli, A.

    2011-12-01

    This work summarizes the status of the art of electronic designs, using CMOS technologies, to stand LHC and S-LHC radiation-hard environments. Radiation effects can be divided into Single Event Effects and Total Ionizing Dose effects, which are consequences of different interaction effects within the silicon and the electronics. These types of effects are commonly investigated and faced separately. The commercial 130 nm CMOS technology, today primarily proposed for SLHC electronic upgrades, only implements redundancies against the Single Event Effects`. On the contrary, the 250 nm technology node used in the past years for LHC experiments, was also hardened against the Total Ionizing Dose. Hence, the choice of the technology to be used for high-energy experiments is very crucial as it implies huge efforts in the designs of the components. In addition, an unavoidable technology scaling keeps moving toward ever-smaller sizes and this affects the availability of the silicon process for medium and long-term experiments.

  9. Radiation hardness evaluation of a 130 nm SiGe BiCMOS technology for high energy physics applications

    NASA Astrophysics Data System (ADS)

    Dķez, S.; Clark, T.; Grillo, A. A.; Kononenko, W.; Martinez-McKinney, F.; Newcomer, F. M.; Norgren, M.; Rescia, S.; Spencer, E.; Spieler, H.; Ullįn, M.; Wilder, M.

    2013-10-01

    Final results for a comprehensive radiation hardness evaluation of a high performance, low cost, 130 nm SiGe BiCMOS technology are presented. After a survey of several available SiGe technologies, one was chosen in terms of performance, power consumption, radiation hardness, and cost and it is presented as a suitable technology for the future upgrades of the ATLAS detector of the High Luminosity LHC. Bipolar devices of different sizes and geometries have been evaluated, along with a prototype Front-End readout ASIC designed for binary readout of silicon microstrip detectors. Gamma, neutron and proton irradiations have been performed up to the expected doses and fluences of the experiment.

  10. 10 GHz low phase noise fully integrated VCOs in 130 nm high resistivity CMOS\\/SOI for 40 Gbits\\/s datacom

    Microsoft Academic Search

    D. Axelrad; E. de Foucauld; P. Vincent; M. Belleville; F. Gaffiot

    2004-01-01

    This paper discusses the 10 GHz low phase noise fully integrated VCOs in 130 nm high resistivity CMOS\\/SOI for 40 Gbits\\/s datacom. This work is a first step towards the evaluation of SOI technology for 40 Gbit\\/s applications. In particular, CMOS\\/SOI technologies allow the design of high speed, high performance VCOs and key blocks for high data rate designs. Useful

  11. Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

    E-print Network

    Kruth, A; Arutinov, D; Barbero, M; Gronewald, M; Hemperek, T; Karagounis, M; Krueger, H; Wermes, N; Fougeron, D; Menouni, M; Beccherle, R; Dube, S; Ellege, D; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gromov, V; Kluit, R; Schipper, J

    2009-01-01

    FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for t...

  12. A saw-less direct conversion long term evolution receiver with 25% duty-cycle LO in 130 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Siyuan, He; Changhong, Zhang; Liang, Tao; Weifeng, Zhang; Longyue, Zeng; Wei, Lü; Haijun, Wu

    2013-03-01

    A CMOS long-term evolution (LTE) direct convert receiver that eliminates the interstage SAW filter is presented. The receiver consists of a low noise variable gain transconductance amplifier (TCA), a quadrature passive current commutating mixer with a 25% duty-cycle LO, a trans-impedance amplifier (TIA), a 7th-order Chebyshev filter and programmable gain amplifiers (PGAs). A wide dynamic gain range is allocated in the RF and analog parts. A current commutating passive mixer with a 25% duty-cycle LO improves gain, noise, and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference. Fabricated in a 0.13 ?m CMOS process, the receiver chain achieves a 107 dB maximum voltage gain, 2.7 dB DSB NF (from PAD port), -11 dBm IIP3, and > +65 dBm IIP2 after calibration, 96 dB dynamic control range with 1 dB steps, less than 2% error vector magnitude (EVM) from 2.3 to 2.7 GHz. The total receiver (total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.

  13. The eCDR, a Radiation-Hard 40/80/160/320 Mbit/s CDR with internal VCO frequency calibration and 195 ps programmable phase resolution in 130 nm CMOS

    NASA Astrophysics Data System (ADS)

    Tavernier, F.; Francisco, R.; Bonacini, S.; Poltorak, K.; Moreira, P.

    2013-12-01

    A clock and data recovery IP, the eCDR, is presented which is intended to be implemented on the detector front-end ASICs that need to communicate with the GBTX by means of e-links. The programmable CDR accepts data at 40, 80, 160 or 320Mbit/s and generates retimed data as well as 40, 80, 160 and 320MHz clocks that are aligned to the retimed data. Moreover, all the outputs have a programmable phase with a resolution of 195ps. An internal calibration mechanism enables the eCDR to lock on incoming data even without the availability of any form of reference clock. The radiation-hard design, integrated in a 130nm CMOS technology, operates at a supply voltage between 1.2V and 1.5V. The power consumption is between 28.5mW and 34.5mW, depending on the settings. The eCDR can achieve a very low RMS jitter below 10ps.

  14. Design and development of 130nm ICs for a 720 Gb\\/s networking system

    Microsoft Academic Search

    A. Khan; K. Ruparel; C. Joly; V. Ghanta; D. Le; T. Nguyent; S. Yang; I. Ahmed; N. Burnside; M. Cheung; F. Chiu; Y. Fan; D. Ge; J. Gill; P. Huang; V. Jayapal; O. Kim; M. Li; S. Nguyen; P. Trant; H. Truong; A. Tsou; D. Wang; X. Zhong

    2005-01-01

    A system-centric, fully-hierarchical design methodology and design techniques developed to create four ICs, which provide the core functionality of a multi-gigabit switching network system, are presented. The system is capable of switching more than 500 million packets per second. Electrical and physical design methods for one IC are described. ?76M transistors are integrated in a 130nm CMOS 8-metal process. Functional

  15. Measurement of Radiation Damage to 130nm Hybrid Pixel Detector Readout Chips

    E-print Network

    Plackett, R; Ballabriga, R; Campbell, M; Tlustos, L; Wong, W

    2009-01-01

    We present the first measurements of the performance of the Medipix3 hybrid pixel readout chip after exposure to significant x-ray flux. Specifically the changes in performance of the mixed mode pixel architecture, the digital periphery, digital to analogue converters and the e-fuse technology were characterised. A high intensity, calibrated x- ray source was used to incrementally irradiate the separate regions of the detector whilst it was powered. This is the first total ionizing dose study of a large area pixel detector fabricated using the 130nm CMOS technology.

  16. Photonic integration in a commercial scaled bulk-CMOS process

    E-print Network

    Kaertner, Franz X.

    We demonstrate the first photonic chip designed for a commercial bulk CMOS process (65 nm-node) using standard process layers combined with post-processing, enabling dense photonic integration with high-performance ...

  17. Tests of commercial colour CMOS cameras for astronomical applications

    NASA Astrophysics Data System (ADS)

    Pokhvala, S. M.; Reshetnyk, V. M.; Zhilyaev, B. E.

    2013-12-01

    We present some results of testing commercial colour CMOS cameras for astronomical applications. Colour CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in colour CMOS sensors is close to the astronomical Johnson BVR system. The basic camera characteristics: read noise (e^{-}/pix), thermal noise (e^{-}/pix/sec) and electronic gain (e^{-}/ADU) for the commercial digital camera Canon 5D MarkIII are presented. We give the same characteristics for the scientific high performance cooled CCD camera system ALTA E47. Comparing results for tests of Canon 5D MarkIII and CCD ALTA E47 show that present-day commercial colour CMOS cameras can seriously compete with the scientific CCD cameras in deep astronomical imaging.

  18. A 130 nm ASIC prototype for the NA62 Gigatracker readout

    NASA Astrophysics Data System (ADS)

    Dellacasa, G.; Garbolino, S.; Marchetto, F.; Martoiu, S.; Mazza, G.; Rivetti, A.; Wheadon, R.

    2011-09-01

    One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27 mm×60 mm. While the maximum pixel size is fairly large, 300 ?m×300 ?m the system has to sustain a very high particle rate, 1.5 MHz/mm 2, which corresponds to 800 MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150 ps (rms). Therefore the front-end ASIC should provide for each pixel a 200 ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130 nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Converter based TDC, both of them implemented on each pixel cell. The End of Column circuit containing only digital logic is responsible for the data readout from the pixel cell. The whole chip works with a system clock of 160 MHz and the digital logic is SEU protected by the use of Hamming codes. The detailed architecture of the ASIC prototype and test results are presented.

  19. Shallow-trench-isolation bounded single-photon avalanche diodes in commercial deep submicron CMOS technologies

    E-print Network

    Finkelstein, Hod

    2007-01-01

    CMOS technology, based on a new shallow-trench isolationtechnologies, especially DRAM processes, offer deep-trench isolation.Isolation Bounded Single-Photon Avalanche Diodes in Commercial Deep Submicron CMOS Technologies

  20. Micromachined thermocouple microwave detector by commercial CMOS fabrication

    Microsoft Academic Search

    V. Milanovic; M. Gaitan; M. E. Zaghloul

    1998-01-01

    This paper reports on the design and testing of a thermocouple microwave detector fabricated through a commercial CMOS foundry with an additional maskless etching procedure. The detector measures true r.m.s. power of signals in the frequency range from 50 MHz to 20 GHz, and input power range from -30 to +10 dBm, the device has linearity better than ±0.4% for

  1. Dual Damascene Interconnect Technology for 130-nm-node Complementary Metal-Oxide-Semiconductor Devices Using Ladder-Oxide Film

    NASA Astrophysics Data System (ADS)

    Yokoyama, Takashi; Shiba, Kazutoshi; Nishizawa, Atsushi; Nagahara, Seiji; Yamato, Hidekazu; Usami, Tatsuya; Watanabe, Susumu; Nakabeppu, Kenichi; Kunimune, Yorinobu; Sekine, Makoto; Oda, Noriaki; Horiuchi, Tadahiko

    2003-09-01

    A 0.34-?m-pitch Cu dual damascene interconnect technology using a low-k ladder-oxide film (k=2.9) is developed for 130-nm-node complementary metal oxide semiconductor (CMOS) devices. Photoresist poisoning was improved by adopting the ladder-oxide film with annealing before the photolithography step. The fence structures around via openings caused poor Cu gap filling. The problem was solved by controlling the filling height of a bottom anti-reflective coating and by eliminating the photoresist poisoning. Furthermore, no degradation of the ladder-oxide film upon photoresist stripping was observed. It was demonstrated that these technologies could be applied to a product-level application-specific integrated circuit chip with a seven-level Cu interconnect.

  2. A SrRuO3\\/IrO2 top electrode FeRAM with Cu BEOL process for embedded memory of 130nm generation and beyond

    Microsoft Academic Search

    Y. Kumura; T. Ozaki; H. Kanaya; O. Hidaka; Y. Shimojo; S. Shuto; Y. Yamada; K. Tomioka; K. Yamakawa; S. Yamazaki; D. Takashima; T. Miyakawa; S. Shiratake; S. Ohtsuki; I. Kunishima; A. Nitayama

    2005-01-01

    An extremely damage-robust SrRuO3\\/IrO2 top electrode FeRAM with Cu BEOL process is demonstrated for the first time as a promising device for 130nm CMOS embedded memory. The ferroelectric capacitor with SrRuO3\\/IrO2 top electrode has no degradation during Cu metallization to suppress the oxygen and lead vacancies at the top electrode interface. Switching charge (Qsw) of 40uC\\/cm2 is achieved for 0.45×0.45?m2

  3. A Commercial 65 nm CMOS Technology for Space Applications: Heavy Ion, Proton and Gamma Test Results and Modeling

    Microsoft Academic Search

    Philippe Roche; Gilles Gasiot; Slawosz Uznanski; Jean-Marc Daveau; Josep Torras-Flaquer; Sylvain Clerc; Reno Harboe-Sorensen

    2010-01-01

    This paper presents new experimental and modeling evidences that advanced commercial CMOS technologies get intrinsically harder against space radiations with technology downscaling. A 65 nm commercial bulk CMOS process can deliver improved radiation-tolerance without sacrificing electrical performance.

  4. An Accelerator-Based Wireless Sensor Network Processor in 130nm CMOS

    E-print Network

    Hempstead, Mark

    Frequency ( > 1kHz) Breathing sounds 100 - 5k Industrial vibrations 40k Audio (human hearing range) 15 - 44k (in Hz) Very Low Frequency Atmospheric temperature 0.017 - 1 Barometric pressure 0.017 - 1 Low Frequency Heart rate 0.8 - 3.2 Volcanic infrasound 20 - 80 Natural seismic vibration 0.2 - 100 Mid Frequency

  5. Fully digital, phase-domain ?? 3D range image sensor in 130nm CMOS imaging technology 

    E-print Network

    Walker, Richard John

    2012-06-25

    Three-Dimensional (3D) optical range-imaging is a field experiencing rapid growth, expanding into a wide variety of machine vision applications, most recently including consumer gaming. Time of Flight (ToF) cameras, akin ...

  6. Status and perspectives of deep N-well 130 nm CMOS MAPS

    Microsoft Academic Search

    Valerio Re

    2009-01-01

    Deep N-Well (DNW) MAPS were developed in two different flavors to approach the specifications of vertex detectors in dissimilar experimental environments such as the Super B-Factory and the ILC. The first generation of MAPS with on-pixel data sparsification and time stamping capabilities is now available and was tested in a beam for the first time in September 2008. These devices

  7. Power and Performance of Native and Java Benchmarks on 130nm to 32nm Process Technologies

    E-print Network

    Paris-Sud XI, Université de

    Power and Performance of Native and Java Benchmarks on 130nm to 32nm Process Technologies Hadi with chip power reduc- tions. This paper examines how well process technology and mi- croarchitecture delivered on this assumption. This paper evalu- ates power and performance of native and Java workloads

  8. Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process

    Microsoft Academic Search

    Jason S. Orcutt; Anatol Khilo; M. A. Popovic; C. W. Holzwarth; B. Moss; Hanqing Li; M. S. Dahlem; T. D. Bonifield; F. X. Kartner; E. P. Ippen; J. L. Hoyt; R. J. Ram; V. Stojanovic

    2008-01-01

    We demonstrate the first photonic chip designed in a commercial bulk CMOS process (65 nm node) using standard process layers combined with scalable post-processing, enabling dense photonic integration with high-performance microprocessor electronics.

  9. Embedded ferroelectric memory using a 130-nm 5 metal layer Cu \\/ FSG logic process

    Microsoft Academic Search

    S. Summerfelt; S. Aggarwal; K. Boku; F. Celii; L. Hall; L. Matz; S. Martin; H. McAdams; K. Remack; J. Rodriguez; K. Taylor; K. R. Udayakumar; T. Moise; R. Bailey; M. Depner; G. Fox; J. Eliason

    2004-01-01

    An embedded ferroelectric memory (FRAM) has been developed using a 1.5V, 130nm 5 metal layer Cu \\/ FSG logic process. The only modification to the logic process was the addition of a ferroelectric process consisting of two additional masks (FECAP, VIA0) immediately before MET1. The ferroelectric was 70nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The bit distribution

  10. Lifetime studies of 130nm nMOS transistors intended for long-duration, cryogenic high-energy physics experiments.

    SciTech Connect

    Hoff, J.R.; /Fermilab; Arora, R.; Cressler, J.D.; /Georgia Tech; Deptuch, G.W.; /Fermilab; Gui, P.; /Southern Methodist U.; Lourenco, N.E.; /Georgia Tech; Wu, G.; /Southern Methodist U.; Yarema, R.J.; /Fermilab

    2011-12-01

    Future neutrino physics experiments intend to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. To increase performance, integrated readout electronics should work inside the cryostat. Due to the scale and cost associated with evacuating and filling the cryostat, the electronics will be unserviceable for the duration of the experiment. Therefore, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is via hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130nm nMOS transistors operating at cryogenic temperatures are investigated. The results show that the difference in lifetime for room temperature operation and cryogenic operation for this process are not great and the lifetimes at both 300K and at 77K can be projected to more than 20 years at the nominal voltage (1.5V) for this technology.

  11. Thermoelectric Infrared Imaging Microsystems by Commercial CMOS Technology

    Microsoft Academic Search

    O. Paull; N. Schneeberger; U. Munch; M. Walti; A. Schaufelbuhl; H. Baltes; C. Menolfi; Q. Huang; E. Doering; K. Muller; M. Loepfe

    1998-01-01

    We report the design, fabrication, and characterization of an uncooled 10 by 10 pixel infrared detector array with on-chip multiplexing and amplifier system. The microsystem was fabricated using commer­ cial ASIC CMOS technology followed by standard Au electroplating and bulk silicon micromachining. The pixels have a pitch of

  12. Design-to-process integration: optimizing 130-nm X architecture manufacturing

    NASA Astrophysics Data System (ADS)

    Dean, Robert; Malhotra, Vinod K.; King, Nahid; Sanie, Michael; MacDonald, Susan S.; Jordan, James D.; Hirukawa, Shigeru

    2003-07-01

    The X Architecture is a novel on-chip interconnect architecture based on the pervasive use of diagonal wiring. This diagonal wiring reduces total chip wire length by an average 20% and via count by an average of 30%, resulting in simultaneous improvements in chip speed, power, a cost. Thirty percent or greater reduction in via counts is a compelling feature for IC design - but can chips with massive amounts of diagonal wiring be manufactured without some other penalty? This paper presents the result of a project, collaborated by Cadence Design Systems, Numerical Technologies, DuPont Photomasks, and Nikon, aimed at optimizing each step of the lithography supply chain for the Architecture from masks to wafers at 130 nm.

  13. 130 nm, ~ 20 X &1 ) and SiO2 (~ 15 nm) films. The deposition was performed

    E-print Network

    130 nm, ~ 20 X &±1 ) and SiO2 (~ 15 nm) films. The deposition was performed by RF sputtering in 2 investigated by field emission scanning electron microscopy (FESEM) (S-5000, Hitachi), TEM (JEOL-100 kV), XRD diffraction patterns. Received: May 21, 2002 Final version: September 9, 2002 ± [1] C. R. Martin, Science 1994

  14. Radiation Performance of Commercial SiGe HBT BiCMOS High Speed Operational Amplifiers

    Microsoft Academic Search

    Dakai Chen; Jonathan Pellish; Anthony Phan; Hak Kim; Sam Burns; Rafi Albarian; Bruce Holcombe; B. Little; J. Salzman; P. Marshall; K. LaBel

    2010-01-01

    We present results on heavy-ion and proton irradiations for commercial SiGe BiCMOS differential amplifiers: LTC6400-20 from Linear Technology and THS4304 from Texas Instruments. We found that the devices are susceptible to heavy-ion-induced SETs, with relatively low LET thresholds (LETth). The LTC6400 exhibits a LETth <; 7.4 MeV-cm2\\/mg for frequencies ranging from 10 to 1000 MHz. The THS4304 exhibits a LETth

  15. A 64 Mbit embedded FeRAM utilizing a 130 nm, 5LM Cu\\/FSG logic process

    Microsoft Academic Search

    H. McAdams; R. Acklin; T. Blake; J. Fong; D. Liu; S. Madan; T. Moise; S. Natarajan; N. Qian; Y. Qui; J. Roscher; A. Seshadri; S. Summerfelt; X. Du; J. Eliason; W. Kraus; R. Lanham; F. Li; C. Pietrzyk; J. Rickes

    2003-01-01

    A low-voltage (1.3V), 64 Mbit Ferroelectric Random Access Memory using a 1-transistor, 1-capacitor (1T1C) cell is demonstrated. This is the largest FRAM memory demonstrated to date. The memory is constructed using a state-of-the-art 130 nm transistor and a five-level Cu\\/FSG interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate oxide, low-voltage logic

  16. A 60GHz down-converting CMOS single-gate mixer

    Microsoft Academic Search

    Sohrab Emami; Chinh H. Doan; Ali M. Niknejad; Robert W. Brodersen

    2005-01-01

    A quadrature balanced single-gate CMOS mixer, designed to exploit the unlicensed band around 60-GHz, is presented. Also a millimeter-wave (mm-wave) modeling methodology is discussed which is suitable for the design of CMOS mm-wave active mixers. The performance of a fully-integrated mixer fabricated on a standard digital 130-nm CMOS process is given and compared to the simulations. At a radio frequency

  17. Reticle inspection optimization for 90-nm and 130-nm technology nodes using a multibeam UV wavelength inspection tool

    NASA Astrophysics Data System (ADS)

    Lai, Rick; Hsu, Luke; Kung, Chiun Hong; Hung, Johnson; Huang, Wei H.; Yoo, Chue-San; Huang, Yao-Tsu; Hsu, Vincent

    2003-12-01

    As the lithography design rule of IC manufacturing industry migrates into sub-130nm nodes, low k1 factor prevails, the mask error enhancement factor (MEEF) increases. Low k1 processing calls for aggressive sub-resolution assist features and the use of attenuated phase shift masks (AttPSMs). The aggressive OPC features pose challenges to reticle inspection due to high false detection, which is time-consuming for defect classification and impacts the throughput of mask manufacturing. Moreover, the high transmission of the shifter material of 193 nm AttPSM also challenges the UV-based reticle inspection tools with high nuisance counts due to undesirable optical diffraction effects. For a given reticle inspection tool, it is necessary to calibrate the system contrast between the clear and opaque regions (quartz/chrome or quartz/MoSi) of the reticles. In this study, we present the influences of various calibration conditions on sensitivity, false and nuisance detection of reticle inspections. Both the STARlight contamination inspections and the die-to-die pattern inspections were carried out using the KLA-Tencor TeraStar inspection tools with production masks and programmed defect test masks including binary intensity masks (BIMs) and AttPSMs. Successful applications with low false detection and adapted sensitivity will be illustrated in terms of optimizing the calibration setup.

  18. Investigating the degradation mechanisms caused by the TID effects in 130 nm PDSOI I/O NMOS

    NASA Astrophysics Data System (ADS)

    Peng, Chao; Hu, Zhiyuan; Zhang, Zhengxuan; Huang, Huixiang; Ning, Bingxu; Bi, Dawei

    2014-06-01

    This paper evaluates the radiation responses of 3.3 V I/O NMOSFETs from 130 nm partially-depleted silicon-on-insulator (PDSOI) technology. The data obtained from 60Co ionizing radiation experiments indicate that charge trapped in the shallow trench isolation, particularly at the bottom region of the trench oxide, should be the dominant contributor to the off-state drain-to-source leakage current under ON bias. The body doping profile and device dimension are two key factors affecting the performance degradation of the PDSOI transistors after radiation. Significant front gate threshold voltage shift is observed in the T-shape gate device, which is well known as the Radiation Induced Narrow Channel Effect (RINCE). The charge trapped in the buried oxide can induce large threshold voltage shift in the front gate transistor through coupling effect in the low body doping device. The coupling effect is evaluated through three-dimensional simulation. A degradation of the carrier mobility which relates to shallow trench isolation (STI) oxide trapped charge in the narrow channel device is also discussed.

  19. Analysis of the performance of CMOS APS imagers after proton damage

    NASA Astrophysics Data System (ADS)

    Meroli, S.; Passeri, D.; Servoli, L.; Angelucci, A.

    2013-02-01

    In this work we have irradiated a standard commercial CMOS imager with a 24 MeV proton beam at INFN Laboratori Nazionali del Sud, Catania (Italy) up to a nominal fluence of 1014 [protons/cm-2]. The device under test was a standard VGA detector, fabricated with a 130 nm technology without radiation hardening. During the irradiation the detector was operated to monitor the progressive damaging of the sensor and the associated on-pixel electronics. After 18 months from the irradiation damage session, with the detector stored at room temperature, a study on the detection efficiency and charge collection capability has been carried out using fluorescent X-ray photons, emitted from copper target. We found that the detector is still working at 1013 protons/cm2, with a moderate increase of the noise and a slightly decrease of the detection capabilities.

  20. Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu\\/FSG logic process

    Microsoft Academic Search

    T. S. Moise; S. R. Summerfelt; H. McAdams; S. Aggarwal; K. R. Udayakumar; F. G. Celii; J. S. Martin; G. Xing; L. Hall; K. J. Taylor; T. Hurd; J. Rodriguez; K. Remack; M. D. Khan; K. Boku; G. Stacey; M. Yao; M. G. Albrecht; E. Zielinski; M. Thakre; S. Kuchimanchi; A. Thomas; B. McKee; J. Rickes; A. Wang; J. Grace; J. Fong; D. Lee; C. Pietrzyk; R. Lanham; S. R. Gilbert; D. Taylor; J. Amano; R. Bailey; F. Chu; G. Fox; S. Sun; T. Davenport

    2002-01-01

    We demonstrate the bit functionality of a low-voltage, embedded ferroelectric random-access memory constructed using a 130 nm gate and five-level Cu\\/FSG interconnect process. By inserting the two additional masks required for the eFRAM module into this logic flow, we have co-integrated ferroelectric memory and SRAM on a single wafer.

  1. 1Gb\\/s integrated optical detectors and receivers in commercial CMOS technologies

    Microsoft Academic Search

    T. K. Woodward; Ashok V. Krishnamoorthy

    1999-01-01

    The ability to produce a high-performance monolithic CMOS photoreceiver, including the photodetector, could enable greater use of optics in short-distance communication systems. Such a receiver requires the ability to simultaneously produce a photodetector compatible with a high-volume high-yield CMOS process, as well as the entire receiver circuit. The quest for this element has yet to produce a clear winner, and

  2. Visible and ultraviolet \\/800-130 nm\\/ extinction of vapor-condensed silicate, carbon, and silicon carbide smokes and the interstellar extinction curve

    Microsoft Academic Search

    J. R. Stephens

    1980-01-01

    The extinction curves from 800 to 130 nm (1.25-7.7\\/micron) of amorphous silicate smokes nominally of olivine and pyroxene composition, carbon smokes, and crystalline SiC smokes are presented. The SiC smoke occurred in the low-temperature (beta) cubic structural form. The SiC smoke showed an absorption edge which occurred at significantly longer wavelengths than the calculated extinction profile of the hexagonal SiC

  3. Visible and ultraviolet (800--130 nm) extinction of vapor-condensed silicate, carbon, and silicon carbide smokes and the interstellar extinction curve

    Microsoft Academic Search

    J. R. Stephens

    1980-01-01

    The extinction curves from 800 to 130 nm (1.25--7.7 ..mu..mā»Ā¹) of amorphous silicate smokes nominally of olivine and pyroxene composition, carbon smokes, and crystalline SiC smokes are presented. The SiC smoke occurred in the low-temperature (..beta..) cubic structural form. The mean grain radius ranged from 5 to 13 nm. The extinction profiles of the amorphous olivine smokes were similar in

  4. Front end electronics for silicon strip detectors in 90nm CMOS technology: advantages and challenges

    Microsoft Academic Search

    J. Kaplon; M. Noy

    2010-01-01

    We present a 16 channel front end prototype implemented in 90nm CMOS IBM process and optimized for 5pF input capacitance. The primary motivation for this project is to study the usefulness of the CMOS technologies below 130nm for front end amplifiers optimized for short strip silicon detectors in Super Large Hadron Collider (SLHC) experiments [1]. In the presented design we

  5. A 5th generation SPARC64 processor is fabricated in 130nm SOI CMOS process with 8 layers of Cu metallization. It runs at

    E-print Network

    Koppelman, David M.

    over 190M transistors with 19M in logic circuits. The chip size is 18.14mm x 15.99mm. The error circuits, measures 18.14mm x 15.99mm and is covered with 5,858 low alpha emission lead bumps of which 269

  6. An integrated DC-DC step-up charge pump and step-down converter in 130 nm technology

    E-print Network

    Bochenek, M; Faccio, F; Kaplon, J

    2009-01-01

    After the LHC luminosity upgrade the number of readout channels in the ATLAS Inner Detector will be increased by one order of magnitude and delivering the power to the front-end electronics as well as cooling will become a critical system issue. Therefore a new solution for powering the readout electronics has to be worked out. Two main approaches for the power distribution are under development, the serial powering of a chain of modules and the parallel powering with a DCDC conversion stage on the detector. In both cases switchedcapacitor converters in the CMOS front-end chips will be used. In the paper we present the design study of a step-up charge pump and a step-down converter. In optimized designs power efficiency of 85 % for the step-up converter and 92 % for the step-down converter has been achieved.

  7. A Comparative Study of Heavy Ion and Proton Induced Bit Error Sensitivity and Complex Burst Error Modes in Commercially Available High Speed SiGe BiCMOS

    NASA Technical Reports Server (NTRS)

    Marshall, Paul; Carts, Marty; Campbell, Art; Reed, Robert; Ladbury, Ray; Seidleck, Christina; Currie, Steve; Riggs, Pam; Fritz, Karl; Randall, Barb

    2004-01-01

    A viewgraph presentation that reviews recent SiGe bit error test data for different commercially available high speed SiGe BiCMOS chips that were subjected to various levels of heavy ion and proton radiation. Results for the tested chips at different operating speeds are displayed in line graphs.

  8. A CMOS baseband receiver for wireless broadband communications

    Microsoft Academic Search

    Seunghyun Jang; Seung-Sik Lee; Sang-Sung Choi; Kwang-Chun Lee

    2010-01-01

    This paper presents an UWB baseband receiver including VGAs, LPFs, FGAs and IO buffers, fully integrated in 130 nm CMOS process. The voltage gain range by two VGAs and a FGA for each I\\/Q path is from -5 to +65 dB providing a dynamic range of 70 dB. For a more stable operation against variations in process, voltage and temperature

  9. Radiation Characteristics of a 0.11 Micrometer Modified Commercial CMOS Process

    NASA Technical Reports Server (NTRS)

    Poivey, Christian; Kim, Hak; Berg, Melanie D.; Forney, Jim; Seidleck, Christina; Vilchis, Miguel A.; Phan, Anthony; Irwin, Tim; LaBel, Kenneth A.; Saigusa, Rajan K.; Mirabedini, Mohammad R.; Finlinson, Rick; Suvkhanov, Agajan; Hornback, Verne; Sung, Jun; Tung, Jeffrey

    2006-01-01

    We present radiation data, Total Ionizing Dose and Single Event Effects, on the LSI Logic 0.11 micron commercial process and two modified versions of this process. Modified versions include a buried layer to guarantee Single Event Latchup immunity.

  10. DEVELOPMENT OF CMOS ACTIVE PIXEL IMAGE SENSORS FOR LOW COST COMMERCIAL APPLICATIONS

    Microsoft Academic Search

    Russell C. Gee; Sabrina E. Kcmcny; Quicsup Kim; Junichi Nakamura; Robert H. Nixon; Monico A. Ortiz; Craig Staller; Zhimin Zhou; Eric R Fossum

    2004-01-01

    The Jet Propulsion Laboratory, under sponsorship from the NASA Oflice of Advanced Cmeepts and Technology, has been developing a second-generat ion scdid-state image sensor technology. Charge-coupled devices (CCDS) are a well-establish ed first generation image sensor technology. For both commercial and NASA applications, CCDS have numerous short comings. In response, the active phcl sensor (APS) technology has been under research,

  11. Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

    NASA Technical Reports Server (NTRS)

    Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Staller, C.; Zhou, Z; Fossum, E.

    1994-01-01

    JPL, under sponsorship from the NASA Office of Advanced Concepts and Technology, has been developing a second-generation solid-state image sensor technology. Charge-coupled devices (CCD) are a well-established first generation image sensor technology. For both commercial and NASA applications, CCDs have numerous shortcomings. In response, the active pixel sensor (APS) technology has been under research. The major advantages of APS technology are the ability to integrate on-chip timing, control, signal-processing and analog-to-digital converter functions, reduced sensitivity to radiation effects, low power operation, and random access readout.

  12. Cross/bar polymer electro-optic routing switch with broadband flatting spectral response over 130 nm: Principle, design and analysis

    NASA Astrophysics Data System (ADS)

    Zheng, Chuan-Tao; Zheng, Li-Hua; Luo, Qian-Qian; Liang, Lei; Ma, Chun-Sheng; Zhang, Da-Ming

    2013-05-01

    A novel non-resonance 2×2 polymer electro-optic (EO) switch with flatting spectral response is proposed by employing two-section reversed active Mach-Zehnder interferometers (MZIs), a passive middle directional coupler (M-DC) and two passive phase generating couplers (PGCs). Two crosstalk compensations are performed by optimizing the PGCs to broaden the spectrum under bar-state and optimizing the two active MZIs to broaden the spectrum under cross-state. The bar-state and cross-state voltages are 0 and ±4 V, respectively, with the two optimized MZI EO region lengths of 4068 and 5941 ?m. Sufficiently considering wavelength dispersion of material and waveguide, a wide spectrum over 130 nm (1473-1603 nm) is achieved for dropping the crosstalk below -30 dB, and within this range, an insertion loss of 1.8-12.3 dB is observed. Under the same crosstalk level, this spectrum is over 2 times of that of the traditional 2×2 MZI switch (60 nm) based on the same materials. This broadband 2×2 switch is more attractive than our previously reported broadband 1×1 switch due to cross/bar routing operations other than simple ON/OFF functions.

  13. Visible and ultraviolet /800-130 nm/ extinction of vapor-condensed silicate, carbon, and silicon carbide smokes and the interstellar extinction curve

    NASA Technical Reports Server (NTRS)

    Stephens, J. R.

    1980-01-01

    The extinction curves from 800 to 130 nm (1.25-7.7/micron) of amorphous silicate smokes nominally of olivine and pyroxene composition, carbon smokes, and crystalline SiC smokes are presented. The SiC smoke occurred in the low-temperature (beta) cubic structural form. The SiC smoke showed an absorption edge which occurred at significantly longer wavelengths than the calculated extinction profile of the hexagonal SiC form previously used to calculate the interstellar extinction profile. Neither SiC nor amorphous silicates show an extinction band similar to the observed 6.6/micron astronomical extinction band. The infrared absorption peaks for the silicate and SiC samples near 10 microns and 11-13 microns, respectively, were also measured. The ultraviolet to infrared extinction ratio for the amorphous silicate samples is similar to the observed astronomical extinction ratio. The measured extinction ratios for SiC smokes are significantly below the interstellar extinction ratio. The extinction peak of the carbon smokes occurred at 4.0 and 4.25/micron, for samples of mean radii 13 and 6 nm, respectively. The extinction profile is distinctly different from that predicted for graphite grains of the same size, and is similar to that predicted for glassy carbon grains.

  14. A Schottky barrier diode ultra-wideband amplitude modulation (AM) detector in foundry CMOS technology

    Microsoft Academic Search

    Swaminathan Sankaran; Kenneth KO

    2006-01-01

    Utility of Schottky diodes fabricated in foundry digital 130-nm CMOS technology is demonstrated by implementing an ultra-wideband (UWB) amplitude modulation detector consisting of a low noise amplifier (LNA), a Schottky diode rectifier, and a low-pass filter. The detector is matched to 50 Omega, from 0-10.3 GHz and 0-1.7 GHz at the input and output, respectively and almost covers the entire

  15. CMOS Programmable Gain Distributed Amplifier With 0.5dB Gain Steps

    Microsoft Academic Search

    Byul Hur; William R. Eisenstadt

    2011-01-01

    A new CMOS programmable gain distributed am- plifier with 0.5-dB gain steps is fabricated in a 130-nm process. The circuit is designed to demonstrate broadband ( 1 decade) programmable gains with excellent matching and high isolation for use in RF integrated-circuit testing. The measured slope of loss is approximately 3 dB\\/decade over frequencies from 0.8 to 9 GHz where input

  16. A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

    Microsoft Academic Search

    Sanggeun Jeon; Yu-Jiu Wang; Hua Wang; Florian Bohn; Arun Natarajan; Aydin Babakhani; Ali Hajimiri

    2008-01-01

    This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the

  17. A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems.

    PubMed

    Zheng, Xuezhe; Liu, Frankie; Patil, Dinesh; Thacker, Hiren; Luo, Ying; Pinguet, Thierry; Mekis, Attila; Yao, Jin; Li, Guoliang; Shi, Jing; Raj, Kannan; Lexau, Jon; Alon, Elad; Ho, Ron; Cunningham, John E; Krishnamoorthy, Ashok V

    2010-01-01

    We report ultra-low-power (690fJ/bit) operation of an optical receiver consisting of a germanium-silicon waveguide detector intimately integrated with a receiver circuit and embedded in a clocked digital receiver. We show a wall-plug power efficiency of 690microW/Gbps for the photonic receiver made of a 130nm SOI CMOS Ge waveguide detector integrated to a 90nm Si CMOS receiver circuit. The hybrid CMOS photonic receiver achieved a sensitivity of -18.9dBm at 5Gbps for BER of 10(-12). Enabled by a unique low-overhead bias refresh scheme, the receiver operates without the need for DC balanced transmission. Small signal measurements of the CMOS Ge waveguide detector showed a 3dB bandwidth of 10GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit will be possible. PMID:20173840

  18. Ultra-low-energy all-CMOS modulator integrated with driver.

    PubMed

    Zheng, Xuezhe; Lexau, Jon; Luo, Ying; Thacker, Hiren; Pinguet, Thierry; Mekis, Attila; Li, Guoliang; Shi, Jing; Amberg, Philip; Pinckney, Nathaniel; Raj, Kannan; Ho, Ron; Cunningham, John E; Krishnamoorthy, Ashok V

    2010-02-01

    We report the first sub-picojoule per bit (400fJ/bit) operation of a silicon modulator intimately integrated with a driver circuit and embedded in a clocked digital transmitter. We show a wall-plug power efficiency below 400microW/Gbps for a 130nm SOI CMOS carrier-depletion ring modulator flip-chip integrated to a 90nm bulk Si CMOS driver circuit. We also demonstrate stable error-free transmission of over 1.5 petabits of data at 5Gbps over 3.5 days using the integrated modulator without closed-loop ring resonance tuning. Small signal measurements of the CMOS ring modulator, sans circuit, showed a 3dB bandwidth in excess of 15GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit is possible while retaining compatibility with CMOS drive voltages. PMID:20174136

  19. Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

    NASA Astrophysics Data System (ADS)

    Rizzo, G.; Comott, D.; Manghisoni, M.; Re, V.; Traversi, G.; Fabbri, L.; Gabrielli, A.; Giorgi, F.; Pellegrini, G.; Sbarra, C.; Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Berra, A.; Lietti, D.; Prest, M.; Bevan, A.; Wilson, F.; Beck, G.; Morris, J.; Gannaway, F.; Cenci, R.; Bombelli, L.; Citterio, M.; Coelli, S.; Fiorini, C.; Liberali, V.; Monti, M.; Nasri, B.; Neri, N.; Palombo, F.; Stabile, A.; Balestri, G.; Batignani, G.; Bernardelli, A.; Bettarini, S.; Bosi, F.; Casarosa, G.; Ceccanti, M.; Forti, F.; Giorgi, M. A.; Lusiani, A.; Mammini, P.; Morsani, F.; Oberhof, B.; Paoloni, E.; Perez, A.; Petragnani, G.; Profeti, A.; Soldani, A.; Walsh, J.; Chrzaszcz, M.; Gaioni, L.; Manazza, A.; Quartieri, E.; Ratti, L.; Zucca, S.; Alampi, G.; Cotto, G.; Gamba, D.; Zambito, S.; Dalla Betta, G.-F.; Fontana, G.; Pancheri, L.; Povoli, M.; Verzellesi, G.; Bomben, M.; Bosisio, L.; Cristaudo, P.; Lanceri, L.; Liberti, B.; Rashevskaya, I.; Stella, C.; Vitale, L.

    2013-08-01

    In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10-15 ?m in both coordinates, low material budget <1%X0, and the ability to withstand a background hit rate of several tens of MHz/cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.

  20. An 80Gb\\/s 2\\/sup 31\\/-1 pseudorandom binary sequence generator in SiGe BiCMOS technology

    Microsoft Academic Search

    Timothy O. Dickson; Ekaterina Laskin; Imran Khalid; Rudy Beerkens; Jingqiong Xie; Boris Karajica; Sorin P. Voinigescu

    2005-01-01

    A2 1 pseudorandom binary sequence (PRBS) generator with adjustable output data rates up to 80 Gb\\/s is re- ported in a production 130-nm BiCMOS process with 150-GHz SiGe heterojunction bipolar transistor (HBT). The pseudorandom sequence is generated at 20 Gb\\/s using a linear feedback shift register (FSR), which is then multiplexed up to 80 Gb\\/s with a 4:1 multiplexer. A

  1. 3D monolithically stacked CMOS Active Pixel Sensors for particle position and direction measurements

    NASA Astrophysics Data System (ADS)

    Servoli, L.; Passeri, D.; Morozzi, A.; Magalotti, D.; Piperku, L.

    2015-01-01

    In this work we propose a 3D monolithically stacked, multi-layer detectors based on CMOS Active Pixel Sensors (APS) layers which allows at the same time accurate estimation of the impact point and of the incidence angle an ionizing particle. The whole system features two fully-functional CMOS APS matrix detectors, including both sensing area and control/signal elaboration circuitry, stacked in a monolithic device by means of Through Silicon Via (TSV) connections thanks to the capabilities of the CMOS vertical scale integration (3D-IC) 130 nm Chartered/Tezzaron technology. In order to evaluate the suitability of the two layer monolithic active pixel sensor system to reconstruct particle tracks, tests with proton beams have been carried out at the INFN LABEC laboratories in Florence (Italy) with 3 MeV proton beam.

  2. A CMOS readout circuit for microstrip detectors

    NASA Astrophysics Data System (ADS)

    Nasri, B.; Fiorini, C.

    2015-03-01

    In this work, we present the design and the results of a CMOS analog channel for silicon microstrips detectors. The readout circuit was initially conceived for the outer layers of the SuperB silicon vertex tracker (SVT), but can serve more generally other microstrip-based detection systems. The strip detectors considered show a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been investigated. The ASIC is composed by a preamplifier, shaping amplifier and a Time over Threshold (T.o.T) block for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit includes the possibility to select the peaking time of the shaper output from four values: 250 ns, 375 ns, 500 ns and 750 ns. In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The ASIC prototype has been fabricated in the 130 nm IBM technology which is considered intrinsically radiation hard. The results of the experimental characterization of a produced prototype are satisfactorily matched with simulation.

  3. 560 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 2, FEBRUARY 2012 A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque

    E-print Network

    Zhang, Tong

    tunneling junction (MTJ) and MOS transistors in the scaled technologies severely limit the yield of STT states of a magnetic tunneling junction (MTJ) device. The conventional MRAM technology uses a current cell structure, fast read/write speed ( ns), high endurance, high array density, and excellent CMOS

  4. CMOS-Integrated RF MEMS Resonators

    Microsoft Academic Search

    Maxim K. Zalalutdinov; Joshua D. Cross; Jeffrey W. Baldwin; Bojan R. Ilic; Wenzhe Zhou; Brian H. Houston; Jeevak M. Parpia

    2010-01-01

    We present a design approach that enables monolithic integration of high-quality-factor (Q) radio-frequency (RF) microelectromechanical systems (MEMS) resonators with CMOS electronics. Commercially available CMOS processes that feature two polysilicon layers and field oxide isolation can be used to implement this approach. By using a nonplanar resonator geometry in conjunction with mechanical stress in polycrystalline silicon (poly) gate layers, we create

  5. Solar XUV Imaging and Nondispersive Spectroscopy for Solar-C Enabled by Scientific CMOS APS Arrays

    Microsoft Academic Search

    Robert A. Stern; J. R. Lemen; L. Shing; J. Janesick; J. Tower

    2009-01-01

    Monolithic CMOS Advanced Pixel Sensor (APS) arrays are showing great promise as eventual replacements for the current workhorse of solar physics focal planes, the scientific CCD. CMOS APS devices have individually addressable pixels, increased radiation tolerance compared to CCDs, and require lower clock voltages, and thus lower power. However, commercially available CMOS chips, while suitable for use with intensifiers or

  6. A two-tier monolithically stacked CMOS Active Pixel Sensor to measure charged particle direction

    NASA Astrophysics Data System (ADS)

    Passeri, D.; Servoli, L.; Meroli, S.; Magalotti, D.; Placidi, P.; Marras, A.

    2014-05-01

    In this work we present an innovative approach to particle tracking based on CMOS Active Pixel Sensors (APS) layers, monolithically integrated in an all-in-one chip featuring multiple, stacked, fully functional detector layers capable to provide momentum measurement (particle direction) within a single detector by using multiple layer impact point coordinates. The whole system will results in a very low material detector, since each layer can be thinned down to tens of micrometres, thus dramatically reducing multiple scattering issues. To build such a detector, we rely on the capabilities of the CMOS vertical scale integration (3D-IC) 130 nm Chartered/Tezzaron technology, used to integrate two fully-functional CMOS APS matrix detectors, including both sensing area and control/signal elaboration circuitry, stacked in a monolithic device by means of Through Silicon Via (TSV) connections. Such a detector would allow accurate estimation of the impact point of an ionizing particle and of its incidence angle. Two batches of the first chip prototype have been produced and characterized using particle beams (e.g. protons) demonstrating the suitability of particle direction measurement with a single, multiple layers, 3D vertically stacked APS CMOS detector.

  7. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    PubMed Central

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-01-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18?um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

  8. CMOS MEMS - present and future

    Microsoft Academic Search

    Henry Baltes; Oliver Brand; Andreas Hierlemann; Dirk Lange; Christoph Hagleitner

    2002-01-01

    The paper reviews the state-of-the-art in the field of CMOS-based microelectromechanical systems (MEMS). The different CMOS MEMS fabrication approaches, pre-CMOS, intermediate-CMOS, and post-CMOS, are summarized and examples are given. Two microsystems fabricated with post-CMOS micromachining are presented, namely a mass-sensitive chemical sensor for detection of organic volatiles in air and a 10-cantilever force sensor array for application in scanning probe

  9. Ion traps fabricated in a CMOS foundry

    NASA Astrophysics Data System (ADS)

    Mehta, K. K.; Eltony, A. M.; Bruzewicz, C. D.; Chuang, I. L.; Ram, R. J.; Sage, J. M.; Chiaverini, J.

    2014-07-01

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  10. Ion traps fabricated in a CMOS foundry

    E-print Network

    K. K. Mehta; A. M. Eltony; C. D. Bruzewicz; I. L. Chuang; R. J. Ram; J. M. Sage; J. Chiaverini

    2014-06-13

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, in any modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  11. Ion traps fabricated in a CMOS foundry

    E-print Network

    Mehta, K K; Bruzewicz, C D; Chuang, I L; Ram, R J; Sage, J M; Chiaverini, J

    2014-01-01

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, in any modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  12. Clocked CMOS calculator circuitry

    Microsoft Academic Search

    Y. Suzuki; K. Odagawa; T. Abe

    1973-01-01

    A novel circuit technique that has been applied to the world's first CMOS-LSI for a desktop calculator is described in detail. The CMOS-LSI includes 3300 elements and has a chip size of about 200 mil square, operates at 6 V supply voltage, and dissipates power of about 1 mW at a clock frequency of 50 kHz.

  13. CMOS Oscillators INTRODUCTION

    E-print Network

    Markatos, Evangelos P.

    . To determine the frequency of oscillation, it is necessary to examine the propagation delay of the inverters. CMOS propagation delay depends on supply voltage and load ca- pacitance. Several curves for propagation delay for Fair- child's 74C line of CMOS gates are reproduced in Figure 3. From these, the natural

  14. A CMOS humidity sensor with on-chip calibration

    Microsoft Academic Search

    Y. Y. Qiu; C. Azeredo-Leme; L. R. Alcįcer; J. E. Franca

    2001-01-01

    This paper describes a capacitive humidity sensor with on-chip calibration circuit fabricated by a standard CMOS process to achieve a cost-effective solution for accurate and reliable humidity measurement. The humidity sensing property on-chip is obtained by a post-processing step after the standard CMOS fabrication and whereby a commercial polyimide is deposited on the packaged chip. The sensing principle of the

  15. CMOS compatible edge coupled capacitive MEMS switch for RF applications

    Microsoft Academic Search

    Shumin Zhang; Wansheng Su; M. E. Zaghloul

    2007-01-01

    This paper presents the design, simulation and fabrication of a CMOS process compatible capacitive MEMS switch. The MEMS switch uses thermal actuation and finger structures for capacitive coupling. The design is fabricated using commercial 0.6 um CMOS process and post-processed using mask-less RIE process. Results show that the insertion loss is 0.7 dB at 2 GHz and the isolation is

  16. Scintillator and CMOS APS Imager for Radiography Conditions

    Microsoft Academic Search

    Kwang Hyun Kim; Young Soo Kim

    2008-01-01

    We evaluated X-ray image performance for several scintillators and a CMOS APS imager by both diagnostic radiography and mammography conditions. Commercially available scintillators such as Lanex screen, needle structured CsI (Tl), and fiber optic structured CsI (Tl) were coupled with a CMOS APS imager. The X-ray machines used in this study were fixed tube voltage of 80 kVp and variable

  17. Evaluation of CMOS APS imager for digital radiography and mammography

    Microsoft Academic Search

    Kwang Hyun Kim; Jeon Sung Chae; Sun Woo Yuk; Young Soo Kim; Young Ki Chi; Gyuseong Cho

    2003-01-01

    We evaluated image performance of scintillator coupled CMOS APS imager for radiography and mammography conditions, respectively. 80 kVp and 28 kVp of X-ray tube voltage at the SID of 720 mm and 600 mm were set for each condition. Commercially available scintillator such as Lanex screen, needle structured CsI(Tl), and fiber optic structured CsI (Tl) were coupled CMOS APS imager.

  18. Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis

    Microsoft Academic Search

    John Paul Shen; F. Joel Ferguson

    1988-01-01

    FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0\\/1 fault model. Faults

  19. Fully Integrated Single Photon Avalanche Diode Detector in Standard CMOS 0.18- m Technology

    Microsoft Academic Search

    Naser Faramarzpour; M. Jamal Deen; Shahram Shirani; Qiyin Fang

    2008-01-01

    Avalanche photodiodes (APDs) operating in Geiger mode can detect weak optical signals at high speed. The implementation of APD systems in a CMOS technology makes it possible to integrate the photodetector and its peripheral circuits on the same chip. In this paper, we have fabricated APDs of different sizes and their driving circuits in a commercial 0.18-mum CMOS technology. The

  20. Thin, fully depleted monolithic active pixel sensor based on 3D integration of heterogeneous CMOS layers

    Microsoft Academic Search

    W. Dulinski; G. Bertolone; R. de Masi; Y. Degerli; A. Dorokhov; F. Morel; F. Orsini; L. Ratti; C. Santos; V. Re; X. Wei; M. Winter

    2009-01-01

    On the way towards fast, radiation tolerant and ultra thin CMOS radiation sensors, we propose new generation of devices based on commercial availability of vertical integration of several CMOS wafers (3D Electronics). In this process, each wafer may be thinned down to about 10 microns end equipped with through-silicon vias (TSV) allowing for electrical interconnection between wafers at a very

  1. CMOS image sensors: State-of-the-art and future perspectives

    Microsoft Academic Search

    Albert THEUWISSEN

    2007-01-01

    Over the last decade, CMOS image sensor technology made huge progress. Not only the performance of the imagers was drastically improved, but also their commercial success boomed after the introduction of mobile phones with an onboard camera. Many scientists and marketing specialists predicted 15 years ago that CMOS image sensors were going to completely take over from CCD imagers, in

  2. Graphene for CMOS and Beyond CMOS Applications

    Microsoft Academic Search

    Sanjay K. Banerjee; Leonard Franklin Register; Emanuel Tutuc; Dipanjan Basu; Seyoung Kim; Dharmendar Reddy; Allan H. MacDonald

    2010-01-01

    Owing in part to complementary metal-oxide-semiconductor (CMOS) scaling issues, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide a solution beyond the 22-nm node. Single and few layers of carbon sheets (graphene) have been fabricated by a variety of techniques including mechanical exfoliation and chemical vapor deposition, and field-effect devices have been demonstrated

  3. CMOS MEMS capacitive absolute pressure sensor

    NASA Astrophysics Data System (ADS)

    Narducci, M.; Yu-Chia, L.; Fang, W.; Tsai, J.

    2013-05-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal-oxide-semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa-1 in the pressure range of 0-300 kPa.

  4. DRAM lithographic scaling in the sub-130-nm regime

    NASA Astrophysics Data System (ADS)

    Bukofsky, Scott J.

    2001-09-01

    Continuous downward pressure on chip size has led to aggressive ground rule shrink paths in the semiconductor industry, especially in the DRAM sector. Ever-decreasing feature sizes have necessitated the extensive use of attenuated phase shift masks, off-axis illumination, optical proximity correction, etc. For the foreseeable future, the ability to meet the demands of the design is closely tied to the extendibility of ArF lithography. This paper explores DRAM lithographic scaling by predicting required process latitude and depth of focus based on litho-graphic merit function scaling. This allows the predictions to be anchored against data collected on current products, as well as indicating the rate at which learning must occur for a ground rule shrink to be successful. Modeling of ArF extendibility is presented, with particular emphasis on the role of alternating phase shift masks. Additionally, simple signal-to-noise argu-ments are made in connection with the required process window for a given technology, taking into the account fundamental error sources of the process. The analyses are anchored to existing technologies wherever possible. The results indicate that ArF lithography will extend through the 90 nm technology node with a critical dependence on alternating phase shift masks.

  5. Prompt and total dose response of hard 4K and 16K CMOS static random access memories (SRAMs)

    Microsoft Academic Search

    A. A. Witteles; H. Volmerange; H. Davidson; H. Yue; R. Jennings; G. J. Brucker

    1984-01-01

    Total dose (TD) and prompt dose (PD) rate effects were measured in three types of SRAMs: Harris 6504RH (CMOS\\/bulk) and RCA 11121 (CMOS\\/SOS) which are commercially available 4K memories, and developmental samples of a more recent hardened 16K CMOS\\/SOS SRAM (RCA TA 12702). TD exposure was performed with C0-60 at dose rates of 5-240 rad (Si)\\/s, while PD testing used

  6. Verity - A formal verification program for custom CMOS circuits

    Microsoft Academic Search

    Andreas Kuehlmann; Arvind Srinivasan; David P. Lapotin

    1995-01-01

    In an effort to fully exploit CMOS performance, custom design techniques are used extensively in commercial microprocessor design. However, given the complexity of cur- rent generation processors and the necessity for manual designer intervention through- out the design process, proving design correctness is a major concern. In this paper we discuss Verity, a formal verification program for symbolically proving the

  7. Thermally actuated CMOS micromirrors

    Microsoft Academic Search

    J. Bühler; J. Funk; O. Paul; F.-P. Steiner; H. Baltes

    1995-01-01

    Thermally actuated micromirrors fabricated using a standard CMOS process and one subsequent anisotropic silicon etch step are presented. The device consists of a mirror plate supported by bimorph cantilever beams. Even short beams show a large deflection effect. A theoretical analysis valid for n-morph bending beams has been derived and found to be consistent with experimental and computer-simulation results.

  8. CMOS distributed amplifiers

    Microsoft Academic Search

    Juan C. Ranuįrez; Yogesh K. Ramadass; M. Jamal Deen

    2004-01-01

    This paper reviews the characteristics of broadband distributed amplifiers (DA) and traveling wave amplifiers (TWA) implemented in CMOS technology. The basic equations that govern the performance and design of DAs in terms of gain, bandwidth, matching and noise are summarized, as well as the implications of the use of transmission lines to replace on-chip inductors. The difficulties that arise for

  9. CMOS APS MTF modeling

    Microsoft Academic Search

    Igor Shcherback; Orly Yadid-Pecht

    2001-01-01

    In this paper, a unified model, based on a thorough analysis of experimental data, is developed for the overall modulation transfer function (MTF) estimation for CMOS image sensors. The model covers the physical diffusion effect together with the influence of the pixel active area geometrical shape. Comparison of both our predicted results and the MTF calculated from the point spread

  10. CMOS-based resonant sensors

    Microsoft Academic Search

    Oliver Brand

    2005-01-01

    The paper provides an overview of resonant sensors based on CMOS technology. Applications of these sensors range from inertial sensors to chemical\\/biochemical sensors, from atomic force microscopy to high-frequency filters. CMOS technology enables to co-integrate the resonant microstructures with necessary analog and digital circuit functions. The paper discusses CMOS-based fabrication approaches for resonant sensors, possible sensing and actuation schemes, suitable

  11. Micromachined thermally based CMOS microsensors

    Microsoft Academic Search

    HENRY BALTES; OLIVER PAUL; OLIVER BRAND

    1998-01-01

    An integrated circuit (IC) approach to thermal microsensors is presented. The focus is on thermal sensors with on-chip bias and signal conditioning circuits made by industrial complementary metal-oxide-semiconductor (CMOS) IC technology in combination with post-CMOS micromachining or deposition techniques. CMOS materials and physical effects pertinent to thermal sensors are summarized together with basic structures used for microheaters, thermistors, thermocouples, thermal

  12. Analytical models of CMOS APS

    Microsoft Academic Search

    Victor A. Shilin; Pavel A. Skrylev; A. L. Stempkovsky

    2002-01-01

    The comparison of the CMOS APS and CCD device features has been made. It is expedient to develop high resolution and wide dynamic range systems with the PhCCD and simple systems with CMOS APS, which allows developing camera-on-a-chip. Schematic and layout types of CMOS APS pixel: with 3, 4 transistors per pixel, and with 5 transistors per two pixels have

  13. Building strong partnerships with CMOs.

    PubMed

    Dye, Carson F

    2014-07-01

    CFOs and chief medical officers (CMOs) can build on common traits to form productive partnerships in guiding healthcare organizations through the changes affecting the industry. CFOs can strengthen bonds with CMOs by taking steps to engage physicians on their own turf--by visiting clinical locations and attending medical-executive committee meetings, for example. Steps CFOs can take to help CMOs become more acquainted with the financial operations of health systems include demonstrating the impact of clinical decisions on costs and inviting CMOs to attend finance-related meetings. PMID:25076635

  14. CMOS Gates Demonstration

    NSDL National Science Digital Library

    This website, hosted by the University of Hamburg, provides an in depth description of the basic operation of CMOS circuits including inverters, NAND gates, and NOR gates. Circuit simulations are shown and power dissipation is discussed. Some of these include: inverters, NAND and NOR gates, transmission gates, D-latch with T-gates, power consumption, complex gates and SRAM cells. Overall, the site is perfect for undergraduate computer science majors to learn more about the exciting topic of semiconductors.

  15. Integrated CMOS RF amplifier

    NASA Technical Reports Server (NTRS)

    Charity, C.; Whitaker, S.; Purviance, J.; Canaris, M.

    1990-01-01

    This paper reports an integrated 2.0 micron CMOS RF amplifier designed for amplification in the 420-450 MHz frequency band. Design techniques are shown for the test amplifier configuration. Problems of decreased amplifier bandwidth, gain element instability, and low Q values for the inductors were encountered. Techniques used to overcome these problems are discussed. Layouts of the various elements are described and a summary of the simulation results are included. Test circuits have been submitted to MOSIS for fabrication.

  16. Mitigating defective CMOS to Non-CMOS vias in CMOS\\/Molecular memories

    Microsoft Academic Search

    Nor Zaidi Haron; Said Hamdioui

    2010-01-01

    CMOS\\/Molecular (CMOL) memory is one of the emerging memory technologies that promises increased data storage, reduced power consumption and minimized fabrication complexity. The fabrication of these memories is based on the stacking of non-CMOS-based memory cell array on the top of CMOS-based peripheral circuits. Similarly to existing 3D technology, vertical vias are utilized to connect the two components. Because of

  17. Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

    SciTech Connect

    Sumant, A.V.; Auciello, O.; Yuan, H.-C; Ma, Z.; Carpick, R. W.; Mancini, D. C.; Univ. of Wisconsin; Univ. of Pennsylvania

    2009-05-01

    Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materials integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.

  18. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    PubMed Central

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  19. Fully CMOS analog and digital SiPMs

    NASA Astrophysics Data System (ADS)

    Zou, Yu; Villa, Federica; Bronzi, Danilo; Tisa, Simone; Tosi, Alberto; Zappa, Franco

    2015-03-01

    Silicon Photomultipliers (SiPMs) are emerging single photon detectors used in many applications requiring large active area, photon-number resolving capability and immunity to magnetic fields. We present three families of analog SiPM fabricated in a reliable and cost-effective fully standard planar CMOS technology with a total photosensitive area of 1×1 mm2. These three families have different active areas with fill-factors (21%, 58.3%, 73.7%) comparable to those of commercial SiPM, which are developed in vertical (current flow) custom technologies. The peak photon detection efficiency in the near-UV tops at 38% (fill-factor included) comparable to commercial custom-process ones and dark count rate density is just a little higher than the best-in-class commercial analog SiPMs. Thanks to the CMOS processing, these new SiPMs can be integrated together with active components and electronics both within the microcell and on-chip, in order to act at the microcell level or to perform global pre-processing. We also report CMOS digital SiPMs in the same standard CMOS technology, based on microcells with digitalized processing, all integrated on-chip. This CMOS digital SiPMs has four 32×1 cells (128 microcells), each consisting of SPAD, active quenching circuit with adjustable dead time, digital control (to switch off noisy SPADs and readout position of detected photons), and fast trigger output signal. The achieved 20% fill-factor is still very good.

  20. Regenerative switching CMOS system

    DOEpatents

    Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

    1998-01-01

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

  1. Regenerative switching CMOS system

    DOEpatents

    Welch, J.D.

    1998-06-02

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

  2. A CMOS focal-plane array for terahertz imaging

    Microsoft Academic Search

    U. R. Pfeiffer; E. Ojefors; A. Lisauskas; D. Glaab; F. Voltolina; V. M. F. Nzogang; P. H. Bolivar; H. G. Roskos

    2008-01-01

    A terahertz focal-plane array (FPA) for video-rate imaging applications has been fabricated in a commercially available CMOS process technology. The 3times5 pixel array uses conventional low-cost quarter-micron NMOS transistors for incoherent power detection. Each pixel has a size of 150times150 mum2 and consists of an on-chip antenna, an incoherent power detection circuit, and a 43-dB amplifier with a 1.6-MHz bandwidth.

  3. Noise Sources in Bulk CMOS

    Microsoft Academic Search

    Kent H. Lundberg

    The noise behavior of bulk CMOS devices is dominated primarily by two noise sources: thermal noise and ?icker (1=f) noise. Other sources that are sometimes present in the noise spectrum are shot noise, generation\\/recombination noise, and \\\\popcorn\\

  4. Transistor sizing in CMOS circuits

    Microsoft Academic Search

    Mehmet A. Cirit

    1987-01-01

    The problem of optimally sizing transistors in a VLSI CMOS circuit is considered. Models and algorithms for performing optimization on a single path using RC-tree approximation are presented. The results of an automatic optimization procedure are discussed.

  5. Reliability evaluation of CMOS RAMs

    Microsoft Academic Search

    C. J. Salvo; A. T. Sasaki

    1982-01-01

    The results of an evaluation of the reliability of a 1K x 1 bit CMOS RAM and a 4K x 1 bit CMOS RAM for the USAF are reported. The tests consisted of temperature cycling, thermal shock, electrical overstress-static discharge and accelerated life test cells. The study indicates that the devices have high reliability potential for military applications. Use-temperature failure

  6. CMOS array design automation techniques

    NASA Technical Reports Server (NTRS)

    Lombardi, T.; Feller, A.

    1976-01-01

    The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

  7. Proof of principle study of the use of a CMOS active pixel sensor for proton radiography

    SciTech Connect

    Seco, Joao; Depauw, Nicolas [Francis H. Burr Proton Therapy Center, Department of Radiation Oncology, Massachusetts General Hospital (MGH), Boston, Massachusetts 02114 (United States)

    2011-02-15

    Purpose: Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). Methods: A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissue contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Results: Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Conclusion: Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The development and use of CMOS in proton radiography could allow in vivo proton range checks, patient setup QA, and real-time tumor tracking.

  8. TDC-based frequency synthesizer for wireless applications

    Microsoft Academic Search

    Robert Bogdan Staszewski; D. Leipold; Chih-Ming Hung; P. T. Balsara

    2004-01-01

    We analyze phase noise performance and further discuss details of an all-digital PLL that is used in a commercial 130 nm CMOS single-chip Bluetooth radio. The frequency synthesizer uses a digitally controlled oscillator with a digital loop filter and a time-to-digital converter that acts as a phase\\/frequency detector. When implemented in a deep-submicron CMOS, the presented architecture appears more advantageous

  9. CMOS APS PHOTORESPONSE AND CROSSTALK OPTIMIZATION ANALYSIS FOR SCALABLE CMOS TECHNOLOGIES

    E-print Network

    1 CMOS APS PHOTORESPONSE AND CROSSTALK OPTIMIZATION ANALYSIS FOR SCALABLE CMOS TECHNOLOGIES Igor developed for photoresponse estimation of a photodiode based CMOS Active Pixel Sensor (APS). We show its use for maximum pixel photosignal prediction and CMOS APS crosstalk (CTK) optimization. Our model reveals

  10. Finding Open Faults In CMOS Circuits

    NASA Technical Reports Server (NTRS)

    Chandramouli, R.

    1984-01-01

    Algorithm specifies sequence of input test signals and interpretation of resulting output signals for identifying stuck-open faults in complementary metal-oxide semiconductor (CMOS) integrated logic circuits. Incorporated in software for online production testing of CMOS circuits.

  11. Multiemitter BiCMOS logic circuit family

    Microsoft Academic Search

    Gerard Boudon; Pierre Mollier; Ieng Ong; Jean-Paul Nuez; Daniel Mauchauffee; Dominique Plassat; Jean-Louis Simonet; Frank Wallart

    1991-01-01

    A new multiemitter BiCMOS circuit using half-micrometer BiCMOS technology with a 3.6-V supply provides 85 % improvement in delay over CMOS design and 40 % improvement over conventional BiCMOS. This benefit is demonstrated in a 64-b carry look-ahead adder where most of the gates have a high number of inputs. A complete logic circuit family based on the multiemitter (ME)

  12. CMOS PIN fiber receiver and DVD OEIC

    Microsoft Academic Search

    A. Ghazi; T. Heide; H. Zimmermann; P. Seegebrecht

    1999-01-01

    Two monolithically integrated PIN CMOS OEICs (optoelectronic integrated circuits) are presented: A high-speed CMOS PIN fiber receiver for optical data transmission and optical interconnects and a CMOS PIN OEIC for optical storage systems. Both OEICs were integrated in a 1.0 ?m twin-well CMOS-process, using PIN-photodiodes as photodetectors. For the high-speed fiber receiver a NRZ data rate of 622 Mbit\\/s is

  13. An ultra low power CMOS motion detector

    Microsoft Academic Search

    Sang-Hyeok Yang; Kyoung-Bum Kim; Eung-Ju Kim; Kwang-Hyun Baek; Suki Kim

    2009-01-01

    This paper proposes a CMOS motion detector which consumes extremely low power. CMOS image sensor pixels in this motion detector senses image and image data are converted into just one-bit by using clocked comparators. Because using one-bit data makes additional processing units simple, total power consumption of this CMOS motion detector can be reduced. That is, internal memory which is

  14. Transient surface damage and latchup in CMOS devices. Final report, 13 May 1974--12 May 1975

    Microsoft Academic Search

    1975-01-01

    The work consists of concurrent studies of transient surface damage and latchup phenomena in irradiated CMOS devices. Data are presented for CMOS 4007 inverters from 0.0001 to 0.001 sec after exposure to ionizing radiation pulses. Commercial and research samples prepared on bulk silicon as well as silicon-on-sappire substrates are evaluated. High and low temperature annealing data are used to develop

  15. Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units

    NASA Astrophysics Data System (ADS)

    Smith, James H.; Montague, Stephen; Allen, James J.; Ellis, J. R.; Burgett, Scott M.

    1997-06-01

    One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, we will examine the key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) Minimum MEMS feature size, (2) Minimum CMOS feature size, (3) Maximum MEMS linear dimension, (4) Number of mechanical MEMS layers, and (5) MEMS/CMOS spacing. In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 micrometers , CMOS critical dimensions of 1.25 micrometers , MEMS linear dimensions of 1000 micrometers , a single mechanical level of polysilicon, and a 100 micrometers space between MEMS and CMOS.

  16. Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units

    SciTech Connect

    Smith, J.H.; Ellis, J.R.; Montague, S.; Allen, J.J.

    1997-03-01

    One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing. In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.

  17. A LOW-POWER CMOS NEURAL AMPLIFIER WITH AMPLITUDE MEASUREMENTS FOR SPIKE SORTING

    E-print Network

    Maryland at College Park, University of

    fabricated a prototype circuit in a commercially- available 1.5 m, 2-metal, 2-poly CMOS process that occupies inputs and the outputs are from: an amplifier, a peak detector, a trough detector, and a level detector contribution. Following the amplifier, we have implemented a peak detector, a trough detector, and a level

  18. A LOW-POWER CMOS NEURAL AMPLIFIER WITH AMPLITUDE MEASUREMENTS FOR SPIKE SORTING

    E-print Network

    Horiuchi, Timothy K.

    fabricated a prototype circuit in a commercially- available 1.5µm, 2-metal, 2-poly CMOS process that occupies inputs and the outputs are from: an amplifier, a peak detector, a trough detector, and a level detector contribution. Following the amplifier, we have implemented a peak detector, a trough detector, and a level

  19. Process-dependent thin-film thermal conductivities for thermal CMOS MEMS

    Microsoft Academic Search

    Martin von Arx; Oliver Paul; Henry Baltes

    2000-01-01

    The thermal conductivities ? of the dielectric and conducting thin films of three commercial CMOS processes were determined in the temperature range from 120 to 400 K. The measurements were performed using micromachined heatable test structures containing the layers to be characterized. The ? values of thermally grown silicon oxides are reduced from bulk fused silica by roughly 20%. The

  20. Development of CMOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Bertino, F.; Feller, A.; Greenhouse, J.; Lombardi, T.; Merriam, A.; Noto, R.; Ozga, S.; Pryor, R.; Ramondetta, P.; Smith, A.

    1979-01-01

    Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.

  1. 7.2 A ldGb/s, 3 mW CMOS Receiver for Optical Communication Azita Emami-Neyestanak, Dean Liu, Gordon Keeler, Noah Helman and Mark Horowitz

    E-print Network

    Emami-Neyestanak, Azita

    with commercial electronic circuits [2]-[5]. However a dense array of optical detectors requires very low-power7.2 A ldGb/s, 3 mW CMOS Receiver for Optical Communication Azita Emami-Neyestanak, Dean Liu, Gordon and fabricated in a 0.25-pm CMOS process. This receiver has no transimpedance amplifier and uses the parasitic

  2. Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

    NASA Technical Reports Server (NTRS)

    Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

    2012-01-01

    Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

  3. CMOS and post-CMOS on-chip microwave pulse power detectors

    Microsoft Academic Search

    Woochul Jeon; John Melngailis

    2006-01-01

    Schottky diode microwave pulse power detectors were fabricated by both a CMOS process and a post-CMOS process. Focused ion beam (FIB) milling and ion-induced deposition were used for the post-CMOS fabrication. Fabricated detectors were tested under RF direct injection and RF radiation. CMOS fabricated Schotty diode power detectors had 820ns pulse response time, 36dBm dynamic range, and began to detect

  4. Portable design rules for bulk CMOS

    NASA Astrophysics Data System (ADS)

    Griswold, T. W.

    1982-10-01

    It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

  5. Portable design rules for bulk CMOS

    NASA Technical Reports Server (NTRS)

    Griswold, T. W.

    1982-01-01

    It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

  6. Prediction of CMOS APS design enabling maximum photoresponse for scalable CMOS technologies

    Microsoft Academic Search

    Igor Shcherback; Orly Yadid-Pecht

    2004-01-01

    This brief represents the CMOS active pixel sensor (APS) photoresponse model use for maximum pixel photosignal prediction in scalable CMOS technologies. We have proposed a simple approximation determining the technology-scaling effect on the overall device photoresponse. Based on the above approximation and the data obtained from the CMOS 0.5 ?m process thorough investigation we have theoretically predicted, designed, measured and

  7. A wide band CMOS RF power detector

    Microsoft Academic Search

    Yijun ZhouandMichael; M. Chia Yan Wah

    2006-01-01

    This paper presents a wide band CMOS RF power detector using 0.25 mum technology. It includes a CMOS power detector unit, a chopper modulator and a logarithmic amplifier. Chopper technique is applied to reduce the dc offset. The CMOS RF power detector achieves 45 dB dynamic range with bandwidth up to 6 GHz. The power consumption is 17 mW from

  8. RF power amplifier integration in CMOS technology

    Microsoft Academic Search

    Y. J. E. Chen; M. Hamai; D. Heo; A. Sutono; S. Yoo; J. Laskar

    2000-01-01

    This paper explores different levels of integration for CMOS RF power amplifiers, including integration fully on chip, integration with LTCC passive components, and integration with off-chip components. At 1.9 GHz, the fully on-chip integrated CMOS PA can deliver 20 dBm output power with 16% efficiency. Because the LTCC inductors have much higher Q than the on-chip inductors, the CMOS PA

  9. Performance of downward scaled CMOS\\/SOS

    Microsoft Academic Search

    Sinji TAGUCHI; Hiroyuki TANGO; Kenji MAEGUCHI; Luong Mo Dang

    1979-01-01

    MOS\\/SOS structures have been investigated which suppress various anomalous currents and also adjust threshold voltage to the desired value for downward scaled CMOS\\/ SOS devices. Furthermore, short channel CMOS\\/SOS device performance has been discussed in comparison with the CMOS\\/Bulk. A deeper, boron implant was used for n-channel MOSFET on SOS to suppress the back channel current and the punch through

  10. A CCD\\/CMOS image motion sensor

    Microsoft Academic Search

    Massimo Gottardi; Woodward Yang

    1993-01-01

    Presents a 1D image motion sensor with a 115-pixel linear image sensor and analog CCD\\/CMOS processors that correlates two image frames that are spatially shifted between -5 and +5 pixels, to estimate object motion over a range of ±1 to ±5000 pixels\\/s. The CCD\\/CMOS smart sensor chip is fabricated with a standard double poly, double metal, 2-?m CMOS\\/CCD process available

  11. High speed CMOS technology for ASIC application

    Microsoft Academic Search

    H. Ooka; S. Murakami; M. Murayama; K. Yoshida; S. Takao; O. Kudoh

    1986-01-01

    In order to realize high speed and high density CMOS logic LSI's, an advanced two-level metal CMOS technology, having minimum feature size of 1.0 µm, has been developed. The technology has proven very high speed feasibility of CMOS logic arrays of less than half-nsec delay times, in addition to high reliability of 5V operation. BCD3structure is employed for 1.0 µm

  12. Reliability evaluation of CMOS RAMs

    NASA Astrophysics Data System (ADS)

    Salvo, C. J.; Sasaki, A. T.

    The results of an evaluation of the reliability of a 1K x 1 bit CMOS RAM and a 4K x 1 bit CMOS RAM for the USAF are reported. The tests consisted of temperature cycling, thermal shock, electrical overstress-static discharge and accelerated life test cells. The study indicates that the devices have high reliability potential for military applications. Use-temperature failure rates at 100 C were 0.54 x 10 to the -5th failures/hour for the 1K RAM and 0.21 x 10 to the -5th failures/hour for the 4K RAM. Only minimal electrostatic discharge damage was noted in the devices when they were subjected to multiple pulses at 1000 Vdc, and redesign of the 7 Vdc quiescent parameter of the 4K RAM is expected to raise its field threshold voltage.

  13. Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics

    SciTech Connect

    Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka; Pithawa, C. K. [Centre for Microelectronics, Prabhadevi, Mumbai-400028 (India)

    2011-10-20

    Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm{sup 2} with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensors are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.

  14. Del 1: Grunnleggende Digital CMOS YNGVAR BERG

    E-print Network

    Sahay, Sundeep

    Del 1: Grunnleggende Digital CMOS YNGVAR BERG I. Innhold TRANSISTOR SOM BRYTER anvendt i enkleMOS transistorer. Pass transistorer og transmisjonsporter. Tristate buffer og tristate inverter. Ulike typer. 2. Transistor som bryter. Kapittel 1.3 side 9. 3. CMOS inverter. Kapittel 1.4.1 side 10. 4. NAND

  15. Thermoelectric infrared sensors by CMOS technology

    Microsoft Academic Search

    Rene Lenggenhager; Henry Baltes; Jon Peer; Martin Forster

    1992-01-01

    The authors report two integrated thermoelectric infrared sensors on thin silicon oxide\\/nitride microstructures realized by industrial CMOS IC technology, followed by one compatible single maskless anisotropic etching step. No additional material is needed to enhance infrared absorption since the passivation layer, as provided by the CMOS process, is sufficient for certain spectral bands. The responsivities are between 12 and 28

  16. CMOS Microsystems for Phase Fluorometric Biochemical Monitoring

    Microsoft Academic Search

    Alexander N. Cartwright; Vamsy P. Chodavarapu; Sung Jin Kim; Rachel M. Bukowski; Albert H. Titus; Frank V. Bright

    2007-01-01

    This article will present a review of our recent work on the development of Complementary Metal-Oxide Semiconductor (CMOS) detection and signal processing interfaces for fluorescence based biochemical sensors as well as the development of a new sensor. We will discuss a number of microsystems that integrate CMOS Application Specific Integrated Circuits (ASICs) with nanoporous sensor materials. Specifically, sol-gel derived xerogel

  17. Output transition time modeling of CMOS structures

    Microsoft Academic Search

    Philippe Maurine; Mustapha Rezzoug; Daniel Auvergne

    2001-01-01

    Non zero signal rise and fall times contribute significantly to CMOS gate performances such as propagation delay or short circuit power dissipation. We present a closed form expression to model output rise and fall times in deep submicron CMOS structures. The model is first developed for inverters considering fast and slow input ramp conditions. It is then extended to gates

  18. Optimum design of CMOS APS imagers

    Microsoft Academic Search

    Victor A. Shilin; Pavel A. Skrylev; Alexander L. Stempkovsky

    2003-01-01

    The main problem for CMOS active pixel sensors (APS) design is its fill factor and photosensitivity improvement. Using developed CMOS APS models we have solved this problem as mathematical optimization task. The fill factor is the aim function. The limits are: time delays, signal-to-noise ratio, horizontal and vertical MTFs, pixel sizes, and project rules. The simulation results for APS based

  19. JPL CMOS Active Pixel Sensor Technology

    NASA Technical Reports Server (NTRS)

    Fossum, E. R.

    1995-01-01

    This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

  20. A CMOS signed multiplier using wave pipelining

    Microsoft Academic Search

    V. D. Nguyen; W. Liu; C. T. Gray; R. K. Cavin

    1993-01-01

    The authors present a high-performance 8 × 8 CMOS signed multiplier using the wave pipelining technique. The multiplier architecture is based on the modified Booth algorithm and Wallace-Tree techniques. At the transistor level, a biased CMOS gate is used to balance the path delays; it provides a means of postprocess tuning, even though it has a disadvantage in power consumption.

  1. A CMOS-compatible 2-D vertical Hall magnetic-field sensor using active carrier confinement and post-process micromachining

    Microsoft Academic Search

    M Paranjape; L. M Landsberger; Mojtaba Kahrizi

    1996-01-01

    This work presents a CMOS-based magnetic-field sensor for the detection of magnetic-field vector components that occur parallel to the chip surface. The device employs two vertical Hall plate structures embedded in the substrate orthogonal to each other. The sensor is fabricated using a standard 3 ?m CMOS process provided by a commercial integrated circuit (IC) manufacturer, and a maskless post-process

  2. Maintaining the benefits of CMOS scaling when scaling bogs down

    Microsoft Academic Search

    Edward J. Nowak

    2002-01-01

    A survey of industry trends from the last two decades of scaling for CMOS logic is examined in an attempt to extrapolate practical directions for CMOS technology as lithography progresses toward the point at which CMOS is limited by the size of the silicon atom itself. Some possible directions for various specialized applications in CMOS logic are explored, and it

  3. NanoNano--CMOS MixedCMOS Mixed--Signal CircuitSignal CircuitNanoNano CMOS MixedCMOS Mixed Signal CircuitSignal Circuit MetamodelingMetamodeling TechniquesTechniques

    E-print Network

    Mohanty, Saraju P.

    NanoNano--CMOS MixedCMOS Mixed--Signal CircuitSignal CircuitNanoNano CMOS MixedCMOS Mixed Signal NanoSystem Design Laboratory (NSDL, http://nsdl.cse.unt.edu), University of North Texas Denton TX 76203 This paper targets sampling techniques which are technology independent and the amount that is needed

  4. Dark Current Characterization of the CMOS APS Imagers with Test Patterns Fabricated Using a 0.18 CMOS Technology

    E-print Network

    Lee, Jong Duk

    #12;Dark Current Characterization of the CMOS APS Imagers with Test Patterns Fabricated Using a 0 been investigated in the CMOS APS with test patterns fabricated with the 0.18 CMOS technology. We sensors (APS), fabricated using a standard CMOS process, have advantages of low power consumption, low

  5. CMOS foveal image sensor chip

    NASA Technical Reports Server (NTRS)

    Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

    2002-01-01

    A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

  6. Nanosecond monolithic CMOS readout cell

    DOEpatents

    Souchkov, Vitali V.

    2004-08-24

    A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

  7. 0.15-?m RF CMOS technology compatible with logic CMOS for low-voltage operation

    Microsoft Academic Search

    Masanobu Saito; Mizuki Ono; Ryuichi Fujimoto; Hiroshi Tanimoto; Nobuyuki Ito; Takashi Yoshitomi; Tatsuya Ohguro; Hisayo Sasaki Momose; Hiroshi Iwai

    1998-01-01

    Radio Frequency (RF) CMOS is expected to replace bipolar and GaAs MESFETs in RF front-end ICs for mobile telecommunications devices in the near future. In order for the RF CMOS to be popularly used in this application, compatibility of its process for high-speed logic CMOS and low supply voltage operation are important for low fabrication cost and low power consumption.

  8. Bridging faults in BiCMOS circuits

    NASA Technical Reports Server (NTRS)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1993-01-01

    Combining the advantages of CMOS and bipolar, BiCMOS is emerging as a major technology for many high performance digital and mixed signal applications. Recent investigations revealed that bridging faults can be a major failure mode in IC's. Effects of bridging faults in BiCMOS circuits are presented. Bridging faults between logical units without feedback and logical units with feedback are considered. Several bridging faults can be detected by monitoring the power supply current (I(sub DDQ) monitoring). Effects of bridging faults and bridging resistance on output logic levels were examined along with their effects on noise immunity.

  9. Chaotic UWB transceiver with tunable chaotic signal generation in CMOS 0.18um technology

    Microsoft Academic Search

    Sang-Min Han; Oleg Popov; Yun Seong Eo

    2007-01-01

    The chaotic UWB RF transceiver system is designed in CMOS 0.18 mum technology with flexible chaotic signal generation. Although the chaotic UWB technology is expected as a promising solution for near-range connectivity services, it has a limitation for commercial applications due to a fixed-band chaotic signal generator. In this paper, the noble flexible chaotic signal generator with adjustable frequency range

  10. Chaotic UWB transceiver with tunable chaotic signal generation in CMOS 0.18um technology

    Microsoft Academic Search

    Sang-Min Han; Oleg Popov; Yun Seong Eo

    2007-01-01

    The chaotic UWB RF transceiver system is designed in CMOS 0.18 m technology with flexible chaotic signal generation. Although the chaotic UWB technology is expected as a promising solution for near-range connectivity services, it has a limitation for commercial applications due to a fixed-band chaotic signal generator. In this paper, the noble flexible chaotic signal generator with adjustable frequency range

  11. Converting a bulk radiation-hardened BiCMOS technology into a dielectrically-isolated process

    Microsoft Academic Search

    M. Delaus; D. Emily; B. Mappes; R. Pease

    1993-01-01

    A radiation-hardened dielectrically isolated BiCMOS process has been developed by retrofitting dielectric isolation to an existing radiation-hardened JI (junction-isolated) process. The process is fabricated on a bonded-wafer silicon-on-insulator (SOI) substrate and employs deep trenches for lateral device isolation. The isolation technique employed is similar to that used on advanced commercial complementary-bipolar processes. Trench\\/substrate induced defects are sensitive to the device

  12. Fully-integrated oscillator in CMOS technology

    Microsoft Academic Search

    Gheorghe Pristavu; Anca-Gabriela Vasilica; Mihai Apostolescu; Gheorghe Brezeanu

    2010-01-01

    This paper describes the architecture of a fully integrated oscillator in CMOS technology, emphasizing the need for a simple design in order to achieve desired performances. The effect of parasitic transitions is investigated and eliminated.

  13. A CMOS-compatible compact display

    E-print Network

    Chen, Andrew R. (Andrew Raymond)

    2005-01-01

    Portable information devices demand displays with high resolution and high image quality that are increasingly compact and energy-efficient. Microdisplays consisting of a silicon CMOS backplane integrated with light ...

  14. A CMOS Smart Temperature and Humidity Sensor with Combined Readout

    PubMed Central

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-01-01

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 ?m CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 ?A. PMID:25230305

  15. Efficient design of CMOS TSC checkers

    Microsoft Academic Search

    SHAMANNA MANJUNATH; DAMU RADHAKRISHNAN

    1991-01-01

    The design of an efficient, robustly testable CMOS totally self-checking (TSC) checker for k-out-of-2k codes is treated. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers especially under the stuck-open fault model, owing to timing skews and arbitrary delays in the circuit. A new

  16. A 450 MHz CMOS RF power detector

    Microsoft Academic Search

    Stacy Ho

    2001-01-01

    An RF power detector based on a CMOS logarithmic\\/limiting amplifier achieves 50 dB dynamic range at 450 MHz. The logarithmic accuracy is +\\/- 1dB over the temperature range 0 to 85 degC. The chip is fabricated in 0.35 um double-poly triple-metal CMOS and consumes 10 mA with a 3 V supply

  17. CMOS technology using SEG isolation technique

    Microsoft Academic Search

    N. Endo; N. Kasai; A. Ishitani; Y. Kurogi

    1983-01-01

    An advanced bulk CMOS process has been developed using SEG (Selective Epitaxial Growth) isolation technique and high impurity concentration substrate, in order to suppress latch-up phenomenon. CMOS devices are fabricated on epitiaxial layer, which is selectively grown over p-type silicon substrate surrounded by a 2 µm thick SiO2insulator, using a reduced pressure SiH2Cl2-H2-HCl system. P-channel devices are formed in an

  18. Post-CMOS integration of germanium microstructures

    Microsoft Academic Search

    A. E. Franke; D. Bilic; D. T. Chang; P. T. Jones; T.-J. King; R. T. Howe; G. C. Johnson

    1999-01-01

    Polycrystalline germanium (poly-Ge) microstructures have been fabricated on standard CMOS wafers. Conventional low pressure chemical vapor deposition (LPCVD) and rapid thermal annealing (RTA) processes were used to achieve low-resistivity (2.3 m?-cm) tensile poly-Ge structural films, with a thermal budget which is compatible with Al (2% Si) metallization. The CMOS circuitry was passivated with low-temperature oxide and amorphous Si; the latter

  19. CMOS Integrated Nanophotonics for Future Computing Systems

    NASA Astrophysics Data System (ADS)

    Vlasov, Yurii A.

    2011-10-01

    CMOS Integrated Nanophotonics allows ultra-dense monolithic single-chip integration of optical and electrical functions. This technology can enable future Exaflops supercomputers by connecting racks, modules, and chips together with ultra-low power massively parallel optical interconnects. I will describe the progress this field witnessed during last several years starting from explorations of fundamental optical phenomena at the nanoscale through development of advanced nanophotonics devices to demonstration of advanced optoelectronic systems integrated into a single CMOS die.

  20. High speed submicron BiCMOS memory

    Microsoft Academic Search

    Masahide Takada; Kazuyuki Nakamura; Tohru Yamazaki

    1995-01-01

    This paper reviews device and circuit technologies for submicron BiCMOS memories, especially for high speed and large capacity SRAM's with 0.8 ?m, 0.55 ?m and 0.4 ?m design rules. First, poly-silicon emitter structure and triple-well structure are described as key submicron BiCMOS device technologies for achieving high transistor performance and minimized process complexity, as well as high reliability. Next, submicron

  1. CMOS imager technology shrinks and image performance

    Microsoft Academic Search

    H. Rhodes; G. Agranov; C. Hong; U. Boettiger; R. Mauritzson; J. Ladd; I. Karasev; J. McKee; E. Jenkins; W. Quinlin; I. Patrick; J. Li; X. Fan; R. Panicacci; S. Smith; C. Mouli; J. Bruce

    2004-01-01

    In this paper, we present a performance summary of CMOS imager pixels from 5.2 ?m to 4.2 ?m using 0.18 ?m imager design rules, then to 3.2 ?m using 0.15 ?m imager design rules. These pixels support 1.3-megapixel, 2.0-megapixel, and 3.1-megapixel CMOS image sensors for digital still cameral (DSC) applications at 3.3 V, respectively. The 4TC pixels are all based

  2. CMOS scaling into the nanometer regime

    Microsoft Academic Search

    Yuan Taur; DOUGLAS A. BUCHANAN; Wei Chen; DAVID J. FRANK; KHALID E. ISMAIL; Shih-Hsien Lo; G. A. Sai-Halasz; R. G. Viswanathan; H.-J. C. Wann; S. J. Wind; Hon-Sum Wong

    1997-01-01

    Starting with a brief review on 0.1-?m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect

  3. Design and defect tolerance beyond CMOS

    Microsoft Academic Search

    Xiaobo Sharon Hu; Alexander Khitun; Konstantin K. Likharev; Michael T. Niemier; Mingqiang Bao; Kang L Wang

    2008-01-01

    ABSTRACT It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advance- ment of CMOS-based VLSI circuits and systems. Regardless of the models, devices and technologies, any enhancement\\/replacement to CMOS must show,significant gains in at least one of the key met- rics (including speed, power and cost) for at least a

  4. Flexible packaging and integration of CMOS IC with elastomeric microfluidics

    NASA Astrophysics Data System (ADS)

    Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

    2013-05-01

    We have demonstrated flexible packaging and integration of CMOS IC chips with PDMS microfluidics. Microfluidic channels are used to deliver both liquid samples and liquid metals to the CMOS die. The liquid metals are used to realize electrical interconnects to the CMOS chip. As a demonstration we integrated a CMOS magnetic sensor die and matched PDMS microfluidic channels in a flexible package. The packaged system is fully functional under 3cm bending radius. The flexible integration of CMOS ICs with microfluidics enables previously unavailable flexible CMOS electronic systems with fluidic manipulation capabilities, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing.

  5. Delay models for timing simulation of CMOS\\/BiCMOS\\/BiNMOS mixed digital circuits

    Microsoft Academic Search

    S. Embabi; R. Damodaran

    1993-01-01

    The authors report on delay models for three basic structures, CMOS, BiCMOS and BiNMOS inverters. The models account for input slope. They also account for the various second order effects such as short channel effects in MOS transistors, high current effects in BJTs, and the device parasitics of MOS and BJT transistors. The error between the delay models and SPICE

  6. CMOS APS photoresponse and crosstalk optimization analysis for scalable CMOS technologies

    Microsoft Academic Search

    I. Shcherback; O. Yadid-Pecht

    2004-01-01

    This work presents an improved semi-analytical model developed for photoresponse estimation of a photodiode based CMOS active pixel sensor (APS). We show its use for maximum pixel photosignal prediction and CMOS APS crosstalk (CTK) optimization. Our model reveals the photosignal and the CTK dependence on the pixel geometrical shape and the pixel arrangement within the array. It brings out clearly

  7. Sub-threshold Circuit Design with Shrinking CMOS Devices

    E-print Network

    Calhoun, Benton H.

    Sub-threshold Circuit Design with Shrinking CMOS Devices Benton H. Calhoun, Sudhanshu Khanna, Randy, and these challenges increase as CMOS devices continue shrinking. This paper examines how sub-VT circuits scale

  8. Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

    PubMed

    Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

    2011-01-01

    The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

  9. A CMOS Magnetic Sensor Chip for Biomedical Applications

    E-print Network

    Liu, PENG

    2012-01-01

    CMOS bead relaxation detector significantly reduces the powerpower saving 5.6 Chip Implementation The microbead detector is implemented in 0.18 µm CMOS.detectors with all building blocks implemented in CMOS process are compact, low-power and

  10. Low power, CMOS digital autocorrelator spectrometer for spaceborne applications

    NASA Technical Reports Server (NTRS)

    Chandra, Kumar; Wilson, William J.

    1992-01-01

    A 128-channel digital autocorrelator spectrometer using four 32 channel low power CMOS correlator chips was built and tested. The CMOS correlator chip uses a 2-bit multiplication algorithm and a full-custom CMOS VLSI design to achieve low DC power consumption. The digital autocorrelator spectrometer has a 20 MHz band width, and the total DC power requirement is 6 Watts.

  11. Energy Effective 3D Stacked Hybrid NEMFET-CMOS Caches

    E-print Network

    Kuzmanov, Georgi

    -HdpMC) that combines the appealing ultra-low leakage SCCF NEMFET inverter with the versatility of CMOS technology. WeEnergy Effective 3D Stacked Hybrid NEMFET-CMOS Caches Mihai Lefter, Marius Enachescu, George Razvan-stacked hybrid memories as alternative to traditional CMOS SRAMs in L1 and L2 cache implementations and analyse

  12. 1 V full swing bootstrapped CMOS inverter circuit

    Microsoft Academic Search

    Kobchai Dejhan; Paiboon Tooprakai; Somsak Mitatha; Fusak Cheevasuvit; C. Soonyeekan

    2002-01-01

    This paper proposes a low voltage and full swing bootstrapped CMOS inverter circuit, designed by using the output drive CMOS transistors same as the conventional CMOS inverter in both pull up and pull down section. In pull up section, the overdrive at gate of pull up section is used by bootstrapped scheme. The circuit has the high speed full swing

  13. CMOS logic gates Where circuit delays come from

    E-print Network

    Chamberlain, Roger

    times of a CMOS inverter. Which has the largest overall propagation delay, tPD, a NAND gate, or a NOR in complementary arrangements inverter NAND A B (AB)' B A NOR (A+B)' NAND3 Circuit Delays in CMOS Circuits1 CMOS logic gates Where circuit delays come from Implementation of latches and flip flops How

  14. LOW VOLTAGE ANALOG CIRCUITS USING STANDARD CMOS TECHNOLOGY

    E-print Network

    Rincon-Mora, Gabriel A.

    LOW VOLTAGE ANALOG CIRCUITS USING STANDARD CMOS TECHNOLOGY Phillip E. Allen, Benjamin J. Blalock, and Gabriel A. Rincon School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta supply voltages in CMOS integrated circuits. As the channel lengths of CMOS technology decrease

  15. Study of CMOS APS Responsivity Enhancement: Ring-Shaped Photodiode

    E-print Network

    Study of CMOS APS Responsivity Enhancement: Ring-Shaped Photodiode Tatiana Danov, Igor Shcherback the possibilities of CMOS APS spectral response improvement are discussed. Thorough submicron scanning results sensitivity. Index Terms - APS (Active Pixel Sensor), CMOS image sensor, minority carriers, diffusion

  16. Clustered Pixels for CMOS Image Sensors Zhiqiong Yu

    E-print Network

    Hornsey, Richard

    The active pixel sensor (APS) is a pixel architecture commonly used in high quality CMOS image sensors. This thesis presents clustered pixels for CMOS APS. Clustered pixels with a unity gain amplifier (UGA..........................................................................1 1.1.2 Advantages of CMOS APS

  17. Region-of-interest cone beam computed tomography (ROI CBCT) with a high resolution CMOS detector

    NASA Astrophysics Data System (ADS)

    Jain, A.; Takemoto, H.; Silver, M. D.; Nagesh, S. V. S.; Ionita, C. N.; Bednarek, D. R.; Rudin, S.

    2015-03-01

    Cone beam computed tomography (CBCT) systems with rotational gantries that have standard flat panel detectors (FPD) are widely used for the 3D rendering of vascular structures using Feldkamp cone beam reconstruction algorithms. One of the inherent limitations of these systems is limited resolution (<3 lp/mm). There are systems available with higher resolution but their small FOV limits them to small animal imaging only. In this work, we report on region-of-interest (ROI) CBCT with a high resolution CMOS detector (75 ?m pixels, 600 ?m HR-CsI) mounted with motorized detector changer on a commercial FPD-based C-arm angiography gantry (194 ?m pixels, 600 ?m HL-CsI). A cylindrical CT phantom and neuro stents were imaged with both detectors. For each detector a total of 209 images were acquired in a rotational protocol. The technique parameters chosen for the FPD by the imaging system were used for the CMOS detector. The anti-scatter grid was removed and the incident scatter was kept the same for both detectors with identical collimator settings. The FPD images were reconstructed for the 10 cm x10 cm FOV and the CMOS images were reconstructed for a 3.84 cm x 3.84 cm FOV. Although the reconstructed images from the CMOS detector demonstrated comparable contrast to the FPD images, the reconstructed 3D images of the neuro stent clearly showed that the CMOS detector improved delineation of smaller objects such as the stent struts (~70 ?m) compared to the FPD. Further development and the potential for substantial clinical impact are suggested.

  18. Impact of Spacecraft Shielding on Direct Ionization Soft Error Rates for sub-130 nm Technologies

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan A.; Xapsos, Michael A.; Stauffer, Craig A.; Jordan, Michael M.; Sanders, Anthony B.; Ladbury, Raymond L.; Oldham, Timothy R.; Marshall, Paul W.; Heidel, David F.; Rodbell, Kenneth P.

    2010-01-01

    We use ray tracing software to model various levels of spacecraft shielding complexity and energy deposition pulse height analysis to study how it affects the direct ionization soft error rate of microelectronic components in space. The analysis incorporates the galactic cosmic ray background, trapped proton, and solar heavy ion environments as well as the October 1989 and July 2000 solar particle events.

  19. Photodissociation channels for N2O near 130 nm studied by product imaging

    E-print Network

    Houston, Paul L.

    2 NO + NO. 3 NO produced in 3 is the primary catalytic agent destroying the stratospheric ozone in the stratosphere by reaction with O 1 D produced either in 1 or from the dissociation of ozone N2O + O 1 D N2 + O2

  20. A reliable wire bonding on 130nm Cu\\/low-k device

    Microsoft Academic Search

    X. Gu; J. Antol; Y. F. Yao; K. H. Chua

    2003-01-01

    New circuits made of Cu traces and low-k dielectrics bring new challenges such as pad peeling during the wire bonding process. The wire bonding process characterization requires special attention compared to those conventionally made with Al and FSG. Failures encountered in the very first trial were found to be due to open circuits and serious pad peeling. Bond lift during

  1. Improved gate process control at the 130-nm node using spectroscopic-ellipsometry-based profile metrology

    Microsoft Academic Search

    J. Scott Hodges; Yu-Lun C. Lin; Dale R. Burrows; Ray H. Chiao; Robert M. Peters; Srinivasan Rangarajan; Kamal N. Bhatia; Suresh Lakkapragada

    2003-01-01

    The ability to control the cross-sectional profile of polysilicon gate structures on semiconductor devices is paramount to maximize product yield and transistor performance. Tighter control of gate profile parameters leads to a tighter distribution of transistor speeds, resulting in more optimized and consistent device performance. Furthermore, the ability to correlate physical in-line profile measurements taken at gate patterning process steps,

  2. RTD\\/CMOS nanoelectronic circuits: thin-film InP-based resonant tunneling diodes integrated with CMOS circuits

    Microsoft Academic Search

    J. I. Bergman; J. Chang; Y. Joo; B. Matinpour; J. Laskar; N. M. Jokerst; M. A. Brooke; B. Brar

    1999-01-01

    The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed

  3. A 0.18?m CMOS low-power radiation sensor for UWB wireless transmission

    NASA Astrophysics Data System (ADS)

    Crepaldi, M.; Demarchi, D.; Gabrielli, A.; Khan, A.; Pikhay, E.; Roizin, Y.; Villani, G.; Zhang, Z.

    2012-12-01

    The paper describes the design of a floating gate MOS sensor embedded in a readout CMOS element, used as a radiation monitor. A maximum sensitivity of 1 mV/rad is estimated within an absorbed dose range from 1 to 10 krad. The paper shows in particular the design of a microelectronic circuit that includes the floating gate sensor, an oscillator, a modulator, a transmitter and an integrated antenna. A prototype of the circuit has recently been simulated, fabricated and tested exploiting a commercial 180 nm, 4 metal CMOS technology. Some simulation results are presented along with a measurement of the readout circuit response to an input voltage swing. Given the small estimated area of the complete chip prototype, that is less than 1 mm2, the chip fits a large variety of applications, from spot radiation monitoring systems in medicine to punctual measurements or radiation level in High-Energy Physics experiments.

  4. Design of a total-dose radiation hardened monolithic CMOS DC-DC boost converter

    NASA Astrophysics Data System (ADS)

    Zhi, Liu; Hongying, Ning; Hongbo, Yu; Youbao, Liu

    2011-07-01

    This paper presents the design and implementation of a monolithic CMOS DC-DC boost converter that is hardened for total dose radiation. In order to improve its radiation tolerant abilities, circuit-level and device-level RHBD (radiation-hardening by design) techniques were employed. Adaptive slope compensation was used to improve the inherent instability. The H-gate MOS transistors, annular gate MOS transistors and guard rings were applied to reduce the impact of total ionizing dose. A boost converter was fabricated by a standard commercial 0.35 ?m CMOS process. The hardened design converter can work properly in a wide range of total dose radiation environments, with increasing total dose radiation. The efficiency is not as strongly affected by the total dose radiation and so does the leakage performance.

  5. Faint-meteor survey with a large-format CMOS sensor

    NASA Astrophysics Data System (ADS)

    Watanabe, J.; Enomoto, T.; Terai, T.; Kasuga, T.; Miyazaki, S.; Oota, K.; Muraoka, F.; Onishi, T.; Yamasaki, T.; Mito, H.; Aoki, T.; Soyano, T.; Tarusawa, K.; Matsunaga, N.; Sako, S.; Kobayashi, N.; Doi, M.

    2014-07-01

    For observing faint meteors, we need a large telescope or similar optics, which always give a restriction of the field of view. It is a kind of trade-off between the high sensitivity by using larger telescope and narrower field of view. Reconciling this contradiction, we need a large-format imaging detector together with fast readout for meteor observations. A high-sensitivity CMOS sensor of the large format was developed by Canon Inc. in 2010[1]. Its size is 202 mm×205 mm which makes it the largest one-chip CMOS sensor in the world, and approximately 40 times the size of Canon's largest commercial CMOS sensor as shown in the figure. The number of pixel is 1280×1248. Because the increased size of the new CMOS sensor allows more light to be gathered, it enables shooting in low-light environments. The sensor makes image capture possible in one-hundredth the amount of light required by a 35 mm full-frame CMOS sensor, facilitating the shooting of 60 frame-per-second video with a mere 0.3 lux of illumination. We tried to use this large-format CMOS sensor attached to the prime focus of the 1.05-m (F3.1) Schmidt telescope at the Kiso Observatory, University of Tokyo, for surveying faint meteors. The field of view is 3.3 by 3.3 degrees. Test observations including operation check of the system were carried out in January 2011, September 2011,and December 2012. Images were obtained at a time resolution of 60 frames per second. In this system, the limiting magnitude is estimated to be about 11-12. Because of the limitation of the data storage, full-power observations (14-bit data per 1/60 second) were performed for about one or two hours each night. During the first period, we can count a sporadic meteor every 5 seconds. This is about one order higher detection rate of the faint meteors compared with the previous work[2]. Assuming the height of faint meteors at 100 km, the derived flux of the sporadic meteors is about 5 × 10^{-4} km^{-2} sec^{-1}. The last run was performed during the active period of the Geminid meteor shower. We could take valuable data on December 12 and 13. The result will be given in this presentation, together with the future potential of the large format CMOS sensor.

  6. Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference

    PubMed Central

    Boufouss, El Hafed; Francis, Laurent A.; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

    2013-01-01

    This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of ?40–200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage VREF depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 ?W at room temperature and only 75 ?W at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of VREF and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2. PMID:24351635

  7. A low-leakage 2.5GHz skewed CMOS 32b adder for nanometer CMOS technologies

    Microsoft Academic Search

    Klaus von Arnim; Peter Seegebrecht; Roland Thewes; Christian Pacha

    2005-01-01

    A 32b parallel prefix adder demonstrates leakage-current-reduction capabilities of skewed CMOS logic. Sub-100nA leakage currents and single-cycle activation from standby mode is achieved using multi-tox logic gates in 90nm CMOS technology. The data path contains improved sense amplifier-based flip-flops and skewed CMOS logic adapted latches.

  8. Computer Physics Communications 1 Optical Link ASICs for LHC Upgrades

    E-print Network

    Gan, K. K.

    frequency clock to serialize the data for transmission. These ASICs were designed using a 130 nm CMOS. The prototype ASIC were fabricated using a 130 nm CMOS process. The ASIC contains three main blocks [1]; a VCSEL suitable for SLHC ap

  9. HSST BiCMOS technology with 26 ps ECL and 45 ps 2 V CMOS inverter

    Microsoft Academic Search

    S. Konaka; T. Kobayashi; T. Matsuda; M. Ugajin; K. Imai; T. Sakai

    1990-01-01

    HSST\\/BiCMOS technology has been developed by merging a novel 0.3 ?m self-aligned double-poly bipolar process called high-performance super self-aligned process technology (HSST) and the 0.22 ?m CMOS process. The HSST bipolar transistor size is 2.5 times smaller than that of 1 ?m SST-1B with an emitter 0.4 ?m wide. This results from a 0.3 ?m design rule, a collector polysilicon

  10. CMOS Avalanche Radio-over-Fiber wchoi@yonsei.ac.kr

    E-print Network

    Choi, Woo-Young

    #12;#12;CMOS Avalanche Radio-over-Fiber , wchoi@yonsei.ac.kr CMOS Avalanche Photo-detector for Radio-over-Fiber Systems Yonsei Univ. 0.13um CMOS avalanche (avalanche photo-detector, APDF) [1-2]. RoF CMOS . CMOS GaAs responsivity . APD avalanche

  11. A CMOS Integrated Power Detector for UWB

    Microsoft Academic Search

    Kenneth A. Townsend; James W. Haslett; John Nielsen

    2007-01-01

    An integrated CMOS RF power detector for wideband systems that does not require additional processing steps is presented. The received signal modulates the resistance of a MOSFET biased in triode to produce a DC current at the input of a transimpedance amplifier proportional to the received power. The resulting voltage is applied to an auto-zeroed logarithmic amplifier that provides offset

  12. ESD protection for wideband RF CMOS LNAs

    Microsoft Academic Search

    D. Linten; S. Thijs; G. Groeseneken

    2010-01-01

    Providing ESD protection for wideband RF CMOS LNAs is a challenging task: it requires both ESD and RF design skills in order to achieve high ESD robustness, while maintaining the overall RF performance. In this paper, an overview of the different wideband RF ESD protection strategies used in the literature is presented.

  13. Status and potential for CMOS terminal PAs

    Microsoft Academic Search

    Domine Leenaerts; Giuseppe Grillo

    2004-01-01

    In this overview, the status and potential for CMOS terminal RF power amplifiers (PAs) are discussed. The paper focuses on two application areas for RF PAs, namely wireless LAN\\/PAN applications, with output power levels up to 24 dBm, and cellular applications with power levels beyond 30 dBm.

  14. CMOS design challenges to power wall

    Microsoft Academic Search

    T. Kuroda

    2001-01-01

    CMOS power dissipation has been increasing due to the increase in power density. The power dissipation increased fourfold every three years until the early 1990's, due to a constant voltage scaling. Recently, a constant field scaling has been applied to reduce power dissipation, where the power density is increased proportional to the 0.7th power of scaling factor, resulting in power

  15. Dew-point relative humidity CMOS microsensors

    Microsoft Academic Search

    S. Baglio; S. Castorina; V. Sacco; N. Savalli; C. Tringali

    2004-01-01

    In this work we present the development of relative humidity (RH) microsensors in standard CMOS technology and bulk micromachining. Miniaturization of RH sensors allows reducing size, response times, power consumption and costs. Our device makes use of dew-point temperature detection approach, to achieve simple operation and high reproducibility. It is based on a suspended plate, anchored to the substrate by

  16. Battery-powered digital CMOS design

    Microsoft Academic Search

    Massoud Pedram; Qing Wu

    2002-01-01

    In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utilization factor) decreases as the average discharge current from the battery increases. The implication is that the battery life is a superlinear function of the average discharge current. Next we show that

  17. Highly sensitive Hall sensor in CMOS technology

    Microsoft Academic Search

    H Blanchard; F De Montmollin; J Hubin; R. S Popovic

    2000-01-01

    We present a highly sensitive Hall device fabricated in a standard CMOS technology and combined with integrated flux concentrators acting as magnetic amplifiers. The active area of the Hall plate is in a buried n-well with a shape optimized by removing the parts less sensitive to the magnetic field. The effect of the shape of the concentrators is studied. This

  18. CMOS ring oscillators with enhanced frequency operation

    Microsoft Academic Search

    A. El mourabit; Guo-Neng Lu; Ming Zhang; P. Pittet; Y. Birjali; F. Lahjoumri

    2010-01-01

    This paper presents a new technique to improve frequency performance of CMOS ring oscillator. It is based on the adding of a CR differentiators-based MOS transistor to boost switching speed of the oscillator delay cell. The method can be used for simple and differential oscillator and offers a simple way to implement frequency tuning without introduction of any additional phase

  19. CMOS current source based radiation sensors

    Microsoft Academic Search

    E. Garcia-Moreno; R. Picos; E. Isern; M. Roca; K. Suenaga

    2010-01-01

    This paper presents a comparison of two gamma radiation sensors intended to be embedded in CMOS integrated circuits. Both sensors are based on a current source, whose output depends upon the cumulated radiation dose, followed by a current-frequency converter. The two sensors differ in the sensing elements: one uses conventional transistors and the other a floating gate transistor. Results are

  20. Switch level optimization for CMOS circuits 

    E-print Network

    Chugh, Pankaj Pravinkumar

    1997-01-01

    In this report, 'Input vs Path Matrix 'Techique' and 'Node vs Input Matrix Technique' techniques for reducing transistor count in the pull-up and the pull-down array of CMOS circuits are proposed. Also, algorithms for optimization of both the pull...

  1. Power consumption estimation in CMOS VLSI chips

    Microsoft Academic Search

    Dake Liu; Christer Svensson

    1994-01-01

    Power consumption from logic circuits, interconnections, clock distribution, on chip memories, and off chip driving in CMOS VLSI is estimated. Estimation methods are demonstrated and verified. An estimate tool is created. Power consumption distribution between interconnections, clock distribution, logic gates, memories, and off chip driving are analyzed by examples. Comparisons are done between cell library, gate array, and full custom

  2. Noise in digital dynamic CMOS circuits

    Microsoft Academic Search

    Patrik Larsson; Christer Svensson

    1994-01-01

    Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits

  3. A comprehensive delay model for CMOS inverters

    Microsoft Academic Search

    Santanu Dutta; Shivaling S. Mahant Shetti; Stephen L. Lusky

    1995-01-01

    A method to accurately calculate the delay and the output transition-time of a CMOS inverter for any input ramp and output loading is considered. This paper is an extension of Sakurai's work (1990) on delay modeling of inverters for fast input ramps. We observed that two different mechanisms, that can be adequately modeled analytically, govern the delay and the output

  4. Delay degradation effect in submicronic CMOS inverters

    Microsoft Academic Search

    J. Juan-Chico; M. J. Bellido; A. J. Acosta; A. Barriga; M. Valencia

    1997-01-01

    This communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS inverter when consecutive input transition are close in time. Complete understanding of the effect is demonstrated, providing a quantifying model. Fully characterization as a function of design variables and external conditions is carried out, making the model suitable for using in library

  5. Timing and power model for CMOS inverters

    Microsoft Academic Search

    Richard Geißler; Hans-Jörg Pfleiderer

    2003-01-01

    Nowadays, the delay, the output transition time and the short circuit power consumption of CMOS gates depend on the load capacitance and the input transition time. In currently used technology libraries, table models with 25 or more samples are used for calculating by interpolation each of these three variables. Previous work deriving analytical models are based on neglecting the short

  6. Accurate timing model for the CMOS inverter

    Microsoft Academic Search

    L. Bisdounis; S. Nikolaidis; O. Koufopavlou; C. Goutis

    1996-01-01

    This paper introduces an accurate, analytical timing model for the CMOS inverter. Analytical output waveform expressions for all the inverter operation regions and input waveform slopes are derived, which take into account the complete expression of the short-circuit current and the gate-to-drain coupling capacitance

  7. Analytical transient response of CMOS inverters

    Microsoft Academic Search

    A. I. Kayssi; K. A. Sakallah; T. M. Burks

    1992-01-01

    A general formula relating the waveform at the output of a CMOS inverter to the waveform at its input is derived. The formula is applied to three cases: a step input, a ramp input, and an exponential input. A one-dimensional function dependence of the inverter propagation delay and output slew rate on circuit parameters is derived and an inverter macromodel

  8. Minimizing power consumption in digital CMOS circuits

    Microsoft Academic Search

    ANANTHA P. CHANDRAKASAN; ROBERT W. BRODERSEN

    1995-01-01

    An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology

  9. ELECTROSTATIC DISCHARGE (ESD) PROTECTION IN CMOS

    E-print Network

    Baker, R. Jacob

    ELECTROSTATIC DISCHARGE (ESD) PROTECTION IN CMOS A Thesis Presented in Partial Fulfillment ofthe for the degree ofMaster of Science with a major in Electrical Engineering and titled "ELECTROSTATIC DISCHARGE and evaluated. This thesis begins with a briefoverview of Electrostatic Discharge (ESD) and its reliability

  10. Analysis of temporal noise in CMOS APS

    Microsoft Academic Search

    Hui Tian; Boyd A. Fowler; Abbas El Gamal

    1999-01-01

    Temporal noise sets a fundamental limit on image sensor performance, especially under low illumination and in video applications. In a CCD image sensor, temporal noise is well studied and characterized. It is primarily due to the photodetector shot noise and the thermal and 1\\/f noise of the output charge to voltage amplifier. In a CMOS APS several addition sources contribute

  11. CMOS APS ASIC testing and evaluation

    Microsoft Academic Search

    S. Moussa; T. A. Elkhatib; H. Haddara; H. F. Ragaie

    2004-01-01

    An ASIC CMOS image Active Pixel Sensor (APS) with combined linear and logarithmic modes of operation is presented. The chip consists of a 64 x 64 pixel array, together with its digital control and timing circuits. Test structures including individual photodiodes and pixels are also integrated for characterization purpose. The chip features selectable linear and logarithmic modes of operation, digitally

  12. Optimal Layout of CMOS Functional Arrays

    Microsoft Academic Search

    Takao Uehara; William M. Van Cleemput

    1981-01-01

    Designers of MOS LSI circuits can take advantage of complex functional cells in order to achieve better performance. This paper discusses the implemention of a random logic function on an array of CMOS transistors. A graph-theoreti cal algorithm which minimizes the size of an array is presented. This method is useful for the design of cells used in conventional design

  13. CMOS ACTIVE PIXEL SENSOR NITIN N. VELUDANDI

    E-print Network

    Furth, Paul

    to regenerate the image incident on the sensor. A data acquisition system has been developed to test the sensorCMOS ACTIVE PIXEL SENSOR BY NITIN N. VELUDANDI Master's Technical Report Electrical Engineering New Sensor," a master technical report prepared by Nitin N Veludandi, in partial fulfillment

  14. Transistor matching in analog CMOS applications

    Microsoft Academic Search

    Marcel J. M. Pelgrom; Hans P. Tuinhout; Maarten Vertregt

    1998-01-01

    This paper gives an overview of MOSFET mismatch effects that form a performance\\/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit design is discussed. Mismatch effects gain importance as critical dimensions and CMOS power supply voltages decrease

  15. Nanoparticle SnO2 Gas Sensor with Circuit and Micro Heater on Chip Fabricated Using CMOS-MEMS Technique

    Microsoft Academic Search

    Ching-Liang Dai; Mao-Chen Liu

    2007-01-01

    The fabrication of a carbon monoxide (CO) micro gas sensor integrated with an inverting amplifier circuit and a micro heater on chip using the commercial 0.35mum complementary metal oxide semiconductor (CMOS) process and a post-process have been implemented. The gas sensor is composed of a polysilicon resistor and a CO gas sensing film. Tin dioxide prepared by the sol-gel method

  16. Design of an ultra low power CMOS pixel sensor for a future neutron personal dosimeter

    SciTech Connect

    Zhang, Y.; Hu-Guo, C.; Husson, D.; Hu, Y. [Institut Pluridisplinaire Hubert Curien IPHC, Univ. of Strasbourg, CNRS/IN2P3, 23 Rue du Loess, 67037 Strasbourg (France)

    2011-07-01

    Despite a continuously increasing demand, neutron electronic personal dosimeters (EPDs) are still far from being completely established because their development is a very difficult task. A low-noise, ultra low power consumption CMOS pixel sensor for a future neutron personal dosimeter has been implemented in a 0.35 {mu}m CMOS technology. The prototype is composed of a pixel array for detection of charged particles, and the readout electronics is integrated on the same substrate for signal processing. The excess electrons generated by an impinging particle are collected by the pixel array. The charge collection time and the efficiency are the crucial points of a CMOS detector. The 3-D device simulations using the commercially available Synopsys-SENTAURUS package address the detailed charge collection process. Within a time of 1.9 {mu}s, about 59% electrons created by the impact particle are collected in a cluster of 4 x 4 pixels with the pixel pitch of 80 {mu}m. A charge sensitive preamplifier (CSA) and a shaper are employed in the frond-end readout. The tests with electrical signals indicate that our prototype with a total active area of 2.56 x 2.56 mm{sup 2} performs an equivalent noise charge (ENC) of less than 400 e - and 314 {mu}W power consumption, leading to a promising prototype. (authors)

  17. Fast behavioral modeling of organic CMOS devices for digital and analog circuit applications

    NASA Astrophysics Data System (ADS)

    Jacob, Stephanie; Daami, Anis; Gwoziecki, Romain; Coppard, Romain; Hamani, Rachid; Guerin, Mathieu; Bergeret, Emmanuel; Pannier, Philippe

    2011-10-01

    Organic thin film technologies have opened a new range of interest into the optoelectronics industry. Nevertheless the physics and devices modeling still present a lack of accuracy. In order to provide designers with the latest performances of our organic CMOS technology, we have compared the performances of a behavioral model to the public a-Si TFT model in terms of accuracy on device modeling and basic circuit simulations. Fully printed organic CMOS devices and circuits have been processed and characterized in order to validate our device models. In particular, measurements have been carried out on several digital circuits like inverters and ring oscillators. Analog circuits such as current mirrors and differential pairs have also been measured. Simulations of these circuits have been performed using the device behavioral model and the a-Si TFT one under common EDA commercial tools. We show that both kinds of models enable to reproduce the different simple CMOS circuits performances in static as well as in dynamic modes which can open the way for designing a wide range and more complex digital and analog organic applications.

  18. Ultra-fast high-resolution hybrid and monolithic CMOS imagers in multi-frame radiography

    NASA Astrophysics Data System (ADS)

    Kwiatkowski, Kris; Douence, Vincent; Bai, Yibin; Nedrow, Paul; Mariam, Fesseha; Merrill, Frank; Morris, Christopher L.; Saunders, Andy

    2014-09-01

    A new burst-mode, 10-frame, hybrid Si-sensor/CMOS-ROIC FPA chip has been recently fabricated at Teledyne Imaging Sensors. The intended primary use of the sensor is in the multi-frame 800 MeV proton radiography at LANL. The basic part of the hybrid is a large (48×49 mm2) stitched CMOS chip of 1100×1100 pixel count, with a minimum shutter speed of 50 ns. The performance parameters of this chip are compared to the first generation 3-frame 0.5-Mpixel custom hybrid imager. The 3-frame cameras have been in continuous use for many years, in a variety of static and dynamic experiments at LANSCE. The cameras can operate with a per-frame adjustable integration time of ~ 120ns-to- 1s, and inter-frame time of 250ns to 2s. Given the 80 ms total readout time, the original and the new imagers can be externally synchronized to 0.1-to-5 Hz, 50-ns wide proton beam pulses, and record up to ~1000-frame radiographic movies typ. of 3-to-30 minute duration. The performance of the global electronic shutter is discussed and compared to that of a high-resolution commercial front-illuminated monolithic CMOS imager.

  19. Multiple-samples-method enabling high dynamic range imaging for high frame rate CMOS image sensor by FPGA and co-processor

    NASA Astrophysics Data System (ADS)

    Jacquot, Blake C.; Johnson-Williams, Nathan

    2014-09-01

    We present results from a prototype CMOS camera system implementing a multiple sampled pixel level algorithm ("Last Sample Before Saturation") to create High-Dynamic Range (HDR) images that approach the dynamic range of CCDs. The system is built around a commercial 1280 × 1024 CMOS image sensor with 10-bits per pixel and up to 500 Hz full frame rate with higher frame rates available through windowing. We analyze imagery data collected at room temperature for SNR versus photocurrent, among other figures of merit. Results conform to expectations of a model that uses only dark current, read noise, and photocurrent as input parameters.

  20. Real-time algorithm enabling high dynamic range imaging and high frame rate exploitation for custom CMOS image sensor system implemented by FPGA with co-processor

    NASA Astrophysics Data System (ADS)

    Jacquot, Blake C.; Johnson-Williams, Nathan

    2015-02-01

    We present results from a prototype CMOS camera system implementing a multiple sampled pixel level algorithm ("Last Sample Before Saturation") in real-time to create High-Dynamic Range (HDR) images that approach the dynamic range of CCDs. The system is built around a commercial 1280 × 1024 CMOS image sensor with 10-bits per pixel and up to 500 Hz full frame rate with higher frame rates available through windowing. We provide details of system architecture and present images collected with the system.

  1. A novel compact model for on-chip stacked transformers in RF-CMOS technology

    NASA Astrophysics Data System (ADS)

    Jun, Liu; Jincai, Wen; Qian, Zhao; Lingling, Sun

    2013-08-01

    A novel compact model for on-chip stacked transformers is presented. The proposed model topology gives a clear distinction to the eddy current, resistive and capacitive losses of the primary and secondary coils in the substrate. A method to analytically determine the non-ideal parasitics between the primary coil and substrate is provided. The model is further verified by the excellent match between the measured and simulated S -parameters on the extracted parameters for a 1 : 1 stacked transformer manufactured in a commercial RF-CMOS technology.

  2. Three-Dimensional Silicon–Germanium Nanostructures for CMOS-Compatible Light Emitters

    Microsoft Academic Search

    David J. Lockwood; L. Tsybeskov

    \\u000a The present status of light emitters based on SiGe nanostructures is reviewed. To be commercially valuable, these light emitters\\u000a should be efficient, fast, operational at room temperature, and, perhaps most importantly, compatible with the “main stream”\\u000a CMOS technology. Another important requirement is in the emission wavelength, which should match the optical waveguide low-loss\\u000a spectral region, i.e., 1.3–1.6 ?m. Among other approaches,

  3. PAM-4 Signaling over VCSELs with 0.13µm CMOS Chip Technology

    NASA Astrophysics Data System (ADS)

    Cunningham, J. E.; Beckman, D.; Zheng, Xuezhe; Huang, Dawei; Sze, T.; Krishnamoorthy, A. V.

    2006-12-01

    We present results for VCSEL based links operating PAM-4 signaling using a commercial 0.13µm CMOS technology. We perform a complete link analysis of the Bit Error Rate, Q factor, random and deterministic jitter by measuring waterfall curves versus margins in time and amplitude. We demonstrate that VCSEL based PAM 4 can match or even improve performance over binary signaling under conditions of a bandwidth limited, 100meter multi-mode optical link at 5Gbps. We present the first sensitivity measurements for optical PAM-4 and compare it with binary signaling. Measured benefits are reconciled with information theory predictions.

  4. ISSCC 2003 / SESSION 12 / CMOS IMAGERS, SENSORS AND DISPLAYS / PAPER 12.3 /4 inch 8.3M Pixel Digital Output CMOS APS

    E-print Network

    Fossum, Eric R.

    Pixel Digital Output CMOS APS for UDTV Application I. Takayanagi, M. Shirakawa1 , K. Mitani1 , MISSCC 2003 / SESSION 12 / CMOS IMAGERS, SENSORS AND DISPLAYS / PAPER 12.3 12.3 A 11 /4 inch 8.3M system. A newly developed digital-output CMOS image sensor fabricated in 0.25µm CMOS technology

  5. Single-pixel carrier-based approach for full-field laser interferometry using a CMOS-DSP camera

    NASA Astrophysics Data System (ADS)

    Aguanno, Mauro V.; Lakestani, Fereydoun; Whelan, Maurice P.; Connelly, Michael J.

    2004-02-01

    This investigation describes the implementation of a Single Pixel Carrier Based Demodulation (SPCBD) approach on a digital CMOS-DSP camera for full-field heterodyne interferometry. A full-field vibration measurement system is presented as an alternative to a classical scanning Laser Doppler Vibrometer (LDV). The Heterodyne set-up, CMOS-DSP camera and the signal demodulation techniques adopted are described. Characterisation tests that describe the basic performance of the CMOS-DSP camera, in terms of acquisition rates and time response are presented. A simple experiment was performed to demonstrate the novel laser vibrometry system that consisted of determining the displacement of a point on the surface of a vibrating mirror. The measured velocity and displacement data were compared to the output from a commercial LDV. The integration of a CMOS sensor, DSP and a laser-doppler interferometer has lead to the development of a fully digital "functional" machine vision system that provides a flexible, compact and inexpensive tool for automated high-precision optical measurements.

  6. An RF (R) MS Power Detector in Standard CMOS

    Microsoft Academic Search

    F. H. J. van der Aa

    2006-01-01

    This Master thesis describes the research towards the integration of RF power\\u000adetectors for 3G cellular phones and base stations in CMOS technology1. It\\u000ais a feasibility study with the emphasis on the identification of fundamen-\\u000atal limitations of CMOS (particularly CMOS9) and of a number of squaring\\u000acircuits for this specific application, rather than to meet the target specifica-

  7. New energy recovery CMOS XNOR\\/XOR gates

    Microsoft Academic Search

    Y. Xu; A. Srivastava

    2007-01-01

    In this paper, new energy recovery CMOS XNOR\\/XOR gates have been proposed. These circuits have been simulated using Cadence\\/Spectre along with three other XNOR\\/XOR gates. The results show that the new CMOS XNOR\\/XOR gates consume 30% less power than in the clocked adiabatic logic (CAL). Experimental results on new energy recovery CMOS XNOR\\/XOR gates fabricated in standard 0.5 mum n-well

  8. Retinomorphic system design in three dimensional SOI-CMOS

    Microsoft Academic Search

    Miriam Adlerstein Marwick; Andreas G. Andreou

    2006-01-01

    Three dimensional (3D) silicon on insulator (SOI)-CMOS technology offers opportunities for integration of truly complex neuromorphic systems that do not suffer from the limitations that hinder neuron-like local connectivity in 2D CMOS technologies. In this paper, we outline the rationale for morphing neural structures into 3D SOI-CMOS systems. We discuss design challenges for mixed signal neuromorphic circuits in single tier

  9. CMOS-MEMS membrane for audio-frequency acoustic actuation

    Microsoft Academic Search

    Kaigham J. Gabriel

    2001-01-01

    Using CMOS-MEMS micromachining techniques we have constructed a prototype earphone that is audible from 1 to 15 kHz. The fabrication of the acoustic membrane consists of only two steps in addition to the prior post-CMOS micromachining steps developed at CMU. The ability to build a membrane directly on a standard CMOS chip, integrating mechanical structures with signal processing electronics will

  10. Radiation characteristics of scintillator coupled CMOS APS for radiography conditions

    Microsoft Academic Search

    Kwang Hyun Kim; Soongpyung Kim; Dong-Won Kang; Dong-Kie Kim

    2006-01-01

    Under industrial radiography conditions, we analyzed short-term radiation characteristics of scintillator coupled CMOS APS (hereinafter SC CMOS APS). By means of experimentation, the contribution of the transmitted X-ray through the scintillator to the properties of the CMOS APS and the afterimage, generated in the acquired image even at low dose condition, were investigated. To see the transmitted X-ray effects on

  11. A New Photon Counting Detector: Intensified CMOS-APS

    Microsoft Academic Search

    Giovanni Bonanno; Massimiliano Belluso; Antonio Calģ; Alessandro Carbone; Rosario Cosentino; Angelo Modica; Salvo Scuderi; Cristina Timpanaro; Michela Uslenghi

    2004-01-01

    A new type of position sensor (CMOS-APS) used as readout system in MCP-based intensified photon counter is presented. Thanks to CMOS technology, the pixel addressing and the readout circuits as well as the analogue-to-digital converters are integrated into the chip. These unique characteristics make the CMOS-APS a very compact, low power consumption, photon counting system. The more classical Photon Counting

  12. Fundamental performance differences of CMOS and CCD imagers: part V

    NASA Astrophysics Data System (ADS)

    Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

    2013-02-01

    Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

  13. Cmos spdt switch for wlan applications

    NASA Astrophysics Data System (ADS)

    Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

    2015-04-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 ?m CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

  14. IR CMOS: infrared enhanced silicon imaging

    NASA Astrophysics Data System (ADS)

    Pralle, M. U.; Carey, J. E.; Haddad, Homayoon; Vineis, C.; Sickler, J.; Li, X.; Jiang, J.; Sahebi, F.; Palsule, C.; McKee, J.

    2013-06-01

    SiOnyx has developed visible and infrared CMOS image sensors leveraging a proprietary ultrafast laser semiconductor process technology. This technology demonstrates 10 fold improvements in infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Furthermore, these sensitivity enhancements are achieved on a focal plane with state of the art noise performance of 2 electrons/pixel. By capturing light in the visible regime as well as infrared light from the night glow, this sensor technology provides imaging in daytime through twilight and into nighttime conditions. The measured 10x quantum efficiency at the critical 1064 nm laser node enables see spot imaging capabilities in a variety of ambient conditions. The spectral sensitivity is from 400 to 1200 nm.

  15. Advances in fully CMOS integrated photonic devices

    NASA Astrophysics Data System (ADS)

    Michel, Jurgen; Liu, J. F.; Ahn, D. H.; Sparacin, D.; Sun, R.; Hong, C. Y.; Giziewicz, W. P.; Beals, M.; Kimerling, L. C.; Kopa, A.; Apsel, A. B.; Rasras, M. S.; Gill, D. M.; Patel, S. S.; Tu, K. Y.; Chen, Y. K.; White, A. E.; Pomerene, A.; Carothers, D.; Grove, M. J.

    2007-02-01

    The complete integration of photonic devices into a CMOS process flow will enable low cost photonic functionality within electronic circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, Cornell University, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application specific, electronic-photonic integrated circuit (AS-EPIC). The first phase of the program was dedicated to photonics device designs, CMOS process flow integration, and basic electronic functionality. We will present the latest results on the performance of waveguide integrated detectors, and tunable optical filters.

  16. Lateral IMPATT diodes in standard CMOS technology

    Microsoft Academic Search

    T. Al-Attar; M. D. Mulligan; T. H. Lee

    2004-01-01

    We investigate the use of a lateral IMPATT diode built in 0.25?m CMOS technology as a high frequency power source. These diodes are monolithically integrated in coplanar waveguides and characterized by S-parameter measurements from 40 MHz to 110 GHz. These measurements show excellent agreement with predictions of theoretical models. To our knowledge, this is the first such structure built in

  17. Space efficient CMOS nonlinear transmission lines

    Microsoft Academic Search

    Keith G. Lyon; Fan Yu; Edwin C. Kan

    2009-01-01

    Nonlinear transmission lines (NLTLs) are used in diverse applications such as edge-sharpening, pulse generation, and frequency conversion, however, length of a useful NLTL can require significant MMIC or RFIC real estate. We present an analytical model for the complex propagation constant of lossy, distributed NLTLs and fabricate several NLTLs in 0.25 mum CMOS for verification. Space-saving layout techniques such as

  18. Optimization of CMOS MEMS microwave power sensors

    Microsoft Academic Search

    Veljko MilanoviC; Matt Hopcroft; Christian A. Zincke; Michael Gaitan; Mona E. Zaghloul

    1999-01-01

    AbstractMicromachined power sensors with operation up to 50GHz were recently achieved in CMOS technology [1]. To improve their sensitivity and signal-to-noise ratio, while maintaining microwave performance, several design parameters must be considered, such as the number and placement of thermocouples. This paper presents experimental and analytical thermal characterization of the sensors, which provides insight into,the ,proper ,adjustment ,of the ,layout

  19. Metrology Of Silicide Contacts For Future CMOS

    Microsoft Academic Search

    Stefan Zollner; Richard B. Gregory; M. L. Kottke; Victor Vartanian; Xiang-Dong Wang; David Theodore; P. L. Fejes; J. R. Conner; Mark Raymond; Xiaoyan Zhu; Dean Denning; Scott Bolton; Kyuhwan Chang; Ross Noble; Mohamad Jahanbani; Marc Rossow; Darren Goedeke; Stan Filipiak; Ricardo Garcia; Dharmesh Jawarani; Bill Taylor; Bich-Yen Nguyen; P. E. Crabtree; Aaron Thean

    2007-01-01

    Silicide materials (NiSi, CoSi2, TiSi2, etc) are used to form low-resistance contacts between the back-end (W plugs and Cu interconnects) and front-end portions (silicon source, drain, and gate regions) of integrated CMOS circuits. At the 65 nm node, a transition from CoSi2 to NiSi was necessary because of the unique capability of NiSi to form narrow silicide nanowires on active

  20. Thermoelectric AC power sensor by CMOS technology

    Microsoft Academic Search

    Dominik Jaeggi; Henry Baltes; David Moser

    1992-01-01

    The authors report the development of a thermoelectric AC power sensor (thermoconverter) realized by industrial CMOS IC technology in combination with postprocessing micromachining. The sensor is based on a polysilicon heating resistor and a polysilicon\\/aluminum thermopile integrated on an oxide microbridge. The thermopile sensitivity is 9.9 mV\\/mW and the burn-out power of the sensor is 50 mW. The time constant

  1. Wide-IF-Band CMOS Mixer Design

    Microsoft Academic Search

    Pei-Yuan Chiang; Chao-Wei Su; Sz-Yun Luo; Robert Hu; Christina F. Jou

    2010-01-01

    A wide-IF-band transistor mixer has been designed using a 0.13-??m RF-CMOS process where its RF frequency is 8.7-17.4 GHz, local oscillator (LO) fixed at 17.4 GHz, and IF up to 8.7 GHz. Proper layout arrangement for the Marchand balun has been discussed and then implemented; the output amplitude and phase imbalance are less than 0.5 dB and 1 ?? measured

  2. RF-CMOS oscillators with switched tuning

    Microsoft Academic Search

    A. Kral; F. Behbahani; A. A. Abidi

    1998-01-01

    Fully integrated CMOS oscillators are of great interest for use in single-chip wireless transceivers. In most oscillator circuits reported to date that operate in the 0.9 to 2 GHz frequency range, an integrated spiral inductor sets the frequency. It is generally believed that an LC oscillator, even when it uses a low-Q inductor, displays a lower phase noise than a

  3. High-speed CMOS circuit technique

    Microsoft Academic Search

    JIREN YUAN; CHRISTER SVENSSON

    1989-01-01

    Ahtract -We have demonstrated that clock frequencies in ewes5 of 200 MHz are feasible in a 3-pm CMOS process. This is obtained by mean5 of clocking strategj, device sizing, and logic style selection. We use a precharge technique with a true single-phase clock, which remarkably increases the clock frequent) and reduces the skew problems, Device sizing with the help of

  4. LiB: a CMOS cell compiler

    Microsoft Academic Search

    Yung-ching Hsieh; Chi-yi Hwang; Youn-long Lin; Yu-chin Hsu

    1991-01-01

    An automatic layout generation system, called LiB, for the small-scale integrated (SSI) cells used in CMOS VLSI design, is presented. LiB takes a transistor-level circuit schematic in SPICE format and outputs a mask layout in CIF. The layout style is a modification of that proposed by T. Uehara, and W. M. van Cleemput (IEEE Trans. Comput., vol.C-30, no.5, p.305-12, 1981).

  5. Modeling and simulation of CMOS APS

    Microsoft Academic Search

    Beatriz Blanco-Filgueira; P. Lopez; Diego Cabello; J. Ernst; H. Neubauer; J. Hauer

    2009-01-01

    This work studies the importance of the peripheral collection in the overall photoresponse in deep sub-micron CMOS 3T active pixel sensors (APS), focusing on the contribution of the bottom surface of the depletion region. We analyze a semi-analytical expression, inspired by previous works, that models the photoresponse of a set of fabricated pixels with octagonal photodiodes that could be easily

  6. In-pixel autoexposure cmos aps

    Microsoft Academic Search

    Orly Yadid-Pecht; Alexander Belenky

    2003-01-01

    A CMOS active pixel sensor (APS) with in-pixel auto- exposure and a wide dynamic-range linear output is described. The chip features a unique architecture enabling a customized number of additional bits per pixel per readout, with minimal effect on the sensor spatial or temporal resolution. By utilizing multiple read- outs via real-time feedback, each pixel in the field of view

  7. Four-transistor static CMOS memory cells

    Microsoft Academic Search

    L. G. Walker; J. Manoliu; R. D. Rung

    1977-01-01

    A new approach toward size reduction of low-power static memory cells, based on ion-implanted leaky diodes in CMOS circuits, is described. The leaky diodes act as trickle chargers counteracting normal diode leakage currents and can be used in four different cells: a one-sided cell, a two-sided cell, and their complements. The reverse conductance of the implanted diodes must be greater

  8. Battery-powered digital CMOS design

    Microsoft Academic Search

    Massoud Pedram; Qing Wu

    1999-01-01

    In this paper we study tradeoffs between energy dissipation and delay in battery-powered digital CMOS designs. In contrast to previous work, we adopt an integrated model of the VLSI circuit and the battery sub-system that powers it. We show that accounting for the dependence of battery capacity on the average discharge current changes shape of the energy-delay trade-off curve and

  9. IDDQ testing in CMOS digital ASICs

    Microsoft Academic Search

    Roger Perry

    1992-01-01

    IDDQ testing with precision measurement unit (PMU) was used to eliminate early life failures caused by CMOS digital ASICs in our products. Failure analysis of the rejected parts found that bridging faults caused by particles were not detected in incoming tests created by automatic test generation (ATG) for stuck-at-faults (SAF). The nominal 99.6% SAF test coverage required to release a

  10. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design

    PubMed Central

    2013-01-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory. PMID:24180626

  11. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.

    PubMed

    Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-01-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory. PMID:24180626

  12. Space Commercialization

    NASA Technical Reports Server (NTRS)

    Martin, Gary L.

    2011-01-01

    A robust and competitive commercial space sector is vital to continued progress in space. The United States is committed to encouraging and facilitating the growth of a U.S. commercial space sector that supports U.S. needs, is globally competitive, and advances U.S. leadership in the generation of new markets and innovation-driven entrepreneurship. Energize competitive domestic industries to participate in global markets and advance the development of: satellite manufacturing; satellite-based services; space launch; terrestrial applications; and increased entrepreneurship. Purchase and use commercial space capabilities and services to the maximum practical extent Actively explore the use of inventive, nontraditional arrangements for acquiring commercial space goods and services to meet United States Government requirements, including measures such as public-private partnerships, . Refrain from conducting United States Government space activities that preclude, discourage, or compete with U.S. commercial space activities. Pursue potential opportunities for transferring routine, operational space functions to the commercial space sector where beneficial and cost-effective.

  13. Current-mode CMOS hybrid image sensor

    NASA Astrophysics Data System (ADS)

    Benyhesan, Mohammad Kassim

    Digital imaging is growing rapidly making Complimentary Metal-Oxide-Semi conductor (CMOS) image sensor-based cameras indispensable in many modern life devices like cell phones, surveillance devices, personal computers, and tablets. For various purposes wireless portable image systems are widely deployed in many indoor and outdoor places such as hospitals, urban areas, streets, highways, forests, mountains, and towers. However, the increased demand on high-resolution image sensors and improved processing features is expected to increase the power consumption of the CMOS sensor-based camera systems. Increased power consumption translates into a reduced battery life-time. The increased power consumption might not be a problem if there is access to a nearby charging station. On the other hand, the problem arises if the image sensor is located in widely spread areas, unfavorable to human intervention, and difficult to reach. Given the limitation of energy sources available for wireless CMOS image sensor, an energy harvesting technique presents a viable solution to extend the sensor life-time. Energy can be harvested from the sun light or the artificial light surrounding the sensor itself. In this thesis, we propose a current-mode CMOS hybrid image sensor capable of energy harvesting and image capture. The proposed sensor is based on a hybrid pixel that can be programmed to perform the task of an image sensor and the task of a solar cell to harvest energy. The basic idea is to design a pixel that can be configured to exploit its internal photodiode to perform two functions: image sensing and energy harvesting. As a proof of concept a 40 x 40 array of hybrid pixels has been designed and fabricated in a standard 0.5 microm CMOS process. Measurement results show that up to 39 microW of power can be harvested from the array under 130 Klux condition with an energy efficiency of 220 nJ /pixel /frame. The proposed image sensor is a current-mode image sensor which has several advantages over the voltage-mode. The most important advantages of using current-mode technique are: reduced power consumption of the chip, ease of arithmetic operations implementation, simplification of the circuit design and hence reduced layout complexity.

  14. Fabrication of Wireless Micro Pressure Sensor Using the CMOS Process

    PubMed Central

    Dai, Ching-Liang; Lu, Po-Wei; Wu, Chyan-Chyi; Chang, Chienliu

    2009-01-01

    In this study, we fabricated a wireless micro FET (field effect transistor) pressure sensor based on the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The wireless micro pressure sensor is composed of a FET pressure sensor, an oscillator, an amplifier and an antenna. The oscillator is adopted to generate an ac signal, and the amplifier is used to amplify the sensing signal of the pressure sensor. The antenna is utilized to transmit the output voltage of the pressure sensor to a receiver. The pressure sensor is constructed by 16 sensing cells in parallel. Each sensing cell contains an MOS (metal oxide semiconductor) and a suspended membrane, which the gate of the MOS is the suspended membrane. The post-process employs etchants to etch the sacrificial layers in the pressure sensor for releasing the suspended membranes, and a LPCVD (low pressure chemical vapor deposition) parylene is adopted to seal the etch holes in the pressure. Experimental results show that the pressure sensor has a sensitivity of 0.08 mV/kPa in the pressure range of 0–500 kPa and a wireless transmission distance of 10 cm. PMID:22291534

  15. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    NASA Technical Reports Server (NTRS)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  16. CMOS solid state photomultipliers for ultra-low light levels

    NASA Astrophysics Data System (ADS)

    Johnson, Erik B.; Stapels, Christopher J.; Chen, Xaio Jie; Whitney, Chad; Chapman, Eric C.; Alberghini, Guy; Rines, Rich; Augustine, Frank; Christian, James

    2011-05-01

    Detection of single photons is crucial for a number of applications. Geiger photodiodes (GPD) provide large gains with an insignificant amount of multiplication noise exclusively from the diode. When the GPD is operated above the reverse bias breakdown voltage, the diode can avalanche due to charged pairs generated from random noise (typically thermal) or incident photons. The GPD is a binary device, as only one photon is needed to trigger an avalanche, regardless of the number of incident photons. A solid-state photomultiplier (SSPM) is an array of GPDs, and the output of the SSPM is proportional to the incident light intensity, providing a replacement for photomultiplier tubes. We have developed CMOS SSPMs using a commercial fabrication process for a myriad of applications. We present results on the operation of these devices for low intensity light pulses. The data analysis provides a measured of the junction capacitance (~150 fF), which affects the rise time (~2 ns), the fall time (~32 ns), and gain (>106). Multipliers for the cross talk and after pulsing are given, and a consistent picture within the theory of operation of the expected dark current and photodetection efficiency is demonstrate. Enhancement of the detection efficiency with respect to the quantum efficiency at unity gain for shallow UV photons is measured, indicating an effect due to fringe fields within the diode structure. The signal and noise terms have been deconvolved from each other, providing the fundamental model for characterizing the behavior at low-light intensities.

  17. Solar XUV Imaging and Non-dispersive Spectroscopy for Solar-C Enabled by Scientific CMOS APS Arrays

    NASA Astrophysics Data System (ADS)

    Stern, Robert A.; Lemen, J. R.; Shing, L.; Janesick, J.; Tower, J.

    2009-05-01

    Monolithic CMOS Advanced Pixel Sensor (APS) arrays are showing great promise as eventual replacements for the current workhorse of solar physics focal planes, the scientific CCD. CMOS APS devices have individually addressable pixels, increased radiation tolerance compared to CCDs, and require lower clock voltages, and thus lower power. However, commercially available CMOS chips, while suitable for use with intensifiers or fluorescent coatings, are generally not optimized for direct detection of EUV and X-ray photons. A high performance scientific CMOS array designed for these wavelengths will have significant new capabilities compared to CCDs, including the ability to read out small regions of the solar disk at high (sub sec) cadence, count single X-ray photons with Fano-limited energy resolution, and even operate at room temperature with good noise performance. Such capabilities will be crucial for future solar X-ray and EUV missions such as Solar-C. Sarnoff Corporation has developed scientific grade, monolithic CMOS arrays for X-ray imaging and photon counting. One prototype device, the "minimal" array, has 8 um pixels, is 15 to 25 um thick, is fabricated on high-resistivity ( 10 to 20 kohm-cm) Si wafers, and can be back-illuminated. These characteristics yield high quantum efficiency and high spatial resolution with minimal charge sharing among pixels, making it ideal for the detection of keV X-rays. When used with digital correlated double sampling, the array has demonstrated noise performance as low as 2 e, allowing single photon counting of X-rays over a range of temperatures. We report test results for this device in X-rays, and discuss the implications for future solar space missions.

  18. Hinged Polysilicon Structures with Integrated CMOS Thin Film Transistors

    NASA Astrophysics Data System (ADS)

    Pister, Kristofer Stefan Josef

    Micro electromechanical systems (MEMS) have the potential to have a profound impact on both scientific research and commercial products. MEMS have proven to be a commercial success, finding application in such diverse environments as hospital operating rooms and automobile engines. One of the open research problems in MEMS is the fabrication of three dimensional structures using what is essentially a planar process. Several methods exist for making large vertical steps in silicon, but they offer only specific geometries and have limited resolution. The process described here is based on polysilicon surface micromachining, with the addition that micro hinges are built along with other structures. In this approach, polycrystalline silicon structural elements are fabricated in the plane of the wafer, and then rotated out of the plane of the wafer using hinged joints. Individual elements are then assembled together to form more complicated three dimensional structures with high detail in all dimensions. The assembly process has been automated to some degree by the inclusion of spring loaded locks which snap into place once a hinge has reached a critical angle. With these hinged structures and spring locks, thousands of structures can be rotated and locked into place simultaneously in the final step of fabrication. Several examples of hinged three dimensional structures are presented, including a hot wire anemometer, a frog-embryo dynamometer, and a parallel jaw gripper, all of which fit inside a 1 millimeter cube. In addition to the structural elements provided in the process, several electronic elements have been integrated as well. These elements include CMOS thin film transistors integrated directly in the polysilicon structural thin film, piezoresistive strain sensors for measuring force and deflection, and flexible micro ribbon cable which allows electrical wiring to be run between the substrate and the rotated structures.

  19. Direct Measures of Path Delays on Commercial FPGA Chips Mattia RuffoniDI

    E-print Network

    Bogliolo, Alessandro

    ) is twice the propagation delay of the loop. In principle, inserting a new element (such as a wire, a non-inverting including a structure under test (SUT) composed of a net and a non-inverting CMOS driver (representedDirect Measures of Path Delays on Commercial FPGA Chips Mattia RuffoniDI Alessandro BoglioloSTI DI

  20. A 77GHz Monolithic IMPATT Transmitter in Standard CMOS Technology

    E-print Network

    Lee, Thomas H.

    A 77GHz Monolithic IMPATT Transmitter in Standard CMOS Technology Talal Al-Attar, Arjang Hassibi consists of a lateral IMPATT diode and a microstrip patch antenna. The antenna impedance seen by the IMPATT the simulation results. Index Terms -- CMOS, IMPATT diode, microstrip patch antenna, stub, Sonnet, vector network

  1. Linear array of CMOS double pass metal micromirrors

    Microsoft Academic Search

    Johannes Buehler; Franz-Peter Steiner; Henry Baltes

    1996-01-01

    Low-cost linear arrays of deflectable micromirrors using a CMOS process to define both on-chip circuitry and the mirror structure are presented. The mirrors consist of the second CMOS metallization deposited in two successive passes in order to establish a thick metal layer for the stiff mirror plate as well as a thin one for the flexible hinges. The mirrors are

  2. CCD\\/CMOS hybrid FPA for low light level imaging

    Microsoft Academic Search

    Xinqiao Liu; Boyd A. Fowler; Steve K. Onishi; Paul Vu; David D. Wen; Hung Do; Stuart Horn

    2005-01-01

    We present a CCD \\/ CMOS hybrid focal plane array (FPA) for low light level imaging applications. The hybrid approach combines the best of CCD imaging characteristics (e.g. high quantum efficiency, low dark current, excellent uniformity, and low pixel cross talk) with the high speed, low power and ultra-low read noise of CMOS readout technology. The FPA is comprised of

  3. Transit-time limited response from low capacitance CMOS photodetectors

    E-print Network

    Miller, David A. B.

    ) the 425 nm pump pulse on the silicon photodetector raises the voltage on the modulator until sufficient maps the voltage rise at the CMOS photodetector with sub-picosecond resolution. The total signal swingTransit-time limited response from low capacitance CMOS photodetectors Aparna Bhatnagar, Salman

  4. PhD Dissertation Defense Presentation CMOS INSTRUMENTATION FOR

    E-print Network

    Micro-system for Real-Time Measurement of Human Safety," IEEE EMBC, 2012. [3] X. Liu, L. Li, B. Awate, RPhD Dissertation Defense Presentation CMOS INSTRUMENTATION FOR ELECTROCHEMICAL BIOSENSOR ARRAY 2219 Engineering Building #12;CMOS INSTRUMENTATION FOR ELECTROCHEMICAL BIOSENSOR ARRAY MICROSYSTEMS

  5. Integrated CMOS Wireless Power Transfer for Neural Implants

    E-print Network

    Gulak, P. Glenn

    for biomedical implants and neural activity monitoring/stimulation. In this system the circuits containedIntegrated CMOS Wireless Power Transfer for Neural Implants Meysam Zargham and P. Glenn Gulak the possibility of an integrated receiver coil on a CMOS substrate useful for neural implants. It is shown

  6. GaAs MQW modulators integrated with silicon CMOS

    Microsoft Academic Search

    K. W. Goossen; J. A. Walker; L. A. D'Asaro; S. P. Hui; B. Tseng; R. Leibenguth; D. Kossives; D. D. Bacon; D. Dahringer; L. M. F. Chirovsky; A. L. Lentine; D. A. B. Miller

    1995-01-01

    We demonstrate integration of GaAs-AlGaAs multiple quantum well modulators to silicon CMOS circuitry via flip-chip solder-bonding followed by substrate removal. We obtain 95% device yield for 32×32 arrays of devices with 15 micron solder pads. We show operation of a simple circuit composed of a modulator and a CMOS transistor

  7. SiGe BiCMOS technology for communication products

    Microsoft Academic Search

    Marco Racanelli; Paul Kempf

    2003-01-01

    SiGe BiCMOS technology is reviewed with focus on recent advances including the achievement of >200 GHz Ft and Fmax SiGe transistors, integration with generic 0.13 ?m CMOS, and the realization of low-cost nodes for the integration of wireless transceivers. Record-breaking wireless and wire-line circuit examples are also provided.

  8. Autonomous mobile mini-robot with embedded CMOS vision system

    Microsoft Academic Search

    J. Palacin; A. Sanuy; X. Clua; G. Chapinal; S. Bota; M. Moreno; A. Herms

    2002-01-01

    This paper presents a prototype of a mobile minirobot with an embedded vision system. The robot control is implemented in a low cost microcontroller and the vision system is based in a proprietary CMOS imaging array. The proposed vision sensor has enough flexibility to be incorporated directly to most microcontroller-based systems without any additional electronics. The CMOS camera sensor has

  9. CMOS technology characterization for analog and RF design

    Microsoft Academic Search

    Behzad Razavi

    1998-01-01

    Characterization of CMOS technologies for digital applications often proves inadequate for analog and RF design. This paper describes a set of characterization vehicles and tests that quantify the analog behavior of active and passive devices in CMOS processes, in particular, properties that are not represented accurately in SPICE models. Test structures and circuits are introduced for measuring speed, noise, linearity,

  10. Consistent Layout Techniques For Successful RF CMOS Design

    Microsoft Academic Search

    Troels Emil Kolding

    2000-01-01

    Scalable RF CMOS device models constitute an effective mean to increase design flexibility and to build highperformancecircuits. To operate at gigahertz frequencies, low-cost CMOS technology must operate at the peakof its performance and this may only be achieved with accurate device models. This paper discusses the problemsof obtaining scalable models for active devices and proposes layout confinements that are necessary

  11. Bridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess

    E-print Network

    Larrabee, Tracy

    Bridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess Tracy Larrabee \\Lambda shown that the vast majority of all local defects in MOS technologies cause changes in the circuit. We use the Carafe fault extractor to extract realistic bridge faults in CMOS circuits [10

  12. Minimum supply voltage for bulk Si CMOS GSI

    Microsoft Academic Search

    Azeez J. Bhavnagarwala; Blanca Austin; James D. Meindl

    1998-01-01

    Limits on energy dissipation are investigated for bulk Si CMOS circuits at each node of the 1997 National Technology Roadmap for Semiconductors (NTRS). Physical, continuous and smooth MOSFET Transregional drain current models that consider high-field effects in scaled devices, and permit trade-offs between saturation drive current and subthreshold leakage current are described and employed to model CMOS circuit performance and

  13. Analog CMOS high-frequency continuous wavelet transform circuit

    Microsoft Academic Search

    E. W. Justh; F. J. Kub

    1999-01-01

    A 16-channel analog CMOS high-frequency continuous wavelet transform circuit has been realized. The circuit performs a time-frequency decomposition of a high-frequency input signal. A 100 MHz operating frequency, 45 MHz bandwidth, and 40 mW\\/channel power dissipation have been achieved using a 0.5 ?m CMOS process

  14. Reliability Study of the 90 nm CMOS Inverter

    Microsoft Academic Search

    Dayanasari Abdul Hadi; Norhayati Soin; S. F. Wan Muhamad Hatta

    2011-01-01

    The effect of the negative bias temperature instability (NBTI) has been studied on the performance of the CMOS inverter using ELDO analog simulator. A simulation study had been conducted on a CMOS inverter using BSIM3V3 model and focused on the PMOS device of the inverter that was simulated with different elevated temperatures in 10 years' time. In this paper, the

  15. Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies

    Microsoft Academic Search

    Zhangcai Huang; Hong Yu; Atsushi Kurokawa; Yasuaki Inoue

    2007-01-01

    With the scaling of CMOS technology, the over- shooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer

  16. Timing and power models for CMOS repeaters driving resistive interconnect

    Microsoft Academic Search

    Victor Adler; Eby G. Friedman

    1996-01-01

    A delay and power model of a CMOS inverting repeater driving a resistive-capacitive load is presented. The model is derived from Sakurai's alpha-power law and exhibits good accuracy. The model can be used to design and analyze those CMOS inverters that drive a large RC load when considering both speed and power. Expressions are provided for estimating the propagation delay

  17. Reliability Study of the 90 nm CMOS Inverter

    Microsoft Academic Search

    Dayanasari Abdul Hadi; Norhayati Soin; S. F. Wan Muhamad Hatta

    2011-01-01

    The effect of the negative bias temperature instability (NBTI) has been studied on the performance of the CMOS inverter using ELDO analog simulator. A simulation study had been conducted on a CMOS inverter using BSIM3V3 model and focused on the PMOS device of the inverter that was simulated with different elevated temperatures in 10 years’ time. In this paper, the

  18. RF power potential of 45 nm CMOS technology

    E-print Network

    Putnam, Christopher

    This paper presents the first measurements of the RF power performance of 45 nm CMOS devices with varying device widths and layouts. We find that 45 nm CMOS can deliver a peak output power density of around 140 mW/mm with ...

  19. Generic linear RC delay modeling for digital CMOS circuits

    Microsoft Academic Search

    An-chang Deng; Yan-chyuan Shiau

    1990-01-01

    The linear RC delay modeling technique is used to model the timing delays in CMOS circuit empirically. The empirical model, a multidimensional function of various circuit and device parameters, is shown to be simplified to a two-dimensional model which estimates the delay of a CMOS subcircuit in terms of the generic RC delay ad the rise\\/fall time of the input

  20. Experimental Investigation of Microwave Vulnerabilities in CMOS Inverters

    E-print Network

    Anlage, Steven

    Experimental Investigation of Microwave Vulnerabilities in CMOS Inverters Agis A. Iliadis effects on single CMOS inverters, the fundamental building block of logic ICs, consisting of an NMOS and a PMOS transistor. The inverters were designed in our group and fabricated in the AMI-1.5µm MOSIS line

  1. Performance computation for precharacterized CMOS gates with RC loads

    Microsoft Academic Search

    Florentin Dartu; Noel Menezes; Lawrence T. Pileggi

    1996-01-01

    For efficiency, the performance of digital CMOS gates is often expressed in terms of empirical models. Both delay and short-circuit power dissipation are sometimes characterized as a function of load capacitance and input signal transition time. However, gate loads can no longer be modeled by purely capacitive loads for high performance CMOS due to the RC metal interconnect effects. This

  2. Quiescent power supply current measurement for CMOS IC defect detection

    Microsoft Academic Search

    CHARLES F. HAWKINS; JERRY M. SODEN; RONALD R. FRITZEMEIER; LUTHER K. HORNING

    1989-01-01

    Quiescent power supply current (IDDQ) measurement is a very effective technique for detecting in CMOS integrated circuits (ICs). This technique uniquely detects certain CMOS IC defects such as gate oxide shorts, defective p-n junctions, and parasitic transistor leakage. In addition, IDDQ monitoring will detect all stuck-at faults with the advantage of using a node toggling test set that has fewer

  3. INTEGRATED CMOS OPTICAL PHASE SENSOR VAMSY PONNAPUREDDY, B.Tech.

    E-print Network

    Furth, Paul

    INTEGRATED CMOS OPTICAL PHASE SENSOR BY VAMSY PONNAPUREDDY, B.Tech. A thesis submitted Engineering New Mexico State University Las Cruces, New Mexico February 2007 #12;"INTEGRATED CMOS OPTICAL, especially during the optical test setup, are greatly ap- preciated. I am thankful to Dr.Nancy Chanover

  4. Exact noise analysis of a CMOS BDJ APS

    Microsoft Academic Search

    Sylvain Feruglio; Victor Fouad Hanna; Georges Alquié; Gabriel Vasilescu

    2005-01-01

    At low illumination levels, the performance of image sensors is severely limited by their intrinsic electrical noise. In the buried double junction (BDJ) active pixel sensor (APS), as in any CMOS image sensor, noise is primarily due to the photodetector and to the in-pixel transistors. In this paper, we present an exact noise analysis of CMOS BDJ APS in charge

  5. CMOS APS crosstalk: modeling, technology and design trends

    Microsoft Academic Search

    Shcherback Igor; Belenky Alex; O. Yadid-Pecht

    2004-01-01

    In this work based on a unique sub-micron scanning system (S-cube system) measurements of the lateral photoresponse and crosstalk (CTK) in CMOS active pixel sensor (APS) have been investigated and an analytical model was developed for crosstalk estimation in photodiode based CMOS APS arrays. Based on handy process and design data only, our model estimates the CTK contribution to the

  6. Analysis of 1\\/f noise in CMOS APS

    Microsoft Academic Search

    Hui Tian; Abbas El Gamal

    2000-01-01

    As CMOS technology scales, the effect of 1\\/f noise on low frequency analog circuits such as CMOS image sensors becomes more pronounced, and therefore must be more accurately estimated. analysis of 1\\/f noise is typically performed in the frequency domain even though the process is nonstationary. To find out if the frequency domain analysis produces acceptable results, the paper introduces

  7. Bottom collection of photodiode-based CMOS APS

    Microsoft Academic Search

    B. Blanco-Filgueira; P. Lopez; D. Cabello; J. Ernst; H. Neubauer; J. Hauer

    2008-01-01

    The market for solid-state image sensors has been experiencing an explosive growth in recent years resulting in CMOS sensors rapidly becoming one of the emerging sectors with more projection potential in the semiconductors industry. A CMOS active pixel sensor (APS) with a reverse biased p-n junction photodiode constitutes the structure of more widespread use, and it has been made a

  8. A CMOS fault extractor for inductive fault analysis

    Microsoft Academic Search

    F. Joel Ferguson; John Paul Shen

    1988-01-01

    The inductive fault analysis (IFA) method is presented and a description is given of the CMOS fault extraction program FXT. The IFA philosophy is to consider the causes of faults (manufacturing defects) and then simulate these causes to find the faults that are likely to occur in a circuit. FXT automates IFA for a CMOS technology by generating a list

  9. Carafe: an inductive fault analysis tool for CMOS VLSI circuits

    Microsoft Academic Search

    Alvin Jee; F. Joel Ferguson

    1993-01-01

    Traditional fault models for testing CMOS VLSI circuits do not take into account the actual mechanisms that precipitate faults in CMOS circuits. As a result, tests based on traditional fault models may not detect all the faults that occur in the circuit. This paper discusses the Carafe software package which determines which faults are likely to occur in a circuit

  10. Carafe: An Inductive Fault Analysis Tool for CMOS VLSI Circuits

    Microsoft Academic Search

    Alvin Jee; F. Joel Ferguson Boar

    1991-01-01

    Traditional fault models for testing CMOS VLSIcircuits do not take into account the actual mechanismsthat precipitate faults in CMOS circuits. As aresult, tests based on traditional fault models may notdetect the actual faults in the circuit. This paper discussesthe Carafe software package which determineswhich faults are likely to occur in a circuit based onthe circuit's physical design, defect parameters, andfabrication

  11. Circuit technologies for BiCMOS VLSIs as computer elements

    Microsoft Academic Search

    H. Maejima; T. Bandoh; Y. Nishio; T. Fukushima; M. Odaka; A. Hotta

    1989-01-01

    System requirements for VLSI technologies are reviewed and circuit technologies for BiCMOS VLSIs as computer elements are described. The following topics are dealt with: circuits for logic gates-conventional circuits and feedback type circuits for finer process; circuits for macrocells-CMOS logic circuits with bipolar sense circuits; and circuits for application-specific memories-sense amplifiers with comparators

  12. Supply and threshold voltage scaling for low power CMOS

    Microsoft Academic Search

    Ricardo Gonzalez; Benjamin M. Gordon; Mark A. Horowitz

    1997-01-01

    This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially when the transistors are velocity saturated and the nodes have a high activity factor, In

  13. A CMOS capacitive pressure sensor chip for fingerprint detection

    Microsoft Academic Search

    Yung-Shih Hsiung; Michael S.-C. Lu

    2011-01-01

    Biometric techniques, such as fingerprint detection, can be applied to identify a specific user for security and safety reasons. We present a capacitive fingerprint sensor that can detect the difference of pressures induced by the ridges and valleys of a finger tip. Post-CMOS fabrication of the 8×32 sensor array is conducted based on wet etch of CMOS metal layers without

  14. Digital autoradiography using room temperature CCD and CMOS imaging technology

    Microsoft Academic Search

    Jorge Cabello; Alexis Bailey; Ian Kitchen; Mark Prydderch; Andy Clark; Renato Turchetta; Kevin Wells

    2007-01-01

    CCD (charged coupled device) and CMOS imaging technologies can be applied to thin tissue autoradiography as potential imaging alternatives to using conventional film. In this work, we compare two particular devices: a CCD operating in slow scan mode and a CMOS-based active pixel sensor, operating at near video rates. Both imaging sensors have been operated at room temperature using direct

  15. An Embedded DRAM for CMOS ASICs John Poulton

    E-print Network

    Poulton, John W.

    An Embedded DRAM for CMOS ASICs John Poulton Department of Computer Science University of North, will also require more memory than can easily be supported on logic-oriented ASIC processes. Most ASIC. This paper describes development of a DRAM, compatible with a standard CMOS ASIC process, that provides

  16. A fully integrated programmable dual-band RF filter based on electrically and mechanically coupled CMOS-MEMS resonators

    NASA Astrophysics Data System (ADS)

    Giner, J.; Uranga, A.; Muńóz-Gamarra, J. L.; Marigó, E.; Barniol, N.

    2012-05-01

    In this paper, a novel fully integrated CMOS-MEMS filter implemented on a commercial CMOS technology is presented. The combination of mechanical and electrical coupling is used to enhance the response of the band pass filter. In particular, a 20 dB shape factor as low as 2 and a 35 dB stopband rejection are achieved. Moreover, the topology of the device allows obtaining a dual-bandpass filter behavior, presenting a tunable bandwidth and a deep notch between bands. Results show a dual-band filter with a 22 dB inner stopband rejection, center frequencies at 27.5 and 27.8 MHz, respectively, and a 0.6% relative bandwidth.

  17. Design of high speed camera based on CMOS technology

    NASA Astrophysics Data System (ADS)

    Park, Sei-Hun; An, Jun-Sick; Oh, Tae-Seok; Kim, Il-Hwan

    2007-12-01

    The capacity of a high speed camera in taking high speed images has been evaluated using CMOS image sensors. There are 2 types of image sensors, namely, CCD and CMOS sensors. CMOS sensor consumes less power than CCD sensor and can take images more rapidly. High speed camera with built-in CMOS sensor is widely used in vehicle crash tests and airbag controls, golf training aids, and in bullet direction measurement in the military. The High Speed Camera System made in this study has the following components: CMOS image sensor that can take about 500 frames per second at a resolution of 1280*1024; FPGA and DDR2 memory that control the image sensor and save images; Camera Link Module that transmits saved data to PC; and RS-422 communication function that enables control of the camera from a PC.

  18. Fundamental performance differences between CMOS and CCD imagers, part IV

    NASA Astrophysics Data System (ADS)

    Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Grygon, Mark; Keller, Dave

    2010-07-01

    This paper is a continuation of past papers written on fundamental performance differences of scientific CMOS and CCD imagers. New characterization results presented below include: 1). a new 1536 × 1536 × 8?m 5TPPD pixel CMOS imager, 2). buried channel MOSFETs for random telegraph noise (RTN) and threshold reduction, 3) sub-electron noise pixels, 4) 'MIM pixel' for pixel sensitivity (V/e-) control, 5) '5TPPD RING pixel' for large pixel, high-speed charge transfer applications, 6) pixel-to-pixel blooming control, 7) buried channel photo gate pixels and CMOSCCDs, 8) substrate bias for deep depletion CMOS imagers, 9) CMOS dark spikes and dark current issues and 10) high energy radiation damage test data. Discussions are also given to a 1024 × 1024 × 16 um 5TPPD pixel imager currently in fabrication and new stitched CMOS imagers that are in the design phase including 4k × 4k × 10 ?m and 10k × 10k × 10 um imager formats.

  19. A 115mW CMOS GPS Receiver Derek K. Shaeffer

    E-print Network

    Lee, Thomas H.

    ;OUTLINE GPS Overview / Receiver Architecture Low-Noise Amplifiers ­ CMOS noise models. ­ Power Receiver Implementation Experimental Results Summary and Contributions #12;GPS OVERVIEW: WHY RF CMOS? CMOS be done competitively in CMOS, it will. #12;GPS OVERVIEW: THE SYSTEM 24 satellites in LEO, broadcasting

  20. Post-CMOS Parylene Packaging for On-chip Biosensor Arrays

    E-print Network

    Mason, Andrew

    Post-CMOS Parylene Packaging for On-chip Biosensor Arrays Lin Li Department of Electrical as an open challenge. This paper presents a robust and reliable packaging scheme for on-CMOS biosensors CMOS die. Photos of a packaged CMOS biosensor array chip and electrochemical measurements in potassium

  1. Heavy Ion Radiation Effects on CMOS Image Sensors Henok T. Mebrahtu

    E-print Network

    Hornsey, Richard

    . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 CMOS APS Basics . . . . . . . . . . . . . . . . . . . . . . . . 9 vii #12;2.1.2 CMOS APSHeavy Ion Radiation Effects on CMOS Image Sensors Henok T. Mebrahtu A thesis submitted for CMOS devices. Simulation work of the heavy ion damage on structure was conducted to predict

  2. Development of a RF Bipolar Transistor in a Standard 0.35m CMOS Technology

    E-print Network

    Ng, Wai Tung

    Development of a RF Bipolar Transistor in a Standard 0.35µm CMOS Technology I-Shan Michael Sun-0021, Japan ABSTRACT A RF Bipolar Transistor integrated to a standard 0.35µm CMOS process is presented compared to previously published BiCMOS technologies. Key Words 0.35µm CMOS Technology, RF Silicon Bipolar

  3. A CAD tool for the power estimation of CMOS, BiCMOS and BiNMOS gates 

    E-print Network

    Islam, Kazi Inamul

    1995-01-01

    This thesis describes a CAD tool for the power estimation of CMOS, BiCMOS and BiNMOS gates. Using analytical models for the transient behavior of the gates, accurate estimates of the power dissipated by each type of gate during a typical transition...

  4. A CAD tool for the power estimation of CMOS, BiCMOS and BiNMOS gates

    E-print Network

    Islam, Kazi Inamul

    1995-01-01

    This thesis describes a CAD tool for the power estimation of CMOS, BiCMOS and BiNMOS gates. Using analytical models for the transient behavior of the gates, accurate estimates of the power dissipated by each type of gate during a typical transition...

  5. Diurnal measurements with prototype CMOS Omega receivers

    NASA Technical Reports Server (NTRS)

    Burhans, R. W.

    1976-01-01

    Diurnal signals from eight omega channels have been monitored at 10.2 KHz for selected station pairs. All eight Omega stations have been received at least 50 percent of the time over a 24 hour period during the month of October 1976. The data presented confirm the expected performance of the CMOS omega sensor processor in being able to digsignals out of a noisy environment. Of particular interest are possibilities for use of antipodal reception phenomena and a need for some ways of correcting for multi-modal propagation effects.

  6. Monolithic CMOS imaging x-ray spectrometers

    NASA Astrophysics Data System (ADS)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

    2014-07-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15?m, high resistivity custom (~30k?-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16?m pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40?V/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9?m epitaxial silicon and have a 1k by 1k format. They incorporate similar 16?m pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and spectrally resolved without saturation. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting x-ray astronomy. These features include read noise, x-ray spectral response and quantum efficiency. Funding for this work has been provided in large part by NASA Grant NNX09AE86G and a grant from the Betty and Gordon Moore Foundation.

  7. X-Ray Detector with CMOS Sensor Camera Application of Calcium Denisty Measurement

    Microsoft Academic Search

    Y. Pititheerapab; T. Chanmalueang; T. Rerksngaem; C. Kitipol; C. Pintavirooj

    2006-01-01

    This paper presented a design of an x-ray-detector using CMOS image sensor. The main components consist of CMOS sensor, taper fiber optic, and image intensifier screen. CMOS sensor offers various advantages including miniature-sized, low power consumption and cost effective. CMOS-based digital camera becomes hence very demanding due to its potential application in multimedia and information technology. To apply the CMOS

  8. Enhancing CMOS Using Nanoelectronic Devices: A Perspective on Hybrid Integrated Systems

    Microsoft Academic Search

    David S. Ricketts; James A. Bain; Yi Luo; R. D. Blanton; Kenneth Mai; Gary K. Fedder

    2010-01-01

    In this paper, we present a vision for the cointegration of deeply scaled complementary metal-oxide-semiconductor (CMOS) and emerging nanoelectronic devices into CMOS-hybrid systems. These hybrid systems will create new functionality, modality and add value to existing CMOS integrated circuits. We describe several new nanoelectronic devices which may enable new dimensions to traditional CMOS circuits and systems that build on CMOS

  9. A high speed\\/power ratio continuous-time CMOS current comparator

    Microsoft Academic Search

    Lu Chen; Bingxue Shi; Chun Lu

    2000-01-01

    Current comparator is a fundamental component of current-mode circuits. A new high-performance continuous-time CMOS current comparator is proposed in this paper, which comprises one CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. A MOS resistor is used as the CMOS complementary amplifier's negative feedback. Because the voltage swings of the CMOS complementary amplifier are reduced by low input

  10. Metrology Of Silicide Contacts For Future CMOS

    NASA Astrophysics Data System (ADS)

    Zollner, Stefan; Gregory, Richard B.; Kottke, M. L.; Vartanian, Victor; Wang, Xiang-Dong; Theodore, David; Fejes, P. L.; Conner, J. R.; Raymond, Mark; Zhu, Xiaoyan; Denning, Dean; Bolton, Scott; Chang, Kyuhwan; Noble, Ross; Jahanbani, Mohamad; Rossow, Marc; Goedeke, Darren; Filipiak, Stan; Garcia, Ricardo; Jawarani, Dharmesh; Taylor, Bill; Nguyen, Bich-Yen; Crabtree, P. E.; Thean, Aaron

    2007-09-01

    Silicide materials (NiSi, CoSi2, TiSi2, etc) are used to form low-resistance contacts between the back-end (W plugs and Cu interconnects) and front-end portions (silicon source, drain, and gate regions) of integrated CMOS circuits. At the 65 nm node, a transition from CoSi2 to NiSi was necessary because of the unique capability of NiSi to form narrow silicide nanowires on active (monocrystalline) and gate (polycrystalline) lines. Like its predecessors TiSi2 and CoSi2, NiSi is a mid-gap silicide, i.e., the Fermi level of the NiSi metal is pinned half-way between the conduction and valence band edges in silicon. This leads to a Schottky barrier between the silicide and silicon source-drain regions, which creates undesirable parasitic resistances. For future CMOS generations, band-edge silicides, such as PtSi for contacts to p-type or rare earth silicides for contacts to n-type Si will be needed. This paper reviews metrology and characterization techniques for NiSi process control for development and manufacturing, with special emphasis on x-ray reflectance and x-ray fluorescence. We also report measurement methods useful for development of a PtSi PMOS module.

  11. Far ultraviolet sensitivity of silicon CMOS sensors

    NASA Astrophysics Data System (ADS)

    Davis, Michael W.; Greathouse, Thomas K.; Retherford, Kurt D.; Winters, Gregory S.; Bai, Yibin; Beletic, James W.

    2012-07-01

    We describe vacuum ultraviolet sensitivity measurements of a new high performance silicon-based CMOS sensor from Teledyne Imaging Sensors. These sensors do not require the high voltages of MCP detectors, making them a lower mass and power alternative to the more mature MCP technology. These devices demonstrate up to 40 percent quantum efficiency at vacuum ultraviolet wavelengths, either meeting or greatly exceeding 10 percent quantum efficiency across the entire 100-200 nm wavelength region. As with similar visible sensitive devices, backside illumination results in a higher quantum efficiency than frontside illumination. Measurements of the vacuum ultraviolet sensitivity of the Teledyne silicon PIN detectors were made by directing a known intensity of ultraviolet light at discrete wavelengths onto the test detectors and reading out the resulting photocurrent. The sensitivity of the detector at a given wavelength was then calculated from the intensity and wavelength of the incoming light and the relative photodiode to NIST-traceable calibration diode active areas. A custom electromechanical interface was developed to make these measurements within the SwRI Vacuum Radiometric Calibration Chamber. While still in the single pixel stage, full 1K × 1K focal plane arrays are possible using existing CMOS readout electronics and hold great promise for inclusion in future spaceflight instrument concepts.

  12. A novel colour-sensitive CMOS detector

    NASA Astrophysics Data System (ADS)

    Langfelder, G.; Longoni, A.; Zaraga, F.

    2009-10-01

    A novel colour-sensitive semiconductor detector is proposed. The device (named Transverse Field Detector (TFD)) can be used to measure the colour of the incident light without any colour filter. The device is completely compatible with standard CMOS processes and is suitable to be integrated in a pixel array for imaging purposes. The working principle is based on the capability of this device to collect at different superficial junctions the carriers, generated at different depths, by means of suitable transverse electric fields. The transverse components of the electric field are generated inside the depleted region by a suitable bias of the superficial junctions. Thanks to the differences in the light absorption coefficients at different wavelengths, the device performs colour separation. Among the advantages of this approach are the capability of an active tuning of the pixel colour response, which can be obtained just by changing the biasing values of collecting junctions, and foreseen higher colour fidelity, thanks to the easy extension to four colour pixels. First test structures of three colours TFD pixels were designed and built in a standard CMOS 90 nm technology. Operative principles of the device and first experimental results are presented.

  13. Design of a K-Band Chip Filter With Three Tunable Transmission Zeros Using a Standard 0.13- CMOS Technology

    Microsoft Academic Search

    Chin-Lung Yang; Shin-Yi Shu; Yi-Chyun Chiang

    2010-01-01

    A novel bandpass filter (BPF), which is fabricated with a commercial CMOS process, demonstrating a low insertion loss in the passband and multiple transmission zeros in stopbands, is presented for 24-GHz automotive ultrawideband (UWB) radar systems. The filter combines a second-order asymmetrically compact resonator filter with a source-load coupling mechanism to realize three transmission zeros; two zeros are arranged in

  14. Design of RFICs in 0.35 \\/spl mu\\/m Si\\/SiGe BiCMOS technology for a 5GHz domotic transmitter

    Microsoft Academic Search

    F. Alimenti; M. Borgarino; R. Codeluppi; V. Palazzari; M. Pifferi; L. Roselli; A. Scorzoni; F. Fantini

    2005-01-01

    This paper deals with the basic building blocks of a 5GHz WLAN transmitter for domotic applications. These building blocks have been designed exploiting a commercial 0.35 mum Si\\/SiGe BiCMOS technology with the purpose to avoid the necessity of external components. On-wafer measurements have been carried-out on the realized prototypes showing a good agreement with simulated performances

  15. Design of RFICs in 0.35 ?m Si\\/SiGe BiCMOS technology for a 5 GHz domotic transmitter

    Microsoft Academic Search

    F. Alimenti; M. Borgarino; R. Codeluppi; V. Palazzari; M. Pifferi; L. Roselli; A. Scorzoni; F. Fantini

    2005-01-01

    This paper deals with the basic building blocks of a 5GHz WLAN transmitter for domotic applications. These building blocks have been designed exploiting a commercial 0.35 ?m Si\\/SiGe BiCMOS technology with the purpose to avoid the necessity of external components. On-wafer measurements have been carried-out on the realized prototypes showing a good agreement with simulated performances.

  16. 65 nm CMOS technology (CMOS5) with high density embedded memories for broadband microprocessor applications

    Microsoft Academic Search

    N. Yanagiya; S. Matsuda; S. Inaba; M. Takayanagi; I. Mizushima; K. Ohuchi; K. Okano; K. Takahasi; E. Morifuji; M. Kanda; Y. Matsubara; M. Habu; M. Nishigoori; K. Honda; H. Tsuno; K. Yasumoto; T. Yamamoto; K. Hiyama; K. Kokubun; T. Suzuki; J. Yoshikawa; T. Sakurai; T. Ishizuka; Y. Shoda; M. Moriuchi; M. Kishida; H. Matsumori; H. Harakawa; H. Oyamatsu; N. Nagashima; S. Yamada; T. Noguchi; H. Okamoto; M. Kakumu

    2002-01-01

    In this paper, we present a 65 nm CMOS technology for high performance SoC (system-on-chip), especially for broadband core chip applications. Logic gate length is scaled down to 30 nm, and embedded SRAM cell size is shrunk to 0.6 ?m2. Embedded DRAM cell size is 0.11 ?m2. MOSFET's in this technology have high nitrogen concentration plasma nitrided oxide gate dielectrics

  17. New full-voltage-swing multi-drain/multi-collector complementary BiCMOS buffers (M 2 CBiCMOS)

    NASA Astrophysics Data System (ADS)

    El-Hady, M.; ElSaid, M. H.; Hafez, I. M.; Haddara, H.

    1995-01-01

    In this short paper we introduce new complementary BiCMOS buffers employing multidrain/multi-collector structures. These circuits offer near rail-to-rail output voltage, less circuit complexity, less process complexity, and high performance at scaled down power supply voltages (<2 V). The new circuits are configured in a way that ensures the implemented pnp BJTs (even poor ones) do not appreciably affect the speed performance. The introduced circuits are simulated and compared to conventional BiCMOS and CBiCMOS buffers.

  18. CMOS Hybrid Pixel Detectors for Scientific, Industrial and Medical Applications

    NASA Astrophysics Data System (ADS)

    Broennimann, Christian

    2009-03-01

    Crystallography is the principal technique for determining macromolecular structures at atomic resolution and uses advantageously the high intensity of 3rd generation synchrotron X-ray sources . Macromolecular crystallography experiments benefit from excellent beamline equipment, recent software advances and modern X-ray detectors. However, the latter do not take full advantage of the brightness of modern synchrotron sources. CMOS Hybrid pixel array detectors, originally developed for high energy physics experiments, meet these requirements. X-rays are recorded in single photon counting mode and data thus are stored digitally at the earliest possible stage. This architecture leads to several advantages over current detectors: No detector noise is added to the signal. Readout time is reduced to a few milliseconds. The counting rates are matched to beam intensities at protein crystallography beamlines at 3rd generation synchrotrons. The detector is not sensitive to X-rays during readout; therefore no mechanical shutter is required. The detector has a very sharp point spread function (PSF) of one pixel, which allows better resolution of adjacent reflections. Low energy X-rays can be suppressed by the comparator At the Paul Scherrer Institute (PSI) in Switzerland the first and largest array based on this technology was constructed: The Pilatus 6M detector. The detector covers an area of 43.1 x 44.8 cm2 , has 6 million pixels and is read out noise free in 3.7 ms. Since June 2007 the detector is in routine operation at the beamline 6S of the Swiss Light Source (SLS). The company DETCRIS Ltd, has licensed the technology from PSI and is commercially offering the PILATUS detectors. Examples of the wide application range of the detectors will be shown.

  19. Prompt and total dose response of hard 4K and 16K CMOS static random access memories (SRAMs)

    NASA Astrophysics Data System (ADS)

    Witteles, A. A.; Volmerange, H.; Davidson, H.; Yue, H.; Jennings, R.; Brucker, G. J.

    1984-12-01

    Total dose (TD) and prompt dose (PD) rate effects were measured in three types of SRAMs: Harris 6504RH (CMOS/bulk) and RCA 11121 (CMOS/SOS) which are commercially available 4K memories, and developmental samples of a more recent hardened 16K CMOS/SOS SRAM (RCA TA 12702). TD exposure was performed with C0-60 at dose rates of 5-240 rad (Si)/s, while PD testing used facilities that can deliver a PD of 7 krad (Si) in a 22 ns pulse and 50 krad (Si) in a 45 ns pulse. The results indicate that the dynamic upset level for the TA 12702 is 1.1 x 10 to the 11th rad (Si) for either a read or write mode of operation at 5 V bias for a wide range of process variables. The static upset level for most of the samples was greater than 5 x 10 to the 11th rad (Si)/s. Increasing the voltage to 6 V would make the noncorruptible dose rate about 10 to the 12th rad (Si)/s. It is concluded that production-quality parts of all three device types can operate at high ionizing dose levels, i.e., greater than 100 krad (Si).

  20. Real-time video rate imaging with a 1k-pixel THz CMOS focal plane array

    NASA Astrophysics Data System (ADS)

    Grzyb, J.; Sherry, H.; Zhao, Y.; Al Hadi, R.; Cathelin, A.; Kaiser, A.; Pfeiffer, U.

    2012-06-01

    Future submillimeter-wave and THz (300GHz-3THz) imaging applications will require low-cost portable systems operating at room-temperature with a video-rate speed and capable of delivering acceptable sensitivity at the very low-power consumption levels to become attractive for truly commercial applications. In particular, CMOS technologies are of interest due to their high integration level offered at a high yield that is capable of massive cost reduction of currently existing THz systems. It has been recently demonstrated that CMOS direct detectors achieve the performance comparable or even superior to the today's existing classical THz devices for active imaging operating at room-temperature. So far, however, only single pixels have been used, allowing only a raster-scan operation. To address this obstacle, we present the very initial work on a 1k-pixel camera chip with a completely integrated readout circuitry and with a full video-rate capability at a power consumption of 2.5?W/pixel. The chip is fully compliant with an industrial bulk CMOS technology and it is intended for active imaging applications. It exhibits a pixel pitch of 80?m, defined by a novel on-chip wire ring antenna, and is designed to accommodate silicon hyper-hemispherical lens for a wide operation bandwidth of at least 0.7-1.1 THz.

  1. A SubMicron BiCMOS Technology for Telecommunications

    Microsoft Academic Search

    R. Hadaway; P. Kempf; P. Schvan; M. Rowlandson; V. Ho; J. Kolk; B. Tait; D. Sutherland; G. Jolly; I. Emesh

    1991-01-01

    A high performance, 0.8 æm, analog-digital technology is presented. Telecommunication circuit and system diversity has been accommodated by incorporating modular device options into a triple-level-metal BiCMOS process.

  2. CMOS front-end amplifier for broadband DTV tuner 

    E-print Network

    Zhang, Guang

    2005-08-29

    In this work, the design of a CMOS broadband low noise amplifier with inherent high performance single-to-differential conversion is presented. These characteristics are driven by the double quadrature single conversion digital television tuner...

  3. CMOS temperature sensor utilizing interface-trap charge pumping 

    E-print Network

    Berber, Feyza

    2006-10-30

    The objective of this thesis is to introduce an alternative temperature sensor in CMOS technology with small area, low power consumption, and high resolution that can be easily interfaced. A novel temperature sensor utilizing the interface...

  4. Design of a CMOS compatible, athermal, optical waveguide

    E-print Network

    Fernandez, Luis Enrique, S.B. Massachusetts Institute of Technology

    2007-01-01

    This paper explores a possible design for a CMOS compatible, athermal, optical waveguide. The design explored is a slot waveguide with light guided in the low index material. A design paradigm is proposed which shows the ...

  5. Circuits and algorithms for pipelined ADCs in scaled CMOS technologies

    E-print Network

    Brooks, Lane Gearle, 1975-

    2008-01-01

    CMOS technology scaling is creating significant issues for analog circuit design. For example, reduced signal swing and device gain make it increasingly difficult to realize high-speed, high-gain feedback loops traditionally ...

  6. CMOS front-end amplifier for broadband DTV tuner

    E-print Network

    Zhang, Guang

    2005-08-29

    In this work, the design of a CMOS broadband low noise amplifier with inherent high performance single-to-differential conversion is presented. These characteristics are driven by the double quadrature single conversion digital television tuner...

  7. CMOS temperature sensor utilizing interface-trap charge pumping

    E-print Network

    Berber, Feyza

    2006-10-30

    The objective of this thesis is to introduce an alternative temperature sensor in CMOS technology with small area, low power consumption, and high resolution that can be easily interfaced. A novel temperature sensor utilizing the interface...

  8. CMOS serial link for fully duplexed data communication

    NASA Astrophysics Data System (ADS)

    Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

    1995-04-01

    This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

  9. A Single-Transistor Active Pixel CMOS Image Sensor Architecture

    NASA Astrophysics Data System (ADS)

    Zhang, Guo-An; Zhang, Dong-Wei; He, Jin; Su, Yan-Mei; Wang, Cheng; Chen, Qin; Liang, Hai-Lang; Ye, Yun

    2012-03-01

    A single-transistor CMOS active pixel image sensor (1 T CMOS APS) architecture is proposed. By switching the photosensing pinned diode, resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower. Thus, the reset and selected transistors can be removed. In addition, the reset and selected signal lines can be shared to reduce the metal signal line, leading to a very high fill factor. The pixel design and operation principles are discussed in detail. The functionality of the proposed 1T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35 ?m CMOS AMIS technology.

  10. A silicon avalanche photodetector fabricated with standard CMOS technology

    E-print Network

    Choi, Woo-Young

    A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain a silicon avalanche photodetector (APD) fabricated with standard complementary metal-well junction, and its current-voltage characteristics, responsivity, avalanche gain, and photodetection

  11. Fabrication and simulation of CMOS-compatible photodiodes

    E-print Network

    DiLello, Nicole Ann

    2008-01-01

    CMOS-compatible photodiodes are becoming increasinging important devices to study because of their application in combined electronic-photonic systems. They are already used as inexpensive optical transceivers in fiber ...

  12. The prospects for 10 nm III-V CMOS

    E-print Network

    del Alamo, Jesus A.

    The increasing difficulties for further scaling down of Si CMOS is bringing to the fore the investigation of alternative channel materials. Among these, III-V compound semiconductors are very attractive due to their ...

  13. Photonic Device Layout Within the Foundry CMOS Design Environment

    E-print Network

    Orcutt, Jason Scott

    A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs ...

  14. Strain-engineered CMOS-compatible Ge photodetectors

    E-print Network

    Cannon, Douglas Dale, 1974-

    2004-01-01

    The development of CMOS-compatible photodetectors capable of operating throughout the entire telecommunications wavelength spectrum will aid in the integration of photodetectors with Si microelectronics, thus offering a ...

  15. Depleted Monolithic Active Pixel Sensors (DMAPS) implemented in LF-150 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Kishishita, T.; Hemperek, T.; Krüger, H.; Wermes, N.

    2015-03-01

    We present the recent development of Depleted Monolithic Active Pixel Sensors (DMAPS), implemented with an LFoundry (LF) 150 nm CMOS process. MAPS detectors based on an epi-layer have been matured in recent years and have attractive features in terms of reducing material budget and handling cost compared to conventional hybrid pixel detectors. However, the obtained signal is relatively small (~1000 e?) due to the thin epi-layer, and charge collection time is relatively slow, e.g., in the order of 100 ns, because charges are mainly collected by diffusion. Modern commercial CMOS technology, however, offers advanced process options to overcome such difficulties and enable truly monolithic devices as an alternative to hybrid pixel sensors and charge coupled devices. Unlike in the case of the standard MAPS technologies with epi-layers, the LF process provides a high-resistivity substrate that enables large signal and fast charge collection by drift in a ~50 ?m thick depleted layer. Since this process also enables the use of deep n- and p-wells to isolate the collection electrode from the thin active device layer, PMOS and NMOS transistors are available for the readout electronics in each pixel cell. In order to evaluate the sensor and transistor characteristics, several collection electrodes variants and readout architectures have been implemented. In this report, we focus on its design aspect of the LF-DMAPS prototype chip.

  16. Optical modulation techniques for analog signal processing and CMOS compatible electro-optic modulation

    NASA Astrophysics Data System (ADS)

    Gill, Douglas M.; Rasras, Mahmoud; Tu, Kun-Yii; Chen, Young-Kai; White, Alice E.; Patel, Sanjay S.; Carothers, Daniel; Pomerene, Andrew; Kamocsai, Robert; Beattie, James; Kopa, Anthony; Apsel, Alyssa; Beals, Mark; Mitchel, Jurgen; Liu, Jifeng; Kimerling, Lionel C.

    2008-02-01

    Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production CMOS electronics will enable new design paradigms for existing system architectures and open new opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint, weight, and power consumption of today's communication systems. While broadband analog system applications represent a smaller volume market than that for digital data transmission, there are significant deployments of analog electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block in optical analog signal processing and also could have significant applications in digital communication systems. Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges and opportunities for analog signal processing since the index and propagation loss change within the waveguide during modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques for optical modulation.

  17. A resistorless CMOS current reference with temperature compensation

    Microsoft Academic Search

    Yan Wei; Tian Xin; Li Wenhong; Liu Ran

    2011-01-01

    A resistorless CMOS current reference is presented. Temperature compensation is achieved by subtracting two sub-currents with different positive temperature coefficients. The circuit has been implemented with a Chartered 0.35 mum CMOS process. The output current is 1.5 muA, and the circuit works properly with a supply voltage down to 2 V. Measurement results show that the temperature coefficient is 98

  18. An integrated CMOS distributed amplifier utilizing packaging inductance

    Microsoft Academic Search

    Patrick J. Sullivan; Bernard A. Xavier; Walter H. Ku

    1997-01-01

    An integrated CMOS distributed amplifier is presented. The required inductance needed for the distributed waveguide structure is realized by the parasitic packaging inductance of a plastic surface-mount package. A fully packaged three-stage distributed amplifier fabricated in a 0.8-?m CMOS process is presented. The distributed amplifier has a unity gain cutoff frequency of 4.7 GHz, a gain of 5 dB, with

  19. BiCMOS OEIC with enhanced sensitivity for DVD systems

    Microsoft Academic Search

    K. Kieschnick; H. Zimmermann; P. Seegebrecht

    2001-01-01

    A new BiCMOS OEIC with enhanced sensitivity for advanced optical storage systems is presented. The photodiode and the amplifier are monolithically integrated on the same substrate in an industrial 0:8 µm BiCMOS process. The OEIC shows a sensitivity of 43.3mV\\/µW in combination with a -3 dB-bandwidth of 60.2 MHz.

  20. Electrical properties and detection methods for CMOS IC defects

    Microsoft Academic Search

    Jerry M. Soden; Charles F. Hawkins

    1989-01-01

    CMOS failure modes and mechanisms and the test vector and parametric test requirements for the detection are reviewed. The CMOS stuck-open fault is discussed from a physical viewpoint, with results given from failure analysis of ICs having this failure mode. The results show that among functional, stuck-at, stuck-open, and IDDQ test strategies, no single method guarantees detection of all types

  1. Delta Doping High Purity CCDs and CMOS for LSST

    NASA Technical Reports Server (NTRS)

    Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

    2006-01-01

    A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

  2. An Immunoassay Platform Based on CMOS Hall Sensors

    Microsoft Academic Search

    Turgut Aytur; P. Robert Beatty; Bernhard Boser; Tomohiro Ishikawa

    2002-01-01

    We describe an immunoassay utilizing standard CMOS technology. An array of Hall sensors is used to detect the magnetic beads that serve as the assay signal. Electrical and magnetic modulation is employed to improve the sensitivity of the sensors. The devices receive two post-processing steps to improve sensitivity and biocompatibility. We have fabricated prototype devices using a 0.25-µm BiCMOS process,

  3. Phase noise analysis and design of CMOS differential ring VCO

    Microsoft Academic Search

    Honghui Deng; Yongsheng Yin; Gaoming Du

    2009-01-01

    A complete six-order CMOS differential ring voltage-controlled oscillator (VCO) is designed with a 0.35\\/m CMOS process in this paper. The circuit has been successfully applied in a CPPLL of a high-speed high-resolution DAC, and has been successfully taped out and passed the test. The relative factors that influence the VCO phase noise are analyzed comprehensively to instruct the circuit design.

  4. IR CMOS: ultrafast laser-enhanced silicon detection

    Microsoft Academic Search

    M. U. Pralle; J. E. Carey; H. Homayoon; J. Sickler; X. Li; J. Jiang; D. Miller; C. Palsule; J. McKee

    2011-01-01

    SiOnyx has developed a novel silicon processing technology for CMOS sensors that will extend spectral sensitivity into the near\\/shortwave infrared (NIR\\/SWIR) and enable a full performance digital night vision capability comparable to that of current image-intensifier based night vision goggles. The process is compatible with established CMOS manufacturing infrastructure and has the promise of much lower cost than competing approaches.

  5. CMOS RF receiver design for wireless LAN applications

    Microsoft Academic Search

    Behzad Razavi

    1999-01-01

    This paper describes design techniques for RF CMOS receivers operating in the 2.4-GHz band. A direct-conversion receiver targetting spread-spectrum wireless LAN applications employs partial channel selection filtering, DC offset removal and baseband amplification. Fabricated in a 0.6-?m CMOS technology, the receiver achieves a noise figure of 8.3 dB, IP3 of -9 dBm, IP2 of +22 dBm, and voltage gain of

  6. Simple SPICE model for comparison of CMOS output driver circuits 

    E-print Network

    Hermann, John Karl

    1993-01-01

    on CMOS technologies. Journal model is IEEE 'I?ansactions on Automatic Control. A. Literature Survey Research has been done in the past concerning noise generated by digital logic de- vices. In particular, Advanced CMOS Logic (ACL) integrated circuits... supply voltage are easy to incorporate. A. Model Attributes Integrated circuits are filled with various parasitic components. Some of these par- asitics aid the design effort. More often than not, however, parasitic components that are large enough...

  7. Radiation-hardened N (+) gate CMOS\\/SOS

    Microsoft Academic Search

    G. W. Hughes; G. J. Brucker; R. K. Smeltzer

    1981-01-01

    Process development work for a hardened N+ polysilicon-gate CMOS\\/SOS process has demonstrated that it is possible to make functional 4K CMOS\\/SOS static RAMs that are hard to 5 x 10 to the 5th power rads without the implementation of special hardened circuit design techniques. Present circuit probe yields are low, limited by the lack of a hardened low-temperature contoured field

  8. Black silicon enhanced photodetectors: a path to IR CMOS

    Microsoft Academic Search

    M. U. Pralle; J. E. Carey; H. Homayoon; S. Alie; J. Sickler; X. Li; J. Jiang; D. Miller; C. Palsule; J. McKee

    2010-01-01

    SiOnyx has developed a novel silicon processing technology for CMOS sensors that will extend spectral sensitivity into the near\\/shortwave infrared (NIR\\/SWIR) and enable a full performance digital night vision capability comparable to that of current image-intensifier based night vision goggles. The process is compatible with established CMOS manufacturing infrastructure and has the promise of much lower cost than competing approaches.

  9. A statistical MOSFET modeling method for CMOS integrated circuit simulation

    E-print Network

    Chen, Jian

    1992-01-01

    A STATISTICAL MOSFET MODELING METHOD FOR CMOS IN'I'EGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Submitted to the Office of Graduate Studies of Texas AE~M University in partial fulfillment of the requirements for the degree of MASTER... OF SCIENCE August l 99'2 Major Sub ject: Electrical Engineering A STATISTICAL MOSFET MODELING METHOD FOR CMOS INTEGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Approved as to style and content by: H. Maciej . Styblinski ) (Chair of Committee...

  10. W-band pulsed radar receiver in low cost CMOS

    Microsoft Academic Search

    Ning Zhang; K. O. Kenneth

    2010-01-01

    A CMOS heterodyne receiver integrating a phase-locked loop that includes a bulk of transmitter functions for W-band pulsed radar is realized using low leakage transistors of a low cost 65-nm bulk CMOS process with 5 thin and 1 thick metal layers used to manufacture cell phone RFIC's. The peak conversion gain of receiver is 7 dB and the minimum NF

  11. High gain CMOS UWB LNA employing thermal noise cancellation

    Microsoft Academic Search

    Mehdi Forouzanfar; Sasan Naseh

    2009-01-01

    This paper presents a 3.1-10.6 GHz CMOS LNA designed with a 0.18 mum CMOS technology. In this amplifier, cancellation of two important noise sources in the amplifier, plus increasing effective transconductance of the input stage, reduce the noise figure (NF) of the amplifier. Noise canceling LNAs suffer from relatively low power gain. In contrast, this paper presents an ultra-wideband LNA

  12. Wide intrascene dynamic range CMOS APS using dual sampling

    Microsoft Academic Search

    Orly Yadid-Pecht; Eric R. Fossum

    1997-01-01

    A CMOS active pixel sensor (APS) that achieves wide intrascene dynamic range using dual sampling is reported. A 64×64 element prototype sensor with dual output architecture was fabricated using a 1.2 ?m n-well CMOS process with 20.4 ?m pitch photodiode-type active pixels. The sensor achieves an intrascene dynamic range of 109 dB without nonlinear companding

  13. CMOS Image Sensors: Electronic Camera On A Chip

    NASA Technical Reports Server (NTRS)

    Fossum, E. R.

    1995-01-01

    Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

  14. Study of CMOS APS Responsivity Enhancement: Ring-Shaped Photodiode

    Microsoft Academic Search

    Tatiana Danov; Igor Shcherback; Orly Yadid-Pecht

    2005-01-01

    In this work the possibilities of CMOS APS spectral response improvement are discussed. Thorough submicron scanning results obtained from various ring-shaped pixel photodiodes with different inner radius, implemented in a standard CMOS 0.35µm technology, are compared with numerical computer simulations. The functional dependence of the pixel response on the ring opening size was discovered and formulated for various wavelengths illumination.

  15. Study of CMOS APS responsivity enhancement: ring-shaped photodiode

    Microsoft Academic Search

    Tatiana Danov; Igor Shcherback; Orly Yadid-Pecht

    2005-01-01

    In this brief, the possibilities of complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) spectral response improvement are discussed. Thorough submicrometer scanning results obtained from various ring-shaped pixel photodiodes with different inner radius, implemented in a standard CMOS 0.35-?m technology, are compared with numerical computer simulations and verified analytically. The functional dependence of the pixel response on the ring opening size

  16. CMOS device optimization for mixed-signal technologies

    Microsoft Academic Search

    P. A. Stolk; H. P. Tuinhout; R. Duffy; E. Augendre; L. P. Bellefroid; M. J. B. Bolt; J. Croon; C. J. J. Dachs; F. R. J. Huisman; A. J. Moonen; Y. V. Ponomarev; R. F. M. Roes; M. Da Rold; E. Seevinck; K. N. Sreerambhatla; R. Surdeanu; R. M. D. A. Velghe; M. Vertregt; M. N. Webster; N. K. J. van Winkelhoff; A. T. A. Zegers-Van Duijnhoven

    2001-01-01

    This paper studies the suitability of CMOS device technology for mixed-signal applications. The currently proposed scaling scenario's for CMOS technologies lead to strong degradation of analog transistor performance. As a result the combined optimization of digital and analog devices for system-on-a-chip applications will require increasingly elaborate process modifications. New device solutions such as metal gate integration and asymmetric (source-side-only) workfunction

  17. Nano-CMOS Technology for Next Fifteen Years

    Microsoft Academic Search

    H. Iwai; H. Wong

    2006-01-01

    Complementary metal-oxide-semiconductor (CMOS) technology has been developed into the sub-100 nm range. It is expected that the nano-CMOS technology will govern the IC manufacturing for at least another couple of decades. Though there are many challenges ahead, further down-sizing the device to a few nanometers is still on the schedule of International Technology Roadmap for Semiconductors (ITRS). Several technological options

  18. CMOS image sensors optimised for GEO observation

    NASA Astrophysics Data System (ADS)

    Bréart de Boisanger, Michel; Larnaudie, Franck; Saint-Pé, Olivier

    2013-10-01

    CMOS Image Sensors (CIS) arrays have well proven their capabilities to address the growing need of space imaging from the GEO orbit within the visible and near infrared spectral bands. The main interesting features of CIS detectors for such applications are smearing-free capability, small pixel pitches even with large charge handling capacity, fine tuning of QE and MTF, low power dissipation, exposure control and good radiation behaviour. This paper will present new results obtained by our team in the field of development of such 2D arrays, including large format detectors (up to 12 million pixels), front and back side illuminations, 3T and 4T pixels, microlenses and different types of epitaxial layers/thicknesses. Radiometric and geometric characterisation results obtained for various devices will be presented.

  19. Log polar image sensor in CMOS technology

    NASA Astrophysics Data System (ADS)

    Scheffer, Danny; Dierickx, Bart; Pardo, Fernando; Vlummens, Jan; Meynants, Guy; Hermans, Lou

    1996-08-01

    We report on the design, design issues, fabrication and performance of a log-polar CMOS image sensor. The sensor is developed for the use in a videophone system for deaf and hearing impaired people, who are not capable of communicating through a 'normal' telephone. The system allows 15 detailed images per second to be transmitted over existing telephone lines. This framerate is sufficient for conversations by means of sign language or lip reading. The pixel array of the sensor consists of 76 concentric circles with (up to) 128 pixels per circle, in total 8013 pixels. The interior pixels have a pitch of 14 micrometers, up to 250 micrometers at the border. The 8013-pixels image is mapped (log-polar transformation) in a X-Y addressable 76 by 128 array.

  20. CMOS digital pixel sensors: technology and applications

    NASA Astrophysics Data System (ADS)

    Skorka, Orit; Joseph, Dileepan

    2014-04-01

    CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

  1. Latchup in CMOS devices from heavy ions

    NASA Technical Reports Server (NTRS)

    Soliman, K.; Nichols, D. K.

    1983-01-01

    It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

  2. Commercial Capaciflector

    NASA Technical Reports Server (NTRS)

    Vranish, John M.

    1991-01-01

    A capacitive proximity/tactile sensor with unique performance capabilities ('capaciflector' or capacitive reflector) is being developed by NASA/Goddard Space Flight Center (GSFC) for use on robots and payloads in space in the interests of safety, efficiency, and ease of operation. Specifically, this sensor will permit robots and their attached payloads to avoid collisions in space with humans and other objects and to dock these payloads in a cluttered environment. The sensor is simple, robust, and inexpensive to manufacture with obvious and recognized commercial possibilities. Accordingly, NASA/GSFC, in conjunction with industry, is embarking on an effort to 'spin' this technology off into the private sector. This effort includes prototypes aimed at commercial applications. The principles of operation of these prototypes are described along with hardware, software, modelling, and test results. The hardware description includes both the physical sensor in terms of a flexible printed circuit board and the electronic circuitry. The software description will include filtering and detection techniques. The modelling will involve finite element electric field analysis and will underline techniques used for design optimization.

  3. CMOS image sensor with contour enhancement

    NASA Astrophysics Data System (ADS)

    Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

    2010-10-01

    Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5?m DPTM CMOS process.

  4. PIN photodiodes with significantly improved responsivities implemented in a 0.35Āµm CMOS\\/BiCMOS technology

    Microsoft Academic Search

    I. Jonak-Auer; A. Marchlewski; S. Jessenig; A. Polzer; W. Gaberl; A. Schmiderer; E. Wachmann; H. Zimmermann

    2010-01-01

    We report on monolithically integrated PIN photodiodes whose responsivity values could be significantly enhanced over the whole spectral range by the implementation of a Bottom Antireflective Coating (BARC) process module into austriamicrosystems 0.35mum CMOS as well as high-speed SiGe BiCMOS technologies. The resulting photodiodes achieve excellent responsivities together with low capacitances and high bandwidths. We processed finger-photodiodes with interdigitated n+

  5. CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) Circuit Design for Nanosecond Quantum-Bit Read-out

    Microsoft Academic Search

    Thomas M. Gurrieri; Malcolm S. Carroll; Michael P. Lilly; James E. Levy

    2008-01-01

    Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling

  6. Design Considerations for CMOS-Integrated Hall-Effect Magnetic Bead Detectors for Biosensor Applications.

    PubMed

    Skucha, K; Gambini, S; Liu, P; Megens, M; Kim, J; Boser, Be

    2013-06-01

    We describe a design methodology for on-chip magnetic bead label detectors based on Hall-effect sensors. Signal errors caused by the label-binding process and other factors that limit the minimum detection area are quantified and adjusted to meet typical assay accuracy standards. The methodology is demonstrated by designing an 8192 element Hall sensor array, implemented in a commercial 0.18 ?m CMOS process with single-mask postprocessing. The array can quantify a 1% surface coverage of 2.8 ?m beads in 30 seconds with a coefficient of variation of 7.4%. This combination of accuracy and speed makes this technology a suitable detection platform for biological assays based on magnetic bead labels. PMID:25031503

  7. Design Considerations for CMOS-Integrated Hall-Effect Magnetic Bead Detectors for Biosensor Applications

    PubMed Central

    Skucha, K.; Gambini, S.; Liu, P.; Megens, M.; Kim, J.; Boser, BE

    2014-01-01

    We describe a design methodology for on-chip magnetic bead label detectors based on Hall-effect sensors. Signal errors caused by the label-binding process and other factors that limit the minimum detection area are quantified and adjusted to meet typical assay accuracy standards. The methodology is demonstrated by designing an 8192 element Hall sensor array, implemented in a commercial 0.18 ?m CMOS process with single-mask postprocessing. The array can quantify a 1% surface coverage of 2.8 ?m beads in 30 seconds with a coefficient of variation of 7.4%. This combination of accuracy and speed makes this technology a suitable detection platform for biological assays based on magnetic bead labels. PMID:25031503

  8. Exploiting Hysteresis in a CMOS Bu er Radu M. Secareanu, Victor Adler, and Eby G. Friedman

    E-print Network

    Friedman, Eby G.

    Exploiting Hysteresis in a CMOS Bu er Radu M. Secareanu, Victor Adler, and Eby G. Friedman@ece.rochester.edu, adler@ece.rochester.edu, friedman@ece.rochester.edu Abstract| A high drive CMOS bu er circuit character

  9. CMOS Integrated Circuit Design for Ultra-Wideband Transmitters and Receivers 

    E-print Network

    Xu, Rui

    2010-10-12

    and Bluetooth are mostly narrow band based. To implement UWB technologies on CMOS imposes the development of CMOS front-end building blocks which can perform wideband signal processing such as amplifying, frequency conversion, frequency generation as well...

  10. A 4-ns 4K*1-bit two-port BiCMOS SRAM

    Microsoft Academic Search

    TSEN-SHAU YANG; MARK A. HOROWITZ; BRUCE A. WOOLEY

    1988-01-01

    T'fris paper introduces a two-port BiCMOS static memory cell that combines ECL-level word-linevoltageswingsandemitter-follower bit-line coupling with a static CMOS latch for data storage. With this cell, referred to as a CMOS storage emitter access (CSEA) cell, it is possible to achieve access times comparable to those of high-speed bipolar SRAM'S while preserving the high density and low power of CMOS

  11. Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano\\/CMOS Circuit Design

    Microsoft Academic Search

    Weisheng Zhao; Guillaume Agnus; Vincent Derycke; Ariana Filoramo; Christian Gamrat; Jean-Philippe Bourgoin

    2009-01-01

    Hybrid Nano (e.g. Nanotube and Nanowire) \\/CMOS circuits combine both the advantages of Nano-devices and CMOS technologies;\\u000a they have thus become the most promising candidates to relax the intrinsic drawbacks of CMOS circuits beyond Moore’s law.\\u000a A functional simulation model for an hybrid Nano\\/CMOS design is presented in this paper. It is based on Optically Gated Carbon\\u000a NanoTube Field Effect

  12. A JFET-CMOS Technology for Low-Noise Sensor Interface Circuits

    Microsoft Academic Search

    Hidekuni Takao; Rikiya Asaoka; Kazuaki Sawada; Shoji Kawahito; Makoto Ishida

    2003-01-01

    In this paper, fabrication technology and device characteristics of junction field effect transistor (JFET) which can be integrated in CMOS sensor interface circuits are presented. The JFET is applicable to CMOS (operational) amplifiers to realize a very low-noise front-end amplifier in sensor interface circuits. It is formed with isolated p-well area in CMOS device. Extra processes to a standard CMOS

  13. CMOS photodetectors\\/receivers for smart-pixel based photonic systems

    Microsoft Academic Search

    Jianjing Tang; Sunil Konanki; Bharath Seshadri; Boon K. Lee; Robert C. Chi; Andrew J. Steckl; Fred R. Beyette

    2000-01-01

    The design, characterization and evaluation of CMOS based silicon photodetectors\\/photoreceivers suitable for smart-pixel based applications are presented. Implemented with a conventional CMOS fabrication process, these photodetectors\\/receiver circuits can be reliably fabricated for smart-pixel based photonic information processing systems that combine the parallelism associated with optics and the data processing capabilities associated with CMOS logic. Several different CMOS based photodetector structures

  14. Polyadenylation of c-mos mRNA as a control point in Xenopus meiotic maturation

    Microsoft Academic Search

    Michael D. Sheets; Michael Wu; Marvin Wickens

    1995-01-01

    c-mos protein, encoded by a proto-oncogene, is essential for the meiotic maturation of frog oocytes. Polyadenylation of c-mos messenger RNA is shown here to be a pivotal regulatory step in meiotic maturation. Maturation is prevented by selective amputation of polyadenylation signals from c-mos mRNA. Injection of a prosthetic RNA, which restores c-mos polyadenylation signals by base pairing to the amputated

  15. CMOS foundry Schottky diode microwave power detector fabrication, Spice modeling, and application

    Microsoft Academic Search

    W. Jeon; J. Melngailis

    2006-01-01

    CMOS Schottky diodes with various contact areas and geometries were fabricated through 0.35mu CMOS process. Fabricated diodes were tested under DC and RF direct injection. Based on the measured result, a CMOS Schotkty diode SPICE model is suggested and simulated. The suggested SPICE model is used for designing charge pump circuits

  16. CMOS-based microsensors ISBN 87-89935-50-0 21

    E-print Network

    Akin, Tayfun

    dynamic range. A 16x16 test array is fabricated using a 0.8µm CMOS process. Each detector pixel imagers are challenged by CMOS imagers that have advantages like low cost, low power consumption CMOS process. The detector diode in each pixel is reverse biased, and when incoming photons

  17. IntroductionIntroduction Development of SerDes IP based on 018nm CMOS

    E-print Network

    Choi, Woo-Young

    degeneration amplifier (Cherry-Hooper amplifier) - Power Detector: Current steering rectifier to increaseIntroductionIntroduction Topic Development of SerDes IP based on 018nm CMOS Team member Team member CMOS technologyA 2.7 Gb/s Adaptive Equalizer in 0.18um CMOS technology 2.7Gb/s Adaptive Feed forward

  18. CMOS Schottky diode microwave power detector fabrication, Spice modeling, and applications

    Microsoft Academic Search

    Woochul Jeon; John Melngailis; Robert W. Newcomb

    2006-01-01

    CMOS Schottky diodes with various contact areas and geometries were fabricated through 0.35? CMOS process. Fabricated diodes were tested under DC and RF direct injection. Based on the measured result, a CMOS Schottky diode SPICE model is suggested and simulated. The suggested SPICE model is used for designing charge pump circuits and a low-voltage reference circuit.

  19. On-Chip RF Pulse Power Detector Using FIB as a Post-CMOS Fabrication Process

    Microsoft Academic Search

    Woochul Jeon; Todd M. Firestone; John C. Rodgers; John Melngailis

    2006-01-01

    RF pulse power detectors on a CMOS chip may be useful in studying and mitigating the effects of unwanted RF radiation on chip performance. Focused ion beam (FIB) milling and ion-induced deposition were used as post-fabrication steps to build Schottky diodes on the CMOS chips fabricated using MOSIS. The standard CMOS layout of chips had Schottky diodes and was fabricated

  20. T. Lee, Paul G. Allen Center for Integrated Systems Narrowband CMOS RF Low-Noise Amplifiers

    E-print Network

    Lee, Thomas H.

    T. Lee, Paul G. Allen Center for Integrated Systems Narrowband CMOS RF Low-Noise Amplifiers Narrowband CMOS RF Low-Noise Amplifiers Prof. Thomas H. Lee Stanford University tomlee@ee.stanford.edu http://www-smirc.stanford.edu #12;T. Lee, Paul G. Allen Center for Integrated Systems Narrowband CMOS RF Low-Noise Amplifiers

  1. On-wafer calibration techniques for giga-hertz CMOS measurements

    Microsoft Academic Search

    Troels Emil Kolding; Fredrik Bajers Vej

    1999-01-01

    This paper presents five different methods for performing on-wafer calibration of RF CMOS measurements. All methods are compatible with standard CMOS technology. A comparison of method performance up to 12 GHz is made with measurements on RF CMOS devices. The results verify that substrate and metallization losses must be considered to obtain high accuracy. Fixture design issues are discussed and

  2. A 12 mW wide dynamic range CMOS front end for a portable GPS receiver

    Microsoft Academic Search

    A. R. Shahani; D. K. Shaeffer; T. H. Lee

    1997-01-01

    At submicron channel lengths, CMOS is an attractive alternative to silicon bipolar and GaAs MESFET technologies for use in wireless receivers. A 12mW Global Positioning System (GPS) receiver front-end, comprising a low noise amplifier (LNA) and mixer implemented in a standard 0.35?m digital CMOS process, demonstrates the aptitude of CMOS for portable wireless applications

  3. Modeling the current behavior of the digital BiCMOS gate 

    E-print Network

    Tang, Zhilong

    1995-01-01

    This thesis describes a piece-wise approximation of transient current response of the digital BiCMOS gate. Based on the detailed transient analysis of the conventional digital BiCMOS gate, a new circuit model for digital BiCMOS gate is derived which...

  4. Planarization of a CMOS die for an integrated metal MEMS Hocheol Lee*, Michele H. Miller+

    E-print Network

    for metal MEMS, the polymer benzocyclobutene (BCB), which has been used for multichip module applicationsPlanarization of a CMOS die for an integrated metal MEMS Hocheol Lee*, Michele H. Miller+ , Thomas a flat CMOS die surface for the integration of a MEMS metal mirror array. The CMOS die for our device

  5. A new type of CMOS inverter with Lubistor load and NMOS driver

    Microsoft Academic Search

    Jyi-Tsong Lin; Hsuan-Hsu Chen; Kuan-Yu Lu; Cheng-Hsin Chen

    2010-01-01

    This paper presents a non-conventional CMOS device, which is composed of an nMOSFET and a tunneling field effect transistor (TFET) for driver and load. Based on the measurement data of TFET device published, we have for the first time drawn the Q line of the new designed CMOS compared with the conventional CMOS to verify its feasibility. The static power

  6. Low Threshold CMOS Circuits with Low Standby Current Mircea R. Stan

    E-print Network

    Stan, Mircea R.

    Low Threshold CMOS Circuits with Low Standby Current Mircea R. Stan University of Virginia, Electrical Engineering Department Charlottesville, VA 22903 mircea@virginia.edu Abstract Multi­Voltage CMOS­Threshold CMOS (MTCMOS). 1 Introduction Low­power design techniques try to reduce the power dis­ sipation of high

  7. A In-depth Simulation Study of CMOS Inverters Based on the Novel Surrounding Gate Transistors

    Microsoft Academic Search

    A. Roldan; J. B. Roldan; F. Gamiz

    2008-01-01

    The main features of CMOS inverters based on the novel surrounding gate transistors (SGT) have been analyzed. A Verilog-A compact model for the SGT has been implemented in a circuit simulator to study both analog and digital circuits. In particular, CMOS inverter gate delays, CMOS inverter ring oscillator frequencies, etc., have been obtained in order characterize the relations between the

  8. Multi-gigabit signaling with CMOS William J. Dally -Massachusetts Institute of Technology

    E-print Network

    Poulton, John W.

    , 1997 · 0.5µ CMOS has FO4 inverter delay of about 180psec Can switch current onto a differential wire elements (simulated jitter ~ 40psec in 0.5µ CMOS) Closed-loop timing recovery cancels skew & lowMulti-gigabit signaling with CMOS William J. Dally - Massachusetts Institute of Technology John

  9. Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load

    E-print Network

    Friedman, Eby G.

    Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load Victor Adler, transition time, and short circuit power dissipa- tion for a CMOS inverter driving resistive@ee.rochester. edu. friedman@ee.rochester.edu Abstract ­ A delay and power model of a CMOS in- verter driving

  10. Modeling the current behavior of the digital BiCMOS gate

    E-print Network

    Tang, Zhilong

    1995-01-01

    This thesis describes a piece-wise approximation of transient current response of the digital BiCMOS gate. Based on the detailed transient analysis of the conventional digital BiCMOS gate, a new circuit model for digital BiCMOS gate is derived which...

  11. Abstract -CMOS processes that have been developed primarily for logic are now increasingly used for ana-

    E-print Network

    McNeill, John A.

    that provide a system development ap- proach for mixed signal circuitry on digital CMOS processes. Index TermsPage: 1 Abstract - CMOS processes that have been developed primarily for logic are now increasingly - Mixed analog-digital design, MOS inte- grated circuits, CMOS analog integrated circuits, an- alog

  12. Differential Mode CMOS Active Pixel Sensor (APS) for Optically Programmable Gate Array (OPGA)

    E-print Network

    Fossum, Eric R.

    1 Differential Mode CMOS Active Pixel Sensor (APS) for Optically Programmable Gate Array (OPGA@photobit.com Abstract A differential mode CMOS active pixel sensor (APS) was designed, fabricated, and tested as part.35 m standard CMOS process technology. I. Introduction Field programmable gate arrays (FPGA) are widely

  13. Variability-Aware Optimization of Nano-CMOS Active Pixel Sensors

    E-print Network

    Mohanty, Saraju P.

    of nanoscale CMOS Active Pixel Sensor (APS) arrays is proposed. For case study, 32 nm 8 × 8 APS array of APS for post-nano-CMOS, such as high-/metal gate, Carbon Nanotube, and Dual-Gate FETs. 3/6/2009 2 #12 of nanoscale CMOS Active Pixel Sensor (APS) arrays is proposed. For case study, 32nm 8 × 8 APS array

  14. CMOS APS crosstalk characterization via a unique Sub-micron Scanning System

    E-print Network

    CMOS APS crosstalk characterization via a unique Sub-micron Scanning System Igor Shcherback, Orly introduces a novel way for CMOS APS crosstalk (CTK) determination and prediction based on our unique Sub out that CMOS APS crosstalk is mostly affected by the specific pixel architecture and the pixels

  15. Analysis of Temporal Noise in CMOS APS Hui Tian, Boyd Fowler, and Abbas El Gamal

    E-print Network

    El Gamal, Abbas

    Analysis of Temporal Noise in CMOS APS Hui Tian, Boyd Fowler, and Abbas El Gamal Information shot noise and the thermal and 1/f noise of the output charge to voltage amplifier. In a CMOS APS of the APS charge to voltage characteristics, which is becoming more pronounced as CMOS technology scales

  16. Active Pixel Sensors Fabricated in a Standard 0.18 urn CMOS Technology

    E-print Network

    El Gamal, Abbas

    is not significantly affected by this problem, however. Keywords: CMOS APS, image sensor, dark current, quantumActive Pixel Sensors Fabricated in a Standard 0.18 urn CMOS Technology Hui Tian, Xinqiao Liu, Suk Stanford, CA 94305 USA ABSTRACT CMOS image sensors have benefited from technology scaling down to O.351um

  17. Biomimetic Sampling Architectures for CMOS Image Sensors Fayal Saffih*a

    E-print Network

    Hornsey, Richard

    . INTRODUCTION The relatively recent development of CMOS active pixel sensors (APS) has permitted largeBiomimetic Sampling Architectures for CMOS Image Sensors Fayēal Saffih*a and Richard Hornseyb-orthogonal architecture for a CMOS active pixel image sensor, called here pyramid architecture, for improved two

  18. Radiation-induced dark signal in 0.5-um CMOS APS image sensors

    Microsoft Academic Search

    El-Sayed I. Eid; Richard H. Tsai; Eric R. Fossum; Robert Spagnuolo; John J. Deily; Hal Anthony

    2000-01-01

    A CMOS APS image sensor test chip, which was designed employing the physical design techniques of enclosed geometry and guard rings and fabricated in a 0.5-micrometers CMOS process, underwent a Co60 (gamma) -ray irradiation experiment. The experiment demonstrated that implementing the physical design techniques of enclosed geometry and guard rings in CMOS APS image sensors is possible. It verified that

  19. Human Perception of Fixed Pattern Noise in Pyramidal CMOS Image Sensor

    E-print Network

    Hornsey, Richard

    -performance CMOS active pixel sensors (APS) image sensor are attracting more and more interest thanksHuman Perception of Fixed Pattern Noise in Pyramidal CMOS Image Sensor Fayēal Saffih*a , Richard I Street, Toronto, ON, CANADA M3J 1P3 ABSTRACT We demonstrate a non-orthogonal architecture for a CMOS

  20. Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology

    E-print Network

    Fossum, Eric R.

    using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detectorLow Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology Eric R. Fossum Center using a highly specialized fabrication process that is not generally CMOS compatible. Separate support

  1. Analysis of 1/f noise in CMOS APS Hui Tian, and Abbas El Gamal

    E-print Network

    El Gamal, Abbas

    Analysis of 1/f noise in CMOS APS Hui Tian, and Abbas El Gamal Information Systems Laboratory is used to analyze the effect of 1/f noise due to pixel level transistors in a CMOS APS. The results show noise, subthreshold operation, nonstationary 1/f noise model, time domain noise analysis, CMOS APS

  2. ILP Based Leakage Optimization During Nano-CMOS RTL Synthesis: A DOXCMOS Versus DTCMOS Perspective

    E-print Network

    Mohanty, Saraju P.

    ILP Based Leakage Optimization During Nano-CMOS RTL Synthesis: A DOXCMOS Versus DTCMOS Perspective Indian Institute of Technology, New Delhi - 110016, India. Email: bkpanigrahi@ee.iitd.ac.in Abstract) library. For nanoscale CMOS (nano-CMOS) circuits leakage is a predom- inate form of power dissipation

  3. Simultaneous Scheduling and Binding for Low Gate Leakage Nano-CMOS Datapath Circuit Behavioral Synthesis

    E-print Network

    Mohanty, Saraju P.

    Terms Nano-CMOS, Gate-Oxide Leakage, Direct Tunneling, Multiple-Tox Technology, Low Power Synthesis I component for low-end nano-CMOS technology of 65nm and below. Thus, the major sources of power dissipation1 Simultaneous Scheduling and Binding for Low Gate Leakage Nano-CMOS Datapath Circuit Behavioral

  4. Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits

    E-print Network

    Mohanty, Saraju P.

    : smohanty@cs.unt.edu Email: eliask@unt.edu Abstract-- For a nanoCMOS of sub-65nm technology, where the gate for low-end nanoCMOS technology (i. e. sub-65nm) using ultra-thin gate oxide [4], [2], [5]. ThusModeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits Saraju P

  5. Asynchronous Logic for High Variability NanoCMOS Alain J. Martin

    E-print Network

    Martin, Alain

    of digital circuits in nano CMOS or other emerging technologies. This paper examines the robustness of one variations. INTRODUCTION All future technologies, nano­CMOS as well as potential emerging technologies likeAsynchronous Logic for High Variability Nano­CMOS Alain J. Martin California Institute

  6. A PVT Aware Accurate Statistical Logic Library for High-Metal-Gate Nano-CMOS

    E-print Network

    Mohanty, Saraju P.

    A PVT Aware Accurate Statistical Logic Library for High- Metal-Gate Nano-CMOS Dhruva Ghai1 , Saraju character- ization for high- metal-gate nano-CMOS based logic gates. Keywords Nanoscale CMOS, High- metal-gate technology, Monte Carlo, Gate Induced Drain Leakage (GIDL), Subthreshold Leakage, Dynamic Power 1

  7. A Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization

    E-print Network

    Mohanty, Saraju P.

    . In the context of nano-CMOS technology, the challenges for design engineers have significantly increased dueA Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization Shibaji Banerjee1 for Nano-CMOS RTL Leakage Optimization Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K

  8. Architecture and Performance Evaluation of 3D CMOS-NEM FPGA

    E-print Network

    Chen, Deming

    Architecture and Performance Evaluation of 3D CMOS-NEM FPGA Chen Dong*, Chen Chen+, Subhasish Mitra In this paper, we introduce a reconfigurable architecture, named 3D CMOS-NEM FPGA, which utilizes include: hybrid CMOS-NEM FPGA look-up tables (LUTs) and configurable logic blocks (CLBs), NEM-based switch

  9. Figures of merit for CMOS SPADs and arrays

    NASA Astrophysics Data System (ADS)

    Bronzi, D.; Villa, F.; Bellisai, S.; Tisa, S.; Ripamonti, G.; Tosi, A.

    2013-05-01

    SPADs (Single Photon Avalanche Diodes) are emerging as most suitable photodetectors for both single-photon counting (Fluorescence Correlation Spectroscopy, Lock-in 3D Ranging) and single-photon timing (Lidar, Fluorescence Lifetime Imaging, Diffuse Optical Imaging) applications. Different complementary metal-oxide semiconductor (CMOS) implementations have been reported in literature. We present some figure of merit able to summarize the typical SPAD performances (i.e. Dark Counting Rate, Photo Detection Efficiency, afterpulsing probability, hold-off time, timing jitter) and to identify a proper metric for SPAD comparison, both as single detectors and also as imaging arrays. The goal is to define a practical framework within which it is possible to rank detectors based on their performances in specific experimental conditions, for either photon-counting or photon-timing applications. Furthermore we review the performances of some CMOS and custom-made SPADs. Results show that CMOS SPADs performances improve as the technology scales down; moreover, miniaturization of SPADs and new solutions adopted to counteract issues related with the SPAD design (electric field uniformity, premature edge breakdown, tunneling effects, defect-rich STI interface) along with advances in standard CMOS processes led to a general improvement in all fabricated photodetectors; therefore, CMOS SPADs can be suitable for very dense and cost-effective many-pixels imagers with high performances.

  10. NSC 800, 8-bit CMOS microprocessor

    NASA Technical Reports Server (NTRS)

    Suszko, S. F.

    1984-01-01

    The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

  11. IEEE TRANSACTIONS ON NUCLEAR SCIENCE. VOL. 43. NO.3. JUNE 19'16 CMOS Charged Particle Spectrometers

    E-print Network

    Fossum, Eric R.

    region. Space Technology Research Vehicle-2 (STRV·2) APS CMOS prawn and electron spectrometer design the numher of cell upsets. III. CMOS APS SPECTROMETER DESIGN Current CMOS chip spectrometer designs are both fahricated in 1.2 !J-II1 n-well technology through MOS Implementation System (MOSIS). The CMOS APS

  12. Point by Point Thorough Photoresponse Analysis of CMOS APS by means of our Unique Sub-micron Scanning System

    E-print Network

    Point by Point Thorough Photoresponse Analysis of CMOS APS by means of our Unique Sub pixel topologies of CMOS APS chips fabricated in two different CMOS technologies (the standard 0.5µm.g., logic transistors, metal lines, etc.) which is extremely important for CMOS APS where the pixel

  13. 1764 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 10, OCTOBER 1997 Frame-Transfer CMOS Active

    E-print Network

    Fossum, Eric R.

    , and Eric R. Fossum, Senior Member, IEEE Abstract--The first frame-transfer CMOS active pixel sensor (APS.2-m CMOS and demonstrated. I. INTRODUCTION THE CMOS active pixel image sensor (APS) has permitted for passive pixels [6], in CMOS APS by a slight change in timing [7], and in more complex compression

  14. Design Techniques for Gate-Leakage Reduction in CMOS Circuits Rafik S. Guindi and Farid N. Najm

    E-print Network

    Najm, Farid N.

    -negligible component with a potential impact on circuit operation and performance. With CMOS technology ap- proachingDesign Techniques for Gate-Leakage Reduction in CMOS Circuits Rafik S. Guindi and Farid N. Najm leakage mechanism in sub-100nm CMOS cir- cuits. In this paper, we present an analysis of static CMOS

  15. Design Techniques for GateLeakage Reduction in CMOS Circuits Rafik S. Guindi and Farid N. Najm

    E-print Network

    Najm, Farid N.

    ­negligible component with a potential impact on circuit operation and performance. With CMOS technology ap­ proachingDesign Techniques for Gate­Leakage Reduction in CMOS Circuits Rafik S. Guindi and Farid N. Najm leakage mechanism in sub­100nm CMOS cir­ cuits. In this paper, we present an analysis of static CMOS

  16. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 5, MAY 2003 1233 Analysis of CMOS Photodiodes--Part I

    E-print Network

    Hornsey, Richard

    photodiode arrays. Index Terms--Active pixel sensor (APS), CMOS image sensor, CMOS photodiode, edgeIEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 5, MAY 2003 1233 Analysis of CMOS Photodiodes Abstract--An improved one-dimensional (1-D) analysis of CMOS photodiode has been derived in which

  17. Design of CMOS logic gates for TID radiation

    NASA Technical Reports Server (NTRS)

    Attia, John Okyere; Sasabo, Maria L.

    1993-01-01

    The rise time, fall time and propagation delay of the logic gates were derived. The effects of total ionizing dose (TID) radiation on the fall and rise times of CMOS logic gates were obtained using C program calculations and PSPICE simulations. The variations of mobility and threshold voltage on MOSFET transistors when subjected to TID radiation were used to determine the dependence of switching times on TID. The results of this work indicate that by increasing the size of P-channel transistor with respect to the N-channel transistors of the CMOS gates, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in TID radiation.

  18. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    PubMed Central

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 ?m CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 ?W at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  19. Operation and biasing for single device equivalent to CMOS

    DOEpatents

    Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

    2001-01-01

    Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

  20. Transient radiation hardened CMOS (Complementary Metal Oxide Semiconductor) operational amplifiers

    NASA Astrophysics Data System (ADS)

    Trombley, Gerald J.

    General strategies are developed for designing radiation hardened bulk and silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) operational amplifiers. Comparisons are made between each technology concerning photocurrent mechanisms and the inherent advantages of SOI CMOS. Methods are presented for analyzing circuit designs and minimizing the net photocurrent responses. Analysis is performed on standard operational amplifier circuits and subcircuits to demonstrate the usefulness of these methods. Radiation hardening topics discussed include superior radiation hardened topologies, photocurrent compensation and its limitations, and methods to ensure a preferred direction of photocurrent response. Several operational amplifier subcircuits are compared for their hardness characteristics. Folded cascade and three-stage operational amplifiers were fabricated on an SOI CMOS test chip supported by Texas Instruments, Incorporated. At the time of publication, the circuit operation was verified but radiation data were not yet available.

  1. A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

    NASA Technical Reports Server (NTRS)

    Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

    1993-01-01

    A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

  2. An 8 ns BiCMOS 1 Mb ECL SRAM with a configurable memory array size

    Microsoft Academic Search

    H. Tran; K. Fung; D. Bell; R. Chapman; M. Harward; T. Suzuki; R. Havemann; R. Eklund; R. Fleck; D. Le; C. Wei; N. Iyengar; M. Rodder; R. Haken; D. Scott

    1989-01-01

    A 1-Mb*1 BiCMOS ECL (emitter-coupled-logic) I\\/O SRAM (static random access memory) is fabricated using a 0.8- mu m BiCMOS process. This memory device utilizes a 76- mu m 2 full-CMOS six-transistor memory cell, a dual-MOS current-source BiCMOS bit line sensing scheme, a BiCMOS current-source voltage reference network, and a low-capacitance load block line decoding circuit to achieve 8-ns access time.

  3. High-voltage MOS transistors compatible with CMOS VLSI technology

    NASA Astrophysics Data System (ADS)

    Podmiotko, Wlodzimierz

    1992-08-01

    In this paper high-voltage MOS transistors structures fabricated using a standard CMOS technology and a special design technique are presented. The design, characterization, and modeling of n-MOS, with the breakdown voltage of 50 V, and p-MOS, with the breakdown voltage of 130 V, fabricated using a standard 3 micrometers CMOS process are discussed. In addition, the possibility of high-voltage buffer circuit realization which is composed of n-MOS and p-MOS transistors, operating with the supply system USS equals 0, UDD equals 5 V, UE equals - 40 V, self-isolated from low-voltage components is demonstrated.

  4. Statistical circuit design for yield improvement in CMOS circuits

    NASA Technical Reports Server (NTRS)

    Kamath, H. J.; Purviance, J. E.; Whitaker, S. R.

    1990-01-01

    This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.

  5. Physical insights on nanoscale multi-gate CMOS design

    NASA Astrophysics Data System (ADS)

    Fossum, Jerry G.

    2007-02-01

    Several studies of multi-gate silicon MOSFETs are overviewed to convey physical insights on the (front-end) design of nonclassical nanoscale CMOS. The studies imply that double-gate (DG) FinFETs have mainstream potential, and the suggested device designs are pragmatic and doable. Numerical device simulations and UFDG/Spice3 device/circuit simulations suggest that pragmatic DG-FinFET CMOS can be optimally designed to yield outstanding performances in all applications, with good tradeoffs between speed and power consumption as the gate length is scaled to less than 10 nm.

  6. The latchup risk of CMOS-technology in space

    SciTech Connect

    Moreau, Y.; Rochette, H. de la; Bruguier, G.; Gasiot, J.; Pelanchon, F.; Sudre, C. (Centre d'Electronique, Montpellier (France)); Ecoffet, R. (Centre National d'Etudes Spatiales, Toulouse (France))

    1993-12-01

    The use of CMOS technology in space needs a careful evaluation of the latchup risk. The radiation tolerance is studied here for a standard 1.0 [mu]m high density technology and its hardened variants. The internal currents and densities are read through dynamic two/three dimensional device simulations, performed on a complete description of the CMOS inverter cell and a simulated heavy ion strike. An evaluation of the capture cross section versus the ion energy is derived from the statistical distribution of ion tracks through the structure.

  7. Delay modeling and glitch estimation for CMOS circuits 

    E-print Network

    Shiau, Yan-Chyuan

    1988-01-01

    the timing delay. 15 CHAPTER IV CAPACITANCE MODELING 4. 1 Units Used in Project The timing library I construct is based on the MOSIS CMOS 3prn processing parameters. Some important units are defined as following that will be used in this project: Time... CMOS process and simulate the output response by running SPICE. If we use different tool based on different technologies to calculate timing response, we may get distinct result dued to separate device parameters. 4. 3. 2 Circuit Structure A node...

  8. A statistical MOSFET modeling method for CMOS integrated circuit simulation 

    E-print Network

    Chen, Jian

    1992-01-01

    riw = cir. /(sisr), or X:, ", (z. , ? 22)(x, s ? rs) r1k- (n ? 1)s, ss (2 4) It is clear from equations (2. 3) and (2. 4) that crt = cir, r po = r, s and res = 1. The correlation coefficient approaches 1. 0 (or -1. 0) when a, strong positive (or... PARAMETER VARIATIONS IN CMOS CIR- CIJITS A. IC Simulation and Statistical Model . B. Basic Characterizations of Multivariate Populations C, Parameter Standardization and Scaling D. Transistor Parameter Variations in CMOS Circuits 3 4 6 8 8 8 11...

  9. CMOS sensor as charged particles and ionizing radiation detector

    NASA Astrophysics Data System (ADS)

    Cruz-Zaragoza, E.; Pińa López, I.

    2015-01-01

    This paper reports results of CMOS sensor suitable for use as charged particles and ionizing radiation detector. The CMOS sensor with 640 × 480 pixels area has been integrated into an electronic circuit for detection of ionizing radiation and it was exposed to alpha particle (Am-241, Unat), beta (Sr-90), and gamma photons (Cs-137). Results show after long period of time (168 h) irradiation the sensor had not loss of functionality and also the energy of the charge particles and photons were very well obtained.

  10. Delay modeling and glitch estimation for CMOS circuits

    E-print Network

    Shiau, Yan-Chyuan

    1988-01-01

    DELAY MODELING AND GLITCH ESTIMATION FOR CMOS CIRCUITS A Thesis by YAN-CHYUAN SHIAU Submitted to the Graduate College of Texas A8rM University in partial fulfillment of the requirement for the degree of MASTER OF SCIENCE August 1988 Major... Subject: Electrical Engineering DELAY MODELING AND GLITCH ESTIMATION FOR CMOS CIRCUITS A Thesis by YAN-CHYUAN SHIAU Approved as to style and content by: An-Chang Deng (Chairman of Committee) Karan Watson (Member) I / l j j Stephen M. Morg...

  11. IR CMOS: ultrafast laser-enhanced silicon detection

    NASA Astrophysics Data System (ADS)

    Pralle, M. U.; Carey, J. E.; Homayoon, H.; Sickler, J.; Li, X.; Jiang, J.; Miller, D.; Palsule, C.; McKee, J.

    2011-06-01

    SiOnyx has developed a novel silicon processing technology for CMOS sensors that will extend spectral sensitivity into the near/shortwave infrared (NIR/SWIR) and enable a full performance digital night vision capability comparable to that of current image-intensifier based night vision goggles. The process is compatible with established CMOS manufacturing infrastructure and has the promise of much lower cost than competing approaches. The measured thin layer quantum efficiency is as much as 10x that of incumbent imaging sensors with spectral sensitivity from 400 to 1200 nm.

  12. Black silicon enhanced photodetectors: a path to IR CMOS

    NASA Astrophysics Data System (ADS)

    Pralle, M. U.; Carey, J. E.; Homayoon, H.; Alie, S.; Sickler, J.; Li, X.; Jiang, J.; Miller, D.; Palsule, C.; McKee, J.

    2010-04-01

    SiOnyx has developed a novel silicon processing technology for CMOS sensors that will extend spectral sensitivity into the near/shortwave infrared (NIR/SWIR) and enable a full performance digital night vision capability comparable to that of current image-intensifier based night vision goggles. The process is compatible with established CMOS manufacturing infrastructure and has the promise of much lower cost than competing approaches. The measured thin layer quantum efficiency is as much as 10x that of incumbent imaging sensors with spectral sensitivity from 400 to 1200 nm.

  13. IR CMOS: ultrafast laser-enhanced silicon imaging

    NASA Astrophysics Data System (ADS)

    Pralle, M. U.; Carey, J. E.; Homayoon, H.; Sickler, J.; Li, X.; Jiang, J.; Hong, C.; Sahebi, F.; Palsule, C.; McKee, J.

    2012-06-01

    SiOnyx has developed a CMOS image sensor with enhanced infrared sensitivity. The technology deployed in this remarkable device is based on SiOnyx's proprietary ultrafast laser semiconductor process. We have established a high volume manufacturing process while maintaining complete compatibility with standard CMOS image sensor process flows. The enhanced performance proves the viability of a highly scalable low cost digital infrared sensor. The spectral sensitivity is from 400 to 1200 nm with measured quantum efficiency improvements of more than 3x at 940 nm.

  14. A very high frequency CMOS Variable Gain Amplifier

    E-print Network

    Tan, Siang Tong

    2001-01-01

    A VERY HIGH FREQUENCY CMOS VARIABLE GAIN AMPLIFIER A Thesis by SIANG TONG TAN Submitted to the Office of Graduate Studies of Texas AgrM University in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE December 2001... of an analog multiplier, current gain stages, and resistor loads is designed for very high frequency applications. The gain can be programmed from OdB to 40dB with -3dB bandwidth greater than 200MHz and 500MHz in 0. 5ltm and 0. 35pm CMOS process...

  15. Radiation tolerant back biased CMOS VLSI

    NASA Technical Reports Server (NTRS)

    Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

    2003-01-01

    A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

  16. CMOS optoelectronic database filter: implementation and analysis

    NASA Astrophysics Data System (ADS)

    Tang, Jianjing; Pattanayak, Arunansu; Beyette, Fred R., Jr.

    2003-12-01

    Optical storage devices are being used to meet the growing demand for high capacity archival data storage. A challenging task facing the designers for the next generation of archival storage system is to provide storage capacities several orders of magnitude larger than existing systems while maintaining current data access times. To meet this challenge, we have developed a smart optoelectronic database filter suitable for large capacity relational database systems that use page-oriented optical storage devices. The photonic VLSI chip monolithically integrates a smart-pixel array that incorporates page-oriented optical reading, data manipulation logic, data buffering and filter control circuitry for interfacing the filter chip with an electronic host computer. By selectively passing only the data requested by the query operation, the database filter is able to accomplish the reduction in data rate without loss of valid data or significant delay in data access. The design, testing and performance evaluation of a 32x32-bit database filter fabricated in a 0.35-micron CMOS process is reported. In addition to demonstrating the first fully functioning database filter chip, we present a program that has been developed to simulate the filtering algorithm implemented by the hardware. Queuing theory has been used to perform the system level analysis of the database filter. It is shown that even with the limitation of finite queue capacity, a database filter chip could be controlled to work at near optimal performance where database search time is limited by the data transfer rate going into the host computer. The simulation program has been used to verify the validity of the queuing analysis.

  17. Low back-reflection CMOS-compatible grating coupler for perfectly vertical coupling

    NASA Astrophysics Data System (ADS)

    Dabos, G.; Pleros, N.; Tsiokos, D.

    2015-02-01

    In view of high volume manufacturing of silicon based photonic-integrated-circuits (Si-PICs), CMOS compatible low-cost fabrication processes as well as simplified packaging methods are imperatively needed. Silicon-onInsulator (SOI) based grating couplers (GCs) have attracted attention as the key components for providing optical interfaces to Si-PICs due their fabrication simplicity compared to the edge coupling alternatives. GCs based on perfectly vertical coupling scheme become essential by introducing substantial savings in the packaging cost as no angular configurations are required but at the expense of high coupling efficiency values due to the second order diffraction. In this context, research efforts concentrated on designing GCs with minimized back reflection into the waveguide yet employing more than one etching steps or rather complex fabrication processes. Herein, we propose a fully etched CMOS compatible non-uniform one-dimensional (1D) GC for perfectly vertical coupling with low back reflected optical power by means of numerical simulations. A particle-swarm-optimization (PSO) algorithm was deployed in conjunction with a commercially available 2D finite-difference-time-domain (FDTD) method to maximize the coupling efficiency to a SMF fiber for TM polarization. The design parameters were restricted to the period length and the filling factor while the minimum feature size was 80 nm. A peak coupling loss of 4.4 dB at 1553 nm was achieved with a 1-dB bandwidth of 47 nm and a back reflection of -20 dB. The coupling tolerance to fabrication errors was also investigated.

  18. Performance of PHOTONIS' low light level CMOS imaging sensor for long range observation

    NASA Astrophysics Data System (ADS)

    Bourree, Loig E.

    2014-05-01

    Identification of potential threats in low-light conditions through imaging is commonly achieved through closed-circuit television (CCTV) and surveillance cameras by combining the extended near infrared (NIR) response (800-10000nm wavelengths) of the imaging sensor with NIR LED or laser illuminators. Consequently, camera systems typically used for purposes of long-range observation often require high-power lasers in order to generate sufficient photons on targets to acquire detailed images at night. While these systems may adequately identify targets at long-range, the NIR illumination needed to achieve such functionality can easily be detected and therefore may not be suitable for covert applications. In order to reduce dependency on supplemental illumination in low-light conditions, the frame rate of the imaging sensors may be reduced to increase the photon integration time and thus improve the signal to noise ratio of the image. However, this may hinder the camera's ability to image moving objects with high fidelity. In order to address these particular drawbacks, PHOTONIS has developed a CMOS imaging sensor (CIS) with a pixel architecture and geometry designed specifically to overcome these issues in low-light level imaging. By combining this CIS with field programmable gate array (FPGA)-based image processing electronics, PHOTONIS has achieved low-read noise imaging with enhanced signal-to-noise ratio at quarter moon illumination, all at standard video frame rates. The performance of this CIS is discussed herein and compared to other commercially available CMOS and CCD for long-range observation applications.

  19. X-ray imaging and spectroscopy using low cost COTS CMOS sensors

    NASA Astrophysics Data System (ADS)

    Lane, David W.

    2012-08-01

    Whilst commercial X-ray sensor arrays are capable of both imaging and spectroscopy they are currently expensive and this can limit their widespread use. This study examines the use of very low cost CMOS sensors for X-ray imaging and spectroscopy based on the commercial off the shelf (COTS) technology used in cellular telephones, PC multimedia and children's toys. Some examples of imaging using a 'webcam' and a modified OmniVision OV7411 sensor are presented, as well as a simple energy dispersive X-ray detector based on an OmniVision OV7221 sensor. In each case X-ray sensitivity was enabled by replacing the sensor's front glass window with a 5 ?m thick aluminium foil, with X-rays detected as an increase in a pixel's dark current due to the generation of additional electron-hole pairs within its active region. The exposure control and data processing requirements for imaging and spectroscopy are discussed. The modified OV7221 sensor was found to have a linear X-ray energy calibration and a resolution of approximately 510 eV.

  20. Radiation-hard active CMOS pixel sensors for HL-LHC detector upgrades

    NASA Astrophysics Data System (ADS)

    Backhaus, Malte

    2015-02-01

    The luminosity of the Large Hadron Collider (LHC) will be increased during the Long Shutdown of 2022 and 2023 (LS3) in order to increase the sensitivity of its experiments. A completely new inner detector for the ATLAS experiment needs to be developed to withstand the extremely harsh environment of the upgraded, so-called High-Luminosity LHC (HL-LHC). High radiation hardness as well as granularity is mandatory to cope with the requirements in terms of radiation damage as well as particle occupancy. A new silicon detector concept that uses commercial high voltage and/or high resistivity full complementary metal-oxide-semiconductor (CMOS) processes as active sensor for pixel and/or strip layers has risen high attention, because it potentially provides high radiation hardness and granularity and at the same time reduced price due to the commercial processing and possibly relaxed requirements for the hybridization technique. Results on the first prototypes characterized in a variety of laboratory as well as test beam environments are presented.

  1. Implantable CMOS imaging devices for bio-medical applications

    Microsoft Academic Search

    Jun Ohta

    2011-01-01

    This paper reviews recent results for implantable CMOS imaging devices applied to biomedical applications. The topics include retinal prosthesis devices and deep-brain implantation devices for small animals. Device structures and their characteristics are described, and the results of in vivo experiments are demonstrated.

  2. A 77GHz monolithic IMPATT transmitter in standard CMOS technology

    Microsoft Academic Search

    Talal Al-Attar; Arjang Hassibi; Thomas H. Lee

    2005-01-01

    In this paper, a fully integrated transmitter at 77GHz is presented in a 0.18?m standard CMOS technology. The system consists of a lateral IMPATT diode and a microstrip patch antenna. The antenna impedance seen by the IMPATT diode is optimized using the high frequency electromagnetic (EM) field solver, Sonnet, which is matched to the measured impedance of the diode. The

  3. Simulation toolkit with CMOS detector in the framework of hadrontherapy

    NASA Astrophysics Data System (ADS)

    Rescigno, R.; Finck, Ch.; Juliani, D.; Baudot, J.; Dauvergne, D.; Dedes, G.; Krimmer, J.; Ray, C.; Reithinger, V.; Rousseau, M.; Testa, E.; Winter, M.

    2014-03-01

    Proton imaging can be seen as a powerful technique for on-line monitoring of ion range during carbon ion therapy irradiation. The protons detection technique uses, as three-dimensional tracking system, a set of CMOS sensor planes. A simulation toolkit based on GEANT4 and ROOT is presented including detector response and reconstruction algorithm.

  4. CMOS Four-Port Direct Conversion Receiver for BPSK Demodulation

    Microsoft Academic Search

    Seong-Mo Moon; Jong-Won Yu; Moon-Que Lee

    2009-01-01

    We propose a new four-port BPSK direct conversion receiver based on 0.18 ??m CMOS technology for the first time. The proposed direct conversion receiver is composed of two active combiners, an active balun, two power detectors and a decoder. The designed direct conversion receiver is successfully demonstrated by demodulating BPSK signal with 40 Mbps in the L-band.

  5. Soft-Error Hardening Designs of Nanoscale CMOS Latches

    Microsoft Academic Search

    Sheng Lin; Yong-Bin Kim; Fabrizio Lombardi

    2009-01-01

    As technology scales down in the deep sub- micron\\/nano ranges, CMOS circuits are more sensitive to externally induced phenomena to likely cause the occurrence of so-called soft errors. Therefore, the operation of these circuits to tolerate soft errors is a strict requirement in today's designs. Traditional error tolerant methods result in significant cost penalties in terms of power, area and

  6. Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks

    E-print Network

    Larrabee, Tracy

    into two categories: those that physically disconnect one or more transistor gates from their drivers, and those that disconnect transistors from each other in the pĀ­network or nĀ­network of a CMOS cell [12]. We or more transistor paths between the cell output and Vdd or GND. A transistor path is a sequence

  7. Test Considerations for Gate Oxide Shorts in CMOS ICs

    Microsoft Academic Search

    Jerry M. Soden; Charles Hawkins

    1986-01-01

    Gate oxide shorts are defects that must be detected to produce high-reliability ICs. These problems will continue as devices are scaled down and oxide thicknesses are reduced to the 100-?? range. Complete detection of gate oxide shorts and other CMOS failure mechanisms requires measuring the IDD current during the quiescent state after each test vector is applied to the IC.

  8. Defect classes-an overdue paradigm for CMOS IC testing

    Microsoft Academic Search

    Charles F. Hawkins; Jerry M. Soden; A. W. Righter; F. Joel Fergusonti

    1994-01-01

    The IC test industry has struggled for move than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the rest

  9. CCD AND PIN-CMOS DEVELOPMENTS FOR LARGE OPTICAL TELESCOPE.

    SciTech Connect

    RADEKA, V.

    2006-04-03

    Higher quantum efficiency in near-IR, narrower point spread function and higher readout speed than with conventional sensors have been receiving increased emphasis in the development of CCDs and silicon PIN-CMOS sensors for use in large optical telescopes. Some key aspects in the development of such devices are reviewed.

  10. Synchronous coherent extraction of heat [CMOS logic cooling

    Microsoft Academic Search

    V. Guruprasad

    1998-01-01

    This paper describes embedded techniques for cooling clocked CMOS circuits by converting the primary phonons excited by the switching currents to electricity. The intent is to extract the energy as coherently as possible before it disperses into the bulk lattice and becomes heat at a lower average temperature. The first method is a heat engine, using the bulk lattice as

  11. Quantification of Shallow-junction Dopant Loss during CMOS Process

    SciTech Connect

    Buh, G.H.; Park, T.; Jee, Y.; Hong, S.J.; Ryoo, C.; Yoo, J.; Lee, J.W.; Yon, G.H.; Jun, C.S.; Shin, Y.G.; Chung, U.-In; Moon, J.T. [Semiconductor R and D Center, Samsung Electronics Co., Ltd., Yongin-City, Gyeonggi-Do, 449-711 (Korea, Republic of)

    2005-09-09

    We analyzed dopant concentration and profiles in source drain extension (SDE) by using in-line low energy electron induced x-ray emission spectrometry (LEXES), four point probe (FPP), and secondary ion mass spectroscopy (SIMS). By monitoring the dopant dose with LEXES, dopant loss in implantation and annealing process was successfully quantified. To measure the actual SDE sheet resistance in CMOS device structure without probe penetration in FPP, we fabricated a simple SDE sheet-resistance test structure (SSTS) by modifying a conventional CMOS process. It was found that the sheet resistances determined with SSTS are larger than those measured with FPP. There are three mechanisms of dopants loss in CMOS process: 1) wet-etching removal during photo resist cleaning, 2) out-diffusion, and 3) deactivation by post-thermal process. We quantified the loss of the dopant in SDE during the CMOS process, and found that the wet-etching removal and out-diffusion are the most significant causes for dopant loss in n-SDE and p-SDE, respectively.

  12. CMOS three axis Hall sensor and joystick application

    Microsoft Academic Search

    Christian Schott; Robert Racz; Samuel Huber

    2004-01-01

    We present for the first time a three-axis CMOS Hall sensor based on integrated magnetic concentrator technology (IMC). The sensor measures the two in-plane magnetic field components Bx and By and the vertical component Bz and generates three output voltages proportional to them. The sensing core consists of four Hall elements arranged at 90° under the edge of a ferromagnetic

  13. Device and Architecture Outlook for Beyond CMOS Switches

    Microsoft Academic Search

    Kerry Bernstein; Ralph K. Cavin; Wolfgang Porod; Alan Seabaugh; Jeff Welser

    2010-01-01

    Sooner or later, fundamental limitations destine complementary metal-oxide-semiconductor (CMOS) scaling to a conclusion. A number of unique switches have been proposed as replacements, many of which do not even use electron charge as the state variable. Instead, these nanoscale structures pass tokens in the spin, excitonic, photonic, magnetic, quantum, or even heat domains. Emergent physical behaviors and idiosyncrasies of these

  14. The method for integrating FBAR with circuitry on CMOS chip

    Microsoft Academic Search

    Po-Hsun Sung; Chi-Ming Fang; Pei-Zen Chang; Yung-Chung Chin; Pei-Yen Chen

    2004-01-01

    A method is described to integrate a 3×2 ladder type film bulk acoustic wave (FBAR) filter on a CMOS chip. The modified Mason equivalent circuit model is used to simulate the FBAR characteristics. The filter is designed by the insertion loss method to meet the requirements. A low noise amplifier (LNA) has been designed and manufactured by the UMC 0.18

  15. Effect of a polywell leometry on a CMOS photodiode array

    Microsoft Academic Search

    Paul V. Jansz; Steven Hinckley; Graham Wild

    2010-01-01

    The effect of a polywell geometry hybridized with a stacked gradient poly-homojunction architecture, on the response of a CMOs compatible photodiode array was simulated. Crosstalk and sensitivity improved compared to the polywell geometry alone, for both back and front illumination.

  16. Effect of a Polywell geometry on a CMOS Photodiode Array

    Microsoft Academic Search

    Paul V Jansz; Steven Hinckley; Graham Wild

    2010-01-01

    The effect of a polywell geometry hybridized with a stacked gradient poly-homojunction architecture, on the response of a CMOs compatible photodiode array was simulated. Crosstalk and sensitivity improved compared to the polywell geometry alone, for both back and front illumination

  17. Effects Of Dose Rates On Radiation Damage In CMOS Parts

    NASA Technical Reports Server (NTRS)

    Goben, Charles A.; Coss, James R.; Price, William E.

    1990-01-01

    Report describes measurements of effects of ionizing-radiation dose rate on consequent damage to complementary metal oxide/semiconductor (CMOS) electronic devices. Depending on irradiation time and degree of annealing, survivability of devices in outer space, or after explosion of nuclear weapons, enhanced. Annealing involving recovery beyond pre-irradiation conditions (rebound) detrimental. Damage more severe at lower dose rates.

  18. Fast scientific computation in CMOS VLSI shared-memory multiprocessors

    Microsoft Academic Search

    B. K. Bose; P. M. Hansen; C. Lee; D. A. Patterson

    1988-01-01

    The authors present design considerations for fast and efficient scientific computation in CMOS VLSI in general, and shared memory multiprocessors in particular, using SPUR as a case study. Algorithmic and technological tradeoffs for fast floating-point arithmetic are presented, together with design issues in tightly-coupled coprocessor interfaces. SPUR simulations indicate that basic arithmetic operations are three to ten times faster than

  19. CMOS technology characterization for analog and RF design

    Microsoft Academic Search

    Behzad Razavi

    1999-01-01

    The design of analog and radio-frequency (RF) circuits in CMOS technology becomes increasingly more difficult as device modeling faces new challenges in deep submicrometer processes and emerging circuit applications. The sophisticated set of characteristics used to represent today's “digital” technologies often proves inadequate for analog and RF design, mandating many additional measurements and iterations to arrive at an acceptable solution.

  20. RF CMOS mixer design and optimization for wideband CDMA application

    Microsoft Academic Search

    Shenggao Li; Jerusimos Zohios; Jung H. Choi; Mohammed Ismail

    2000-01-01

    This paper presents the design of a Gilbert downconversion mixer for wideband CDMA application. The mixer is designed using a 0.18 ?m 1.5 V\\/3.3 V dual voltage digital CMOS technology. The design methodology is presented to achieve high linearity and low noise figure. A design flow is introduced targeting the automatic design and optimization for mixers

  1. CMOS layout and bias optimization for RF IC design applications

    Microsoft Academic Search

    Cheon Soo Kim; Hyun Kyu Yu; Hanjin Cho; Seonghearn Lee; Kee Soo Nam

    1997-01-01

    High frequency and low noise performance of 0.8 ?m polysilicon gate CMOS device has been analyzed intensively with the various multi-finger polysilicon gate layout and bias to find the optimal condition. From the analysis, the optimal width of unit gate finger and bias condition have been found to maximize fmax and minimize Fmin. At the conditions, Fmin, gain and noise

  2. CMOS VLSI Layout and Verification of a SIMD Computer

    NASA Technical Reports Server (NTRS)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  3. Intensity Histogram CMOS Image Sensor for Adaptive Optics

    E-print Network

    Cauwenberghs, Gert

    Intensity Histogram CMOS Image Sensor for Adaptive Optics Yu M. Chi, Gary Carhart , Mikhail A imaging mode and 4.6mW in high-speed histogram mode. Applications include real-time adaptive optics control for laser communications. I. INTRODUCTION Adaptive optical systems are highly useful

  4. CMOS Active-Pixel Image Sensor With Simple Floating Gates

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

    1996-01-01

    Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

  5. 3D CMOL based on CMOS\\/nanomaterial hybrid technology

    Microsoft Academic Search

    Deyu Tu; Ming Liu; Sansiri Haruehanroengra; Wei Wang

    2007-01-01

    CMOS molecular (CMOL) circuits promise great opportunities for future hybrid nanoscale IC implementation. In this paper, a novel three dimension (3D) architecture of CMOL circuit is introduced. It eliminates the special pin requirement, enabling feasible fabrication. It also doubles the density of nanowires of the original CMOL circuit, while providing similar operation performance. This work significantly advances applications of 3D

  6. Conformational Molecular Switches for Post-CMOS Nanoelectronics

    Microsoft Academic Search

    Alain E. Kaloyeros; Mircea R. Stan; Barry Arkles; Robert Geer; Eric T. Eisenbraun; James E. Raynolds; Anand Gadre; James Ryan

    2007-01-01

    Theoretical treatments forecast that bistable CMOS devices using electronic charge as a state variable will operate at their maximum thermal dissipation limit possibly as early as 2012. The problem is further compounded by increasing manufacturing challenges associated with the ever decreasing logic switch dimensions. These challenges require the development of new fabrication strategies that replace or complement current top-down lithography

  7. Single Event Upset Behavior of CMOS Static RAM Cells

    NASA Technical Reports Server (NTRS)

    Lieneweg, Udo; Jeppson, Kjell O.; Buehler, Martin G.

    1993-01-01

    An improved state-space analysis of the CMOS static RAM cell is presented. Introducing theconcept of the dividing line, the critical charge for heavy-ion-induced upset of memory cells can becalculated considering symmetrical as well as asymmetrical capacitive loads. From the criticalcharge, the upset-rate per bit-day for static RAMs can be estimated.

  8. Autoclave testing of plastic encapsulated 4001 CMOS integrated circuits

    Microsoft Academic Search

    R. Holecinski

    1980-01-01

    Samples from 10 vendors of CMOS 4001 plastic encapsulated integrated circuits were tested in an autoclave at 121 C, 100% RH and 15 psig with and without electrical bias. Twenty-nine test groups of 16 circuits each accumulated over 200,000 device hours. Failure analyses were performed to verify moisture related electrochemical aluminum metal corrosion on the die. Weibull failure distributions showed

  9. High-speed wavefront sensor compatible with standard CMOS technology

    Microsoft Academic Search

    D. W. de Lima Monteiro; G. Vdovin; P. M. Sarro

    2004-01-01

    This paper addresses the design, implementation and performance of an integrated Hartmann (–Shack) wavefront sensor suitable for real-time operation and compatible with standard CMOS technology.A wavefront sensor can be used to detect distortions in the profile of a light beam or indirectly in that of an optical component. Such a sensor can also be coupled to a deformable mirror to

  10. Analysis of pixel circuits in CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Mei, Zou; Chen, Nan; Yao, Li-bin

    2015-04-01

    CMOS image sensors (CIS) have lower power consumption, lower cost and smaller size than CCD image sensors. However, generally CCDs have higher performance than CIS mainly due to lower noise. The pixel circuit used in CIS is the first part of the signal processing circuit and connected to photodiode directly, so its performance will greatly affect the CIS or even the whole imaging system. To achieve high performance, CMOS image sensors need advanced pixel circuits. There are many pixel circuits used in CIS, such as passive pixel sensor (PPS), 3T and 4T active pixel sensor (APS), capacitive transimpedance amplifier (CTIA), and passive pixel sensor (PPS). At first, the main performance parameters of each pixel structure including the noise, injection efficiency, sensitivity, power consumption, and stability of bias voltage are analyzed. Through the theoretical analysis of those pixel circuits, it is concluded that CTIA pixel circuit has good noise performance, high injection efficiency, stable photodiode bias, and high sensitivity with small integrator capacitor. Furthermore, the APS and CTIA pixel circuits are simulated in a standard 0.18-?m CMOS process and using a n-well/p-sub photodiode by SPICE and the simulation result confirms the theoretical analysis result. It shows the possibility that CMOS image sensors can be extended to a wide range of applications requiring high performance.

  11. Development of RF CMOS receiver front-ends for ultrawideband 

    E-print Network

    Guan, Xin

    2009-05-15

    measurement result of 7.2dB gain, 4.2-6dB noise figure, and less than -10dB return loss through 0-11GHz. A new distributed amplifier implementing cascade common source gain cells is presented in 0.18-?m CMOS. The new amplifier demonstrates a high gain of 16d...

  12. A very high frequency CMOS Variable Gain Amplifier 

    E-print Network

    Tan, Siang Tong

    2001-01-01

    A fully differential CMOS Variable Gain Amplifier (VGA) consisting of an analog multiplier, current gain stages, and resistor loads is designed for very high frequency applications. The gain can be programmed from 0dB to 40dB with -3dB bandwidth...

  13. Embedded CMOS imaging system for real-time robotic vision

    Microsoft Academic Search

    Henrry Andrian; Kai-Tai Song

    2005-01-01

    This paper presents a real-time robotic vision system that provides visual information for a control scheme of mobile manipulation. The hardware implementation consists of a CMOS image board and a TI DSP board which uses C6416 as the main processor. The merits of using these two boards are the construction of a low cost embedded platform with high performance. Meanwhile

  14. Analog CMOS synaptic learning circuits adapted from invertebrate biology

    Microsoft Academic Search

    Christian Schneider; Howard Card

    1991-01-01

    Analog CMOS circuits implementing abstractions of certain biological synaptic processes are presented. In particular, the circuits extract features of synaptic learning observed in the marine mollusk Aplysia. Two types of nonassociative learning, habituation and sensitization, as well as associative learning (classical conditioning), are modeled. The synaptic learning rules used by Aplysia are considerably more complex than those typically used in

  15. Technology portable delay model for DSM CMOS inverters

    Microsoft Academic Search

    A. Kabbani; D. Al-Khalili; A. J. Al-Khalili

    2004-01-01

    A closed form expression to accurately estimate the delay of a CMOS deep submicron (DSM) inverter is presented in this paper. This model does not depend on any extracted or fitting parameters. Instead it depends on the device model parameters. This model exhibits a good accuracy when compared with Spectre simulations using BSIM3v3 model, for a wide range of device

  16. Analytic nonlinear model for harmonics analysis in CMOS inverters

    Microsoft Academic Search

    Cheng-Kuang Liu

    1998-01-01

    An analytic nonlinear model is proposed for analyzing the frequency response of digital circuits. Applying a Volterra series expansion method, we have developed analytic nonlinear Fourier transfer functions for a CMOS inverter. Comparison between our calculations and a SPICE simulation, its application to study the effects of device models on circuit performance, and its expansion in complex digital modules are

  17. A model for delay evaluation of a CMOS inverter

    Microsoft Academic Search

    S. R. Vemuru; A. R. Thorbjornsen

    1990-01-01

    A model is proposed for computing the propagation delay of a CMOS inverter. The model takes into account the shape of the input waveform, the capacitive load, and the transconductances of the PMOS and NMOS transistors. The model uses either an analytical solution or a power series approximate solution for the differential equations that govern the behavior of the inverter.

  18. CMOS inverter current and delay model incorporating interconnect effects

    Microsoft Academic Search

    M. Hafed; N. Rumin

    1998-01-01

    We present a new model for predicting the switching current and delay in a CMOS inverter with an RC load. The model exploits the ability of an inverter model to predict accurately the current peak time, tm, as a function of inverter size, input slope and capacitive load. An iterative procedure computes the effective capacitance presented by the RC load,

  19. Testing for bridging faults (shorts) in CMOS circuits

    Microsoft Academic Search

    John M. Acken

    1983-01-01

    The stuck-at fault model, which is commonly used with fault simulation, does not adequately evaluate the effects of bridging faults (shorts between adjacent signal lines) in CMOS circuits. Tests for bridging faults can be performed on automatic test equipment, and the test vectors can be evaluated using logic simulation.

  20. Simulation and reduction of CMOS power dissipation at logic level

    Microsoft Academic Search

    F. Dresig; P. Lanches; O. Rettig; U. G. Baitinger

    1993-01-01

    A logic simulation approach suitable to get information about the dissipated power of a system without the need of a specific current simulation is described. With this approach it is possible to retrieve estimations for average power dissipation under typical operating conditions. Furthermore a mapping approach which performs a power-minimal mapping for a given CMOS combinational circuit structure is suggested

  1. Latchup-free CMOS structure using shallow trench isolation

    Microsoft Academic Search

    Y. Niitsu; S. Taguchi; K. Shibata; H. Fuji; Y. Shimamune; H. Iwai; K. Kanzaki

    1985-01-01

    Using a shallow trench and a thin epitaxial layer, latchup-free CMOS has been realized. When the trench depth is 1.4 µm and the epitaxial layer thickness is 2 µm, the latchup holding voltage, VHis higher than 13 V. The mechanism of VHincrease is discussed using an equivalent circuit including the reverse transistors of the parasitic bipolar transistors. The interruption of

  2. BI-CMOS TRACKING SERVO LSI FOR 8 mm VCR

    Microsoft Academic Search

    Satoshi Mizoguchi; Yasuhiro Sugimoto; Minoru Taguchi; Hiroshi Sadamatsu; Tetsuo Hirota; Kiyoshi Nishitani; Yoji Tanii

    2010-01-01

    A tracking servo LSI for 8 mm VCR has been developed by utilizing 3 um high-speed Bipolar CMOS technology. The chip con- tains analog functions such as a low noise amplifier, a gain control amplifier, balanced demodulators, rectifiers, a precision schmit amplifier and a subtrac- ter, mixed analog-digital functions such as switched capacitor filters, sample & hold amplifiers and analog

  3. 2210 Experiment 13 CMOS Logic T. Roppel Nov. 2009 1

    E-print Network

    Niu, Guofu

    as a function of the input voltage over the range of 0 to +5 V. Use the Bit-Bucket variable DC source to provide) does your inverter switch logic levels? (b) What are the output logic level voltages? (c) What logic inverter circuit is shown in Fig. 1. Figure 1. CMOS logic inverter. When MP is on, MN is off

  4. A 24GHz CMOS RF Transceiver for Car Radar Applications

    E-print Network

    Nam, Sangwook

    System Design 2.1 Overall Architecture In FMCW radar system, detection range and minimum detectable incoming interference signal. Also, when array system is adopted to increase detection range, phaseA 24GHz CMOS RF Transceiver for Car Radar Applications # Sungho Lee 1,2 , Kyoungwon Min1

  5. Transversal direct readout CMOS APS with variable shutter mode

    Microsoft Academic Search

    Shigehiro Miyatake; Masaru Miyamoto; Takashi Morimoto; Yasuo Masaki; Hideki Tanabe

    2002-01-01

    A transversal direct readout (TDR) structure for CMOS active pixel image sensors (APSs) eliminates the vertically striped fixed pattern noise. This novel architecture has evolved to incorporate a variable shutter mode as well as simplifying the pixel structure. This paper describes a 320 X 240- pixel TDR APS that not only exhibits neither vertically nor horizontally striped fixed pattern noise,

  6. Autoscaling CMOS APS with customized increase of dynamic range

    Microsoft Academic Search

    Orly Yadid-Pecht; Alexander Belenky

    2001-01-01

    A 64×64 CMOS active pixel sensor uses autoscaling and a floating-point representation to achieve wide dynamic-range linear output. The chip features a new architecture enabling a customized number of additional bits per pixel readout, with minimal effect on the sensor spatial and temporal resolution

  7. CMOS APS imaging system application in star tracker

    Microsoft Academic Search

    Jie Li; Jinguo Liu; Xuekui Li; Yaxia Liu; Zhihang Hao

    2005-01-01

    Small satellites are capable of performing space explore missions that require accurate attitude determination and control. However, low weight, size, power and cost requirements limit the types of attitude sensor of small craft, such as CCD, are not practical for small satellites. CMOS APS is a good substitute for attitude sensors of small craft. Some of the technical advantages of

  8. CMOS APS crosstalk characterization via a unique submicron scanning system

    Microsoft Academic Search

    Igor Shcherback; Orly Yadid-Pecht

    2003-01-01

    This work introduces a novel way for CMOS APS crosstalk (CTK) determination and prediction based on our unique Submicron Scanning System (SSS) measurements. It enables the crosstalk magnitude determination, the tracking of its main causes, and can be used as a predictive tool for design optimization. A pronounced crosstalk asymmetry within the array which was revealed by the measurements is

  9. A Method for Estimating Quantum Efficiency for CMOS Image Sensors

    Microsoft Academic Search

    Boyd Fowler; Abbas El Gamal; David Yang; Hui Tian

    1998-01-01

    The standard method for measuring QE for a CCD sensor is not adequate for CMOS APS since it does not take into consideration the random offset, gain variations, and nonlinearity introduced by the APS readout circuits. The paper presents a new method to accurately estimate QE of an APS. Instead of varying illumination as in the CCD method, illumination is

  10. Low-noise readout using active reset for CMOS APS

    Microsoft Academic Search

    Boyd A. Fowler; Michael D. Godfrey; Janusz Balicki; John Canfield

    2000-01-01

    Pixel reset noise sets the fundamental detection limit on photodiode based CMOS image sensors. Reset noise in standard active pixel sensor (APS) is well understood and is of order kT\\/C. In this paper we present a new technique for resetting photodiodes, called active reset, which reduces reset noise without adding lag. Active reset can be applied to standard APS. Active

  11. A test structure for characterization of CMOS APS

    Microsoft Academic Search

    T. A. Elkhatib; S. Moussa; H. F. Ragaie; H. Haddara

    2003-01-01

    A test structure to characterize CMOS APS image sensor is presented. Individual photodiodes and pixels as well as an image sensor array of 64×64 active pixels with selectable linear or logarithmic operation modes are designed. A test chip includes these features in addition to on-chip timing and control digital circuits as well as correlated double sampling have been built on

  12. Linear bilateral CMOS resistor for neural-type circuits

    Microsoft Academic Search

    L. Sellamit; S. K. Singh; R. W. Newcomb; G. Moon

    1997-01-01

    A previous CMOS bilateral linear resistor is analyzed and shown to be reducible from four to two transistors with improved linearity. This is developed for neural-type circuits to allow its use in emulating both excitatory and inhibitory voltage variable synapses. Simulation results using parameters of MOSIS transistors are presented to verify the theory.

  13. IBM Systems and Technology Electronics IBM CMOS 7HV for

    E-print Network

    to improve effi- ciency, cost per kilowatt and reliability of solar modules IBM CMOS 7HV is the industry, cost per kilowatt and reliability of solar modules. While this research is critical, photovoltaics companies can significantly improve these metrics today by using IBM technology in smart solar- panel

  14. CMOS Active Pixel Sensor Developments at the Rutherford Appleton Laboratory

    Microsoft Academic Search

    Guy Woodhouse; Nicholas Waltham; Marcus French; Mark Prydderch; Quentin Morrissey; Renato Turchetta; Andy Marshall; James King

    This paper reports on an on-going research programme at the Rutherford Appleton Laboratory (RAL) to develop science-grade CMOS Active Pixel Sensors for space science missions in which compactness, low-mass, low-power, and greater radiation tolerance are advantageous.

  15. Radiation Response of High Speed CMOS Integrated Circuits

    Microsoft Academic Search

    H. Yue; D. Davison; R. F. Jennings; P. Lothongkam; D. Rinerson; D. Wyland

    1987-01-01

    This paper studies the total dose and dose rate radiation response of the FCT family of high speed CMOS integrated circuits. Data taken on the devices is used to establish the dominant failure modes, and this data is further analyzed using one-sided tolerance factors for normal distribution statistical analysis.

  16. Neutron induced soft errors in CMOS memories under reduced bias

    SciTech Connect

    Hazucha, P.; Svensson, C. [Linkoeping Univ. (Sweden). Electronic Devices Group] [Linkoeping Univ. (Sweden). Electronic Devices Group; Johansson, K. [Linkoeping Univ. (Sweden). Electronic Devices Group] [Linkoeping Univ. (Sweden). Electronic Devices Group; [Ericsson Saab Avionics AB, Linkoeping (Sweden)

    1998-12-01

    A custom designed 16 kbit CMOS memory was irradiated by 14 MeV neutrons and 100 MeV neutrons. SEU cross sections were evaluated under different supply voltages. The cross section values are compared to those predicted by the BGR model.

  17. Predictions of CMOS compatible on-chip optical interconnect

    Microsoft Academic Search

    Guoqing Chen; Hui Chen; Mikhail Haurylau; Nicholas A. Nelson; David H. Albonesi; Philippe M. Fauchet; Eby G. Friedman

    Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect

  18. A Planar CMOS Field-Emission Vacuum Magnetic Sensor

    Microsoft Academic Search

    Paul J. French; Anthony J. Kenyon; David M. Garner

    2009-01-01

    We have fabricated a CMOS vacuum magnetic sensor that exploits the deflection of an electron beam produced by field emission by a perpendicular magnetic field. The device is planar and fabricated by conventional lithography and etching processes. An extremely high magnetic field sensitivity of 4times103%\\/T is reported.

  19. Process flow innovations for photonic device integration in CMOS

    NASA Astrophysics Data System (ADS)

    Beals, Mark; Michel, J.; Liu, J. F.; Ahn, D. H.; Sparacin, D.; Sun, R.; Hong, C. Y.; Kimerling, L. C.; Pomerene, A.; Carothers, D.; Beattie, J.; Kopa, A.; Apsel, A.; Rasras, M. S.; Gill, D. M.; Patel, S. S.; Tu, K. Y.; Chen, Y. K.; White, A. E.

    2008-02-01

    Multilevel thin film processing, global planarization and advanced photolithography enables the ability to integrate complimentary materials and process sequences required for high index contrast photonic components all within a single CMOS process flow. Developing high performance photonic components that can be integrated with electronic circuits at a high level of functionality in silicon CMOS is one of the basic objectives of the EPIC program sponsored by the Microsystems Technology Office (MTO) of DARPA. Our research team consisting of members from: BAE Systems, Alcatel-Lucent, Massachusetts Institute of Technology, Cornell University and Applied Wave Research reports on the latest developments of the technology to fabricate an application specific, electronic-photonic integrated circuit (AS_EPIC). Now in its second phase of the EPIC program, the team has designed, developed and integrated fourth order optical tunable filters, both silicon ring resonator and germanium electro-absorption modulators and germanium pin diode photodetectors using silicon waveguides within a full 150nm CMOS process flow for a broadband RF channelizer application. This presentation will review the latest advances of the passive and active photonic devices developed and the processes used for monolithic integration with CMOS processing. Examples include multilevel waveguides for optical interconnect and germanium epitaxy for active photonic devices such as p-i-n photodiodes and modulators.

  20. The Evolution of Digital Imaging: From CCD to CMOS

    E-print Network

    La Rosa, Andres H.

    the grandfathers of the digital imaging revolution, which has all but converted cameras and video recorders fromThe Evolution of Digital Imaging: From CCD to CMOS A Micron White Paper Digital imaging began into electrical charges have become increasingly efficient. The processes for transforming optical to digital have