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1

An Accelerator-Based Wireless Sensor Network Processor in 130nm CMOS  

E-print Network

An Accelerator-Based Wireless Sensor Network Processor in 130nm CMOS Mark Hempstead ARM Ltd-1-60558-626-7/09/10 ...$10.00. Keywords Wireless Sensor Networks, Ultra-Low Power, Accelerator-based 1. INTRODUCTION Networks of wireless sensor networks (WSNs) have uti- lized nodes based on off-the-shelf general purpose

Hempstead, Mark

2

On-chip Oscilloscope for Signal Integrity Characterization of Interconnects in 130nm CMOS Technology  

E-print Network

[1]. As the minimum feature size continues to shrink, integrated circuit designs tend to grow Technology Pavle Milosevic and Jos� E. Schutt-Ain� Department of Electrical and Computer Engineering, the design of a prototype chip for signal integrity characterization in 130nm CMOS technology is discussed

Schutt-Ainé, José E.

3

A Calibration-Free Low-Cost Process-Compensated Temperature Sensor in 130 nm CMOS  

Microsoft Academic Search

A calibration-free low-cost CMOS integrated smart temperature sensor is presented that requires significantly less die area than previously published designs through the use of novel circuit technique and the 130 nm CMOS process. Uncalibrated sensor operation is achieved through the extensive use of analog dynamic element matching and chopper stabilization circuitry. A novel process-compensation circuit is presented that uses the

Robert P. Fisk; S. M. Rezaul Hasan

2011-01-01

4

A Single-Event-Hardened Phase-Locked Loop Fabricated in 130 nm CMOS  

Microsoft Academic Search

A radiation-hardened-by-design phase-locked loop (PLL)-designed and fabricated in 130 nm CMOS-is shown to mitigate single-event transients (SETs). Two-photon-absorption (TPA) laser tests were used to characterize the error signatures of the PLL and to perform single-event upset (SEU) mapping of the PLL sub-components. Results show that a custom, voltage-based charge pump reduces the error response of the PLL over conventional designs

T. D. Loveless; L. W. Massengill; B. L. Bhuva; W. T. Holman; R. A. Reed; D. McMorrow; J. S. Melinger; P. Jenkins

2007-01-01

5

Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies  

Microsoft Academic Search

The distributions of SET pulse-widths produced by heavy ions in 130-nm and 90-nm CMOS technologies are measured experimentally using an autonomous pulse characterization technique. The event cross section is the highest for SET pulses between 400 ps to 700 ps in the 130-nm process, while it is dominated by SET pulses in the range of 500 ps to 900 ps

Balaji Narasimham; Bharat L. Bhuva; Ronald D. Schrimpf; Lloyd W. Massengill; Matthew J. Gadlage; Oluwole A. Amusan; William Timothy Holman; Arthur F. Witulski; William H. Robinson; Jeffrey D. Black; Joseph M. Benedetto; Paul H. Eaton

2007-01-01

6

Single Event Gate Rupture in 130-nm CMOS Transistor Arrays Subjected to X-Ray Irradiation  

E-print Network

We present new experimental results on heavy ion-induced gate rupture on deep submicron CMOS transistor arrays. Through the use of dedicated test structures, composed by a large number of 130-nm MOSFETs connected in parallel, we show the response to heavy ion irradiation under high stress voltages of devices previously irradiated with X-rays. We found only a slight impact on gate rupture critical voltage at a LET of 32 MeV cm(2) mg(-1) for devices previously irradiated up to 3 Mrad(SiO2), and practically no change for 100 Mrad(SiO2) irradiation, dose of interest for the future super large hadron collider (SLHC).

Silvestri, M; Gerardin, Simone; Faccio, Federico; Paccagnella, Alessandro

2010-01-01

7

An accelerator-based wireless sensor network processor in 130nm CMOS Mark Hempstead, Gu-Yeon Wei, David Brooks  

E-print Network

An accelerator-based wireless sensor network processor in 130nm CMOS Mark Hempstead, Gu-Yeon Wei that characterize wireless sensor network workloads. The system employs application specific hardware accelerators processor, heterogeneous hardware accelerators, and application-controlled VDD gating. Networks of ultra

Hempstead, Mark

8

Conceptual design of a MGy tolerant integrated signal conditioning circuit in 130nm and 700nm CMOS  

NASA Astrophysics Data System (ADS)

The conceptual design of a MGy tolerant configurable discrete time signal conditioning circuit in a 130nm and 700nm CMOS technology is presented, for use with resistive sensors like strain gauge pressure sensors. The design features a differential preamplifier using a Correlated Double Sampling (CDS) architecture at a sample rate of 20kHz. Furthermore, a high voltage buffer and level shifter is presented in the 0.7?m design. The gain is digitally controllable between 27 and 400. The nominal input referred noise voltage is only 8.6?V at room temperature. The circuits have a simulated radiation tolerance of more than 1MGy. Simulations of the radiation behaviour are based on results obtained from [1],[2].

Verbeeck, J.; Van Uffelen, M.; Steyaert, M.; Leroux, P.

2012-01-01

9

Traveling wave electrode design for ultra compact carrier-injection HBT-based electroabsorption modulator in a 130nm BiCMOS process  

NASA Astrophysics Data System (ADS)

Silicon photonic system, integrating photonic and electronic signal processing circuits in low-cost silicon CMOS processes, is a rapidly evolving area of research. The silicon electroabsorption modulator (EAM) is a key photonic device for emerging high capacity telecommunication networks to meet ever growing computing demands. To replace traditional large footprint Mach-Zehnder Interferometer (MZI) type modulators several small footprint modulators are being researched. Carrier-injection modulators can provide large free carrier density change, high modulation efficiency, and compact footprint. The large optical bandwidth and ultra-fast transit times of 130nm HBT devices make the carrierinjection HBT-based EAM (HBT-EAM) a good candidate for ultra-high-speed optical networks. This paper presents the design and 3D full-wave simulation results of a traveling wave electrode (TWE) structure to increase the modulation speed of a carrier-injection HBT-EAM device. A monolithic TWE design for an 180um ultra compact carrier-injection-based HBT-EAM implemented in a commercial 130nm SiGe BiCMOS process is discussed. The modulator is electrically modeled at the desired bias voltage and included in a 3D full-wave simulation using CST software. The simulation shows the TWE has a S11 lower than -15.31dB and a S21 better than -0.96dB covering a bandwidth from DC-60GHz. The electrical wave phase velocity is designed close to the optical wave phase velocity for optimal modulation speed. The 3D TWE design conforms to the design rules of the BiCMOS process. Simulation results show an overall increase in modulator data rate from 10Gbps to 60Gbps using the TWE structure.

Fu, Enjin; Joyner Koomson, Valencia; Wu, Pengfei; Huang, Z. Rena

2014-03-01

10

Low-Power Circuits for a 2.5-V, 10.7-to-86Gb\\/s Serial Transmitter in 130-nm SiGe BiCMOS  

Microsoft Academic Search

Low-power building blocks for a serial transmitter operating up to 86 Gb\\/s are designed and implemented in a 130-nm SiGe BiCMOS technology with 150-GHz SiGe fT HBT. Design techniques are presented which aim to minimize high-speed building block power consumption. They include lowering the supply voltage by employing a true BiCMOS high-speed logic family, as well as reducing current consumption

Timothy O. Dickson; Sorin P. Voinigescu

2007-01-01

11

Micromachined thermal radiation emitter from a commercial CMOS process  

Microsoft Academic Search

Fabrication of thermally isolated micromechanical structures capable of generating thermal radiation for dynamic thermal scene simulation (DTSS) is described. Complete compatibility with a commercial CMOS process is achieved through design of a novel, but acceptable, layout for implementation by the CMOS foundry using its regular process sequence. Following commercial production and delivery of the CMOS chips, a single maskless etch

M. Parameswaran; Alexander M. Robinson; David L. Blackburn; Michael Gaitan; Jon Geist

1991-01-01

12

An accelerator-based wireless sensor network processor in 130nm CMOS  

Microsoft Academic Search

Networks of ultra-low-power nodes capable of sensing, computa- tion, and wireless communication have applications in medicine, science, industrial automation, and security. Over the past few years, deployments of wireless sensor networks (WSNs) have uti- lizednodesbasedonoff-the-shelfgeneralpurposemicrocontrollers. Reducing power consumption requires the development of System- on-chip (SoC) implementations that must provide both energy effi- ciency and adequate performance to meet the demands

Mark Hempstead; Gu-yeon Wei; David Brooks

2009-01-01

13

Thermally tunable SOI CMOS photonics circuits  

NASA Astrophysics Data System (ADS)

Ring waveguide resonating structures with high quality factors are the key components in the silicon photonics portfolio boosting up its functionality and circuit performance. Due to a number of manufacturing reasons their peak wavelengths are often prone to deviate from designed values. In order to keep the ring resonator operating as specified, its peak wavelength then needs to be corrected in a reliable and power efficient way. We demonstrate the performance of the thermally tunable mux/demux filter ring structures fabricated in the commercial 130 nm SOI CMOS line.

Shubin, Ivan; Zheng, Xuezhe; Thacker, Hiren; Yao, Jin; Costa, Joannes; Luo, Ying; Li, Guoliang; Krishnamoorthy, Ashok V.; Cunningham, John E.; Pinguet, Thierry; Mekis, Attila

2010-02-01

14

Monolithically integrated high-speed CMOS photonic transceivers  

Microsoft Academic Search

We demonstrate monolithically integrated 4times10 Gb\\/s WDM transceivers built in a production 130 nm SOI CMOS process. Only light sources are external to the chip. 40 Gb\\/s error-free, bidirectional transmission is demonstrated.

T. Pinguet; B. Analui; E. Balmater; D. Guckenberger; M. Harrison; R. Koumans; D. Kucharski; Y. Liang; G. Masini; A. Mekis; S. Mirsaidi; A. Narasimha; M. Peterson; D. Rines; V. Sadagopan; S. Sahni; T. J. Sleboda; D. Song; Y. Wang; B. Welch; J. Witzens; J. Yao; S. Abdalla; S. Gloeckner; P. De Dobbelaere

2008-01-01

15

Quantitative Comparison of Commercial CCD and Custom-Designed CMOS Camera for Biological  

E-print Network

Quantitative Comparison of Commercial CCD and Custom-Designed CMOS Camera for Biological and systems where even the smallest details have a meaning, CCD cameras are mostly preferred and they hold camera to compete with the default CCD camera of an inverted microscope for fluorescence imaging

De Micheli, Giovanni

16

Performance of commercial CMOS cameras for high-speed multicolor photometry  

E-print Network

We present some results of testing of commercial color CMOS cameras for astronomical applications. CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in CMOS sensors is close to the Johnson BVR system. We demonstrate transformation from the Bayer color system to the Johnson one. Our photometric measurements with color CMOS cameras coupled to small telescopes (11 - 30 inch) reveal that in video mode stars up to V $\\sim$ 9 can be shot at 24 frames per second. Using a high-speed CMOS camera with short exposure times (10 - 20 ms) we can perform an imaging mode called "lucky imaging". We can pick out high quality frames and combine them into a single image using "shift-and-add" technique. This allows us obtain an image with much higher resolution than would be possible shooting a single image with long exposure. For image selection we use the Strehl-selection method. We demonstrates advan...

Pokhvala, S M; Reshetnyk, V M

2013-01-01

17

RuMBa: a rule-model OPC for low MEEF 130-nm KrF lithography  

Microsoft Academic Search

For cost effective 130nm node manufacturing, it is prefer to use KrF binary chrome mask. To realize a production worth process for making random logic device, we need to effectively control mask error enhancement factor (MEEF) through pitch. In low k1 lithography, process parameters such as focus, lens aberration, linewidth, and line pitch, style of proximity correction (OPC), and resist

Stephen Hsu; Xuelong Shi; Michael Hsu; Noel P. Corcoran; J. Fung Chen; Sunil Desai; Micheal J. Sherrill; Y. C. Tseng; H. A. Chang; J. F. Kao; Alex Tseng; WeiJyh Liu; Anseime Chen; Arthur Lin; Jan P. Kujten; Eric Jacobs; Arjan Verhappen

2001-01-01

18

A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects  

Microsoft Academic Search

A leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported. Dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V. High Vt transistors have drive currents of 1.03 mA\\/?m and 0.5 mA\\/?m for NMOS and PMOS respectively, while low Vt transistors have currents of 1.17 mA\\/?m

S. Tyagi; M. Alavi; R. Bigwood; T. Bramblett; J. Brandenburg; W. Chen; B. Crew; M. Hussein; P. Jacob; C. Kenyon; C. Lo; B. McIntyre; Z. Ma; P. Moon; P. Nguyen; L. Rumaner; R. Schweinfurth; S. Sivakumar; M. Stettler; S. Thompson; B. Tufts; J. Xu; S. Yang; M. Bohr

2000-01-01

19

Intensity of the oxygen 130nm triplet through the atmosphere of Mars and Venus; Comparison with Spicam data.  

NASA Astrophysics Data System (ADS)

The problem of the oxygen emission in the planetary atmospheres is crucial to constraint the atmospheric models and had never been directly measured. The oxygen 130nm triplet is optically thick in those atmospheres and is resonant with sun radiations. The instruments SPICAV and SPICAM are able to measure the intensity of this triplet without any spectral resolution. The Hubble space telescope with the STIS instrument is able to get enough spectral resolution to see the lines profile. In previous simulations, the overlapping between this triplet and lines of the CO fourth positive band has never been taken into account. We present new simulations calculating the oxygen 130nm triplet intensity and line profile taking into account the overlapping problem with a partial redistribution. Due to the structure of the triplet, we had to develop a new expression of the RII redistribution function. The effects of the CO lines modified strongly the O 130nm line parameters, intensity and line profile. These effects depend strongly of the geometry of the line of sight. We show that it is essential to take this problem into account in both the martian and venusian cases and that this could be a very useful way to get strong information on both the CO and the O states in these atmosphere for various geometrical conditions. After fitting these simulations with 2 Spicam data sets with two different Ls angles, we find that it is coherent with strong seasonal variations of the O and CO concentrations. EPSC Abstracts, Vol. 3, EPSC2008-A-00417, 2008 European Planetary Science Congress, Author(s) 2008

Mathieu, Barthelemy; Guillaume, Gronoff; Jean, Lilensten; Jean-Yves, Chaufray; Cyril, Simon

2008-09-01

20

Micro Ethanol Sensors with a Heater Fabricated Using the Commercial 0.18 ?m CMOS Process  

PubMed Central

The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

21

Comparisons of soft error rate for SRAMs in commercial SOI and bulk below the 130-nm technology node  

Microsoft Academic Search

This paper presents experimental ASER on SOI and BULK SRAMs for the 250-, 130-, and 90-nm technologies. The key parameters controlling soft error rate (SER) in these technologies are modeled with Monte Carlo simulations to predict SER to the 65-nm node.

P. Roche; G. Gasiot; K. Forbes; V. O'Sullivan; V. Ferlet

2003-01-01

22

Soft X-ray Microscope Constructed with 130-nm Spatial Resolution Using a High Harmonic X-ray Source  

NASA Astrophysics Data System (ADS)

Using high harmonic radiation as an X-ray light source, a soft X-ray microscope with nanometer-scale spatial resolution was investigated. A transmission soft X-ray microscope was constructed using a Mo/Si multilayer concave mirror as a condenser and a Fresnel zone plate as a microscope objective. The high-order harmonic source at 13 nm, emitted from neon atoms driven by intense femtosecond laser pulses, was optimized by controlling laser chirp. Objects, patterned on 160-nm-thick hydrogen silsesquioxane coated on a 100-nm-thick Si3N4 membrane, were used for imaging. The analysis of object images, captured on an X-ray charge-coupled device, showed that the spatial resolution of the microscope was about 130 nm, verifying the usefulness of the tabletop soft X-ray source.

Kim, Deuk Su; Park, Jong Ju; Lee, Kyoung Hwan; Park, Juyun; Nam, Chang Hee

2009-02-01

23

Shallow-trench-isolation bounded single-photon avalanche diodes in commercial deep submicron CMOS technologies  

NASA Astrophysics Data System (ADS)

This dissertation describes the first single-photon detection device to be manufactured in a commercial deep-submicron CMOS technology. It also describes novel self-timed peripheral circuits which optimize the performance of the new device. An extension of the new device for dual-color single-photon detection is investigated. Finally, an area- and power-efficient method for single-photon frequency upconversion is presented, analyzed, and experimentally examined. Single-photon avalanche diodes have been used in diverse applications, including three-dimensional laser radar, three-dimensional facial mapping, fluorescence-correlation techniques and time-domain tomography. Due to the high electric fields which these devices must sustain, they have traditionally been manufactured in custom processes, severely limiting their speed and the ability to integrate them in high-resolution imagers. By utilizing a process module originally designed to enhance the performance of CMOS transistors, we achieve highly planar junctions in an area-efficient manner. This results in SPADs exhibiting high fill factors, small pitch and ultrafast operation. Device miniaturization is accompanied by excessive noise, which was shown to emanate from trapped avalanche charges. Due to the fast recharging of the device, these charges are released in a subsequent charged phase of the device, causing correlated after-pulses. We present electrostatic and electrical simulation results, as well as a comprehensive characterization of the new device. We also show for the first time that by utilizing the two junctions included in the device, we can selectively detect photons of different wavelengths in the same pixel, as is desirable in cross-correlation experiments. This dissertation also describes an efficient new method for single-photon frequency upconversion. This is desirable for applications including quantum-key distribution and high-resolution near-infrared imaging. The new technique is based on electroluminescence in or near the multiplication region of the device, resulting from hot-carrier recombination. We model a proposed hybrid device and deduce the critical parameters for efficient upconversion. Lastly, we experimentally demonstrate that the electroluminescence yield from an InGaAs/InAlAs avalanche diode is sufficient for highly-efficient upconversion.

Finkelstein, Hod

24

2D and 3D CMOS MAPS with high performance pixel-level signal processing  

NASA Astrophysics Data System (ADS)

Deep N-well (DNW) MAPS have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. These devices have been fabricated in a planar (2D) 130 nm CMOS technology. The triple-well structure available in such an ultra-deep submicron technology is exploited by using the deep N-well as the charge-collecting electrode. This paper intends to discuss the design features and measurement results of the last prototype (Apsel5T chip) recently fabricated in a 2D 130 nm CMOS technology. Recent advances in microelectronics industry have made 3D integrated circuits an option for High Energy Physics experiments. A 3D version of the Apsel5T chip has been designed in a 130 nm CMOS, two-layer, vertically integrated technology. The main features of this new 3D monolithic detector are presented in this paper.

Traversi, Gianluca; Gaioni, Luigi; Manghisoni, Massimo; Ratti, Lodovico; Re, Valerio

2011-02-01

25

An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V  

Microsoft Academic Search

A leading edge 130 nm technology with 6 layers of Cu interconnects and 1.3 V operation has previously been presented (Tyagi et al., 2000). In this work, we enhance the previous technology with the following: transistor improvements which support a 60 nm gate dimension and increased drive current, improved 6-T SRAM device matching to allow low power and high performance

S. Thompson; M. Alavi; R. Arghavani; A. Brand; R. Bigwood; J. Brandenburg; B. Crew; V. Dubin; M. Hussein; P. Jacob; C. Kenyon; E. Lee; B. Mcintyre; Z. Ma; P. Moon; P. Nguyen; M. Prince; R. Schweinfurth; S. Sivakumar; P. Smith; M. Stettler; S. Tyagi; M. Wei; J. Xu; S. Yang; M. Bohr

2001-01-01

26

Effect of Total Ionizing Dose on a Bulk 130 nm Ring Oscillator Operating at Ultra-Low Power  

Microsoft Academic Search

Total ionizing dose experiments showed an increase in operating frequency (and therefore, power consumption) in bulk CMOS ring oscillators when operated at ultra-low power supply voltages. Combined-environment experiments showed the single-event susceptibility of ULP circuits increases with total dose exposure. To operate ULP circuits in a total dose environment and ensure there is little change in their circuit characteristics, the

Megan C. Casey; Sarah E. Armstrong; Rajan Arora; Michael P. King; Jonathan R. Ahlbin; S. Ashley Francis; Bharat L. Bhuva; Dale McMorrow; Harold L. Hughes; Patrick J. McMarr; Joseph S. Melinger; Lloyd W. Massengill

2009-01-01

27

Design of the analog front-end for the Timepix3 and Smallpix hybrid pixel detectors in 130 nm CMOS technology  

NASA Astrophysics Data System (ADS)

This paper describes a front-end for hybrid pixel readout chips, which was developed for the Timepix3 and Smallpix ASICs. The front-end contains a single-ended preamplifier with a structure for leakage current compensation which can handle both signal polarities, and a single-threshold discriminator with compensation for pixel-to-pixel mismatch. Preamplifier and discriminator are required to be fast, to allow a Time-Of-Arrival (TOA) measurement with a resolution of 1.56 ns. Time-Over-Threshold (TOT) is also measured; the monotonicity of TOT with respect to the input charge is greatly improved as compared to the previous Timepix chip. The analog area is only 55 ?m 13.5 ?m. Timepix3 has already been fabricated and the first test results are also presented in this paper.

De Gaspari, M.; Alozy, J.; Ballabriga, R.; Campbell, M.; Frjdh, E.; Idarraga, J.; Kulis, S.; Llopart, X.; Poikela, T.; Valerio, P.; Wong, W.

2014-01-01

28

A 5th generation SPARC64 processor is fabricated in 130nm SOI CMOS process with 8 layers of Cu metallization. It runs at  

E-print Network

processor chips, the MTBF requirement for each processor is much more stringent than the one for single of Cu metallization. It runs at 1.3GHz with 34.7W power dissipation in the laboratory. The chip contains over 190M transistors with 19M in logic circuits. The chip size is 18.14mm x 15.99mm. The error

Koppelman, David M.

29

High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments  

NASA Astrophysics Data System (ADS)

High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 1015 neq/cm2, nearly 100% detection efficiency and a spatial resolution of about 3 ?m were demonstrated. Since 2011 the HV detectors have first applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process.

Peri?, Ivan; Fischer, Peter; Kreidl, Christian; Hanh Nguyen, Hong; Augustin, Heiko; Berger, Niklaus; Kiehn, Moritz; Perrevoort, Ann-Kathrin; Schning, Andr; Wiedner, Dirk; Feigl, Simon; Heim, Timon; Meng, Lingxin; Mnstermann, Daniel; Benoit, Mathieu; Dannheim, Dominik; Bompard, Frederic; Breugnon, Patrick; Clemens, Jean-Claude; Fougeron, Denis; Liu, Jian; Pangaud, Patrick; Rozanov, Alexandre; Barbero, Marlon; Backhaus, Malte; Hgging, Fabian; Krger, Hans; Ltticke, Florian; Marias, Carlos; Obermann, Theresa; Garcia-Sciveres, Maurice; Schwenker, Benjamin; Dierlamm, Alexander; La Rosa, Alessandro; Miucci, Antonio

2013-12-01

30

Effects of Guard Bands and Well Contacts in Mitigating Long SETs in Advanced CMOS Processes  

Microsoft Academic Search

Mixed mode TCAD simulations are used to show the effects of guard bands and high density well contacts in maintaining the well potential after a single event strike and thus reduce the width of long transients in a 130-nm CMOS process. Experimental verification of the effectiveness in mitigating long transients was achieved by measuring the distribution of SET pulse widths

Balaji Narasimham; Bharat L. Bhuva; Ronald D. Schrimpf; Lloyd W. Massengill; Matthew J. Gadlage; T. W. Holman; Arthur F. Witulski; William H. Robinson; Jeffrey D. Black; Joseph M. Benedetto; Paul H. Eaton

2008-01-01

31

Effects of guard bands and well contacts in mitigating long SETs in advanced CMOS processes  

Microsoft Academic Search

Mixed mode TCAD simulations are used to show the effects of guard bands and high density well contacts in maintaining the well potential after a single event strike and thus reduce the width of long transients in a 130-nm CMOS process. Experimental verification of the effectiveness in mitigating long transients was achieved by measuring the distribution of SET pulse widths

Balaji Narasimham; Bharat L. Bhuva; Ronald D. Schrimpf; Lloyd W. Massengill; Matthew J. Gadlage; W. Timothy Holman; Arthur F. Witulski; William H. Robinson; Jeffrey D. Black; Joseph M. Benedetto; Paul H. Eaton

2007-01-01

32

Active devices under CMOS I\\/O pads  

Microsoft Academic Search

Active devices, including electrostatic discharge protection devices and ring-oscillator circuits, under CMOS I\\/O pads are investigated in a 130 nm full eight-level copper metal complementary metal-oxide-semiconductor process, using fluorinated silicate glass (FSG) low-k inter-metal dielectric. The high current I-V curve measured in the second breakdown trigger point (Vt2, It2) of ESD protection devices under various metal level stack structures, shows

Kuo-Yu Chou; Ming-Jer Chen; Chi-Wen Liu

2002-01-01

33

Color recognition sensor in standard CMOS technology  

NASA Astrophysics Data System (ADS)

Two integrated color detectors are presented as a solution for low cost color sensing applications. The color detection is based on lateral carrier diffusion and wavelength-dependent absorption-depth. The proposed detectors are implemented in a standard 130 nm CMOS technology without process modification or color filters. Three independent output signals are obtained with spectral responsivities optimized to short, middle and long wavelengths. R, G, B or X, Y, Z standard color representation can be realized by a linear transformation of the output signals.

Batistell, Graciele; Zhang, Vincent Chi; Sturm, Johannes

2014-12-01

34

Illumination pupil fill measurement and analysis and its application in scanner V-H bias characterization for 130-nm node and beyond  

NASA Astrophysics Data System (ADS)

A detailed characterization of across chip line width variation (ACLV) has been carried out on the latest Nikon scanners with a combination of advanced metrology techniques in Texas Instruments, including scatterometer-based image field and CD fingerprinting, lens aberrations measurement using a Litel in-situ interferometer, and illumination source imaging with a pin-hole camera. This paper describes the application of the above techniques in our investigation of the root causes for pattern CD bias between vertical and horizontal features. Illumination source radiance distribution is found sometimes to have a significant impact on V-H bias and the final overall ACLV on production wafers. Examples are given to demonstrate a comprehensive methodology that is used to quantitatively break down the overall CD errors and correlate them back to the basic optical and imaging components. It is shown through pupil-gram analysis that the ellipticity in partial coherence is typically within 1+/-1% for conventional illuminations settings on the advanced Nikon scanners while the uneven radiance distribution across the source plays a major role in V-H pattern CD bias. For scanners with low and uniform lens coma aberrations, the V-H bias after removing the contribution from image field errors is found to follow a linear relationship with the source radiance non-uniformity described also in terms of ellipticity. It is shown that radiance ellipticity is a bigger concern for off-axis illuminators. Tighter design rules patterned with off-axis illumination are more vulnerable to source radiance non-uniformity as well as lens aberrations. Illuminator induced V-H bias across the slit is compared to the signature caused by lens aberrations specifically uneven x,y-coma. Implications to exposure tool specification, control, and matching are further explored through experiments and lithography simulation for the current 130nm production and the future technology nodes in development.

Zhang, Gary; Wang, Changan; Tan, Colin L.; Ilzhoefer, John R.; Atkinson, Chris; Renwick, Stephen P.; Slonaker, Steve D.; Godfrey, David; Fruga, Catherine H.

2003-06-01

35

Correlation of Prediction to On-Orbit SEU Performance for a Commercial 0.25-?m CMOS SRAM  

Microsoft Academic Search

Boeing Satellite Development Center (SDC) geomoblie satellites have experienced a number of very large solar flares during their operational life. Comparison performance in a geostationary orbit to predictions based on heavy-ion ground testing for a digital signal processor (DSP) payload based on 0.25-mum CMOS, megagate-ASICs will be presented. Performance during flare peaks will be shown, and comparisons will be made

D. L. Hansen; K. Jobe; J. Whittington; M. Shoga; D. A. Sunderland

2007-01-01

36

Scaling trends of single-photon avalanche diode arrays in nanometer CMOS technology  

NASA Astrophysics Data System (ADS)

A family of scaleable single photon avalanche diode (SPAD) structures in 130nm and 90nm CMOS is presented. Performance trends such as dark count rate (DCR), jitter and breakdown voltage are studied versus active diameter for devices ranging from 32?m down to 2?m. To address pixel pitch we introduce a shared buried n-well approach allowing compact arrays containing both NMOS-transistor readout circuitry and SPAD devices. A pixel pitch of 5?m has been achieved in 90nm CMOS technology, offering the potential for future megapixel single photon image sensors.

Richardson, Justin A.; Webster, Eric A. G.; Grant, Lindsay A.; Henderson, Robert K.

2011-05-01

37

Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker  

NASA Astrophysics Data System (ADS)

In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10-15 ?m in both coordinates, low material budget <1%X0, and the ability to withstand a background hit rate of several tens of MHz/cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.

Rizzo, G.; Comott, D.; Manghisoni, M.; Re, V.; Traversi, G.; Fabbri, L.; Gabrielli, A.; Giorgi, F.; Pellegrini, G.; Sbarra, C.; Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Berra, A.; Lietti, D.; Prest, M.; Bevan, A.; Wilson, F.; Beck, G.; Morris, J.; Gannaway, F.; Cenci, R.; Bombelli, L.; Citterio, M.; Coelli, S.; Fiorini, C.; Liberali, V.; Monti, M.; Nasri, B.; Neri, N.; Palombo, F.; Stabile, A.; Balestri, G.; Batignani, G.; Bernardelli, A.; Bettarini, S.; Bosi, F.; Casarosa, G.; Ceccanti, M.; Forti, F.; Giorgi, M. A.; Lusiani, A.; Mammini, P.; Morsani, F.; Oberhof, B.; Paoloni, E.; Perez, A.; Petragnani, G.; Profeti, A.; Soldani, A.; Walsh, J.; Chrzaszcz, M.; Gaioni, L.; Manazza, A.; Quartieri, E.; Ratti, L.; Zucca, S.; Alampi, G.; Cotto, G.; Gamba, D.; Zambito, S.; Dalla Betta, G.-F.; Fontana, G.; Pancheri, L.; Povoli, M.; Verzellesi, G.; Bomben, M.; Bosisio, L.; Cristaudo, P.; Lanceri, L.; Liberti, B.; Rashevskaya, I.; Stella, C.; Vitale, L.

2013-08-01

38

Recent progress in the development of 3D deep n-well CMOS MAPS  

NASA Astrophysics Data System (ADS)

In the deep n-well (DNW) monolithic active pixel sensor (MAPS) a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. This work is concerned with the design and characterization of DNW MAPS fabricated in a vertical integration (3D) CMOS technology. 3D processes can be very effective in overcoming typical limitations of monolithic active pixel sensors. This paper discusses the main features of a new analog processor for DNW MAPS (ApselVI) in view of applications to the SVT Layer0 of the SuperB Factory. It also presents the first experimental results from the test of a DNW MAPS prototype in the GlobalFoundries 130 nm CMOS technology.

Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.; Zucca, S.

2012-02-01

39

CMOS Meets Bio  

Microsoft Academic Search

There are burgeoning efforts to use CMOS ICs for biotechnology. This paper reviews one such effort, development of a CMOS\\/Microfluidic hybrid system for magnetic manipulation of biological cells originally reported by the authors in H. Lee et al. (2005, 2006). Programmable magnetic field patterns produced by a CMOS microcoil array IC efficiently manipulate individual cells (tagged by magnetic beads) inside

Yong Liu; Hakho Lee; R. M. Westervelt; D. Ham

2006-01-01

40

CMOS image sensors  

Microsoft Academic Search

In this article, we provide a basic introduction to CMOS image-sensor technology, design and performance limits and present recent developments and future directions in this area. We also discuss image-sensor operation and describe the most popular CMOS image-sensor architectures. We note the main non-idealities that limit CMOS image sensor performance, and specify several key performance measures. One of the most

A. El Gamal; H. Eltoukhy

2005-01-01

41

Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design  

NASA Astrophysics Data System (ADS)

In this paper, a compact channel thermal noise model for short-channel MOSFETs is presented and applied to the radio frequency integrated circuit (RFIC) design. Based on the analysis of the relationship among different short-channel effects such as velocity saturation effect (VSE), channel-length modulation (CLM), and carrier heating effect (CHE), the compact model for the channel thermal noise was analytically derived as a simple form. In order to simulate MOSFET's noise characteristics in circuit simulators, an appropriate methodology is proposed. The used compact noise model is verified by comparing simulated results to the measured data at device and circuit level by using 65nm and 130nm CMOS technologies, respectively.

Jeon, Jongwook; Song, Ickhyun; Lee, Jong Duk; Park, Byung-Gook; Shin, Hyungcheol

42

Planarization of a CMOS die for an integrated metal MEMS  

NASA Astrophysics Data System (ADS)

This paper describes a planarization procedure to achieve a flat CMOS die surface for the integration of a MEMS metal mirror array. The CMOS die for our device is 4 mm 4 mm and comes from a commercial foundry. The initial surface topography has 0.9 ?m bumps from the aluminum interconnect patterns that are used for addressing the individual micro mirror array elements. To overcome the tendency for tilt error in the planarization of the small CMOS die, our approach is to sputter a thick layer of silicon nitride (2.2 ?m) at low temperature and to surround the CMOS die with dummy pieces to define the polishing plane. The dummy pieces are first lapped down to the height of the CMOS die, and then all pieces are polished. This process reduces the 0.9 ?m height of the bumps to less than 25 nm.

Lee, Hocheol; Miller, Michele H.; Bifano, Thomas G.

2003-01-01

43

Ion traps fabricated in a CMOS foundry  

E-print Network

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, in any modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

Mehta, K K; Bruzewicz, C D; Chuang, I L; Ram, R J; Sage, J M; Chiaverini, J

2014-01-01

44

The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector  

NASA Astrophysics Data System (ADS)

This work presents the characterization of Deep N-well (DNW) active pixel sensors fabricated in a vertically integrated technology. The DNW approach takes advantage of the triple well structure to lay out a sensor with relatively large charge collecting area (as compared to standard three transistor MAPS), while the readout is performed by a classical signal processing chain for capacitive detectors. This new 3D design relies upon stacking two homogeneous tiers fabricated in a 130 nm CMOS process where the top tier is thinned down to about 12 ?m to expose through silicon vias (TSV), therefore making connection to the buried circuits possible. This technology has been used to design a fine pitch 3D CMOS sensor with sparsification capabilities, in view of vertexing applications to the International Linear Collider (ILC) experiments. Results from the characterization of different kind of test structures, including single pixels, 33 and 88 matrices, are presented.

Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.

2013-12-01

45

Scintillator and CMOS APS Imager for Radiography Conditions  

Microsoft Academic Search

We evaluated X-ray image performance for several scintillators and a CMOS APS imager by both diagnostic radiography and mammography conditions. Commercially available scintillators such as Lanex screen, needle structured CsI (Tl), and fiber optic structured CsI (Tl) were coupled with a CMOS APS imager. The X-ray machines used in this study were fixed tube voltage of 80 kVp and variable

Kwang Hyun Kim; Young Soo Kim

2008-01-01

46

CMOS\\/BiCMOS power amplifier technology trend in Japan  

Microsoft Academic Search

Aiming for 2-5GHz band transceiver system on a chip, the integration of RF section has been developed by using conventional CMOS\\/BiCMOS (SiGeCMOS) process. The attempts to integrate power amplifiers (PA's) have been successful for low transmit power system such as Bluetooth, but these attempts are very limited due to the poor power handling capability of FET's in CMOS and the

Noriharu Suematsu; Shintaro Shinjo

2001-01-01

47

All-CMOS night vision viewer with integrated microdisplay  

NASA Astrophysics Data System (ADS)

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 ?m CMOS process, with no process alterations or post processing. The display features a 25 ?m pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

2014-02-01

48

CMOS dot matrix microdisplay  

NASA Astrophysics Data System (ADS)

Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

2011-03-01

49

Co-design of fully integrated 60GHz CMOS digital radio in QFN package  

Microsoft Academic Search

The past few years has witnessed the emergence of CMOS based circuits operating at millimeter wave-frequencies. Co-design of fully integrated 60 Ghz CMOS single chip digital radio with low cost QFN package is the promise for high volume low cost fabrication, opening huge commercial markets. As standardization efforts catalyzed the interest and investment of industry and agencies, one can be

J. Laskar; S. Pinel; D. Dawn; S. Sarkar; P. Sen; B. Perunama; D. Yeh; F. Barale

2008-01-01

50

CMOS Bridging Fault Detection  

Microsoft Academic Search

The authors compare the performance of two test generation techniques, stuck fault testing and current testing, when applied to CMOS bridging faults. Accurate simulation of such faults mandated the development of several new design automation tools, including an analog-digital fault simulator. The results of this simulation are analyzed. It is shown that stuck fault test generation, while inherently incapable of

Thomas M. Storey; Wojciech Maly

1990-01-01

51

Surface enhanced biodetection on a CMOS biosensor chip  

NASA Astrophysics Data System (ADS)

We present a rigorous electromagnetic theory of the electromagnetic power emitted by a dipole located in the vicinity of a multilayer stack. We applied this formalism to a luminescent molecule attached to a CMOS photodiode surface and report light collection efficiency larger than 80% toward the CMOS silicon substrate. We applied this result to the development of a low-cost, simple, portable device based on CMOS photodiodes technology for the detection and quantification of biological targets through light detection, presenting high sensitivity, multiplex ability, and fast data processing. The key feature of our approach is to perform the analytical test directly on the CMOS sensor surface, improving dramatically the optical detection of the molecule emitted light into the high refractive index semiconductor CMOS material. Based on adequate surface chemistry modifications, probe spotting and micro-fluidics, we performed proof-of-concept bio-assays directed against typical immuno-markers (TNF-? and IFN-?). We compared the developed CMOS chip with a commercial micro-plate reader and found similar intrinsic sensitivities in the pg/ml range.

Belloni, Federico; Sandeau, Laure; Conti, Sylvain; Vicaire, Florence; Owens, Roisin; Rigneault, Herv

2012-03-01

52

Micromachined thermally based CMOS microsensors  

Microsoft Academic Search

An integrated circuit (IC) approach to thermal microsensors is presented. The focus is on thermal sensors with on-chip bias and signal conditioning circuits made by industrial complementary metal-oxide-semiconductor (CMOS) IC technology in combination with post-CMOS micromachining or deposition techniques. CMOS materials and physical effects pertinent to thermal sensors are summarized together with basic structures used for microheaters, thermistors, thermocouples, thermal

HENRY BALTES; OLIVER PAUL; OLIVER BRAND

1998-01-01

53

Integrated CMOS RF amplifier  

NASA Technical Reports Server (NTRS)

This paper reports an integrated 2.0 micron CMOS RF amplifier designed for amplification in the 420-450 MHz frequency band. Design techniques are shown for the test amplifier configuration. Problems of decreased amplifier bandwidth, gain element instability, and low Q values for the inductors were encountered. Techniques used to overcome these problems are discussed. Layouts of the various elements are described and a summary of the simulation results are included. Test circuits have been submitted to MOSIS for fabrication.

Charity, C.; Whitaker, S.; Purviance, J.; Canaris, M.

1990-01-01

54

Total-Ionizing-Dose Effects in Modern CMOS Technologies  

Microsoft Academic Search

This review paper discusses several key issues associated with deep submicron CMOS devices as well as advanced semiconductor materials in ionizing radiation environments. There are, as outlined in the ITRS roadmap, numerous challenges ahead for commercial industry in its effort to track Moore's Law down to the 45 nm node and beyond. While many of the classical threats posed by

H. J. Barnaby

2006-01-01

55

Design of CMOS chopper amplifiers for thermal sensor interfacing  

Microsoft Academic Search

An analytical approach to the design of compact CMOS chopper amplifiers for integrated thermoelectric sensors is presented. The impact of the high resistance and low signal bandwidth of thermopile sources on the design is illustrated. The proposed approach, regarding the precision vs noise tradeoff, is applied to the design of a practical prototype, using a commercial process. Accurate electrical simulations

Michele Dei; Paolo Bruschi; Massimo Piotto

2008-01-01

56

Silicon Avalanche Photodetectors Fabricated With Standard CMOS/BiCMOS Technology  

E-print Network

Silicon Avalanche Photodetectors Fabricated With Standard CMOS/BiCMOS Technology Myung-Jae Lee Photonics for High-Speed Interconnects .....1 1-2. Silicon Photodetectors in Standard CMOS/BiCMOS Technology/BiCMOS Technology for Photodetectors .......................................................7 2-2. Silicon

Choi, Woo-Young

57

Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments  

E-print Network

CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Castro, Xitzel Sanchez; Winter, Marc

2014-01-01

58

Design and Fabrication of Vertically-Integrated CMOS Image Sensors  

PubMed Central

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Skorka, Orit; Joseph, Dileepan

2011-01-01

59

Regenerative switching CMOS system  

DOEpatents

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

Welch, J.D.

1998-06-02

60

Regenerative switching CMOS system  

DOEpatents

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

1998-01-01

61

CMOS sensor for RSI applications  

NASA Astrophysics Data System (ADS)

Three CMOS sensors were developed for remote sensing instrument (RSI) applications. First device is linear CMOS Sensor for Terrain Mapping Camera (TMC). This device has 4000 elements, 7 ?m x 7 ?m of pixel size. Second device is area CMOS Sensor for Hyper Spectral Imager (HySI). The device has 512 x 256 elements and 50 ?m x 50 ?m of pixel size. Third device is multi band sensor for Remote Sensing Instrument (RSI). This device integrates five linear CMOS sensor into a single monolithic chip to form a Multiple System On Chip (MSOC) IC. The multi band sensor consists of one panchromatic (PAN) and four multi - spectral (MS) bands. The PAN is 12000 elements, 10 ?m x 10 ?m with integration time of 297 ?s +/- 5%. Each MS band is 6000 elements, 20 ?m x 20 ?m with integration time of 594 us ?s +/- 5%. Both linear and area CMOS sensor were designed and developed for Chandrayaan-1 project. The Chandrayaan-1 satellite was launched to the moon on October 22, 2008. The moon orbit height is 100 km and 20 km of swath size. The multi band sensor was designed for earth orbit. The earth orbit height is about 720 km and 24 km of swath. The low weight, low power consumption and high radiation tolerance camera requirement only can be done by CMOS Sensor technology. The detail device structure and performance of three CMOS sensors will present.

Wang, Weng Lyang; Lin, Shengmin

2012-11-01

62

An extremely low power 2 GHz CMOS LC VCO for wireless communication applications  

Microsoft Academic Search

An extremely low power low phase noise CMOS LC voltage controlled oscillator (VCO) has been fully integrated in a commercial 0.18 mum CMOS process. To achieve low power and low phase noise, a complementary NMOS and PMOS cross-coupled differential LC structure is used. The LC tank is composed of octagonal-shaped inductors with 2 mum Al metal and standard NMOS varactors.

Han-il Lee; Tae-young Choi; Saeed Mohammadi; L. P. B. Katehi

2005-01-01

63

Single-chip CMOS anemometer  

Microsoft Academic Search

For the first time a packaged single-chip anemometry microsystem is reported. The system includes a thermal CMOS flow sensor with on-chip power management, signal conditioning, and A\\/D conversion. It is fabricated using an industrial IC process followed by post-CMOS micromachining. The system is packaged on a flexible substrate using flip-chip interconnection technology. The measurement of wind speeds is demonstrated in

F. Mayer; A. Haberli; H. Jacobs; G. Ofner; O. Paul; H. Baltes

1997-01-01

64

CMOS array design automation techniques  

NASA Technical Reports Server (NTRS)

The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

Lombardi, T.; Feller, A.

1976-01-01

65

25 nm CMOS design considerations  

Microsoft Academic Search

This paper explores the limit of bulk (or partially-depleted SOI) CMOS scaling. A feasible design for 25 nm (channel length) CMOS, without continued scaling of oxide thickness and power supply voltage, is presented. A highly 2D nonuniform profile (super-halo) is shown to yield low off-currents while delivering a significant performance advantage for a 1.0 V power supply. Several key issues,

Y. Taur; Clement H. Wann; David J. Frank

1998-01-01

66

High-speed graphene interconnects monolithically integrated with CMOS ring oscillators operating at 1.3GHz  

E-print Network

We have successfully experimentally integrated graphene interconnects with commercial 0.25 ¿m technology CMOS ring oscillator circuit using conventional fabrication techniques, and demonstrated high speed on-chip graphene ...

Chen, Xiangyu

67

A Single-Chip 8-Band CMOS Transceiver for 3G Cellular Systems with Digital Interface  

NASA Astrophysics Data System (ADS)

In this paper, a single-chip dual-mode 8-band 130nm CMOS transceiver including A/D/A converters and digital filters with 312MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.

Yoshida, Hiroshi; Toyoda, Takehiko; Tsurumi, Hiroshi; Itoh, Nobuyuki

68

CMOS RAM cosmic-ray-induced-error-rate analysis  

NASA Technical Reports Server (NTRS)

A significant number of spacecraft operational anomalies are believed to be associated with cosmic-ray-induced soft errors in the LSI memories. Test programs using a cyclotron to simulate cosmic rays have established conclusively that many common commercial memory types are vulnerable to heavy-ion upset. A description is given of the methodology and the results of a detailed analysis for predicting the bit-error rate in an assumed space environment for CMOS memory devices. Results are presented for three types of commercially available CMOS 1,024-bit RAMs. It was found that the HM6508 is susceptible to single-ion induced latchup from argon and krypton ions. The HS6508 and HS6508RH and the CDP1821 apparently are not susceptible to single-ion induced latchup.

Pickel, J. C.; Blandford, J. T., Jr.

1981-01-01

69

A 90 MHz CMOS RISC CPU designed for sustained performance  

Microsoft Academic Search

A CMOS CPU which operates at 90 MHz under typical conditions and implements an existing RISC (reduced-instruction-set-computer) 140-instruction set is described. The processor has been designed for sustained performance for workstation and both commercial and technical multiuser applications. Key performance features include a 3-ns, 32-b adder; low-skew on-chip clock buffers; and cycling off-chip caches at the operating frequency, using industry-standard

Darius Tanksalvala; Joel Lamb; Michael Buckley; B. Long; S. Chapin; J. Lotz; E. Delano; R. Luebs; K. Erskine; S. McMullen; M. Forsyth; R. Novak; T. Gaddis; D. Quarnstrom; C. Gleason; E. Rashid; D. Halperin; L. Sigel; H. Hill; C. Simpson; D. Hollenbeck; J. Spencer; R. Horning; H. Tran; T. Hotchkiss; D. Weir; D. Kipp; J. Wheeler; P. Knebel; J. Yetter; C. Kohlhardt

1990-01-01

70

An improved standard total dose test for CMOS space electronics  

Microsoft Academic Search

The postirradiation response of hardened and commercial CMOS devices is investigated as a function of total dose, dose rate, and annealing time and temperature. Cobalt-60 irradiation at about 200 rad(SiO2)\\/s followed by a one-week 100 deg C biased anneal and testing is shown to be an effective screen of hardened devices for space use. However, a similar screen and single-point

D. M. Fleetwood; P. S. Winokur; L. C. Riewe; R. L. Pease

1989-01-01

71

CMOS PIN fiber receiver and DVD OEIC  

Microsoft Academic Search

Two monolithically integrated PIN CMOS OEICs (optoelectronic integrated circuits) are presented: A high-speed CMOS PIN fiber receiver for optical data transmission and optical interconnects and a CMOS PIN OEIC for optical storage systems. Both OEICs were integrated in a 1.0 ?m twin-well CMOS-process, using PIN-photodiodes as photodetectors. For the high-speed fiber receiver a NRZ data rate of 622 Mbit\\/s is

A. Ghazi; T. Heide; H. Zimmermann; P. Seegebrecht

1999-01-01

72

Fabrication and characterization of CMOS-MEMS thermoelectric micro generators.  

PubMed

This work presents a thermoelectric micro generator fabricated by the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 ?V at the temperature difference of 1 K. PMID:22205869

Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

2010-01-01

73

A perspective on CMOS technology trends  

Microsoft Academic Search

Integrated circuit technology continues to evolve at a rapid pace, driven by the requirements of new applications for electronics of higher performance at ever lower cost. The attributes of CMOS technology in a ULSI environment are an ideal match to these requirements; thus CMOS is becoming the ubiquitous integrated circuit technology. The main feature of CMOS is the existence of

W. C. Holton; R. K. Cavin

1986-01-01

74

CMOS Integrated Carbon Nanotube Sensor  

SciTech Connect

Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A. [Grupo MEMS, Comision Nacional de Energia Atomica, Buenos Aires (Argentina); Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S. [Dpto. de Ing. Electrica y de Computadoras, Universidad Nacional del Sur, Bahia Blanca (Argentina); Buffa, F. A. [INTEMA Facultad de Ingenieria, Universidad Nacional de Mar del Plata, Mar del Plata (Argentina)

2009-05-23

75

Hybrid CMOS SiPIN detectors as astronomical imagers  

NASA Astrophysics Data System (ADS)

Charge Coupled Devices (CCDs) have dominated optical and x-ray astronomy since their inception in 1969. Only recently, through improvements in design and fabrication methods, have imagers that use Complimentary Metal Oxide Semiconductor (CMOS) technology gained ground on CCDs in scientific imaging. We are now in the midst of an era where astronomers might begin to design optical telescope cameras that employ CMOS imagers. The first three chapters of this dissertation are primarily composed of introductory material. In them, we discuss the potential advantages that CMOS imagers offer over CCDs in astronomical applications. We compare the two technologies in terms of the standard metrics used to evaluate and compare scientific imagers: dark current, read noise, linearity, etc. We also discuss novel features of CMOS devices and the benefits they offer to astronomy. In particular, we focus on a specific kind of hybrid CMOS sensor that uses Silicon PIN photodiodes to detect optical light in order to overcome deficiencies of commercial CMOS sensors. The remaining four chapters focus on a specific type of hybrid CMOS Silicon PIN sensor: the Teledyne Hybrid Visible Silicon PIN Imager (HyViSI). In chapters four and five, results from testing HyViSI detectors in the laboratory and at the Kitt Peak 2.1m telescope are presented. We present our laboratory measurements of the standard detector metrics for a number of HyViSI devices, ranging from 1k1k to 4k4k format. We also include a description of the SIDECAR readout circuit that was used to control the detectors. We then show how they performed at the telescope in terms of photometry, astrometry, variability measurement, and telescope focusing and guiding. Lastly, in the final two chapters we present results on detector artifacts such as pixel crosstalk, electronic crosstalk, and image persistence. One form of pixel crosstalk that has not been discussed elsewhere in the literature, which we refer to as Interpixel Charge Transfer (IPCT), is introduced. This effect has an extremely significant impact on x-ray astronomy. For persistence, a new theory and accompanying simulations are presented to explain latent images in the HyViSI. In consideration of these artifacts and the overall measured performance, we argue that HyViSI sensors are ready for application in certain regimes of astronomy, such as telescope guiding, measurements of fast planetary transits, and x-ray imaging, but not for others, such as deep field imaging and large focal plane astronomical surveys.

Simms, Lance Michael

76

RF-CMOS performance trends  

Microsoft Academic Search

The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance

Pierre H. Woerlee; Mathijs J. Knitel; Ronald van Langevelde; Dirk B. M. Klaassen; Luuk F. Tiemeijer; Andries J. Scholten; A. T. A. Zegers-van Duijnhoven

2001-01-01

77

Dark current study for CMOS fully integrated-PIN-photodiodes  

NASA Astrophysics Data System (ADS)

PIN photodiodes are semiconductor devices widely used in a huge range of applications, such as photoconductors, charge-coupled devices and pulse oximeters for medical applications. The possibility to combine and to integrate the fabrication of the sensor with its signal conditioning circuitry in a CMOS process allows device miniaturization in addition to enhance its properties lowering the production and assembly costs. This paper presents the design and characterization of silicon based PIN photodiodes integrated in a CMOS commercial process. A high-resistivity, low impurity substrate is chosen as the start material for the PIN photodiode array fabrication in order to fabricate devices with a minimum dark current. The dark current is studied, analyzed and measured for two different starting materials and for different geometries. A model previously proposed is reviewed and compared with experimental data.

Teva, Jordi; Jessenig, Stefan; Jonak-Auer, Ingrid; Schrank, Franz; Wachmann, Ewald

2011-05-01

78

A Brief Discussion of Radiation Hardening of CMOS Microelectronics  

SciTech Connect

Commercial microchips work well in their intended environments. However, generic microchips will not fimction correctly if exposed to sufficient amounts of ionizing radiation, the kind that satellites encounter in outer space. Modern CMOS circuits must overcome three specific concerns from ionizing radiation: total-dose, single-event, and dose-rate effects. Minority-carrier devices such as bipolar transistors, optical receivers, and solar cells must also deal with recombination-generation centers caused by displacement damage, which are not major concerns for majority-carrier CMOS devices. There are ways to make the chips themselves more resistant to radiation. This extra protection, called radiation hardening, has been called both a science and an art. Radiation hardening requires both changing the designs of the chips and altering the ways that the chips are manufactured.

Myers, D.R.

1998-12-18

79

A CMOS enhanced solid-state nanopore based single molecule detection platform.  

PubMed

Solid-state nanopores have emerged as a single molecule label-free electronic detection platform. Existing transimpedance stages used to measure ionic current nanopores suffer from dynamic range limitations resulting from steady-state baseline currents. We propose a digitally-assisted baseline cancellation CMOS platform that circumvents this issue. Since baseline cancellation is a form of auto-zeroing, the 1/f noise of the system is also reduced. Our proposed design can tolerate a steady state baseline current of 10A and has a usable bandwidth of 750kHz. Quantitative DNA translocation experiments on 5kbp DNA was performed using a 5nm silicon nitride pore using both the CMOS platform and a commercial system. Comparison of event-count histograms show that the CMOS platform clearly outperforms the commercial system, allowing for unambiguous interpretation of the data. PMID:24109650

Chen, Chinhsuan; Yemenicioglu, Sukru; Uddin, Ashfaque; Corgliano, Ellie; Theogarajan, Luke

2013-01-01

80

A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass  

PubMed Central

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 ?m CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 ?m CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

81

A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.  

PubMed

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 ?m CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 ?m CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

82

Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units  

SciTech Connect

One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing. In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.

Smith, J.H.; Ellis, J.R.; Montague, S.; Allen, J.J.

1997-03-01

83

Integration of solid-state nanopores in a 0.5 ?m CMOS foundry process  

NASA Astrophysics Data System (ADS)

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductors 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Uddin, A.; Yemenicioglu, S.; Chen, C.-H.; Corigliano, E.; Milaninia, K.; Theogarajan, L.

2013-04-01

84

Integration of solid-state nanopores in a 0.5?m CMOS foundry process.  

PubMed

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+polysilicon/SiO2/n+polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

85

Integration of solid-state nanopores in a 0.5 ?m cmos foundry process  

PubMed Central

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductors 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

86

Latest results of the R&D on CMOS MAPS for the Layer0 of the SuperB SVT  

NASA Astrophysics Data System (ADS)

Physics and high background conditions set very challenging requirements on readout speed, material budget and resolution for the innermost layer of the SuperB Silicon Vertex Tracker operated at the full luminosity. Monolithic Active Pixel Sensors (MAPS) are very appealing in this application since the thin sensitive region allows grinding the substrate to tens of microns. Deep N-Well MAPS, developed in the ST 130 nm CMOS technology, achieved in-pixel sparsification and fast time stamping. Further improvements are being explored with an intense R&D program, including both vertical integration and 2D MAPS with the INMAPS quadruple well. We present the results of the characterization with IR laser, radioactive sources and beam of several chips produced with the 3D (Chartered/Tezzaron) process. We have also studied prototypes exploiting the features of the quadruple well and the high resistivity epitaxial layer of the INMAPS 180 nm process. Promising results from an irradiation campaign with neutrons on small matrices and other test-structures, as well as the response of the sensors to high energy charged tracks are presented.

Balestri, G.; Batignani, G.; Beck, G.; Bernardelli, A.; Berra, A.; Bettarini, S.; Bevan, |A.; Bombelli, L.; Bosi, F.; Bosisio, L.; Casarosa, G.; Ceccanti, M.; Cenci, R.; Citterio, M.; Coelli, S.; Comotti, D.; Dalla Betta, G.-F.; Fabbri, L.; Fiorini, C.; Fontana, G.; Forti, F.; Gabrielli, A.; Gaioni, L.; Gannaway, F.; Giorgi, F.; Giorgi, M. A.; Lanceri, L.; Liberali, V.; Lietti, D.; Lusiani, A.; Mammini, P.; Manazza, A.; Manghisoni, M.; Monti, M.; Morris, J.; Morsani, F.; Nasri, B.; Neri, N.; Oberhof, B.; Palombo, F.; Pancheri, L.; Paoloni, E.; Pellegrini, G.; Perez, A.; Petragnani, G.; Prest, M.; Povoli, M.; Profeti, A.; Quartieri, E.; Rashevskaya, I.; Ratti, L.; Re, V.; Rizzo, G.; Sbarra, C.; Semprini-Cesari, N.; Soldani, A.; Stabile, A.; Stella, C.; Traversi, G.; Valentinetti, S.; Verzellesi, G.; Villa, M.; Vitale, L.; Walsh, J.; Wilson, F.; Zoccoli, A.; Zucca, S.

2013-12-01

87

CMOS RF Power Amplifier Design for Wireless Communications  

E-print Network

power, while the electronic isolation of the transformersPower Ratio CE Consumer Electronic CMOS Complementary Metal-Oxide-Semiconductor CMOS+ Post-CMOS backend process module DAT Distributive Active Transformer

FANG, Qiang

2012-01-01

88

A CCD\\/CMOS image motion sensor  

Microsoft Academic Search

Presents a 1D image motion sensor with a 115-pixel linear image sensor and analog CCD\\/CMOS processors that correlates two image frames that are spatially shifted between -5 and +5 pixels, to estimate object motion over a range of 1 to 5000 pixels\\/s. The CCD\\/CMOS smart sensor chip is fabricated with a standard double poly, double metal, 2-?m CMOS\\/CCD process available

Massimo Gottardi; Woodward Yang

1993-01-01

89

High Resolution CMOS Current Comparators  

Microsoft Academic Search

A 2m CMOS current comparator prototype is presented with an input current comparison range of 140dB and virtual zero offset(?10pA). The circuit uses capacitive sensing for high resolution and nonlinear feedback to achieve small input voltage variations in the complete input current range. Operation speed for low current is abot two orders of magnitude larger than for conventional circuits. Simplified

R. Dominguez-Castro; A. Rodriguez-Vazquez; F. Medeiro; J. L. Huertas

1992-01-01

90

New package for CMOS sensors  

Microsoft Academic Search

Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low

Jean-Luc Diot; Kum Weng Loo; Jean-Pierre Moscicki; Hun Shen Ng; Tong Yan Tee; Jerome Teysseyre; Daniel Yap

2004-01-01

91

Radiation response of two Harris semiconductor radiation hardened 1k CMOS RAMs  

SciTech Connect

This paper describes the testing of two types 1K CMOS static RAMs in various transient and steady state ionizing radiation environments. Type HM 6551R (256x4 bits) and type HM 6508R (1024x1 bit) RAMs were evaluated. The RAMs are radiation hardened versions of Harris' commercial RAMs. A brief description of the radiation hardened process is presented.

Abare, W.E.; Huffman, D.D.; Moffett, G.E.

1982-12-01

92

A CMOS image sensor for low light applications Honghao Ji, Pamela A. Abshire  

E-print Network

A CMOS image sensor for low light applications Honghao Ji, Pamela A. Abshire Department pixel for high speed, low light imaging applications. The new pixel achieves lower dark current integration node. An image sensor with a 256 ? 256 array of these pixels was designed for a commercially

Maryland at College Park, University of

93

Charge-coupled CMOS and hybrid detector arrays  

NASA Astrophysics Data System (ADS)

Over a decade has passed since complementary metal oxide semiconductor (CMOS) imaging detectors made their move into the charge-coupled device (CCD) arena. Low cost, low power, on-chip system integration, high-speed operation and tolerance to high-energy radiation sources are unique features that make CMOS detectors popular. However, it remains unclear if CMOS arrays can compete with the CCD in high performance applications (e.g., scientific). This paper compares fundamental performance parameters common to both CMOS and CCD imagers, and lists specific SMOS performance deficiencies that prevent the technology from high end use. In this paper we will present custom CMOS pixel designs and related fabrication processes that solve most deficiencies. We will also discuss "hybrid" imaging arrays that marry the advantages of CCD and CMOS producing sensors with superior performance in comparison to CCD and CMOS bulk monolithic sensors. CCD to CMOS, CMOS to CMOS and CMOS SOI hybrids are reviewed.

Janesick, James R.

2004-01-01

94

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices  

NASA Technical Reports Server (NTRS)

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

95

Hinged polysilicon structures with integrated CMOS TFTs  

Microsoft Academic Search

The surface micromachining process described can produce a variety of microelectromechanical components, including CMOS thin film transistors and three dimensional polysilicon structures with large features and high detail in all three dimensions. Polysilicon structural elements are made with integrated hinges, which allow three dimensional structures to be erected out of the plane of the wafer. CMOS transistors are integrated directly

Kristofer S. J. Pister

1992-01-01

96

Thermoelectric infrared sensors by CMOS technology  

Microsoft Academic Search

The authors report two integrated thermoelectric infrared sensors on thin silicon oxide\\/nitride microstructures realized by industrial CMOS IC technology, followed by one compatible single maskless anisotropic etching step. No additional material is needed to enhance infrared absorption since the passivation layer, as provided by the CMOS process, is sufficient for certain spectral bands. The responsivities are between 12 and 28

Rene Lenggenhager; Henry Baltes; Jon Peer; Martin Forster

1992-01-01

97

Accelerated life testing effects on CMOS microcircuit characteristics  

NASA Technical Reports Server (NTRS)

Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

1977-01-01

98

Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics  

SciTech Connect

Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm{sup 2} with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensors are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.

Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka; Pithawa, C. K. [Centre for Microelectronics, Prabhadevi, Mumbai-400028 (India)

2011-10-20

99

Integrated Microphone with CMOS Circuits on a Single Chip  

NASA Astrophysics Data System (ADS)

A miniature diaphragm microphone having sensitivity to acoustic signals at the level of conversational speech has successfully been integrated with CMOS circuits on a single chip. The microphone is built on 1.4 ?m thick LPCVD silicon nitride diaphragm (2 x 2 mm^2 in size) with electrodes and ZnO piezoelectric film to transduce mechanical deformation into electrical charge. The CMOS amplifier put next to the microphone on a single chip has a gain of 491, flat in audio frequency range with 3-dB frequency being 18 kHz. The total number of transistors integrated in an amplifier is more than 300. The amplified sensitivity of the integrated microphone with a gain of 491 is 1.5 mV/mu bar when excited by sound waves at 1 kHz with the sensitivity variation from 100 Hz to 20 kHz being approximately 9 dB. The integrated microphone has been fabricated through an interactive joint process between a commercial CMOS foundry and a university lab. It is the first to demonstrate an integration of a microphone with CMOS circuits on a single chip. Theory of the integrated microphone has been developed through combining mechanics, piezoelectricity and circuit theory. Also developed are theoretical optimizations for sensitivity-bandwidth product and signal-to-noise ratio. A new processing technique to align features on the front side of a wafer to those on its backside has been developed for bulk micromachining. A tiny (30 mum-square and 1.6 ?m -thick) diaphragm serves as an alignment pattern. At the same time that the alignment diaphragm is made, much thicker, large-area diaphragms can be partially etched using "mesh" masking patterns in these area. The mesh-masking technique exploits the etch-rate differences between (100) and (111) planes to control the depths reached by etch pits in selected areas. The large, partially etched diaphragms (2 to 3 mm squares roughly 100 ?m thick) are sufficiently robust to survive subsequent IC-processing steps in a silicon-foundry environment. The thin alignment diaphragm can be processed through these steps because of its very small area. The partially etched diaphragms can be reduced to useful thicknesses in a final etch step after the circuits have been fabricated. This technique was successfully employed to fabricate microphones and on-chip CMOS circuits.

Kim, Eun Sok

1990-01-01

100

Integrated RF MEMS/CMOS Devices  

E-print Network

A maskless post-processing technique for CMOS chips is developed that enables the fabrication of RF MEMS parallel-plate capacitors with a high quality factor and a very compact size. Simulations and measured results are presented for several MEMS/CMOS capacitors. A 2-pole coupled line tunable bandpass filter with a center frequency of 9.5 GHz is designed, fabricated and tested. A tuning range of 17% is achieved using integrated variable MEMS/CMOS capacitors with a quality factor exceeding 20. The tunable filter occupies a chip area of 1.2 x 2.1 mm2.

Mansour, R R; Bakeri-Kassem, M

2008-01-01

101

Carbon Nanotube Integration with a CMOS Process  

PubMed Central

This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 ?m CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

2010-01-01

102

A CMOS-compatible compact display  

E-print Network

Portable information devices demand displays with high resolution and high image quality that are increasingly compact and energy-efficient. Microdisplays consisting of a silicon CMOS backplane integrated with light ...

Chen, Andrew R. (Andrew Raymond)

2005-01-01

103

Electrical Characteristics of Intraoral Dental Imaging Devices Based on the CMOS Imager Coupled with Integrated X-ray Conversion Fiber Optics  

Microsoft Academic Search

As a continuation of our digital X-ray imaging sensor R&D, we have developed a cost-effective, intraoral imaging device based on the CMOS photosensor array coupled with an integrated X-ray conversion fiber-optic faceplate. It consists of a commercially available CMOS photosensor of a 35 times 35 mum2 pixel size and a 688 times 910 pixel array dimension, and a high efficiency

Hyosung ChoandSungil Choi; Sungil Choi; Bongsoo Lee; Sin Kim

2006-01-01

104

CMOS \\/ CMOL architectures for spiking cortical column  

Microsoft Academic Search

We present a spiking cortical column model based on neural associative memory, and demonstrate architectures for emulating the cortical column model with nanogrid molecular circuitry. We investigate a number of options for cost-effective hardware with digital CMOS and mixed-signal CMOL, a hybrid CMOS\\/nanogrid technology. We also give an example of a dynamic learning algorithm that is a suitable match to

Changjian Gao; Mazad S. Zaveri; Dan W. Hammerstrom

2008-01-01

105

CMOS scaling into the nanometer regime  

Microsoft Academic Search

Starting with a brief review on 0.1-?m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect

Yuan Taur; DOUGLAS A. BUCHANAN; Wei Chen; DAVID J. FRANK; KHALID E. ISMAIL; Shih-Hsien Lo; G. A. Sai-Halasz; R. G. Viswanathan; H.-J. C. Wann; S. J. Wind; Hon-Sum Wong

1997-01-01

106

CMOS imager technology shrinks and image performance  

Microsoft Academic Search

In this paper, we present a performance summary of CMOS imager pixels from 5.2 ?m to 4.2 ?m using 0.18 ?m imager design rules, then to 3.2 ?m using 0.15 ?m imager design rules. These pixels support 1.3-megapixel, 2.0-megapixel, and 3.1-megapixel CMOS image sensors for digital still cameral (DSC) applications at 3.3 V, respectively. The 4TC pixels are all based

H. Rhodes; G. Agranov; C. Hong; U. Boettiger; R. Mauritzson; J. Ladd; I. Karasev; J. McKee; E. Jenkins; W. Quinlin; I. Patrick; J. Li; X. Fan; R. Panicacci; S. Smith; C. Mouli; J. Bruce

2004-01-01

107

Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments  

E-print Network

CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity epitaxial layers leads to the better radiation hardness and allows the implementation of accelerated readout circuits. The TowerJazz $0.18 \\mu m$ CMOS process being one of the most relevant examples recently became of interest for several future detector projects. The most imminent of these project is an upgrade of the Inner Tracking System (ITS) of the ALICE detector at LHC. It will be followed by the Micro-Vertex Detector (MVD) of the CBM experiment at FAIR. Other experiments like ILD consider CPS as one of the viable options for flavour tagging and tracking sub-systems.

Serhiy Senyukov; Jerome Baudot; Auguste Besson; Giles Claus; Loic Cousin; Wojciech Dulinski; Mathieu Goffe; Boris Hippolyte; Robert Maria; Levente Molnar; Xitzel Sanchez Castro; Marc Winter

2014-02-10

108

Low-voltage log-domain signal processing in CMOS and BiCMOS  

Microsoft Academic Search

This paper presents the most important properties of log-domain filters for the realization of low-voltage and low power analog signal processing circuits. The noise behavior is discussed and the advantage of the combination of companding and class AB operation is highlighted. Examples of BiCMOS and CMOS realizations operating at supply voltages as low as 1 V are presented

Christian Enz; Manfred Punzenberger; Dominique Python

1999-01-01

109

Radiation damages in CMOS image sensors: testing and hardening challenges brought by deep sub-micrometer CIS processes  

Microsoft Academic Search

This paper presents a summary of the main results we observed after several years of study on irradiated custom imagers manufactured using 0.18 mum CMOS processes dedicated to imaging. These results are compared to irradiated commercial sensor test results provided by the Jet Propulsion Laboratory to enlighten the differences between standard and pinned photodiode behaviors. Several types of energetic particles

Vincent Goiffon; Cdric Virmontois; Pierre Magnan; Paola Cervantes; Franck Corbire; Magali Estribeau; Philippe Pinel

2010-01-01

110

A CMOS Smart Temperature and Humidity Sensor with Combined Readout  

PubMed Central

A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 ?m CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 ?A. PMID:25230305

Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

2014-01-01

111

Fabrication and characterization of CMOS-MEMS magnetic microsensors.  

PubMed

This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5-200 mT. PMID:24172287

Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

112

Low-loss and low-crosstalk 8 8 silicon nanowire AWG routers fabricated with CMOS technology.  

PubMed

Low-loss and low-crosstalk 8 8 arrayed waveguide grating (AWG) routers based on silicon nanowire waveguides are reported. A comparative study of the measurement results of the 3.2 nm-channel-spacing AWGs with three different designs is performed to evaluate the effect of each optimal technique, showing that a comprehensive optimization technique is more effective to improve the device performance than a single optimization. Based on the comprehensive optimal design, we further design and experimentally demonstrate a new 8-channel 0.8 nm-channel-spacing silicon AWG router for dense wavelength division multiplexing (DWDM) application with 130 nm CMOS technology. The AWG router with a channel spacing of 3.2 nm (resp. 0.8 nm) exhibits low insertion loss of 2.32 dB (resp. 2.92 dB) and low crosstalk of -20.5~-24.5 dB (resp. -16.9~-17.8 dB). In addition, sophisticated measurements are presented including all-input transmission testing and high-speed WDM system demonstrations for these routers. The functionality of the Si nanowire AWG as a router is characterized and a good cyclic rotation property is demonstrated. Moreover, we test the optical eye diagrams and bit-error-rates (BER) of the de-multiplexed signal when the multi-wavelength high-speed signals are launched into the AWG routers in a system experiment. Clear optical eye diagrams and low power penalty from the system point of view are achieved thanks to the low crosstalk of the AWG devices. PMID:24787827

Wang, Jing; Sheng, Zhen; Li, Le; Pang, Albert; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Qi, Minghao; Gan, Fuwan

2014-04-21

113

RF CMOS UWB transmitter and receiver front-end design  

E-print Network

The low-cost low-power complementary metal-oxide semiconductor (CMOS) ultra wideband (UWB) transmitter and receiver front-ends based on impulse technology were developed. The CMOS UWB pulse generator with frequency-band tuning capability...

Miao, Meng

2009-05-15

114

New package for CMOS sensors  

NASA Astrophysics Data System (ADS)

Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

2004-02-01

115

A 54-mW 8-Gbit/s VCSEL driver in a 65-nm CMOS technology  

NASA Astrophysics Data System (ADS)

We report a VCSEL driver ASIC designed and fabricated in a commercial 65-nm CMOS process. At 8 Gbps, the eye diagram passes the eye mask test and the bit-error-rate is less than 10-12 at the 95% confidence level. The total power consumption (including VCSEL) is about 54 mW, less than 1/4 of our previous VCSEL driver ASIC in a silicon-on-sapphire CMOS technology. The VCSEL driver has been tested in a neutron beam with the maximum energy of 800 MeV and the cross section has been estimated to be less than 3.14 10-11 cm2.

Liang, F.; Lu, W.; Chen, J.; Deng, B.; Gong, D.; Guo, D.; Jin, G.; Li, X.; Liang, H.; Liu, C.; Liu, G.; Wang, Z.; Xiang, A.; Xu, T.; Ye, J.; Liu, T.

2014-01-01

116

LOW VOLTAGE ANALOG CIRCUITS USING STANDARD CMOS TECHNOLOGY  

E-print Network

are incompatible with the CMOS technology trends of the future. Ways to circumvent this conflict are to develop, or develop circuit techniques that are compatible with future standard CMOS technology trends. This paperLOW VOLTAGE ANALOG CIRCUITS USING STANDARD CMOS TECHNOLOGY Phillip E. Allen, Benjamin J. Blalock

Rincon-Mora, Gabriel A.

117

A Standard CMOS Humidity Sensor without Post-Processing  

PubMed Central

A 2 ?W power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 802310 humidity-sensitive layer, and a CMOS capacitance to voltage converter. PMID:22163949

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2011-01-01

118

Evaluation of a CMOS image detector for low-cost and power medical x-ray imaging applications  

NASA Astrophysics Data System (ADS)

Recent developments in CMOS image detectors are changing the way digital imaging is performed for many applications. The replacement of charge coupled devices (CCDs), with CMOS detectors is a desirable paradigm shift that will depend on the ability to match the high performance characteristics of CCDs. Digital X-ray imaging applications (chest X-ray, mammography) would benefit greatly from this shift because CMOS detectors have the following inherent characteristics: (1) Low operating power (5 - 10 times lower than CCD/processing electronics). (2) Standard CMOS manufacturing process (CCD requires special manufacturing). (3) On-chip integration of analog/digital processing functions (difficult with CCD). (4) Low Cost (5 - 10 times lower cost than CCD). The achievement of both low cost and low power is highly desirable for portable applications as well as situations where large, expensive X-ray imaging machines are not feasible (small hospitals and clinics, emergency medical vehicles, remote sites). Achieving this goal using commercially available components would allow rapid development of such digital X-ray systems as compared with the development difficulties incurred through specialized direct detectors and systems. The focus of this paper is to evaluate a CMOS image detector for medical X-ray applications and to demonstrate the results obtained from a prototype CMOS digital X-ray camera. Results from the images collected from this optically-coupled camera are presented for a particular lens, X-ray conversion screen, and demagnification factor. Further, an overview of the overall power consumption and cost of a multi-sensor CMOS mosaic compared to its CCD counterpart are also reported.

Smith, Scott T.; Bednarek, Daniel R.; Wobschall, Darold C.; Jeong, Myoungki; Kim, Hyunkeun; Rudin, Stephen

1999-05-01

119

Investigation of Fast Switched CMOS Inverter using  

E-print Network

Inverter is truly the nucleus of electronics industry. It is the main building block of everyday appliances i.e. microwaves, power tools, battery chargers, air conditioners and computers etc. In this paper, CMOS technology has been chosen to study the transient and dc characteristics of an inverter. Feature size is the main parameter to study the voltage transfer characteristics of inverter, for which length and width of transistors is varied. Further, CMOS inverters can be paralleled for increased power to drive higher current loads. Simulations are run on cadence design tool and the schematic diagrams are drawn in virtuoso schematic editor using 180nm technology file.

Navneet Kaur; Guru Nanak; Dev Engineering; Gurpurneet Kaur; Chahat Jain; Guru Nanak; Dev Engineering

120

Optical addressing technique for a CMOS RAM  

NASA Technical Reports Server (NTRS)

Progress on optically addressing a CMOS RAM for a feasibility demonstration of free space optical interconnection is reported in this paper. The optical RAM chip has been fabricated and functional testing is in progress. Initial results seem promising. New design and SPICE simulation of optical gate cell (OGC) circuits have been carried out to correct the slow fall time of the 'weak pull down' OGC, which has been characterized experimentally. Methods of reducing the response times of the photodiodes and the associated circuits are discussed. Even with the current photodiode, it appears that an OGC can be designed with a performance that is compatible with a CMOS circuit such as the RAM.

Wu, W. H.; Bergman, L. A.; Allen, R. A.; Johnston, A. R.

1988-01-01

121

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors  

PubMed Central

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

122

SPICE analysis of the SEU sensitivity of a fully depleted SOI CMOS SRAM cell  

SciTech Connect

Fully depleted silicon-on-insulator (SOI) technologies are of interest for commercial applications as well as for use in harsh (radiation-intensive) environments. In both types of application, effects of charged particles (single-event effects) are of concern. Here, SPICE analysis of SEU sensitivity of a 6-T SRAM cell using commercially-representative fully depleted SOI CMOS technology parameters indicates that reduction of the minority carrier lifetime (parasitic bipolar gain) and use of thinner silicon can significantly reduce SEU sensitivity.

Alles, M.L. (Ibis Technology Corporation, Danvers, MA (United States))

1994-12-01

123

Low-voltage log-domain signal processing in CMOS and BiCMOS  

Microsoft Academic Search

This paper presents the most important properties of log-domain filters for the realization of low-voltage (LV) and low-power (LP) analog signal processing circuits. The noise behavior is briefly discussed and the advantage of the combination of companding and class AB operation is highlighted. Examples of BiCMOS and standard digital CMOS realizations operating at supply voltages as low as 1 V

C. C. Enz; M. Punzenberger; D. Python

1997-01-01

124

III V CMOS:III-V CMOS: A sub-10 nm Electronics Technology?gy  

E-print Network

Microsystems Technology Laboratories, MIT AVS 57th International Symposium & Exhibition October 17-22, 2010 microprocessors Intel microprocessors 3 #12;Recent trend in CMOS scaling · Si CMOS has entered era of "power nm)- InAs core (tInAs = 5 nm) - InGaAs cladding - n Hall = 13,200 cm2/V-secn,Hall 13,200 cm /V sec

del Alamo, Jesús A.

125

A fully integrated CMOS chopper amplifier  

Microsoft Academic Search

A CMOS chopper amplifier that achieves reduced input offset voltage and fast overload recovery time while maintaining bandwidths comparable to conventional operational amplifiers and requiring no external components is presented. The chopper amplifier consists of two folded cascode operational transconductance amplifiers (OTA) connected in a switched feed-forward configuration, and a third OTA that is used to realize a large capacitive

Doug Garrity; Jenkuan Young; Don Thelen

1991-01-01

126

ALU design using reconfigurable CMOS logic  

Microsoft Academic Search

In designing ALUs, many techniques have been followed. The functional units of an ALU have been realized using conventional transistors and pass transistor gates. In this paper, we present the design of a 4 bit ALU using multi-input floating gate (MIFG) CMOS reconfigurable logic. It has been designed in a 1.5 ?m technology for 3 V operation. The ALU can

A. Srivastava; C. Srinivasan

2002-01-01

127

Switch level optimization for CMOS circuits  

E-print Network

In this report, 'Input vs Path Matrix 'Techique' and 'Node vs Input Matrix Technique' techniques for reducing transistor count in the pull-up and the pull-down array of CMOS circuits are proposed. Also, algorithms for optimization of both the pull...

Chugh, Pankaj Pravinkumar

2012-06-07

128

Simulation of SEU transients in CMOS ICs  

Microsoft Academic Search

An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combinational logic circuits to SEU. SITA is described in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used

N. Kaul; B. L. Bhuva; S. E. Kerns

1991-01-01

129

A study on CMOS negative resistance circuits  

Microsoft Academic Search

An in-depth study of CMOS transconductor designed negative resistance circuits is presented. Important large signal and small signal characteristics including noise, stability and bandwidth are investigated. A strategy of designing large bandwidth active resistors is proposed with supporting analysis. Key stability issues that have not previously been reported are discussed. Finally, applications which include the design of a low phase

Vishal Patel; R. Raut

2008-01-01

130

Predictive Oscillation Based Test of CMOS circuits  

Microsoft Academic Search

Two different CMOS circuits has been used to check the predictive oscillation based test (POBT) approach, combined with supply current monitoring technique. These circuits are a two stage op amp and a biquad filter composed by two transconductance amplifiers (OTA). The combination of both techniques has given excellent results in predicting the main performance parameters of the circuits as DC

K. Suenaga; E. Isern; R. Picos; S. Bota; M. Roca; E. Garcia-Moreno

2006-01-01

131

Micropower CMOS temperature sensor with digital output  

Microsoft Academic Search

A CMOS smart temperature sensor with digital output is presented. It consumes only 7 ?W. To achieve this extremely low-power consumption, the system is equipped with a facility that switches off the supply power after each sample. The circuit uses substrate bipolars as a temperature sensor. Conversion to the digital domain is done by a sigma-delta converter which makes the

Anton Bakker; J. H. Huijsing

1996-01-01

132

CMOS Compatible Nanoscale Nonvolatile Resistance Switching  

E-print Network

) inside the a-Si matrix at positive (negative) applied voltages.3-5 Such M/a-Si/M devices, however, need involves standard CMOS processes only, with the exception that the active device area is defined with electron-beam lithography to test the smallest devices. The cross-sectional image of a fabri- cated device

Lu, Wei

133

Statistical power analysis for nanoscale CMOS  

Microsoft Academic Search

With the scaling down of CMOS technology, process variations are becoming significant. Power consumption is a major constraint on IC yield. However, there has been little research on statistical power analysis compared with that on timing analysis. Here, both the static and dynamic power are considered. We characterize a cell library containing mean power. A standard deviation power library is

Yangang Wang; Michael Merrett; Mark Zwolinski

2010-01-01

134

An integrated CMOS microsystem for NMR applications  

Microsoft Academic Search

A monolithic CMOS microsystem for nuclear magnetic resonance applications has been designed and tested. It includes two planar microcoils and a complete readout electronics with a single 3.3 V supply. It measures static fields around 1 T with a field resolution better than 1 ppm\\/?Hz. The probe can also be used for NMR spectroscopy with a spectral resolution of 15

J. Frounchi; G. Boero; B. Furrer; P.-A. Besse; R. S. Popovic

2001-01-01

135

CMOS preamplifiers for detectors large and small  

SciTech Connect

We describe four CMOS preamplifiers developed for multiwire proportional chambers (MWPC) and silicon drift detectors (SDD) covering a capacitance range from 150 pF to 0.15 pF. Circuit techniques to optimize noise performance, particularly in the low-capacitance regime, are discussed.

O`Connor, P. [Brookhaven National Lab., Upton, NY (United States)

1997-12-31

136

Low energy CMOS for space applications  

NASA Technical Reports Server (NTRS)

The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

Panwar, Ramesh; Alkalaj, Leon

1992-01-01

137

A capacitor-free high PSR CMOS low dropout voltage regulator  

NASA Astrophysics Data System (ADS)

This paper presents a capacitor-free CMOS low dropout voltage regulator which has high PSR performance and low chip area. Pole splitting and gm boosting techniques are employed to achieve good stability. The capacitor-free chip LDO was fabricated in commercial 0.18 ?m CMOS technology provided by GSMC (Shanghai, China). Measured results show that the capacitor-free LDO has a stable output voltage 1.79 V, when supply voltage changes from 2.5 to 5 V, and the LDO is capable of driving maximum 100 mA load current. The LDO has high power supply rejection about -79 dB at low frequency and -40 dB at 1 MHz frequency, while sacrifice of the LDO's active chip-area is only smaller than 0.02 mm2.

Zhichao, Li; Yuntao, Liu; Zhangqu, Kuang; Jie, Chen

2014-06-01

138

Photodissociation channels for N2O near 130 nm studied by product imaging  

E-print Network

component of the earth's natural atmosphere, produced primarily by biological pro- cesses in soils and oceans. Mostly inert in the troposphere, it is transported to the stratosphere where it is destroyed both

Houston, Paul L.

139

Scatterometry measurement method for gate CD control of sub-130nm technology  

NASA Astrophysics Data System (ADS)

Recently, the scatterometry is becoming more and more popular as a inline metrology tool for lithography process control as well as etching process control because of the advantage of fast measurement with high accuracy. Especially, at the gate patterning that fabricates transistors, the scatterometry can be very powerful because it gives massive volume of CD (Critical Dimension) measurement data and gate poly profile, simultaneously. Those results could help to understand and forecast the performance of transistors. In order to achieve accurate and consistent measurement results by scatterometry, the setup of stable model and library is very crucial since it has nature of indirect measurement. For example, as defining of substrate conditions, modeling range of parameters, target values and type of models, scatterometry (in this paper, we call as OCD; Optical CD) gives different results even if we use same data basis. In this paper we have shown the best practice how to optimize variables of scatterometry to get accurate and stable results. We used the OCD(Optic CD: Accent CDS200) angular scatterometry system which can rotate HeNe laser light source from -47 to +47 degree. In order to investigate the substrate dependency, various silicon wafer substrates having periodic patterned with different materials such as photoresist, BARC, poly silicon, and thermal oxide film has been used. Finally, we observed OCD has the excellent capability for inline process controllability.

Jang, Jeongyeol; Kwak, Sungho; Lee, Karl; Kim, Keeho; Park, Heongsu; Youn, James; Sohn, Lucas

2005-05-01

140

IR CMOS: infrared enhanced silicon imaging  

NASA Astrophysics Data System (ADS)

SiOnyx has developed visible and infrared CMOS image sensors leveraging a proprietary ultrafast laser semiconductor process technology. This technology demonstrates 10 fold improvements in infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Furthermore, these sensitivity enhancements are achieved on a focal plane with state of the art noise performance of 2 electrons/pixel. By capturing light in the visible regime as well as infrared light from the night glow, this sensor technology provides imaging in daytime through twilight and into nighttime conditions. The measured 10x quantum efficiency at the critical 1064 nm laser node enables see spot imaging capabilities in a variety of ambient conditions. The spectral sensitivity is from 400 to 1200 nm.

Pralle, M. U.; Carey, J. E.; Haddad, Homayoon; Vineis, C.; Sickler, J.; Li, X.; Jiang, J.; Sahebi, F.; Palsule, C.; McKee, J.

2013-06-01

141

Critical charge concepts for CMOS SRAMs  

SciTech Connect

The dramatic effects of external circuit loading on the heavy-ion-induced charge-collection response of a struck transistor are illustrated using three-dimensional mixed-mode simulations. Simulated charge-collection and SEU characteristics of a CMOS SRAM cell indicate that, in some cases, more charge can be collected at sensitive nodes from strikes that do not cause upset than from strikes that do cause upset. Computations of critical charge must taken into account the time during which charge is collected, not simply the total amount of charge collected. Model predictions of the incident linear energy transfer required to cause upset agree well with measured data for CMOS SRAMs, without parameter adjustments. The results show the absolute necessity of treating circuit effects in any realistic device simulation of single-event upset (SEU) in SRAMs.

Dodd, P.E.; Sexton, F.W. [Sandia National Labs., Albuquerque, NM (United States)] [Sandia National Labs., Albuquerque, NM (United States)

1995-12-01

142

A CNN UNIVERSAL CHIP IN CMOS TECHNOLOGY  

Microsoft Academic Search

This paper describes the design of a programmable Cellular Neural Network (CNN) chip,with added functionalities similar to those of the CNN Universal Machine. The prototype contains1024 cells and has been designed in a 1.0|m, n-well CMOS technology. Careful selectionof the topology and design parameters has resulted in a cell density of 31 cells\\/mm2and around7-8 bits accuracy in the weight values.

S. ESPEJO; R. Domnguez-Castro; R. Carmona; A. RODRGUEZ-VZQUEZ

1996-01-01

143

Battery-powered digital CMOS design  

Microsoft Academic Search

In this paper we study tradeoffs between energy dissipation and delay in battery-powered digital CMOS designs. In contrast to previous work, we adopt an integrated model of the VLSI circuit and the battery sub-system that powers it. We show that accounting for the dependence of battery capacity on the average discharge current changes shape of the energy-delay trade-off curve and

Massoud Pedram; Qing Wu

1999-01-01

144

RF-CMOS oscillators with switched tuning  

Microsoft Academic Search

Fully integrated CMOS oscillators are of great interest for use in single-chip wireless transceivers. In most oscillator circuits reported to date that operate in the 0.9 to 2 GHz frequency range, an integrated spiral inductor sets the frequency. It is generally believed that an LC oscillator, even when it uses a low-Q inductor, displays a lower phase noise than a

A. Kral; F. Behbahani; A. A. Abidi

1998-01-01

145

Analog Circuit Design in Nanoscale CMOS Technologies  

Microsoft Academic Search

As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic

Lanny L. Lewyn; Trond Ytterdal; Carsten Wulff; Kenneth Martin

2009-01-01

146

Critical charge concepts for CMOS SRAMs  

Microsoft Academic Search

The dramatic effects of external circuit loading on the heavy-ion-induced charge-collection response of a struck transistor are illustrated using three-dimensional mixed-mode simulations. Simulated charge-collection and SEU characteristics of a CMOS SRAM cell indicate that, in some cases, more charge call be collected at sensitive nodes from strikes that do not cause upset than from strikes that do cause upset. Computations

P. E. Dodd; F. W. Sexton

1995-01-01

147

Layout optimization of static CMOS functional cells  

Microsoft Academic Search

A general theory for designing minimum-area layouts of static series-parallel CMOS functional cells (also called complex gates) in a standard cell layout style is presented. T. Uehara and W.M. vanCleemput. (1981) originally formulated this as the graph optimization problem of finding the minimum number of dual trails that cover a multigraph model of M of a cell. The present theory

Robert L. Maziasz; John P. Hayes

1990-01-01

148

A CMOS interface IC for CCD imagers  

Microsoft Academic Search

A 2- mu m CMOS IC interfaces directly to the output of a CCD, level shifts the signal, amplifies it by a 4-bit programmable gain of up to 20 dB, and corrects the offset per pixel with a 3-bit word. A non-reset video output is obtained with an internal time-interleaved architecture. The total harmonic distortion (THD) of -50 dB is

K. Y. Kim; A. A. Abidi

1993-01-01

149

Noise modeling for RF CMOS circuit simulation  

Microsoft Academic Search

The RF noise in 0.18-?m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with

Andries J. Scholten; Luuk F. Tiemeijer; Ronald van Langevelde; Ramon J. Havens; A. T. A. Zegers-van Duijnhoven; Vincent C. Venezia

2003-01-01

150

Low noise CMOS micro-fluxgate magnetometer  

Microsoft Academic Search

We present a new two-axis fluxgate magnetometer fully integrated in CMOS technology. The magnetometer exhibits excellent sensitivity of 2700 V\\/T and the magnetic equivalent noise spectral density of 6nT\\/?Hz at 1 Hz. The total power consumption is as low as 35 m W from the single 5 V power supply. The low noise characteristic is obtained using the combination of

Predrag M. Drljaca; P. Kejik; F. Vincent; R. S. Popovic

2003-01-01

151

OPASYN: a compiler for CMOS operational amplifiers  

Microsoft Academic Search

A silicon compilation system for CMOS operational amplifiers (OPASYN) is discussed. The synthesis system takes as inputs system-level specifications, fabrication-dependent technology parameters, and geometric layout rules. It produces a design-rule-correct compact layout of an optimized operational amplifier. The synthesis proceeds in three stages: (1) heuristic selection of a suitable circuit topology; (2) parametric circuit optimization based on analytic models; and

Han Young Koh; Carlo H. Squin; Paul R. Gray

1990-01-01

152

Thermoelectric AC power sensor by CMOS technology  

Microsoft Academic Search

The authors report the development of a thermoelectric AC power sensor (thermoconverter) realized by industrial CMOS IC technology in combination with postprocessing micromachining. The sensor is based on a polysilicon heating resistor and a polysilicon\\/aluminum thermopile integrated on an oxide microbridge. The thermopile sensitivity is 9.9 mV\\/mW and the burn-out power of the sensor is 50 mW. The time constant

Dominik Jaeggi; Henry Baltes; David Moser

1992-01-01

153

Radiation Hardening of CMOS Microelectronics  

SciTech Connect

A unique methodology, silicon transfer to arbitrary substrates, has been developed under this program and is being investigated as a technique for significantly increasing the radiation insensitivity of limited quantities of conventional silicon microelectronic circuits. In this approach, removal of the that part of the silicon substrate not required for circuit operation is carried out, following completion of the circuit fabrication process. This post-processing technique is therefore applicable to state-of-the-art ICs, effectively bypassing the 3-generation technology/performance gap presently separating today's electronics from available radiation-hard electronics. Also, of prime concern are the cost savings that result by eliminating the requirement for costly redesign of commercial circuits for Rad-hard applications. Successful deployment of this technology will result in a major impact on the radiation hard electronics community in circuit functionality, design and software availability and fabrication costs.

McCarthy, A.; Sigmon, T.W.

2000-02-20

154

CMOS Characterization, Modeling, and Circuit Design in the Presence of Random Local Variation.  

E-print Network

??Random local variation in CMOS transistors complicates characterization procedures, modeling efforts, simulation tools, and circuit design methodologies in highly scaled CMOS devices. Mismatch is not (more)

Millemon, Benjamin A., Sr.

2012-01-01

155

Ultra-fast high-resolution hybrid and monolithic CMOS imagers in multi-frame radiography  

NASA Astrophysics Data System (ADS)

A new burst-mode, 10-frame, hybrid Si-sensor/CMOS-ROIC FPA chip has been recently fabricated at Teledyne Imaging Sensors. The intended primary use of the sensor is in the multi-frame 800 MeV proton radiography at LANL. The basic part of the hybrid is a large (4849 mm2) stitched CMOS chip of 11001100 pixel count, with a minimum shutter speed of 50 ns. The performance parameters of this chip are compared to the first generation 3-frame 0.5-Mpixel custom hybrid imager. The 3-frame cameras have been in continuous use for many years, in a variety of static and dynamic experiments at LANSCE. The cameras can operate with a per-frame adjustable integration time of ~ 120ns-to- 1s, and inter-frame time of 250ns to 2s. Given the 80 ms total readout time, the original and the new imagers can be externally synchronized to 0.1-to-5 Hz, 50-ns wide proton beam pulses, and record up to ~1000-frame radiographic movies typ. of 3-to-30 minute duration. The performance of the global electronic shutter is discussed and compared to that of a high-resolution commercial front-illuminated monolithic CMOS imager.

Kwiatkowski, Kris; Douence, Vincent; Bai, Yibin; Nedrow, Paul; Mariam, Fesseha; Merrill, Frank; Morris, Christopher L.; Saunders, Andy

2014-09-01

156

Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference  

PubMed Central

This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of ?40200 C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 C and 200 C). The maximum drift of the reference voltage VREF depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 ?W at room temperature and only 75 ?W at a high temperature of 200 C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of VREF and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2. PMID:24351635

Boufouss, El Hafed; Francis, Laurent A.; Kilchytska, Valeriya; Gerard, Pierre; Simon, Pascal; Flandre, Denis

2013-01-01

157

A 0.13-?m CMOS serializer for data and trigger optical links in particle physics experiments  

Microsoft Academic Search

A 3.2-Gbit\\/s serializer prototype has been fabricated in a 0.13-?m CMOS technology to demonstrate its applicability within future Large Hadron Collider (LHC) data readout and trigger systems. The IC includes a clock-multiplying phase-locked-loop (PLL), a 50-? line driver, internal self-testing features, and data pattern generation. The serial output stream is 8 B\\/10 B encoded for compatibility with commercial receivers. Radiation

Giovanni Cervelli; Alessandro Marchioro; Paulo Moreira

2004-01-01

158

RF power potential of 45 nm CMOS technology  

E-print Network

This paper presents the first measurements of the RF power performance of 45 nm CMOS devices with varying device widths and layouts. We find that 45 nm CMOS can deliver a peak output power density of around 140 mW/mm with ...

Putnam, Christopher

159

Lab-on-CMOS integration of microfluidics and electrochemical sensors.  

PubMed

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Huang, Yue; Mason, Andrew J

2013-10-01

160

Biological inspired CMOS foveated sensor: For neural network training  

Microsoft Academic Search

In this work we describe the design and testing of a custom CMOS-based motion detection system that derives its functionality from biology. The system will beone component of a CMOS visual sensor system that will identify and foveate on objects. The system is inspired by different animals that perform similar functions and have similar retinal structures. For example, we mimic

Yongwoo Jeong; Albert H. Titus

2011-01-01

161

Failures of CMOS Circuits Irradiated At Low Rates  

NASA Technical Reports Server (NTRS)

Report describes experiments on irradiation of SGS 4007 complementary metal oxide/semiconductor (CMOS) integrated inverter circuits by 60Co and 137Cs radioactive sources. Purpose of experiments to supplement previous observations that minimum radiation doses at which failure occurred in more-complicated CMOS parts were lower at lower dose rates.

Goben, Charles A.; Price, William E.

1990-01-01

162

Fluctuation limits & scaling opportunities for CMOS SRAM cells  

Microsoft Academic Search

Fundamental limitations on scaling CMOS SRAM cell transistor dimensions and operating voltages are demonstrated by measuring the local stochastic distributions of read, write and retention DC margins of 65nm PDSOI CMOS SRAM cells. DC measurements show, for the first time, the write operation to be more fluctuation limited. Measurements also reveal fundamental insights into terminal voltage dependencies of the fluctuations

Azeez Bhavnagarwala; Stephen Kosonocky; Carl Radens; Kevin Stawiasz; Randy Mann; Qiuyi Ye; Ken Chin

2005-01-01

163

Low-Power Strategies for High-Performance CMOS Circuits  

Microsoft Academic Search

Power dissipation has become one of the most critical CMOS design parameters. It will be shown that even under constraints on the supply voltage there are effective strategies for the reduction of power dissipation on the different levels of the CMOS design process. Enforcing localization, using redundant number representations and applying an optimal degree of pipelining will be demonstrated as

Tobias G. Noll; RWTH Aachen Rogowski-Institu

1994-01-01

164

Supply and threshold voltage scaling for low power CMOS  

Microsoft Academic Search

This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially when the transistors are velocity saturated and the nodes have a high activity factor, In

Ricardo Gonzalez; Benjamin M. Gordon; Mark A. Horowitz

1997-01-01

165

A 1-V CMOS log-domain integrator  

Microsoft Academic Search

A novel circuit implementation of a CMOS log-domain integrator is presented. Unlike most other implementations, it does not require placing of MOSFETs in separated wells, and therefore allows very compact filters, which are fully compatible with modern standard CMOS technologies. Besides the saving of chip area, this also helps to reduce parasitic capacitances. The most important advantage of this circuit

Dominique Python; Manfred Punzenberger; Christian C. Enz

1999-01-01

166

Variable Input Delay CMOS Logic for Low Power Design  

Microsoft Academic Search

Modern digital circuits consist of logic gates imple- mented in the complementary metal oxide semiconduc- tor (CMOS) technology. The time taken for a logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional CMOS gate is designed to have the same input to out- put delay irrespective of which

Tezaswi Raja; Vishwani D. Agrawal; Michael L. Bushnell

2005-01-01

167

CCD\\/CMOS hybrid FPA for low light level imaging  

Microsoft Academic Search

We present a CCD \\/ CMOS hybrid focal plane array (FPA) for low light level imaging applications. The hybrid approach combines the best of CCD imaging characteristics (e.g. high quantum efficiency, low dark current, excellent uniformity, and low pixel cross talk) with the high speed, low power and ultra-low read noise of CMOS readout technology. The FPA is comprised of

Xinqiao Liu; Boyd A. Fowler; Steve K. Onishi; Paul Vu; David D. Wen; Hung Do; Stuart Horn

2005-01-01

168

The temperature characteristics of bipolar transistors fabricated in CMOS technology  

Microsoft Academic Search

This paper presents the results of an experimental investigation of the temperature characteristics of bipolar transistors fabricated in CMOS technology. These results have to be known and understood to enable the design of high-performance temperature sensors and bandgap references in CMOS integrated circuits. The non-idealities of proportional to the absolute temperature voltage (VPTAT) have been studied, and the results show

Guijie Wang; Gerard C. M Meijer

2000-01-01

169

Counter based CMOS temperature sensor for low frequency applications  

Microsoft Academic Search

A simple temperature sensor in Bi-CMOS technology is proposed for applications with low frequency temperature variations in addition to a complete analysis of each block in the system. Most CMOS temperature sensors are based on the temperature characteristics of parasitic bipolar transistors. Two important factors need to be met in the design of the sensor: the first is the accuracy

Omar Fathy; Ahmed Abdallah; Amr Wassal; Yehea Ismail

2010-01-01

170

A new compact model for junctions in advanced CMOS technologies  

Microsoft Academic Search

We present a new compact model for the junction capacitances and leakage currents in deep-submicron CMOS technologies. The model contains Shockley-Read-Hall generation\\/recombination, trap-assisted tunneling, band-to-band-tunneling, and avalanche breakdown. It has been validated for a wide range of bias and temperature, for NMOS and PMOS junctions, and for different CMOS generations

A. J. Scholten; G. D. J. Smit; M. Durand; R. van Langevelde; C. J. J. Dachs; D. B. M. Klaassen

2005-01-01

171

Plasmonic Color Filters for CMOS Image Sensor Applications Sozo Yokogawa,,,  

E-print Network

Plasmonic Color Filters for CMOS Image Sensor Applications Sozo Yokogawa,,,§ Stanley P. Burgos, 243-0014, Japan ABSTRACT: We report on the optical properties of plasmonic hole arrays as they apply to requirements for plasmonic color filters designed for state-of-the-art Si CMOS image sensors. The hole arrays

Atwater, Harry

172

Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors  

PubMed Central

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Huang, Yue; Mason, Andrew J.

2013-01-01

173

RF CMOS is more than CMOS: Modeling of RF passive components  

Microsoft Academic Search

This paper details recent progress in modeling some RF CMOS passive components: inductors, transformers, and resistors. Many different topologies have been proposed for networks to model spiral inductors; these are analyzed and shown to trend toward reviving the one-segment (pi- or T-topology) approach. The need to account for the distributed nature of metal windings and coupling through a lossy substrate

Zhiping Yu; Colin C. McAndrew

2009-01-01

174

Design of high speed camera based on CMOS technology  

NASA Astrophysics Data System (ADS)

The capacity of a high speed camera in taking high speed images has been evaluated using CMOS image sensors. There are 2 types of image sensors, namely, CCD and CMOS sensors. CMOS sensor consumes less power than CCD sensor and can take images more rapidly. High speed camera with built-in CMOS sensor is widely used in vehicle crash tests and airbag controls, golf training aids, and in bullet direction measurement in the military. The High Speed Camera System made in this study has the following components: CMOS image sensor that can take about 500 frames per second at a resolution of 1280*1024; FPGA and DDR2 memory that control the image sensor and save images; Camera Link Module that transmits saved data to PC; and RS-422 communication function that enables control of the camera from a PC.

Park, Sei-Hun; An, Jun-Sick; Oh, Tae-Seok; Kim, Il-Hwan

2007-12-01

175

Monolithic CMOS imaging x-ray spectrometers  

NASA Astrophysics Data System (ADS)

The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15?m, high resistivity custom (~30k?-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16?m pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40?V/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9?m epitaxial silicon and have a 1k by 1k format. They incorporate similar 16?m pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and spectrally resolved without saturation. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting x-ray astronomy. These features include read noise, x-ray spectral response and quantum efficiency. Funding for this work has been provided in large part by NASA Grant NNX09AE86G and a grant from the Betty and Gordon Moore Foundation.

Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

2014-07-01

176

Nanoscale Materials and Structures for CMOS Devices  

NSDL National Science Digital Library

This presentation was given at the Arizona Nanotechnology Conference in March of 2008 by Dr. Stefan Zollner, Freescale Semiconductor, USA. The focus is on problems with planar CMOS and their solutions. These solutions consist of: SOI or FINFET to reduce source and drain leakage, high mobility channel materials to increase drive current, new silicide materials to reduce source and drain contact resistance, metal oxides with high dielectric constants to reduce gate leakage and metal gate electrodes to reduce gate depletion. Overall, the presentation is filled with images and diagrams allowing it to flow easily. This is an excellent resource for anyone looking to learn more about nanotechnology and its applications.

Zollner, Stefan

2008-10-27

177

Power conserving CMOS reference voltage source  

SciTech Connect

This patent describes a power-conserving CMOS reference voltage generation circuit comprising first (101) and second (101') parallel reference voltage sources, coupled to a common ENABLE input, and having a common reference voltage output node (101''), each source including a first, p-channel (102,102') and a second, n-channel (103,103') CMOS transistor series-connected between Vcc and ground. The first and second transistors have respective gates connected at a common gate node (G, G') and respective drains connected to a common drain node (D, D'), characterized in that: the second reference voltage source (101') is of relatively large capacity compared to the first source (101), means (173,107'), responsive to a rising signal edge at the ENABLE input, are provided for temporarily enabling the second source (101'). This shortens the time required to drive the reference voltage at the output node (101'') to a desired level, i.e. enhancing the slew rate of the node, and means (190-194) are provided for interconnecting the common gate nodes (G,G') the common drain nodes (D,D'), and the common output reference voltage output node (101'') in response to a high signal on the ENABLE input and for isolating the nodes from one another in response to a low signal on the ENABLE input, thereby conserving power.

Lee, R.D.

1986-12-09

178

X-Ray Detector with CMOS Sensor Camera Application of Calcium Denisty Measurement  

Microsoft Academic Search

This paper presented a design of an x-ray-detector using CMOS image sensor. The main components consist of CMOS sensor, taper fiber optic, and image intensifier screen. CMOS sensor offers various advantages including miniature-sized, low power consumption and cost effective. CMOS-based digital camera becomes hence very demanding due to its potential application in multimedia and information technology. To apply the CMOS

Y. Pititheerapab; T. Chanmalueang; T. Rerksngaem; C. Kitipol; C. Pintavirooj

2006-01-01

179

Leakage Control of Digital Circuits Using McCMOS Technique  

NASA Astrophysics Data System (ADS)

In Nano Scale CMOS design, non-minimum length transistors offer the possibility of achieving excellent leakage control without the disadvantages of other known leakage control techniques. Preliminary analysis indicate that one can expect leakage reduction by a factor of at least 100 (and possibly orders of magnitude higher) with only modest, increase in circuit area and switched capacitance. This paper briefly reviews related leakage control techniques, describes the Multiple Channel CMOS (McCMOS) technique, by using 45 nm MOS and presents simulation results that are indicative of the performance of the technique. This technique will be very much useful for designing low leakage high performance ALU units.

Kayal, Dibyendu; Dandapat, Anup; Sarkar, C. K.

2010-10-01

180

A 0.13$\\mu$m CMOS technology Its radiation hardness and its application in high energy physics experiments  

E-print Network

Radiation hardness is a major concern for electronics in high luminosity colliders for high energy physics (HEP). For several years, the HEP community has studied and evaluated radiation hard technologies suitable for the development of analog, digital, and mixed signal application specific integrated circuits. The European Organization for Nuclear Research (CERN) uses currently extensively a commercial 0.25?m complementary metal oxide semiconductor (CMOS) technology for the custom-developed integrated circuits for instrumentation in the Large Hadron Collider. This technology has been carefully evaluated in the past and several measures have been taken to assert the radiation hardness of its applications. To explore the benefits of more advanced technologies, to stay in line with technology progress and in order to prepare for a phase out of this quarter micron technology, a 0.13?m CMOS technology has been analyzed. This thesis outlines, after a theoretical introduction into the fields of ra...

Hnsler, Kurt

2004-01-01

181

CMOS digital pixel sensors: technology and applications  

NASA Astrophysics Data System (ADS)

CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

Skorka, Orit; Joseph, Dileepan

2014-04-01

182

Latchup in CMOS devices from heavy ions  

NASA Technical Reports Server (NTRS)

It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

Soliman, K.; Nichols, D. K.

1983-01-01

183

Fabrication and simulation of CMOS-compatible photodiodes  

E-print Network

CMOS-compatible photodiodes are becoming increasinging important devices to study because of their application in combined electronic-photonic systems. They are already used as inexpensive optical transceivers in fiber ...

DiLello, Nicole Ann

2008-01-01

184

Circuits and algorithms for pipelined ADCs in scaled CMOS technologies  

E-print Network

CMOS technology scaling is creating significant issues for analog circuit design. For example, reduced signal swing and device gain make it increasingly difficult to realize high-speed, high-gain feedback loops traditionally ...

Brooks, Lane Gearle, 1975-

2008-01-01

185

Failures Of CMOS Devices At Low Radiation-Dose Rates  

NASA Technical Reports Server (NTRS)

Method for obtaining approximate failure-versus-dose-rate curves derived from experiments on failures of SGS 4007 complementary metal oxide/semiconductor (CMOS) integrated circuits irradiated by Co60 and Cs137 radioactive sources.

Goben, Charles A.; Price, William E.

1990-01-01

186

Strain-engineered CMOS-compatible Ge photodetectors  

E-print Network

The development of CMOS-compatible photodetectors capable of operating throughout the entire telecommunications wavelength spectrum will aid in the integration of photodetectors with Si microelectronics, thus offering a ...

Cannon, Douglas Dale, 1974-

2004-01-01

187

A study of CMOS technologies for image sensor applications  

E-print Network

CMOS (Complementary Metal-Oxide-Silicon) imager technology, as compared with mature CCD (Charge-Coupled Device) imager technology, has the advantages of higher circuit integration, lower power consumption, and potentially ...

Wang, Ching-Chun, 1969-

2001-01-01

188

III-V CMOS: What have we learned from HEMTs?  

E-print Network

The ability of Si CMOS to continue to scale down transistor size while delivering enhanced logic performance has recently come into question. An end to Moore's Law threatens to bring to a halt the microelectronics revolution: ...

del Alamo, Jesus A.

189

CMOS serial link for fully duplexed data communication  

NASA Astrophysics Data System (ADS)

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

1995-04-01

190

CMOS front-end amplifier for broadband DTV tuner  

E-print Network

In this work, the design of a CMOS broadband low noise amplifier with inherent high performance single-to-differential conversion is presented. These characteristics are driven by the double quadrature single conversion digital television tuner...

Zhang, Guang

2005-08-29

191

A wide-dynamic-range time-based CMOS imager  

E-print Network

This thesis describes a novel dual-threshold time-based current sensing algorithm suitable for use in wide-dynamic-range CMOS imagers. A prototype 150 x 256 pixel imager employing this algorithm experimentally achieves ...

O'Halloran, Micah G. (Micah Galletta), 1978-

2008-01-01

192

BiCMOS OEIC with enhanced sensitivity for DVD systems  

Microsoft Academic Search

A new BiCMOS OEIC with enhanced sensitivity for advanced optical storage systems is presented. The photodiode and the amplifier are monolithically integrated on the same substrate in an industrial 0:8 m BiCMOS process. The OEIC shows a sensitivity of 43.3mV\\/W in combination with a -3 dB-bandwidth of 60.2 MHz.

K. Kieschnick; H. Zimmermann; P. Seegebrecht

2001-01-01

193

CMOS Image Sensors: Electronic Camera On A Chip  

NASA Technical Reports Server (NTRS)

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

Fossum, E. R.

1995-01-01

194

Deep submicron CMOS based on silicon germanium technology  

Microsoft Academic Search

The advantages to be gained by using SiGe in CMOS technology are examined, Conventional MOSFETs are compared with SiGe heterojunction MOSFETs suitable for CMOS technology and having channel lengths between 0.5 and 0.1 ?m. Two-dimensional computer simulation demonstrates that the improved mobility in the SiGe devices, due to higher bulk mobility and the elimination of Si\\/SiO2 interface scattering by the

A. G. O'Neill; D. A. Antoniadis

1996-01-01

195

Delta Doping High Purity CCDs and CMOS for LSST  

NASA Technical Reports Server (NTRS)

A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

2006-01-01

196

A study of phase noise in CMOS oscillators  

Microsoft Academic Search

This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis of a linear oscillatory system leads to a noise shaping function and a new definition of Q. A linear model of CMOS ring oscillators is used to calculate their phase noise, and three phase noise phenomena, namely, additive noise, high-frequency multiplicative noise, and low-frequency multiplicative

Behzad Razavi

1996-01-01

197

A novel CMOS SRAM feedback element for SEU environments  

SciTech Connect

A hardened CMOS SRAM has been proposed which utilizes a leaky polysilicon Schottky diode placed in the feedback path to attain the SEU immunity of resistor-coupled SRAMs while improving the access speed of the cell. Novel polysilicon hybrid Schottky-resistor structures which emulate the leaky diodes have been designed and fabricated. The elements' design criteria and methods of fulfilling them are presented along with a practical implementation scheme for CMOS SRAM cells.

Verghese, S.; Wortman, J.J.; Kerns, S.E.

1987-12-01

198

Burn-In Stress Test of Analog CMOS ICs  

Microsoft Academic Search

With the successful development of EVoSTA (Extreme-Voltage Stress Test for Analog CMOS ICs), this paper investigated whether the extreme-temperature burn-in stress test is properly applied for enhancing the gate-oxide reliability of mixed-signal\\/analog CMOS ICs. Burn-in is an effective screening method used in predicting, achieving, and enhancing field reliability of ICs. Today, almost all IC manufacturers perform 100% burn-in for various

Chin-long Wey; Meng-yao Liu

2004-01-01

199

An advanced, radiation hardened bulk CMOS/LSI technology  

NASA Technical Reports Server (NTRS)

An advanced, second generation, bulk, Si-gate CMOS process is described. This process is capable of producing LSI and VLSI parts that are latch-up free and hardened to total dose levels in excess of 2 x 10 to the 5th rad-Si for applications in space and weapons radiation environments. Two memories designed to use this process are also described. Both circuits are 4096-bit, static CMOS RAMs.

Schroeder, J. E.; Lichtel, R. L.; Gingerich, B. L.

1981-01-01

200

A New High-Filling-Factor CMOS-Compatible Thermopile  

Microsoft Academic Search

To reach a high fill factor, a new CMOS-compatible thermopile was designed and fabricated. The floating membrane of the thermopile that we designed was formed by a T-shape anisotropic etching window with a minimum etching area. The design and fabrication of thermopile sensors are realized by using 1.2-mum CMOS IC technology combined with a subsequent anisotropic front-side etching. The proposed

Shu-Jung Chen; Chih-Hsiung Shen

2007-01-01

201

Sensing temperature in CMOS circuits for Thermal Testing  

Microsoft Academic Search

Abstract Temperature,is a ,physical ,magnitude ,that can ,be used,as an ,observable ,quantity ,for ,IC testing purposes. The authors ,discuss ,in this ,paper ,the suitability of two ,temperature ,measuring ,strategies applicable to standard ,CMOS integrated circuits: a laser interferometer ,and ,a differential ,fully CMOS built-in temperature,sensor. Keywords: Thermal testing, temperature sensors, analysis failure, built-in self test 1. Introduction:Thermal testing Thermal,testing comprises

Josep Altet; Antonio Rubio; M. Amine Salhi; J. L. Glvez; Stefan Dilhaire; Ashish Syal; Andr Ivanov

2004-01-01

202

Precision interface electronics for a CMOS smart temperature sensor  

Microsoft Academic Search

This paper describes the interface electronics of a CMOS smart temperature sensor that is accurate to plusmn0.1degC over the full military temperature range. The sensor is fabricated in a standard CMOS process. Substrate bipolar transistors are used as temperature-sensitive devices. Precision interface electronics are used to make the most of their temperature characteristics. While the sensor is trimmed at one

Michiel A. P. Pertijs; J. H. Huijsing

2005-01-01

203

First fully CMOS-integrated 3D Hall probe  

Microsoft Academic Search

We present the first fully CMOS-integrated 3D Hall probe. The microsystem is developed for precise magnetic field measurements in the range from mT up to tens of tesla in the frequency range from DC to 30 kHz and with a spatial resolution of about 150 ?m. The microsystem is realized in a conventional CMOS process without any additional processing step

P. Kejik; E. Schurig; F. Bergsma; R. S. Popovic

2005-01-01

204

CMOS Amperometric Instrumentation and Packaging for Biosensor Array Applications  

Microsoft Academic Search

An integrated CMOS amperometric instrument with on-chip electrodes and packaging for biosensor arrays is pre- sented. The mixed-signal integrated circuit supports a variety of electrochemical measurement techniques including linear sweep, constant potential, cyclic and pulse voltammetry. Implemented in CMOS, the chip dissipates 22.5 mW for a 200 kHz clock. The highly programmable chip provides a wide range of user-controlled stimulus

Lin Li; Xiaowen Liu; Waqar A. Qureshi; Andrew J. Mason

2011-01-01

205

A low voltage CMOS low drop-out voltage regulator  

Microsoft Academic Search

A low voltage implementation of a CMOS Low Drop-Out voltage regulator (LDO) is presented. The requirement of low voltage devices is crucial for portable devices that require extensive computations in a low power environment. The LDO is implemented in 90nm generic CMOS technology. It generates a fixed 0.8V from a 2.5V supply which on discharging goes to 1V. The buffer

Salma Ali Bakr; Tanvir Ahmad Abbasi; Mohammas Suhaib Abbasi; Mohamed Samir Aldessouky; Mohammad Usaid Abbasi

2009-01-01

206

CMOS magnetic sensor integrated circuit with sectorial MAGFET  

Microsoft Academic Search

In this paper, a CMOS magnetic sensor integrated circuit (IC) for a perpendicular magnetic field is introduced. The sensor integrated circuit is designed and fabricated in a 0.6?m digital CMOS process. It consists of a pair of common-source split-drain magnetic field-effect transistor (MAGFET), a pre-processing circuit with a switches array, a correlated double sampling (CDS) circuit and a digital controlling

Guo Qing; Zhu Dazhong; Yao Yunruo

2006-01-01

207

A statistical MOSFET modeling method for CMOS integrated circuit simulation  

E-print Network

A STATISTICAL MOSFET MODELING METHOD FOR CMOS IN'I'EGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Submitted to the Office of Graduate Studies of Texas AE~M University in partial fulfillment of the requirements for the degree of MASTER... OF SCIENCE August l 99'2 Major Sub ject: Electrical Engineering A STATISTICAL MOSFET MODELING METHOD FOR CMOS INTEGRATED CIRCUIT SIMULATION A Thesis by JIAN CHEN Approved as to style and content by: H. Maciej . Styblinski ) (Chair of Committee...

Chen, Jian

2012-06-07

208

Advancement of CMOS Doping Technology in an External Development Framework  

NASA Astrophysics Data System (ADS)

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

209

Modeling and simulation of TDI CMOS image sensors  

NASA Astrophysics Data System (ADS)

In this paper, a mathematical model of TDI CMOS image sensors was established in behavioral level through MATLAB based on the principle of a TDI CMOS image sensor using temporal oversampling rolling shutter in the along-track direction. The geometric perspective and light energy transmission relationships between the scene and the image on the sensor are included in the proposed model. A graphical user interface (GUI) of the model was also established. A high resolution satellitic picture was used to model the virtual scene being photographed. The effectiveness of the proposed model was verified by computer simulations based on the satellitic picture. In order to guide the design of TDI CMOS image sensors, the impacts of some parameters of TDI CMOS image sensors including pixel pitch, pixel photosensitive size, and integration time on the performance of the sensors were researched through the proposed model. The impacts of the above parameters on the sensors were quantified by sensor's modulation transfer function (MTF) of the along-track direction, which was calculated by slanted-edge method. The simulation results indicated that the TDI CMOS image sensor can get a better performance with smaller pixel photosensitive size and shorter integration time. The proposed model is useful in the process of researching and developing a TDI CMOS image sensor.

Nie, Kai-ming; Yao, Su-ying; Xu, Jiang-tao; Gao, Jing

2013-09-01

210

Low Dark Count Single-Photon Avalanche Diode Structure Compatible With Standard Nanometer Scale CMOS Technology  

Microsoft Academic Search

A single-photon avalanche diode structure implemented in a 130-nm imaging process is reported. The device employs a p-well anode, rather than the commonly adopted p+, and a novel guard ring compatible with recent scaling trends in standard nanometer scale complementary metal-oxide-semiconductor technologies. The 50-mum 2 active area device exhibits a dark count rate of 25 Hz at 20 degC and

Justin A. Richardson; Lindsay A. Grant; Robert K. Henderson

2009-01-01

211

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor  

PubMed Central

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18??m TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18??m TSMC CMOS technology. PMID:24782680

Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

212

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.  

PubMed

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18? ?m TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 ?m TSMC CMOS technology. PMID:24782680

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

213

A CMOS wireless biomolecular sensing system-on-chip based on polysilicon nanowire technology.  

PubMed

As developments of modern societies, an on-field and personalized diagnosis has become important for disease prevention and proper treatment. To address this need, in this work, a polysilicon nanowire (poly-Si NW) based biosensor system-on-chip (bio-SSoC) is designed and fabricated by a 0.35 ?m 2-Poly-4-Metal (2P4M) complementary metal-oxide-semiconductor (CMOS) process provided by a commercialized semiconductor foundry. Because of the advantages of CMOS system-on-chip (SoC) technologies, the poly-Si NW biosensor is integrated with a chopper differential-difference amplifier (DDA) based analog-front-end (AFE), a successive approximation analog-to-digital converter (SAR ADC), and a microcontroller to have better sensing capabilities than a traditional Si NW discrete measuring system. In addition, an on-off key (OOK) wireless transceiver is also integrated to form a wireless bio-SSoC technology. This is pioneering work to harness the momentum of CMOS integrated technology into emerging bio-diagnosis technologies. This integrated technology is experimentally examined to have a label-free and low-concentration biomolecular detection for both Hepatitis B Virus DNA (10 fM) and cardiac troponin I protein (3.2 pM). Based on this work, the implemented wireless bio-SSoC has demonstrated a good biomolecular sensing characteristic and a potential for low-cost and mobile applications. As a consequence, this developed technology can be a promising candidate for on-field and personalized applications in biomedical diagnosis. PMID:24080725

Huang, C-W; Huang, Y-J; Yen, P-W; Tsai, H-H; Liao, H-H; Juang, Y-Z; Lu, S-S; Lin, C-T

2013-11-21

214

A 2.4 GHz CMOS ultra low power low noise amplifier design with 65 nm CMOS technology  

Microsoft Academic Search

In this paper, design approach of 2.4 GHz CMOS ultra low power Low Noise Amplifier (LNA) using 65 nm CMOS technology is presented. Conventional Inductively degenerated cascode topology where both MOS transistors are biased in sub-threshold region is used. There are many performance factors of LNAs such as signal power gain, noise factor, input referred 1-dB compression point (P-1dBin) and

MinSuk Koo; Hakchul Jung; Ickhyun Song; Hee-Sauk Jhon; Hyungcheol Shin

2008-01-01

215

Real-time video rate imaging with a 1k-pixel THz CMOS focal plane array  

NASA Astrophysics Data System (ADS)

Future submillimeter-wave and THz (300GHz-3THz) imaging applications will require low-cost portable systems operating at room-temperature with a video-rate speed and capable of delivering acceptable sensitivity at the very low-power consumption levels to become attractive for truly commercial applications. In particular, CMOS technologies are of interest due to their high integration level offered at a high yield that is capable of massive cost reduction of currently existing THz systems. It has been recently demonstrated that CMOS direct detectors achieve the performance comparable or even superior to the today's existing classical THz devices for active imaging operating at room-temperature. So far, however, only single pixels have been used, allowing only a raster-scan operation. To address this obstacle, we present the very initial work on a 1k-pixel camera chip with a completely integrated readout circuitry and with a full video-rate capability at a power consumption of 2.5?W/pixel. The chip is fully compliant with an industrial bulk CMOS technology and it is intended for active imaging applications. It exhibits a pixel pitch of 80?m, defined by a novel on-chip wire ring antenna, and is designed to accommodate silicon hyper-hemispherical lens for a wide operation bandwidth of at least 0.7-1.1 THz.

Grzyb, J.; Sherry, H.; Zhao, Y.; Al Hadi, R.; Cathelin, A.; Kaiser, A.; Pfeiffer, U.

2012-06-01

216

Gathering effect on dark current for CMOS fully integrated-, PIN-photodiodes  

NASA Astrophysics Data System (ADS)

PIN photodiodes are semiconductor devices widely used in a huge range of applications, such as photoconductors, charge-coupled devices, and pulse oximeters. The possibility to combine and to integrate the fabrication of the sensor with its signal conditioning circuitry in a CMOS process flow opens the window to device miniaturization enhancing its properties and lowering the production and assembly costs. This paper presents the design and characterization of silicon based PIN photodiodes integrated in a CMOS commercial process. A high-resistivity, low impurity float zone substrate is chosen as the start material for the PIN photodiode array fabrication in order to fabricate devices with a minimum dark current. The photodiodes in the array are isolated by a guard ring consisting of a n+-p+ diffusions. However, the introduction of the guard ring design, necessary for photodiode-to-photodiode isolation, leads to an increase of the photodiodes dark current. In this article, the new parasitic term on the dark current is identified, formulated, modelled and experimental proven and has finally been used for an accurate design of the guard ring.

Teva, Jordi; Jonak-Auer, Ingrid; Schrank, Franz; Kraft, Jochen; Siegert, Joerg; Wachmann, Ewald

2010-02-01

217

Commercial Crew  

NASA Video Gallery

Phil McAlister delivers a presentation by the Commercial Crew (CC) study team on May 25, 2010, at the NASA Exploration Enterprise Workshop held in Galveston, TX. The purpose of this workshop was to...

218

Characterization of SOS-CMOS FETs at Low Temperatures for the Design of Integrated Circuits for Quantum Bit Control and Readout  

Microsoft Academic Search

We have assessed the use of commercial silicon-on-sapphire CMOS electronics in control circuits, which could be used to interface with quantum bits at low temperatures. We have characterized n-type MOSFETs, p-type MOSFETs, and an n+-diffusion resistor at 300 K and 4.2 K and extended these studies into the millikelvin regime. Our measurements of dc responses at 300 K, 4.2 K,

S. Ramesh Ekanayake; Torsten Lehmann; Andrew S. Dzurak; Robert G. Clark; Andrew Brawley

2010-01-01

219

NSC 800, 8-bit CMOS microprocessor  

NASA Technical Reports Server (NTRS)

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Suszko, S. F.

1984-01-01

220

Simulation of SEU transients in CMOS ICs  

SciTech Connect

This paper reports that available analytical models of the number of single-event-induced errors (SEU) in combinational logic systems are not easily applicable to real integrated circuits (ICs). An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combinational logic circuits to SEU. SITA is described in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used to estimate the probability that ion-device interactions produce erroneous signals capable of propagating to a latch (or n output node), and logic-level simulation to predict the spread of such erroneous, latched information through the IC. Simulation results are compared to those from SPICE for several circuit and logic configurations. SITA results are comparable to this established circuit-level code, and SITA can analyze circuits with state-of-the-art device densities (which SPICE cannot). At all IC complexity levels, SITAS offers several factors of 10 savings in simulation time over SPICE.

Kaul, N.; Bhuva, B.L.; Kerns, S.E. (Space Electronics Research Group, Vanderbilt Univ., Nashville, TN (US))

1991-12-01

221

HELIOS: photonics electronics functional integration on CMOS  

NASA Astrophysics Data System (ADS)

Silicon photonics have generated an increasing interest in the recent year, mainly for optical telecommunications or for optical interconnects in microelectronic circuits. The rationale of silicon photonics is the reduction of the cost of photonic systems through the integration of photonic components and an IC on a common chip, or in the longer term, the enhancement of IC performance with the introduction of optics inside a high performance chip. In order to build a Opto-Electronic Integrated circuit (OEIC), a large European project HELIOS has been launched two years ago. The objective is to combine a photonic layer with a CMOS circuit by different innovative means, using microelectronics fabrication processes. High performance generic building blocks that can be used for a broad range of applications are developed such as WDM sources by III-V/Si heterogeneous integration, fast Si modulators and Ge or InGaAs detectors, Si passive circuits and specific packaging. Different scenari for integrating photonic with an electronic chip and the recent advances on the building blocks of the Helios project are presented.

Fdli, Jean-Marc; Fulbert, Laurent; Van Thourhout, Dries; Viktorovitch, Pierre; O'Connor, Ian; Duan, Guang-Hua; Reed, Graham; Della Corte, Francesco; Vivien, Laurent; Lopez Royo, Francisco; Pavesi, Lorenzo; Garrido, Blas; Grard, Emmanuel; Tillack, Bernd; Zimmermann, Lars; Formont, Stphane; Hakansson, Andreas; Wachmann, Ewald; Zimmermann, Horst; Bakker, Arjen; Porte, Henri

2010-05-01

222

Modeling and manufacturing of a micromachined magnetic sensor using the CMOS process without any post-process.  

PubMed

The modeling and fabrication of a magnetic microsensor based on a magneto-transistor were presented. The magnetic sensor is fabricated by the commercial 0.18 mm complementary metal oxide semiconductor (CMOS) process without any post-process. The finite element method (FEM) software Sentaurus TCAD is utilized to analyze the electrical properties and carriers motion path of the magneto-transistor. A readout circuit is used to amplify the voltage difference of the bases into the output voltage. Experiments show that the sensitivity of the magnetic sensor is 354 mV/T at the supply current of 4 mA. PMID:24732100

Tseng, Jian-Zhi; Wu, Chyan-Chyi; Dai, Ching-Liang

2014-01-01

223

Modeling the current behavior of the digital BiCMOS gate  

E-print Network

This thesis describes a piece-wise approximation of transient current response of the digital BiCMOS gate. Based on the detailed transient analysis of the conventional digital BiCMOS gate, a new circuit model for digital BiCMOS gate is derived which...

Tang, Zhilong

2012-06-07

224

High gain CMOS image sensor design and fabrication on SOI and bulk technology  

Microsoft Academic Search

The CMOS imager is now competing with the CCD imager, which still dominates the electronic imaging market. By taking advantage of the mature CMOS technology, the CMOS imager can integrate AID converters, digital signal processing (DSP) and timing control circuits on the same chip. This low cost and high-density integration solution to the image capture is the strong driving force

Weiquan Zhang

2000-01-01

225

N3ASICs: Designing nanofabrics with fine-grained CMOS integration  

Microsoft Academic Search

We propose a novel nanofabric approach that mixes unconventional nanomanufacturing with CMOS manufacturing flow and design rules in order to build a reliable nanowire- CMOS fabric called N 3 ASIC with no new manufacturing constraints added. Active devices are formed on a dense uniform semiconductor nanowire array and standard area distributed pins\\/vias; metal interconnects route the signals in 3D. CMOS

Pavan Panchapakeshan; Pritish Narayanan; Csaba Andras Moritz

2011-01-01

226

Del 2: Enkel elektrisk transistor modell og introduksjon til CMOS prosess  

E-print Network

Del 2: Enkel elektrisk transistor modell og introduksjon til CMOS prosess YNGVAR BERG I. Innhold GJ ennomgang av CMOS prosess, tverrsnitt av nMOS- og pMOS transistor og tverrsnitt av CMOS inverter. Enkel forklaring p°a begreper som akkumulasjon, deplesjon og inver- sjon. Enkel fysikalsk forklaring p°a transistor

Sahay, Sundeep

227

Design Considerations for CMOS-Integrated Hall-Effect Magnetic Bead Detectors for Biosensor Applications  

PubMed Central

We describe a design methodology for on-chip magnetic bead label detectors based on Hall-effect sensors. Signal errors caused by the label-binding process and other factors that limit the minimum detection area are quantified and adjusted to meet typical assay accuracy standards. The methodology is demonstrated by designing an 8192 element Hall sensor array, implemented in a commercial 0.18 ?m CMOS process with single-mask postprocessing. The array can quantify a 1% surface coverage of 2.8 ?m beads in 30 seconds with a coefficient of variation of 7.4%. This combination of accuracy and speed makes this technology a suitable detection platform for biological assays based on magnetic bead labels. PMID:25031503

Skucha, K.; Gambini, S.; Liu, P.; Megens, M.; Kim, J.; Boser, BE

2014-01-01

228

A hybrid CMOS-microfluidic contact imaging microsystem  

NASA Astrophysics Data System (ADS)

A hybrid CMOS/Microfluidic microsystem is presented. The microsystem integrates a soft polymer microfluidic network with a 64x128 pixel imager fabricated in low-cost standard 0.35 micron CMOS technology. The multiple microfluidic channels facilitate in-situ photochemical reactions of analytes and their detection directly on the surface of the CMOS photosensor array. The promixity between the analyte and the photosensor enhances the microsystem sensitivity, thus requiring only microliter volumes of the sample. Circuit techniques such as pixel binning and a two transistor reset path technique are employed to improve the imager sensitivity. The integrated microsystem is validated in on-chip chemiluminescence detection of luminol for the two microfluidic network prototypes designed.

Singh, Ritu Raj; Leng, Lian; Guenther, Axel; Genov, Roman

2009-08-01

229

VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications  

NASA Astrophysics Data System (ADS)

This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

Arcamone, Julien; Dupr, Ccilia; Arndt, Grgory; Colinet, Eric; Hentz, Sbastien; Ollier, Eric; Duraffourg, Laurent

2014-10-01

230

VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications.  

PubMed

This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 ?m long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association. PMID:25288224

Arcamone, Julien; Dupr, Ccilia; Arndt, Grgory; Colinet, Eric; Hentz, Sbastien; Ollier, Eric; Duraffourg, Laurent

2014-10-31

231

A CMOS Humidity Sensor for Passive RFID Sensing Applications  

PubMed Central

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 ?m CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 ?W at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

232

Operation and biasing for single device equivalent to CMOS  

DOEpatents

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

2001-01-01

233

Commercial Sensory Survey Radiation Testing Progress Report  

NASA Technical Reports Server (NTRS)

The NASA Electronic Parts and Packaging (NEPP) Program Sensor Technology Commercial Sensor Survey task is geared toward benefiting future NASA space missions with low-cost, short-duty-cycle, visible imaging needs. Such applications could include imaging for educational outreach purposes or short surveys of spacecraft, planetary, or lunar surfaces. Under the task, inexpensive commercial grade CMOS sensors were surveyed in fiscal year 2007 (FY07) and three sensors were selected for total ionizing dose (TID) and displacement damage dose (DDD) tolerance testing. The selected sensors had to meet selection criteria chosen to support small, low-mass cameras that produce good resolution color images. These criteria are discussed in detail in [1]. This document discusses the progress of radiation testing on the Micron and OmniVision sensors selected in FY07 for radiation tolerance testing.

Becker, Heidi N.; Dolphic, Michael D.; Thorbourn, Dennis O.; Alexander, James W.; Salomon, Phil M.

2008-01-01

234

Delay modeling and glitch estimation for CMOS circuits  

E-print Network

DELAY MODELING AND GLITCH ESTIMATION FOR CMOS CIRCUITS A Thesis by YAN-CHYUAN SHIAU Submitted to the Graduate College of Texas A8rM University in partial fulfillment of the requirement for the degree of MASTER OF SCIENCE August 1988 Major... Subject: Electrical Engineering DELAY MODELING AND GLITCH ESTIMATION FOR CMOS CIRCUITS A Thesis by YAN-CHYUAN SHIAU Approved as to style and content by: An-Chang Deng (Chairman of Committee) Karan Watson (Member) I / l j j Stephen M. Morg...

Shiau, Yan-Chyuan

2012-06-07

235

Impact of technology trends on SEU in CMOS SRAMs  

SciTech Connect

The impact of technology trends on the SEU hardness of epitaxial CMOS SRAMs is investigated using three-dimensional simulation. The authors study trends in SEU susceptibility with parameter variations across and within technology generations. Upset mechanisms for various strike locations and their dependence on gate-length scaling are explored. Such studies are useful for technology development and providing input for process and design decisions. An application of SEU simulation to the development of a 0.5-{micro}m radiation-hardened CMOS SRAM is presented.

Dodd, P.E.; Sexton, F.W.; Hash, G.L.; Shaneyfelt, M.R.; Draper, B.L.; Farino, A.J.; Flores, R.S. [Sandia National Labs., Albuquerque, NM (United States)] [Sandia National Labs., Albuquerque, NM (United States)

1996-12-01

236

A high performance 0.25 mu m CMOS technology  

Microsoft Academic Search

A high-performance 0.25- mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented. A loaded ring oscillator (NAND FI=FO=3. Cw=0.2 pF) delay per stage of 280 ps achieved (Weff\\/Leff=15 mu m\\/0.25 mu m), which is a 1.7 X improvement over 0.5- mu m CMOS technology. At shorter channel lengths (0.18 mu m),

B. Davari; W. H. Chang; M. R. Wordeman; C. S. Oh; Y. Taur; K. E. Petrillo; D. Moy; J. J. Bucchignano; H. Y. Ng; M. G. Rosenfield; F. J. Hohn; M. D. Rodriguez

1988-01-01

237

Organic Field-Effect Transistors for CMOS Devices  

Microsoft Academic Search

\\u000a Organic field-effect transistors (OFETs) are the key elements of future low cost electronics such as radio frequency identification\\u000a tags. In order to take full advantage of organic electronics, low power consumption is mandatory, requiring the use of a complementary\\u000a metal oxide semiconductor (CMOS) like technique. To realize CMOS-devices p-type and n-type organic field-effect transistors\\u000a on one substrate have to be

Christian Melzer; Heinz von Seggern

2010-01-01

238

A 130 nm radiation hardened flipflop with an annular gate and a C-element  

NASA Astrophysics Data System (ADS)

This paper presents a radiation hardened flipflop with an annular gate and a Muller C-element. The proposed cell has multiple working modes which can be used in different situations. Each part of the cell can be verified easily and completely by using different modes. This cell has been designed under an SMIC 0.13 ?m process and 3-D simulated by using Synopsys TCAD. Heavy-ion testing has been done on the cell and its counterparts. The test results demonstrate that the presented cell reduces the cell's saturation cross section by approximately two orders of magnitude with little penalty on performance.

Lei, Wang; Jianhua, Jiang; Yiming, Xiang; Yumei, Zhou

2014-01-01

239

The Measurement of Van Der Waals Dispersion Forces in the Range 1.5 to 130 nm  

Microsoft Academic Search

This paper describes an experimental study of the van der Waals dispersion forces between curved mica surfaces. For separations in the range 1.4 to 20 nm the forces were determined by the jump method described in earlier work by Tabor & Winterton (1969). For larger separations the forces were determined by a new dynamic method. One surface was supported on

J. N. Israelachvili; D. Tabor

1972-01-01

240

Performance and Limitations of 65 nm CMOS for  

E-print Network

· High-volume, low cost consumer applications ­ Current: WLAN, Bluetooth, Cell-phone PA driver, Wi Vdd impact on reliability ­ Use I/O devices (if available) process complexity (cost) ­ Increase · Devices designed and fabricated in IBM's 65 nm CMOS WG,TOT = NC x NF x WG,F NC = # of cells NF

del Alamo, Jesús A.

241

Low-power 2-D fully integrated CMOS fluxgate magnetometer  

Microsoft Academic Search

In this paper, we present a low-power, two-axis fluxgate magnetometer. The planar sensor is integrated in a standard CMOS process, which provides metal layers for the coils and electronics for the signal extraction and processing. The ferromagnetic core is placed diagonally above the four excitation coils by a compatible photolithographic post process, performed on a whole wafer. The sensor works

Predrag M. Drljaca; Pavel Kejik; Franck Vincent; Dominique Piguet; Radivoje S. Popovic

2005-01-01

242

CMOS Transistor Mismatch Model valid from Weak to Strong Inversion  

E-print Network

CMOS Transistor Mismatch Model valid from Weak to Strong Inversion Teresa Serrano and PMOS transistors for 30 different geometries has been done with this continuos model. The model is able of transistor mismatch is crucial for precision analog design. Using very reduced transistor geometries produces

Barranco, Bernabe Linares

243

An Analog CMOS Backward Error-propagation LSI  

Microsoft Academic Search

The design of a novel cascadable CMOS analog IC architecture that implements the Backward Error Propagation algorithm is describcd. Forward and backward propagation signals coexist simultaneously in this unclockcd system, and internal analog weights are stored as charges on capacitors. This IC will speed up convergence of this algorithm many orders of magnitude over conventional software implementations, allowing a variety

B. Furman; A. A. Abidi

1988-01-01

244

An integrated CMOS micromechanical resonator high-Q oscillator  

Microsoft Academic Search

A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator with the intent of achieving high stability. The operation and performance of micromechanical resonators are modeled, with emphasis on circuit and noise modeling of multiport resonators. A series resonant oscillator design is

Clark T.-C. Nguyen; Roger T. Howe

1999-01-01

245

Gate engineering for deep-submicron CMOS transistors  

Microsoft Academic Search

Gate depletion and boron penetration through thin gate oxide place directly opposing requirements on the gate engineering for advanced MOSFET's. In this paper, several important issues of deep-submicron CMOS transistor gate engineering are discussed. First, the impact of gate nitrogen implantation on the performance and reliability of deep-submicron CMOSFET's is investigated. The suppression of boron penetration is confirmed by the

Bin Yu; Dong-Hyuk Ju; Wen-Chin Lee; Nick Kepler; Tsu-Jae King; Chenming Hu

1998-01-01

246

Development of RF CMOS receiver front-ends for ultrawideband  

E-print Network

measurement result of 7.2dB gain, 4.2-6dB noise figure, and less than -10dB return loss through 0-11GHz. A new distributed amplifier implementing cascade common source gain cells is presented in 0.18-?m CMOS. The new amplifier demonstrates a high gain of 16dB...

Guan, Xin

2009-05-15

247

Bridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess  

E-print Network

circuit. The bridge fault transforms the two gates for which the bridged wires are outputs into a singleBridge Fault Simulation Strategies for CMOS Integrated Circuits Brian Chess Tracy Larrabee \\Lambda present a theorem for detecting feedback bridge faults. We discuss two different methods of bridge fault

Larrabee, Tracy

248

Leakage sources and possible solutions in nanometer CMOS technologies  

Microsoft Academic Search

Until recent years, dynamic power dissipation contributed the most to the chip's total power dissipation in CMOS digital circuits thus much attention was given to reduce this dynamic power. But as technology advances into the sub-100 nm regime, leakage power dissipation, which is a static power, increases at a much faster rate than dynamic power and it is expected to

Walid M. Elgharbawy; Magdy A. Bayoumi

2005-01-01

249

Evaluation of Transistor Densities for Submicronic CMOS Technologies  

Microsoft Academic Search

The transistor density is one of the parameters to be considered for an optimal use of CMOS process. Therefore, layout strategies have to be evaluated through metrics considering all the involved parameters. The objective of this paper is to study the real transistor density available for a given technology at the cell and circuit level, from the design rules. This

F. Moraes; L. Torres; M. Robert; D. Auvergne

250

Determination of SEU parameters of NMOS and CMOS SRAMs  

Microsoft Academic Search

Procedures for determining the SEU parameters for advanced memory devices are demonstrated for CMOS and resistor-loaded NMOS SRAMs. The dimensions of the sensitive volume are either obtained from charge collection measurements on test structures or estimated from similar measurements on the SRAMs themselves. Values of the critical charge determined from simple proton measurements agree with the values obtained for three

P. J. McNulty; W. J. R. J. Beavais; D. R. Roth

1991-01-01

251

Relationship between IBICC imaging and SEU in CMOS ICs  

SciTech Connect

Ion-beam-induced charge-collection (IBICC) images of the TA670 16K-bit CMOS SRAM are analyzed and compared to previous SEU images. Enhanced charge collection was observed in the n-source/drains regions consistent with bipolar amplification or shunting.

Sexton, F.W.; Horn, K.M.; Doyle, B.L. [Sandia National Labs., Albuquerque, NM (United States); Laird, J.S.; Cholewa, M.; Saint, A.; Legge, G.J.F. [Melbourne Univ., Parkville, VIC (Australia)

1993-03-01

252

Overcoming scaling concerns in a radiation-hardening CMOS technology  

SciTech Connect

Scaling efforts to develop an advanced radiation-hardened CMOS process to support a 4M SRAM are described. Issues encountered during scaling of transistor, isolation, and resistor elements are discussed, as well as the solutions used to overcome these issues. Transistor data, total dose radiation results, and the performance of novel resistors for prevention of single event upsets (SEU) are presented.

Maimon, J.; Haddad, N.

1999-12-01

253

Impact of technology trends on SEU in CMOS SRAMs  

Microsoft Academic Search

The impact of technology trends on the SEU hardness of epitaxial CMOS SRAMs is investigated using three-dimensional simulation. We study trends in SEU susceptibility with parameter variations across and within technology generations. Upset mechanisms for various strike locations and their dependence on gate-length scaling are explored. Such studies are useful for technology development and providing input for process and design

P. E. Dodd; F. W. Sexton; G. L. Hash; M. R. Shaneyfelt; B. L. Draper; A. J. Farino; R. S. Flores

1996-01-01

254

Radiation and postirradiation functional upsets in CMOS SRAM  

SciTech Connect

The CMOS SRAM radiation and postirradiation functional upsets are investigated as a function of total dose, dose rate, annealing time and functional tests. Local and conventional X-ray as well as LINAC and Sr-90 irradiation procedures were performed. A model explaining the experimental results is discussed.

Chumakov, A.I.; Yanenko, A.V. [Specialized Electronic Systems, Moscow (Russian Federation)] [Specialized Electronic Systems, Moscow (Russian Federation)

1996-12-01

255

Relationship between IBICC imaging and SEU in CMOS ICs  

SciTech Connect

Ion-beam-induced charge-collection (IBICC) images of the TA670 16K-bit CMOS SRAM are analyzed and compared to previous SEU images. Enhanced charge collection was observed in the n-source/drains regions consistent with bipolar amplification or shunting.

Sexton, F.W.; Horn, K.M.; Doyle, B.L. (Sandia National Labs., Albuquerque, NM (United States)); Laird, J.S.; Cholewa, M.; Saint, A.; Legge, G.J.F. (Melbourne Univ., Parkville, VIC (Australia))

1993-01-01

256

Measuring Power and Energy of CMOS Circuits: A Comparative Analysis  

E-print Network

DD(t), it is possible to calculate the charge, energy and power consumed by an IC. The main problem lays on the properMeasuring Power and Energy of CMOS Circuits: A Comparative Analysis J. Rius, A. Peidro, S. Manich presents and compares a set of experimental results on the measurement of power and energy consumed using

Boemo, Eduardo

257

CMOS Monolithic Voltage Converter ________________________________________________________________ Maxim Integrated Products 1  

E-print Network

or Doubles Input Supply Voltage Selectable Oscillator Frequency: 10kHz/80kHz 88% Typ Conversion Efficiency for both battery-powered and board- level voltage conversion applications. The MAX660 can also doubleMAX660 CMOS Monolithic Voltage Converter

Berns, Hans-Gerd

258

Upper-Bound Estimates Of SEU in CMOS  

NASA Technical Reports Server (NTRS)

Theory of single-event upsets (SEU) (changes in logic state caused by energetic charged subatomic particles) in complementary metal oxide/semiconductor (CMOS) logic devices extended to provide upper-bound estimates of rates of SEU when limited experimental information available and configuration and dimensions of SEU-sensitive regions of devices unknown. Based partly on chord-length-distribution method.

Edmonds, Larry D.

1990-01-01

259

A Fully Differential CMOS Potentiostat Meisam Honarvar Nazari  

E-print Network

of poor selectivity [1]. In FSCV a cyclic potential is applied between recording electrodes. It offers beneficial when supply voltage shrinks due to CMOS technology scaling. + - VOUT WE1WE2RE I1I2 I/V ION-SELECTIVE down to pico-ampere range. The fully differential architecture with differential recording electrodes

Genov, Roman

260

Intensity Histogram CMOS Image Sensor for Adaptive Optics  

E-print Network

Intensity Histogram CMOS Image Sensor for Adaptive Optics Yu M. Chi, Gary Carhart , Mikhail A imaging mode and 4.6mW in high-speed histogram mode. Applications include real-time adaptive optics control for laser communications. I. INTRODUCTION Adaptive optical systems are highly useful

Cauwenberghs, Gert

261

Single Event Upset Behavior of CMOS Static RAM Cells  

NASA Technical Reports Server (NTRS)

An improved state-space analysis of the CMOS static RAM cell is presented. Introducing theconcept of the dividing line, the critical charge for heavy-ion-induced upset of memory cells can becalculated considering symmetrical as well as asymmetrical capacitive loads. From the criticalcharge, the upset-rate per bit-day for static RAMs can be estimated.

Lieneweg, Udo; Jeppson, Kjell O.; Buehler, Martin G.

1993-01-01

262

CMOS image sensors as an efficient platform for glucose monitoring.  

PubMed

Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications. PMID:23900281

Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

2013-10-01

263

Defect classes: An overdue paradigm for CMOS IC testing  

Microsoft Academic Search

The IC test industry has struggled for more than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS IC's that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the test

C. F. Hawkins; J. M. Soden; A. W. Righter; F. J. Ferguson

1994-01-01

264

The Evolution of Digital Imaging: From CCD to CMOS  

E-print Network

The Evolution of Digital Imaging: From CCD to CMOS A Micron White Paper Digital imaging began with the invention of the charge- coupled device (CCD) in 1969. Since then, the technologies used to convert light honors, for developing the charge-coupled device (CCD) while they were both researchers

La Rosa, Andres H.

265

Record RF performance of standard 90 nm CMOS technology  

Microsoft Academic Search

We have optimized 3 key RF devices realized in standard logic 90 nm CMOS technology and report a record performance in terms of n-MOS maximum oscillation frequency fmax (280 GHz), varactor tuning range and varactor and inductor quality factor.

L. F. Tiemeijer; R. J. Havens; R. de Kort; A. J. Scholten; R. van Langevelde; D. B. M. Klaassen; G. T. Sasse; Y. Bouttement; C. Petot; S. Bardy; D. Gloria; P. Scheer; S. Boret; B. Van Haaren; C. Clement; J.-F. Larchanche; I.-S. Lim; A. Duvallet; A. Zlotnicka

2004-01-01

266

Accurate thermal noise model for deep-submicron CMOS  

Microsoft Academic Search

Extensive measurements of drain current thermal noise are presented for 3 different CMOS technologies and for gate lengths ranging from 2 ?m down to 0.17 ?m. Using a surface-potential-based compact MOS model with improved descriptions of carrier mobility and velocity saturation, all the experimental results can be described accurately without invoking carrier heating effects or introducing additional parameters

A. J. Scholten; H. J. Tromp; L. F. Tiemeijer; R. Van Langevelde; R. J. Havens; P. W. H. De Vreede; R. F. M. Roes; P. H. Woerlee; A. H. Montreen; D. B. M. Klaassen

1999-01-01

267

BiCMOS differential temperature sensor: Characterization and BIST applications  

Microsoft Academic Search

Measurements of thermal gradients inside the silicon die can be used for BIST applications. Two temperature sensors sensible to changes of the surface thermal gradient have been implemented in a 1.2 m BiCMOS technology. Results show that the power dissipated by a circuit can be monitored by placing differential temperature sensors. A detailed analysis of the noise coupled to the

Josep Altet; X. Aragones; Jose Luis GonzAlez; Diego Mateo; Antonio Rubio

1998-01-01

268

Dynamic internal testing of CMOS circuits using hot luminescence  

Microsoft Academic Search

Subnanosecond pulses of hot electron luminescence are shown to be generated coincident with logic state switching of individual devices in CMOS circuits. These pulses are used to directly observe 90 ps gate delays in a ring oscillator as well as the logic switching and gate delays of a counter. By use of a detector with both space- and time-resolution, the

J. A. Kash; J. C. Tsang

1997-01-01

269

A CMOS Linear power supply for a Wireless Biomedical Sensor  

Microsoft Academic Search

This paper describes a CMOS Linear Voltage Regulator (LVR) of an implanted physiological signal system (biosensor) that is used to monitor blood pressure. This system is part of a Wireless Biomedical Sensor (WBS). The LVR topology is based on a classical structure of a Low Dropout Regulator (LDO). The energy is received from a RF link, thus operating as a

Paulo Crepaldi; Tales Pimenta; Robson Moreno; Edgar Rodriguez

2010-01-01

270

CMOS VLSI Layout and Verification of a SIMD Computer  

NASA Technical Reports Server (NTRS)

A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

Zheng, Jianqing

1996-01-01

271

CMOS-year 2010 and beyond; from technological side  

Microsoft Academic Search

CMOS LSIs, having advanced remarkably during the past 25 years, are expected to continue to progress well into the next century. The progress has been driven by the downsizing of the components in an LSI, such as MOSFETs. However, even before the downsizing of MOSFETs reaches its fundamental limit, the downsizing is expected to encounter severe technological and economic problems

Hiroshi Iwai; Komukai Toshiba-cho

1998-01-01

272

Research-grade CMOS image sensors for remote sensing applications  

Microsoft Academic Search

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been

Olivier Saint-Pe; Michel Tulet; Robert Davancens; Franck Larnaudie; Pierre Magnan; Philippe Martin-Gonthier; Franck Corbiere; Pierre Belliot; Magali Estribeau

2004-01-01

273

SMALL-SIGNAL MODELING OF RF CMOS A DISSERTATION  

E-print Network

SMALL-SIGNAL MODELING OF RF CMOS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL, where it is becoming a serious contender for radio frequency (RF) appli- cations in the GHz range are critical requirements for circuit designs, the RF behavior and physics are not well understood

Dutton, Robert W.

274

Table of Contents Deep Submicron CMOS Photonics 5-1  

E-print Network

Characteristics of Selectively Grown Ge-on-Si Photodiodes 5-18 Excitonic Surface Plasmon Resonance Biosensor 5-threshold Vertical Cavity Surface-emitting Lasers Recess Integrated within Silicon CMOS Integrated Circuits 5-14 Magnetic Oxides for Optical Isolators and Magnetoelectronic Devices 5-15 Development of Terahertz Quantum

Reif, Rafael

275

Analog CMOS Velocity Sensors C. M. Higgins and C. Koch  

E-print Network

. Keywords: Analog VLSI, CMOS, velocity sensors, motion sensors, optical ow 1. INTRODUCTION Motion is a key. Continuous-time optical sensor arrays have clear advantages over discrete-time sampled arrays for motion pro a long history,1 10 but only recently have such sensors begun to simultane- ously accomplish the aims

276

IBM Systems and Technology Electronics IBM CMOS 7HV for  

E-print Network

companies can significantly improve these metrics today by using IBM technology in smart solar- panel to improve effi- ciency, cost per kilowatt and reliability of solar modules IBM CMOS 7HV is the industry, cost per kilowatt and reliability of solar modules. While this research is critical, photovoltaics

277

Power Supply Generation in CMOS Passive UHF RFID Tags  

Microsoft Academic Search

The paper discusses the design of a power generation circuit suitable to provide the supply voltage for a passive UHF RFID tag. The proposed differential rectifier exhibits a low activation threshold and is compatible with digital CMOS technologies. The chip supply voltage is obtained through a Dickson-based voltage multiplier and an ultra low-power voltage regulator

Alessio Facen; A. Boni

2006-01-01

278

Optical and noise performance of CMOS solid-state photomultipliers  

NASA Astrophysics Data System (ADS)

Solid-state photomultipliers (SSPM) are photodetectors composed of avalanche photodiode pixel arrays operating in Geiger mode (biased above diode breakdown voltage). They are built using CMOS technology and can be used in a variety of applications in high energy and nuclear physics, medical imaging and homeland security related areas. The high gain and low cost associated with the SSPM makes it an attractive alternative to existing photodetectors such as the photomultiplier tube (PMT). The capability of integrating CMOS on-chip readout circuitry on the same substrate as the SSPM also provides a compact and low-power-consumption solution to photodetector applications with stringent area and power requirements. The optical performance of the SSPM, specifically the detection and quantum efficiencies, can depend on the geometry and the doping profile associated with each photodiode pixel. The noise associated with the SSPM not only includes dark noise from each pixel, but also consists of excess noise terms due to after pulsing and inter-pixel cross talk. The magnitude of the excess noise terms can depend on biasing conditions, temperature, as well as pixel and inter-pixel dimensions. We present the optical and noise performance of SSPMs fabricated in a conventional CMOS process, and demonstrate the dependence of the SSPM performance on pixel/inter-pixel geometry, doping profile, temperature, as well as bias conditions. The continuing development of CMOS SSPM technology demonstrated here shows that low cost and high performance solid state photodetectors are viable solutions for many existing and future optical detection applications.

Chen, Xiao Jie; Johnson, Erik B.; Staples, Christopher J.; Chapman, Eric; Alberghini, Guy; Christian, James F.

2010-08-01

279

Method of recording CMOS IC parameters after a destabilizing pulse  

SciTech Connect

The techniques presented for recording the parameters of a CMOS IC make it possible to determine the pulse transient response function of an integrated circuit and to observe the behavior of the IC during a destabilizing pulse and just after it for 10{sup -5}-10{sup -4} sec.

Chertov, A.V.

1995-09-01

280

Roadmap for CMOS image sensors: Moore meets Planck and Sommerfeld  

E-print Network

lithographic feature size has decreased by thirty percent every three years.2, 3 CMOS technology scaling can be used to shrink transistor size and increase photosensitive area in the pixel (fill-factor). Different and diffraction-limited blurring (Sommerfeld).6 First, consider photon noise. As pixel size shrinks, the mean

Wandell, Brian A.

281

A very high frequency CMOS Variable Gain Amplifier  

E-print Network

A fully differential CMOS Variable Gain Amplifier (VGA) consisting of an analog multiplier, current gain stages, and resistor loads is designed for very high frequency applications. The gain can be programmed from 0dB to 40dB with -3dB bandwidth...

Tan, Siang Tong

2012-06-07

282

Helicopter rotors pyramid angle measurement based on CMOS technology  

Microsoft Academic Search

Based on computer image processing, give a new method on helicopter rotors pyramid angle by CMOS -Camera. give a overall design of the system, compare image results with different camera's location and analyze the system's qualitative error. design a synchronized system by external synchronized pulse in order to catch the accuracy image and calculate the blade's height differences by filter

Jiang Mai; Cai Cheng-Tao; Zhu Qi-Dan; Shi Zhen

2009-01-01

283

Test Considerations for Gate Oxide Shorts in CMOS ICs  

Microsoft Academic Search

Gate oxide shorts are defects that must be detected to produce high-reliability ICs. These problems will continue as devices are scaled down and oxide thicknesses are reduced to the 100-?? range. Complete detection of gate oxide shorts and other CMOS failure mechanisms requires measuring the IDD current during the quiescent state after each test vector is applied to the IC.

Jerry M. Soden; Charles Hawkins

1986-01-01

284

Ultrabroadband supercontinuum generation in a CMOS-compatible platform  

E-print Network

Ultrabroadband supercontinuum generation in a CMOS-compatible platform R. Halir,1,5, * Y. Okawachi 162267); published May 10, 2012 We demonstrate supercontinuum generation spanning 1.6 octaves in silicon Optical Society of America OCIS codes: 190.4390, 320.7110, 320.6629, 230.7370. Supercontinuum generation

Lipson, Michal

285

Polysilicon sensors for CMOS-MEMS electrothermal probes  

Microsoft Academic Search

We describe multiple embedded polysilicon resistive sensors in CMOS-MEMS electrothermal probes as a step toward creating probe arrays for passing current on ICs to reconfigure resistance change (RC) vias. When not in contact, a low-resistivity unsilicided polysilicon (LP) resistor detects probe displacement indirectly through the temperature coefficient of resistance (TCR) effect. When in contact with a load force, the difference

J. Liu; M. Noman; J. A. Bain; T. E. Schlesinger; G. K. Fedder

2009-01-01

286

Contact CMOS imaging of gaseous oxygen sensor array  

PubMed Central

We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within solgel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 W and an average dynamic power of 625 W when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

2014-01-01

287

A HIGH RESOLUTION, STICTIONLESS, CMOS COMPATIBLE SOI ACCELEROMETER WITH A LOW NOISE, LOW POWER, 0.25M CMOS INTERFACE  

E-print Network

0.25µm CMOS. The interface IC consumes 3mW of power. II. ACCELEROMETER DESIGN The simplified with no perforations results in a smaller footprint for the sensor and an improved mechanical design. The fabricated-release low temperature process comprising of three plasma etching steps. The fabricated devices were

Ayazi, Farrokh

288

Commercial Capaciflector  

NASA Technical Reports Server (NTRS)

A capacitive proximity/tactile sensor with unique performance capabilities ('capaciflector' or capacitive reflector) is being developed by NASA/Goddard Space Flight Center (GSFC) for use on robots and payloads in space in the interests of safety, efficiency, and ease of operation. Specifically, this sensor will permit robots and their attached payloads to avoid collisions in space with humans and other objects and to dock these payloads in a cluttered environment. The sensor is simple, robust, and inexpensive to manufacture with obvious and recognized commercial possibilities. Accordingly, NASA/GSFC, in conjunction with industry, is embarking on an effort to 'spin' this technology off into the private sector. This effort includes prototypes aimed at commercial applications. The principles of operation of these prototypes are described along with hardware, software, modelling, and test results. The hardware description includes both the physical sensor in terms of a flexible printed circuit board and the electronic circuitry. The software description will include filtering and detection techniques. The modelling will involve finite element electric field analysis and will underline techniques used for design optimization.

Vranish, John M.

1991-01-01

289

296 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 5, NO. 2, MARCH/APRIL 1999 Smart CMOS Focal Plane Arrays: A Si CMOS  

E-print Network

CMOS Focal Plane Arrays: A Si CMOS Detector Array and Sigma­Delta Analog-to-Digital Converter Imaging-order sigma­delta analog- to-digital converter front end, has been fabricated, and test results for uniformity array data followed by transportation of the data to an off-chip serial analog-to-digital (A

Wills, Scott

290

Practicality of Evaluating Soft Errors in Commercial sub-90 nm CMOS for Space Applications  

NASA Technical Reports Server (NTRS)

The purpose of this presentation is to: Highlight space memory evaluation evolution, Review recent developments regarding low-energy proton direct ionization soft errors, Assess current space memory evaluation challenges, including increase of non-volatile technology choices, and Discuss related testing and evaluation complexities.

Pellish, Jonathan A.; LaBel, Kenneth A.

2010-01-01

291

Supporting Information Packaging Commercial CMOS Chips for Lab on a Chip Integration  

E-print Network

with photoresist to permit selective deposition of PEDOT:PSS onto the recording and reference electrodes. (The green color of the image results from the filter used in the microscope to protect the resist from

Shapiro, Benjamin

292

X-ray imaging and spectroscopy using low cost COTS CMOS sensors  

NASA Astrophysics Data System (ADS)

Whilst commercial X-ray sensor arrays are capable of both imaging and spectroscopy they are currently expensive and this can limit their widespread use. This study examines the use of very low cost CMOS sensors for X-ray imaging and spectroscopy based on the commercial off the shelf (COTS) technology used in cellular telephones, PC multimedia and children's toys. Some examples of imaging using a 'webcam' and a modified OmniVision OV7411 sensor are presented, as well as a simple energy dispersive X-ray detector based on an OmniVision OV7221 sensor. In each case X-ray sensitivity was enabled by replacing the sensor's front glass window with a 5 ?m thick aluminium foil, with X-rays detected as an increase in a pixel's dark current due to the generation of additional electron-hole pairs within its active region. The exposure control and data processing requirements for imaging and spectroscopy are discussed. The modified OV7221 sensor was found to have a linear X-ray energy calibration and a resolution of approximately 510 eV.

Lane, David W.

2012-08-01

293

Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections  

Microsoft Academic Search

The e!ect of interconnect coupling capacitance on the transient characteristics of a CMOS logic gate strongly depends upon the signal activity. A transient analysis of CMOS logic gates driving two and three coupled resistive}capacitive interconnect lines is presented in this paper for di!erent signal combinations. Analytical expressions characterizing the output voltage and the propagation delay of a CMOS logic gate

Kevin T. Tang; Eby G. Friedman

2000-01-01

294

IntroductionIntroduction Development of SerDes IP based on 018nm CMOS  

E-print Network

CMOS technologyA 2.7 Gb/s Adaptive Equalizer in 0.18um CMOS technology 2.7Gb/s Adaptive Feed forward technologyA 2.7 Gb/s Adaptive Equalizer in 0.13um CMOS technology Next Plan - Equalizer filter: Capacitive part: W.S Kim SponsorSponsor System2010 OECC/ACOFT 20081 #12;A 2.7 Gb/s Adaptive Equalizer in 0.18um

Choi, Woo-Young

295

Low-power logic styles: CMOS versus pass-transistor logic  

Microsoft Academic Search

Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with

Reto Zimmermann; Wolfgang Fichtner

1997-01-01

296

Towards a SPR-based biosensing platform incorporating a CMOS active column sensor  

Microsoft Academic Search

A biosensing platform based on surface plasmon resonance and\\u000a incorporating a CMOS imager is being developed. This work comprises\\u000a three different tasks towards this goal: a numerical analysis to\\u000a determine the optimal plasmon resonance conditions, a numerical analysis\\u000a to select the best CMOS photodiode and the architecture proposal of a\\u000a CMOS imager. A simulation with COMSOL of a Kretschmann configuration

A. a Salazar; S. a Camacho-Leon; S. O. a Martnez-Chapa; O. b Rossetto

2013-01-01

297

Post-CMOS Compatible Micromachining Technique for On-Chip Passive RF Filter Circuits  

Microsoft Academic Search

This paper reports on a post-CMOS compatible micromachining technology for passive RF circuit integration. The micromachining technology combines the formation of high performance microelectromechanical systems solenoid inductors and metal-insulator-metal (MIM) capacitors by using a post CMOS process on standard CMOS substrate. Utilizing this process, novel on-chip 3-D configured RF filters for 5 GHz band are integrated on-chip. Two types of

Zhengzheng Wu; Lei Gu; Xinxin Li

2009-01-01

298

Low-cost epoxy packaging of CMOS Hall-effect compasses  

Microsoft Academic Search

For the first time, a compass using CMOS Hall-sensors in a low-cost epoxy package is presented. Due to the high mechanical stress sensitivity of CMOS Hall-sensors, such low-cost plastic or epoxy mold packages have not been a viable option for low-offset applications like the compass application. Instead, expensive ceramic packages have been used. A recently developed, stress insensitive, CMOS Hall-sensor,

Jeroen van der Meer; Frank Riedijk; E. van Kampen; K. Makinwa; J. Huijsing

2005-01-01

299

High Speed Low Gate Leakage Large Capacitive-Load Driver Circuits for Low-Voltage CMOS  

Microsoft Academic Search

In this work, a high-speed full swing driver for large capacitive-loads for low-voltage CMOS applications is presented. The driver which has multi-path for driving the load has a low gate leakage. It works similar to a standard CMOS gate and can be implemented in any CMOS fabrication technology. The circuit does not use extra bootstrap capacitors, has a small effective

B. Kheradmand-Boroujeni; A. Seyyedi; A. Afzali-Kusha

2005-01-01

300

X-ray laminographic application of lens-coupled CMOS detector for PCB inspection  

Microsoft Academic Search

A lens-coupled CMOS detector has been tested for the application in X-ray laminography, which is a tomographic technique recently popular in the nondestructive inspection of printed circuit boards (PCBs). The lens-coupled CMOS detector is extremely cost-effective because of the simple configuration and the well-known CMOS technology. For the feasibility test, we have acquired X-ray images at various imaging conditions and

Ho Kyung Kim; Sung Chae Jeon; Gyuseong Cho; Seong-Hoon Lim

2001-01-01

301

65 nm CMOS Sensors Applied to Mathematically Exact Colorimetric Reconstruction  

E-print Network

Extracting colorimetric image information from the spectral characteristics of image sensors is a key issue in accurate image acquisition. Technically feasible filter/sensor combinations usually do not replicate colorimetric responses with sufficient accuracy to be directly applicable to color representation. A variety of transformations have been proposed in the literature to compensate for this. However, most of those rely on heuristics and/or introduce a reconstruction dependent on the composition of the incoming illumination. In this work, we present a spectral reconstruction method that is independent of illumination and is derived in a mathematically strict way. It provides a deterministic method to arrive at a least mean squared error approximation of a target spectral characteristic from arbitrary sensor response curves. Further, we present a new CMOS sensor design in a standard digital 65nm CMOS technology. Novel circuit techniques are used to achieve performance comparable with much larger-sized spe...

Mayr, C; Krause, A; Schller, J -U; Schffny, R

2014-01-01

302

Diffuse reflectance measurements using lensless CMOS imaging chip  

NASA Astrophysics Data System (ADS)

To assess superficial epithelial microcirculation, a diagnostic tool should be able to detect the heterogeneity of microvasculature, and to monitor qualitative derangement of perfusion in a diseased condition. Employing a lensless CMOS imaging chip with an RGB Bayer filter, experiments were conducted with a microfluidic platform to obtain diffuse reflectance maps. Haemoglobin (Hb) solution (160 g/l) was injected in the periodic channels (grooves) of the microfluidic phantom which were covered with ~250 ?m thick layer of intralipid to obtain a diffusive environment. Image processing was performed on data acquired on the surface of the phantom to evaluate the diffuse reflectance from the subsurface periodic pattern. Thickness of the microfluidic grooves, the wavelength dependent contrast between Hb and the background, and effective periodicity of the grooves were evaluated. Results demonstrate that a lens-less CMOS camera is capable of capturing images of subsurface structures with large field of view.

Schelkanova, I.; Pandya, A.; Shah, D.; Lilge, L.; Douplik, A.

2014-10-01

303

High dynamic range CMOS (HDRC) imagers for safety systems  

NASA Astrophysics Data System (ADS)

The first part of this paper describes the high dynamic range CMOS (HDRC) imager - a special type of CMOS image sensor with logarithmic response. The powerful property of a high dynamic range (HDR) image acquisition is detailed by mathematical definition and measurement of the optoelectronic conversion function (OECF) of two different HDRC imagers. Specific sensor parameters will be discussed including the pixel design for the global shutter readout. The second part will give an outline on the applications and requirements of cameras for industrial safety. Equipped with HDRC global shutter sensors SafetyEYE is a high-performance stereo camera system for safe three-dimensional zone monitoring enabling new and more flexible solutions compared to existing safety guards.

Strobel, Markus; Dttling, Dietmar

2013-04-01

304

Smart CMOS image sensor for lightning detection and imaging.  

PubMed

We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256256 pixel array and a 60 ?m pixel pitch has been fabricated using a 0.35 ?m 2P 5M technology and tested to validate the selected detection approach. PMID:23458812

Rolando, Sbastien; Goiffon, Vincent; Magnan, Pierre; Corbire, Franck; Molina, Romain; Tulet, Michel; Brart-de-Boisanger, Michel; Saint-P, Olivier; Guiry, Saprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

2013-03-01

305

High Speed Smart CMOS Sensor for Adaptive Optics - Poster Paper  

Microsoft Academic Search

We describe the design and experimental performance of a smart Shack-Hartmann wavefront sensor based on a high speed CMOS imager chip and a Field Programmable Gate Array (FPGA) capable of full frame operation at 500 frames\\/s and operated via simple USB2.0 interface. Two FPGA firmware designs are described. The serial version is most suited to modest speed (100 frames\\/s) high

T. D. Raymond; Daniel R. Neal; A. Whitehead; G. Wirth

2008-01-01

306

CMOS Phased Array Transceiver Technology for 60 GHz Wireless Applications  

Microsoft Academic Search

Based on the indoor radio-wave propagation analysis, and the fundamental limits of CMOS technology it is shown that phased array technology is the ultimate solution for the radio and physical layer of the millimeter wave multi-Gb\\/s wireless networks. A low-cost, single-receiver array architecture with RF phase-shifting is proposed and design, analysis and measurements of its key components are presented. A

Mohammad Fakharzadeh; Mohammad-Reza Nezhad-Ahmadi; Behzad Biglarbegian; Javad Ahmadi-Shokouh; Safieddin Safavi-Naeini

2010-01-01

307

Single core fully integrated CMOS micro-fluxgate magnetometer  

Microsoft Academic Search

A new fully integrated 2D micro-fluxgate magnetometer is presented. This magnetometer is integrated in a standard CMOS process and uses a ferromagnetic core integrated on the chip by a photolithographic post-process compatible with the integrated circuit technology. The cross-shaped ferromagnetic core is placed diagonally above four excitation coils, two for each measurement axis. A novel electronic signal extraction technique is

Predrag M. Drlja?a; Pavel Kejik; Franck Vincent; Dominique Piguet; Franois Gueissaz; Radivoje S. Popovi?

2004-01-01

308

Variable gain CMOS potentiostat for dissolved oxygen sensor  

Microsoft Academic Search

This paper presents a variable gain potetiostat designed for the electrochemical control of Dissolved Oxygen (DO) sensors. The design is targeted for implementation using MIMOS 0.35 um CMOS process technology at 3.3V. The potentiostat amplifier for dissolved oxygen utilizes three electrodes (working, reference and counter) which work together to form the electrochemical reaction. There are several types of DO sensor

Mei Yee Ng; Yuzman Yusoff

2010-01-01

309

Low phase noise CMOS voltage-controlled oscillators  

Microsoft Academic Search

Design considerations and performance comparisons for several low phase noise CMOS voltage-controlled oscillator (VCO) topologies are presented including the Hartley, quadrature Colpitts, Clapp, and tuned-input tuned-output configurations. An indirect approach for high-frequency signal generation using a VCO coupled with a 2X passive frequency multiplier is also described. Several of the structures are attractive alternatives to the conventional LC tank VCO.

David J. Allstot; Sankaran Aniruddhan; Min Chu; Nathan M. Neihart; Dicle Ozis; S. Shekhar; J. S. Walling

2007-01-01

310

Class-G headphone driver in 65nm CMOS technology  

Microsoft Academic Search

A 65 nm CMOS Class-G headphone driver operates from 1.4 V, 0.35 V supplies. At low power level it uses the low voltage supply to reduce the dissipation to 1.63 mW @ Pout = 0.5 mW into 32 . At higher power level, the smooth transition between the voltage supply rails allows a THD+N better than -80 dB for Pout

Alex Lollio; Giacomino Bollati; Rinaldo Castello

2010-01-01

311

An alternative to source degeneration of CMOS differential pair  

Microsoft Academic Search

This paper presents a method to extend linear range of conventional CMOS source-coupled pair with transistor polarised on\\u000a saturation of strong inversion. The used principle is similar to the principle of source degeneration, but the additional\\u000a device is horizontally added, in parallel with the input transistors, which overcame the constraints on common mode range\\u000a and supply voltage and allow low

Aimad El Mourabit; Mohamed-halim Sbaa; Guo-Neng Lu; Patrick Pittet

2010-01-01

312

Simulation of design dependent failure exposure levels for CMOS ICs  

SciTech Connect

The total dose exposure of CMOS ICs introduces bias-dependent parameter shifts in individual devices. The bias dependency of individual parameter shifts of devices cause different designs to behave differently under identical testing conditions. This paper studies the effect of design and bias on the radiation tolerance of ICs and presents an automated design tool that produces different designs for a logic function, and presents important parameters of each design to circuit designer for trade off analysis.

Kaul, N.; Bhuva, B.L.; Rangavajjhala, V.; van der Molen, H.; Kerns, S.E. (Vanderbilt Univ., Nashville, TN (USA). Dept. of Electrical Engineering)

1990-12-01

313

Analysis of Timing Jitter in CMOS Ring Oscillators  

Microsoft Academic Search

in this paper the effects of thermal noise in transistors on timing jitter in CMOS ring-oscillators composed of source-coupled differential resistively-loaded delay cells is investigated. The relationship between delay element design parameters and the inherent thermal noise-induced jitter of the generated waveform are analyzed. These results are compared with simulated results from a Monte-Carlo analysis with good agreement. The analysis

Todd C. Weigandt; Beomsup Kim; Paul R. Gray

1994-01-01

314

CMOS RF Integrated Circuits: Past, Present and Future (Invited)  

Microsoft Academic Search

CMOS RF ICs continue their transition from academic curiosities to practical devices. Recent milestones at the device- and building block-level include: Noise figures for single-ended LNAs of ~ldB in the low-GHz range; fully integrated oscillators with phase noise compliant with GSM specifications at under lOmW power consumption; 5GHz injection-locked frequency dividers with sub-mW power consumption and large (~30%) tuning range;

Thomas H. Lee

1999-01-01

315

CMOS silicon avalanche photodiodes for NIR light detection: a survey  

Microsoft Academic Search

This paper surveys recent research on CMOS silicon avalanche photodiodes (SiAPD) and presents the design of a SiAPD based\\u000a photoreceiver dedicated to near-infrared spectroscopy (NIRS) application. Near-infrared spectroscopy provides an inexpensive,\\u000a non-invasive, and portable means to image brain function, and is one of the most efficient diagnostic techniques of different\\u000a neurological diseases. In NIRS system, brain tissue is penetrated by

Ehsan Kamrani; Mohamad Sawan

316

CMOS low-noise amplifier design optimization techniques  

Microsoft Academic Search

This paper reviews and analyzes four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-constrained simultaneous noise and input matching (PCSNIM) techniques. Very simple and insightful sets of noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques.

Trung-Kien Nguyen; Chung-Hwan Kim; Gook-Ju Ihm; Moon-Su Yang; Sang-Gug Lee

2004-01-01

317

Low complexity CMOS competitive array for approaching assignments  

Microsoft Academic Search

This work presents a CMOS analog integrated circuit in which an array of 88 winner-take-all neural units or competitive units computes binary matrices as an approach to the solution of assignment problems. The small silicon area in this system results from using early low-complexity current-mode circuits. The dynamic performance for selecting winning units by this prototype analog integrated circuit that

F. Gomez-Casraneda; Luis M. Flores-Nava; J. A. Moreno-Cadenas

1998-01-01

318

A CMOS digitally programmable filter technique for VLSI applications  

Microsoft Academic Search

A novel technique for designing analog CMOS integrated filters is proposed. The technique uses digitally controlled current\\u000a amplifiers (DCCAs) to provide precise frequency and\\/or gain characteristics that can be digitally tuned over a wide range.\\u000a This paper provides an overview of the possibilities of using the DCCA as the core element in programmable filters. In mixed\\u000a analog\\/digital systems, the digital

Hussain Abdullah Alzaher

2008-01-01

319

An integrated CMOS-CCD TV ghost canceler  

Microsoft Academic Search

Two transversal filters with 0.1 and 0.3?s tap spacing, providing 15dB suppression for ghost delays up to 20?s, have been developed. This paper will describe the CMOS-CCD technology employed to achieve a chip dissipation of 500mW, and the use of half of the peripheral components required for NMOS-CCD implementation.

S. Matsumoto; K. Kondo; T. Murata; M. Kazumi; S. Matsuura; I. Kobayashi; N. Horino

1984-01-01

320

A Cmos Interface for Thermocouples with Reference-Junction Compensation  

Microsoft Academic Search

This paper presents a CMOS interface for a thermocouple, includingreference-junction compensation. The interface contains a first-orderoscillator whose period is modulated by the signal from the thermocouple(VX) and two other signals generated internally. One is abase-emitter voltage (VBE) and the other is a PTAT voltage(VPTAT). Linear combinations of the periods corresponding tothese two voltages are made by a C, to obtain

Saleh H. Khadouri; Gerard C. M. Meijer; Frank M. L. van der Goes

1997-01-01

321

A generation of CMOS readout ASICs for CZT detectors  

Microsoft Academic Search

As a result of a cooperation between Brookhaven National Laboratory and eV Products a generation of high performance readout ASICs was developed. The ASICs, realized in CMOS 0.5 ?m technology, are available in several different versions, single or multi-channel and with unipolar or bipolar shaper, in view of their use in research, spectroscopy, medical, safeguard and industrial applications. Four innovative

G. De Geronimo; P. O'Connor; J. Grosholz

1999-01-01

322

A generation of CMOS readout ASICs for CZT detectors  

Microsoft Academic Search

As a result of a cooperation between Brookhaven National Laboratory and eV Products a generation of high performance readout ASICs was developed. The ASICs, realized in CMOS 0.5 ?m technology, are available in several different versions, single or multi-channel and with unipolar or bipolar shaper, in view of their use in research, spectroscopy, medical, safeguard and industrial applications. Four innovative

G. De Geronimo; P. O'Connor; J. Grosholz

2000-01-01

323

A parallel analog CCD\\/CMOS neural network IC  

Microsoft Academic Search

A mixed analog\\/digital neural network chip is presented that uses standard 2-?m CCD\\/CMOS fabrication. The device incorporates a matrix of charge injection device elements which hold a matrix of charge encoding the synapse strengths. A vector-matrix multiplier with simple charge-domain multiply-accumulate units has been implemented. The device computes the product of a binary vector and an analog matrix of charge,

C. F. Neugebauer; A. Yariv

1991-01-01

324

Comparison of CMOS microprocessors and single chip microcomputers  

Microsoft Academic Search

Three CMOS (Complimentary Metal Oxide Semiconductor) 8 bit microprocessors (CPU) and eleven versions of three single chip microcomputers (MCU) have been compared regarding hardware features, assembly language, bus architecture, and internal register architecture. They are the Intersil IM6100, National Semiconductor NSC-800, RCA CDP1802, Motorola MC146805E2, National Semiconductor NS80C35, and the RCA CDP1805. Several power reduction techniques for microcomputer systems are

T. Fryberger

1982-01-01

325

POWER HARVESTING AND TELEMETRY IN CMOS FOR IMPLANTED DEVICES  

Microsoft Academic Search

Implanted sensors offer many advantages to those studying the behavior of the human body. Unfortunately, the need to power and communicate with devices often requires tradeoffs that compromise their usefulness. We describe a power harvesting and telemetry chip that allows operation without wires or batteries. The chip has been fabricated in 0.5m CMOS. The chip is able to supply 2mA

Christian Sauer; Milutin Stanacevic; Gert Cauwenberghs; Nitish Thakor

2005-01-01

326

CMOS compatible Multiple Power-Output MEMS Radioisotope ?-Power Generator  

Microsoft Academic Search

The authors demonstrate a novel 6.6% high-efficiency CMOS compatible piezoelectric aluminum nitride (AlN) thin-film based integrated ?-radioisotope-powered electro-mechanical power generator (IREMPG). the authors integrate silicon betavoltaics with radioisotope actuated piezoelectric unimorph converters to efficiently utilize both kinetic energy and charge of the emitted beta particles for electrical power generation. IREMPG has three output ports generating (1) a 2.8MHz pulse remotely

Rajesh Duggirala; A. Lai; Ronald G. Polcawich; Madan Dubey

2006-01-01

327

Analog CMOS Implementation of Neural Network for Adaptive Signal Processing  

Microsoft Academic Search

A modular analog CMOS artificial neural network is designed and fabricated for adaptive signal processing. A modified Gilbert multiplier is used as a linear combination of several input signals. Modified back-propagation continuous-time learning rules are used as an adaptive algorithm. The adaptive algorithm adjusts the weights in real time by on-chip learning circuits. Hardware learning circuits are simulated using PSPICE,

Oh Hwa-joon; Fathi M. A. Salam

1994-01-01

328

High Performance CMOS Image Sensor for Low Light Imaging  

Microsoft Academic Search

We present a prototype CMOS image sensor (CIS) intended for low light imaging applications. The prototype sensor contains 320 x 240 pixels with 36 different pixel architectures. Pixel size is 10.8 m x 10.8 m. The measured QE is 55% at 555nm, dark current is 11pA\\/cm 2 at 30 ?C, read noise is 1.9e- RMS operating at 30 Mpixels\\/sec, and

Boyd Fowler; Steve Mims; Brett Frymire

329

CMOS image sensor binning circuit for low-light imaging  

Microsoft Academic Search

This work presents a column level binning circuit for a CMOS image sensor for detecting low-light imaging. A 22 kernel pixel binning (averaging) is employed in this design reducing the spatial resolution to 1\\/4 of the original size and every two columns of the pixel array share one binning circuit. The output signal of each pixel is sampled unto the

Hong-Yi Huang; Patrick Adrian Conge; Li-Wei Huang

2011-01-01

330

CMOS bandgap references and temperature sensors and their applications  

Microsoft Academic Search

Two main parts have been presented in this thesis: device characterization and circuit. \\u000aIn integrated bandgap references and temperature sensors, the IC(VBE, characteristics of bipolar transistors are used to generate the basic signals with high accuracy. To investigate the possibilities to fabricate high-precision bandgap references and temperature sensors in low-cost CMOS technology, the electrical characteristics of substrate bipolar pnp transistors

G. Wang

2005-01-01

331

A CMOS microcoil-associated preamplifier for NMR spectroscopy  

Microsoft Academic Search

For improving sensitivity of nuclear magnetic resonance (NMR) measurements, an in-field preamplifier in a low-cost CMOS process is presented. It is based on a second-generation positive current conveyor (CCII+), with an impedance-matching output stage. The circuit has been designed with optimization of key performances, such as bandwidth, noise, and offset voltage. There have also been precautions taken against potential effect

Tewfik Cherifi; Nacer Abouchi; Guo-Neng Lu; Latifa Bouchet-Fakri; Laurent Quiquerez; B. Sorli; Jean-Franois Chateaux; M. Pitaval; P. Morin

2005-01-01

332

Self-checking CMOS circuits using pass-transistor logic  

Microsoft Academic Search

This article presents a new approach to implementing self-checking circuits in CMOS technology. Implementations are made self-checking with respect to a single line stuck-at 0\\/1 fault. It is assumed that stuck faults at a common gate of neighboring PMOS and NMOS are not independent and the contact between a PMOS (NMOS) source and a power (ground) line is fault free.

Kanji Hirabayashi; Komukai Toshiba-cho

1991-01-01

333

A 0.6-V Low Power UWB CMOS LNA  

Microsoft Academic Search

This paper presents the design of a low-power ultra-wideband low noise amplifier in 0.18-mum CMOS technology. The inductive degeneration is applied to the conventional distributed amplifier design to reduce the broadband noise figure under low power operation condition. A common-source amplifier is cascaded to the distributed amplifier to improve the gain at high frequency and extend the bandwidth. Operated at

Yueh-Hua Yu; Yi-Jan Emery Chen; Deukhyoun Heo

2007-01-01

334

A novel DPS integrator for fast CMOS imagers  

Microsoft Academic Search

A novel DPS integrator scheme for fast CMOS imagers is presented, which combines the advantages of analog APS and DPS circuits. The reset-insensitive integrator proposal improves the linearity of the ADC curve, while it allows both low-power consumption for the active blocks and low-voltage operation for the switching devices even at high frame rates. In this sense, a comparative study

Josep Maria Margarit; Justo Sabadell; Llus Ters; Francisco Serra-graells

2008-01-01

335

A lowvoltage CMOS transconductor for very high frequencies  

Microsoft Academic Search

This paper presents a pseudo-differential continuous time transconductor for applications in low-voltage systems over the very high frequency range. By using a 0.8 m CMOS process, the transconductor consumes less than 1.5 mW from a 2.7 V supply. A prototype third-order 60 MHz elliptic lowpass ladder filter with a transmission zero at 200 MHz confirms the feasibility of the proposed

S. Celma; J. Sabadell; C. Aldea; P. A. Martinez

1999-01-01

336

A CMOS THz staring imager with in-pixel electronics  

Microsoft Academic Search

A 16 16 st aring imaging array was implemented in a 0.15-m standard CMOS technology for terahertz detection in the range of 0.8 THz to 1.5 THz. Each pixel is composed of an antenna, a FET detector, and its readout electronics (a current integrator) so that the pixel signals of the whole matrix can be acquired simultaneously. The current

Suzana Domingues; Matteo Perenzoni; David Stoppa; Antonio D. Capobianco; Francesco Sacchetto

2011-01-01

337

Magnetically Coupled Current Sensors Using CMOS Split-Drain Transistors  

Microsoft Academic Search

Integrated current-sensing circuits intended for smart-power and embedded applications featuring galvanic isolation are implemented. They are based on magnetic detection using a CMOS-compatible split-drain transistor that provides a very linear output current versus magnetic field. Two approaches are used to generate the magnetic field: the coil approach and the strip approach. In the first, the current to be sensed flows

Fernando C. Castaldo; Vilson R. Mognon; Carlos A. dos Reis Filho

2009-01-01

338

Bridging Defects Resistance Measurements in a CMOS Process  

Microsoft Academic Search

Measurements on process-related defect nionitwing ,wcijers are presented in order to euuluute the i,csisluiict. ,ualu,e of b ridyzng deJects zn CMOS VLSI circu~ts. 'I'he inethodoloyy u sed is dlustrated and statzstics OIL the 1.esistance values are p resented. As a result, the vast niajoi-zty of the measured brzdges have a 1o.w 7.eszsta.nce. Only a small percentage of the brzdges has

Rosa Rodrguez-montas; Joan Figueras; Eric Bruls

1992-01-01

339

Diagnosing CMOS bridging faults with stuck-at fault dictionaries  

Microsoft Academic Search

It is shown that the traditional approach to diagnosing stuck-at faults with fault dictionaries generated for stuck-at faults is not appropriate for diagnosing CMOS bridging faults. A novel technique for using stuck-at-fault dictionaries to diagnose bridging faults is described. Teradyne's LASAR was used to simulate bridging and stuck-at faults in a number of combinational circuits, including parity trees, multiplexers, and

Steven D. Millman; Edward J. McCluskey; John M. Acken

1990-01-01

340

Below 2.0mum CMOS imager technology shrinks  

Microsoft Academic Search

A quick calculation and accurate estimation algorithm with systematic analysis of optical view is crucial in developing sub 2.0mum imager since as the pixel size scales down below 2.0mum, saturation and sensitivity are reduced more than those expected by nominal scaling factor of CMOS process. In this paper, an unconventional treatment by diffraction focal shift theory is proposed for explaining

H. W. Lee; C. H. Wu

2008-01-01

341

CMOS-compatible AlN piezoelectric micromachined ultrasonic transducers  

Microsoft Academic Search

Piezoelectric micromachined ultrasonic transducers for air-coupled ultrasound applications were fabricated using aluminum nitride (AlN) as the active piezoelectric layer. The AlN is deposited via a low-temperature sputtering process that is compatible with deposition on metalized CMOS wafers. An analytical model describing the electromechanical response is presented and compared with experimental measurements. The membrane deflection was measured to be 210 nm

Stefon Shelton; Mei-Lin Chan; David Horsley; Bernhard Boser; Igor Izyumin; Richard Przybyla; Tim Frey; Michael Judy; K. Nunan; F. Sammoura; Ken Yang

2009-01-01

342

Commercial applications  

NASA Astrophysics Data System (ADS)

The near term (one to five year) needs of domestic and foreign commercial suppliers of radiochemicals and radiopharmaceuticals for electromagnetically separated stable isotopes are assessed. Only isotopes purchased to make products for sale and profit are considered. Radiopharmaceuticals produced from enriched stable isotopes supplied by the Calutron facility at ORNL are used in about 600,000 medical procedures each year in the United States. A temporary or permanent disruption of the supply of stable isotopes to the domestic radiopharmaceutical industry could curtail, if not eliminate, the use of such diagnostic procedures as the thallium heart scan, the gallium cancer scan, the gallium abscess scan, and the low radiation dose thyroid scan. An alternative source of enriched stable isotopes exist in the USSR. Alternative starting materials could, in theory, eventually be developed for both the thallium and gallium scans. The development of a new technology for these purposes, however, would take at least five years and would be expensive. Hence, any disruption of the supply of enriched isotopes from ORNL and the resulting unavailability of critical nuclear medicine procedures would have a dramatic negative effect on the level of health care in the United States.

343

Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm  

E-print Network

This paper presents a BPD (Balanced Power Dissipation) heuristic scheduling algorithm applied to VLSI CMOS digital circuits/systems in order to reduce the global computational demand and provide balanced power dissipation of computational units of the designed digital VLSI CMOS system during the task assignment stage. It results in reduction of the average and peak temperatures of VLSI CMOS digital circuits. The elaborated algorithm is based on balanced power dissipation of local computational (processing) units and does not deteriorate the throughput of the whole VLSI CMOS digital system.

Wladyslaw Szczesniak

2008-01-07

344

Organic thin-film transistors for flexible CMOS integration  

NASA Astrophysics Data System (ADS)

In this work a fully photolithographically defined complementary metal oxide semiconductor (CMOS) device is fabricated. Particular focus was on the use of solution based materials for device integration. P-type and n-type materials were evaluated for use in an organic thin film transistor (OTFT) device. The reliability and organic thin-film transistor performance of solution based dielectric polymeric dielectric materials are presented. Fabrication and characterization of integrated hybrid complementary metal oxide semiconductor devices (CMOS) using 6, 13-bis (triisopropylsilylethynyl) pentacene (TIPS-PC) and cadmium sulfide (CdS) as the active layers deposited using solution based processes are demonstrated. The hybrid CMOS technology demonstrated is compatible with large-area and mechanically flexible substrates given the low temperature processing (<100C) and scalable design. Devices evaluated are diodes, n- and p-type thin film transistors (TFTs), inverters, NAND and NOR gates. The inverters exhibited a DC gain of ?52 V/V with full rail-to-rail switching. The NAND logic gates switch rail-to-rail with a transition point of V DD/2.

Perez, Michael Ramon

345

Neuronal cell biocompatibility and adhesion to modified CMOS electrodes.  

PubMed

The use of CMOS (Complementary Metal Oxide Semiconductor) integrated circuits to create electrodes for biosensors, implants and drug-discovery has several potential advantages over passive multi-electrode arrays (MEAs). However, unmodified aluminium CMOS electrodes may corrode in a physiological environment. We have investigated a low-cost electrode design based on the modification of CMOS metallisation to produce a nanoporous alumina electrode as an interface to mammalian neuronal cells and corrosion inhibitor. Using NG108-15 mouse neuroblastoma x rat glioma hybrid cells, results show that porous alumina is biocompatible and that the inter-pore distance (pore pitch) of the alumina has no effect on cell vitality. To establish whether porous alumina and a cell membrane can produce a tight junction required for good electrical coupling between electrode and cell, we devised a novel cell detachment centrifugation assay to assess the long-term adhesion of cells. Results show that porous alumina substrates produced with a large pore pitch of 206 nm present a significantly improved surface compared to the unmodified aluminium control and that small pore-pitches of 17 nm and 69 nm present a less favourable surface for cell adhesion. PMID:19459049

Graham, Anthony H D; Bowen, Chris R; Taylor, John; Robbins, Jon

2009-10-01

346

Optimization of precision localization microscopy using CMOS camera technology  

NASA Astrophysics Data System (ADS)

Light microscopy imaging is being transformed by the application of computational methods that permit the detection of spatial features below the optical diffraction limit. Successful localization microscopy (STORM, dSTORM, PALM, PhILM, etc.) relies on the precise position detection of fluorescence emitted by single molecules using highly sensitive cameras with rapid acquisition speeds. Electron multiplying CCD (EM-CCD) cameras are the current standard detector for these applications. Here, we challenge the notion that EM-CCD cameras are the best choice for precision localization microscopy and demonstrate, through simulated and experimental data, that certain CMOS detector technology achieves better localization precision of single molecule fluorophores. It is well-established that localization precision is limited by system noise. Our findings show that the two overlooked noise sources relevant for precision localization microscopy are the shot noise of the background light in the sample and the excess noise from electron multiplication in EM-CCD cameras. At low light conditions (< 200 photons/fluorophore) with no optical background, EM-CCD cameras are the preferred detector. However, in practical applications, optical background noise is significant, creating conditions where CMOS performs better than EM-CCD. Furthermore, the excess noise of EM-CCD is equivalent to reducing the information content of each photon detected which, in localization microscopy, reduces the precision of the localization. Thus, new CMOS technology with 100fps, <1.3 e- read noise and high QE is the best detector choice for super resolution precision localization microscopy.

Fullerton, Stephanie; Bennett, Keith; Toda, Eiji; Takahashi, Teruo

2012-02-01

347

Aluminum nitride on titanium for CMOS compatible piezoelectric transducers  

PubMed Central

Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d33f, d31 and d33 of up to 2.9, ?1.9 and 6.5 pm V?1, respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals. PMID:20333316

Doll, Joseph C; Petzold, Bryan C; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L

2010-01-01

348

CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.  

SciTech Connect

Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

2008-08-01

349

Noise performance and ionizing radiation tolerance of CMOS Monolithic Active Pixel Sensors using the 0.18?m CMOS process  

NASA Astrophysics Data System (ADS)

CMOS Monolithic Active Pixel Sensors (MAPS) have demonstrated excellent performance as tracking detectors for charged particles. They provide an outstanding spatial resolution (a few ?m), a detection efficiency of gtrsim99.9%, very low material budget (0.05% X0) and good radiation tolerance (gtrsim 1 Mrad, gtrsim 1014 neq/cm2) [1]. This recommends them as an interesting technology for various applications in heavy ion and particle physics. For the vertex detectors of CBM and ALICE, we are aiming at developing large scale sensors with an integration time of 30?s. Reaching this goal is eased by features available in CMOS-processes with 0.18?m feature size. To exploit this option, some sensor designs have been migrated from the previously used 0.35?m processes to this novel process. We report about our first findings with the devices obtained with a focus on noise and the tolerance to ionizing radiation.

Doering, D.; Baudot, J.; Deveaux, M.; Linnik, B.; Goffe, M.; Senyukov, S.; Strohauer, S.; Stroth, J.; Winter, M.

2014-05-01

350

Associate Program, Commercial Banking Commercial Banking  

E-print Network

Associate Program, Commercial Banking Commercial Banking Job Code 0203 � Level 6 CIBC is a leading and services to 11 million individual, small business, commercial, corporate and institutional clients Group of Companies please visit CIBC.com. Job Overview The Commercial Banking Associate Program provides

Northern British Columbia, University of

351

COMMERCIAL SPACE ACCOMPLISHMENTS Commercial Cargo Space Accomplishments  

E-print Network

11/13/2013 COMMERCIAL SPACE ACCOMPLISHMENTS Commercial Cargo Space Accomplishments The Obama Administration's ambitious commercial space program, which has bipartisan support in Congress, has enabled NASA NASA does business, helping build a strong American commercial space industry, and freeing the agency

Waliser, Duane E.

352

Pressure Sensor Monolithically Integrating MEMS and CMOS-LSI with CMOS Compatible ``Back-end-of-line MEMS processes''  

Microsoft Academic Search

Back-end-of-line (BEOL) MEMS processes for a compact, high-precision pressure sensor was developed. A CMOS-LSI-integrated capacitive pressure-sensor was fabricated with a chip size of 0.72 mm2 using developed BEOL MEMS processes. Multi-sensor chip (with a size of 1.7 by 1.9 mm2) which consists of pressure sensor, temperature sensor and high-precision measurement circuits was also fabricated, and precise atmospheric pressure measurement (~

Tsukasa Fujimori; Hideaki Takano; Yuko Hanaoka; Yasushi Goto

2010-01-01

353

Digital pixel CMOS focal plane array with on-chip multiply accumulate units for low-latency image processing  

NASA Astrophysics Data System (ADS)

A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization occurs at the pixel level, enabling in-pixel DSP and noiseless data transfer from the pixel array to the peripheral processing units. The pipelined processing of row and column image data prior to off chip readout reduces the required output bandwidth of the image sensor, thus reducing the latency of computations necessary to implement various image processing systems. Data volume reductions of over 80% lead to sub 10?s latency for completing various tracking and sensor algorithms. This paper details the architecture of the pixel-processing imager (PPI) and presents some initial results from a prototype device fabricated in a standard 65nm CMOS process hybridized to a commercial off-the-shelf short-wave infrared (SWIR) detector array.

Little, Jeffrey W.; Tyrrell, Brian M.; D'Onofrio, Richard; Berger, Paul J.; Fernandez-Cull, Christy

2014-06-01

354

CMOS compatible thin-film ALD tungsten nanoelectromechanical devices  

NASA Astrophysics Data System (ADS)

This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different WALD fabrication technologies two generations of 2-terminal WALD NEMS switches have been developed. These devices have functional gap heights of 30-50 nm, and actuation voltages typically ranging from 3--5 Volts. Via the extension of a two terminal WALD technology novel 3-terminal WALD NEMS devices were developed. These devices have actuation voltages ranging from 1.5--3 Volts, reliabilities in excess of 2 million cycles, and have been designed to be the fundamental building blocks for WALD NEMS complementary inverters. Through the development of these devices several advancements in the modeling and design of thin-film NEMS devices were achieved. A new model was developed to better characterize pre-actuation currents commonly measured for NEMS switches with nano-scale gate-to-source gap heights. The developed model is an extension of the standard field-emission model and considers the electromechanical response, and electric field effects specific to thin-film NEMS switches. Finally, a multi-physics FEM/FD based model was developed to simulate the dynamic behavior of 2 or 3-terminal electrostatically actuated devices whose electrostatic domains have an aspect ratio on the order of 10-3. The model uses a faux-Lagrangian finite difference method to solve Laplaces equation in a quasi-statatically deforming domain. This model allows for the numerical characterization and design of thin-film NEMS devices not feasible using typical non-specialized BEM/FEM based software. Using this model several novel and feasible designs for fixed-fixed 3-terminal WALD NEMS switches capable for the construction of complementary inverters were discovered.

Davidson, Bradley Darren

355

CMOS analog and radio-frequency integrated-circuit design employing low-power switched-capacitor techniques.  

E-print Network

??We propose and verify the design of low-power, high-performance CMOS Switched-Capacitor (SC) circuits for analog and radio-frequency (RF) applications. In low-cost CMOS semiconductor processes, SC (more)

Song, Yu (1980 - )

2011-01-01

356

High gain CMOS image sensor design and fabrication on SOI and bulk technology  

NASA Astrophysics Data System (ADS)

The CMOS imager is now competing with the CCD imager, which still dominates the electronic imaging market. By taking advantage of the mature CMOS technology, the CMOS imager can integrate AID converters, digital signal processing (DSP) and timing control circuits on the same chip. This low cost and high-density integration solution to the image capture is the strong driving force in industry. Silicon on insulator (SOI) is considered as the coming mainstream technology. It challenges the current bulk CMOS technology because of its reduced power consumption, high speed, radiation hardness etc. Moving the CMOS imager from the bulk to the SOI substrate will benefit from these intrinsic advantages. In addition, the blooming and the cross-talk between the pixels of the sensor array can be ideally eliminated, unlike those on the bulk technology. Though there are many advantages to integrate CMOS imager on SOI, the problem is that the top silicon film is very thin, such as 2000. Many photons can just pass through this layer without being absorbed. A good photo-detector on SOI is critical to integrate SOI CMOS imagers. In this thesis, several methods to make photo-detectors on SOI substrate are investigated. A floating gate MOSFET on SOI substrate, operating in its lateral bipolar mode, is photon sensitive. One step further, the SOI MOSFET gate and body can be tied together. The positive feedback between the body and gate enables this device have a high responsivity. A similar device can be found on the bulk CMOS technology: the gate-well tied PMOSFET. A 32 x 32 CMOS imager is designed and characterized using such a device as the light-sensing element. I also proposed the idea of building hybrid active pixels on SOI substrate. Such devices are fabricated and characterized. The work here represents my contribution on the CMOS imager, especially moving the CMOS imager onto the SOI substrate.

Zhang, Weiquan

2000-12-01

357

Optimization of CMOS Transistors for Low Power DC-DC Converters Abstract: This paper presents analytical derivation of  

E-print Network

Optimization of CMOS Transistors for Low Power DC-DC Converters Abstract: This paper presents analytical derivation of optimum width of CMOS transistors to minimize losses in monolithic buck converters. High optimal width of CMOS transistors entails use of tapered inverter chain as gate driver. A novel

Chapman, Patrick

358

Experimental and Theoretical Evaluation of a High Resolution CMOS Based Detector Under X-Ray Imaging Conditions  

Microsoft Academic Search

Fundamental imaging performance in terms of Mod- ulation Transfer Function (MTF), Noise Power Spectrum (NPS) and Detective Quantum Efficiency (DQE) was investigated for a high resolution CMOS based imaging sensor. The device consists of a 33.91 :Tb scintillator screen, placed in direct contact with a CMOS photodiode array. The CMOS photodiode array, featuring 1200 1600 pixels with a pixel pitch

Christos M. Michail; Vasiliki A. Spyropoulou; George P. Fountos; Nektarios I. Kalyvas; Ioannis G. Valais; Ioannis S. Kandarakis; George S. Panayiotakis

2011-01-01

359

Full-Custom Design Project for Digital VLSI and IC Design Courses using Synopsys Generic 90nm CMOS Library  

E-print Network

custom fashion from schematic to layout in the generic 90nm CMOS technology. The developed design flow aspects of design from schematic to layout. Given the rapid progress of industry in scaling of CMOS to reflect these rapid industry developments. For most universities, access to modern CMOS technologies can

Mahmoodi, Hamid

360

Detection of On-chip Temperature Gradient Using a 1.5V Low Power CMOS Temperature Sensor  

E-print Network

Detection of On-chip Temperature Gradient Using a 1.5V Low Power CMOS Temperature Sensor Yiming@glue.umd.edu Abstract--We present a 1.5V low power CMOS temperature sensor for detection of on-chip temperature the primary temperature gradients. We report a tiny 1.5V low power CMOS temperature sensor and demonstrate its

Maryland at College Park, University of

361

Estimation of On-Chip Simultaneous Switching Noise on Signal Delay in Synchronous CMOS Integrated Circuits  

Microsoft Academic Search

On-chip parasitic inductance inherent to the power distribution network has becoming significant in high speed digital circuits. Therefore, current surges result in voltage fluctuations within the power distribution network, creating delay uncertainty. On-chip simultaneous switching noise should therefore be considered when estimating the propagation delay of a CMOS logic gate in high speed synchronous CMOS integrated circuits.

Kevin T. Tang; Eby G. Friedman

362

Delay uncertainty due to on-chip simultaneous switching noise in high performance CMOS integrated circuits  

Microsoft Academic Search

On-chip parasitic inductance inherent to the power supply rails has become significant in high speed digital circuits. Therefore, current surges result in voltage fluctuations within the power distribution networks, creating delay uncertainty. On-chip simultaneous switching noise should therefore be considered when estimating the propagation delay of a CMOS logic gate in high speed synchronous CMOS integrated circuits. Analytical expressions characterizing

Kevin T. Tang; Eby G. Friedman

2000-01-01

363

A 400 to 500-MHz CMOS Power Amplifier with Multi-Watt Output  

E-print Network

A 400 to 500-MHz CMOS Power Amplifier with Multi-Watt Output Jeongmin Jeon, Student Member, IEEE ­- A two-stage P-band (400 MHz) CMOS multi-Watt Power Amplifier (PA) is reported. Four identical 1.25-Watt PA cells are power-combined to generate approximately 5-Watt output. The same PA chip is used

Kuhn, William B.

364

A Redox-Enzyme-Based Electrochemical Biosensor with a CMOS Integrated Bipotentiostat  

E-print Network

A Redox-Enzyme-Based Electrochemical Biosensor with a CMOS Integrated Bipotentiostat Yue Huang enzymes and a supporting CMOS bipotentiostat. The bipotentiostat architecture supports redox recycling was created on a microfabricated interdigitated electrode array as an example redox-enzyme-based biosensor

Mason, Andrew

365

QUBiC4: a silicon RF-BiCMOS technology for wireless communication ICs  

Microsoft Academic Search

QUBiC4 is a silicon RF-BiCMOS technology with NPN ft\\/f max up to 40\\/100 GHz, 0.25 ?m CMOS, high quality passives, and five metal layers for wireless applications. LNA noise figure of 0.99 dB at 2 GHz has been achieved

D. Szmyd; R. Brock; N. Bell; S. Harker; G. Patrizi; J. Fraser; R. Dondero

2001-01-01

366

Smart-pixel cellular neural networks in analog current-mode CMOS technology  

Microsoft Academic Search

This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light detection is made with vertical CMOS-BJT's connected in a Darlington structure. Pixel smartness is achieved by exploiting the cellular neural network paradigm, incorporating at each pixel location an analog computing

S. Espejo; A. Rodriguez-Vazquez; R. Dominguez-Castro; J. L. Huertas; E. Sanchez-Sinencio

1994-01-01

367

CMOS tunable bandpass RF filters utilizing coupled on-chip inductors  

Microsoft Academic Search

A novel scheme for tunable integrated CMOS bandpass RF filters using magnetically coupled on-chip inductors is proposed. A filter designed in a 0.6 ?m CMOS process exhibits a blocking dynamic range of over 70 dB, when tuned at a center frequency in the range of 900-1000 MHz and a filter Q of 25

Sotiris Bantas; Yannis Papananos; Yorgos Koutsoyannopoulos

1999-01-01

368

CMOS transconductor VCO with adjust~bia operating and centre frequencies  

E-print Network

fabricated in CMOS have typically been composed of current-starved ring oscil- lators [I, 2], which haveLimum current out of the transconductor stage. During linear operation, I. =r. + 1_ Therefore. when V_ = 0, IDII.J. Baker and H.W. Li Indexing terms: CMOS integrated circuits, Voltage controlled oscillators A novel

Baker, R. Jacob

369

ULP Variability-Insensitive SRAM Design in sub-32nm UTBB FDSOI CMOS  

E-print Network

ULP Variability-Insensitive SRAM Design in sub-32nm UTBB FDSOI CMOS Adam Makosiej1 , Andrei This paper describes a design approach based on optimization of embedded SRAMs that takes advantage on an analytical model including statistical variations for Static Noise Margin (SNM) of CMOS SRAMs operating

Paris-Sud XI, Université de

370

Evaluation of the upset risk in CMOS SRAM through full three dimensional simulation  

SciTech Connect

Upsets caused by incident heavy ion on CMOS static RAM are studied here. Three dimensional device simulations, based on a description of a full epitaxial CMOS inverter, and experimental results are reported for evaluation of single and multiple bit error risk. The particular influences of hit location and incidence angle are examined.

Moreau, Y.; Gasiot, J. [Centre d`Electronique de Montpellier (France)] [Centre d`Electronique de Montpellier (France); Duzellier, S. [CERT-ONERA, Toulouse (France)] [CERT-ONERA, Toulouse (France)

1995-12-01

371

Comparative BTI Reliability Analysis of SRAM Cell Designs in Nano-Scale CMOS Technology  

E-print Network

Comparative BTI Reliability Analysis of SRAM Cell Designs in Nano-Scale CMOS Technology Shreyas. BTI affects the stability and reliability of conventional six transistor (6T) SRAM design in nano-scale CMOS technology. Eight transistor (8T) and Ten transistor (10T) SRAM cell de- signs are known

Mahmoodi, Hamid

372

Dynamic SRAM Stability Characterization in 45nm CMOS Seng Oon Toh, Zheng Guo and Borivoje Nikoli  

E-print Network

Dynamic SRAM Stability Characterization in 45nm CMOS Seng Oon Toh, Zheng Guo and Borivoje Nikoli for characterizing dynamic SRAM stability using pulsed wordlines, is demonstrated in 45nm CMOS. Static read margins margins. Introduction Static (DC) noise margins are often used to characterize SRAM because

Nikolic, Borivoje

373

A Subthreshold Single Ended I/O SRAM Cell Design for Nanometer CMOS Technologies  

E-print Network

A Subthreshold Single Ended I/O SRAM Cell Design for Nanometer CMOS Technologies Jawar Singh-transistor static random access memory (SRAM) cell (7T-LSRAM) as an alternative for nanometer CMOS technology) consumption. However, ultra-low-power design of high-density SRAMs in which the operating voltage is below

Mohanty, Saraju P.

374

X- and gamma ray imaging systems based on CdTe-CMOS detector technology  

Microsoft Academic Search

Both charge integrating and single photon identifying X- and gamma ray imaging devices constructed of CdTe pixel detectors bump bonded to CMOS ASICs have been developed, tested and utilized in a variety of applications. The charge integrating devices apply either frame mode or time delayed integration (TDI) signal readout schemes on the CMOS pixels depending on the requirements of the

Konstantinos Spartiotis; Ray Durrant; Anssi Leppanen; Henrik Lohman; Olli Mannisto; Tuomas Pantsar; Jouni Pyyhtia; Tom Schulman

2008-01-01

375

A High Dynamic Range CMOS Image Sensor with In-Pixel Light-To-Frequency Conversion  

E-print Network

A High Dynamic Range CMOS Image Sensor with In-Pixel Light-To-Frequency Conversion by Xiuling Wang-micron CMOS technology exaggerates this problem due to the decreased voltage swing, the scaling induced noise sensor that overcomes the quality degradation of the conventional APSs due to the scaled supply voltage

Hornsey, Richard

376

A New Spatiotemporal CMOS Imager With Analog Accumulation Capability for Nanosecond Low-Power Pulse Detections  

Microsoft Academic Search

High-speed cameras use the interesting performances of CMOS imagers that offer advantages in on-chip functionalities, system power reduction, cost, and miniaturization. The FAst MOS Imager (FAMOSI) project consists in reproducing the streak camera functionality with a CMOS imager. In this paper, a new imager called FAMOSI 2, which implements an electronic shutter and analog accumulation capabilities inside the pixel, is

Frdric Morel; Jean-Pierre Le Normand; Chantal-Virginie Zint; Wilfried Uhring; Yann Hu; Daniel Mathiot

2006-01-01

377

Capabilities of a new spatiotemporal CMOS imager for nanosecond low power pulse detection  

Microsoft Academic Search

High speed cameras use the interesting performances of CMOS imagers which offer advantages in on-chip functionalities, system power reduction, cost and miniaturization. The FAst MOS Imager (FAMOSI) project consists in reproducing the streak camera functionality with a CMOS imager. In this paper, we present a new imager called FAMOSI 2 which implements an electronic shutter and analog accumulation capabilities inside

Frdric Morel; Chantal-Virginie Zint; Wilfried Uhring; Jean-Pierre Le Normand

2006-01-01

378

Rapid Detection of E.Coli Bacteria using Potassium-Sensitive FETs in CMOS  

E-print Network

alternatives for ion-selective electrodes (ISE) and have been extensively used and reviewed in several papers. The chip has been tested using phages as biological detecting elements along with CMOS ion- selective FETs elements combined with ion-selective FETs (ISFET) implemented in conventional CMOS technology to accurately

Gulak, P. Glenn

379

Impact of CMOS technology scaling on the atmospheric neutron soft error rate  

Microsoft Academic Search

We investigated scaling of the atmospheric neutron soft error rate (SER) which affects reliability of CMOS circuits at ground level and airplane flight altitudes. We considered CMOS circuits manufactured in a bulk process with a lightly-doped p-type wafer. One method, based on the empirical model, predicts a linear decrease of SER per bit with decreasing feature size LG. A different

Peter Hazucha; Christer Svensson

2000-01-01

380

Impact of substrate coupling induced by 3D-IC architecture on advanced CMOS technology  

E-print Network

Impact of substrate coupling induced by 3D-IC architecture on advanced CMOS technology Maxime variations on normal operating conditions of advanced devices. Influence of design and technology parameters. In certain cases, it may be destructive for advanced CMOS technology. Dynamic variations on saturation drain

Paris-Sud XI, Université de

381

An 0.8m CMOS technology for high performance logic applications  

Microsoft Academic Search

This paper reports on the process architecture and results of an 0.8m 5V CMOS logic technology. The process, which is a factor of two faster than current 1.2m CMOS technology, features seven optically patterned levels with 0.8m geometries: isolation, gates, contacts, vias, TiN local interconnect (LI), and two metal levels.

Richard A. Chapman; Roger A. Haken; David A. Bell; C. C. Wei; R. H. Havemann; T. E. Tang; T. C. Holloway; R. J. Gale

1987-01-01

382

Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study  

E-print Network

Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study Oleg Garitselov1 , Saraju P. Mohanty2 , Elias Kougianos3 , and Priyadarsan Patra4 NanoSystem Design Laboratory (NSDL, http Abstract--Fast design space exploration of complex nano- CMOS mixed-signal circuits is an important problem

Mohanty, Saraju P.

383

A Low Power Thyristor-Based CMOS Programmable Delay Element Junmou Zhang  

E-print Network

A Low Power Thyristor-Based CMOS Programmable Delay Element Junmou Zhang , Simon R. Cooper and Development Laboratories Eastman Kodak Company Rochester, New York 14650-2008 Abstract-- A delay element element, based on a CMOS thyristor, is proposed in this paper. This thyristor uses current rather than

Friedman, Eby G.

384

Noise effects on performance of low power design schemes in deep submicron regime [CMOS digital ICs  

Microsoft Academic Search

The noise immunity of modern CMOS digital design has become an important metric, as well as its power consumption. In this paper, we evaluate the noise immunity of static CMOS low power design schemes in terms of logic and delay error. To fulfill the aims of the paper, first a model representing the different sources of noise in deep submicron

Mohamed Abbas; Makoto Ikeda; Kunihiro Asada

2004-01-01

385

Design of the Input Matching Network of RF CMOS LNAs for Low-Power Operation  

Microsoft Academic Search

Optimum design of input matching network of CMOS low-noise amplifiers (LNAs) for low-power applications is discussed in this paper. This is done through an investigation of the effect of four different matching methodologies on the gain of radio frequency CMOS LNAs by means of compact analytical expressions. It is demonstrated that methods that convert the MOSFET's input impedance to 50

Saman Asgaran; M. Jamal Deen; Chih-Hung Chen

2007-01-01

386

Low-Power 915MHz CMOS LNA Design Optimization Techniques for RFID  

Microsoft Academic Search

According to the definition of noise figure, this paper presents a detailed analysis of the noise parameter of a low noise amplified (LNA) in a CMOS cascode topology with the source degeneration inductance and gate shunt capacitance. Based on the derived equations, the important application of this topology is discussed and a low power UHF CMOS LNA is optimized for

Xiushan Wu; Ling Sun; Zhigong Wang

2007-01-01

387

A high speed camera system based on an image sensor in standard CMOS technology  

Microsoft Academic Search

In this contribution a novel camera system developed for high speed imaging will be presented. The core of the system consists of a CMOS image sensor manufactured in a 1 ?m standard CMOS process. The special merit of the image sensor is the capability to acquire more than 1000 frames\\/s using a global electronic shutter in each sensor cell. The

Nenad Stevanovic; Matthias Hillebrand; Bedrich J. Hosticka; Uri Iurgel; Andreas Teuner

1999-01-01

388

A wafer scale active pixel CMOS image sensor for generic x-ray radiology  

Microsoft Academic Search

This paper describes a CMOS Active Pixel Image Sensor developed for generic X-ray imaging systems using standard CMOS technology and an active pixel architecture featuring low noise and a high sensitivity. The image sensor has been manufactured in a standard 0.35 mum technology using 8\\

Danny Scheffer

2007-01-01

389

The optimization of zero-spaced microlenses for 2.2um pixel CMOS image sensor  

Microsoft Academic Search

In CMOS image sensor, microlens arrays are generally used as light propagation carrier onto photo diode to increase collection efficiency and reduce optical cross-talk. Today, the scaling trend of CMOS technology drives reduction of the pixel size for higher integration density and resolution improvement. Microlenses are typically formed by photo resist patterning and thermal reflowing, and the space between photo

Hyun hee Nam; Jeong Lyeol Park; Jea Sung Choi; Jeong Gun Lee

2007-01-01

390

Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits  

E-print Network

Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits Harish in the circuit. In 1 , the algorithm was demonstrated for simple gate delay and current models. In this paper, we Abstract Excessive voltage drops in power and ground P&G buses of CMOS VLSI circuits can severely degrade

Najm, Farid N.

391

Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits  

E-print Network

Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits Harish in the circuit. In [1], the algorithm was demonstrated for simple gate delay and current models. In this paper Abstract Excessive voltage drops in power and ground (P&G) buses of CMOS VLSI circuits can severely degrade

Najm, Farid N.

392

CMOS-compatible Titanium Dioxide Deposition for Athermalization of Silicon Photonic Waveguides  

E-print Network

CMOS-compatible Titanium Dioxide Deposition for Athermalization of Silicon Photonic Waveguides@ucdavis.edu , sbyoo@ucdavis.edu Abstract: We discuss titanium dioxide material development for CMOS compatible fabrication and integration of athermal silicon photonic components. Titanium dioxide overclad ring modulators

Yoo, S. J. Ben

393

CMOS digital intra-oral sensor for x-ray radiography  

NASA Astrophysics Data System (ADS)

In this paper, we present a CMOS digital intra-oral sensor for x-ray radiography. The sensor system consists of a custom CMOS imager, custom scintillator/fiber optics plate, camera timing and digital control electronics, and direct USB communication. The CMOS imager contains 1700 x 1346 pixels. The pixel size is 19.5um x 19.5um. The imager was fabricated with a 0.18um CMOS imaging process. The sensor and CMOS imager design features chamfered corners for patient comfort. All camera functions were integrated within the sensor housing and a standard USB cable was used to directly connect the intra-oral sensor to the host computer. The sensor demonstrated wide dynamic range from 5uGy to 1300uGy and high image quality with a SNR of greater than 160 at 400uGy dose. The sensor has a spatial resolution more than 20 lp/mm.

Liu, Xinqiao; Byczko, Andrew; Choi, Marcus; Chung, Lap; Do, Hung; Fowler, Boyd; Ispasoiu, Radu; Joshi, Kumar; Miller, Todd; Nagy, Alex; Reaves, David; Rodricks, Brian; Teeter, Doug; Wang, George; Xiao, Feng

2011-03-01

394

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager  

PubMed Central

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132124 high sensitivity imager array with a 20.1 ?m pixel pitch fabricated in a standard 0.5 ? CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 ?A from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 ?W/cm2. Implementing 44 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2012-01-01

395

Single ion channel recordings with CMOS-anchored lipid membranes.  

PubMed

We present single-ion-channel recordings performed with biomimetic lipid membranes which are directly attached to the surface of a complementary metal-oxide-semiconductor (CMOS) preamplifier chip. With this system we resolve single-channel currents from several types of bacterial ion channels, including fluctuations of a single alamethicin channel at a bandwidth of 1 MHz which represent the fastest single-ion-channel recordings reported to date. The platform is also used for high-resolution ?-hemolysin nanopore recordings. These results illustrate the high signal fidelity, fine temporal resolution, small geometry, and multiplexed integration which can be achieved by leveraging integrated semiconductor platforms for advanced ion channel interfaces. PMID:23634707

Rosenstein, Jacob K; Ramakrishnan, Siddharth; Roseman, Jared; Shepard, Kenneth L

2013-06-12

396

Laser SEU sensitivity mapping of deep submicron CMOS SRAM  

NASA Astrophysics Data System (ADS)

The pulsed laser facility for SEU sensitivity mapping is utilized to study the SEU sensitive regions of a 0.18 ?m CMOS SRAM cell. Combined with the device layout micrograph, SEU sensitivity maps of the SRAM cell are obtained. TCAD simulation work is performed to examine the SEU sensitivity characteristics of the SRAM cell. The laser mapping experiment results are discussed and compared with the electron micrograph information of the SRAM cell and the TCAD simulation results. The results present that the test technique is reliable and of high mapping precision for the deep submicron technology device.

Yongtao, Yu; Guoqiang, Feng; Rui, Chen; Jianwei, Han

2014-06-01

397

A CMOS clock and data recovery circuit for intraocular microsystems.  

PubMed

This paper presents the implementation of a clock and data recovery circuit (CDR) for intraocular microsystems. The CDR was designed to minimize chip area and power consumption and to recover the clock and data signals from the incoming data stream. Since the CDR has been designed without any external components it is well suited for being integrated in an intraocular microsystem. Simulation results show that this CDR works with power dissipation of less than 2.4 mW with a single 3.3 V power supply. The simulations are based on a 0.6 micron n-well CMOS single-polysilicon, three-metal technology. PMID:12451805

Prmassing, F; Pttjer, D; Buss, R; Jger, D

2002-01-01

398

Predicting Lifetimes Of CMOS ASIC's From Test Data  

NASA Technical Reports Server (NTRS)

Concise report discusses recent developments in use of semiempirical mathematical models to predict rates of failure and operating lifetimes of complementary metal oxide/semiconductor (CMOS) application-specific integrated circuits (ASIC's). Each model represents specific mechanism of failure. Once failure mechanisms and models relevant to given ASIC chosen, adjustable parameters in models fitted to life-test data acquired from representative integrated-circuit structures on test coupons fabricated along with ASIC's. Then design parameters of ASIC's incorporated into models, and models yield lifetimes.

Buehler, Martin G.; Zamani, Nasser; Zoutendyk, John A.

1993-01-01

399

High Speed, Radiation Hard CMOS Pixel Sensors for Transmission Electron Microscopy  

NASA Astrophysics Data System (ADS)

CMOS monolithic active pixel sensors are currently being established as the technology of choice for new generation digital imaging systems in Transmission Electron Microscopy (TEM). A careful sensor design that couples ?m-level pixel pitches with high frame rate readout and radiation hardness to very high electron doses enables the fabrication of direct electron detectors that are quickly revolutionizing high-resolution TEM imaging in material science and molecular biology. This paper will review the principal characteristics of this novel technology and its advantages over conventional, optically-coupled cameras, and retrace the sensor development driven by the Transmission Electron Aberration corrected Microscope (TEAM) project at the LBNL National Center for Electron Microscopy (NCEM), illustrating in particular the imaging capabilities enabled by single electron detection at high frame rate. Further, the presentation will report on the translation of the TEAM technology to a finer feature size process, resulting in a sensor with higher spatial resolution and superior radiation tolerance currently serving as the baseline for a commercial camera system.

Contarato, Devis; Denes, Peter; Doering, Dionisio; Joseph, John; Krieger, Brad

400

Design considerations for a new high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS)  

NASA Astrophysics Data System (ADS)

The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 ?m pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

Loughran, Brendan; Swetadri Vasan, S. N.; Singh, Vivek; Ionita, Ciprian N.; Jain, Amit; Bednarek, Daniel R.; Titus, Albert H.; Rudin, Stephen

2013-03-01

401

PIN photodiode bandwidth optimization in integrated CMOS process  

NASA Astrophysics Data System (ADS)

Silicon photodiode integrated with CMOS has been in extensive study for the past ten years due to its wide use in applications such as short-distance communication, VCD players, ambient light sensors and many other intelligent systems. In recent years, high speed blue-ray DVD is replacing conventional DVD due to its larger storage capacity and higher speed. In this work, the photodiode optimized for blue ray is fully integrated with standard 0.35um CMOS process and the bandwidth dependency upon thermal process and epitaxial material is investigated. It was found that the additional substrate thermal process can improve bandwidth for blue and red light but reduce bandwidth for infra-red. It is also found that higher level p-type epi doping does not impact bandwidth for blue light but reduces bandwidth for red and infra-red. The various mechanisms of bandwidth were discussed based on the experimental results. It indicated that the bandwidth of photodiodes depends on photo carriers travel time which can be explained by simple model of drift transport and diffusion transport. The design of photodiode should optimize the depletion region and reduce the carrier travel time.

Fang, Fred; Franke, Matthias; Gaebler, Daniel; Sang Sool, Koo

2011-05-01

402

An integrated CMOS high data rate transceiver for video applications  

NASA Astrophysics Data System (ADS)

This paper presents a 5 GHz CMOS radio frequency (RF) transceiver built with 0.18 ?m RF-CMOS technology by using a proprietary protocol, which combines the new IEEE 802.11n features such as multiple-in multiple-out (MIMO) technology with other wireless technologies to provide high data rate robust real-time high definition television (HDTV) distribution within a home environment. The RF frequencies cover from 4.9 to 5.9 GHz: the industrial, scientific and medical (ISM) band. Each RF channel bandwidth is 20 MHz. The transceiver utilizes a direct up transmitter and low-IF receiver architecture. A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration. The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude (EVM) at -3 dBm output power.

Yaping, Liang; Dazhi, Che; Cheng, Liang; Lingling, Sun

2012-07-01

403

Fabrication of a CMOS compatible nanopore detector for DNA  

NASA Astrophysics Data System (ADS)

Nanopore based DNA sequencers require integration of miniaturized electrodes and amplifier electronics in close proximity to the nanopores in a CMOS platform. This will facilitate portability, enable faster analysis, and improve sensing performance. Here we report for the first time the fabrication of a DNA nanopore detector compatible with a standard CMOS process. Our nanopore devices are made using an N+ polysilicon/gate oxide/N+ polysilicon stack on an oxidized silicon substrate identical to the AMI 0.5? process. The nanopores are created in the gate oxide membrane (36 nm) while doped polysilicon layers (250 and 370 nm) act as electrodes to apply bias across pores. Five lithography masks are used to pattern the oxide membrane and the electrodes. The nanopores are defined by etching the membrane using electron beam lithography patterned holes in a resist mask. Using this method we have directly fabricated pores with diameters as small as 11 nm, without applying conventional pore shrinkage techniques. This is enhanced by cold development of the e-beam exposed resist resulting in sub-10 nm pores. DNA experiments are currently underway utilizing our nanopores.

Uddin, Ashfaque; Milaninia, Kaveh; Elibol, Oguz; Daniels, Jonathan; Su, Xing; Varma, Madoo; Stein, Derek; Theogarajan, Luke

2010-03-01

404

Post-irradiation effects in CMOS integrated circuits  

SciTech Connect

The post-irradiation response of CMOS integrated circuits from three vendors has been measured as a function of temperature and irradiation bias. The author's have found that a worst-case anneal temperature for rebound testing is highly process dependent. At an anneal temperature of 80/sup 0/C, the timing parameters of a 16K SRAM from vendor A quickly saturate at maximum values, and display no further changes at this temperature. At higher temperature, evidence for the anneal of interface state charge is observed. Dynamic bias during irradiation results in the same saturation value for the timing parameters, but the anneal time required to reach this value is longer. CMOS/SOS integrated circuits (vendor B) were also examined, and showed similar behavior, except that the saturation value for the timing parameters was stable up to 105/sup 0/C. After irradiation to 10 Mrad(Si), a 16K SRAM (vendor C) was annealed at 80/sup 0/C. In contrast to the results from the vendor A SRAM, the access time decreased toward prerad values during the anneal. Another part irradiated in the same manner but annealed at room temperature showed a slight increase during the anneal.

Zietlow, T.C.; Barnes, C.E.; Morse, T.C.; Grusynski, J.S.; Nakamura, K.; Amram, A.; Wilson, K.T.

1988-12-01

405

CMOS: Efficient Clustered Data Monitoring in Sensor Networks  

PubMed Central

Tiny and smart sensors enable applications that access a network of hundreds or thousands of sensors. Thus, recently, many researchers have paid attention to wireless sensor networks (WSNs). The limitation of energy is critical since most sensors are battery-powered and it is very difficult to replace batteries in cases that sensor networks are utilized outdoors. Data transmission between sensor nodes needs more energy than computation in a sensor node. In order to reduce the energy consumption of sensors, we present an approximate data gathering technique, called CMOS, based on the Kalman filter. The goal of CMOS is to efficiently obtain the sensor readings within a certain error bound. In our approach, spatially close sensors are grouped as a cluster. Since a cluster header generates approximate readings of member nodes, a user query can be answered efficiently using the cluster headers. In addition, we suggest an energy efficient clustering method to distribute the energy consumption of cluster headers. Our simulation results with synthetic data demonstrate the efficiency and accuracy of our proposed technique. PMID:24459444

2013-01-01

406

CMOS-compatible active thermopiles for noise-added theory  

NASA Astrophysics Data System (ADS)

Recently a novel signal processing theory related with noise has grown and proven. Certain complex systems can improve performance with added optimal noise that classical theory cannot explain. Their behavior may be represented by a simplified scheme that combines both a deterministic and stochastic source. To that end, we are using noise in remote temperature sensing system to enhance their function without altering the system. A new investigation of noise added scheme has been realized by an embedded heater for CMOS compatible thermoelectric infrared sensor. The design and fabrication of thermopile sensors are realized by using 1.2?m CMOS IC technology combined with a subsequent anisotropic front-side etching. We firstly develop an active thermopile with a heater embedded which is easily and naturally driven by a noise generation circuit. The stochastic resonance theory can be realized as a reduction in threshold of temperature detection. We have shown the possibility of improving the performance of remote temperature sensing system in the presence of noise. The strategy depends on the application. Stochastic resonance can reduce threshold detection resolution and greatly improve the temperature detection limit with a low cost scheme without using higher resolution ADC.

Shen, Chih-Hsiung; Hou, Kuan-Chou

2004-05-01

407

Review of radiation damage studies on DNW CMOS MAPS  

NASA Astrophysics Data System (ADS)

Monolithic active pixel sensors fabricated in a bulk CMOS technology with no epitaxial layer and standard resistivity (10 ? cm) substrate, featuring a deep N-well as the collecting electrode (DNW MAPS), have been exposed to ?-rays, up to a final dose of 10 Mrad (SiO2), and to neutrons from a nuclear reactor, up to a total 1 MeV neutron equivalent fluence of about 3.71013 cm-2. The irradiation campaign was aimed at studying the effects of radiation on the most significant parameters of the front-end electronics and on the charge collection properties of the sensors. Device characterization has been carried out before and after irradiations. The DNW MAPS irradiated with 60Co ?-rays were also subjected to high temperature annealing (100 C for 168 h). Measurements have been performed through a number of different techniques, including electrical characterization of the front-end electronics and of DNW diodes, laser stimulation of the sensors and tests with 55Fe and 90Sr radioactive sources. This paper reviews the measurement results, their relation with the damage mechanisms underlying performance degradation and provides a new comparison between DNW devices and MAPS fabricated in a CMOS process with high resistivity (1 k? cm) epitaxial layer.

Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.; Zucca, S.; Bettarini, S.; Rizzo, G.; Morsani, F.; Bosisio, L.; Rashevskaya, I.; Cindro, V.

2013-12-01

408

Electronic-photonic integrated circuits on the CMOS platform  

NASA Astrophysics Data System (ADS)

The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application-specific, electronicphotonic integrated circuit (AS-EPIC). As part of the development of this demonstration platform we are exploring selected functions normally associated with the front end of mixed signal receivers such as modulation, detection, and filtering. The chip will be fabricated in the BAE Systems CMOS foundry and at MIT's Microphotonics Center. We will present the latest results on the performance of multi-layer deposited High Index Contrast Waveguides, CMOS compatible modulators and detectors, and optical filter slices. These advances will be discussed in the context of the Communications Technology Roadmap that was recently released by the MIT Microphotonics Center Industry Consortium.

Kimerling, L. C.; Ahn, D.; Apsel, A. B.; Beals, M.; Carothers, D.; Chen, Y.-K.; Conway, T.; Gill, D. M.; Grove, M.; Hong, C.-Y.; Lipson, M.; Liu, J.; Michel, J.; Pan, D.; Patel, S. S.; Pomerene, A. T.; Rasras, M.; Sparacin, D. K.; Tu, K.-Y.; White, A. E.; Wong, C. W.

2006-02-01

409

High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.  

PubMed

A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. PMID:20728336

Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

2010-12-15

410

Algorithmic Design of CMOS LNAs and PAs for 60GHz Radio  

Microsoft Academic Search

Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor fT\\/fMAX of 120 GHz\\/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB

Terry Yao; Michael Q. Gordon; Keith K. W. Tang; Kenneth H. K. Yau; Ming-Ta Yang; Peter Schvan; Sorin P. Voinigescu

2007-01-01

411

Commercial Fisheries Biological Laboratory  

E-print Network

Bureau of Commercial Fisheries Biological Laboratory Galveston, Texas Penaeid Shrimp Life Cvcle ^.y Bureau of Commercial Fisheries Circular 307 #12;The Bureau of Commercial Fisheries Biological Laboratory at commercially important species of shrimp in the Gulf of Mexico through four research programs: (1) Shrimp

412

Hafnium oxide and hafnium aluminum oxide for CMOS applications  

NASA Astrophysics Data System (ADS)

The continued scaling of the CMOS gate dielectric to its fundamental limit governed by the large gate leakage current requires the introduction of high-k material for sub-100-nm technology nodes. This dissertation research deals with the physical and electrical properties of a promising high-k candidate, hafnium oxide, as a gate dielectric for CMOS applications. Hafnium oxide made by the Jet-Vapor-Deposition process shows very promising properties in terms of surface roughness, dielectric constant, and energy bandgap, but there are also severe challenges, such as low crystallization temperature, high charge trapping probability, and low channel mobility, which have been studied in detail in this thesis. We have found that the crystallization of HfO2 could result in a significant increase of the leakage current. This problem has been solved by adding Al in the HfO2 film. The impacts of Al inclusion in HfO 2 film on crystallization temperature, bandgap energy, and dielectric constant have been investigated. Considering the trade-off among the crystallization temperature, bandgap energy, and dielectric constant, we have concluded that the optimum concentration is about 30% Al for conventional self-aligned CMOS gate processing technology. The charge trapping properties of ultra-thin HfO2 in metal-oxide-silicon capacitors during constant voltage stress have also been investigated. The effects of stress voltage, substrate type, annealing temperature, and gate electrode have been studied in detail, and reported in this dissertation. Accurate measurements and degradation mechanisms of the channel mobility for MOSFETs with HfO2 as the gate dielectric have been systemetically studied. The error in mobility extraction caused by a high density of interface traps for a MOSFET with high-k gate dielectric has been analyzed, and a new method to correct this error has been proposed. Other sources of error in mobility extraction, including gate leakage current, channel resistance, and contact resistance for a MOSFET with ultra-thin high-k dielectric have also been investigated and reported in this thesis. Based on the accurately measured channel mobility, we have analyzed the degradation mechanisms of channel mobility for a MOSFET with HfO2 as the gate dielectric. The mobility degradation due to Coulomb scatting arising from interface trapped charges, and that due to remote soft optical phonon scattering are discussed.

Zhu, Wenjuan

413

High-performance VGA-resolution digital color CMOS imager  

NASA Astrophysics Data System (ADS)

This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be suitable for a variety of color imaging applications including still/full motion imaging, security/surveillance, and teleconferencing/multimedia among other high performance, cost sensitive, low power consumer applications.

Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

1999-04-01

414

Single Ion Channel Recordings with CMOS-Anchored Lipid Membranes  

PubMed Central

We present single-ion-channel recordings performed with biomimetic lipid membranes which are directly attached to the surface of a complementary metal-oxide-semiconductor (CMOS) preamplifier chip. With this system we resolve single-channel currents from several types of bacterial ion channels, including fluctuations of a single alamethicin channel at a bandwidth of 1 MHz which represent the fastest single-ion-channel recordings reported to date. The platform is also used for high-resolution alpha-hemolysin nanopore recordings. These results illustrate the high signal fidelity, fine temporal resolution, small geometry, and multiplexed integration which can be achieved by leveraging integrated semiconductor platforms for advanced ion channel interfaces. PMID:23634707

Rosenstein, Jacob K.; Ramakrishnan, Siddharth; Roseman, Jared; Shepard, Kenneth L.

2013-01-01

415

A 20 MHz CMOS reorder buffer for a superscalar microprocessor  

NASA Technical Reports Server (NTRS)

Superscalar processors can achieve increased performance by issuing instructions out-of-order from the original sequential instruction stream. Implementing an out-of-order instruction issue policy requires a hardware mechanism to prevent incorrectly executed instructions from updating register values. A reorder buffer can be used to allow a superscalar processor to issue instructions out-of-order and maintain program correctness. This paper describes the design and implementation of a 20MHz CMOS reorder buffer for superscalar processors. The reorder buffer is designed to accept and retire two instructions per cycle. A full-custom layout in 1.2 micron has been implemented, measuring 1.1058 mm by 1.3542 mm.

Lenell, John; Wallace, Steve; Bagherzadeh, Nader

1992-01-01

416

Heavy ion microscopy of single event upsets in CMOS SRAMs  

SciTech Connect

The single event upset (SEU) imaging has been applied at the GSI heavy ion microprobe to determine the sensitivity of integrated circuits (IC) to heavy ion irradiation. This method offers the possibility to directly image those parts of an IC which are sensitive to ion-induced malfunctions. By a 3-dimensional simulation of charge collection across p-n-micro-junctions the authors can predict SEU cross-sections. For a MHS65162 2k [times] 8bit CMOS SRAM they found two regions per bit with different sensitivity and measured a total cross-section of (71[+-]18)[mu]m[sup 2] for a bitflip per cell and simulated 60[mu]m[sup 2] with an argon beam of 1.4 MeV/nucl. (LET of 19.7 MeV/mg/cm[sup 2]).

Metzger, S.; Dreute, J.; Heinrich, W.; Roecher, H. (Univ.-GH-Siegen (Germany)); Fischer, B.E. (Gesellschaft fuer Schwerionenforschung mbH, Darmstadt (Germany)); Harboe-Soerensen, R.; Adams, L. (ESA-ESTEC, Noordwijk (Netherlands))

1994-06-01

417

Failure analysis of a half-micron CMOS IC technology  

SciTech Connect

We present the results of recent failure analysis of an advanced, 0.5 {mu}m, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.

Liang, A.Y.; Tangyunyong, P.; Bennett, R.S.; Flores, R.S. [and others

1996-08-01

418

Single event upset in irradiated 16k CMOS SRAMs  

SciTech Connect

The Single Event Upset (SEU) characteristics of a CMOS SRAM cell irradiated under conditions that simulate the total-dose degradation anticipated in space applications are experimentally and theoretically investigated. Simulations of SEU sensitivity utilizing a 2D circuit/device simulator, with measured transistor threshold-voltage shifts and mobility degradations as inputs, are shown to be in good agreement with experimental data at high total dose. Both simulation and experiment show a strong SRAM cell SEU imbalance, resulting in a more SEU tolerant preferred state and a less tolerant non-preferred state. The resulting cell imbalance causes an overall degradation in SEU immunity which increases with increasing total dose and which should be taken into account in SEU testing and part characterization.

Axness, C.L.; Schwank, J.R.; Winokur, P.S.; Browning, J.S.; Fleetwood, D.M.; Koga, R.

1988-12-01

419

Two CMOS gate arrays for the EPACT experiment  

SciTech Connect

Two semicustom CMOS digital gate arrays are described in this paper which have been developed for the Energetic Particles: Acceleration, Composition, and Transport (EPACT) experiment. The first device, the 'Event Counters: 16 by 24-bit' (EC1624), implements sixteen 24-bit ripple counters and has flexible counting and readout options. The second device, the 'Serial Transmitter/Receiver' (SXR), is a multi-personality chip that can be used at either end of a serial, synchronous communications data link. It can be configured as a master in a central control unit, or as one of many slaves within remote assemblies. Together a network of SXRs allows for commanding and verification of distributed control signals. Both gate arrays are radiation hardened and qualified for space flight use. The architecture of each chip is presented and the benefits to the experiment summarized.

Winkert, G. (National Aeronautics and Space Administration, Greenbelt, MD (United States). Goddard Space Flight Center)

1992-08-01

420

A radiation hardened SONOS/CMOS EEPROM family  

SciTech Connect

There has long been a need for fast read nonvolatile, rad hard memories for military and space applications. Recent advances in EEPROM technology now allow this need to be met for many applications. Harris/Sandia have developed a 16k and a 256k rad hard EEPROM. The EEPROMs utilize a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory transistor integrated into a 2 {mu}m, rad hard two level metal CMOS process. Both the 16k and the 256k parts have been designed to interface with the Intel 8085 or 80C51 and National 32000 series microprocessors and feature page and block clear modes. Both parts are functionally identical, and are produced by the same fabrication process. They are also pin for pin compatible with each other, except for the extra address and ground pins on the 256k. This paper describes the characteristics of this EEPROM family. 1 ref.

Klein, V.F.; Wood, G.M.; Buller, J.F. (Harris Corp., Melbourne, FL (USA). Semiconductor Sector); Murray, J.R.; Rodriquez, J.L. (Sandia National Labs., Albuquerque, NM (USA))

1990-01-01

421

CMOS detector cells for holographic optical interconnects in microcircuits  

NASA Technical Reports Server (NTRS)

This paper reports on the characterization of CMOS detectors for holographic optical interconnects in micro circuits. A VLSI temporal response system has been built, which has high-magnification viewing capabilities to facilitate the identification of the sample area under investigation. An isolated photodiode and load circuit has been characterized to determine responsivity, response time, and light spot positioning effects. The threshold of optical gate cells incorporating the above detectors and a transistor inverter stage to couple to other circuitry has been determined. The rise time and fall time of the optical gate cells have also been determined experimentally. The results were compared with the results of SPICE simulation, and show satisfactory agreement. The time delay of optical gate cell output was thus determined to be 70 ns at 10 microW light input. Threshold power was 0.5 microW light input.

Wu, W. H.; Johnston, A. R.

1987-01-01

422

Characteristic of e2v CMOS sensors for astronomical applications  

NASA Astrophysics Data System (ADS)

We report the testing result of e2v CIS 107 CMOS sensor for temperature from 300K to 170K. The CIS 107 sensor is a prototype device with 10 different variations of pixel designs. The sensor has 1500 2000, 7 ?m pixels with 4 outputs. Each variation covers 1500 200 pixels. These are 4T pixels with high resistivity epitaxial silicon and back thinned to 11?m. At room temperature, the several variants of pixels show peak QE higher than 90%, readout noise around 5e- and dark current around 50e-/s/pix. The full well is about 15000 e- due to the limitation of the transfer gate capacitor. The CIS 107 device was further characterized at different device temperatures from 170K to 300K. The readout noise decreases and the full well increases as the device is operated at lower temperature.

Wang, Shiang-Yu; Ling, Hung-Hsu; Hu, Yen-Shan; Geary, John C.; Amato, Stephen M.; Pratlong, Jerome; Pike, Andrew; Jordan, Paul; Lehner, Matthew J.

2014-07-01

423

Characterization of a megapixel CMOS charge dump and read camera  

NASA Astrophysics Data System (ADS)

The National Ignition Facility requires a radiation-hardened, megapixel CMOS imaging sensor-based camera to be a direct physical and operational replacement for the CCD cameras currently used in x-ray streak cameras and gated imaging detectors. Camera electronics were selected to operate up to 10 krad(Si). The camera incorporates a fast dump of the sensor followed by exposure and image readout. This allows the dumping of charge due to the prompt radiation background and then readout of the longer persistence phosphor image from the x-ray diagnostics. Internal timing delays and optical performance were measured for a radiation-tolerant camera, based on the 2k by 2k CMV4000 sensor from CMOSIS Inc.

Kimbrough, Joseph R.; Bell, P. M.; Datte, P. S.; Thao, M. S.; Vergel de Dios, E. O.; Peters, A. S.

2013-09-01

424

Enabling Solutions for 28 nm CMOS Advanced Junction Formation  

NASA Astrophysics Data System (ADS)

Controlling short channel effects for further scaled CMOS is required to take full advantage of the introduction of high K/metal gate or stress induced carrier mobility enhancement. Ultra-Shallow junction formation is necessary to minimize the short channel effects. In this paper, we will discuss the challenges for 28 nm Ultra-Shallow Junction formations in terms of figure of merits of Rs/Xj and junction leakage. We will demonstrate that by adopting and integrating Carborane (CBH, C2B10H12) molecular implant and Phosphorus along with co-implantation and PTC II (VSEA Process Temperature Control) technology, sub-32 nm pLDD and nLDD junction targets can be timely achieved using traditional anneals. Those damage engineering solutions can be readily implemented on state-of-the-art 28 nm device manufacturing.

Li, C. I.; Kuo, P.; Lai, H. H.; Ma, K.; Liu, R.; Wu, H. H.; Chan, M.; Yang, C. L.; Wu, J. Y.; Guo, B. N.; Colombeau, B.; Thirumal, T.; Arevalo, E.; Toh, T.; Shim, K. H.; Sun, H. L.; Wu, T.; Lu, S.

2011-01-01

425

Development of a radiation-hard CMOS process  

NASA Technical Reports Server (NTRS)

It is recommended that various techniques be investigated which appear to have the potential for improving the radiation hardness of CMOS devices for prolonged space flight mission. The three key recommended processing techniques are: (1) making the gate oxide thin. It has been shown that radiation degradation is proportional to the cube of oxide thickness so that a relatively small reduction in thickness can greatly improve radiation resistance; (2) cleanliness and contamination control; and (3) to investigate different oxide growth (low temperature dry, TCE and HCL). All three produce high quality clean oxides, which are more radiation tolerant. Technique 2 addresses the reduction of metallic contamination. Technique 3 will produce a higher quality oxide by using slow growth rate conditions, and will minimize the effects of any residual sodium contamination through the introduction of hydrogen and chlorine into the oxide during growth.

Power, W. L.

1983-01-01

426

Improving TCSPC data acquisition from CMOS SPAD arrays  

NASA Astrophysics Data System (ADS)

We present a digital architecture for fast acquisition of time correlated single photon counting (TCSPC) timestamps from 3232 CMOS SPAD array. Custom firmware was written to select 64 pixels out of 1024 available for fast transfer of TCSPC timestamps. Our 64 channel TCSPC is capable of acquiring up to 10 million TCSPC timestamps per second over a USB2 link. We describe the TCSPC camera (Megaframe), camera interface to the PC and the microscope setup. We characterize the Megaframe camera for fluorescence lifetime imaging (FLIM) including instrument response function, time resolution and variability of both across the array. We show a fluorescence lifetime image of a plant specimen (Convallaria majalis) from a custom-built multifocal multiphoton microscope. The image was acquired in 20 seconds (with average timestamp acquisition rate of 4.7 million counts per second).

Krstaji?, Nikola; Poland, Simon; Tyndall, David; Walker, Richard; Coelho, Simao; Li, David D.; Richardson, Justin; Ameer-Beg, Simon; Henderson, Robert

2013-06-01

427

Monolithic electronic-photonic integration in state-of-the-art CMOS processes  

E-print Network

As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. ...

Orcutt, Jason S. (Jason Scott)

2012-01-01

428

Substrate engineering for monolithic integration of III-V semiconductors with Si CMOS technology  

E-print Network

Ge virtual substrates, fabricated using Si1-xGex-.Ge, compositionally graded buffers, enable the epitaxial growth of device-quality GaAs on Si substrates, but monolithic integration of III-V semiconductors with Si CMOS ...

Dohrman, Carl Lawrence

2008-01-01

429

Platform for monolithic integration of III-V devices with Si CMOS technology  

E-print Network

Monolithic integration of III-V compound semiconductors and Si complementary metal-oxide- semiconductor (CMOS) enables the creation of advanced circuits with new functionalities. In order to merge the two technologies, ...

Pacella, Nan Yang

2012-01-01

430

Analytical model for RF power performance of deeply scaled CMOS devices  

E-print Network

This paper presents a first order model for RF power of deeply scaled CMOS. The model highlights the role of device on-resistance in determining the maximum RF power. We show excellent agreement between the model and the ...

Gogineni, Usha

431

Radiation Performance of 1 Gbit DDR SDRAMs Fabricated in the 90 nm CMOS Technology Node  

NASA Technical Reports Server (NTRS)

We present Single Event Effect (SEE) and Total Ionizing Dose (TID) data for 1 Gbit DDR SDRAMs (90 nm CMOS technology) as well as comparing this data with earlier technology nodes from the same manufacturer.

Ladbury, Raymond L.; Gorelick, Jerry L.; Berg, M. D.; Kim, H.; LaBel, K.; Friendlich, M.; Koga, R.; George, J.; Crain, S.; Yu, P.; Reed, R. A.

2006-01-01

432

Post assembly process development for Monolithic OptoPill integration on silicon CMOS  

E-print Network

Monolithic OptoPill integration by means of recess mounting is a heterogeneous technique employed to integrate III-V photonic devices on silicon CMOS circuits. The goal is to create an effective fabrication process that ...

Lei, Yi-Shu Vivian, 1979-

2004-01-01

433

An integrating CMOS APS for X-ray imaging with an in-pixel preamplifier  

NASA Astrophysics Data System (ADS)

We present in this paper an integrating CMOS Active Pixel Sensor (APS) circuit coated with scintillator type sensors for intra-oral dental X-ray imaging systems. The photosensing element in the pixel is formed by the p-diffusion on the n-well diode. The advantage of this photosensor is its very low direct absorption of X-rays compared to the other available photosensing elements in the CMOS pixel. The pixel features an integrating capacitor in the feedback loop of a preamplifier of a finite gain in order to increase the optical sensitivity. To verify the effectiveness of this in-pixel preamplification, a prototype 3280 element CMOS active pixel array was implemented in a 0.8 ?m CMOS double poly, n-well process with a pixel pitch of 50 ?m. Measured results confirmed the improved optical sensitivity performance of the APS. Various measurements on device performance are presented.

Abdalla, M. A.; Frjdh, C.; Petersson, C. S.

2001-06-01

434

Design of clock recovery circuits for optical clocking in DSM CMOS  

NASA Astrophysics Data System (ADS)

CMOS technology scaling especially in the sub-100 nm regime has made signaling in long global a challenge, resulting in a need for an improved interconnect technology. Optical signalling is a promising alternative to existing global interconnects and alleviates interconnect bottle-neck. This paper presents a design of a CMOS trans-impedance amplifier (TIA) that is intended for a truly CMOS compatible on-chip optical clock distribution system. This TIA employs replica biasing technique to achieve stability while maximizing its bandwidth and gain. The design was implemented in a 0.35?m CMOS process and is currently under probe testing. The simulation results show that the design achieved a bandwidth of 1GHz and gain of 128dB-?. Extensive Monte-Carlo simulations indicate the superior characteristics of stability under a variety of process and environmental variations.

Thangaraj, Charles; Stephenson, Kevin; Chen, Tom; Lear, Kevin; Raza, Abdul Matheen

2007-05-01

435

Development of monolithic CMOS-compatible visible light emitting diode arrays on silicon  

E-print Network

The synergies associated with integrating Si-based CMOS ICs and III-V-material-based light-emitting devices are very exciting and such integration has been an active area of research and development for quite some time ...

Chilukuri, Kamesh

2006-01-01

436

Time-based circuits for communication systems in advanced CMOS technology  

E-print Network

As device size scales down, there have been challenges to design conventional analog circuits, such as low voltage headroom and the low intrinsic gain of a device. Although ever-decreasing device channel length in CMOS ...

Park, Min, Ph. D. Massachusetts Institute of Technology

2009-01-01

437

Nano-scale metal contacts for future III-V CMOS  

E-print Network

As modem transistors continue to scale down in size, conventional Si CMOS is reaching its physical limits and alternative technologies are needed to extend Moore's law. Among different candidates, MOSFETs with a III-V ...

Guo, Alex

2012-01-01

438

A Cryogenic CMOS-based Control System for Testing Superconductor Electronics.  

E-print Network

??A Cryogenic CMOS-based Control System for Testing Superconductor Electronics P.C. van Niekerk Department of Electrical and Electronic Engineering University of Stellenbosch Private Bag X1, 7602 (more)

Van Niekerk, Philip Charl

2008-01-01

439

Pixel-parallel CMOS active pixel sensor for fast object location Ryan Burns1  

E-print Network

Pixel-parallel CMOS active pixel sensor for fast object location Ryan Burns1 , Christopher Thomas2 , Paul Thomas3 , Richard Hornsey2 1. Electrical & Computer Engineering, University of Waterloo, Canada 2

Hornsey, Richard

440

Current mode integrators and their applications in low-voltage high frequency CMOS signal processing  

E-print Network

Low voltage CMOS fully differential integrators for high frequency continuous-time filters using current-mode techniques are presented.. Current mode techniques are employed to avoid the use of the floating differential pair, in order to achieve...

Smith, Sterling Lane

2012-06-07

441

Design of CMOS integrated frequency synthesizers for ultra-wideband wireless communications systems  

E-print Network

Ultrawide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used...

Tong, Haitao

2009-05-15

442

CMOS Integrated Circuit Design for Ultra-Wideband Transmitters and Receivers  

E-print Network

makes the CMOS circuit capable of handling signal at multi-giga herz. However, some design challenges still remain to be solved. Unlike regular narrow band signal, the UWB signal is discrete pulse instead of continuous wave (CW), which results...

Xu, Rui

2010-10-12

443

Anodic Ta 2O 5 for CMOS compatible low voltage electrowetting-on-dielectric device fabrication  

NASA Astrophysics Data System (ADS)

This paper reports a CMOS compatible fabrication procedure that enables electrowetting-on-dielectric (EWOD) technology to be post-processed on foundry CMOS technology. With driving voltages less than 15 V it is believed to be the lowest reported driving voltage for any material system compatible with post-processing on completed integrated circuits wafers. The process architecture uses anodically grown tantalum pentoxide as a pinhole free high dielectric constant insulator with an overlying 16 nm layer of Teflon-AF , which provides the hydrophobic surface for droplets manipulation. This stack provides a very robust dielectric, which maintains a sufficiently high capacitance per unit area for effective operation at a reduced voltage (15 V) which is more compatible with standard CMOS technology. The paper demonstrates that the sputtered tantalum layer used for the electrodes and the formation of the insulating dielectric can readily be integrated with both aluminium and copper interconnect used in foundry CMOS.

Li, Y.; Parkes, W.; Haworth, L. I.; Stokes, A. A.; Muir, K. R.; Li, P.; Collin, A. J.; Hutcheon, N. G.; Henderson, R.; Rae, B.; Walton, A. J.

2008-09-01

444

256 x 256 CMOS active pixel image sensor  

NASA Astrophysics Data System (ADS)

A 256 X 256 CMOS photo-gate active pixel image sensor is presented. The image sensor uses four MOS transistors within each pixel to buffer the photo-signal, enhance sensitivity, and suppress noise. The pixel size is 20 micrometers X 20 micrometers and was implemented in a standard digital 0.9 micrometers single-polysilicon, double-metal, n-well CMOS process; leading to 25% fill-factor. Row and column decoders and counters are monolithically integrated as well as per column analog signal correlated double-sampling (CDS) processors, yielding a total chip size of approximately 4.5 mm X 5.0 mm. The image sensor features random accessibility and can be employed for electronic panning applications. It is powered from a single 5.0 V source. At 5.0 V power supply, the video signal saturation level is approximately 1,200 mV with rms read-out noise level of approximately 300 (mu) V, yielding a dynamic range of 72 dB (12 bits). The read-out sensitivity is approximately 6.75 (mu) V per electron, indicating a read-out node capacitance of approximately 24 fF which is consistent with the extracted value. The measured dark current (at room temperature) is approximately 160 mV/s, equivalent to 3.3 nA/cm2. The raw fixed pattern noise (exhibited as column-wise streaks) is approximately 20 mV (peak-to-peak) or approximately 1.67% of saturation level. At 15 frames per second, the power dissipation is approximately 75 mW.

Eid, Sayed I.; Dickinson, Alex G.; Inglis, Dave A.; Ackland, Bryan D.; Fossum, Eric R.

1995-04-01

445

Technology aspects of a CMOS neuro-sensor: back end process and packaging  

Microsoft Academic Search

A CMOS-compatible process is presented which allows to realize sensor arrays for non-invasive, extracellular, high density, long term recording of neural activity. A high-permittivity biocompatible dielectric is used to capacitively couple nerve cell-induced biological signals to the CMOS circuitry-based electronic world. The transducer consists of a multi layer of TiO2 and ZrO2 and is fabricated in the backend of a

Franz Hofmann; Bjrn Eversmann; Martin Jenkner; Alexander Frey; Matthias Merz; Tamara Birkenmaier; Peter Fromherz; Matthias Schreiter; Reinhard Gabl; Kurt Plehnert; Michael Steinhauser; Gerald Eckstein; Roland Thewes

2003-01-01

446

A comprehensive CMOS APS crosstalk study: photoresponse model, technology, and design trends  

Microsoft Academic Search

In this paper the lateral photoresponse and crosstalk (CTK) in complementary metal-oxide-semiconductor (CMOS) photodiodes is investigated by means of a unique sub-micron scanning system (S-cube system) and numerical device simulation. An improved semi-analytical model developed for photoresponse estimation of a photodiode-based CMOS active pixel sensor reveals the photosignal and the CTK dependence on the pixels geometrical shape and arrangement within

Igor Shcherback; Tatiana Danov; Orly Yadid-Pecht

2004-01-01

447

Analysis of the syntenic relationship of bovine thyroglobulin, carbonic anhydrase II, and c-mos genes  

E-print Network

ANALYSIS OF THE SYNTENIC RELATIONSHIP OF BOVINE THYROGLOBULIN, CARBONIC ANHYDRASE II, AND C-MOS GENES A Thesis by LAURA KRISTEN FABER Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment... of the requirements for the degree of MASTER OF SCIENCE December 1988 Major Subject: Genetics ANALYSIS OF THE SYNTENIC RELATIONSHIP OF BOVINE THYROGLOBULIN, CARBONIC ANHYDRASE II, AND C-MOS GENES A Thesis by LAURA KRISTEN FABER Approved as to style...

Faber, Laura Kristen

2012-06-07

448

A novel analog CMOS cellular neural network for biologically-inspired walking robot  

Microsoft Academic Search

We propose a novel analog CMOS circuit that implements a class of cellular neural networks (CNNs) for biologically-inspired walking robots. Recently, a class of autonomous CNNs, so-called a reaction-diffusion (RD) CNN, has applied to locomotion control in robotics. We have introduced a novel RD-CNN, and implemented it as an analog CMOS circuit by using multiple-input floating-gate (MIFG) MOS FETs. As

Kazuki NAKADA; Tetsuya ASAI; Yoshihito AMEMIYA

2003-01-01

449

Investigation of various ways of obtaining output waveforms of CMOS digital circuits by explicit methods  

E-print Network

INVESTIGATION OF VARIOUS WAYS OF OBTAINING OUTPUT WAVEFORMS OF CMOS DIGITAL CIRCUITS BY EXPLICIT METHODS A Thesis by LIAN WAH ONG Submitted to the Office of Graduate Studies of Texas Agi. M University in partial fulfillment... of the requirement for the degree of iMASTER OF SCIENCE December 1989 Major Subject: Electrical Engineering INVESTIGATION OF VARIOUS WAYS OF OBTAINING OUTPUT WAVEFORMS OF CMOS DIGITAL CIRCUITS BY EXPLICIT METHODS A Thesis by LIAN-WAH ONG Approved...

Ong, Lian Wah

2012-06-07

450

A SOC\\/SOP co-design approach for mmW CMOS in QFN technology  

Microsoft Academic Search

The past few years have witnessed the emergence of CMOS based circuits operating at millimeter wave-frequencies. The co-design of fully integrated mmW CMOS single chip digital radios with low cost QFN packages operating from 30 to 100 GHz offers the promise for high volume manufacturing which paves the way for a new millimeter-wave industry. As standardization efforts catalyzed the interest

J. Laskar; S. Pinel; S. Sarkar; P. Sen; B. Perunama; D. Dawn; D. Yeh; F. Barale

2008-01-01

451

[The use of c-mos nuclear gene as a phylogenetic marker in tetraonidae birds].  

PubMed

A 480-bp fragment of nuclear c-mos gene was sequenced in nine bird species representing four genera of the family Tetraonidae. It was demonstrated that nuclear genome region examined was highly conservative. The data were used to construct phylogenetic relationships among the c-mos gene sequences in Tetraonidae. The data obtained point to a paraphyletic origin of hazel grouse (Bonasa bonasia) and ruffed grouse (Bonasa umbellus). PMID:15575499

Butorina, O T; Colovenchuk, L L

2004-10-01

452

A CMOS Current-Reused Transceiver with Stacked LNA and Mixer for WPAN  

Microsoft Academic Search

A low power transceiver is designed in 0.25 mum CMOS technology. Designed transceiver is composed of CMOS PA and low-IF receiver architecture for high integration. To reduce the power dissipation, current-reused topology is used in Rx and up-conversion mixer. And, the simulated power consumption of PA is minimized by optimizing the size of power cells. The power consumptions are 31

Sang-sun Yoo; Seok-oh Yun; Soo-hwan Shin; Hyung-joun Yoo

2006-01-01

453

A high performance CMOS LNA for system-on-chip GPS  

Microsoft Academic Search

A 1.6 GHz CMOS single-ended low noise amplifier (LNA) optimized for integration and use in Global Positioning System (GPS) applications is presented. The LNA is implemented in a 0.13 mum standard CMOS process with on-chip inductors. The LNA achieves a noise figure of 1.35 dB, a power gain of 16.7 dB and a 1 dB compression point of -14 dBm

Bo Bokinge; Wenche Einerman; Anders Emericks; Christian Grewing; Ola Pettersson; Detlev Theil; Stefan van Waasen

2006-01-01

454

Fully integrated CMOS GPS receiver for system-on-chip solutions  

Microsoft Academic Search

A CMOS receiver for the Global Positioning System (GPS) is presented. It is designed in a 0.13mum standard CMOS process and is fully integrated for the needs of a system-on-chip (SoC) solution for GPS and assisted GPS (A-GPS). It provides the needed frequency conversion, gain and filtering for GPS signals without any other external components than those required for matching

Christian Grewing; Bo Bokinge; Wenche Einerman; Anders Emericks; Detlev Theil; Stefan van Waasen

2006-01-01

455

A CMOS-Based Tactile Sensor for Continuous Blood Pressure Monitoring  

Microsoft Academic Search

A monolithic integrated tactile sensor array is presented, which is used to perform non-invasive blood pressure monitoring of a patient. The advantage of this device compared to a hand cuff based approach is the capability of recording continuous blood pressure data. The capacitive, membrane-based sensor device is fabricated in an industrial CMOS-technology combined with post-CMOS micromachining. The capacitance change is

Kay-uwe Kirstein; Jan Sediv; Tomi Salo; Christoph Hagleitner; Tobias Vancura; Andreas Hierlemann

2004-01-01

456

A CMOS-Based Tactile Sensor for Continuous Blood Pressure Monitoring  

Microsoft Academic Search

A monolithic integrated tactile sensor array is presented, which is used to perform non-invasive blood pressure monitoring of a patient. The advantage of this device compared to a hand cuff based approach is the capability of recording continuous blood pressure data. The capacitive, membrane-based sensor device is fabricated in an industrial CMOS-technology combined with post-CMOS micromachining. The capacitance change is

K. u. Kirstein; J. Sedivy; T. Salo; C. Hagleitner; T. Vancura; A. Hierlemann

2005-01-01

457

Three-Dimensional Photoacoustic Imaging by a CMOS Micromachined Capacitive Ultrasonic Sensor  

Microsoft Academic Search

In this letter, we demonstrate the feasibility of 3-D photoacoustic imaging using a monolithic CMOS micromachined capacitive ultrasonic sensor. The sensing membranes are released by a post-CMOS metal etch and sealed by silicon dioxide. Nine membranes, each with an inner diameter of 60 ?m, form a single detection unit with a capacitance value of 292.5 fF. A 6-? mc arbon

Meng-Lin Li; Po-Hsun Wang; Pei-Liang Liao; Michael S.-C. Lu

2011-01-01

458

A CMOS-based tactile sensor for continuous blood pressure monitoring  

Microsoft Academic Search

A monolithic integrated tactile sensor array is presented, which is used to perform non-invasive blood pressure monitoring of a patient. The advantage of this device, compared to a hand cuff based approach, is the capability of recording continuous blood pressure data. The capacitive, membrane-based sensor device is fabricated in an industrial CMOS-technology combined with post-CMOS micromachining. The capacitance change is

K.-U. Kirstein; J. Sedivy; T. Salo; C. Hagleitner; T. Vancura; H. Baltes

2004-01-01

459

Three dimensional photoacoustic imaging using a monolithic CMOS MEMS capacitive ultrasonic sensor  

Microsoft Academic Search

In this study, we demonstrate the feasibility of three dimensional (3-D) photoacoustic imaging using a monolithic CMOS MEMS capacitive ultrasonic sensor. The sensing membranes are released by a post-CMOS metal etch and sealed by silicon dioxide. Nine membranes, each with an inner diameter of 60 ?m, form a single detection unit with a capacitance value of 292.5 fF. The measured

Meng-Lin Li; Po-Hsun Wang; Pei-Liang Liao; Michael S.-C. Lu

2011-01-01

460

A multisampling time-domain CMOS imager with synchronous readout circuit  

Microsoft Academic Search

A novel multisampling time-domain architecture for CMOS imagers with synchronous readout and wide dynamic range is proposed. The architecture was implemented in a prototype of imager with 32x32 pixel array fabricated in AMS CMOS 0.35m and was characterized for sensitivity and color response. The pixel is composed of an n+\\/psub photodiode, a comparator and a D flip-flop having 16% fill-factor

Fernando De Souza Campos; Ognian Marinov; Naser Faramarzpour; Fayal Saffih; M. Jamal Deen; Jacobus W. Swart

2007-01-01

461

An efficient low voltage, high frequency silicon CMOS light emitting device and electro-optical interface  

Microsoft Academic Search

A silicon light emitting device was designed and realized utilizing a standard 2-?m industrial CMOS technology design and processing procedure. The device and its associated driving circuitry were integrated in a CMOS integrated circuit and can interface with a multimode optical fiber. The device delivers 8 nW of optical power (450-850 nm wavelength) per 20-?m diameter of chip area at

L. W. Snyman; M. du Plessis; E. Seevinck; H. Aharoni

1999-01-01

462

CMOS image sensor-based implantable glucose sensor using glucose-responsive fluorescent hydrogel  

PubMed Central

A CMOS image sensor-based implantable glucose sensor based on an optical-sensing scheme is proposed and experimentally verified. A glucose-responsive fluorescent hydrogel is used as the mediator in the measurement scheme. The wired implantable glucose sensor was realized by integrating a CMOS image sensor, hydrogel, UV light emitting diodes, and an optical filter on a flexible polyimide substrate. Feasibility of the glucose sensor was verified by both in vitro and in vivo experiments.

Tokuda, Takashi; Takahashi, Masayuki; Uejima, Kazuhiro; Masuda, Keita; Kawamura, Toshikazu; Ohta, Yasumi; Motoyama, Mayumi; Noda, Toshihiko; Sasagawa, Kiyotaka; Okitsu, Teru; Takeuchi, Shoji; Ohta, Jun

2014-01-01

463

Surface Morphology Measurement and Investigation of A New CMOS Compatible Thermopile with High Fill Factor  

Microsoft Academic Search

A new CMOS compatible thermopile was designed and fabricated with high fill factor, the floating membrane of the thermopile which we designed was formed by T-shape anisotropic etching window that never be proposed before. The design and fabrication of thermopile sensors are realized by using 1.2 mum CMOS IC technology combined with a subsequent anisotropic front-side etching. Four etching windows

Shu-Jung Chen; Chih-Hsiung Shen

2006-01-01

464

Technologies for (sub-) 45nm Analog\\/RF CMOS - Circuit Design Opportunities and Challenges  

Microsoft Academic Search

The new process module and device architecture options emerging for (sub-) 45nm CMOS, lead to both opportunities and challenges for analog\\/RF circuit design. These will be discussed both at the device level and circuit level for two competing architectures (planar bulk CMOS versus FinFETs), for different gate stacks and mobility enhancement techniques. Very high cutoff frequencies will be demonstrated for

S. Decoutere; P. Wambacq; V. Subramanian; J. Borremans; A. Mercha

2006-01-01

465

An acquisition system for CMOS imagers with a genuine 10 Gbit\\/s bandwidth  

Microsoft Academic Search

This paper presents a high data throughput acquisition system for pixel detector readout such as CMOS imagers. This CMOS acquisition board offers a genuine 10 Gbit\\/s bandwidth to the workstation and can provide an on-line and continuous high frame rate imaging capability. On-line processing can be implemented either on the Data Acquisition Board or on the multi-cores workstation depending on

C. Gurin; J. Mahroug; W. Tromeur; J. Houles; P. Calabria; R. Barbier

466

A timing simulator for BICMOS, CMOS and BINMOS circuits and systems  

E-print Network

A TIMING SIMULATOR FOR BICMOS, CMOS AND BINMOS CIRCUITS AND SYSTEMS A Thesis by RAGURAM DAMODARAN Submitted (o the Office of Graduate Studies of Texas ASM University in partial fulfillment of the requirements for the degree of MASTER... OF SCIENCE August 1993 Major Subject: Electrical Engineering A TIMING SIMULATOR FOR BICMOS, CMOS AND BINMOS CIRCUITS AND SYSTEMS A Thesis by RAGURAM DAMODARAN Approved as to style and content by: Sherif . K. Rmbabi (Chair of Committee) Don E. Ross...

Damodaran, Raguram

2012-06-07

467

A wide-band CMOS read amplifier for magnetic data storage systems  

Microsoft Academic Search

Circuit techniques for a CMOS amplifier suitable for read waveform signal processing in high-speed disk drives are described. A 30-MHz low-noise preamplifier with a gain of 100 was designed in 3-?m CMOS, capable of being driven by an inductive source, and producing an equivalent input noise voltage spectral density of 2 nV\\/?Hz. This, with other recent developments, makes it possible

Tzu-Wang Pan; Asad A. Abidi

1992-01-01

468

Challenges in Designing Low-Power CMOS Wireless Systems-on-a-Chip  

Microsoft Academic Search

This paper describes the challenges in designing low-power CMOS systems-on-a-chip for wireless communications. RF transceiver building blocks for signal amplification, frequency translation, and frequency selectivity are examined with special emphasis on low noise amplifier, power amplifier, mixer, and frequency synthesizer. System-on-a-chip integration issues to relevant to a low-power CMOS design are also discussed

David Su

2006-01-01

469

High performance and low power transistors integrated in 65nm bulk CMOS technology  

Microsoft Academic Search

This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated an astonishing 35 %

Z. Luo; A. Steegen; M. Eller; R. Mann; C. Baiocco; P. Nguyen; L. Kim; M. Hoinkis; V. Ku; V. Klee; F. Jamin; P. Wrschka; P. Shafer; W. Lin; S. Fang; A. Ajmera; W. Tan; R. Mo; J. Lian; D. Vietzke; C. Coppock; A. Vayshenker; T. Hook; V. Chan; K. Kim; A. Cowley; S. Kim; E. Kaltalioglu; B. Zhang; S. Marokkey; Y. Lin; K. Lee; H. Zhu; M. Weybright; R. Rengarajan; J. Ku; T. Schiml; J. Sudijono; I. Yang; C. Wann

2004-01-01

470

Towards a hybrid CMOS-imager with organic semiconductors as photoactive layer  

Microsoft Academic Search

Hybrid CMOS-imagers with vertically integrated organic semiconductors are proposed to enhance the currently small fill factor of conventional CMOS-pixels. Organic photodetectors (OPDs) are low-cost and easy processable and their performance begins to match the one of silicon based devices. Therefore, they are advantageous compared to other hybrid concepts like costly microlenses or thin-film-on-ASIC. In addition, the spectral tunability of organic

Daniela Baierl; Morten Schmidt; Giuseppe Scarpa; Paolo Lugli; Lucio Pancheri; David Stoppa; Gian-Franco Dalla Betta

2011-01-01

471

Refined Si-CMOS-MEMS process using AOE, drie and preform bonding  

Microsoft Academic Search

This paper presents a Si-CMOS-MEMS fabrication process that forms released structures out of a 10 m CMOS metal and oxide stack along with a 50 m-thick section of the underlying silicon substrate. The process employs back-side silicon grinding that provides silicon mean roughness of 20 nm and maximum peak-to-valley roughness of 264 nm. The thinned MEMS substrate is bonded with

Y.-J. Fang; T. Mukherjee; G. K. Fedder

2011-01-01

472

An ultra-wideband CMOS low noise amplifier for 3-5GHz UWB system  

Microsoft Academic Search

AbstractAn ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18- m CMOS technology for a

Chang-Wan Kim; Min-Suk Kang; Phan Tuan Anh; Hoon-Tae Kim; Sang-Gug Lee

2005-01-01

473

Fabrication, characterization, and analysis of a DRIE CMOS-MEMS gyroscope  

Microsoft Academic Search

A gyroscope with a measured noise floor of 0.02\\/s\\/Hz12\\/ at 5 Hz is fabricated by post-CMOS micromachining that uses interconnect metal layers to mask the structural etch steps. The 1 1 mm lateral-axis angular rate sensor employs in-plane vibration and out-of-plane Coriolis acceleration detection with on-chip CMOS circuitry. The resultant device incorporates a combination of 1.8-?m-thick thin-film structures for

Huikai Xie; Gary K. Fedder

2003-01-01

474

Transistor-level test generation for physical failures in CMOS circuits  

Microsoft Academic Search

A new methodology is proposed for generating tests at the transistor level for realistic failures including bridging faults, and transistor gate-to-source short and gate-to-drain short faults in CMOS combinational circuits. A new tree model for a fault-free CMOS complex gate is used to propagate errors due to faults with much less computation time. The technique adapts the tree structure representation

Hsi-Ching Shih; Jacob A. Abraham

1986-01-01

475

A self-packaged thermal flow sensor by CMOS MEMS technology  

Microsoft Academic Search

An integrated two-dimensional self-packaged flow sensor made by CMOS technology plus micromachining is presented. Heater resistors formed by diffusion of boron into an n-type Si substrate are located on the center of the chip and four substrate bipolar transistors by CMOS for temperature sensing surround the heaters symmetrically. A trench made by ICP (inductively coupled plasma) technology between the heater

Dong-hui Gao; Ming Qin; Hai-yang Chen; Qing-an Huang

2004-01-01

476

A low-noise CMOS instrumentation amplifier for thermoelectric infrared detectors  

Microsoft Academic Search

A low-noise CMOS instrumentation amplifier for low-frequency thermoelectric infrared sensor applications is described which uses a chopper technique to reduce low-frequency noise and offset. The offset reduction efficiency of the band-pass filter, implemented to reduce residual offset due to clock feedthrough, has been analyzed and experimentally verified. The circuit has been integrated in a transistor-only 1-?m single-poly n-well CMOS process.

Christian Menolfi; Qiuting Huang

1997-01-01

477

A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources  

NASA Astrophysics Data System (ADS)

Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Faur, Nicolaas M.

2013-03-01

478

NASA commercial programs  

NASA Technical Reports Server (NTRS)

An expanded role for the U.S. private sector in America's space future has emerged as a key national objective, and NASA's Office of Commercial Programs is providing a focus for action. The Office supports new high technology commercial space ventures, the commercial application of existing aeronautics and space technology, and expanded commercial access to available NASA capabilities and services. The progress NASA has made in carrying out its new assignment is highlighted.

1988-01-01

479

A Wideband 90 continuous phase shifter for 60GHz phased array transceiver in 90nm CMOS technology  

Microsoft Academic Search

This paper presents a wideband reflective-type phase-shifter in 90 nm CMOS technology. The proposed phase shifter, employs a broadside coupler in the multi-layer metal structure in CMOS technology to attain 3-dB coupling at coupled and through ports where the phase difference between these two ports is 90deg. The reflective load contains a NMOS CMOS varactor with a tuning ratio of

Behzad Biglarbegian; Mohammad-Reza Nezhad-Ahmadi; Mohammad Fakharzadeh; Safieddin Safavi-Naeini

2009-01-01

480

A wideband 90 continuous phase shifter for 60GHz phased array transceiver in 90nm CMOS technology  

Microsoft Academic Search

This paper presents a wideband reflective-type phase-shifter in 90 nm CMOS technology. The proposed phase shifter, employs a broadside coupler in the multi-layer metal structure in CMOS technology to attain 3-dB coupling at coupled and through ports where the phase difference between these two ports is 90. The reflective load contains a NMOS CMOS varactor with a tuning ratio of

Behzad Biglarbegian; Mohammad-Reza Nezhad-Ahmadi; Mohammad Fakharzadeh; Safieddin Safavi-Naeini

2009-01-01

481

Commercialization and Startup Primer  

E-print Network

Technology Commercialization and Startup Primer Office of Technology Licensing (OTL) and UF Tech Connect® Where Science Meets Business #12;Table of Contents page Overview 1 Technology Commercialization and assistance to faculty, staff, and entrepreneurs who may be interested in commercializing University

Jawitz, James W.

482

Pennsylvania Commercial Vegetable  

E-print Network

Pennsylvania Commercial Vegetable Production Recommendations #12;NOT TO BE USED BY HOME GARDENERS This copy of the Pennsylvania Commercial Vegetable Production Recommendations for 2014 replaces all previous production guide is intended for the commercial vegetable grower who has to make numerous managerial

Guiltinan, Mark

483

Nanotechnology Commercialization in Oregon  

E-print Network

Nanotechnology Commercialization in Oregon February 27, 2012 Portland State University Physics Seminar Robert D. "Skip" Rung President and Executive Director #12;2 Nanotechnology Commercialization the transfer of new technologies into products for commercial and public benefit; To develop and sustain

Moeck, Peter

484

PHOTOVOLTAICS AND COMMERCIAL BUILDINGS--  

E-print Network

PHOTOVOLTAICS AND COMMERCIAL BUILDINGS-- A NATURAL MATCH A study highlighting strategic? Business owners and commercial users are uniquely positioned to capitalize on other important factors: · PV's electrical output matches well with patterns of energy use in commercial buildings, promoting effective

Perez, Richard R.

485

Commercial Radio as Communication.  

ERIC Educational Resources Information Center

Compares the day-to-day work routines of commercial radio with the principles of a theoretical communication model. Illuminates peculiarities of the conduct of communication by commercial radio. Discusses the application of theoretical models to the evaluation of practicing institutions. Offers assessments of commercial radio deriving from

Rothenbuhler, Eric W.

1996-01-01

486

Low threshold vertical cavity surface emitting lasers integrated onto Si-CMOS ICs using novel hybrid assembly techniques  

E-print Network

A new heterogeneous integration technique has been developed and demonstrated to integrate vertical cavity surface emitting lasers (VCSELs) on silicon CMOS integrated circuits for optical interconnect applications. Individual ...

Perkins, James Michael, 1978-

2007-01-01

487

A digital output accelerometer using MEMS-based piezoelectric accelerometers and arrayed CMOS inverters with satellite capacitors  

NASA Astrophysics Data System (ADS)

The present paper describes the development of a digital output accelerometer composed of microelectromechanical systems (MEMS)-based piezoelectric accelerometers and arrayed complementary metal-oxide-semiconductor (CMOS) inverters accompanied by capacitors. The piezoelectric accelerometers were fabricated from multilayers of Pt/Ti/PZT/Pt/Ti/SiO2 deposited on silicon-on-insulator (SOI) wafers. The fabricated piezoelectric accelerometers were connected to arrayed CMOS inverters. Each of the CMOS inverters was accompanied by a capacitor with a different capacitance called a 'satellite capacitor'. We have confirmed that the output voltage generated from the piezoelectric accelerometers can vary the output of the CMOS inverters from a high to a low level; the state of the CMOS inverters has turned from the 'off-state' into the 'on-state' when the output voltage of the piezoelectric accelerometers is larger than the threshold voltage of the CMOS inverters. We have also confirmed that the CMOS inverters accompanied by the larger satellite capacitor have become 'on-state' at a lower acceleration. On increasing the acceleration, the number of on-state CMOS inverters has increased. Assuming that the on-state and off-state of CMOS inverters correspond to logic '0' and '1', the present digital output accelerometers have expressed the accelerations of 2.0, 3.0, 5.0, and 5.5 m s - 2 as digital outputs of 111, 110, 100, and 000, respectively.

Kobayashi, T.; Okada, H.; Masuda, T.; Maeda, R.; Itoh, T.

2011-06-01

488

Integration of room temperature single electron transistor with CMOS subsystem  

NASA Astrophysics Data System (ADS)

The single electron transistor (SET) is a charge-based device that may complement the dominant metal-oxide-semiconductor field effect transistor (MOSFET) technology. As the cost of scaling MOSFET to smaller dimensions are rising and the the basic functionality of MOSFET is encountering numerous challenges at dimensions smaller than 10nm, the SET has shown the potential to become the next generation device which operates based on the tunneling of electrons. Since the electron transfer mechanism of a SET device is based on the non-dissipative electron tunneling effect, the power consumption of a SET device is extremely low, estimated to be on the order of 10--18 J. The objectives of this research are to demonstrate technologies that would enable the mass produce of SET devices that are operational at room temperature and to integrate these devices on top of an active complementary-MOSFET (CMOS) substrate. To achieve these goals, two fabrication techniques are considered in this work. The Focus Ion Beam (FIB) technique is used to fabricate the islands and the tunnel junctions of the SET device. A Ultra-Violet (UV) light based Nano-Imprint Lithography (NIL) call Step-and-Flash-Imprint Lithography (SFIL) is used to fabricate the interconnections of the SET devices. Combining these two techniques, a full array of SET devices are fabricated on a planar substrate. Test and characterization of the SET devices has shown consistent Coulomb blockade effect, an important single electron characteristic. To realize a room temperature operational SET device that function as a logic device to work along CMOS, it is important to know the device behavior at different temperatures. Based on the theory developed for a single island SET device, a thermal analysis is carried out on the multi-island SET device and the observation of changes in Coulomb blockade effect is presented. The results show that the multi-island SET device operation highly depends on temperature. The important parameters that determine the SET operation is the effective capacitance Ceff and tunneling resistance Rt. These two parameters lead to the tunneling rate of an electron in the SET device, Gamma. To obtain an accurate model for SET operation, the effects of the deviation in dimensions, the trap states in the insulation, and the background charge effect have to be taken into consideration. The theoretical and experimental evidence for these non-ideal effects are presented in this work.

Cheam, Daw Don

489

COMMERCIAL SERVICES SUSTAINABLE FOOD POLICY  

E-print Network

COMMERCIAL SERVICES SUSTAINABLE FOOD POLICY February 2013 Commercial Services (CS) provides a range, and associated action plan, through the Commercial Services Sustainability Steering Group and the University

Haase, Markus

490

Accelerated life testing effects on CMOS microcircuit characteristics  

NASA Technical Reports Server (NTRS)

This report covers the time period from May 1976 to December 1979 and encompasses the three phases of accelerated testing: Phase 1, the 250 C testing; Phase 2, the 200 C testing; and Phase 3, the 125 C testing. The duration of the test in Phase 1 and Phase 2 was sufficient to take the devices into the wear out region. The wear out distributions were used to estimate the activation energy between the 250 C and the 200 C test temperatures. The duration of the 125 C test, 20,000 hours, was not sufficient to bring the test devices into the wear out region; consequently the third data point at 125 C for determining the consistency of activation energy could not be obtained. It was estimated that, for the most complex of the three device types, the activation energy between 200 C and 125 C should be at least as high as that between 250 C and 200 C. The practicality of the use of high temperature for the accelerated life tests from the point of view of durability of equipment was assessed. Guidelines for the development of accelerated life test conditions were proposed. The use of the silicon nitride overcoat to improve the high temperature accelerated life test characteristics of CMOS microcircuits was explored in Phase 4 of this study and is attached as an appendix to this report.

1980-01-01

491

High resolution, high bandwidth global shutter CMOS area scan sensors  

NASA Astrophysics Data System (ADS)

Global shuttering, sometimes also known as electronic shuttering, enables the use of CMOS sensors in a vast range of applications. Teledyne DALSA Global shutter sensors are able to integrate light synchronously across millions of pixels with microsecond accuracy. Teledyne DALSA offers 5 transistor global shutter pixels in variety of resolutions, pitches and noise and full-well combinations. One of the recent generations of these pixels is implemented in 12 mega pixel area scan device at 6 um pitch and that images up to 70 frames per second with 58 dB dynamic range. These square pixels include microlens and optional color filters. These sensors also offer exposure control, anti-blooming and high dynamic range operation by introduction of a drain and a PPD reset gate to the pixel. The state of the art sense node design of Teledyne DALSA's 5T pixel offers exceptional shutter rejection ratio. The architecture is consistent with the requirements to use stitching to achieve very large area scan devices. Parallel or serial digital output is provided on these sensors using on-chip, column-wise analog to digital converters. Flexible ADC bit depth combined with windowing (adjustable region of interest, ROI) allows these sensors to run with variety of resolution/bandwidth combinations. The low power, state of the art LVDS I/O technology allows for overall power consumptions of less than 2W at full performance conditions.

Faramarzpour, Naser; Sonder, Matthias; Li, Binqiao

2013-10-01

492

A CMOS Smart Thermal Sensor for Biomedical Application  

NASA Astrophysics Data System (ADS)

This paper describes a smart thermal sensing chip with an integrated vertical bipolar transistor sensor, a Sigma Delta Modulator (SDM), a Micro-Control Unit (MCU), and a bandgap reference voltage generator for biomedical application by using 0.18?m CMOS process. The npn bipolar transistors with the Deep N-Well (DNW) instead of the pnp bipolar transistor is first adopted as the sensor for good isolation from substrate coupling noise. In addition to data compression, Micro-Control Unit (MCU) plays an important role for executing auto-calibration by digitally trimming the bipolar sensor in parallel to save power consumption and to reduce feedback complexity. It is different from the present analog feedback calibration technologies. Using one sensor, instead of two sensors, to create two differential signals in 180 phase difference input to SDM is also a novel design of this work. As a result, in the range of 0C to 80C or body temperature (375C), the inaccuracy is less than 0.1C or 0.05C respectively with one-point calibration after packaging. The average power consumption is 268.4?W with 1.8V supply voltage.

Lee, Ho-Yin; Chen, Shih-Lun; Luo, Ching-Hsing

493

Analysis of multiple bit upsets (MBU) in a CMOS SRAM  

SciTech Connect

Multiple Bit Upsets (MBU) have been studied in a 256k CMOS static RAM irradiated at normal incidence and grazing angle. In normal incidence the sensitive areas have been identified with pulsed laser irradiation. The laser power thresholds have been determined for single to quadruple upsets in adjacent cells. Both experimental data and 3D simulations emphasize the role of delayed charge collection, by diffusion, and charge sharing between sensitive areas. Upset tracks have been recorded at grazing angle and used to determine the charge collection depth. These data revealed the existence of an LET threshold for MBU at grazing angle. As the ion LET increases different types of tracks are observed and correlated to the topological pattern in adjacent memory cells. This phenomenon is due to an unexpected charge collection mechanism, which couples adjacent sensitive areas and results in charge transfer between memory cells. The comparison with previous data on the same device indicates a strong influence of both ion energy and angle of incidence on the cross section, emphasizing the intrinsic limitation of standard characterizations with low energy ions. These results indicate that the basic assumption of a rectangular parallelepipedic volume does not take into account coupling phenomena, such as occurs in MBUs, and is no longer valid at grazing angle.

Musseau, O.; Gardic, F.; Roche, P. [CEA, Bruyeres le Chatel (France)] [and others] [CEA, Bruyeres le Chatel (France); and others

1996-12-01

494

Label-free immunodetection with CMOS-compatible semiconducting nanowires  

NASA Astrophysics Data System (ADS)

Semiconducting nanowires have the potential to function as highly sensitive and selective sensors for the label-free detection of low concentrations of pathogenic microorganisms. Successful solution-phase nanowire sensing has been demonstrated for ions, small molecules, proteins, DNA and viruses; however, `bottom-up' nanowires (or similarly configured carbon nanotubes) used for these demonstrations require hybrid fabrication schemes, which result in severe integration issues that have hindered widespread application. Alternative `top-down' fabrication methods of nanowire-like devices produce disappointing performance because of process-induced material and device degradation. Here we report an approach that uses complementary metal oxide semiconductor (CMOS) field effect transistor compatible technology and hence demonstrate the specific label-free detection of below 100 femtomolar concentrations of antibodies as well as real-time monitoring of the cellular immune response. This approach eliminates the need for hybrid methods and enables system-scale integration of these sensors with signal processing and information systems. Additionally, the ability to monitor antibody binding and sense the cellular immune response in real time with readily available technology should facilitate widespread diagnostic applications.

Stern, Eric; Klemic, James F.; Routenberg, David A.; Wyrembak, Pauline N.; Turner-Evans, Daniel B.; Hamilton, Andrew D.; Lavan, David A.; Fahmy, Tarek M.; Reed, Mark A.

2007-02-01

495

Circuit design for nuclear radiation test of CMOS multiplier chips  

SciTech Connect

This paper describes the design of a microprocessor-based electronic circuit to be used in testing the effects of nuclear radiation on a CMOS 8 x 8 multiplier chip. Knowledge of such effects is important for military and space applications of integrated circuits. The multiplier chip undergoing testing is attached to a DUT (device under test) board which is enclosed in a metal container. The container is then lowered to the cobalt 60 radiation source located at the bottom of a 15-ft-deep pool. The gamma-ray radiation test setup is schematically shown. The in-source test board containing the multiplier chip is attached to an 8085-based, single-board microcomputer (SDK-85) by a 30-ft multiconductor cable. Doses of gamma-ray radiation from cobalt 60 are applied in steps at increasing quantities until the multiplier chip, which is tested between doses, begins to malfunction. An 8085 assembly language program is used for functional test of the multiplier. The leakage current and the propagation delay time are also measured between doses.

Lim, T.S.; Martin, R.L.; Hughes, H.L.

1986-09-01

496

Submicron CMOS MIL-STD-1750A based mission processor  

NASA Astrophysics Data System (ADS)

The author describes the design of a MIL-STD-1750A mission processor (MP), which is generally based on the US Air Force Pave Pillar architecture. The MP is composed of a power conditioner unit, a chassis assembly, and a set of SEM-E (3/4 ATR)-size common modules. The common modules utilize a set of seven complex submicrometer CMOS integrated circuits as building blocks. The internal design architecture features a dual PI-Bus for intermodule communication and a dual TM-Bus for operational test and maintenance. The MP is capable of over 22-million-instructions/s performance on the Defense Avionics Instructions Set (DAIS) mix and contains up to 2.56 million words of random-access memory and 288 thousand words of read-only memory. The MP provides external interfaces to three dual redundant MIL-STD-1553B serial communication buses, two differential Small Computer System Interface (SCSI) buses, an IEEE-488 bus, and miscellaneous digital and analog discrete lines.

Coulon, Kenneth E.

497

Characteristics of CMOS Light Detectors at Cryogenic Temperatures  

NASA Astrophysics Data System (ADS)

Advancing nuclear and high-energy physics often requires experiments conducted in harsh environments, such as a liquid helium bath and a superconducting magnet at several Tesla. These experiments need improved sensors that operate in these conditions. Improvements in detector technology used in extreme environments can improve the data quality and allow new designs for experiments that operate under these conditions. Solid-State Photomultipliers (SSPM), a device built from a monolithic array of photodiodes, can be used in these environments where traditional PMTs may not operate. Measurements of the diode properties at low temperatures down to 5 K are used to determine the potential of CMOS SSPMs in these environments. At temperatures below 60 K, extensive after pulsing is observed, which renders the Geiger photodiodes in the SSPM nonfunctional for biases above breakdown. In proportional mode operation, below the reverse bias breakdown, the photodiodes show a linear response to incident light with a relatively large gain and can be used at temperatures near 5 K.

Christian, James; Johnson, Erik; Stapels, Christopher; Linsay, Paul; Miskimen, Rory; Crabb, Donald; Augustine, Frank

2008-10-01

498

Passive radiation detection using optically active CMOS sensors  

NASA Astrophysics Data System (ADS)

Recently, there have been a number of small-scale and hobbyist successes in employing commodity CMOS-based camera sensors for radiation detection. For example, several smartphone applications initially developed for use in areas near the Fukushima nuclear disaster are capable of detecting radiation using a cell phone camera, provided opaque tape is placed over the lens. In all current useful implementations, it is required that the sensor not be exposed to visible light. We seek to build a system that does not have this restriction. While building such a system would require sophisticated signal processing, it would nevertheless provide great benefits. In addition to fulfilling their primary function of image capture, cameras would also be able to detect unknown radiation sources even when the danger is considered to be low or non-existent. By experimentally profiling the image artifacts generated by gamma ray and ? particle impacts, algorithms are developed to identify the unique features of radiation exposure, while discarding optical interaction and thermal noise effects. Preliminary results focus on achieving this goal in a laboratory setting, without regard to integration time or computational complexity. However, future work will seek to address these additional issues.

Dosiek, Luke; Schalk, Patrick D.

2013-05-01

499

CMOS Image Sensor with a Built-in Lane Detector  

PubMed Central

This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 2,389.8 ?m, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 21.8 ?m and the core size of photodiode is 12.45 9.6 ?m; the resulting fill factor is 29.7%. PMID:22573983

Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

2009-01-01

500

High-sensitivity chemiluminescence detection of cytokines using an antibody-immobilized CMOS image sensor  

NASA Astrophysics Data System (ADS)

In this study, we used a Complementary Metal Oxide Semiconductor (CMOS) image sensor with immobilizing antibodies on its surface to detect human cytokines, which are activators that mediate intercellular communication including expression and control of immune responses. The CMOS image sensor has many advantages over the Charge Couple Device, including lower power consumption, operation voltage, and cost. The photodiode, a unit pixel component in the CMOS image sensor, receives light from the detection area and generates digital image data. About a million pixels are embedded, and size of each pixel is 3 x 3 ?m. The chemiluminescence reaction produces light from the chemical reaction of luminol and hydrogen peroxide. To detect cytokines, antibodies were immobilized on the surface of the CMOS image sensor, and a sandwich immunoassay using an HRP-labeled antibody was performed. An HRP-catalyzed chemiluminescence reaction was measured by each pixel of the CMOS image sensor. Pixels with stronger signals indicated higher cytokine concentrations; thus, we were able to measure human interleukin-5 (IL-5) at femtomolar concentrations.

Hong, Dong-Gu; Joung, Hyou-Arm; Kim, Sang-Hyo; Kim, Min-Gon

2013-05-01