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Sample records for 130-nm commercial cmos

  1. Low-noise design issues for analog front-end electronics in 130 nm and 90 nm CMOS technologies

    E-print Network

    Manghisoni, M; Re, V; Speziali, V; Traversi, G

    2007-01-01

    Deep sub-micron CMOS technologies provide wellestablished solutions to the implementation of low-noise front-end electronics in various detector applications. The IC designers’ effort is presently shifting to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In this work the results of noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. The behavior of the 1/f and white noise terms is studied as a function of the device polarity and of the gate length and width. The study is focused on low current density applications where devices are biased in weak or moderate inversion. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends in LHC upgrades.

  2. A 12 GHz low-jitter LC-VCO PLL in 130 nm CMOS

    NASA Astrophysics Data System (ADS)

    You, Y.; Chen, J.; Feng, Y.; Tang, Y.; Huang, D.; Rui, W.; Gong, D.; Liu, T.; Ye, J.

    2015-03-01

    We present a wideband low-jitter LC-VCO phase-locked loop in 130 nm CMOS technology for high speed serial link applications. The PLL covers a 5.6 GHz to 13.4 GHz frequency range by using two LC-VCO cores with an RMS jitter of 370 fs. The single event effects testing is performed with a neutron beam at Los Alamos National Laboratory and no frequency disturbance is found over the test period. The PLL consumes 50.88 mW of power under a 1.2 V power supply.

  3. Development of front-end electronics for LumiCal detector in CMOS 130 nm technology

    NASA Astrophysics Data System (ADS)

    Firlej, M.; Fiutowski, T.; Idzik, M.; Moro?, J.; ?wientek, K.; Terlecki, P.

    2015-01-01

    The design and the preliminary measurements results of a multichannel, variable gain front-end electronics for luminosity detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier with pole-zero cancellation circuit and a CR-RC shaper with 50 ns peaking time. The measurements results confirm full functionality of the prototype and compliance with the requirements imposed by the detector specification. The power consumption of the front-end is in the range 0.6-1.5 mW per channel and the noise ENC around 900 e - at 10 pF input capacitance.

  4. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology.

    PubMed

    Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

    2015-01-01

    This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ?? ADC converts each photo diode's current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 ?A on average at 10 readings per second, and occupies approx. 0.8 mm(2) of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA. PMID:26205275

  5. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology

    PubMed Central

    Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

    2015-01-01

    This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ?? ADC converts each photo diode’s current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 ?A on average at 10 readings per second, and occupies approx. 0.8 mm2 of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA. PMID:26205275

  6. Radiation hardness evaluation of a 130 nm SiGe BiCMOS technology for high energy physics applications

    NASA Astrophysics Data System (ADS)

    Díez, S.; Clark, T.; Grillo, A. A.; Kononenko, W.; Martinez-McKinney, F.; Newcomer, F. M.; Norgren, M.; Rescia, S.; Spencer, E.; Spieler, H.; Ullán, M.; Wilder, M.

    2013-10-01

    Final results for a comprehensive radiation hardness evaluation of a high performance, low cost, 130 nm SiGe BiCMOS technology are presented. After a survey of several available SiGe technologies, one was chosen in terms of performance, power consumption, radiation hardness, and cost and it is presented as a suitable technology for the future upgrades of the ATLAS detector of the High Luminosity LHC. Bipolar devices of different sizes and geometries have been evaluated, along with a prototype Front-End readout ASIC designed for binary readout of silicon microstrip detectors. Gamma, neutron and proton irradiations have been performed up to the expected doses and fluences of the experiment.

  7. Hardening of commercial CMOS PROMs with polysilicon fusible links

    NASA Technical Reports Server (NTRS)

    Newman, W. H.; Rauchfuss, J. E.

    1985-01-01

    The method by which a commercial 4K CMOS PROM with polysilicon fuses was hardened and the feasibility of applying this method to a 16K PROM are presented. A description of the process and the necessary minor modifications to the original layout are given. The PROM circuit and discrete device characteristics over radiation to 1000K rad-Si are summarized. The dose rate sensitivity of the 4K PROMs is also presented.

  8. Fully digital, phase-domain ?? 3D range image sensor in 130nm CMOS imaging technology 

    E-print Network

    Walker, Richard John

    2012-06-25

    Three-Dimensional (3D) optical range-imaging is a field experiencing rapid growth, expanding into a wide variety of machine vision applications, most recently including consumer gaming. Time of Flight (ToF) cameras, akin ...

  9. Lifetime studies of 130nm nMOS transistors intended for long-duration, cryogenic high-energy physics experiments.

    SciTech Connect

    Hoff, J.R.; Arora, R.; Cressler, J.D.; Deptuch, G.W.; Gui, P.; Lourenco, N.E.; Wu, G.; Yarema, R.J.; /Fermilab

    2011-12-01

    Future neutrino physics experiments intend to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. To increase performance, integrated readout electronics should work inside the cryostat. Due to the scale and cost associated with evacuating and filling the cryostat, the electronics will be unserviceable for the duration of the experiment. Therefore, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is via hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130nm nMOS transistors operating at cryogenic temperatures are investigated. The results show that the difference in lifetime for room temperature operation and cryogenic operation for this process are not great and the lifetimes at both 300K and at 77K can be projected to more than 20 years at the nominal voltage (1.5V) for this technology.

  10. Packaging commercial CMOS chips for lab on a chip integration.

    PubMed

    Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

    2014-05-21

    Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems. PMID:24682025

  11. Miroirs pour l'UV lointain (VUV) entre 80 et 130 nm

    NASA Astrophysics Data System (ADS)

    Bridou, F.; Cuniot-Ponsard, M.; Desvignes, J.-M.

    2006-12-01

    Dans le domaine spectral entre 80 et 130 nm situé dans le VUV (“Vacuum Ultra-Violet”), les matériaux ne sont ni transparents, ni vraiment réfléchissants. Il est difficile de réaliser des systèmes optiques et, en conséquence, de déterminer les constantes optiques des matériaux. Les écarts entre la réflectivité calculée à partir des indices référencés dans les tables et la réflectivité expérimentale nous ont conduits à penser que certains de ces indices n'étaient pas exacts. Nous avons développé une méthode expérimentale de détermination des constantes optiques à partir des mesures de réflectivité au voisinage de l'incidence normale, en fonction de la longueur d'onde. A partir des valeurs ainsi déterminées, des composants tels que miroirs ou polariseurs peuvent être conçus et réalisés.

  12. Power Supply Optimization in Sub-130 nm Leakage Dominant Technologies Man L Mui Kaustav Banerjee Amit Mehrotra

    E-print Network

    Power Supply Optimization in Sub-130 nm Leakage Dominant Technologies Man L Mui Kaustav Banerjee a methodology for systematically optimizing the power supply voltage for maximizing the performance of VLSI cir- cuits in technologies where leakage power is not an insignificant fraction of the total power

  13. A radiation-hardened 32-bit microprocessor based on the commercial CMOS process

    SciTech Connect

    Yoshioka, Shinichi; Kamimura, Hiroshi; Akiyama, Masatsugu; Nakamura, Mitsuhiro; Tamura, Takashi; Kuboyama, Satoshi

    1994-12-01

    A radiation-hardened 32-bit microprocessor based on the commercial CMOS process, usable up to 1 kGy(Si), has been developed by (1) adding a silicon nitride passivation layer and (2) thinning the field oxide. Both techniques suppress the leakage current generated by the parasitic MOSFET, because its negative threshold voltage shift due to oxide trapped holes is decreased by the latter, and compensated by the positive shift due to the interface states generated during irradiation of hydrogen trapped in the oxide through the silicon-nitride deposition. The samples supplied with 4.5 V and 20 MHz clock were able to operate normally up to the total dose of 1.3 kGy(Si). The total dose tolerance of the samples was over 20 times as much as that of ones based on the commercial process.

  14. Micro ethanol sensors with a heater fabricated using the commercial 0.18 ?m CMOS process.

    PubMed

    Liao, Wei-Zhen; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 µm complementary metal oxide semiconductor (CMOS) process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm. PMID:24072022

  15. Commercial CMOS image sensors as X-ray imagers and particle beam monitors

    NASA Astrophysics Data System (ADS)

    Castoldi, A.; Guazzoni, C.; Maffessanti, S.; Montemurro, G. V.; Carraresi, L.

    2015-01-01

    CMOS image sensors are widely used in several applications such as mobile handsets webcams and digital cameras among others. Furthermore they are available across a wide range of resolutions with excellent spectral and chromatic responses. In order to fulfill the need of cheap systems as beam monitors and high resolution image sensors for scientific applications we exploited the possibility of using commercial CMOS image sensors as X-rays and proton detectors. Two different sensors have been mounted and tested. An Aptina MT9v034, featuring 752 × 480 pixels, 6?m × 6?m pixel size has been mounted and successfully tested as bi-dimensional beam profile monitor, able to take pictures of the incoming proton bunches at the DeFEL beamline (1-6 MeV pulsed proton beam) of the LaBeC of INFN in Florence. The naked sensor is able to successfully detect the interactions of the single protons. The sensor point-spread-function (PSF) has been qualified with 1MeV protons and is equal to one pixel (6 mm) r.m.s. in both directions. A second sensor MT9M032, featuring 1472 × 1096 pixels, 2.2 × 2.2 ?m pixel size has been mounted on a dedicated board as high-resolution imager to be used in X-ray imaging experiments with table-top generators. In order to ease and simplify the data transfer and the image acquisition the system is controlled by a dedicated micro-processor board (DM3730 1GHz SoC ARM Cortex-A8) on which a modified LINUX kernel has been implemented. The paper presents the architecture of the sensor systems and the results of the experimental measurements.

  16. Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm

    E-print Network

    Hillman, Dan

    2011-01-01

    At 130 nm and 90 nm, power consumption (both dynamic and static) has become a barrier in the roadmap for SoC designs targeting battery powered, mobile applications. This paper presents the results of dynamic and static power reduction achieved implementing Tensilica's 32-bit Xtensa microprocessor core, using Virtual Silicon's Power Management IP. Independent voltage islands are created using Virtual Silicon's VIP PowerSaver standard cells by using voltage level shifting cells and voltage isolation cells to implement power islands. The VIP PowerSaver standard cells are characterized at 1.2V, 1.0V and 0.8V, to accommodate voltage scaling. Power islands can also be turned off completely. Designers can significantly lower both the dynamic power and the quiescent or leakage power of their SoC designs, with very little impact on speed or area using Virtual Silicon's VIP Gate Bias standard cells.

  17. Radiation-enhanced gate-induced-drain-leakage current in the 130 nm partially-depleted SOI pMOSFET

    NASA Astrophysics Data System (ADS)

    Peng, Chao; Hu, Zhiyuan; Ning, Bingxu; Dai, Lihua; Bi, Dawei; Zhang, Zhengxuan

    2015-04-01

    The total ionizing dose (TID) effect of the pMOSFET from 130 nm partially-depleted silicon-on-insulator (PDSOI) is investigated. The data obtained from 60Co ?-ray irradiation experiments indicate that input/output (I/O) device is more susceptible to TID effect than the core device. An anomalous off-state leakage increase is observed for I/O pMOSFET when drain is biased at a high voltage after irradiation. It is proved that this radiation-induced leakage relates to the enhanced gate-induce-drain-leakage (GIDL). Both the radiation-induced interface traps at the gate-oxide/body interface and the oxide trapped charges in the buried oxide (BOX) are responsible for the growth of the leakage current. These conclusions are also verified by the TCAD simulations. The isothermal annealing can recover the leakage current to the pre-irradiation level.

  18. A Single-Chip 630 GHz Transmitter with 210 GHz Sub-Harmonic PLL Local Oscillator in 130 nm InP HBT

    E-print Network

    Rodwell, Mark J. W.

    A Single-Chip 630 GHz Transmitter with 210 GHz Sub-Harmonic PLL Local Oscillator in 130 nm InP HBT) and heterojunction bipolar transistors (HBTs) [1-4]. For compact, low-power THz radio systems, single-chiprd-order Sub-harm. Mixer LO buffer amp. Fig. 1. 630 GHz single-chip transmitter

  19. An acetone microsensor with a ring oscillator circuit fabricated using the commercial 0.18 ?m CMOS process.

    PubMed

    Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

    2014-01-01

    This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is ?-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the ?-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm. PMID:25036331

  20. Charge pump design in 130 nm SiGe BiCMOS technology for low-noise fractional-N PLLs

    NASA Astrophysics Data System (ADS)

    Kucharski, M.; Herzel, F.

    2015-11-01

    This paper presents a numerical comparison of charge pumps (CP) designed for a high linearity and a low noise to be used in a fractional-N phase-locked loop (PLL). We consider a PLL architecture, where two parallel CPs with DC offset are used. The CP for VCO fine tuning is biased at the output to keep the VCO gain constant. For this specific architecture, only one transistor per CP is relevant for phase detector linearity. This can be an nMOSFET, a pMOSFET or a SiGe HBT, depending on the design. The HBT-based CP shows the highest linearity, whereas all charge pumps show similar device noise. An internal supply regulator with low intrinsic device noise is included in the design optimization.

  1. Radiation Characteristics of a 0.11 Micrometer Modified Commercial CMOS Process

    NASA Technical Reports Server (NTRS)

    Poivey, Christian; Kim, Hak; Berg, Melanie D.; Forney, Jim; Seidleck, Christina; Vilchis, Miguel A.; Phan, Anthony; Irwin, Tim; LaBel, Kenneth A.; Saigusa, Rajan K.; Mirabedini, Mohammad R.; Finlinson, Rick; Suvkhanov, Agajan; Hornback, Verne; Sung, Jun; Tung, Jeffrey

    2006-01-01

    We present radiation data, Total Ionizing Dose and Single Event Effects, on the LSI Logic 0.11 micron commercial process and two modified versions of this process. Modified versions include a buried layer to guarantee Single Event Latchup immunity.

  2. A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems.

    PubMed

    Zheng, Xuezhe; Liu, Frankie; Patil, Dinesh; Thacker, Hiren; Luo, Ying; Pinguet, Thierry; Mekis, Attila; Yao, Jin; Li, Guoliang; Shi, Jing; Raj, Kannan; Lexau, Jon; Alon, Elad; Ho, Ron; Cunningham, John E; Krishnamoorthy, Ashok V

    2010-01-01

    We report ultra-low-power (690fJ/bit) operation of an optical receiver consisting of a germanium-silicon waveguide detector intimately integrated with a receiver circuit and embedded in a clocked digital receiver. We show a wall-plug power efficiency of 690microW/Gbps for the photonic receiver made of a 130nm SOI CMOS Ge waveguide detector integrated to a 90nm Si CMOS receiver circuit. The hybrid CMOS photonic receiver achieved a sensitivity of -18.9dBm at 5Gbps for BER of 10(-12). Enabled by a unique low-overhead bias refresh scheme, the receiver operates without the need for DC balanced transmission. Small signal measurements of the CMOS Ge waveguide detector showed a 3dB bandwidth of 10GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit will be possible. PMID:20173840

  3. High-temperature Complementary Metal Oxide Semiconductors (CMOS)

    NASA Technical Reports Server (NTRS)

    Mcbrayer, J. D.

    1981-01-01

    The results of an investigation into the possibility of using complementary metal oxide semiconductor (CMOS) technology for high temperature electronics are presented. A CMOS test chip was specifically developed as the test bed. This test chip incorporates CMOS transistors that have no gate protection diodes; these diodes are the major cause of leakage in commercial devices.

  4. Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor/System-on-a-Chip

    NASA Technical Reports Server (NTRS)

    Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

    2015-01-01

    Hardness assurance test results of Intel state-of-the-art 14nm “Broadwell” U-series processor / System-on-a-Chip (SoC) for total ionizing dose (TID) are presented, along with exploratory results from trials at a medical proton facility. Test method builds upon previous efforts [1] by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

  5. Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor - System-on-a-Chip

    NASA Technical Reports Server (NTRS)

    Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

    2015-01-01

    Hardness assurance test results of Intel state-of-the-art 14nm Broadwell U-series processor System-on-a-Chip (SoC) for total dose are presented, along with first-look exploratory results from trials at a medical proton facility. Test method builds upon previous efforts by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

  6. A CMOS readout circuit for microstrip detectors

    NASA Astrophysics Data System (ADS)

    Nasri, B.; Fiorini, C.

    2015-03-01

    In this work, we present the design and the results of a CMOS analog channel for silicon microstrips detectors. The readout circuit was initially conceived for the outer layers of the SuperB silicon vertex tracker (SVT), but can serve more generally other microstrip-based detection systems. The strip detectors considered show a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been investigated. The ASIC is composed by a preamplifier, shaping amplifier and a Time over Threshold (T.o.T) block for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit includes the possibility to select the peaking time of the shaper output from four values: 250 ns, 375 ns, 500 ns and 750 ns. In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The ASIC prototype has been fabricated in the 130 nm IBM technology which is considered intrinsically radiation hard. The results of the experimental characterization of a produced prototype are satisfactorily matched with simulation.

  7. Planarization of a CMOS die for an integrated metal MEMS Hocheol Lee*, Michele H. Miller+

    E-print Network

    Bifano, Thomas

    the commercial foundry processes of the silicon MEMS are generally incompatible with prefabricated CMOSPlanarization of a CMOS die for an integrated metal MEMS Hocheol Lee*, Michele H. Miller+ , Thomas a flat CMOS die surface for the integration of a MEMS metal mirror array. The CMOS die for our device

  8. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    PubMed Central

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-01-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18?um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

  9. Improving CMOS-compatible Germanium photodetectors.

    PubMed

    Li, Guoliang; Luo, Ying; Zheng, Xuezhe; Masini, Gianlorenzo; Mekis, Attila; Sahni, Subal; Thacker, Hiren; Yao, Jin; Shubin, Ivan; Raj, Kannan; Cunningham, John E; Krishnamoorthy, Ashok V

    2012-11-19

    We report design improvements for evanescently coupled Germanium photodetectors grown at low temperature. The resulting photodetectors with 10 ?m Ge length manufactured in a commercial CMOS process achieve >0.8 A/W responsivity over the entire C-band, with a device capacitance of <7 fF based on measured data. PMID:23187489

  10. The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector

    NASA Astrophysics Data System (ADS)

    Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.

    2013-12-01

    This work presents the characterization of Deep N-well (DNW) active pixel sensors fabricated in a vertically integrated technology. The DNW approach takes advantage of the triple well structure to lay out a sensor with relatively large charge collecting area (as compared to standard three transistor MAPS), while the readout is performed by a classical signal processing chain for capacitive detectors. This new 3D design relies upon stacking two homogeneous tiers fabricated in a 130 nm CMOS process where the top tier is thinned down to about 12 ?m to expose through silicon vias (TSV), therefore making connection to the buried circuits possible. This technology has been used to design a fine pitch 3D CMOS sensor with sparsification capabilities, in view of vertexing applications to the International Linear Collider (ILC) experiments. Results from the characterization of different kind of test structures, including single pixels, 3×3 and 8×8 matrices, are presented.

  11. Planarization of a CMOS die for an integrated metal MEMS

    NASA Astrophysics Data System (ADS)

    Lee, Hocheol; Miller, Michele H.; Bifano, Thomas G.

    2003-01-01

    This paper describes a planarization procedure to achieve a flat CMOS die surface for the integration of a MEMS metal mirror array. The CMOS die for our device is 4 mm × 4 mm and comes from a commercial foundry. The initial surface topography has 0.9 ?m bumps from the aluminum interconnect patterns that are used for addressing the individual micro mirror array elements. To overcome the tendency for tilt error in the planarization of the small CMOS die, our approach is to sputter a thick layer of silicon nitride (2.2 ?m) at low temperature and to surround the CMOS die with dummy pieces to define the polishing plane. The dummy pieces are first lapped down to the height of the CMOS die, and then all pieces are polished. This process reduces the 0.9 ?m height of the bumps to less than 25 nm.

  12. Ion traps fabricated in a CMOS foundry

    NASA Astrophysics Data System (ADS)

    Mehta, K. K.; Eltony, A. M.; Bruzewicz, C. D.; Chuang, I. L.; Ram, R. J.; Sage, J. M.; Chiaverini, J.

    2014-07-01

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  13. Ion traps fabricated in a CMOS foundry

    E-print Network

    Mehta, K K; Bruzewicz, C D; Chuang, I L; Ram, R J; Sage, J M; Chiaverini, J

    2014-01-01

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, in any modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  14. Ion traps fabricated in a CMOS foundry

    E-print Network

    K. K. Mehta; A. M. Eltony; C. D. Bruzewicz; I. L. Chuang; R. J. Ram; J. M. Sage; J. Chiaverini

    2014-06-13

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, in any modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  15. Ion traps fabricated in a CMOS foundry

    SciTech Connect

    Mehta, K. K.; Ram, R. J.; Eltony, A. M.; Chuang, I. L.; Bruzewicz, C. D.; Sage, J. M. Chiaverini, J.

    2014-07-28

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  16. Stacked CMOS SRAM cell

    NASA Astrophysics Data System (ADS)

    Chen, C.-E.; Lam, H. W.; Malhi, S. D. S.; Pinizzotto, R. F.

    1983-08-01

    A static random access memory (SRAM) cell with cross-coupled stacked CMOS inverters is demonstrated for the first time. In this approach, CMOS inverters are fabricated with a laser recrystallized p-channel device stacked on top of and sharing the gate with a bulk n-channel device using a modified two-polysilicon n-MOS process. The memory cell has been exercised through the write and read cycles with external signal generators while the output is buffered by an on-chip, stacked-CMOS-inverter-based amplifier.

  17. All-CMOS night vision viewer with integrated microdisplay

    NASA Astrophysics Data System (ADS)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

    2014-02-01

    The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 ?m CMOS process, with no process alterations or post processing. The display features a 25 ?m pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

  18. Monolithic CMUT on CMOS Integration for Intravascular Ultrasound Applications

    PubMed Central

    Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F. Levent

    2012-01-01

    One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array. PMID:23443701

  19. CMOS MEMS capacitive absolute pressure sensor

    NASA Astrophysics Data System (ADS)

    Narducci, M.; Yu-Chia, L.; Fang, W.; Tsai, J.

    2013-05-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal-oxide-semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa-1 in the pressure range of 0-300 kPa.

  20. CHARACTERIZATION OF A CMOS SENSING CORE FOR ULTRA-MINIATURE WIRELESS IMPLANTABLE TEMPERATURE SENSORS WITH APPLICATION TO CRYOMEDICINE

    PubMed Central

    Khairi, Ahmad; Thaokar, Chandrajit; Fedder, Gary; Paramesh, Jeyanandh; Rabin, Yoed

    2014-01-01

    In effort to improve thermal control in minimally invasive cryosurgery, the concept of a miniature, wireless, implantable sensing unit has been developed recently. The sensing unit integrates a wireless power delivery mechanism, wireless communication means, and a sensing core—the subject matter of the current study. The current study presents a CMOS ultra-miniature PTAT temperature sensing core and focuses on design principles, fabrication of a proof-of-concept, and characterization in a cryogenic environment. For this purpose, a 100?m × 400?m sensing core prototype has been fabricated using a 130nm CMOS process. The senor has shown to operate between ?180°C and room temperature, to consume power of less than 1?W, and to have an uncertainty range of 1.4°C and non-linearity of 1.1%. Results of this study suggest that the sensing core is ready to be integrated in the sensing unit, where system integration is the subject matter of a parallel effort. PMID:25001173

  1. CCD and CMOS sensors

    NASA Astrophysics Data System (ADS)

    Waltham, Nick

    The charge-coupled device (CCD) has been developed primarily as a compact image sensor for consumer and industrial markets, but is now also the preeminent visible and ultraviolet wavelength image sensor in many fields of scientific research including space-science and both Earth and planetary remote sensing. Today"s scientific or science-grade CCD will strive to maximise pixel count, focal plane coverage, photon detection efficiency over the broadest spectral range and signal dynamic range whilst maintaining the lowest possible readout noise. The relatively recent emergence of complementary metal oxide semiconductor (CMOS) image sensor technology is arguably the most important development in solid-state imaging since the invention of the CCD. CMOS technology enables the integration on a single silicon chip of a large array of photodiode pixels alongside all of the ancillary electronics needed to address the array and digitise the resulting analogue video signal. Compared to the CCD, CMOS promises a more compact, lower mass, lower power and potentially more radiation tolerant camera.

  2. CMOS chip planarization by chemical mechanical polishing for a vertically stacked metal MEMS integration

    NASA Astrophysics Data System (ADS)

    Lee, Hocheol; Miller, Michele H.; Bifano, Thomas G.

    2004-01-01

    In this paper we present the planarization process of a CMOS chip for the integration of a microelectromechanical systems (MEMS) metal mirror array. The CMOS chip, which comes from a commercial foundry, has a bumpy passivation layer due to an underlying aluminum interconnect pattern (1.8 µm high), which is used for addressing individual micromirror array elements. To overcome the tendency for tilt error in the CMOS chip planarization, the approach is to sputter a thick layer of silicon nitride at low temperature and to surround the CMOS chip with dummy silicon pieces that define a polishing plane. The dummy pieces are first lapped down to the height of the CMOS chip, and then all pieces are polished. This process produced a chip surface with a root-mean-square flatness error of less than 100 nm, including tilt and curvature errors.

  3. Monolithic CMUT-on-CMOS integration for intravascular ultrasound applications.

    PubMed

    Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F Levent

    2011-12-01

    One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter-based volumetric imaging arrays, for which the elements must be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom-designed CMOS receiver electronics from a commercial IC foundry. The CMUT-on-CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low-temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT-to-CMOS interconnection. This CMUT-to-CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire-bonding method. Characterization experiments indicate that the CMUT-on-CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Ex- periments on a 1.6-mm-diameter dual-ring CMUT array with a center frequency of 15 MHz show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging chronic total occlusions located 1 cm from the CMUT array. PMID:23443701

  4. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    PubMed Central

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  5. Mitigating Defective CMOS to Non-CMOS Vias in CMOS/Molecular Memories

    E-print Network

    of Technology, The Netherlands 2. Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia that promises increased data storage, reduced power consumption and minimized fabrication complexity. The fabrication of these memories is based on the stacking of non-CMOS-based memory cell array on the top of CMOS

  6. DNA decorated carbon nanotube sensors on CMOS circuitry for environmental monitoring

    NASA Astrophysics Data System (ADS)

    Liu, Yu; Chen, Chia-Ling; Agarwal, V.; Li, Xinghui; Sonkusale, S.; Dokmeci, Mehmet R.; Wang, Ming L.

    2010-04-01

    Single-walled carbon nanotubes (SWNTs) with their large surface area, high aspect ratio are one of the novel materials which have numerous attractive features amenable for high sensitivity sensors. Several nanotube based sensors including, gas, chemical and biosensors have been demonstrated. Moreover, most of these sensors require off chip components to detect the variations in the signals making them complicated and hard to commercialize. Here we present a novel complementary metal oxide semiconductor (CMOS) integrated carbon nanotube sensors for portable high sensitivity chemical sensing applications. Multiple zincation steps have been developed to ascertain proper electrical connectivity between the carbon nanotubes and the foundry made CMOS circuitry. The SWNTs have been integrated onto (CMOS) circuitry as the feedback resistor of a Miller compensated operational amplifier utilizing low temperature Dielectrophoretic (DEP) assembly process which has been tailored to be compatible with the post-CMOS integration at the die level. Building nanotube sensors directly on commercial CMOS circuitry allows single chip solutions eliminating the need for long parasitic lines and numerous wire bonds. The carbon nanotube sensors realized on CMOS circuitry show strong response to various vapors including Dimethyl methylphosphonate and Dinitrotoluene. The remarkable set of attributes of the SWNTs realized on CMOS electronic chips provides an attractive platform for high sensitivity portable nanotube based bio and chemical sensors.

  7. High-speed graphene interconnects monolithically integrated with CMOS ring oscillators operating at 1.3GHz

    E-print Network

    Chen, Xiangyu

    We have successfully experimentally integrated graphene interconnects with commercial 0.25 ¿m technology CMOS ring oscillator circuit using conventional fabrication techniques, and demonstrated high speed on-chip graphene ...

  8. Fully CMOS analog and digital SiPMs

    NASA Astrophysics Data System (ADS)

    Zou, Yu; Villa, Federica; Bronzi, Danilo; Tisa, Simone; Tosi, Alberto; Zappa, Franco

    2015-03-01

    Silicon Photomultipliers (SiPMs) are emerging single photon detectors used in many applications requiring large active area, photon-number resolving capability and immunity to magnetic fields. We present three families of analog SiPM fabricated in a reliable and cost-effective fully standard planar CMOS technology with a total photosensitive area of 1×1 mm2. These three families have different active areas with fill-factors (21%, 58.3%, 73.7%) comparable to those of commercial SiPM, which are developed in vertical (current flow) custom technologies. The peak photon detection efficiency in the near-UV tops at 38% (fill-factor included) comparable to commercial custom-process ones and dark count rate density is just a little higher than the best-in-class commercial analog SiPMs. Thanks to the CMOS processing, these new SiPMs can be integrated together with active components and electronics both within the microcell and on-chip, in order to act at the microcell level or to perform global pre-processing. We also report CMOS digital SiPMs in the same standard CMOS technology, based on microcells with digitalized processing, all integrated on-chip. This CMOS digital SiPMs has four 32×1 cells (128 microcells), each consisting of SPAD, active quenching circuit with adjustable dead time, digital control (to switch off noisy SPADs and readout position of detected photons), and fast trigger output signal. The achieved 20% fill-factor is still very good.

  9. Regenerative switching CMOS system

    DOEpatents

    Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

    1998-01-01

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

  10. Regenerative switching CMOS system

    DOEpatents

    Welch, J.D.

    1998-06-02

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

  11. CMOS-Based Biosensor Arrays

    E-print Network

    Thewes, R; Schienle, M; Hofmann, F; Frey, A; Brederlow, R; Augustyniak, M; Jenkner, M; Eversmann, B; Schindler-Bauer, P; Atzesberger, M; Holzapfl, B; Beer, G; Haneder, T; Hanke, H -C

    2011-01-01

    CMOS-based sensor array chips provide new and attractive features as compared to today's standard tools for medical, diagnostic, and biotechnical applications. Examples for molecule- and cell-based approaches and related circuit design issues are discussed.

  12. Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

    PubMed Central

    Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

    2010-01-01

    This work presents a thermoelectric micro generator fabricated by the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 ?V at the temperature difference of 1 K. PMID:22205869

  13. Fabrication and characterization of CMOS-MEMS thermoelectric micro generators.

    PubMed

    Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

    2010-01-01

    This work presents a thermoelectric micro generator fabricated by the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 ?V at the temperature difference of 1 K. PMID:22205869

  14. Design and fabrication of a CMOS MEMS logic gate

    NASA Astrophysics Data System (ADS)

    Tsai, Chun-Yin; Chen, Tsung-Lin; Liao, Hsin-Hao; Lin, Chen-Fu; Juang, Ying-Zong

    2011-03-01

    This study aims to develop a novel CMOS-MEMS logic gate via commercially available CMOS process (TSMC, 2P4M®). Compared to existing CMOS MEMS designs, which uses foundry processes, the proposed design imposes several new challenges including: carrying two voltage levels on a non-warping suspended plate, metal-to- metal contact, and etc. Different combinations of oxide-metal films and post-CMOS process are investigated to achieve a non-warping suspended structure layer. And different wet etchants are investigated to remove sacrificial layers without attacking structure layers and features. In a prototype design, the selected structure layer is metal-3 and oxide film; the device is released using AD-10 and titanium etchant; the device is 250 ?m long, 100 ?m wide, and 1.5 ?m gap. The experimental results show that the suspended plate slightly curls down 0.485 ?m. This device can be actuated by 10/0 V with a moving distance 50nm. The resonant frequency is measured at 36 kHz. Due to the damage of the tungsten plugs, the logic function can only be verified by its mechanical movements instead of electrical readouts for now.

  15. CMOS passive pixel image design techniques

    E-print Network

    Fujimori, Iliana L. (Iliana Lucia)

    2002-01-01

    CMOS technology provides an attractive alternative to the currently dominant CCD technology for implementing low-power, low-cost imagers with high levels of integration. Two pixel configurations are possible in CMOS ...

  16. MonoColor CMOS sensor

    NASA Astrophysics Data System (ADS)

    Wang, Ynjiun P.

    2009-02-01

    A new breed of CMOS color sensor called MonoColor sensor is developed for a barcode reading application in AIDC industry. The RGBW color filter array (CFA) in a MonoColor sensor is arranged in a 8 x 8 pixels CFA with only 4 pixels of them are color (RGB) pixels and the rest of 60 pixels are transparent or monochrome. Since the majority of pixels are monochrome, MonoColor sensor maintains 98% barcode decode performance compared with a pure monochrome CMOS sensor. With the help of monochrome and color pixel fusion technique, the resulting color pictures have similar color quality in terms of Color Semantic Error (CSE) compared with a Bayer pattern (RGB) CMOS color camera. Since monochrome pixels are more sensitive than color pixels, a MonoColor sensor produces in general about 2X brighter color picture and higher luminance pixel resolution.

  17. CMOS Integrated Carbon Nanotube Sensor

    SciTech Connect

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

    2009-05-23

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  18. A back-illuminated megapixel CMOS image sensor

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

    2005-01-01

    In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

  19. A CMOS enhanced solid-state nanopore based single molecule detection platform.

    PubMed

    Chen, Chinhsuan; Yemenicioglu, Sukru; Uddin, Ashfaque; Corgliano, Ellie; Theogarajan, Luke

    2013-01-01

    Solid-state nanopores have emerged as a single molecule label-free electronic detection platform. Existing transimpedance stages used to measure ionic current nanopores suffer from dynamic range limitations resulting from steady-state baseline currents. We propose a digitally-assisted baseline cancellation CMOS platform that circumvents this issue. Since baseline cancellation is a form of auto-zeroing, the 1/f noise of the system is also reduced. Our proposed design can tolerate a steady state baseline current of 10µA and has a usable bandwidth of 750kHz. Quantitative DNA translocation experiments on 5kbp DNA was performed using a 5nm silicon nitride pore using both the CMOS platform and a commercial system. Comparison of event-count histograms show that the CMOS platform clearly outperforms the commercial system, allowing for unambiguous interpretation of the data. PMID:24109650

  20. A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.

    PubMed

    Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

    2011-01-01

    This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 ?m CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 ?m CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

  1. Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units

    SciTech Connect

    Smith, J.H.; Ellis, J.R.; Montague, S.; Allen, J.J.

    1997-03-01

    One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing. In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.

  2. Integration of solid-state nanopores in a 0.5 ?m CMOS foundry process

    NASA Astrophysics Data System (ADS)

    Uddin, A.; Yemenicioglu, S.; Chen, C.-H.; Corigliano, E.; Milaninia, K.; Theogarajan, L.

    2013-04-01

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

  3. Integration of solid-state nanopores in a 0.5 ?m cmos foundry process

    PubMed Central

    Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

    2013-01-01

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 ?m technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp ?-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

  4. Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits1, 2

    E-print Network

    Pedram, Massoud

    current of a CMOS circuit. In both cases, it is assumed that the system or environment produces a "sleep, the "sleep" signal is used to shift in a new set of external inputs and pre-selected internal signals or commercial advantage and that copies bear this notice and the full citation on the first page. To copy

  5. Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

    NASA Technical Reports Server (NTRS)

    Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

    2012-01-01

    Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

  6. CMOS foveal image sensor chip

    NASA Technical Reports Server (NTRS)

    Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

    2002-01-01

    A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

  7. Nanosecond monolithic CMOS readout cell

    DOEpatents

    Souchkov, Vitali V.

    2004-08-24

    A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

  8. CMOS Imaging Detectors as X-ray Detectors for Synchrotron Radiation Experiments

    SciTech Connect

    Yagi, Naoto; Uesugi, Kentaro; Inoue, Katsuaki

    2004-05-12

    CMOS imagers are matrix-addressed photodiode arrays, which have been utilized in devices such as commercially available digital cameras. The pixel size of CMOS imagers is usually larger than that of CCD and smaller than that of TFT, giving them a unique position. Although CMOS x-ray imaging devices have already become commercially available, they have not been used as an x-ray area detector in synchrotron radiation experiments. We tested performance of a CMOS detector from Rad-icon (Shad-o-Box1024) in medical imaging, small-angle scattering, and protein crystallography experiments. It has pixels of 0.048 mm square, read-out time of 0.45 sec, 12-bit ADC, and requires a frame grabber for image acquisition. The detection area is 5-cm square. It uses a Kodak Min-R scintillator screen as a phosphor. The sensitivity to x-rays with an energy less than 15 keV was low because of the thick window materials. Since the readout noise is high, the dynamic range is limited to 2000. The biggest advantages of this detector are cost-effectiveness (about 10,000 US dollars) and compactness (thickness < 3 cm, weight < 2 kg)

  9. A 32 x 32 capacitive micromachined ultrasonic transducer array manufactured in standard CMOS.

    PubMed

    Lemmerhirt, David F; Cheng, Xiaoyang; White, Robert; Rich, Collin A; Zhang, Man; Fowlkes, J Brian; Kripfgans, Oliver D

    2012-07-01

    As ultrasound imagers become increasingly portable and lower cost, breakthroughs in transducer technology will be needed to provide high-resolution, real-time 3-D imaging while maintaining the affordability needed for portable systems. This paper presents a 32 x 32 ultrasound array prototype, manufactured using a CMUT-in-CMOS approach whereby ultrasonic transducer elements and readout circuits are integrated on a single chip using a standard integrated circuit manufacturing process in a commercial CMOS foundry. Only blanket wet-etch and sealing steps are added to complete the MEMS devices after the CMOS process. This process typically yields better than 99% working elements per array, with less than ±1.5 dB variation in receive sensitivity among the 1024 individually addressable elements. The CMUT pulseecho frequency response is typically centered at 2.1 MHz with a -6 dB fractional bandwidth of 60%, and elements are arranged on a 250 ?m hexagonal grid (less than half-wavelength pitch). Multiplexers and CMOS buffers within the array are used to make on-chip routing manageable, reduce the number of physical output leads, and drive the transducer cable. The array has been interfaced to a commercial imager as well as a set of custom transmit and receive electronics, and volumetric images of nylon fishing line targets have been produced. PMID:22828847

  10. Low-loss and low-crosstalk 8 × 8 silicon nanowire AWG routers fabricated with CMOS technology.

    PubMed

    Wang, Jing; Sheng, Zhen; Li, Le; Pang, Albert; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Qi, Minghao; Gan, Fuwan

    2014-04-21

    Low-loss and low-crosstalk 8 × 8 arrayed waveguide grating (AWG) routers based on silicon nanowire waveguides are reported. A comparative study of the measurement results of the 3.2 nm-channel-spacing AWGs with three different designs is performed to evaluate the effect of each optimal technique, showing that a comprehensive optimization technique is more effective to improve the device performance than a single optimization. Based on the comprehensive optimal design, we further design and experimentally demonstrate a new 8-channel 0.8 nm-channel-spacing silicon AWG router for dense wavelength division multiplexing (DWDM) application with 130 nm CMOS technology. The AWG router with a channel spacing of 3.2 nm (resp. 0.8 nm) exhibits low insertion loss of 2.32 dB (resp. 2.92 dB) and low crosstalk of -20.5~-24.5 dB (resp. -16.9~-17.8 dB). In addition, sophisticated measurements are presented including all-input transmission testing and high-speed WDM system demonstrations for these routers. The functionality of the Si nanowire AWG as a router is characterized and a good cyclic rotation property is demonstrated. Moreover, we test the optical eye diagrams and bit-error-rates (BER) of the de-multiplexed signal when the multi-wavelength high-speed signals are launched into the AWG routers in a system experiment. Clear optical eye diagrams and low power penalty from the system point of view are achieved thanks to the low crosstalk of the AWG devices. PMID:24787827

  11. Resonant body transistors in standard CMOS technology

    E-print Network

    Marathe, Radhika A.

    This work presents Si-based electromechanical resonators fabricated at the transistor level of a standard SOI CMOS technology and realized without the need for any postprocessing or packaging. These so-called Resonant Body ...

  12. Ion traps fabricated in a CMOS foundry

    E-print Network

    Mehta, Karan Kartik

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process ...

  13. A CMOS-compatible compact display

    E-print Network

    Chen, Andrew R. (Andrew Raymond)

    2005-01-01

    Portable information devices demand displays with high resolution and high image quality that are increasingly compact and energy-efficient. Microdisplays consisting of a silicon CMOS backplane integrated with light ...

  14. CMOS analog switches for adaptive filters

    NASA Technical Reports Server (NTRS)

    Dixon, C. E.

    1980-01-01

    Adaptive active low-pass filters incorporate CMOS (Complimentary Metal-Oxide Semiconductor) analog switches (such as 4066 switch) that reduce variation in switch resistance when filter is switched to any selected transfer function.

  15. A CMOS smart temperature and humidity sensor with combined readout.

    PubMed

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-01-01

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 ?m CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA. PMID:25230305

  16. A CMOS Smart Temperature and Humidity Sensor with Combined Readout

    PubMed Central

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-01-01

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 ?m CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 ?A. PMID:25230305

  17. Radiation hardening of CMOS-based circuitry in SMART transmitters

    SciTech Connect

    Loescher, D.H. )

    1993-02-01

    Process control transmitters that incorporate digital signal processing could be used advantageously in nuclear power plants; however, because such transmitters are too sensitive to radiation, they are not used. The Electric Power Research Institute sponsored work at Sandia National Laboratories under EPRI contract RP2614-58 to determine why SMART transmitters fail when exposed to radiation and to design and demonstrate SMART transmitter circuits that could tolerate radiation. The term SMART'' denotes transmitters that contain digital logic. Tests showed that transmitter failure was caused by failure of the complementary metal oxide semiconductors (CMOS)-integrated circuits which are used extensively in commercial transmitters. Radiation-hardened replacements were not available for the radiation-sensitive CMOS circuits. A conceptual design showed that a radiation-tolerant transmitter could be constructed. A prototype for an analog-to-digital converter subsection worked satisfactorily after a total dose of 30 megarads(Si). Encouraging results were obtained from preliminary bench-top tests on a dc-to-dc converter for the power supply subsection.

  18. Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique.

    PubMed

    Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

    2009-01-01

    In this study we used the commercial 0.35 ?m CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz. PMID:22454581

  19. September 19, 2012 ASICs: Will We Reach 10 G Arrays?

    E-print Network

    Gan, K. K.

    .S. Smith The Ohio State University #12;K.K. Gan TWEPP2012 2 VCSEL Arrays Arrays with suitable Awaiting receipt of irradiated array driver ASIC and VCSEL to test operation at 5 Gb/s #12;K.K. Gan Gb/s VCSEL driver is possible using: 180 nm CMOS 130 nm BiCMOS 130 nm CMOS

  20. RF CMOS UWB transmitter and receiver front-end design 

    E-print Network

    Miao, Meng

    2009-05-15

    The low-cost low-power complementary metal-oxide semiconductor (CMOS) ultra wideband (UWB) transmitter and receiver front-ends based on impulse technology were developed. The CMOS UWB pulse generator with frequency-band tuning capability...

  1. Future of nano CMOS technology

    NASA Astrophysics Data System (ADS)

    Iwai, Hiroshi

    2015-10-01

    Although Si MOS devices have dominated the integrated circuit applications over the four decades, it has been anticipated that the development of CMOS would reach its limits after the next decade because of the difficulties in the technologies for further downscaling and also because of some fundamental limits of MOSFETs. However, there have been no promising candidates yet, which can replace Si MOSFETs with better performance with low cost. Thus, for the moment, it seems that we have to stick to the Si MOSFET devices until their end. The downsizing is limited by the increase of off-leakage current between source and drain. In order to suppress the off-leakage current, multi-gate structures (FinFET, Tri-gate, and Si-nanowire MOSFETs) are replacing conventional planar MOSFETs, and continuous innovation of high-k/metal gate technologies has enabled EOT scaling down to 0.9 nm in production. However, it was found that the multi-gate structures have a future big problem of significant conduction reduction with decrease in fin width. Also it is not easy to further decrease EOT because of the mobility and reliability degradation. Furthermore, the development of EUV (Extremely Ultra-Violet) lithography, which is supposed to be essential for sub-10 nm lithography, delays significantly because of insufficient illumination intensity for production. Thus, it is now expected that the reduction rate of the gate length, which has a strong influence on the off-leakage current, will become slower in near future.

  2. A Standard CMOS Humidity Sensor without Post-Processing

    PubMed Central

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2011-01-01

    A 2 ?W power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023–10 humidity-sensitive layer, and a CMOS capacitance to voltage converter. PMID:22163949

  3. Soft-Error Hardening Designs of Nanoscale CMOS Latches

    E-print Network

    Ayers, Joseph

    superior performance in terms of power-delay product as well as highest tolerance to soft errors (measured the predictive technology file for 32nm feature size in CMOS. Index Terms: Hardening, Soft Error, Nano CMOS ISoft-Error Hardening Designs of Nanoscale CMOS Latches Sheng Lin, Yong-Bin Kim and Fabrizio

  4. CMOS Photovoltaic-cell Layout Configurations for Harvesting Microsystems

    E-print Network

    Rincon-Mora, Gabriel A.

    CMOS Photovoltaic-cell Layout Configurations for Harvesting Microsystems Rajiv Damodaran Prabha, and radiation, photovoltaic (PV) systems are appealing options. Still, chip-sized CMOS PV cells produce only well in substrate cell are better. Index Terms--Ambient light energy, harvester, CMOS photovoltaic (PV

  5. Low power, CMOS digital autocorrelator spectrometer for spaceborne applications

    NASA Technical Reports Server (NTRS)

    Chandra, Kumar; Wilson, William J.

    1992-01-01

    A 128-channel digital autocorrelator spectrometer using four 32 channel low power CMOS correlator chips was built and tested. The CMOS correlator chip uses a 2-bit multiplication algorithm and a full-custom CMOS VLSI design to achieve low DC power consumption. The digital autocorrelator spectrometer has a 20 MHz band width, and the total DC power requirement is 6 Watts.

  6. Prototype Active Silicon Sensor in 150 nm HR-CMOS Technology for ATLAS Inner Detector Upgrade

    E-print Network

    Rymaszewski, Piotr; Breugnon, Patrick; Godiot, Stépahnie; Gonella, Laura; Hemperek, Tomasz; Hirono, Toko; Hügging, Fabian; Krüger, Hans; Liu, Jian; Pangaud, Patrick; Peric, Ivan; Rozanov, Alexandre; Wang, Anqing; Wermes, Norbert

    2016-01-01

    The LHC Phase-II upgrade will lead to a significant increase in luminosity, which in turn will bring new challenges for the operation of inner tracking detectors. A possible solution is to use active silicon sensors, taking advantage of commercial CMOS technologies. Currently ATLAS R&D programme is qualifying a few commercial technologies in terms of suitability for this task. In this paper a prototype designed in one of them (LFoundry 150 nm process) will be discussed. The chip architecture will be described, including different pixel types incorporated into the design, followed by simulation and measurement results.

  7. Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

    PubMed Central

    Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

    2011-01-01

    The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

  8. Dark Current Characterization of the CMOS APS Imagers with Test Patterns Fabricated Using a 0.18 CMOS Technology

    E-print Network

    Lee, Jong Duk

    are downscaled to deep sub micron eras, it becomes more difficult to fabricate the low dark current imagers-micron CMOS technology. To implement the low dark current CMOS APS with a deep sub-micron technology#12;Dark Current Characterization of the CMOS APS Imagers with Test Patterns Fabricated Using a 0

  9. Region-of-interest cone beam computed tomography (ROI CBCT) with a high resolution CMOS detector

    NASA Astrophysics Data System (ADS)

    Jain, A.; Takemoto, H.; Silver, M. D.; Nagesh, S. V. S.; Ionita, C. N.; Bednarek, D. R.; Rudin, S.

    2015-03-01

    Cone beam computed tomography (CBCT) systems with rotational gantries that have standard flat panel detectors (FPD) are widely used for the 3D rendering of vascular structures using Feldkamp cone beam reconstruction algorithms. One of the inherent limitations of these systems is limited resolution (<3 lp/mm). There are systems available with higher resolution but their small FOV limits them to small animal imaging only. In this work, we report on region-of-interest (ROI) CBCT with a high resolution CMOS detector (75 ?m pixels, 600 ?m HR-CsI) mounted with motorized detector changer on a commercial FPD-based C-arm angiography gantry (194 ?m pixels, 600 ?m HL-CsI). A cylindrical CT phantom and neuro stents were imaged with both detectors. For each detector a total of 209 images were acquired in a rotational protocol. The technique parameters chosen for the FPD by the imaging system were used for the CMOS detector. The anti-scatter grid was removed and the incident scatter was kept the same for both detectors with identical collimator settings. The FPD images were reconstructed for the 10 cm x10 cm FOV and the CMOS images were reconstructed for a 3.84 cm x 3.84 cm FOV. Although the reconstructed images from the CMOS detector demonstrated comparable contrast to the FPD images, the reconstructed 3D images of the neuro stent clearly showed that the CMOS detector improved delineation of smaller objects such as the stent struts (~70 ?m) compared to the FPD. Further development and the potential for substantial clinical impact are suggested.

  10. Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

    NASA Astrophysics Data System (ADS)

    Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

    2014-03-01

    We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

  11. End-of-fabrication CMOS process monitor

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

    1990-01-01

    A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

  12. Optical addressing technique for a CMOS RAM

    NASA Technical Reports Server (NTRS)

    Wu, W. H.; Bergman, L. A.; Allen, R. A.; Johnston, A. R.

    1988-01-01

    Progress on optically addressing a CMOS RAM for a feasibility demonstration of free space optical interconnection is reported in this paper. The optical RAM chip has been fabricated and functional testing is in progress. Initial results seem promising. New design and SPICE simulation of optical gate cell (OGC) circuits have been carried out to correct the slow fall time of the 'weak pull down' OGC, which has been characterized experimentally. Methods of reducing the response times of the photodiodes and the associated circuits are discussed. Even with the current photodiode, it appears that an OGC can be designed with a performance that is compatible with a CMOS circuit such as the RAM.

  13. A 0.18?m CMOS low-power radiation sensor for UWB wireless transmission

    NASA Astrophysics Data System (ADS)

    Crepaldi, M.; Demarchi, D.; Gabrielli, A.; Khan, A.; Pikhay, E.; Roizin, Y.; Villani, G.; Zhang, Z.

    2012-12-01

    The paper describes the design of a floating gate MOS sensor embedded in a readout CMOS element, used as a radiation monitor. A maximum sensitivity of 1 mV/rad is estimated within an absorbed dose range from 1 to 10 krad. The paper shows in particular the design of a microelectronic circuit that includes the floating gate sensor, an oscillator, a modulator, a transmitter and an integrated antenna. A prototype of the circuit has recently been simulated, fabricated and tested exploiting a commercial 180 nm, 4 metal CMOS technology. Some simulation results are presented along with a measurement of the readout circuit response to an input voltage swing. Given the small estimated area of the complete chip prototype, that is less than 1 mm2, the chip fits a large variety of applications, from spot radiation monitoring systems in medicine to punctual measurements or radiation level in High-Energy Physics experiments.

  14. 30-Gb/s 90-nm CMOS-driven equalized multimode optical link.

    PubMed

    Hamel-Bissell, Brendan H; Proesel, Jonathan E; Lee, Benjamin G; Kuchta, Daniel M; Rylyakov, Alexander V; Schow, Clint L

    2013-05-01

    We report an 850-nm vertical cavity surface emitting laser (VCSEL)-based optical link that achieves a new record in speed. The laser driver and receiver ICs are fabricated in standard 90-nm bulk CMOS, and the optoelectronic devices are commercial components. Operation at 30 Gb/s with a bit-error rate < 10(-12) is achieved, representing to the authors' knowledge the highest speed reported to date for a CMOS-based full optical link. Transmitter feed-forward equalization is shown to improve maximum data rate from 25 to 30 Gb/s, timing margin by 17% at 23.5 Gb/s, and receiver sensitivity by 4 dB at 23.5 Gb/s. PMID:23669952

  15. A capacitor-free high PSR CMOS low dropout voltage regulator

    NASA Astrophysics Data System (ADS)

    Zhichao, Li; Yuntao, Liu; Zhangqu, Kuang; Jie, Chen

    2014-06-01

    This paper presents a capacitor-free CMOS low dropout voltage regulator which has high PSR performance and low chip area. Pole splitting and gm boosting techniques are employed to achieve good stability. The capacitor-free chip LDO was fabricated in commercial 0.18 ?m CMOS technology provided by GSMC (Shanghai, China). Measured results show that the capacitor-free LDO has a stable output voltage 1.79 V, when supply voltage changes from 2.5 to 5 V, and the LDO is capable of driving maximum 100 mA load current. The LDO has high power supply rejection about -79 dB at low frequency and -40 dB at 1 MHz frequency, while sacrifice of the LDO's active chip-area is only smaller than 0.02 mm2.

  16. CMOS Avalanche Radio-over-Fiber wchoi@yonsei.ac.kr

    E-print Network

    Choi, Woo-Young

    #12;#12;CMOS Avalanche Radio-over-Fiber , wchoi@yonsei.ac.kr CMOS Avalanche Photo-detector for Radio-over-Fiber Systems Yonsei Univ. 0.13um CMOS avalanche (avalanche photo-detector, APDF) [1-2]. RoF CMOS . CMOS GaAs responsivity . APD avalanche

  17. Low energy CMOS for space applications

    NASA Technical Reports Server (NTRS)

    Panwar, Ramesh; Alkalaj, Leon

    1992-01-01

    The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

  18. Battery-Powered Digital CMOS Massoud Pedram

    E-print Network

    Pedram, Massoud

    1 Page 1 USC Low Power CAD Massoud Pedram Battery-Powered Digital CMOS Design Massoud Pedram Power CAD Massoud Pedram Motivation Extending the battery service life of battery-powered micro- electronic devices is a primary design objective #12;2 Page 2 USC Low Power CAD Massoud Pedram Conventional

  19. CMOS Compatible Nanoscale Nonvolatile Resistance Switching

    E-print Network

    Cafarella, Michael J.

    CMOS Compatible Nanoscale Nonvolatile Resistance Switching Memory Sung Hyun Jo and Wei Lu studies on a nanoscale resistance switching memory structure based on planar silicon that is fully-terminal resistance switching devices show excellent scaling potential well beyond 10 Gb/cm2 and exhibit high yield

  20. CMOS preamplifiers for detectors large and small

    SciTech Connect

    O`Connor, P.

    1997-12-31

    We describe four CMOS preamplifiers developed for multiwire proportional chambers (MWPC) and silicon drift detectors (SDD) covering a capacitance range from 150 pF to 0.15 pF. Circuit techniques to optimize noise performance, particularly in the low-capacitance regime, are discussed.

  1. Radiation Tolerance of 65nm CMOS Transistors

    E-print Network

    M. Krohn; B. Bentele; J. P. Cumalat; S. R. Wagner; D. C. Christian; G. Deptuch; F. Fahim; J. Hoff; A. Shenai

    2015-11-24

    We report on the effects of ionizing radiation on 65nm CMOS transistors held at approximately -20C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

  2. Switch level optimization for CMOS circuits 

    E-print Network

    Chugh, Pankaj Pravinkumar

    1997-01-01

    In this report, 'Input vs Path Matrix 'Techique' and 'Node vs Input Matrix Technique' techniques for reducing transistor count in the pull-up and the pull-down array of CMOS circuits are proposed. Also, algorithms for optimization of both the pull...

  3. Baseband analog circuits in deep-submicron cmos technologies targeted for mobile multimedia 

    E-print Network

    Dhanasekaran, Vijayakumar

    2009-05-15

    load capacitance aware compensation for 3-stage amplifiers is presented. A class-AB 16W headphone driver designed using this scheme in 130nm technology is experimentally shown to handle 1pF to 22nF capacitive load while consuming as low as 1.2m...

  4. Silicon Deformable Mirrors and CMOS-based Wavefront Sensors Justin D. Mansell, Peter B. Catrysse, Eric K. Gustafson, and Robert L. Byer

    E-print Network

    Byer, Robert L.

    Silicon Deformable Mirrors and CMOS-based Wavefront Sensors Justin D. Mansell, Peter B. Catrysse potential commercial applications for adaptive optics like laser beam control and ophthalmology. Silicon have implemented a new architecture of silicon deformable mirror designed to be low cost, have low

  5. 77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-06-06

    ...Investigation No. 337-TA-846] Certain CMOS Image Sensors and Products Containing Same...States after importation of certain CMOS image sensors and products containing same by...States after importation of certain CMOS image sensors and products containing same...

  6. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-07

    ...COMMISSION [Docket No. 2895] Certain CMOS Image Sensors and Products Containing Same...received a complaint entitled Certain CMOS Image Sensors and Products Containing Same...States after importation of certain CMOS image sensors and products containing...

  7. SOI-CMOS-MEMS electrothermal micromirror arrays

    NASA Astrophysics Data System (ADS)

    Gilgunn, Peter J.

    A fabrication technology called SOI-CMOS-MEMS is developed to realize arrays of electrothermally actuated micromirror arrays with fill factors up to 90% and mechanical scan ranges up to +/-45°. SOI-CMOS-MEMS features bonding of a CMOS-MEMS folded electrothermal actuator chip with a SOI mirror chip. Actuators and micromirrors are separately released using Bosch-type and isotropic Si etch processes. A 1-D, 3 x 3 SOI-CMOS-MEMS mirror array is characterized at a 1 mm scale that meets fill factor and scan range targets with a power sensitivity of 1.9 deg·m W-1 and -0.9 deg·m W-1 on inner and outer actuator legs, respectively. Issues preventing fabrication of SOI-CMOS-MEMS micromirror arrays designed for 1-D and 3-D motion at scales from 500 microm to 50 microm are discussed. Electrothermomechanical analytic models of power response of a generic folded actuator topology are developed that provide insight into the trends in actuator behavior for actuator design elements such as beam geometry and heater type, among others. Adverse power and scan range scaling and favorable speed scaling are demonstrated. Mechanical constraints on device geometry are derived. Detailed material, process, test structure and device characterization is presented that demonstrates the consistency of measured device behavior with analytic models. A unified model for aspect ratio dependent etch modulation is developed that achieves depth prediction accuracy of better than 10% up to 160 microm depth over a range of feature shapes and dimensions. The technique is applied extensively in the SOI-CMOS-MEMS process to produce deep multi-level structures in Si with a single etch mask and to control uniformity and feature profiles. TiW attack during release etch is shown to be the driving factor in mirror coplanarity loss. The effect is due to thermally accelerated etching caused by heating of released structures by the exothermic reaction of Si and F. The effect is quantified using in situ infrared imaging. Models are developed that predict suspended device temperatures based on a power balance model using a single parameter, the proportion of etch heat carried away by volatile species, as the sole fitting parameter.

  8. Radiation characteristics of scintillator coupled CMOS APS for radiography conditions

    NASA Astrophysics Data System (ADS)

    Kim, Kwang Hyun; Kim, Soongpyung; Kang, Dong-Won; Kim, Dong-Kie

    2006-11-01

    Under industrial radiography conditions, we analyzed short-term radiation characteristics of scintillator coupled CMOS APS (hereinafter SC CMOS APS). By means of experimentation, the contribution of the transmitted X-ray through the scintillator to the properties of the CMOS APS and the afterimage, generated in the acquired image even at low dose condition, were investigated. To see the transmitted X-ray effects on the CMOS APS, Fein focus™ X-ray machine, two scintillators of Lanex™ Fine and Regular, and two CMOS APS array of RadEye™ were used under the conditions of 50 kV p/1 mAs and 100 kV p/1 mAs. By measuring the transmitted X-ray on signal and Noise Power Spectrum, we analytically examined the generation mechanism of the afterimage, based on dark signal or dark current increase in the sensor, and explained the afterimage in the SC CMOS APS.

  9. Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers

    NASA Astrophysics Data System (ADS)

    Liu, Yu-Chia; Tsai, Ming-Han; Tang, Tsung-Lin; Fang, Weileun

    2011-10-01

    This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

  10. High-performance CMOS image sensors at BAE SYSTEMS Imaging Solutions

    NASA Astrophysics Data System (ADS)

    Vu, Paul; Fowler, Boyd; Liu, Chiao; Mims, Steve; Balicki, Janusz; Bartkovjak, Peter; Do, Hung; Li, Wang

    2012-07-01

    In this paper, we present an overview of high-performance CMOS image sensor products developed at BAE SYSTEMS Imaging Solutions designed to satisfy the increasingly challenging technical requirements for image sensors used in advanced scientific, industrial, and low light imaging applications. We discuss the design and present the test results of a family of image sensors tailored for high imaging performance and capable of delivering sub-electron readout noise, high dynamic range, low power, high frame rates, and high sensitivity. We briefly review the performance of the CIS2051, a 5.5-Mpixel image sensor, which represents our first commercial CMOS image sensor product that demonstrates the potential of our technology, then we present the performance characteristics of the CIS1021, a full HD format CMOS image sensor capable of delivering sub-electron read noise performance at 50 fps frame rate at full HD resolution. We also review the performance of the CIS1042, a 4-Mpixel image sensor which offers better than 70% QE @ 600nm combined with better than 91dB intra scene dynamic range and about 1 e- read noise at 100 fps frame rate at full resolution.

  11. Ultra-fast high-resolution hybrid and monolithic CMOS imagers in multi-frame radiography

    NASA Astrophysics Data System (ADS)

    Kwiatkowski, Kris; Douence, Vincent; Bai, Yibin; Nedrow, Paul; Mariam, Fesseha; Merrill, Frank; Morris, Christopher L.; Saunders, Andy

    2014-09-01

    A new burst-mode, 10-frame, hybrid Si-sensor/CMOS-ROIC FPA chip has been recently fabricated at Teledyne Imaging Sensors. The intended primary use of the sensor is in the multi-frame 800 MeV proton radiography at LANL. The basic part of the hybrid is a large (48×49 mm2) stitched CMOS chip of 1100×1100 pixel count, with a minimum shutter speed of 50 ns. The performance parameters of this chip are compared to the first generation 3-frame 0.5-Mpixel custom hybrid imager. The 3-frame cameras have been in continuous use for many years, in a variety of static and dynamic experiments at LANSCE. The cameras can operate with a per-frame adjustable integration time of ~ 120ns-to- 1s, and inter-frame time of 250ns to 2s. Given the 80 ms total readout time, the original and the new imagers can be externally synchronized to 0.1-to-5 Hz, 50-ns wide proton beam pulses, and record up to ~1000-frame radiographic movies typ. of 3-to-30 minute duration. The performance of the global electronic shutter is discussed and compared to that of a high-resolution commercial front-illuminated monolithic CMOS imager.

  12. Design of an ultra low power CMOS pixel sensor for a future neutron personal dosimeter

    SciTech Connect

    Zhang, Y.; Hu-Guo, C.; Husson, D.; Hu, Y.

    2011-07-01

    Despite a continuously increasing demand, neutron electronic personal dosimeters (EPDs) are still far from being completely established because their development is a very difficult task. A low-noise, ultra low power consumption CMOS pixel sensor for a future neutron personal dosimeter has been implemented in a 0.35 {mu}m CMOS technology. The prototype is composed of a pixel array for detection of charged particles, and the readout electronics is integrated on the same substrate for signal processing. The excess electrons generated by an impinging particle are collected by the pixel array. The charge collection time and the efficiency are the crucial points of a CMOS detector. The 3-D device simulations using the commercially available Synopsys-SENTAURUS package address the detailed charge collection process. Within a time of 1.9 {mu}s, about 59% electrons created by the impact particle are collected in a cluster of 4 x 4 pixels with the pixel pitch of 80 {mu}m. A charge sensitive preamplifier (CSA) and a shaper are employed in the frond-end readout. The tests with electrical signals indicate that our prototype with a total active area of 2.56 x 2.56 mm{sup 2} performs an equivalent noise charge (ENC) of less than 400 e - and 314 {mu}W power consumption, leading to a promising prototype. (authors)

  13. A generalized CMOS-MEMS platform for micromechanical resonators monolithically integrated with circuits

    NASA Astrophysics Data System (ADS)

    Chen, Wen-Chien; Fang, Weileun; Li, Sheng-Shian

    2011-06-01

    A generalized foundry-oriented CMOS-MEMS platform well suited for integrated micromechanical resonators alongside IC amplifiers has been developed for commercial multi-user purpose and demonstrated with a fast turnaround time of only 3 months and a variety of design flexibilities for resonator applications. With this platform, different configurations of capacitively-transduced resonators monolithically integrated with their amplifier circuits, spanning frequencies from 500 kHz to 14.5 MHz, have been realized with resonator Q's ranging between 700 and 3500. This platform, specifically featured with various configurations of structural materials, multi-dimensional displacements, different arrangements of mechanical boundary conditions, tiny supports of resonators, large transduction areas, well-defined anchors and performance enhancement scaling with IC fabrication technology, offers a variety of flexible design options targeted for sensor, timing reference, and RF applications. In addition, resonators consisting of metal-oxide composite structures fabricated by this platform offer an effective temperature compensation scheme for the first time in CMOS-MEMS resonators, showing TCf six times better than that of resonators merely made by CMOS metals.

  14. CMOS compatible on-chip decoupling capacitor based on vertically aligned carbon nanofibers

    NASA Astrophysics Data System (ADS)

    Saleem, A. M.; Göransson, G.; Desmaris, V.; Enoksson, P.

    2015-05-01

    On-chip decoupling capacitor of specific capacitance 55 pF/?m2 (footprint area) which is 10 times higher than the commercially available discrete and on-chip (65 nm technology node) decoupling capacitors is presented. The electrodes of the capacitor are based on vertically aligned carbon nanofibers (CNFs) capable of being integrated directly on CMOS chips. The carbon nanofibers employed in this study were grown on CMOS chips using direct current plasma enhanced chemical vapor deposition (DC-PECVD) technique at CMOS compatible temperature. The carbon nanofibers were grown at temperature from 390 °C to 550 °C. The capacitance of the carbon nanofibers was measured by cyclic voltammetry and thus compared. Futhermore the capacitance of decoupling capacitor was measured using different voltage scan rate to show their high charge storage capability and finally the cyclic voltammetry is run for 1000 cycles to assess their suitability as electrode material for decoupling capacitor. Our results show the high specific capacitance and long-term reliability of performance of the on-chip decoupling capacitors. Moreover, the specific capacitance shown is larger for carbon nanofibers grown at higher temperature.

  15. Fundamental performance differences of CMOS and CCD imagers: part V

    NASA Astrophysics Data System (ADS)

    Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

    2013-02-01

    Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

  16. A New Photon Counting Detector: Intensified CMOS-APS

    NASA Astrophysics Data System (ADS)

    Bonanno, G.; Belluso, M.; Cali, A.; Carbone, A.; Cosentino, R.; Modica, A.; Scuderi, S.; Timpanaro, C.; Uslenghi, M.

    A new type of position sensor (CMOS-APS) used as readout system in MCP-based intensified photon counter is presented. Thanks to CMOS technology, the pixel addressing and the readout circuits as well as the analogue-to-digital converters are integrated into the chip. These unique characteristics make the CMOS-APS a very compact, low power consumption, photon counting system. The more classical Photon Counting Intensified CCDs (PC-ICCD), the selected CMOS-APS, the driving and interface electronics based on Field Programmable Gate Array (FPGA), and the adopted algorithm to compute the center of the luminous spot on the MCP phosphor screen are described.

  17. CMOS Camera Array With Onboard Memory

    NASA Technical Reports Server (NTRS)

    Gat, Nahum

    2009-01-01

    A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

  18. Advanced CMOS Radiation Effects Testing Analysis

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, Kenneth P.; Gordon, Michael S.; LaBel, Kenneth A.; Schwank, James R.; Dodds, Nathaniel A.; Castaneda, Carlos M.; Berg, Melanie D.; Kim, Hak S.; Phan, Anthony M.; Seidleck, Christina M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  19. Advanced CMOS Radiation Effects Testing and Analysis

    NASA Technical Reports Server (NTRS)

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  20. Cantilever-Based Biosensors in CMOS Technology

    E-print Network

    Kirstein, K -U; Zimmermann, M; Vancura, C; Volden, T; Song, W H; Lichtenberg, J; Hierlemannn, A

    2011-01-01

    Single-chip CMOS-based biosensors that feature microcantilevers as transducer elements are presented. The cantilevers are functionalized for the capturing of specific analytes, e.g., proteins or DNA. The binding of the analyte changes the mechanical properties of the cantilevers such as surface stress and resonant frequency, which can be detected by an integrated Wheatstone bridge. The monolithic integrated readout allows for a high signal-to-noise ratio, lowers the sensitivity to external interference and enables autonomous device operation.

  1. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design

    PubMed Central

    2013-01-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory. PMID:24180626

  2. Radiation Hardening of CMOS Microelectronics

    NASA Astrophysics Data System (ADS)

    McCarthy, A.; Sigmon, T. W.

    2000-02-01

    A unique methodology, silicon transfer to arbitrary substrates, has been developed under this program and is being investigated as a technique for significantly increasing the radiation insensitivity of limited quantities of conventional silicon microelectronic circuits. In this approach, removal of the that part of the silicon substrate not required for circuit operation is carried out, following completion of the circuit fabrication process. This post-processing technique is therefore applicable to state-of-the-art ICs, effectively bypassing the 3-generation technology/performance gap presently separating today's electronics from available radiation-hard electronics. Also, of prime concern are the cost savings that result by eliminating the requirement for costly redesign of commercial circuits for Rad-hard applications. Successful deployment of this technology will result in a major impact on the radiation hard electronics community in circuit functionality, design and software availability and fabrication costs.

  3. Interferometric comparison of the performance of a CMOS and sCMOS detector

    NASA Astrophysics Data System (ADS)

    Flores-Moreno, J. M.; De la Torre I., Manuel H.; Hernández-Montes, M. S.; Pérez-López, Carlos; Mendoza S., Fernando

    2015-08-01

    We present an analysis of the imaging performance of two state-of-the-art sensors widely used in the nondestructive- testing area (NDT). The analysis is based on the quantification of the signal-to-noise (SNR) ratio from an optical phase image. The calculation of the SNR is based on the relation of the median (average) and standard deviation measurements over specific areas of interest in the phase images of both sensors. This retrieved phase is coming from the vibrational behavior of a large object by means of an out-of-plane holographic interferometer. The SNR is used as a figure-of-merit to evaluate and compare the performance of the CMOS and scientific CMOS (sCMOS) camera as part of the experimental set-up. One of the cameras has a high speed CMOS sensor while the other has a high resolution sCMOS sensor. The object under study is a metallically framed table with a Formica cover with an observable area of 1.1 m2. The vibration induced to the sample is performed by a linear step motor with an attached tip in the motion stage. Each camera is used once at the time to record the deformation keeping the same experimental conditions for each case. These measurements may complement the conventional procedures or technical information commonly used to evaluate a camerás performance such as: quantum efficiency, spatial resolution and others. Results present post processed images from both cameras, but showing a smoother and easy to unwrap optical phase coming from those recorded with the sCMOS camera.

  4. Envelope tracking CMOS power amplifier with high-speed CMOS envelope amplifier for mobile handsets

    NASA Astrophysics Data System (ADS)

    Yoshida, Eiji; Sakai, Yasufumi; Oishi, Kazuaki; Yamazaki, Hiroshi; Mori, Toshihiko; Yamaura, Shinji; Suto, Kazuo; Tanaka, Tetsu

    2014-01-01

    A high-efficiency CMOS power amplifier (PA) based on envelope tracking (ET) has been reported for a wideband code division multiple access (W-CDMA) and long term evolution (LTE) application. By adopting a high-speed CMOS envelope amplifier with current direction sensing, a 5% improvement in total power-added efficiency (PAE) and a 11 dB decrease in adjacent channel leakage ratio (ACLR) are achieved with a W-CDMA signal. Moreover, the proposed PA achieves a PAE of 25.4% for a 10 MHz LTE signal at an output power (Pout) of 25.6 dBm and a gain of 24 dB.

  5. Current-mode CMOS hybrid image sensor

    NASA Astrophysics Data System (ADS)

    Benyhesan, Mohammad Kassim

    Digital imaging is growing rapidly making Complimentary Metal-Oxide-Semi conductor (CMOS) image sensor-based cameras indispensable in many modern life devices like cell phones, surveillance devices, personal computers, and tablets. For various purposes wireless portable image systems are widely deployed in many indoor and outdoor places such as hospitals, urban areas, streets, highways, forests, mountains, and towers. However, the increased demand on high-resolution image sensors and improved processing features is expected to increase the power consumption of the CMOS sensor-based camera systems. Increased power consumption translates into a reduced battery life-time. The increased power consumption might not be a problem if there is access to a nearby charging station. On the other hand, the problem arises if the image sensor is located in widely spread areas, unfavorable to human intervention, and difficult to reach. Given the limitation of energy sources available for wireless CMOS image sensor, an energy harvesting technique presents a viable solution to extend the sensor life-time. Energy can be harvested from the sun light or the artificial light surrounding the sensor itself. In this thesis, we propose a current-mode CMOS hybrid image sensor capable of energy harvesting and image capture. The proposed sensor is based on a hybrid pixel that can be programmed to perform the task of an image sensor and the task of a solar cell to harvest energy. The basic idea is to design a pixel that can be configured to exploit its internal photodiode to perform two functions: image sensing and energy harvesting. As a proof of concept a 40 x 40 array of hybrid pixels has been designed and fabricated in a standard 0.5 microm CMOS process. Measurement results show that up to 39 microW of power can be harvested from the array under 130 Klux condition with an energy efficiency of 220 nJ /pixel /frame. The proposed image sensor is a current-mode image sensor which has several advantages over the voltage-mode. The most important advantages of using current-mode technique are: reduced power consumption of the chip, ease of arithmetic operations implementation, simplification of the circuit design and hence reduced layout complexity.

  6. Impact of Spacecraft Shielding on Direct Ionization Soft Error Rates for sub-130 nm Technologies

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan A.; Xapsos, Michael A.; Stauffer, Craig A.; Jordan, Michael M.; Sanders, Anthony B.; Ladbury, Raymond L.; Oldham, Timothy R.; Marshall, Paul W.; Heidel, David F.; Rodbell, Kenneth P.

    2010-01-01

    We use ray tracing software to model various levels of spacecraft shielding complexity and energy deposition pulse height analysis to study how it affects the direct ionization soft error rate of microelectronic components in space. The analysis incorporates the galactic cosmic ray background, trapped proton, and solar heavy ion environments as well as the October 1989 and July 2000 solar particle events.

  7. Photodissociation channels for N2O near 130 nm studied by product imaging

    E-print Network

    Houston, Paul L.

    . Davis, O. Tokel, A. A. Dixit, and P. L. Houstona Department of Chemistry and Chemical Biology, Cornell component of the earth's natural atmosphere, produced primarily by biological pro- cesses in soils in the natural atmosphere, as noted by Crutzen.1 At shorter wavelengths, N2O can be excited to the C 1 state near

  8. High responsivity CMOS imager pixel implemented in SOI technology

    NASA Technical Reports Server (NTRS)

    Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

    2000-01-01

    Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

  9. Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

    PubMed Central

    Huang, Yue; Mason, Andrew J.

    2013-01-01

    This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

  10. Integrating Conjugated Polymer Microactuators with CMOS Sensing Circuitry

    E-print Network

    Maryland at College Park, University of

    Integrating Conjugated Polymer Microactuators with CMOS Sensing Circuitry for Studying Living Cells present the use of electroactive polymer actuators as components of a biolab-on-a-chip, which has, and packaging. Keywords: lab-on-a-chip, cells, polypyrrole, conjugated polymers, MEMS, CMOS, potentiostat

  11. A CMOS Potentiostat for Control of Integrated MEMS Actuators

    E-print Network

    Maryland at College Park, University of

    A CMOS Potentiostat for Control of Integrated MEMS Actuators Somashekar Bangalore Prakash, Pamela-- We describe a potentiostat designed for in situ electrochemical control of MEMS actuators. This module is tailored for integration into a hybrid CMOS-MEMS system-on- a-chip to confine cells and measure

  12. Nanophotonic integration in state-of-the-art CMOS foundries

    E-print Network

    Ram, Rajeev J.

    Nanophotonic integration in state-of-the-art CMOS foundries Jason S. Orcutt1,2* , Anatol Khilo1-of-the-art CMOS foundry infrastructure. In our approach, proven XeF2 post-processing technology and compliance with electronic foundry process flows eliminate the need for specialized substrates or wafer bonding

  13. Title of dissertation: CHAOTIC OSCILLATIONS IN CMOS INTEGRATED CIRCUITS

    E-print Network

    Anlage, Steven

    ABSTRACT Title of dissertation: CHAOTIC OSCILLATIONS IN CMOS INTEGRATED CIRCUITS Myunghwan Park and fabricated as an integrated circuit. The underlying physics of the chaotic dynamics in the Boolean chaotic OSCILLATIONS IN CMOS INTEGRATED CIRCUITS by Myunghwan Park Dissertation submitted to the Faculty

  14. Process Compensated CMOS Temperature Sensor for Microprocessor Application

    E-print Network

    Ayazi, Farrokh

    Process Compensated CMOS Temperature Sensor for Microprocessor Application Yaesuk Jeong and Farrokh of a process compensated CMOS temperature sensor that does not require any BJTs. CTAT and PTAT sensors that are based on temperature-dependent threshold voltage (VTH) are designed to have same process variation

  15. CMOS Monolithic Voltage Converter ________________________________________________________________ Maxim Integrated Products 1

    E-print Network

    Berns, Hans-Gerd

    MAX660 CMOS Monolithic Voltage Converter monolithic, charge-pump voltage inverter converts a +1.5V to +5.5V input to a corresponding -1.5V to -5.5V literature: http://www.maxim-ic.com, or phone 1-800-998-8800 #12;CONDITIONS MAX660 CMOS Monolithic Voltage

  16. Analog CMOS Velocity Sensors C. M. Higgins and C. Koch

    E-print Network

    Analog CMOS Velocity Sensors C. M. Higgins and C. Koch Division of Biology, 139-74 California Institute of Technology Pasadena, CA 91125 ABSTRACT A family of analog CMOS velocity sensors is described which measures the velocity of a moving edge by computing its time of travel between adjacent pixels

  17. AN UNCOOLED MICROBOLOMETER INFRARED DETECTOR IN ANY STANDARD CMOS TECHNOLOGY

    E-print Network

    Akin, Tayfun

    AN UNCOOLED MICROBOLOMETER INFRARED DETECTOR IN ANY STANDARD CMOS TECHNOLOGY D.S. Tezcan*, F. Koçer. This approach is very cost-effective to produce large focal plane arrays in CMOS for uncooled infrared imaging with reasonable performance. INTRODUCTION Uncooled infrared detectors have recently gained wide attention

  18. RF power potential of 45 nm CMOS technology

    E-print Network

    Putnam, Christopher

    This paper presents the first measurements of the RF power performance of 45 nm CMOS devices with varying device widths and layouts. We find that 45 nm CMOS can deliver a peak output power density of around 140 mW/mm with ...

  19. CCD vs. CMOS from: http://www.dalsa.com/markets/ccd_vs_cmos.asp

    E-print Network

    Giger, Christine

    vs. oranges: they can both be good for you. DALSA offers both. CCD (charge coupled device) and CMOS into electric charge and process it into electronic signals. In a CCD sensor, every pixel's charge charge tovoltage conversion, and the sensor often also includes amplifiers, noisecorrection

  20. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    NASA Technical Reports Server (NTRS)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  1. CMOS solid state photomultipliers for ultra-low light levels

    NASA Astrophysics Data System (ADS)

    Johnson, Erik B.; Stapels, Christopher J.; Chen, Xaio Jie; Whitney, Chad; Chapman, Eric C.; Alberghini, Guy; Rines, Rich; Augustine, Frank; Christian, James

    2011-05-01

    Detection of single photons is crucial for a number of applications. Geiger photodiodes (GPD) provide large gains with an insignificant amount of multiplication noise exclusively from the diode. When the GPD is operated above the reverse bias breakdown voltage, the diode can avalanche due to charged pairs generated from random noise (typically thermal) or incident photons. The GPD is a binary device, as only one photon is needed to trigger an avalanche, regardless of the number of incident photons. A solid-state photomultiplier (SSPM) is an array of GPDs, and the output of the SSPM is proportional to the incident light intensity, providing a replacement for photomultiplier tubes. We have developed CMOS SSPMs using a commercial fabrication process for a myriad of applications. We present results on the operation of these devices for low intensity light pulses. The data analysis provides a measured of the junction capacitance (~150 fF), which affects the rise time (~2 ns), the fall time (~32 ns), and gain (>106). Multipliers for the cross talk and after pulsing are given, and a consistent picture within the theory of operation of the expected dark current and photodetection efficiency is demonstrate. Enhancement of the detection efficiency with respect to the quantum efficiency at unity gain for shallow UV photons is measured, indicating an effect due to fringe fields within the diode structure. The signal and noise terms have been deconvolved from each other, providing the fundamental model for characterizing the behavior at low-light intensities.

  2. Fabrication of Wireless Micro Pressure Sensor Using the CMOS Process.

    PubMed

    Dai, Ching-Liang; Lu, Po-Wei; Wu, Chyan-Chyi; Chang, Chienliu

    2009-01-01

    In this study, we fabricated a wireless micro FET (field effect transistor) pressure sensor based on the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The wireless micro pressure sensor is composed of a FET pressure sensor, an oscillator, an amplifier and an antenna. The oscillator is adopted to generate an ac signal, and the amplifier is used to amplify the sensing signal of the pressure sensor. The antenna is utilized to transmit the output voltage of the pressure sensor to a receiver. The pressure sensor is constructed by 16 sensing cells in parallel. Each sensing cell contains an MOS (metal oxide semiconductor) and a suspended membrane, which the gate of the MOS is the suspended membrane. The post-process employs etchants to etch the sacrificial layers in the pressure sensor for releasing the suspended membranes, and a LPCVD (low pressure chemical vapor deposition) parylene is adopted to seal the etch holes in the pressure. Experimental results show that the pressure sensor has a sensitivity of 0.08 mV/kPa in the pressure range of 0-500 kPa and a wireless transmission distance of 10 cm. PMID:22291534

  3. Post-CMOS Parylene Packaging for On-chip Biosensor Arrays

    E-print Network

    Mason, Andrew

    Post-CMOS Parylene Packaging for On-chip Biosensor Arrays Lin Li Department of Electrical as an open challenge. This paper presents a robust and reliable packaging scheme for on-CMOS biosensors CMOS die. Photos of a packaged CMOS biosensor array chip and electrochemical measurements in potassium

  4. Theoretical performance analysis for CMOS based high resolution detectors.

    PubMed

    Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2013-03-01

    High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 ?m thick HL-type CsI phosphor, a 50 ?m-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive. PMID:24353390

  5. A CMOS high speed imaging system design based on FPGA

    NASA Astrophysics Data System (ADS)

    Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

    2015-10-01

    CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

  6. A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

    NASA Astrophysics Data System (ADS)

    Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

    2014-01-01

    This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

  7. A CAD tool for the power estimation of CMOS, BiCMOS and BiNMOS gates 

    E-print Network

    Islam, Kazi Inamul

    1995-01-01

    This thesis describes a CAD tool for the power estimation of CMOS, BiCMOS and BiNMOS gates. Using analytical models for the transient behavior of the gates, accurate estimates of the power dissipated by each type of gate during a typical transition...

  8. Solar XUV Imaging and Non-dispersive Spectroscopy for Solar-C Enabled by Scientific CMOS APS Arrays

    NASA Astrophysics Data System (ADS)

    Stern, Robert A.; Lemen, J. R.; Shing, L.; Janesick, J.; Tower, J.

    2009-05-01

    Monolithic CMOS Advanced Pixel Sensor (APS) arrays are showing great promise as eventual replacements for the current workhorse of solar physics focal planes, the scientific CCD. CMOS APS devices have individually addressable pixels, increased radiation tolerance compared to CCDs, and require lower clock voltages, and thus lower power. However, commercially available CMOS chips, while suitable for use with intensifiers or fluorescent coatings, are generally not optimized for direct detection of EUV and X-ray photons. A high performance scientific CMOS array designed for these wavelengths will have significant new capabilities compared to CCDs, including the ability to read out small regions of the solar disk at high (sub sec) cadence, count single X-ray photons with Fano-limited energy resolution, and even operate at room temperature with good noise performance. Such capabilities will be crucial for future solar X-ray and EUV missions such as Solar-C. Sarnoff Corporation has developed scientific grade, monolithic CMOS arrays for X-ray imaging and photon counting. One prototype device, the "minimal" array, has 8 um pixels, is 15 to 25 um thick, is fabricated on high-resistivity ( 10 to 20 kohm-cm) Si wafers, and can be back-illuminated. These characteristics yield high quantum efficiency and high spatial resolution with minimal charge sharing among pixels, making it ideal for the detection of keV X-rays. When used with digital correlated double sampling, the array has demonstrated noise performance as low as 2 e, allowing single photon counting of X-rays over a range of temperatures. We report test results for this device in X-rays, and discuss the implications for future solar space missions.

  9. Vertical Isolation for Photodiodes in CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2008-01-01

    In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

  10. Monolithic CMOS imaging x-ray spectrometers

    NASA Astrophysics Data System (ADS)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

    2014-07-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15?m, high resistivity custom (~30k?-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16?m pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40?V/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9?m epitaxial silicon and have a 1k by 1k format. They incorporate similar 16?m pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and spectrally resolved without saturation. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting x-ray astronomy. These features include read noise, x-ray spectral response and quantum efficiency. Funding for this work has been provided in large part by NASA Grant NNX09AE86G and a grant from the Betty and Gordon Moore Foundation.

  11. Advances in CMOS solid-state photomultipliers for scintillation detector applications

    NASA Astrophysics Data System (ADS)

    Christian, James F.; Stapels, Christopher J.; Johnson, Erik B.; McClish, Mickel; Dokhale, Purushotthom; Shah, Kanai S.; Mukhopadhyay, Sharmistha; Chapman, Eric; Augustine, Frank L.

    2010-12-01

    Solid-state photomultipliers (SSPMs) are a compact, lightweight, potentially low-cost alternative to a photomultiplier tube for a variety of scintillation detector applications, including digital-dosimeter and medical-imaging applications. Manufacturing SSPMs with a commercial CMOS process provides the ability for rapid prototyping, and facilitates production to reduce the cost. RMD designs CMOS SSPM devices that are fabricated by commercial foundries. This work describes the characterization and performance of these devices for scintillation detector applications. This work also describes the terms contributing to device noise in terms of the excess noise of the SSPM, the binomial statistics governing the number of pixels triggered by a scintillation event, and the background, or thermal, count rate. The fluctuations associated with these terms limit the resolution of the signal pulse amplitude. We explore the use of pixel-level signal conditioning, and characterize the performance of a prototype SSPM device that preserves the digital nature of the signal. In addition, we explore designs of position-sensitive SSPM detectors for medical imaging applications, and characterize their performance.

  12. SEMICONDUCTOR INTEGRATED CIRCUITS: A full on-chip CMOS low-dropout voltage regulator with VCCS compensation

    NASA Astrophysics Data System (ADS)

    Leisheng, Gao; Yumei, Zhou; Bin, Wu; Jianhua, Jiang

    2010-08-01

    A full on-chip CMOS low-dropout (LDO) voltage regulator with high PSR is presented. Instead of relying on the zero generated by the load capacitor and its equivalent series resistance, the proposed LDO generates a zero by voltage-controlled current sources for stability. The compensating capacitor for the proposed scheme is only 0.18 pF, which is much smaller than the capacitor of the conventional compensation scheme. The full on-chip LDO was fabricated in commercial 0.35 ?m CMOS technology. The active chip area of the LDO (including the bandgap voltage reference) is 400 × 270 ?m2. Experimental results show that the PSR of the LDO is -58.7 dB at a frequency of 10 Hz and -20 dB at a frequency of 1 MHz. The proposed LDO is capable of sourcing an output current up to 50 mA.

  13. The 1.2 micron CMOS technology

    NASA Technical Reports Server (NTRS)

    Pina, C. A.

    1985-01-01

    A set of test structures was designed using the Jet Propulsion Laboratory (JPL) test chip assembler and was used to evaluate the first CMOS-bulk foundry runs with feature sizes of 1.2 microns. In addition to the problems associated with the physical scaling of the structures, this geometry provided an additional set of problems, since the design files had to be generated in such a way as to be capable of being processed through p-well, n-well, and twin-well processing lines. This requirement meant that the files containing the geometric design rules as well as the structure design files had to produce process-insensitive designs, a requirement that does not apply to the more mature 3.0-micron CMOS feature size technology. Because of the photolithographic steps required with this feature size, the maximum allowable chip size was 10 x 10 mm, and this chip was divided into 24 project areas, with each area being 1.6 x 1.6 mm in size. The JPL-designed structures occupied 13 out of the 21 allowable project sizes and provided the only test information obtained from these three preliminary runs. The structures were used to successfully evaluate three different manufacturing runs through two separate foundries.

  14. Far ultraviolet sensitivity of silicon CMOS sensors

    NASA Astrophysics Data System (ADS)

    Davis, Michael W.; Greathouse, Thomas K.; Retherford, Kurt D.; Winters, Gregory S.; Bai, Yibin; Beletic, James W.

    2012-07-01

    We describe vacuum ultraviolet sensitivity measurements of a new high performance silicon-based CMOS sensor from Teledyne Imaging Sensors. These sensors do not require the high voltages of MCP detectors, making them a lower mass and power alternative to the more mature MCP technology. These devices demonstrate up to 40 percent quantum efficiency at vacuum ultraviolet wavelengths, either meeting or greatly exceeding 10 percent quantum efficiency across the entire 100-200 nm wavelength region. As with similar visible sensitive devices, backside illumination results in a higher quantum efficiency than frontside illumination. Measurements of the vacuum ultraviolet sensitivity of the Teledyne silicon PIN detectors were made by directing a known intensity of ultraviolet light at discrete wavelengths onto the test detectors and reading out the resulting photocurrent. The sensitivity of the detector at a given wavelength was then calculated from the intensity and wavelength of the incoming light and the relative photodiode to NIST-traceable calibration diode active areas. A custom electromechanical interface was developed to make these measurements within the SwRI Vacuum Radiometric Calibration Chamber. While still in the single pixel stage, full 1K × 1K focal plane arrays are possible using existing CMOS readout electronics and hold great promise for inclusion in future spaceflight instrument concepts.

  15. Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

    2008-01-01

    Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

  16. An electrostatic CMOS/BiCMOS Lithium ion vibration-based harvester-charger IC

    NASA Astrophysics Data System (ADS)

    Torres, Erick Omar

    Self-powered microsystems, such as wireless transceiver microsensors, appeal to an expanding application space in monitoring, control, and diagnosis for commercial, industrial, military, space, and biomedical products. As these devices continue to shrink, their microscale dimensions allow them to be unobtrusive and economical, with the potential to operate from typically unreachable environments and, in wireless network applications, deploy numerous distributed sensing nodes simultaneously. Extended operational life, however, is difficult to achieve since their limited volume space constrains the stored energy available, even with state-of-the-art technologies, such as thin-film lithium-ion batteries (Li Ion) and micro-fuel cells. Harvesting ambient energy overcomes this deficit by continually replenishing the energy reservoir and, as a result, indefinitely extending system lifetime. In this work, an electrostatic harvester that harnesses ambient kinetic energy from vibrations to charge an energy-storage device (e.g., a battery) is investigated, developed, and evaluated. The proposed harvester charges and holds the voltage across a vibration-sensitive variable capacitor so that vibrations can induce it to generate current into the battery when capacitance decreases (as its plates separate). The challenge is that energy is harnessed at relatively slow rates, producing low output power, and the electronics required to transfer it to charge a battery can easily demand more than the power produced. To this end, the system reduces losses by time-managing and biasing its circuits to operate only when needed and with just enough energy while charging the capacitor through an efficient quasi-lossless inductor-based precharger. As result, the proposed energy harvester stores a net energy gain in the battery during every vibration cycle. Two energy-harvesting integrated circuits (IC) were analyzed, designed, developed, and validated using a 0.7-im BiCMOS process and a 30-Hz mechanical variable capacitor. The precharger, harvester, monitoring, and control microelectronics of the first prototype draw sufficient power to operate and at the same time produce experimentally 1.27, 2.14, and 2.87 nJ per vibration cycle for battery voltages at 2.7, 3.5, and 4.2 V, which with 30-Hz vibrations produce 38.1, 64.2, and 86.1 nW. By incorporating into the system a self-tuning loop that adapts optimally the inductor-based precharger to varying battery voltages, the second prototype harnessed and gained 1.93, 2.43, and 3.89 nJ per vibration cycle at battery voltages 2.7, 3.5, and 4.2 V, generating 57.89, 73.02, and 116.55 nW at 30 Hz. The harvester ultimately charges from 2.7 to 4.2 V a 1-muF capacitor (which emulates a small thin-film Li Ion) in approximately 69 s, harnessing in the same length of time 47.9% more energy than with a non-adapting harvester.

  17. CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

    NASA Technical Reports Server (NTRS)

    Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

    2006-01-01

    This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

  18. A wide-dynamic-range time-based CMOS imager

    E-print Network

    O'Halloran, Micah G. (Micah Galletta), 1978-

    2008-01-01

    This thesis describes a novel dual-threshold time-based current sensing algorithm suitable for use in wide-dynamic-range CMOS imagers. A prototype 150 x 256 pixel imager employing this algorithm experimentally achieves ...

  19. Photonic Device Layout Within the Foundry CMOS Design Environment

    E-print Network

    Orcutt, Jason Scott

    A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs ...

  20. Implementation of CMOS Millimeter-Wave Devices for Rotational Spectroscopy

    NASA Astrophysics Data System (ADS)

    Drouin, Brian; Tang, Adrian; Schlecht, Erich T.; Daly, Adam M.; Brageot, Emily; Gu, Qun Jane; Ye, Yu; Shu, Ran; Chang, M.-C. Frank; Kim, Rod M.

    2015-06-01

    The extension of radio-frequency CMOS circuitry into millimeter wavelengths promises the extension of spectroscopic techniques in compact, power efficient systems. We are now exploring the use of CMOS millimeter devices for low-mass, low-power instrumentation capable of remote or in-situ detection of gas composition during space missions. This effort focuses on the development of a semi-confocal Fabry-Perot cavity with mm-wavelength CMOS transmitter and receiver attached directly to a cavity coupler. Placement of the devices within the cavity structure bypasses problems encountered with signal injection and extraction in traditional cavity designs and simultaneously takes full advantage of the miniaturized form of the CMOS hardware. The presentation will provide an overview of the project and details of the accomplishments thus far, including the development and testing of a pulse modulated 83-98 GHz transmitter.

  1. A safety monitoring system for taxi based on CMOS imager

    NASA Astrophysics Data System (ADS)

    Liu, Zhi

    2005-01-01

    CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

  2. Strain-engineered CMOS-compatible Ge photodetectors

    E-print Network

    Cannon, Douglas Dale, 1974-

    2004-01-01

    The development of CMOS-compatible photodetectors capable of operating throughout the entire telecommunications wavelength spectrum will aid in the integration of photodetectors with Si microelectronics, thus offering a ...

  3. Fabrication and simulation of CMOS-compatible photodiodes

    E-print Network

    DiLello, Nicole Ann

    2008-01-01

    CMOS-compatible photodiodes are becoming increasinging important devices to study because of their application in combined electronic-photonic systems. They are already used as inexpensive optical transceivers in fiber ...

  4. Foundry Services for MEMS MOSIS: CMOS + post processing

    E-print Network

    Leu, Tzong-Shyng "Jeremy"

    Foundry Services for MEMS MOSIS: CMOS + post processing (pseudo-surface-micromaching - SiO2/Poly Surface micromachining #12;Microfabrication by Foundry Service ·Fixed process (design rules) ·Use layout

  5. Circuits and algorithms for pipelined ADCs in scaled CMOS technologies

    E-print Network

    Brooks, Lane Gearle, 1975-

    2008-01-01

    CMOS technology scaling is creating significant issues for analog circuit design. For example, reduced signal swing and device gain make it increasingly difficult to realize high-speed, high-gain feedback loops traditionally ...

  6. Resonant Body Transistors in IBM's 32nm SOI CMOS technology

    E-print Network

    Marathe, Radhika A.

    This work presents an unreleased CMOS-integrated MEMS resonators fabricated at the transistor level of IBM's 32SOI technology and realized without the need for any post-processing or packaging. These Resonant Body Transistors ...

  7. CMOS temperature sensor utilizing interface-trap charge pumping 

    E-print Network

    Berber, Feyza

    2006-10-30

    The objective of this thesis is to introduce an alternative temperature sensor in CMOS technology with small area, low power consumption, and high resolution that can be easily interfaced. A novel temperature sensor utilizing the interface...

  8. A study of CMOS technologies for image sensor applications

    E-print Network

    Wang, Ching-Chun, 1969-

    2001-01-01

    CMOS (Complementary Metal-Oxide-Silicon) imager technology, as compared with mature CCD (Charge-Coupled Device) imager technology, has the advantages of higher circuit integration, lower power consumption, and potentially ...

  9. Multichannel lens-free CMOS sensors for real-time monitoring of cell growth.

    PubMed

    Chang, Ko-Tung; Chang, Yu-Jen; Chen, Chia-Ling; Wang, Yao-Nan

    2015-02-01

    A low-cost platform is proposed for the growth and real-time monitoring of biological cells. The main components of the platform include a PMMA cell culture microchip and a multichannel lens-free CMOS (complementary metal-oxide-semiconductor) / LED imaging system. The PMMA microchip comprises a three-layer structure and is fabricated using a low-cost CO2 laser ablation technique. The CMOS / LED monitoring system is controlled using a self-written LabVIEW program. The platform has overall dimensions of just 130 × 104 × 115 mm(3) and can therefore be placed within a commercial incubator. The feasibility of the proposed system is demonstrated using HepG2 cancer cell samples with concentrations of 5000, 10?000, 20?000, and 40?000 cells/mL. In addition, cell cytotoxicity tests are performed using 8, 16, and 32 mM cyclophosphamide. For all of the experiments, the cell growth is observed over a period of 48 h. The cell growth rate is found to vary in the range of 44?52% under normal conditions and from 17.4?34.5% under cyclophosphamide-treated conditions. In general, the results confirm the long-term cell growth and real-time monitoring ability of the proposed system. Moreover, the magnification provided by the lens-free CMOS / LED observation system is around 40× that provided by a traditional microscope. Consequently, the proposed system has significant potential for long-term cell proliferation and cytotoxicity evaluation investigations. PMID:25224658

  10. CMOS imager for pointing and tracking applications

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

    2006-01-01

    Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

  11. CMOS digital pixel sensors: technology and applications

    NASA Astrophysics Data System (ADS)

    Skorka, Orit; Joseph, Dileepan

    2014-04-01

    CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

  12. Latchup in CMOS devices from heavy ions

    NASA Technical Reports Server (NTRS)

    Soliman, K.; Nichols, D. K.

    1983-01-01

    It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

  13. USB video image controller used in CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Zhang, Wenxuan; Wang, Yuxia; Fan, Hong

    2002-09-01

    CMOS process is mainstream technique in VLSI, possesses high integration. SE402 is multifunction microcontroller, which integrates image data I/O ports, clock control, exposure control and digital signal processing into one chip. SE402 reduces the number of chips and PCB's room. The paper studies emphatically on USB video image controller used in CMOS image sensor and give the application on digital still camera.

  14. CMOS front end electronics for the ATLAS muon detector

    SciTech Connect

    Huth, J.; Oliver, J.; Hazen, E.; Shank, J.

    1997-12-31

    An all-CMOS design for an integrated ASD (Amplifier-Shaper-Discriminator) chip for readout of the ATLAS Monitored Drift Tubes (MDTs) is presented. Eight channels of charge-sensitive preamp, two-stage pole/zero shaper, Wilkinson ADC and discriminator with programmable hysteresis are integrated on a single IC. Key elements have been prototyped in 1.2 and 0.5 micron CMOS operating at 5V and 3.3V respectively.

  15. Totally self-checking circuits and testable CMOS circuits

    NASA Astrophysics Data System (ADS)

    Jha, N. K.

    1986-06-01

    A Totally Self-Checking (TSC) circuit belongs to a class of circuits used for Concurrent Error Detection (CED) purposes. It consists of a functional circuit that has encoded inputs and outputs and a checker that monitors these outputs and gives and error indication. It is known that the traditional stuck-at fault model is not sufficient to model realistic physical failures. Techniques for implementing existing gate-level TSC circuits in CMOS, Domino-CMOS and standard CMOS technologies, so that they are TSC with respect to physical failures, are described. Design methods which reduce the transistor count, delay, and the number of tests of TSC checkers are also given. Another problem in the area of TSC circuits concerns embedded checkers whose inputs are not directly controllable. If they do not get all the required codewords to test them they cannot be guaranteed to be TSC. A new encoding technique and a design procedure to solve this problem are presented. It has been shown previously that the two-pattern tests used to test CMOS circuits can be invalidated by timing skews. A necessary and sufficient condition is derived to find out whether or not an AND-OR or and OR-AND CMOS realization exists for a given function so that a valid test set can always be found, even in the presence of arbitrary timing skews. A new Hybrid CMOS realization is introduced to take care of the cases in which this is not possible.

  16. An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

    PubMed Central

    Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18??m TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18??m TSMC CMOS technology. PMID:24782680

  17. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    PubMed

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18? ?m TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 ?m TSMC CMOS technology. PMID:24782680

  18. Development of a CMOS MEMS pressure sensor with a mechanical force-displacement transduction structure

    NASA Astrophysics Data System (ADS)

    Cheng, Chao-Lin; Chang, Heng-Chung; Chang, Chun-I.; Fang, Weileun

    2015-12-01

    This study presents a capacitive pressure sensor with a mechanical force-displacement transduction structure based on the commercially available standard CMOS process (the TSMC 0.18 ?m 1P6M CMOS process). The pressure sensor has a deformable diaphragm to support a movable plate with an embedded sensing electrode. As the diaphragm is deformed by the ambient pressure, the movable plate and its embedded sensing electrode are displaced. Thus, the pressure is detected from the capacitance change between the movable and fixed electrodes. The undeformed movable electrode will increase the effective sensing area between the sensing electrodes, thereby improving the sensitivity. Experimental results show that the proposed pressure sensor with a force-displacement transducer will increase the sensitivity by 126% within the 20 kPa–300 kPa absolute pressure range. Moreover, this study extends the design to add pillars inside the pressure sensor to further increase its sensing area as well as sensitivity. A sensitivity improvement of 117% is also demonstrated for a pressure sensor with an enlarged sensing electrode (the overlap area is increased two fold).

  19. Radiation hardening of CMOS-based circuitry in SMART transmitters. Phase 1, Feasibility: Final report

    SciTech Connect

    Loescher, D.H.

    1993-02-01

    Process control transmitters that incorporate digital signal processing could be used advantageously in nuclear power plants; however, because such transmitters are too sensitive to radiation, they are not used. The Electric Power Research Institute sponsored work at Sandia National Laboratories under EPRI contract RP2614-58 to determine why SMART transmitters fail when exposed to radiation and to design and demonstrate SMART transmitter circuits that could tolerate radiation. The term ``SMART`` denotes transmitters that contain digital logic. Tests showed that transmitter failure was caused by failure of the complementary metal oxide semiconductors (CMOS)-integrated circuits which are used extensively in commercial transmitters. Radiation-hardened replacements were not available for the radiation-sensitive CMOS circuits. A conceptual design showed that a radiation-tolerant transmitter could be constructed. A prototype for an analog-to-digital converter subsection worked satisfactorily after a total dose of 30 megarads(Si). Encouraging results were obtained from preliminary bench-top tests on a dc-to-dc converter for the power supply subsection.

  20. Depleted Monolithic Active Pixel Sensors (DMAPS) implemented in LF-150 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Kishishita, T.; Hemperek, T.; Krüger, H.; Wermes, N.

    2015-03-01

    We present the recent development of Depleted Monolithic Active Pixel Sensors (DMAPS), implemented with an LFoundry (LF) 150 nm CMOS process. MAPS detectors based on an epi-layer have been matured in recent years and have attractive features in terms of reducing material budget and handling cost compared to conventional hybrid pixel detectors. However, the obtained signal is relatively small (~1000 e-) due to the thin epi-layer, and charge collection time is relatively slow, e.g., in the order of 100 ns, because charges are mainly collected by diffusion. Modern commercial CMOS technology, however, offers advanced process options to overcome such difficulties and enable truly monolithic devices as an alternative to hybrid pixel sensors and charge coupled devices. Unlike in the case of the standard MAPS technologies with epi-layers, the LF process provides a high-resistivity substrate that enables large signal and fast charge collection by drift in a ~50 ?m thick depleted layer. Since this process also enables the use of deep n- and p-wells to isolate the collection electrode from the thin active device layer, PMOS and NMOS transistors are available for the readout electronics in each pixel cell. In order to evaluate the sensor and transistor characteristics, several collection electrodes variants and readout architectures have been implemented. In this report, we focus on its design aspect of the LF-DMAPS prototype chip.

  1. Hardness variability in commercial technologies

    SciTech Connect

    Shaneyfelt, M.R.; Winokur, P.S.; Meisenheimer, T.L.; Sexton, F.W.; Roeske, S.B.; Knoll, M.G.

    1994-12-01

    The radiation hardness of commercial Floating Gate 256K E{sup 2}PROMs from a single diffusion lot was observed to vary between 5 to 25 krad(Si) when irradiated at a low dose rate of 64 mrad(Si)/s. Additional variations in E{sup 2}PROM hardness were found to depend on bias condition and failure mode (i.e., inability to read or write the memory), as well as the foundry at which the part was manufactured. This variability is related to system requirements, and it is shown that hardness level and variability affect the allowable mode of operation for E{sup 2}PROMs in space applications. The radiation hardness of commercial 1-Mbit CMOS SRAMs from Micron, Hitachi, and Sony irradiated at 147 rad(Si)/s was approximately 12, 13, and 19 krad(Si), respectively. These failure levels appear to be related to increases in leakage current during irradiation. Hardness of SRAMs from each manufacturer varied by less than 20%, but differences between manufacturers are significant. The Qualified Manufacturer`s List approach to radiation hardness assurance is suggested as a way to reduce variability and to improve the hardness level of commercial technologies.

  2. 77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-12-14

    ...COMMISSION [Investigation No. 337-TA-846] Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...sale within the United States after importation of certain CMOS image sensors and products containing the same based on...

  3. Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

    E-print Network

    Wade, Mark T.

    We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS ...

  4. Design Considerations for CMOS-Integrated Hall-Effect Magnetic Bead Detectors for Biosensor Applications

    PubMed Central

    Skucha, K.; Gambini, S.; Liu, P.; Megens, M.; Kim, J.; Boser, BE

    2014-01-01

    We describe a design methodology for on-chip magnetic bead label detectors based on Hall-effect sensors. Signal errors caused by the label-binding process and other factors that limit the minimum detection area are quantified and adjusted to meet typical assay accuracy standards. The methodology is demonstrated by designing an 8192 element Hall sensor array, implemented in a commercial 0.18 ?m CMOS process with single-mask postprocessing. The array can quantify a 1% surface coverage of 2.8 ?m beads in 30 seconds with a coefficient of variation of 7.4%. This combination of accuracy and speed makes this technology a suitable detection platform for biological assays based on magnetic bead labels. PMID:25031503

  5. CMOS Cell Sensors for Point-of-Care Diagnostics

    PubMed Central

    Adiguzel, Yekbun; Kulah, Haluk

    2012-01-01

    The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

  6. NSC 800, 8-bit CMOS microprocessor

    NASA Technical Reports Server (NTRS)

    Suszko, S. F.

    1984-01-01

    The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

  7. Heavy ion radiation damage simulations for CMOS image sensors Henok Mebrahtua

    E-print Network

    Hornsey, Richard

    Heavy ion radiation damage simulations for CMOS image sensors Henok Mebrahtua , Wei Gaoa , Paul J, University of Toronto, Toronto, Ontario, Canada ABSTRACT Damage in CMOS image sensors caused by heavy ions and range of ions in matter) simulation results of heavy ion radiation damage to CMOS image sensors

  8. PHASE NOISE PERFORMANCE COMPARISON BETWEEN LIGA-MEMS AND ON-CHIP CMOS CAPACITORS

    E-print Network

    Saskatchewan, University of

    PHASE NOISE PERFORMANCE COMPARISON BETWEEN LIGA-MEMS AND ON-CHIP CMOS CAPACITORS FOR A VCO between the VCO using a new type of MEMS vari- able capacitor and that using conventional CMOS varactor, which is built on-chip together with the CMOS VCO. A representative MEMS variable capacitor, fabricated

  9. 2444 IEEE SENSORS JOURNAL, VOL. 12, NO. 7, JULY 2012 CMOS Monolithic Nanoparticle-Coated

    E-print Network

    Mason, Andrew

    2444 IEEE SENSORS JOURNAL, VOL. 12, NO. 7, JULY 2012 CMOS Monolithic Nanoparticle of the CMOS monolithic detector array is discussed, and preliminary measurement results using chamber--Chemiresistor, complementary-metal-oxide semiconductor (CMOS) monolithic sensor array, gas chromatography (GC) detector, GC. I

  10. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-07

    ... Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint; Solicitation of... entitled Certain CMOS Image Sensors and Products Containing Same, DN 2895; the Commission is soliciting... importation of certain CMOS image sensors and products containing same. The complaint names as...

  11. Integration of Single-Walled Carbon Nanotubes on to CMOS Circuitry with Parylene-C Encapsulation

    E-print Network

    Dokmeci, Mehmet

    Integration of Single-Walled Carbon Nanotubes on to CMOS Circuitry with Parylene-C Encapsulation for the placement of the SWNTs on to these electrodes. Encapsulating the CMOS chip with a thin (1m) parylene-C layer. Keywords-CMOS circuitry; Dielectrophoretic assembly; Nano scale integration; Parylene-C encapsulation

  12. Modeling the current behavior of the digital BiCMOS gate 

    E-print Network

    Tang, Zhilong

    1995-01-01

    This thesis describes a piece-wise approximation of transient current response of the digital BiCMOS gate. Based on the detailed transient analysis of the conventional digital BiCMOS gate, a new circuit model for digital BiCMOS gate is derived which...

  13. Del 2: Enkel elektrisk transistor modell og introduksjon til CMOS prosess

    E-print Network

    Stølen, Ketil

    Del 2: Enkel elektrisk transistor modell og introduksjon til CMOS prosess YNGVAR BERG I. Innhold GJ ennomgang av CMOS prosess, tverrsnitt av nMOS- og pMOS transistor og tverrsnitt av CMOS inverter. Enkel forklaring p°a begreper som akkumulasjon, deplesjon og inver- sjon. Enkel fysikalsk forklaring p°a transistor

  14. Space Commercialization

    NASA Technical Reports Server (NTRS)

    Martin, Gary L.

    2011-01-01

    A robust and competitive commercial space sector is vital to continued progress in space. The United States is committed to encouraging and facilitating the growth of a U.S. commercial space sector that supports U.S. needs, is globally competitive, and advances U.S. leadership in the generation of new markets and innovation-driven entrepreneurship. Energize competitive domestic industries to participate in global markets and advance the development of: satellite manufacturing; satellite-based services; space launch; terrestrial applications; and increased entrepreneurship. Purchase and use commercial space capabilities and services to the maximum practical extent Actively explore the use of inventive, nontraditional arrangements for acquiring commercial space goods and services to meet United States Government requirements, including measures such as public-private partnerships, . Refrain from conducting United States Government space activities that preclude, discourage, or compete with U.S. commercial space activities. Pursue potential opportunities for transferring routine, operational space functions to the commercial space sector where beneficial and cost-effective.

  15. Commercial Sensory Survey Radiation Testing Progress Report

    NASA Technical Reports Server (NTRS)

    Becker, Heidi N.; Dolphic, Michael D.; Thorbourn, Dennis O.; Alexander, James W.; Salomon, Phil M.

    2008-01-01

    The NASA Electronic Parts and Packaging (NEPP) Program Sensor Technology Commercial Sensor Survey task is geared toward benefiting future NASA space missions with low-cost, short-duty-cycle, visible imaging needs. Such applications could include imaging for educational outreach purposes or short surveys of spacecraft, planetary, or lunar surfaces. Under the task, inexpensive commercial grade CMOS sensors were surveyed in fiscal year 2007 (FY07) and three sensors were selected for total ionizing dose (TID) and displacement damage dose (DDD) tolerance testing. The selected sensors had to meet selection criteria chosen to support small, low-mass cameras that produce good resolution color images. These criteria are discussed in detail in [1]. This document discusses the progress of radiation testing on the Micron and OmniVision sensors selected in FY07 for radiation tolerance testing.

  16. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    PubMed Central

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 ?m CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 ?W at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  17. A comprehensive study of polysilicon resistors for CMOS ULSI applications

    NASA Astrophysics Data System (ADS)

    Chuang, Hung-Ming; Thei, Kong-Beng; Tsai, Sheng-Fu; Lu, Chun-Tsen; Liao, Xin-Da; Lee, Kuan-Ming; Chen, Hon-Rung; Liu, Wen-Chau

    2003-04-01

    The characteristics of polysilicon resistors for CMOS ULSI applications have been investigated. Based on the presented sub-quarter micron CMOS borderless contact, both n + and p + polysilicon resistors with Ti- and Co-silicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyse and calculate some important parameters of polysilicon resistors including electrical delta W(? W), interface resistance Rinterface, and pure sheet resistance Rpure. Furthermore, the characteristics of voltage-coefficient resistor, temperature-coefficient resistor, and resistor mismatching are also studied. An interesting sine-wave voltage-dependent characteristic due to the strong relation to the Rinterface has been modelled in this paper. This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-quarter micron CMOS ULSI technology.

  18. VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications.

    PubMed

    Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

    2014-10-31

    This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 ?m long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association. PMID:25288224

  19. Operation and biasing for single device equivalent to CMOS

    DOEpatents

    Welch, James D. (10328 Pinehurst Ave., Omaha, NE 68124)

    2001-01-01

    Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

  20. Detecting Resistive Shorts for CMOS Domino Circuits Jonathan T.-Y. Chang and Edward J. McCluskey

    E-print Network

    Stanford University

    1 Detecting Resistive Shorts for CMOS Domino Circuits Jonathan T.-Y. Chang and Edward J. Mc-gate resistive shorts. We also propose a new keeper design for CMOS domino circuits. The new keeper design has with testing resistive shorts in CMOS domino circuits. We propose methods to detect resistive shorts in CMOS

  1. Distinct development patterns of c-mos protooncogene expression in female and male mouse germ cells

    SciTech Connect

    Mutter, G.L.; Wolgemuth, D.J.

    1987-08-01

    The protooncogene c-mos is expressed in murine reproductive tissues, producing transcripts of 1.7 and 1.4 kilobases in testis and ovary, respectively. In situ hybridization analysis of c-mos expression in histological sections of mouse ovaries revealed that oocytes are the predominant if not exclusive source of c-mos transcripts. /sup 35/S- or /sup 32/P-labelled RNA probes were transcribed. c-mos transcripts accumulate in growing oocytes, increasing 40- to 90-fold during oocyte and follicular development. c-mos transcripts were also detected in male germ cells and are most abundant after the cells have entered the haploid stage of spermatogenesis. This developmentally regulated pattern of c-mos expression in oocytes and spermatogenic cells suggest that the c-mos gene product may have a function in normal germ-cell differentiation or early embryogenesis.

  2. Commercial Fishing.

    ERIC Educational Resources Information Center

    Florida State Dept. of Education, Tallahassee. Div. of Vocational Education.

    This document is a curriculum framework for a program in commercial fishing to be taught in Florida secondary and postsecondary institutions. This outline covers the major concepts/content of the program, which is designed to prepare students for employment in occupations with titles such as net fishers, pot fishers, line fishers, shrimp boat…

  3. Commercial applications

    NASA Technical Reports Server (NTRS)

    Togai, Masaki

    1990-01-01

    Viewgraphs on commercial applications of fuzzy logic in Japan are presented. Topics covered include: suitable application area of fuzzy theory; characteristics of fuzzy control; fuzzy closed-loop controller; Mitsubishi heavy air conditioner; predictive fuzzy control; the Sendai subway system; automatic transmission; fuzzy logic-based command system for antilock braking system; fuzzy feed-forward controller; and fuzzy auto-tuning system.

  4. Integrated imaging sensor systems with CMOS active pixel sensor technology

    NASA Technical Reports Server (NTRS)

    Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

    2002-01-01

    This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

  5. Low light level CMOS sensor for night vision systems

    NASA Astrophysics Data System (ADS)

    Gross, Elad; Ginat, Ran; Nesher, Ofer

    2015-05-01

    For many years image intensifier tubes were used for night vision systems. In 2014, Elbit systems developed a digital low-light level CMOS sensor, with similar sensitivity to a Gen II image-intensifiers, down to starlight conditions. In this work we describe: the basic principle behind this sensor, physical model for low-light performance estimation and results of field testing.

  6. Single Event Upset Behavior of CMOS Static RAM Cells

    NASA Technical Reports Server (NTRS)

    Lieneweg, Udo; Jeppson, Kjell O.; Buehler, Martin G.

    1993-01-01

    An improved state-space analysis of the CMOS static RAM cell is presented. Introducing theconcept of the dividing line, the critical charge for heavy-ion-induced upset of memory cells can becalculated considering symmetrical as well as asymmetrical capacitive loads. From the criticalcharge, the upset-rate per bit-day for static RAMs can be estimated.

  7. Effects Of Dose Rates On Radiation Damage In CMOS Parts

    NASA Technical Reports Server (NTRS)

    Goben, Charles A.; Coss, James R.; Price, William E.

    1990-01-01

    Report describes measurements of effects of ionizing-radiation dose rate on consequent damage to complementary metal oxide/semiconductor (CMOS) electronic devices. Depending on irradiation time and degree of annealing, survivability of devices in outer space, or after explosion of nuclear weapons, enhanced. Annealing involving recovery beyond pre-irradiation conditions (rebound) detrimental. Damage more severe at lower dose rates.

  8. High speed CMOS/SOS standard cell notebook

    NASA Technical Reports Server (NTRS)

    1978-01-01

    The NASA/MSFC high speed CMOS/SOS standard cell family, designed to be compatible with the PR2D (Place, Route in 2-Dimensions) automatic layout program, is described. Standard cell data sheets show the logic diagram, the schematic, the truth table, and propagation delays for each logic cell.

  9. Mechanically Flexible and High-Performance CMOS Logic Circuits

    PubMed Central

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-01-01

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500?pW/mm at Vin?=?0?V (<7.5?nW/mm at Vin?=?5?V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6?mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

  10. Characterisation of a CMOS charge transfer device for TDI imaging

    NASA Astrophysics Data System (ADS)

    Rushton, J.; Holland, A.; Stefanov, K.; Mayer, F.

    2015-03-01

    The performance of a prototype true charge transfer imaging sensor in CMOS is investigated. The finished device is destined for use in TDI applications, especially Earth-observation, and to this end radiation tolerance must be investigated. Before this, complete characterisation is required. This work starts by looking at charge transfer inefficiency and then investigates responsivity using mean-variance techniques.

  11. A CMOS GENERAL-PURPOSE SAMPLED-DATA ANALOGUE MICROPROCESSOR

    E-print Network

    Dudek, Piotr

    A CMOS GENERAL-PURPOSE SAMPLED-DATA ANALOGUE MICROPROCESSOR Piotr Dudek and Peter J. Hicks.j.hicks@umist.ac.uk Abstract This paper presents a general-purpose sampled-data analogue processing element that essentially functions as an analogue microprocessor (AµP). The AµP executes software programs, in a way akin

  12. High-K materials and Metal Gates for CMOS applications

    E-print Network

    Robertson, John; Wallace, Robert M.

    The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO 2 by a...

  13. Research-grade CMOS image sensors for remote sensing applications

    NASA Astrophysics Data System (ADS)

    Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Martin-Gonthier, Philippe; Corbiere, Franck; Belliot, Pierre; Estribeau, Magali

    2004-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding space applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this paper will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments and performances of CIS prototypes built using an imaging CMOS process will be presented in the corresponding section.

  14. Research-grade CMOS image sensors for demanding space applications

    NASA Astrophysics Data System (ADS)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2004-06-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  15. Integrated Device Technology, Inc. CMOS SyncFIFOTM

    E-print Network

    Berns, Hans-Gerd

    -impedance state · Advanced submicron CMOS technology · Available in the 32-pin plastic leaded chip carrier (PLCC) · All devices, except the 72251, are available in the ceramic leadless chip carrier (LCC) and 32-pin to +85O C) is available (plastic packages only) SyncFIFO is a trademark and the IDT logo is a registered

  16. CMOS Transistor Mismatch Model valid from Weak to Strong Inversion

    E-print Network

    Barranco, Bernabe Linares

    CMOS Transistor Mismatch Model valid from Weak to Strong Inversion Teresa Serrano and PMOS transistors for 30 different geometries has been done with this continuos model. The model is able of transistor mismatch is crucial for precision analog design. Using very reduced transistor geometries produces

  17. High-Damping Energy-Harvesting Electrostatic CMOS Charger

    E-print Network

    Rincon-Mora, Gabriel A.

    adjusting the electrical damping force in the transducer is therefore as important as lowering power losses abate the sacrifice, but only to the extent transducer and circuit efficiencies allow. Optimally increases this force, which is what the energy-harvesting 0.35-µm CMOS charger proposed achieves with a 10-n

  18. Characterization and design optimization for CMOS-compatible MEMS

    NASA Astrophysics Data System (ADS)

    Shia, Tim K.; Yang, Shih-I.; Lee, Cheng-Kuo; Yao, Chih-Min; Lee, Mark H.

    2000-08-01

    A new study of characterizing the mechanical properties of the most used CMOS (Complementary Metal Oxide Semiconductor) materials and how to optimize design variables has revealed a convenient method that could be easily applied for many other micro-electro-mechanical device design and fabrication processes. In general thin film material properties are highly process dependent and are strictly connected to the final performance of some devices. While most micro-device designers do perform calculation to some extent before submitting their design to real fabrication process in order to have the accuracy and precision of the calculation is the input set of constituent material parameters. Mechanical properties of thin films are sometimes unavailable from regular CMOS fabrication foundries where many CMOS compatible micro- devices are fabricated in batches. This paper proposed a design and analysis flow to extract the needed material properties by making simple structures using pilot processes at desired foundry service. As the pilot process results come out, varied material properties can be verified by comparing the experimental data and simulation of data of specially designed test keys. Some test key designs have been widely reported [1,2]. As many of the existing test key designs are only concentrating on one layer or two of thin film materials in the test structures, the proposed method could work out for multi-layers of thin film materials at the same time, which comes even closer to the practical needs of CMOS compatible MEMS.

  19. LINEARITY IMPROVEMENT TECHNIQUE FOR CMOS CONTINUOUS-TIME FILTERS

    E-print Network

    Moon, Un-Ku

    LINEARITY IMPROVEMENT TECHNIQUE FOR CMOS CONTINUOUS-TIME FILTERS BY UN-KU MOON B.S., University CONTINUOUS-TIME FILTERS Un-Ku Moon, Ph.D. Department of Electrical and Computer Engineering University and his team at Analog Devices, Seung-Hoon Lee at Sogang Unversity, Korea, for the use of IC layout

  20. Mechanically Flexible and High-Performance CMOS Logic Circuits

    NASA Astrophysics Data System (ADS)

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-10-01

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500?pW/mm at Vin?=?0?V (<7.5?nW/mm at Vin?=?5?V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6?mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices.

  1. CMOS VLSI Layout and Verification of a SIMD Computer

    NASA Technical Reports Server (NTRS)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  2. CMOS Impedance Spectrum Analyzer with Dual-Slope Multiplying ADC

    E-print Network

    Genov, Roman

    CMOS Impedance Spectrum Analyzer with Dual-Slope Multiplying ADC Hamed Mazhab Jafari, Roman Genov analysis (FRA) to extract the real and imaginary components of a biosensor impedance. Two computationally.06mm2 and consumes 42µW of power from a 1.2V supply. I. INTRODUCTION Impedance spectroscopy

  3. A HIGH RESOLUTION, STICTIONLESS, CMOS COMPATIBLE SOI ACCELEROMETER WITH A LOW NOISE, LOW POWER, 0.25M CMOS INTERFACE

    E-print Network

    Ayazi, Farrokh

    schematic of a differential MEMS accelerometer is shown in Fig. 1. The accelerometer consists of a proofA HIGH RESOLUTION, STICTIONLESS, CMOS COMPATIBLE SOI ACCELEROMETER WITH A LOW NOISE, LOW POWER, 0. The in-plane accelerometers were fabricated on 40µm thick SOI substrates using a two-mask, dry

  4. ECE 423 CMOS Integrated Circuits II Catalog Description: Analysis and design of analog integrated circuits in CMOS technology;

    E-print Network

    ECE 423 ­ CMOS Integrated Circuits II Catalog Description: Analysis and design of analog integrated Integrated Circuits, Gray and Meyer, John Wiley & Sons, 2001 (required) Microelectronic Circuits, A. Sedra Integrated Circuits, B. Razavi, McGraw-Hill, 1999 (optional) Students with Disabilities: #12;Accommodations

  5. Performance of PHOTONIS' low light level CMOS imaging sensor for long range observation

    NASA Astrophysics Data System (ADS)

    Bourree, Loig E.

    2014-05-01

    Identification of potential threats in low-light conditions through imaging is commonly achieved through closed-circuit television (CCTV) and surveillance cameras by combining the extended near infrared (NIR) response (800-10000nm wavelengths) of the imaging sensor with NIR LED or laser illuminators. Consequently, camera systems typically used for purposes of long-range observation often require high-power lasers in order to generate sufficient photons on targets to acquire detailed images at night. While these systems may adequately identify targets at long-range, the NIR illumination needed to achieve such functionality can easily be detected and therefore may not be suitable for covert applications. In order to reduce dependency on supplemental illumination in low-light conditions, the frame rate of the imaging sensors may be reduced to increase the photon integration time and thus improve the signal to noise ratio of the image. However, this may hinder the camera's ability to image moving objects with high fidelity. In order to address these particular drawbacks, PHOTONIS has developed a CMOS imaging sensor (CIS) with a pixel architecture and geometry designed specifically to overcome these issues in low-light level imaging. By combining this CIS with field programmable gate array (FPGA)-based image processing electronics, PHOTONIS has achieved low-read noise imaging with enhanced signal-to-noise ratio at quarter moon illumination, all at standard video frame rates. The performance of this CIS is discussed herein and compared to other commercially available CMOS and CCD for long-range observation applications.

  6. A theoretical investigation of spectra utilization for a CMOS based indirect detector for dual energy applications

    NASA Astrophysics Data System (ADS)

    Kalyvas, N.; Martini, N.; Koukou, V.; Michail, C.; Sotiropoulou, P.; Valais, I.; Kandarakis, I.; Fountos, G.

    2015-09-01

    Dual Energy imaging is a promising method for visualizing masses and microcalcifications in digital mammography. Currently commercially available detectors may be suitable for dual energy mammographic applications. The scope of this work was to theoretically examine the performance of the Radeye CMOS digital indirect detector under three low- and high-energy spectral pairs. The detector was modeled through the linear system theory. The pixel size was equal to 22.5?m and the phosphor material of the detector was a 33.9 mg/cm2 Gd2O2S:Tb phosphor screen. The examined spectral pairs were (i) a 40kV W/Ag (0.01cm) and a 70kV W/Cu (0.1cm) target/filter combinations, (ii) a 40kV W/Cd (0.013cm) and a 70kV W/Cu (0.1cm) target/filter combinations and (iii) a 40kV W/Pd (0.008cm) and a 70kV W/Cu (0.1cm) target/filter combinations. For each combination the Detective Quantum Efficiency (DQE), showing the signal to noise ratio transfer, the detector optical gain (DOG), showing the sensitivity of the detector and the coefficient of variation (CV) of the detector output signal were calculated. The second combination exhibited slightly higher DOG (326 photons per X-ray) and lower CV (0.755%) values. In terms of electron output from the RadEye CMOS, the first two combinations demonstrated comparable DQE values; however the second combination provided an increase of 6.5% in the electron output.

  7. Next-generation CMOS active pixel sensors for satellite hybrid optical communications/imaging sensor systems

    NASA Astrophysics Data System (ADS)

    Stirbl, Robert C.; Pain, Bedabrata; Cunningham, Thomas J.; Hancock, Bruce R.; McCarty, Kenneth P.

    1998-12-01

    Given the current choices of (1) an ever increasing population of large numbers of satellites in low-earth orbit (LEO) constellations for commercial and military global coverage systems, or (2) the alternative of smaller count geosynchronous satellite system constellations in high-earth (HEO), of higher cost and complexity, a number of commercial communications and military operations satellite systems designers are investigating the potential advantages and issues of operating in the mid-earth orbit altitudes (MEO) (between LEO and HEO). At these MEO altitudes both total dose and displacement damage can be traded against the system advantages of fewer satellites required. With growing demand for higher bandwidth communication for real-time earth observing satellite sensor systems, and NASA's interplanetary and deep space virtual unmanned exploration missions in stressing radiation environments, JPL is developing the next generation of smart sensors to address these new requirements of: low-cost, high bandwidth, miniaturization, ultra low-power and mission environment ruggedness. Radiation hardened/tolerant Active Pixel Sensor CMOS imagers that can be adaptively windowed with low power, on-chip control, timing, digital output and provide data-channel efficient on-chip compression, high bandwidth optical communications links are being designed and investigated to reduce size, weight and cost for common optics/hybrid architectures.

  8. CMOS VLSI Active-Pixel Sensor for Tracking

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The diagonal-switch and memory addresses would be generated by the on-chip controller. The memory array would be large enough to hold differential signals acquired from all 8 windows during a frame period. Following the rapid sampling from all the windows, the contents of the memory array would be read out sequentially by use of a capacitive transimpedance amplifier (CTIA) at a maximum data rate of 10 MHz. This data rate is compatible with an update rate of almost 10 Hz, even in full-frame operation

  9. Development of a CMOS SOI Pixel Detector

    SciTech Connect

    Arai, Y.; Hazumi, M.; Ikegami, Y.; Kohriki, T.; Tajima, O.; Terada, S.; Tsuboyama, T.; Unno, Y.; Ushiroda, Y.; Ikeda, H.; Hara, K.; Ishino, H.; Kawasaki, T.; Miyake, H.; Martin, E.; Varner, G.; Tajima, H.; Ohno, M.; Fukuda, K.; Komatsubara, H.; Ida, J.; /NONE - OKI ELECTR INDUST TOKYO

    2008-08-19

    We have developed a monolithic radiation pixel detector using silicon on insulator (SOI) with a commercial 0.15 {micro}m fully-depleted-SOI technology and a Czochralski high resistivity silicon substrate in place of a handle wafer. The SOI TEG (Test Element Group) chips with a size of 2.5 x 2.5 mm{sup 2} consisting of 20 x 20 {micro}m{sup 2} pixels have been designed and manufactured. Performance tests with a laser light illumination and a {beta} ray radioactive source indicate successful operation of the detector. We also briefly discuss the back gate effect as well as the simulation study.

  10. Single photon detection and localization accuracy with an ebCMOS camera

    NASA Astrophysics Data System (ADS)

    Cajgfinger, T.; Dominjon, A.; Barbier, R.

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 ?m. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  11. Performance evaluation of a digital intraoral imaging device based on the CMOS photosensor array coupled with an integrated X-ray conversion fiber-optic faceplate

    NASA Astrophysics Data System (ADS)

    Cho, Hyosung; Choi, Sungil; Kim, Jongguk; Koo, Yangseo; Kim, Taewoo; Ro, Changjoon; Lee, Bongsoo; Kim, Sin; Kim, Hokyung

    2007-08-01

    As a continuation of our digital X-ray imaging sensor R&D, we have developed a cost-effective, intraoral imaging device based on the complementary-metal-oxide semiconductor (CMOS) photosensor array coupled with an integrated X-ray conversion fiber-optic faceplate. It consists of a commercially available CMOS photosensor of a 35×35 ?m 2 pixel size and a 688×910 pixel array dimension, and a high-efficiency columnar CsI(Tl) scintillator of a 90 ?m thickness directly deposited on a fiber-optic faceplate of a 6 ?m core size and an 1.46 mm thickness with 85/15 core-cladding ratio (NA˜1.0 in air). The fiber-optic faceplate is a highly X-ray attenuating material that minimizes X-ray absorption on the end CMOS photosensor array, thus, minimizing X-ray induced noise at the photosensor array. It uses a high light-output columnar CsI(Tl) scintillator with a peak spectral emission at 545 nm, giving better spatial resolution, but attenuates some of this light due to interfacial and optical attenuation factors. In this paper, we presented the performance analysis of the intraoral imaging device with experimental measurements and acquired X-ray images in terms of modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE).

  12. CMOS Imaging Device for Optical Imaging of Biological Activities

    NASA Astrophysics Data System (ADS)

    Shishido, Sanshiro; Oguro, Yasuhiro; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Ohta, Jun

    In this paper, we propose a CMOS image sensor device placed on the brain surface or cerebral sulcus (Fig. 1). The device has a photo detector array where a single optical detector is usually used. The proposed imaging device enables the analysis which reflects a surface blood pattern in the observed area. It is also possible to improve effective sensitivity by image processing and to simplify the measurement system by the CMOS sensor device with on-chip light source. We describe the design details and characterization of proposed device. We also demonstrate detection of hemoglobin oxygenation level with external light source, imaging capability of biological activities, and image processing for sensitivity improvement is also realized.

  13. Digital autoradiography using room temperature CCD and CMOS imaging technology

    NASA Astrophysics Data System (ADS)

    Cabello, Jorge; Bailey, Alexis; Kitchen, Ian; Prydderch, Mark; Clark, Andy; Turchetta, Renato; Wells, Kevin

    2007-08-01

    CCD (charged coupled device) and CMOS imaging technologies can be applied to thin tissue autoradiography as potential imaging alternatives to using conventional film. In this work, we compare two particular devices: a CCD operating in slow scan mode and a CMOS-based active pixel sensor, operating at near video rates. Both imaging sensors have been operated at room temperature using direct irradiation with images produced from calibrated microscales and radiolabelled tissue samples. We also compare these digital image sensor technologies with the use of conventional film. We show comparative results obtained with 14C calibrated microscales and 35S radiolabelled tissue sections. We also present the first results of 3H images produced under direct irradiation of a CCD sensor operating at room temperature. Compared to film, silicon-based imaging technologies exhibit enhanced sensitivity, dynamic range and linearity.

  14. High dynamic range CMOS (HDRC) imagers for safety systems

    NASA Astrophysics Data System (ADS)

    Strobel, Markus; Döttling, Dietmar

    2013-04-01

    The first part of this paper describes the high dynamic range CMOS (HDRC®) imager - a special type of CMOS image sensor with logarithmic response. The powerful property of a high dynamic range (HDR) image acquisition is detailed by mathematical definition and measurement of the optoelectronic conversion function (OECF) of two different HDRC imagers. Specific sensor parameters will be discussed including the pixel design for the global shutter readout. The second part will give an outline on the applications and requirements of cameras for industrial safety. Equipped with HDRC global shutter sensors SafetyEYE® is a high-performance stereo camera system for safe three-dimensional zone monitoring enabling new and more flexible solutions compared to existing safety guards.

  15. Monolithic CMOS-MEMS integration for high-g accelerometers

    NASA Astrophysics Data System (ADS)

    Narasimhan, Vinayak; Li, Holden; Tan, Chuan Seng

    2014-10-01

    This paper highlights work-in-progress towards the conceptualization, simulation, fabrication and initial testing of a silicon-germanium (SiGe) integrated CMOS-MEMS high-g accelerometer for military, munition, fuze and shock measurement applications. Developed on IMEC's SiGe MEMS platform, the MEMS offers a dynamic range of 5,000 g and a bandwidth of 12 kHz. The low noise readout circuit adopts a chopper-stabilization technique implementing the CMOS through the TSMC 0.18 µm process. The device structure employs a fully differential split comb-drive set up with two sets of stators and a rotor all driven separately. Dummy structures acting as protective over-range stops were designed to protect the active components when under impacts well above the designed dynamic range.

  16. 324GHz CMOS VCO Using Linear Superimposition Technique

    NASA Technical Reports Server (NTRS)

    Daquan, Huang; LaRocca, Tim R.; Samoska, Lorene A; Fung, Andy; Chang, Frank

    2007-01-01

    Terahertz (frequencies ranged from 300GHz to 3THz) imaging and spectroscopic systems have drawn increasing attention recently due to their unique capabilities in detecting and possibly analyzing concealed objects. The generation of terahertz signals is nonetheless nontrivial and traditionally accomplished by using either free-electron radiation, optical lasers, Gunn diodes or fundamental oscillation by using III-V based HBT/HEMT technology[1-3]... We have substantially extended the operation range of deep-scaled CMOS by using a linear superimposition method, in which we have realized a 324GHz VCO in 90nm digital CMOS with 4GHz tuning range under 1V supply voltage. This may also pave the way for ultra-high data rate wireless communications beyond that of IEEE 802.15.3c and reach data rates comparable to that of fiber optical communications, such as OC768 (40Gbps) and beyond.

  17. A Low-Cost CMOS Programmable Temperature Switch

    PubMed Central

    Li, Yunlong; Wu, Nanjian

    2008-01-01

    A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 ?m CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45—120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 ?A at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

  18. Nanophotonic integration in state-of-the-art CMOS foundries.

    PubMed

    Orcutt, Jason S; Khilo, Anatol; Holzwarth, Charles W; Popovi?, Milos A; Li, Hanqing; Sun, Jie; Bonifield, Thomas; Hollingsworth, Randy; Kärtner, Franz X; Smith, Henry I; Stojanovi?, Vladimir; Ram, Rajeev J

    2011-01-31

    We demonstrate a monolithic photonic integration platform that leverages the existing state-of-the-art CMOS foundry infrastructure. In our approach, proven XeF2 post-processing technology and compliance with electronic foundry process flows eliminate the need for specialized substrates or wafer bonding. This approach enables intimate integration of large numbers of nanophotonic devices alongside high-density, high-performance transistors at low initial and incremental cost. We demonstrate this platform by presenting grating-coupled, microring-resonator filter banks fabricated in an unmodified 28 nm bulk-CMOS process by sharing a mask set with standard electronic projects. The lithographic fidelity of this process enables the high-throughput fabrication of second-order, wavelength-division-multiplexing (WDM) filter banks that achieve low insertion loss without post-fabrication trimming. PMID:21369052

  19. Smart CMOS image sensor for lightning detection and imaging.

    PubMed

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-03-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 ?m pixel pitch has been fabricated using a 0.35 ?m 2P 5M technology and tested to validate the selected detection approach. PMID:23458812

  20. An Accurate Timing Model for Nano CMOS Circuit Considering Statistical Process Variation

    E-print Network

    Ayers, Joseph

    An Accurate Timing Model for Nano CMOS Circuit Considering Statistical Process Variation Ping Liu variations and global parameter variations [1]. Some researchers also define the fluctuations as systematic

  1. Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm

    E-print Network

    Wladyslaw Szczesniak

    2008-01-07

    This paper presents a BPD (Balanced Power Dissipation) heuristic scheduling algorithm applied to VLSI CMOS digital circuits/systems in order to reduce the global computational demand and provide balanced power dissipation of computational units of the designed digital VLSI CMOS system during the task assignment stage. It results in reduction of the average and peak temperatures of VLSI CMOS digital circuits. The elaborated algorithm is based on balanced power dissipation of local computational (processing) units and does not deteriorate the throughput of the whole VLSI CMOS digital system.

  2. Linear dynamic range enhancement in a CMOS imager

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor)

    2008-01-01

    A CMOS imager with increased linear dynamic range but without degradation in noise, responsivity, linearity, fixed-pattern noise, or photometric calibration comprises a linear calibrated dual gain pixel in which the gain is reduced after a pre-defined threshold level by switching in an additional capacitance. The pixel may include a novel on-pixel latch circuit that is used to switch in the additional capacitance.

  3. Attenuation of single event induced pulses in CMOS combinational logic

    SciTech Connect

    Baze, M.P.; Buchner, S.P.

    1997-12-01

    Results are presented of a study of SEU generated transient pulse attenuation in combinational logic structures built using common digital CMOS design practices. SPICE circuit analysis, heavy ion tests, and pulsed, focused laser simulations were used to examine the response characteristics of transient pulse behavior in long logic strings. Results show that while there is an observable effect, it cannot be generally assumed that attenuation will significantly reduce observed circuit bit error rates.

  4. Aluminum nitride on titanium for CMOS compatible piezoelectric transducers.

    PubMed

    Doll, Joseph C; Petzold, Bryan C; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L

    2010-01-01

    Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d(33f), d(31) and d(33) of up to 2.9, -1.9 and 6.5 pm V(-1), respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals. PMID:20333316

  5. Development of CMOS Imager Block for Capsule Endoscope

    NASA Astrophysics Data System (ADS)

    Shafie, S.; Fodzi, F. A. M.; Tung, L. Q.; Lioe, D. X.; Halin, I. A.; Hasan, W. Z. W.; Jaafar, H.

    2014-04-01

    This paper presents the development of imager block to be associated in a capsule endoscopy system. Since the capsule endoscope is used to diagnose gastrointestinal diseases, the imager block must be in small size which is comfortable for the patients to swallow. In this project, a small size 1.5V button battery is used as the power supply while the voltage supply requirements for other components such as microcontroller and CMOS image sensor are higher. Therefore, a voltage booster circuit is proposed to boost up the voltage supply from 1.5V to 3.3V. A low power microcontroller is used to generate control pulses for the CMOS image sensor and to convert the 8-bits parallel data output to serial data to be transmitted to the display panel. The results show that the voltage booster circuit was able to boost the voltage supply from 1.5V to 3.3V. The microcontroller precisely controls the CMOS image sensor to produce parallel data which is then serialized again by the microcontroller. The serial data is then successfully translated to 2fps image and displayed on computer.

  6. CMOS integration of inkjet-printed graphene for humidity sensing.

    PubMed

    Santra, S; Hu, G; Howe, R C T; De Luca, A; Ali, S Z; Udrea, F; Gardner, J W; Ray, S K; Guha, P K; Hasan, T

    2015-01-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things. PMID:26616216

  7. Cryogenic CMOS circuits for single charge digital readout.

    SciTech Connect

    Gurrieri, Thomas M.; Longoria, Erin Michelle; Eng, Kevin; Carroll, Malcolm S.; Hamlet, Jason R.; Young, Ralph Watson

    2010-03-01

    The readout of a solid state qubit often relies on single charge sensitive electrometry. However the combination of fast and accurate measurements is non trivial due to large RC time constants due to the electrometers resistance and shunt capacitance from wires between the cold stage and room temperature. Currently fast sensitive measurements are accomplished through rf reflectrometry. I will present an alternative single charge readout technique based on cryogenic CMOS circuits in hopes to improve speed, signal-to-noise, power consumption and simplicity in implementation. The readout circuit is based on a current comparator where changes in current from an electrometer will trigger a digital output. These circuits were fabricated using Sandia's 0.35 {micro}m CMOS foundry process. Initial measurements of comparators with an addition a current amplifier have displayed current sensitivities of < 1nA at 4.2K, switching speeds up to {approx}120ns, while consuming {approx}10 {micro}W. I will also discuss an investigation of noise characterization of our CMOS process in hopes to obtain a better understanding of the ultimate limit in signal to noise performance.

  8. Development of large and fast cmos aps cameras at latt

    NASA Astrophysics Data System (ADS)

    Beigbeder, F.; Bourrec, E.; Dupieux, M.; Delaigue, G.; Rondi, S.; Rieutord, M.; Meunier, N.; Roudier, T.

    Since 2004, at the Laboratoire d'Astrophysique de Toulouse Tarbes (LATT), we work with CMOS APS detectors, firstly to develop a large-field,high-resolution camera for the observation of the solar supergranulation, secondly to develop a fast camera for an adaptive optics test bench. In these two projects, we use detectors from FillFactory, now continued by Cypress Semiconductor Corporation: IBIS4-14000, IBIS-16000, LUPA-4000, 14 Mpixels, 16 Mpixels, 4 Mpixels respectively. The last one just reads in a 240 × 240 pixels window to obtain readout rate of 1000 Image/s. For these purposes we developed dedicated controllers to follow the high pixel rate and multi-output readout of this type of detectors. We also studied the characterization methods and measured the main parameters of these CMOS detectors to know their behaviour. Using these kinds of APS detectors in these two particular projects proves that we can already find niches to use CMOS detectors in astronomy taking advantage of their present specificities. Recent improvements like back illumination, noise reduction, should rapidly open news possibilities.

  9. Next generation CMOS SSPMs for scintillation detection applications

    NASA Astrophysics Data System (ADS)

    Chen, Xiao J.; Johnson, Erik B.; Stapels, Christopher J.; Whitney, Chad; Christian, James F.

    2012-10-01

    Early CMOS SSPM pixel designs utilize a highly doped layer near the surface as a component for the Geiger junction, which limits the collection of charge from the surface and the UV response of the high gain solid state photodetector. To address these limitations, we are developing a new generation of CMOS SSPMs using pixel elements with a buried layer as a component of the Geiger junction in a process with smaller feature sizes. The new SSPM, an array of newly designed Geiger photodiode elements, is designed and fabricated to provide improvements in blue light response and dark noise performance. This work compares the performance of the early and new CMOS SSPM designs. Results showed ~2-4× improvement of detection efficiency in the blue/shallow UV region (350nm to 450nm), and a 10× reduction in detector dark count rate. Due to higher operating bias, the after pulse multiplier is no larger than a factor of 1.5 larger than the previous design. Inter-pixel cross-talk is similar to previous SSPM designs at comparable Geiger probabilities.

  10. CMOS integration of inkjet-printed graphene for humidity sensing

    PubMed Central

    Santra, S.; Hu, G.; Howe, R. C. T.; De Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-01-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10–80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things. PMID:26616216

  11. Aluminum nitride on titanium for CMOS compatible piezoelectric transducers

    PubMed Central

    Doll, Joseph C; Petzold, Bryan C; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L

    2010-01-01

    Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d33f, d31 and d33 of up to 2.9, ?1.9 and 6.5 pm V?1, respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals. PMID:20333316

  12. First result on biased CMOS MAPs-on-diamond devices

    NASA Astrophysics Data System (ADS)

    Kanxheri, K.; Citroni, M.; Fanetti, S.; Lagomarsino, S.; Morozzi, A.; Parrini, G.; Passeri, D.; Sciortino, S.; Servoli, L.

    2015-10-01

    Recently a new type of device, the MAPS-on-diamond, obtained bonding a thinned to 25 ?m CMOS Monolithic Active Pixel Sensor to a standard 500 ?m pCVD diamond substrate, has been proposed and fabricated, allowing a highly segmented readout (10×10 ?m pixel size) of the signal produced in the diamond substrate. The bonding between the two materials has been obtained using a new laser technique to deliver the needed energy at the interface. A biasing scheme has been adopted to polarize the diamond substrate to allow the charge transport inside the diamond without disrupting the functionalities of the CMOS Monolithic Active Pixel Sensor. The main concept of this class of devices is the capability of the charges generated in the diamond by ionizing radiation to cross the silicon-diamond interface and to be collected by the MAPS photodiodes. In this work we demonstrate that such passage occurs and measure its overall efficiency. This study has been carried out first calibrating the CMOS MAPS with monochromatic X-rays, and then testing the device with charged particles (electrons) either with and without biasing the diamond substrate, to compare the amount of signal collected.

  13. Fully depleted, thick, monolithic CMOS pixels with high quantum efficiency

    NASA Astrophysics Data System (ADS)

    Clarke, A.; Stefanov, K.; Johnston, N.; Holland, A.

    2015-04-01

    The Centre for Electronic Imaging (CEI) has an active programme of evaluating and designing Complementary Metal-Oxide Semiconductor (CMOS) image sensors with high quantum efficiency, for applications in near-infrared and X-ray photon detection. This paper describes the performance characterisation of CMOS devices made on a high resistivity 50 ? m thick p-type substrate with a particular focus on determining the depletion depth and the quantum efficiency. The test devices contain 8 × 8 pixel arrays using CCD-style charge collection, which are manufactured in a low voltage CMOS process by ESPROS Photonics Corporation (EPC). Measurements include determining under which operating conditions the devices become fully depleted. By projecting a spot using a microscope optic and a LED and biasing the devices over a range of voltages, the depletion depth will change, causing the amount of charge collected in the projected spot to change. We determine if the device is fully depleted by measuring the signal collected from the projected spot. The analysis of spot size and shape is still under development.

  14. Modification of standard CMOS technology for cell-based biosensors.

    PubMed

    Graham, A H D; Surguy, S M; Langlois, P; Bowen, C R; Taylor, J; Robbins, J

    2012-01-15

    We present an electrode based on complementary metal oxide semiconductor (CMOS) technology that can be made fully biocompatible and chemically inert using a simple, low-cost and non-specialised process. Since these devices are based on ubiquitous CMOS technology, the integrated circuits can be readily developed to include appropriate amplifiers, filters and wireless subsystems, thus reducing the complexity and cost of external systems. The unprocessed CMOS aluminium electrodes are modified using anodisation and plating techniques which do not require intricate and expensive semiconductor processing equipment and can be performed on the bench-top as a clean-room environment is not required. The resulting transducers are able to detect both the fast electrical activity of neurons and the slow changes in impedance of growing and dividing cells. By using standard semiconductor fabrication techniques and well-established technologies, the approach can form the basis of cell-based biosensors and transducers for high throughput drug discovery assays, neuroprosthetics and as a basic research tool in biosciences. The technology is equally applicable to other biosensors that require noble metal or nanoporous microelectrodes. PMID:22138468

  15. Practicality of Evaluating Soft Errors in Commercial sub-90 nm CMOS for Space Applications

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan A.; LaBel, Kenneth A.

    2010-01-01

    The purpose of this presentation is to: Highlight space memory evaluation evolution, Review recent developments regarding low-energy proton direct ionization soft errors, Assess current space memory evaluation challenges, including increase of non-volatile technology choices, and Discuss related testing and evaluation complexities.

  16. High-gain cryogenic amplifier assembly employing a commercial CMOS operational amplifier

    NASA Astrophysics Data System (ADS)

    Proctor, J. E.; Smith, A. W.; Jung, T. M.; Woods, S. I.

    2015-07-01

    We have developed a cryogenic amplifier for the measurement of small current signals (10 fA-100 nA) from cryogenic optical detectors. Typically operated with gain near 107 V/A, the amplifier performs well from DC to greater than 30 kHz and exhibits noise level near the Johnson limit. Care has been taken in the design and materials to control heat flow and temperatures throughout the entire detector-amplifier assembly. A simple one-board version of the amplifier assembly dissipates 8 mW to our detector cryostat cold stage, and a two-board version can dissipate as little as 17 ?W to the detector cold stage. With current noise baseline of about 10 fA/(Hz)1/2, the cryogenic amplifier is generally useful for cooled infrared detectors, and using blocked impurity band detectors operated at 10 K, the amplifier enables noise power levels of 2.5 fW/(Hz)1/2 for detection of optical wavelengths near 10 ?m.

  17. High-gain cryogenic amplifier assembly employing a commercial CMOS operational amplifier.

    PubMed

    Proctor, J E; Smith, A W; Jung, T M; Woods, S I

    2015-07-01

    We have developed a cryogenic amplifier for the measurement of small current signals (10 fA-100 nA) from cryogenic optical detectors. Typically operated with gain near 10(7) V/A, the amplifier performs well from DC to greater than 30 kHz and exhibits noise level near the Johnson limit. Care has been taken in the design and materials to control heat flow and temperatures throughout the entire detector-amplifier assembly. A simple one-board version of the amplifier assembly dissipates 8 mW to our detector cryostat cold stage, and a two-board version can dissipate as little as 17 ?W to the detector cold stage. With current noise baseline of about 10 fA/(Hz)(1/2), the cryogenic amplifier is generally useful for cooled infrared detectors, and using blocked impurity band detectors operated at 10 K, the amplifier enables noise power levels of 2.5 fW/(Hz)(1/2) for detection of optical wavelengths near 10 ?m. PMID:26233351

  18. Supporting Information Packaging Commercial CMOS Chips for Lab on a Chip Integration

    E-print Network

    Shapiro, Benjamin

    not appear to exhibit a preference for either the Parylene or silicon dioxide surfaces, likely due to the use after deposition of the Parylene passivation layer over the entire wafer, but before the Parylene has been etched. The active area of the chip was protected before Parylene deposition using a thick layer

  19. CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

    NASA Astrophysics Data System (ADS)

    Davidson, Bradley Darren

    This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different WALD fabrication technologies two generations of 2-terminal WALD NEMS switches have been developed. These devices have functional gap heights of 30-50 nm, and actuation voltages typically ranging from 3--5 Volts. Via the extension of a two terminal WALD technology novel 3-terminal WALD NEMS devices were developed. These devices have actuation voltages ranging from 1.5--3 Volts, reliabilities in excess of 2 million cycles, and have been designed to be the fundamental building blocks for WALD NEMS complementary inverters. Through the development of these devices several advancements in the modeling and design of thin-film NEMS devices were achieved. A new model was developed to better characterize pre-actuation currents commonly measured for NEMS switches with nano-scale gate-to-source gap heights. The developed model is an extension of the standard field-emission model and considers the electromechanical response, and electric field effects specific to thin-film NEMS switches. Finally, a multi-physics FEM/FD based model was developed to simulate the dynamic behavior of 2 or 3-terminal electrostatically actuated devices whose electrostatic domains have an aspect ratio on the order of 10-3. The model uses a faux-Lagrangian finite difference method to solve Laplaces equation in a quasi-statatically deforming domain. This model allows for the numerical characterization and design of thin-film NEMS devices not feasible using typical non-specialized BEM/FEM based software. Using this model several novel and feasible designs for fixed-fixed 3-terminal WALD NEMS switches capable for the construction of complementary inverters were discovered.

  20. 5A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 ?m CMOS Process

    PubMed Central

    Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm. PMID:23503294

  1. A zirconium dioxide ammonia microsensor integrated with a readout circuit manufactured using the 0.18 ?m CMOS process.

    PubMed

    Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 ?m complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm. PMID:23503294

  2. Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique.

    PubMed

    Liu, Mao-Chen; Dai, Ching-Liang; Chan, Chih-Hua; Wu, Chyan-Chyi

    2009-01-01

    This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 ?m complementary metal oxide semiconductor (CMOS) process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature. PMID:22399944

  3. 454 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27. NO. 3. MARCH 1992 Multiemitter BiCMOS CML Circuits

    E-print Network

    Elrabaa, Muhammad E. S.

    . Thermal voltage, Vr = 26 mV. I. INTRODUCTION PTIMAL performance of large digital systems re- 0quires the use of CMOS, BiCMOS, and CML (or ECL) logic: CMOS for low-power densed logic and on- chip memories

  4. 16 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 1, JANUARY 2012 Localized Growth of Carbon Nanotubes on CMOS

    E-print Network

    Ural, Ant

    on foundry CMOS substrate using maskless post- CMOS surface micromachining and localized heating techniques-quality CNTs but also a robust fabrication process that is simple and compat- ible with mainstream foundry CMOS microelectromechanical sys- tems (MEMS) structures has been demonstrated [17]­[19], the devices typically have large

  5. CMOS-compatible Titanium Dioxide Deposition for Athermalization of Silicon Photonic Waveguides

    E-print Network

    Yoo, S. J. Ben

    CMOS-compatible Titanium Dioxide Deposition for Athermalization of Silicon Photonic Waveguides@ucdavis.edu , sbyoo@ucdavis.edu Abstract: We discuss titanium dioxide material development for CMOS compatible fabrication and integration of athermal silicon photonic components. Titanium dioxide overclad ring modulators

  6. Rapid Detection of E.Coli Bacteria using Potassium-Sensitive FETs in CMOS

    E-print Network

    Gulak, P. Glenn

    Rapid Detection of E.Coli Bacteria using Potassium-Sensitive FETs in CMOS Nasim Nikkhoo and P Toronto, Canada Abstract--An integrated bacteria detection chip is implemented in 0.18µm CMOS technology to detect the presence of a specific strain of E.coli. The chip successfully identifies the presence

  7. Determining the thermal expansion coefficient of thin films for a CMOS MEMS process using test cantilevers

    NASA Astrophysics Data System (ADS)

    Cheng, Chao-Lin; Tsai, Ming-Han; Fang, Weileun

    2015-02-01

    Many standard CMOS processes, provided by existing foundries, are available. These standard CMOS processes, with stacking of various metal and dielectric layers, have been extensively applied in integrated circuits as well as micro-electromechanical systems (MEMS). It is of importance to determine the material properties of the metal and dielectric films to predict the performance and reliability of micro devices. This study employs an existing approach to determine the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. Test cantilevers with different stacking of metal and dielectric layers for standard CMOS processes have been designed and implemented. The CTEs of standard CMOS films can be determined from measurements of the out-of-plane thermal deformations of the test cantilevers. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacture Company 0.35??m 2P4M CMOS process are characterized. Eight test cantilevers with different stacking of CMOS layers and an auxiliary Si cantilever on a SOI wafer are fabricated. The equivalent elastic moduli and CTEs of the CMOS thin films including the metal and dielectric layers are determined, respectively, from the resonant frequency and static thermal deformation of the test cantilevers. Moreover, thermal deformations of cantilevers with stacked layers different to those of the test beams have been employed to verify the measured CTEs and elastic moduli.

  8. A LOW-POWER CMOS NEURAL AMPLIFIER WITH AMPLITUDE MEASUREMENTS FOR SPIKE SORTING

    E-print Network

    Maryland at College Park, University of

    A LOW-POWER CMOS NEURAL AMPLIFIER WITH AMPLITUDE MEASUREMENTS FOR SPIKE SORTING T. Horiuchi 1 College, PA 16801, USA ABSTRACT Integrated, low-power, low-noise CMOS neural amplifiers have recently are developing low- power neural amplifiers with integrated pre-filtering and measurements of the spike signal

  9. Spike discrimination using amplitude measurements with a low-power CMOS neural amplifier

    E-print Network

    Maryland at College Park, University of

    Spike discrimination using amplitude measurements with a low-power CMOS neural amplifier (Invited, Massachusetts Inst. of Tech., Cambridge, MA 02139, USA Abstract-- Integrated CMOS neural amplifiers have analysis. I. INTRODUCTION Integrated biosignal amplifiers have been designed and reported for different

  10. RF Power Potential of 90 nm CMOS: Device Options, Performance, and Reliability

    E-print Network

    del Alamo, Jesús A.

    of the RF power potential of the various device options offered in a state-of-the-art 90 nm CMOS foundry and reliability. In a modern foundry process, in addition to the nominal digital devices, it is common to offer in a foundry process. Technology The technology that has been studied in this work is a foundry 90 nm CMOS

  11. Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study

    E-print Network

    Mohanty, Saraju P.

    Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study Oleg Garitselov1 , Saraju P. Mohanty2 , Elias Kougianos3 , and Priyadarsan Patra4 NanoSystem Design Laboratory (NSDL, http Abstract--Fast design space exploration of complex nano- CMOS mixed-signal circuits is an important problem

  12. Integrated CMOS DC-DC Converter with Digital Maximum Power Point Tracking for a Portable Thermophotovoltaic

    E-print Network

    Perreault, Dave

    power generator. The design, implemented in 0.35 µm CMOS technology, consists of a low-power control stage and a dc-dc boost power stage with soft-switching capability. With a nominal input voltage of 1 VIntegrated CMOS DC-DC Converter with Digital Maximum Power Point Tracking for a Portable

  13. Integration of GMR-based spin torque oscillators and CMOS circuitry

    NASA Astrophysics Data System (ADS)

    Chen, Tingsu; Eklund, Anders; Sani, Sohrab; Rodriguez, Saul; Malm, B. Gunnar; Åkerman, Johan; Rusu, Ana

    2015-09-01

    This paper demonstrates the integration of giant magnetoresistance (GMR) spin torque oscillators (STO) with dedicated high frequency CMOS circuits. The wire-bonding-based integration approach is employed in this work, since it allows easy implementation, measurement and replacement. A GMR STO is wire-bonded to the dedicated CMOS integrated circuit (IC) mounted on a PCB, forming a (GMR STO + CMOS IC) pair. The GMR STO has a lateral size of 70 nm and more than an octave of tunability in the microwave frequency range. The proposed CMOS IC provides the necessary bias-tee for the GMR STO, as well as electrostatic discharge (ESD) protection and wideband amplification targeting high frequency GMR STO-based applications. It is implemented in a 65 nm CMOS process, offers a measured gain of 12 dB, while consuming only 14.3 mW and taking a total silicon area of 0.329 mm2. The measurement results show that the (GMR STO + CMOS IC) pair has a wide tunability range from 8 GHz to 16.5 GHz and improves the output power of the GMR STO by about 10 dB. This GMR STO-CMOS integration eliminates wave reflections during the signal transmission and therefore exhibits good potential for developing high frequency GMR STO-based applications, which combine the features of CMOS and STO technologies.

  14. 2005 Quantum Electronics and Laser Science Conference (QELS) MSM-Based Integrated CMOS Wavelength Tunable

    E-print Network

    Miller, David A. B.

    JTuC72 2005 Quantum Electronics and Laser Science Conference (QELS) MSM-Based Integrated CMOS: We present a novel MSM wavelength selective photodetector, integrated with its CMOS driver of itself to form an interference pattem on top ofthe fingers ofa metal-semiconductor-metal (MSM

  15. A CMOS Delayed Locked Loop (DLL) for Reducing Clock Skew to Under 500ps

    E-print Network

    Ayers, Joseph

    A CMOS Delayed Locked Loop (DLL) for Reducing Clock Skew to Under 500ps Element Phase detector.400 Abstract Thas paper presents a varaable delay lane DLL car- cuat amplemented an a 0.8 p m CMOS technology-pull type clock synchronazataon scheme. The delay lane can be programmed 6 to 18 stages. The DLL carcuat

  16. 77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-06-06

    ... Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to 19 U.S.C... importation of certain CMOS image sensors and products containing same by reason of infringement of certain... image sensors and products containing same that infringe one or more of claims 1 and 2 of the...

  17. A Redox-Enzyme-Based Electrochemical Biosensor with a CMOS Integrated Bipotentiostat

    E-print Network

    Mason, Andrew

    -enzyme-based fructose biosensor built on a microfabricated IDA and read out by a new CMOS bipotentiostat. This systemA Redox-Enzyme-Based Electrochemical Biosensor with a CMOS Integrated Bipotentiostat Yue Huang, USA, huangyu3@msu.edu Abstract-- This paper presents an electrochemical biosensor featuring redox

  18. Pixel-parallel CMOS active pixel sensor for fast object location Ryan Burns1

    E-print Network

    Hornsey, Richard

    Pixel-parallel CMOS active pixel sensor for fast object location Ryan Burns1 , Christopher Thomas2 A pixel-parallel image sensor readout technique is demonstrated for CMOS active pixel sensors to facilitate a range of applications where the high-speed detection of the presence of an object

  19. Sensors and Actuators A 109 (2003) 102113 Low-cost uncooled infrared detectors in CMOS process

    E-print Network

    Akin, Tayfun

    2003-01-01

    the implementation and comparison of two low-cost uncooled infrared microbolometer detectors that can be imple. Keywords: Uncooled infrared detector; CMOS infrared detector; Microbolometer; Low-cost infrared detector microbolometers using surface micromachined bridges on CMOS processed wafers, where infrared radia- tion increases

  20. A UHF CMOS Transceiver Front-end with a Resonant TR Switch

    E-print Network

    Kuhn, William B.

    . The transceiver's power amplifier (PA) and LNA are simultaneously connected to the antenna and isolated from eachA UHF CMOS Transceiver Front-end with a Resonant TR Switch Jeongmin Jeon, Student Member, IEEE ­- A fully-integrated UHF CMOS transceiver with resonant transmit/receive (T/R) switch is reported

  1. Scaled CMOS Technology Reliability Users Guide

    NASA Technical Reports Server (NTRS)

    White, Mark

    2010-01-01

    The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. A methodology on how to accomplish this and techniques for deriving the expected product-level reliability on commercial memory products are provided.Competing mechanism theory and the multiple failure mechanism model are applied to the experimental results of scaled SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope (beta)=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is presented revealing a power relationship. General models describing the soft error rates across scaled product generations are presented. The analysis methodology may be applied to other scaled microelectronic products and their key parameters.

  2. CMOS digital intra-oral sensor for x-ray radiography

    NASA Astrophysics Data System (ADS)

    Liu, Xinqiao; Byczko, Andrew; Choi, Marcus; Chung, Lap; Do, Hung; Fowler, Boyd; Ispasoiu, Radu; Joshi, Kumar; Miller, Todd; Nagy, Alex; Reaves, David; Rodricks, Brian; Teeter, Doug; Wang, George; Xiao, Feng

    2011-03-01

    In this paper, we present a CMOS digital intra-oral sensor for x-ray radiography. The sensor system consists of a custom CMOS imager, custom scintillator/fiber optics plate, camera timing and digital control electronics, and direct USB communication. The CMOS imager contains 1700 x 1346 pixels. The pixel size is 19.5um x 19.5um. The imager was fabricated with a 0.18um CMOS imaging process. The sensor and CMOS imager design features chamfered corners for patient comfort. All camera functions were integrated within the sensor housing and a standard USB cable was used to directly connect the intra-oral sensor to the host computer. The sensor demonstrated wide dynamic range from 5uGy to 1300uGy and high image quality with a SNR of greater than 160 at 400uGy dose. The sensor has a spatial resolution more than 20 lp/mm.

  3. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

    PubMed

    He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

    2015-01-01

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring. PMID:26184225

  4. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    PubMed Central

    He, Diwei; Morgan, Stephen P.; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R.

    2015-01-01

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring. PMID:26184225

  5. Multiplexed Oversampling Digitizer in 65 nm CMOS for Column-Parallel CCD Readout

    SciTech Connect

    Grace, Carl; Walder, Jean-Pierre; von der Lippe, Henrik

    2012-04-10

    A digitizer designed to read out column-parallel charge-coupled devices (CCDs) used for high-speed X-ray imaging is presented. The digitizer is included as part of the High-Speed Image Preprocessor with Oversampling (HIPPO) integrated circuit. The digitizer module comprises a multiplexed, oversampling, 12-bit, 80 MS/s pipelined Analog-to-Digital Converter (ADC) and a bank of four fast-settling sample-and-hold amplifiers to instrument four analog channels. The ADC multiplexes and oversamples to reduce its area to allow integration that is pitch-matched to the columns of the CCD. Novel design techniques are used to enable oversampling and multiplexing with a reduced power penalty. The ADC exhibits 188 ?V-rms noise which is less than 1 LSB at a 12-bit level. The prototype is implemented in a commercially available 65 nm CMOS process. The digitizer will lead to a proof-of-principle 2D 10 Gigapixel/s X-ray detector.

  6. Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

    PubMed Central

    Kazior, Thomas E.

    2014-01-01

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200?mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

  7. SOI CMOS Imager with Suppression of Cross-Talk

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

    2009-01-01

    A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

  8. Swap intensified WDR CMOS module for I2/LWIR fusion

    NASA Astrophysics Data System (ADS)

    Ni, Yang; Noguier, Vincent

    2015-05-01

    The combination of high resolution visible-near-infrared low light sensor and moderate resolution uncooled thermal sensor provides an efficient way for multi-task night vision. Tremendous progress has been made on uncooled thermal sensors (a-Si, VOx, etc.). It's possible to make a miniature uncooled thermal camera module in a tiny 1cm3 cube with <1W power consumption. For silicon based solid-state low light CCD/CMOS sensors have observed also a constant progress in terms of readout noise, dark current, resolution and frame rate. In contrast to thermal sensing which is intrinsic day&night operational, the silicon based solid-state sensors are not yet capable to do the night vision performance required by defense and critical surveillance applications. Readout noise, dark current are 2 major obstacles. The low dynamic range at high sensitivity mode of silicon sensors is also an important limiting factor, which leads to recognition failure due to local or global saturations & blooming. In this context, the image intensifier based solution is still attractive for the following reasons: 1) high gain and ultra-low dark current; 2) wide dynamic range and 3) ultra-low power consumption. With high electron gain and ultra low dark current of image intensifier, the only requirement on the silicon image pickup device are resolution, dynamic range and power consumption. In this paper, we present a SWAP intensified Wide Dynamic Range CMOS module for night vision applications, especially for I2/LWIR fusion. This module is based on a dedicated CMOS image sensor using solar-cell mode photodiode logarithmic pixel design which covers a huge dynamic range (> 140dB) without saturation and blooming. The ultra-wide dynamic range image from this new generation logarithmic sensor can be used directly without any image processing and provide an instant light accommodation. The complete module is slightly bigger than a simple ANVIS format I2 tube with <500mW power consumption.

  9. NV-CMOS HD camera for day/night imaging

    NASA Astrophysics Data System (ADS)

    Vogelsong, T.; Tower, J.; Sudol, Thomas; Senko, T.; Chodelka, D.

    2014-06-01

    SRI International (SRI) has developed a new multi-purpose day/night video camera with low-light imaging performance comparable to an image intensifier, while offering the size, weight, ruggedness, and cost advantages enabled by the use of SRI's NV-CMOS HD digital image sensor chip. The digital video output is ideal for image enhancement, sharing with others through networking, video capture for data analysis, or fusion with thermal cameras. The camera provides Camera Link output with HD/WUXGA resolution of 1920 x 1200 pixels operating at 60 Hz. Windowing to smaller sizes enables operation at higher frame rates. High sensitivity is achieved through use of backside illumination, providing high Quantum Efficiency (QE) across the visible and near infrared (NIR) bands (peak QE <90%), as well as projected low noise (<2h+) readout. Power consumption is minimized in the camera, which operates from a single 5V supply. The NVCMOS HD camera provides a substantial reduction in size, weight, and power (SWaP) , ideal for SWaP-constrained day/night imaging platforms such as UAVs, ground vehicles, fixed mount surveillance, and may be reconfigured for mobile soldier operations such as night vision goggles and weapon sights. In addition the camera with the NV-CMOS HD imager is suitable for high performance digital cinematography/broadcast systems, biofluorescence/microscopy imaging, day/night security and surveillance, and other high-end applications which require HD video imaging with high sensitivity and wide dynamic range. The camera comes with an array of lens mounts including C-mount and F-mount. The latest test data from the NV-CMOS HD camera will be presented.

  10. Double junction photodiode for X-ray CMOS sensor IC

    NASA Astrophysics Data System (ADS)

    Chaoqun, Xu; Ying, Sun; Yan, Han; Dazhong, Zhu

    2014-07-01

    A CMOS compatible P+/Nwell/Psub double junction photodiode pixel was proposed, which can efficiently detect fluorescence from CsI(Tl) scintillation in an X-ray sensor. Photoelectric and spectral responses of P+/Nwell, Nwell/Psub and P+/Nwell/Psub photodiodes were analyzed and modeled. Simulation results show P+/Nwell/Psub photodiode has larger photocurrent than P+/Nwell photodiode and Nwell/Psub photodiode, and its spectral response is more in accordance with CsI(Tl) fluorescence spectrum. Improved P+/Nwell/Psub photodiode detecting CsI(Tl) fluorescence was designed in CSMC 0.5 ?m CMOS process, CTIA (capacitive transimpedance amplifier) architecture was used to readout photocurrent signal. CMOS X-ray sensor IC prototype contains 8 × 8 pixel array and pixel pitch is 100 × 100 ?m2. Testing results show the dark current of the improved P+/Nwell/Psub photodiode (6.5 pA) is less than that of P+/Nwell and P+/Nwell/Psub photodiodes (13 pA and 11 pA respectively). The sensitivity of P+/Nwell/Psub photodiode is about 20 pA/lux under white LED. The spectrum response of P+/Nwell/Psub photodiode ranges from 400 nm to 800 nm with a peak at 532 nm, which is in accordance with the fluorescence spectrum of CsI(Tl) in an indirect X-ray sensor. Preliminary testing results show the sensitivity of X-ray sensor IC under Cu target X-ray is about 0.21 V·m2/W or 5097e-/pixel @ 8.05 keV considering the pixel size, integration time and average energy of X-ray photons.

  11. Radiation-hard silicon gate bulk CMOS cell family

    SciTech Connect

    Gibbon, C. F.; Habing, D. H.; Flores, R. S.

    1980-01-01

    A radiation-hardened bulk silicon gate CMOS technology and a topologically simple, high-performance dual-port cell family utilizing this process have been demonstrated. Additional circuits, including a random logic circuit containing 4800 transistors on a 236 x 236 mil die, are presently being designed and processed. Finally, a joint design-process effort is underway to redesign the cell family in reduced design rules; this results in a factor of 2.5 cell size reduction and a factor of 3 decrease in chip interconnect area. Cell performance is correspondingly improved.

  12. Fabrication of a CMOS compatible pressure sensor for harsh environments

    NASA Astrophysics Data System (ADS)

    Pakula, L. S.; Yang, H.; Pham, H. T. M.; French, P. J.; Sarro, P. M.

    2004-11-01

    The fabrication and characteristics of CMOS compatible absolute pressure sensors for harsh environments are presented in this paper. The sensor which was fabricated using post-processing surface micromachining consists of 100 circular membranes with a total capacity of 14 pF. PECVD SiC was used due to its good mechanical properties, but since SiC has high resistivity, aluminium layers were used for electrodes. The stiction problems were avoided by using polyimide PI2610 as a sacrificial layer. The pressure sensors were fabricated and the change of capacitance over full pressure range, 5 bar, was 3.4 pF.

  13. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

    PubMed Central

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-01-01

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly measures humidity in % RH. PMID:26184204

  14. A CMOS clock and data recovery circuit for intraocular microsystems.

    PubMed

    Prämassing, F; Püttjer, D; Buss, R; Jäger, D

    2002-01-01

    This paper presents the implementation of a clock and data recovery circuit (CDR) for intraocular microsystems. The CDR was designed to minimize chip area and power consumption and to recover the clock and data signals from the incoming data stream. Since the CDR has been designed without any external components it is well suited for being integrated in an intraocular microsystem. Simulation results show that this CDR works with power dissipation of less than 2.4 mW with a single 3.3 V power supply. The simulations are based on a 0.6 micron n-well CMOS single-polysilicon, three-metal technology. PMID:12451805

  15. Silicon nanowires integrated with CMOS circuits for biosensing application

    NASA Astrophysics Data System (ADS)

    Jayakumar, G.; Asadollahi, A.; Hellström, P.-E.; Garidis, K.; Östling, M.

    2014-08-01

    We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

  16. Silicide Nanowires for Low-Resistance CMOS Transistor Contacts.

    NASA Astrophysics Data System (ADS)

    Zollner, Stefan

    2007-03-01

    Transition metal (TM) silicide nanowires are used as contacts for modern CMOS transistors. (Our smallest wires are ˜20 nm thick and ˜50 nm wide.) While much research on thick TM silicides was conducted long ago, materials perform differently at the nanoscale. For example, the usual phase transformation sequences (e.g., Ni, Ni2Si, NiSi, NiSi2) for the reaction of thick metal films on Si no longer apply to nanostructures, because the surface and interface energies compete with the bulk energy of a given crystal structure. Therefore, a NiSi film will agglomerate into hemispherical droplets of NiSi by annealing before it reaches the lowest-energy (NiSi2) crystalline structure. These dynamics can be tuned by addition of impurities (such as Pt in Ni). The Si surface preparation is also a more important factor for nanowires than for silicidation of thick TM films. Ni nanowires formed on Si surfaces that were cleaned and amorphized by sputtering with Ar ions have a tendency to form NiSi2 pyramids (``spikes'') even at moderate temperatures (˜400^oC), while similar Ni films formed on atomically clean or hydrogen-terminated Si form uniform NiSi nanowires. Another issue affecting TM silicides is the barrier height between the silicide contact and the silicon transistor. For most TM silicides, the Fermi level of the silicide is aligned with the center of the Si band gap. Therefore, silicide contacts experience Schottky barrier heights of around 0.5 eV for both n-type and p-type Si. The resulting contact resistance becomes a significant term for the overall resistance of modern CMOS transistors. Lowering this contact resistance is an important goal in CMOS research. New materials are under investigation (for example PtSi, which has a barrier height of only 0.3 eV to p-type Si). This talk will describe recent results, with special emphasis on characterization techniques and electrical testing useful for the development of silicide nanowires for CMOS contacts. In collaboration with: P. Grudowski, D. Jawarani, R. Garcia, M.L. Kottke, R.B. Gregory, X.-D. Wang, D. Theodore, P. Fejes, W.J. Taylor, B.Y. Nguyen, C. Capasso, M. Raymond, D. Denning, K. Chang, R. Noble, M. Jahanbani, S. Bolton, P. Crabtree, D. Goedeke, M. Rossow, M. Chowdhury, H. Desjardins, A.Thean.

  17. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

    PubMed

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-01-01

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly measures humidity in % RH. PMID:26184204

  18. High Precision Thin CMOS Sensors for Future Vertex Detectors

    NASA Astrophysics Data System (ADS)

    Winter, M.; Besson, A.; Deveaux, M.; Gay, A.; Gaycken, G.; Grandjean, D.; Himmi, A.; Hu, C.; Valin, I.; Claus, G.; Colledani, C.; Deptuch, G.; Dulinski, W.

    2004-07-01

    CMOS pixel sensors are developed at IReS-LEPSI since 1999 for future vertex detectors needing very high granularity and minimal material budget. The first prototypes, made of small arrays of a few thousands of pixels, demonstrated the viability of the technology and its high tracking performances. In the last two years, new results on the radiation tolerance and tracking performances of the sensors were obtained, and the first real scale prototype was fabricated and tested. Moreover, a new manufacturing technology was investigated, without epitaxial layer but based on a lightly doped substrate. The contribution summarises the performances observed and provides an outlook on the sensor applications.

  19. Autonomous pedestrian localization technique using CMOS camera sensors

    NASA Astrophysics Data System (ADS)

    Chun, Chanwoo

    2014-09-01

    We present a pedestrian localization technique that does not need infrastructure. The proposed angle-only measurement method needs specially manufactured shoes. Each shoe has two CMOS cameras and two markers such as LEDs attached on the inward side. The line of sight (LOS) angles towards the two markers on the forward shoe are measured using the two cameras on the other rear shoe. Our simulation results shows that a pedestrian walking down in a shopping mall wearing this device can be accurately guided to the front of a destination store located 100m away, if the floor plan of the mall is available.

  20. 120-MHz BiCMOS superscalar RISC processor

    NASA Astrophysics Data System (ADS)

    Tanaka, Shigeya; Hotta, Takashi; Murabayashi, Fumio; Yamada, Hiromichi; Yoshida, Shoji; Shimamura, Kotaro; Katsura, Koyo; Bandoh, Tadaaki; Ikeda, Koichi; Matsubara, Kenji

    1994-04-01

    A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm x 16.5 mm, and utilizes 3.3 V/0.5 micron BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design.

  1. The DUV Stability of Superlattice-Doped CMOS Detector Arrays

    NASA Technical Reports Server (NTRS)

    Hoenk, M. E.; Carver, A. G.; Jones, T.; Dickie, M.; Cheng, P.; Greer, H. F.; Nikzad, S.; Sgro, J.; Tsur, S.

    2013-01-01

    JPL and Alacron have recently developed a high performance, DUV camera with a superlattice doped CMOS imaging detector. Supperlattice doped detectors achieve nearly 100% internal quantum efficiency in the deep and far ultraviolet, and a single layer, Al2O3 antireflection coating enables 64% external quantum efficiency at 263nm. In lifetime tests performed at Applied Materials using 263 nm pulsed, solid state and 193 nm pulsed excimer laser, the quantum efficiency and dark current of the JPL/Alacron camera remained stable to better than 1% precision during long-term exposure to several billion laser pulses, with no measurable degradation, no blooming and no image memory at 1000 fps.

  2. Charge collection in submicron CMOS/SOI technology

    SciTech Connect

    Musseau, O.; Ferlet-Cavrois, V.; Campbell, A.B.; Knudson, A.R.; Stapor, W.J.; McDonald, P.T.; Pelloie, J.L.; Raynaud, C.

    1997-12-01

    The authors present experimental measurements of charge collection spectroscopy from high energy ion strikes in submicron CMOS/SOI devices. Due to the specific structure of SOI technology, with symmetrical source and drain junctions, a direct equivalence between upset mechanism and charge collection is established. The bipolar mechanism, responsible for the amplification of the deposited charge is discussed based on 2D device simulations. Based on the experimental data the authors determine qualitatively the influence of transistor geometry on the bipolar gain. Finally the limits of the usual SEU concepts (LET threshold and cross section) are discussed for scaled devices.

  3. Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS).

    PubMed

    Loughran, Brendan; Swetadri Vasan, S N; Singh, Vivek; Ionita, Ciprian N; Jain, Amit; Bednarek, Daniel R; Titus, Albert; Rudin, Stephen

    2013-03-01

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 ?m pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems. PMID:24353389

  4. Design considerations for a new high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS)

    NASA Astrophysics Data System (ADS)

    Loughran, Brendan; Swetadri Vasan, S. N.; Singh, Vivek; Ionita, Ciprian N.; Jain, Amit; Bednarek, Daniel R.; Titus, Albert H.; Rudin, Stephen

    2013-03-01

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 ?m pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

  5. A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

    NASA Technical Reports Server (NTRS)

    Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

    2014-01-01

    Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

  6. IR CMOS: near infrared enhanced digital imaging (Presentation Recording)

    NASA Astrophysics Data System (ADS)

    Pralle, Martin U.; Carey, James E.; Joy, Thomas; Vineis, Chris J.; Palsule, Chintamani

    2015-08-01

    SiOnyx has demonstrated imaging at light levels below 1 mLux (moonless starlight) at video frame rates with a 720P CMOS image sensor in a compact, low latency camera. Low light imaging is enabled by the combination of enhanced quantum efficiency in the near infrared together with state of the art low noise image sensor design. The quantum efficiency enhancements are achieved by applying Black Silicon, SiOnyx's proprietary ultrafast laser semiconductor processing technology. In the near infrared, silicon's native indirect bandgap results in low absorption coefficients and long absorption lengths. The Black Silicon nanostructured layer fundamentally disrupts this paradigm by enhancing the absorption of light within a thin pixel layer making 5 microns of silicon equivalent to over 300 microns of standard silicon. This results in a demonstrate 10 fold improvements in near infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Applications include surveillance, nightvision, and 1064nm laser see spot. Imaging performance metrics will be discussed. Demonstrated performance characteristics: Pixel size : 5.6 and 10 um Array size: 720P/1.3Mpix Frame rate: 60 Hz Read noise: 2 ele/pixel Spectral sensitivity: 400 to 1200 nm (with 10x QE at 1064nm) Daytime imaging: color (Bayer pattern) Nighttime imaging: moonless starlight conditions 1064nm laser imaging: daytime imaging out to 2Km

  7. Illumination robust change detection with CMOS imaging sensors

    NASA Astrophysics Data System (ADS)

    Rengarajan, Vijay; Gupta, Sheetal B.; Rajagopalan, A. N.; Seetharaman, Guna

    2015-05-01

    Change detection between two images in the presence of degradations is an important problem in the computer vision community, more so for the aerial scenario which is particularly challenging. Cameras mounted on moving platforms such as aircrafts or drones are subject to general six-dimensional motion as the motion is not restricted to a single plane. With CMOS cameras increasingly in vogue due to their low power consumption, the inevitability of rolling-shutter (RS) effect adds to the challenge. This is caused by sequential exposure of rows in CMOS cameras unlike conventional global shutter cameras where all pixels are exposed simultaneously. The RS effect is particularly pronounced in aerial imaging since each row of the imaging sensor is likely to experience a different motion. For fast-moving platforms, the problem is further compounded since the rows are also affected by motion blur. Moreover, since the two images are shot at different times, illumination differences are common. In this paper, we propose a unified computational framework that elegantly exploits the scarcity constraint to deal with the problem of change detection in images degraded by RS effect, motion blur as well as non-global illumination differences. We formulate an optimization problem where each row of the distorted image is approximated as a weighted sum of the corresponding rows in warped versions of the reference image due to camera motion within the exposure period to account for geometric as well as photometric differences. The method has been validated on both synthetic and real data.

  8. A CMOS active pixel sensor for retinal stimulation

    NASA Astrophysics Data System (ADS)

    Prydderch, Mark L.; French, Marcus J.; Mathieson, Keith; Adams, Christopher; Gunning, Deborah; Laudanski, Jonathan; Morrison, James D.; Moodie, Alan R.; Sinclair, James

    2006-02-01

    Degenerative photoreceptor diseases, such as age-related macular degeneration and retinitis pigmentosa, are the most common causes of blindness in the western world. A potential cure is to use a microelectronic retinal prosthesis to provide electrical stimulation to the remaining healthy retinal cells. We describe a prototype CMOS Active Pixel Sensor capable of detecting a visual scene and translating it into a train of electrical pulses for stimulation of the retina. The sensor consists of a 10 x 10 array of 100 micron square pixels fabricated on a 0.35 micron CMOS process. Light incident upon each pixel is converted into output current pulse trains with a frequency related to the light intensity. These outputs are connected to a biocompatible microelectrode array for contact to the retinal cells. The flexible design allows experimentation with signal amplitudes and frequencies in order to determine the most appropriate stimulus for the retina. Neural processing in the retina can be studied by using the sensor in conjunction with a Field Programmable Gate Array (FPGA) programmed to behave as a neural network. The sensor has been integrated into a test system designed for studying retinal response. We present the most recent results obtained from this sensor.

  9. Review of radiation damage studies on DNW CMOS MAPS

    NASA Astrophysics Data System (ADS)

    Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.; Zucca, S.; Bettarini, S.; Rizzo, G.; Morsani, F.; Bosisio, L.; Rashevskaya, I.; Cindro, V.

    2013-12-01

    Monolithic active pixel sensors fabricated in a bulk CMOS technology with no epitaxial layer and standard resistivity (10 ? cm) substrate, featuring a deep N-well as the collecting electrode (DNW MAPS), have been exposed to ?-rays, up to a final dose of 10 Mrad (SiO2), and to neutrons from a nuclear reactor, up to a total 1 MeV neutron equivalent fluence of about 3.7 ·1013cm-2. The irradiation campaign was aimed at studying the effects of radiation on the most significant parameters of the front-end electronics and on the charge collection properties of the sensors. Device characterization has been carried out before and after irradiations. The DNW MAPS irradiated with 60Co ?-rays were also subjected to high temperature annealing (100 °C for 168 h). Measurements have been performed through a number of different techniques, including electrical characterization of the front-end electronics and of DNW diodes, laser stimulation of the sensors and tests with 55Fe and 90Sr radioactive sources. This paper reviews the measurement results, their relation with the damage mechanisms underlying performance degradation and provides a new comparison between DNW devices and MAPS fabricated in a CMOS process with high resistivity (1 k? cm) epitaxial layer.

  10. 3D integration of sub-surface photonics with CMOS

    NASA Astrophysics Data System (ADS)

    Jalali, Bahram; Indukuri, Tejaswi; Koonath, Prakash

    2006-02-01

    The integration of photonics and electronics on a single silicon substrate requires technologies that can add optical functionalities without significantly sacrificing valuable wafer area. To this end, we have developed an innovative fabrication process, called SIMOX 3-D Sculpting, that enables monolithic optoelectronic integration in a manner that does not compromise the economics of CMOS manufacturing. In this technique, photonic devices are realized in subsurface silicon layers that are separated from the surface silicon layer by an intervening SiO II layer. The surface silicon layer may then be utilized for electronic circuitry. SIMOX 3-D sculpting involves (1) the implantation of oxygen ions into a patterned silicon substrate followed by (2) high temperature anneal to create buried waveguide-based photonic devices. This process has produced subterranean microresonators with unloaded quality factors of 8000 and extinction ratios >20dB. On the surface silicon layers, MOS transistor structures have been fabricated. The small cross-sectional area of the waveguides lends itself to the realization of nonlinear optical devices. We have previously demonstrated spectral broadening and continuum generation in silicon waveguides utilizing Kerr optical nonlinearity. This may be combined with microresonator filters for on-chip supercontiuum generation and spectral carving. The monolithic integration of CMOS circuits and optical modulators with such multi-wavelength sources represent an exciting avenue for silicon photonics.

  11. A CMOS Imager with Focal Plane Compression using Predictive Coding

    NASA Technical Reports Server (NTRS)

    Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

    2007-01-01

    This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

  12. An integrated CMOS high data rate transceiver for video applications

    NASA Astrophysics Data System (ADS)

    Yaping, Liang; Dazhi, Che; Cheng, Liang; Lingling, Sun

    2012-07-01

    This paper presents a 5 GHz CMOS radio frequency (RF) transceiver built with 0.18 ?m RF-CMOS technology by using a proprietary protocol, which combines the new IEEE 802.11n features such as multiple-in multiple-out (MIMO) technology with other wireless technologies to provide high data rate robust real-time high definition television (HDTV) distribution within a home environment. The RF frequencies cover from 4.9 to 5.9 GHz: the industrial, scientific and medical (ISM) band. Each RF channel bandwidth is 20 MHz. The transceiver utilizes a direct up transmitter and low-IF receiver architecture. A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration. The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude (EVM) at -3 dBm output power.

  13. Single phase dynamic CMOS PLA using charge sharing technique

    NASA Technical Reports Server (NTRS)

    Dhong, Y. B.; Tsang, C. P.

    1991-01-01

    A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

  14. Monolithic integration of high bandwidth waveguide coupled Ge photodiode in a photonic BiCMOS process

    NASA Astrophysics Data System (ADS)

    Lischke, S.; Knoll, D.; Zimmermann, L.

    2015-03-01

    Monolithic integration of photonic functionality in the frontend-of-line (FEOL) of an advanced microelectronics technology is a key step towards future communication applications. This combines photonic components such as waveguides, couplers, modulators, and photo detectors with high-speed electronics plus shortest possible interconnects crucial for high-speed performance. Integration of photonics into CMOS FEOL is therefore in development for quite some time reaching 90nm node recently [1]. However, an alternative to CMOS is high-performance BiCMOS, offering significant advantages for integrated photonics-electronics applications with regard to cost and RF performance. We already presented results of FEOL integration of photonic components in a high-performance SiGe:C BiCMOS baseline to establish a novel, photonic BiCMOS process. Process cornerstone is a local-SOI approach which allows us to fabricate SOI-based, thus low-loss photonic components in a bulk BiCMOS environment [2]. A monolithically integrated 10Gbit/sec Silicon modulator with driver was shown here [3]. A monolithically integrated 25Gbps receiver was presented in [4], consisting of 200GHz bipolar transistors and CMOS devices, low-loss waveguides, couplers, and highspeed Ge photo diodes showing 3-dB bandwidth of 35GHz, internal responsivity of more than 0.6A/W at ?= 1.55?m, and ~ 50nA dark current at 1V. However, the BiCMOS-given thermal steps cause a significant smearing of the Germanium photo diodes doping profile, limiting the photo diode performance. Therefore, we introduced implantation of non-doping elements to overcome such limiting factors, resulting in photo diode bandwidths of more than 50GHz even under the effect of thermal steps necessary when the diodes are integrated in a high performance BiCMOS process.

  15. Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

    NASA Technical Reports Server (NTRS)

    Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

    2009-01-01

    In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

  16. CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

    PubMed Central

    Guo, Nan; Cheung, Ka Wai; Wong, Hiu Tung; Ho, Derek

    2014-01-01

    Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art. PMID:25365460

  17. Top-Down CMOS-NEMS Polysilicon Nanowire with Piezoresistive Transduction

    PubMed Central

    Marigó, Eloi; Sansa, Marc; Pérez-Murano, Francesc; Uranga, Arantxa; Barniol, Núria

    2015-01-01

    A top-down clamped-clamped beam integrated in a CMOS technology with a cross section of 500 nm × 280 nm has been electrostatic actuated and sensed using two different transduction methods: capacitive and piezoresistive. The resonator made from a single polysilicon layer has a fundamental in-plane resonance at 27 MHz. Piezoresistive transduction avoids the effect of the parasitic capacitance assessing the capability to use it and enhance the CMOS-NEMS resonators towards more efficient oscillator. The displacement derived from the capacitive transduction allows to compute the gauge factor for the polysilicon material available in the CMOS technology. PMID:26184222

  18. High-performance VGA-resolution digital color CMOS imager

    NASA Astrophysics Data System (ADS)

    Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

    1999-04-01

    This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be suitable for a variety of color imaging applications including still/full motion imaging, security/surveillance, and teleconferencing/multimedia among other high performance, cost sensitive, low power consumer applications.

  19. Post assembly process development for Monolithic OptoPill integration on silicon CMOS

    E-print Network

    Lei, Yi-Shu Vivian, 1979-

    2004-01-01

    Monolithic OptoPill integration by means of recess mounting is a heterogeneous technique employed to integrate III-V photonic devices on silicon CMOS circuits. The goal is to create an effective fabrication process that ...

  20. Mutation analysis of the c-mos proto-oncogene in human ovarian teratomas.

    PubMed

    de Foy, K A; Gayther, S A; Colledge, W H; Crockett, S; Scott, I V; Evans, M J; Ponder, B A

    1998-05-01

    Female transgenic mice lacking a functional c-mos proto-oncogene develop ovarian teratomas, indicating that c-mos may behave as a tumour-suppressor gene for this type of tumour. We have analysed the entire coding region of the c-MOS gene in a series of human ovarian teratomas to determine whether there are any cancer-causing alterations. DNA from twenty teratomas was analysed by single-strand conformational analysis (SSCA) and heteroduplex analysis (HA) to screen for somatic and germline mutations. In nine of these tumours the entire gene was also sequenced. A previously reported polymorphism and a single new sequence variant were identified, neither of which we would predict to be disease-causing alterations. These results suggest that mutations in the coding region of the c-MOS gene do not play a significant role in the genesis of human ovarian teratomas. PMID:9635841

  1. Substrate engineering for monolithic integration of III-V semiconductors with Si CMOS technology

    E-print Network

    Dohrman, Carl Lawrence

    2008-01-01

    Ge virtual substrates, fabricated using Si1-xGex-.Ge, compositionally graded buffers, enable the epitaxial growth of device-quality GaAs on Si substrates, but monolithic integration of III-V semiconductors with Si CMOS ...

  2. Development of monolithic CMOS-compatible visible light emitting diode arrays on silicon

    E-print Network

    Chilukuri, Kamesh

    2006-01-01

    The synergies associated with integrating Si-based CMOS ICs and III-V-material-based light-emitting devices are very exciting and such integration has been an active area of research and development for quite some time ...

  3. A modular process for integrating thick polysilicon MEMS devices with sub-micron CMOS

    E-print Network

    Afshari, Ehsan

    ) and CMOS integration is required to increase poly mass and stiffness, and reduce electrical parasitics: Mod MEMS process flow. 1. 6000A sensor oxide grown with LOCOS process 2. Blanket nitride for release

  4. Analysis of Power-Clocked CMOS with Application to the Design of Energy-Recovery Circuits*

    E-print Network

    Pedram, Massoud

    Analysis of Power-Clocked CMOS with Application to the Design of Energy-Recovery Circuits* Massoud 90089, USA Tel: +1-213-740-4458 Fax: +1-213-740-7290 email: massoud@zugros.usc.edu Xunwei Wu Institute

  5. SI-based unreleased hybrid MEMS-CMOS resonators in 32nm technology

    E-print Network

    Marathe, Radhika A.

    This work presents the first unreleased Silicon resonators fabricated at the transistor level of a standard CMOS process, and realized without any release steps or packaging. These unreleased bulk acoustic resonators are ...

  6. Nano-scale metal contacts for future III-V CMOS

    E-print Network

    Guo, Alex

    2012-01-01

    As modem transistors continue to scale down in size, conventional Si CMOS is reaching its physical limits and alternative technologies are needed to extend Moore's law. Among different candidates, MOSFETs with a III-V ...

  7. Monolithic electronic-photonic integration in state-of-the-art CMOS processes

    E-print Network

    Orcutt, Jason S. (Jason Scott)

    2012-01-01

    As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. ...

  8. Anodic Ta 2O 5 for CMOS compatible low voltage electrowetting-on-dielectric device fabrication

    NASA Astrophysics Data System (ADS)

    Li, Y.; Parkes, W.; Haworth, L. I.; Stokes, A. A.; Muir, K. R.; Li, P.; Collin, A. J.; Hutcheon, N. G.; Henderson, R.; Rae, B.; Walton, A. J.

    2008-09-01

    This paper reports a CMOS compatible fabrication procedure that enables electrowetting-on-dielectric (EWOD) technology to be post-processed on foundry CMOS technology. With driving voltages less than 15 V it is believed to be the lowest reported driving voltage for any material system compatible with post-processing on completed integrated circuits wafers. The process architecture uses anodically grown tantalum pentoxide as a pinhole free high dielectric constant insulator with an overlying 16 nm layer of Teflon-AF®, which provides the hydrophobic surface for droplets manipulation. This stack provides a very robust dielectric, which maintains a sufficiently high capacitance per unit area for effective operation at a reduced voltage (15 V) which is more compatible with standard CMOS technology. The paper demonstrates that the sputtered tantalum layer used for the electrodes and the formation of the insulating dielectric can readily be integrated with both aluminium and copper interconnect used in foundry CMOS.

  9. CMOS Integrated Circuit Design for Ultra-Wideband Transmitters and Receivers 

    E-print Network

    Xu, Rui

    2010-10-12

    performance components for UWB signal generation, down-conversion, as well as accurate timing control using low cost CMOS technology. We proposed, designed and fabricated a carrier based UWB transmitter to facilitate the discrete feature of the UWB signal...

  10. Radiation Performance of 1 Gbit DDR SDRAMs Fabricated in the 90 nm CMOS Technology Node

    NASA Technical Reports Server (NTRS)

    Ladbury, Raymond L.; Gorelick, Jerry L.; Berg, M. D.; Kim, H.; LaBel, K.; Friendlich, M.; Koga, R.; George, J.; Crain, S.; Yu, P.; Reed, R. A.

    2006-01-01

    We present Single Event Effect (SEE) and Total Ionizing Dose (TID) data for 1 Gbit DDR SDRAMs (90 nm CMOS technology) as well as comparing this data with earlier technology nodes from the same manufacturer.

  11. Low power RF CMOS phase-shifting dual modulus (16/17) prescaler 

    E-print Network

    Duggal, Abhishek

    2000-01-01

    performance is analyzed. The overall system implementation is described at the transistor level and its simulation results are presented. A layout in 0.5u CMOS AMI technology is presented and the important layout considerations are discussed....

  12. Platform for monolithic integration of III-V devices with Si CMOS technology

    E-print Network

    Pacella, Nan Yang

    2012-01-01

    Monolithic integration of III-V compound semiconductors and Si complementary metal-oxide- semiconductor (CMOS) enables the creation of advanced circuits with new functionalities. In order to merge the two technologies, ...

  13. Compressive Sensing Based Bio-Inspired Shape Feature Detection CMOS Imager

    NASA Technical Reports Server (NTRS)

    Duong, Tuan A. (Inventor)

    2015-01-01

    A CMOS imager integrated circuit using compressive sensing and bio-inspired detection is presented which integrates novel functions and algorithms within a novel hardware architecture enabling efficient on-chip implementation.

  14. Current mode integrators and their applications in low-voltage high frequency CMOS signal processing 

    E-print Network

    Smith, Sterling Lane

    1993-01-01

    Low voltage CMOS fully differential integrators for high frequency continuous-time filters using current-mode techniques are presented.. Current mode techniques are employed to avoid the use of the floating differential ...

  15. ''Normal'' tissues from humans exposed to radium contain an alteration in the c-mos locus

    SciTech Connect

    Huberman, E.; Schlenker, R.A.; Hardwick, J.P.

    1989-01-01

    The structures of a number of human proto-oncogenes from persons with internal systemic exposure to radium were analyzed by restriction enzyme digestion and southern blotting of their DNA. Two extra c-mos Eco R1 restriction-fragment-length bands of 5.0 kb and 5.5 kb were found in tissue DNA from six of seven individuals. The extra c-mos bands were detected in DNA from many, but not all, of the tissues of the individuals exposed to radium. Our results suggest that the c-mos restriction-fragment-length alterations (RFLA) found in individuals exposed to radium were induced rather than inherited, are epigenetic in origin, and most likely result from changes in the methylation of bases surrounding the single exon of the c-mos proto-oncogene. 7 refs., 3 figs., 2 tabs.

  16. Silicon CMOS Ohmic Contact Technology for Contacting III-V Compound Materials

    E-print Network

    Pacella, Nan Y.

    Silicon (Si)-encapsulated III-V compound (III-V) device layers enable Si-complementary metal-oxide semiconductor (CMOS) friendly ohmic contact formation to III-V compound devices, allowing for the ultimate seamless planar ...

  17. An Improved Equivalent Simulation Model for CMOS Integrated Hall Plates

    PubMed Central

    Xu, Yue; Pan, Hong-Bin

    2011-01-01

    An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model’s simulation results are in good agreement with the classic experimental results reported in the literature. PMID:22163955

  18. CMOS APS detector characterization for quantitative X-ray imaging

    NASA Astrophysics Data System (ADS)

    Endrizzi, Marco; Oliva, Piernicola; Golosio, Bruno; Delogu, Pasquale

    2013-03-01

    An X-ray Imaging detector based on CMOS Active Pixel Sensor and structured scintillator is characterized for quantitative X-ray imaging in the energy range 11-30 keV. Linearity, dark noise, spatial resolution and flat-field correction are the characteristics of the detector subject of investigation. The detector response, in terms of mean Analog-to-Digital Unit and noise, is modeled as a function of the energy and intensity of the X-rays. The model is directly tested using monochromatic X-ray beams and it is also indirectly validated by means of polychromatic X-ray-tube spectra. Such a characterization is suitable for quantitative X-ray imaging and the model can be used in simulation studies that take into account the actual performance of the detector.

  19. A CMOS single-supply logarithmic amplifier for hearing aids

    NASA Astrophysics Data System (ADS)

    Jarng, Soon Suck; Chen, Lingfeng; Kwon, You Jung

    2005-12-01

    The Log Amplifier described in this paper is designed for hearing aids (HA) application. It works on a low single-supply voltage (1.3V). The input signal varies between 0.01mV and 100mV. To give enough compensation to the hearing impairment, the amplifier provides a very large gain. The output swing is limited because of the low supply voltage and the large gain. Therefore, the logarithmic amplifier introduced into the design of HA to compress input signal so that the output distortion can be avoid. Another factor we use it here is that the amplifier has enough sensitivity and gain to deal with the compressed input signal without getting extra distortion coursed by the pre-process on input signal. The short channel CMOS devices play an important role in reduction of the supply voltage. DONG-BU ANAM 0.18 ?m process is selected.

  20. Triple inverter pierce oscillator circuit suitable for CMOS

    DOEpatents

    Wessendorf; Kurt O. (Albuquerque, NM)

    2007-02-27

    An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

  1. A photonics design tool for advanced CMOS nodes

    E-print Network

    Alloatti, Luca; Stojanovic, Vladimir; Popovic, Milos; Ram, Rajeev Jagga

    2015-01-01

    Recently, we have demonstrated large-scale integrated systems with several million transistors and hundreds of photonic elements. Yielding such large-scale integrated systems requires a design-for-manufacture rigor that is embodied in the 10000 to 50000 design rules that these designs must comply within advanced CMOS manufacturing. Here, we present a photonic design automation (PDA) tool which allows automatic generation of layouts without design-rule violations. Our tool is written in SKILL, the native language of the mainstream electric design automation (EDA) software, Cadence. This allows seamless integration of photonic and electronic design in a single environment. The tool leverages intuitive photonic layer definitions, allowing the designer to focus on the physical properties rather than on technology-dependent details. Removal of design-rule violations - based on Manhattan discretization, Boolean and sizing operations - occurs during data preparation from the initial photonic layers to the final mask...

  2. An integrated 16-channel CMOS time to digital converter

    SciTech Connect

    Ljuslin, C.; Christiansen, J.; Marchioro, A.; Klingsheim, O. )

    1994-08-01

    An integrated 16-channel Time to Digital Converter (TDC) for use in the NA48 experiment at CERN has been developed in a 1[mu]m CMOS technology. The resolution is 1.56ns and the total time history is 204.8ms. Buffering of up to 128 hits is done in on-chip FIFOs. The chip area is 25 mm[sup 2]. The vernier circuit consists of a 16-tap voltage-controlled delay chain controlled by a Delay Locked Loop (DLL). Read out is possible at 40 MHz. JTAG/IEEE 1149.1 protocol has been incorporated to allow in-site testing of the chip. The JTAG data path is also used to access internal control and status registers.

  3. An Approach for Self-Timed Synchronous CMOS Circuit Design

    NASA Technical Reports Server (NTRS)

    Walker, Alvernon; Lala, Parag K.

    2001-01-01

    In this letter we present a timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modi@ the circuit clock period. This letter is concluded with an example of the proposed approach applied to a static CMOS ripple-carry adder.

  4. Two CMOS gate arrays for the EPACT experiment

    SciTech Connect

    Winkert, G. . Goddard Space Flight Center)

    1992-08-01

    Two semicustom CMOS digital gate arrays are described in this paper which have been developed for the Energetic Particles: Acceleration, Composition, and Transport (EPACT) experiment. The first device, the 'Event Counters: 16 by 24-bit' (EC1624), implements sixteen 24-bit ripple counters and has flexible counting and readout options. The second device, the 'Serial Transmitter/Receiver' (SXR), is a multi-personality chip that can be used at either end of a serial, synchronous communications data link. It can be configured as a master in a central control unit, or as one of many slaves within remote assemblies. Together a network of SXRs allows for commanding and verification of distributed control signals. Both gate arrays are radiation hardened and qualified for space flight use. The architecture of each chip is presented and the benefits to the experiment summarized.

  5. Thirty Megarad CMOS gate array for spacecraft applications

    NASA Astrophysics Data System (ADS)

    Voss, H. D.; Roffelsen, L.; Hardage, C.; Jones, F. C.

    1984-12-01

    The recent development, testing, qualification, and integration for spacecraft applications of a general purpose, 30 Megarad-hard, CMOS logic gate array having 3000 transistors is reported. Fabricated on a class S radiation-hard line, the gate array operates above 3 MHz (10V) after 10 to the 7th rad(Si) total dose from a Co-60 source. The threshold voltage change is 0.2 volts (0.5 volts) for the n-channel (p-channel) devices under 10V bias conditions. The rad-hard process of the CDI gate array family is mask compatible with the conventional process for cost effective semicustom design. The rad-hard array is presently operating in-orbit on the AMPTE satellite and is planned for instruments to be flown on the CRRES and UARS satellites.

  6. Failure analysis of a half-micron CMOS IC technology

    SciTech Connect

    Liang, A.Y.; Tangyunyong, P.; Bennett, R.S.; Flores, R.S.

    1996-08-01

    We present the results of recent failure analysis of an advanced, 0.5 {mu}m, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.

  7. Off-Line Testing for Bridge Faults in CMOS Domino Logic Circuits

    NASA Technical Reports Server (NTRS)

    Bennett, K.; Lala, P. K.; Busaba, F.

    1997-01-01

    Bridge faults, especially in CMOS circuits, have unique characteristics which make them difficult to detect during testing. This paper presents a technique for detecting bridge faults which have an effect on the output of CMOS Domino logic circuits. The faults are modeled at the transistor level and this technique is based on analyzing the off-set of the function during off-line testing.

  8. Hybrid CMOS-MQCA Logic Architectures using Multi-Layer Spintronic Devices

    E-print Network

    Das, Jayita; Rajaram, Srinath; Bhanja, Sanjukta

    2011-01-01

    We present a novel hybrid CMOS-MQCA architecture using multi-layer Spintronic devices as computing elements. A feasibility study is presented with 22nm CMOS where new approaches for spin transfer torque induced clocking and read-out scheme for variability-tolerance are introduced. A first-of-its-kind Spintronic device model enables circuit simulation using existing CAD infrastructure. Approximately 70% reduction in energy consumption is observed when compared against conventional field-induced clocking scheme.

  9. Teledyne Imaging Sensors: Silicon CMOS imaging technologies for x-ray, UV, visible, and near infrared

    NASA Astrophysics Data System (ADS)

    Bai, Yibin; Bajaj, Jagmohan; Beletic, James W.; Farris, Mark C.; Joshi, Atul; Lauxtermann, Stefan; Petersen, Anders; Williams, George

    2008-07-01

    Teledyne Imaging Sensors develops and produces high performance silicon-based CMOS image sensors, with associated electronics and packaging for astronomy and civil space. Teledyne's silicon detector sensors use two technologies: monolithic CMOS, and silicon PIN hybrid CMOS. Teledyne's monolithic CMOS sensors are large (up to 59 million pixels), low noise (2.8 e- readout noise demonstrated, 1-2 e- noise in development), low dark current (<10 pA/cm2 at 295K) and can provide in-pixel snapshot shuttering with >103 extinction and microsecond time resolution. The QE limitation of frontside-illuminated CMOS is being addressed with specialized microlenses and backside illumination. A monolithic CMOS imager is under development for laser guide star wavefront sensing. Teledyne's hybrid silicon PIN CMOS sensors, called HyViSITM, provide high QE for the x-ray through near IR spectral range and large arrays (2K×2K, 4K×4K) are being produced with >99.9% operability. HyViSI dark current is 5-10 nA/cm2 (298K), and further reduction is expected from ongoing development. HyViSI presently achieves <10 e- readout noise, and new high speed HyViSI arrays being produced in 2008 should achieve <4 e- readout noise at 900 Hz frame rate. A Teledyne 640×480 pixel HyViSI array is operating in the Mars Reconnaissance Orbiter, a 1K×1K HyViSI array will be launched in 2008 in the Orbiting Carbon Observatory, and HyViSI arrays are under test at several astronomical observatories. The advantages of CMOS in comparison to CCD include programmable readout modes, faster readout, lower power, radiation hardness, and the ability to put specialized processing within each pixel. We present one example of in-pixel processing: event driven readout that is optimal for lightning detection and x-ray imaging.

  10. Commercial Buildings Characteristics, 1992

    SciTech Connect

    Not Available

    1994-04-29

    Commercial Buildings Characteristics 1992 presents statistics about the number, type, and size of commercial buildings in the United States as well as their energy-related characteristics. These data are collected in the Commercial Buildings Energy Consumption Survey (CBECS), a national survey of buildings in the commercial sector. The 1992 CBECS is the fifth in a series conducted since 1979 by the Energy Information Administration. Approximately 6,600 commercial buildings were surveyed, representing the characteristics and energy consumption of 4.8 million commercial buildings and 67.9 billion square feet of commercial floorspace nationwide. Overall, the amount of commercial floorspace in the United States increased an average of 2.4 percent annually between 1989 and 1992, while the number of commercial buildings increased an average of 2.0 percent annually.

  11. Implantable CMOS front-end for nerve-signal sensors

    NASA Astrophysics Data System (ADS)

    Nielsen, Jannik H.; Bruun, Erik

    2005-02-01

    An implantable analog front-end for human nerve signal sensors is presented. The front-end is composed of a low-noise, high-gain pre-amplifier and an analog-to-digital converter (ADC) for quantizing the recorded nerve signal. The front-end is implemented in a 0.35um CMOS technology. The circuit draws 196uA from a 1.8V supply, thus consuming approximately 350uW excluding bias circuitry and buffers. As the signal provided by the nerve signal only has a magnitude of a few microvolts, the pre-amplifier intrinsic noise has to be minimized in order to retain a sufficient signal-to-noise ratio (SNR). A two-stage design for achieving an overall gain of 74dB is employed. For low thermal noise, the first stage is biased at a relatively high current and employs MOS transistors (MOSTs) biased in the weak inversion region. The chopper modulation technique is utilized for shifting low frequency 1/f-noise out of the signal band leaving thermal noise dominant in-band. The measured noise is approximately 7nV/sqrt(Hz) input referred, for a chopping frequency of 20kHz, while the measured gain is 72.5dB over a 4kHz bandwidth. The measured power supply rejection ratio (PSRR) is above 90dB and the common-mode rejection ratio (CMRR) exceeds 105dB inband. The implemented ADC is of the sigma-delta type, and uses a third order continuous-time loop-filter. The loop-filter is implemented using Gm-C integrators, and uses CMOS only for the transconductor implementation. The measured resolution of the manufactured ADC is 10 bits and features a dynamic range (DR) of 67dB at a sampling rate of 1.4MHz.

  12. Research on spaceborne low light detection based on EMCCD and CMOS

    NASA Astrophysics Data System (ADS)

    Wu, Xingxing; Liu, Jinguo; Zhou, Huaide; Zhang, Boyan

    2015-10-01

    Electron Multiplying Charge Coupled Device(EMCCD) can realize read out noise of less than 1e- by promoting gain of charges with the charge multiplication principle and is suitable for low light imaging. With the development of back Illuminated CMOS technology CMOS with high quantum efficiency and less than 1.5e- read noise has been developed by Changchun Institute of Optics, Fine Mechanics and Physics(CIOMP). Spaceborne low light detection cameras based on EMCCD CCD201 and based on CMOS were respectively established and system noise models were founded. Low light detection performance as well as principle of spaceborne camera based on EMCCD and spaceborne camera based on CMOS were compared and analyzed. Results of analysis indicated that signal to noise(SNR) of spaceborne low light detection camera based on EMCCD would be 23.78 as radiance at entrance pupil of the camera was as low as 10-9 W/cm2/sr/?m at the focal plane temperature of 20°C. Spaceborne low light detection camera worked in starring mode and the integration time was 2 second. SNR of low light detection camera based on CMOS would be 27.42 under the same conditions. If cooling systems were used and the temperature was lowered from 20°C to -20°C, SNR of low light detection camera based on EMCCD would be improved to 27.533 while SNR of low light detection camera based on CMOS would be improved to 27.79.

  13. A CMOS-compatible poly-Si nanowire device with hybrid sensor/memory characteristics for System-on-Chip applications.

    PubMed

    Chen, Min-Cheng; Chen, Hao-Yu; Lin, Chia-Yi; Chien, Chao-Hsin; Hsieh, Tsung-Fan; Horng, Jim-Tong; Qiu, Jian-Tai; Huang, Chien-Chao; Ho, Chia-Hua; Yang, Fu-Liang

    2012-01-01

    This paper reports a versatile nano-sensor technology using "top-down" poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically V(th)-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady V(th) adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording. PMID:22666012

  14. Commercialism in Experiential Education.

    ERIC Educational Resources Information Center

    Owen, Steve

    1987-01-01

    Examines perceived threat of commercialism on the ethical foundation of the experiential education movement. Contends that relationship between humanistic values often espoused by experiential educators need not be in conflict with a commercial, profit-oriented perspective. (NEC)

  15. Low threshold vertical cavity surface emitting lasers integrated onto Si-CMOS ICs using novel hybrid assembly techniques

    E-print Network

    Perkins, James Michael, 1978-

    2007-01-01

    A new heterogeneous integration technique has been developed and demonstrated to integrate vertical cavity surface emitting lasers (VCSELs) on silicon CMOS integrated circuits for optical interconnect applications. Individual ...

  16. Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

    NASA Technical Reports Server (NTRS)

    White, Mark; Cooper, Mark; Johnston, Allan

    2011-01-01

    Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

  17. NASA commercial programs

    NASA Technical Reports Server (NTRS)

    1988-01-01

    An expanded role for the U.S. private sector in America's space future has emerged as a key national objective, and NASA's Office of Commercial Programs is providing a focus for action. The Office supports new high technology commercial space ventures, the commercial application of existing aeronautics and space technology, and expanded commercial access to available NASA capabilities and services. The progress NASA has made in carrying out its new assignment is highlighted.

  18. Commercialism in Schools.

    ERIC Educational Resources Information Center

    Larson, Kirstin

    2001-01-01

    This document gives voice to concerns raised by critics and supporters of commercialism in schools and provides brief descriptions of several important resources on this topic. "Commercial Activities in School" (U.S. General Accounting Office) reports on the nature and frequency of commercial activities in public schools, as well as the laws and…

  19. Commercial Radio as Communication.

    ERIC Educational Resources Information Center

    Rothenbuhler, Eric W.

    1996-01-01

    Compares the day-to-day work routines of commercial radio with the principles of a theoretical communication model. Illuminates peculiarities of the conduct of communication by commercial radio. Discusses the application of theoretical models to the evaluation of practicing institutions. Offers assessments of commercial radio deriving from…

  20. COMMERCIAL FOODS, MATHEMATICS - I.

    ERIC Educational Resources Information Center

    DORNFIELD, BLANCHE E.

    THE UNDERSTANDING AND MASTERY OF FUNDAMENTAL MATHEMATICS IS A NECESSARY PART OF COMMERCIAL FOODS WORK. THIS STUDENT HANDBOOK WAS DESIGNED TO ACCOMPANY A COMMERCIAL FOODS COURSE AT THE HIGH SCHOOL LEVEL FOR STUDENTS WITH APPROPRIATE APTITUDES AND COMMERCIAL FOOD SERVICE GOALS. THE MATERIAL, TESTED IN VARIOUS INTERESTED CLASSROOMS, WAS PREPARED BY…

  1. Self-Vth-Cancellation High-Efficiency CMOS Rectifier Circuit for UHF RFIDs

    NASA Astrophysics Data System (ADS)

    Kotani, Koji; Ito, Takashi

    A high-efficiency CMOS rectifier circuit for UHF RFID applications was developed. The rectifier utilizes a self-Vth-cancellation (SVC) scheme in which the threshold voltage of MOSFETs is cancelled by applying gate bias voltage generated from the output voltage of the rectifier itself. A very simple circuit configuration and zero power dissipation characteristics in biasing enable excellent power conversion efficiency (PCE), especially under small RF input power conditions. At higher RF input power conditions, the PCE of the rectifier automatically decreases. This is the built-in self-power-regulation function. The proposed SVC CMOS rectifier was fabricated with a 0.35-µm CMOS process and the measured performance was compared with those of conventional nMOS, pMOS, and CMOS rectifiers and other types of Vth cancellation rectifiers as well. The SVC CMOS rectifier achieves 32% of PCE at the -10dBm RF input power condition. This PCE is larger than rectifiers reported to date under this condition.

  2. Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

    SciTech Connect

    Wang, Zujun Huang, Shaoyan; Liu, Minbo; Xiao, Zhigang; He, Baoping; Yao, Zhibin; Sheng, Jiangkun

    2014-07-15

    The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 ?m CMOS technology. The flux of neutron beams was about 1.33 × 10{sup 8} n/cm{sup 2}s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 10{sup 11}, 5 × 10{sup 11}, and 1 × 10{sup 12} n/cm{sup 2}, respectively. The mean dark signal (K{sub D}), dark signal spike, dark signal non-uniformity (DSNU), noise (V{sub N}), saturation output signal voltage (V{sub S}), and dynamic range (DR) versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike.

  3. Improved Signal Chains for Readout of CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Hancock, Bruce; Cunningham, Thomas

    2009-01-01

    An improved generic design has been devised for implementing signal chains involved in readout from complementary metal oxide/semiconductor (CMOS) image sensors and for other readout integrated circuits (ICs) that perform equivalent functions. The design applies to any such IC in which output signal charges from the pixels in a given row are transferred simultaneously into sampling capacitors at the bottoms of the columns, then voltages representing individual pixel charges are read out in sequence by sequentially turning on column-selecting field-effect transistors (FETs) in synchronism with source-follower- or operational-amplifier-based amplifier circuits. The improved design affords the best features of prior source-follower-and operational- amplifier-based designs while overcoming the major limitations of those designs. The limitations can be summarized as follows: a) For a source-follower-based signal chain, the ohmic voltage drop associated with DC bias current flowing through the column-selection FET causes unacceptable voltage offset, nonlinearity, and reduced small-signal gain. b) For an operational-amplifier-based signal chain, the required bias current and the output noise increase superlinearly with size of the pixel array because of a corresponding increase in the effective capacitance of the row bus used to couple the sampled column charges to the operational amplifier. The effect of the bus capacitance is to simultaneously slow down the readout circuit and increase noise through the Miller effect.

  4. Passive radiation detection using optically active CMOS sensors

    NASA Astrophysics Data System (ADS)

    Dosiek, Luke; Schalk, Patrick D.

    2013-05-01

    Recently, there have been a number of small-scale and hobbyist successes in employing commodity CMOS-based camera sensors for radiation detection. For example, several smartphone applications initially developed for use in areas near the Fukushima nuclear disaster are capable of detecting radiation using a cell phone camera, provided opaque tape is placed over the lens. In all current useful implementations, it is required that the sensor not be exposed to visible light. We seek to build a system that does not have this restriction. While building such a system would require sophisticated signal processing, it would nevertheless provide great benefits. In addition to fulfilling their primary function of image capture, cameras would also be able to detect unknown radiation sources even when the danger is considered to be low or non-existent. By experimentally profiling the image artifacts generated by gamma ray and ? particle impacts, algorithms are developed to identify the unique features of radiation exposure, while discarding optical interaction and thermal noise effects. Preliminary results focus on achieving this goal in a laboratory setting, without regard to integration time or computational complexity. However, future work will seek to address these additional issues.

  5. A 16-channel CMOS preamplifier for laser ranging radar receivers

    NASA Astrophysics Data System (ADS)

    Liu, Ru-qing; Zhu, Jing-guo; Jiang, Yan; Li, Meng-lin; Li, Feng

    2015-10-01

    A 16-channal front-end preamplifier array has been design in a 0.18um CMOS process for pulse Laser ranging radar receiver. This front-end preamplifier array incorporates transimpedance amplifiers(TIAs) and differential voltage post-amplifier(PAMP),band gap reference and other interface circuits. In the circuit design, the regulated cascade (RGC) input stage, Cherry-Hooper and active inductor peaking were employed to enhance the bandwidth. And in the layout design, by applying the layout isolation structure combined with P+ guard-ring(PGR), N+ guard-ring(NGR),and deep-n-well(DNW) for amplifier array, the crosstalk and the substrate noise coupling was reduced effectively. The simulations show that a single channel receiver front-end preamplifier achieves 95 dB? transimpedance gain and 600MHz bandwidth for 3 PF photodiode capacitance. The total power of 16-channel front-end amplifier array is about 800mW for 1.8V supply.

  6. Circuit design for nuclear radiation test of CMOS multiplier chips

    SciTech Connect

    Lim, T.S.; Martin, R.L.; Hughes, H.L.

    1986-09-01

    This paper describes the design of a microprocessor-based electronic circuit to be used in testing the effects of nuclear radiation on a CMOS 8 x 8 multiplier chip. Knowledge of such effects is important for military and space applications of integrated circuits. The multiplier chip undergoing testing is attached to a DUT (device under test) board which is enclosed in a metal container. The container is then lowered to the cobalt 60 radiation source located at the bottom of a 15-ft-deep pool. The gamma-ray radiation test setup is schematically shown. The in-source test board containing the multiplier chip is attached to an 8085-based, single-board microcomputer (SDK-85) by a 30-ft multiconductor cable. Doses of gamma-ray radiation from cobalt 60 are applied in steps at increasing quantities until the multiplier chip, which is tested between doses, begins to malfunction. An 8085 assembly language program is used for functional test of the multiplier. The leakage current and the propagation delay time are also measured between doses.

  7. A CMOS ASIC Design for SiPM Arrays

    PubMed Central

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K.; Miyaoka, Robert S.; Rudell, Jacques C.

    2012-01-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

  8. Design of a CMOS Potentiostat Circuit for Electrochemical Detector Arrays

    PubMed Central

    Ayers, Sunitha; Gillis, Kevin D.; Lindau, Manfred; Minch, Bradley A.

    2010-01-01

    High-throughput electrode arrays are required for advancing devices for testing the effect of drugs on cellular function. In this paper, we present design criteria for a potentiostat circuit that is capable of measuring transient amperometric oxidation currents at the surface of an electrode with submillisecond time resolution and picoampere current resolution. The potentiostat is a regulated cascode stage in which a high-gain amplifier maintains the electrode voltage through a negative feedback loop. The potentiostat uses a new shared amplifier structure in which all of the amplifiers in a given row of detectors share a common half circuit permitting us to use fewer transistors per detector. We also present measurements from a test chip that was fabricated in a 0.5-?m, 5-V CMOS process through MOSIS. Each detector occupied a layout area of 35?m × 15?m and contained eight transistors and a 50-fF integrating capacitor. The rms current noise at 2kHz bandwidth is ? 110fA. The maximum charge storage capacity at 2kHz is 1.26 × 106 electrons. PMID:20514150

  9. PostCMOS compatible sacrificial layers for aluminum nitride microcantilevers

    NASA Astrophysics Data System (ADS)

    Pérez-Campos, Ana; Iriarte, Gonzalo Fuentes; Lebedev, Vadim; Calle, Fernando

    2014-10-01

    This report shows different fabrication procedures followed to obtain piezoelectric microcantilevers. The proposed microcantilever is a sandwich structure composed of chromium (Cr) electrodes (from 50 to 300-nm thick) and a reactive sputtered piezoelectric aluminum nitride (AlN) thin film (from 350 nm to 600-nm thick). The microcantilevers top-view dimensions ranged from 50 to 300 ?m in width and from to 250 to 700 ?m in length. Several materials such as nickel silicide and nickel, as well as a photoresist, and finally the silicon substrate surface have been investigated to discern their possibilities and limitations when used as sacrificial layers. These materials have been studied to determine the optimal processing steps and chemistries required for each of them. The easiest and the only successful microcantilevers release was finally obtained using the top silicon substrate surface as a sacrificial layer. The structural and morphological characteristics of the microcantilevers are presented as well as their piezoelectric character. The main difference of this work resides in the Si surface-based microcantilever release technique. This, along with the synthesis of AlN at room temperature by reactive sputtering, establishes a manufacturing procedure for piezoelectric microbeams, which makes possible the integration of such MEMS devices into postCMOS technology.

  10. A new architecture of current-mode CMOS TDI Sensor

    NASA Astrophysics Data System (ADS)

    Ji, Cheng; Chen, Yongping

    2015-10-01

    Nowadays, CMOS sensors still suffer from the problem of low SNR, especially in the stage of low illumination and high relative scanning velocity. Lots of methods have been develop to overcome this problem. Among these researches, TDI (Time Delay Integration) architecture is a more natural choice, which is natively supported by CCD sensors. In this paper a new kind of proposed current-mode sensor is used to achieve TDI operation in analog domain. The circuit is composed of three main parts. At first, a current-type pixel is proposed, in which the active MOSFET is operated in the triode region to ensure the output current is linearly dependent on the gate voltage and avoid the reduction of threshold voltage in the traditional voltage mode pixels, such as 3T, 4T which use the source followers as its active part. Then a discrete double sampling (DDS) unit, which is operated in the form of currents is used to efficiently reduce the fixed pattern noise (FPN) and make the output is independent of reset voltage of pixels. For accumulation, an improved current mirror adder under controlled of timing circuits is proposed to overcome the problem of saturation suffered in voltage domain. Some main noise sources, especially come from analog sample and holds capacitors and switches is analyzed. Finally, simulation results with CSMC 0.5um technology and Cadence IC show that the proposed method is reasonable and efficient to improve the SNR.

  11. A CMOS pressure sensor tag chip for passive wireless applications.

    PubMed

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-01-01

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation. PMID:25806868

  12. Novel integrated CMOS pixel structures for vertex detectors

    SciTech Connect

    Kleinfelder, Stuart; Bieser, Fred; Chen, Yandong; Gareus, Robin; Matis, Howard S.; Oldenburg, Markus; Retiere, Fabrice; Ritter, Hans Georg; Wieman, Howard H.; Yamamoto, Eugene

    2003-10-29

    Novel CMOS active pixel structures for vertex detector applications have been designed and tested. The overriding goal of this work is to increase the signal to noise ratio of the sensors and readout circuits. A large-area native epitaxial silicon photogate was designed with the aim of increasing the charge collected per struck pixel and to reduce charge diffusion to neighboring pixels. The photogate then transfers the charge to a low capacitance readout node to maintain a high charge to voltage conversion gain. Two techniques for noise reduction are also presented. The first is a per-pixel kT/C noise reduction circuit that produces results similar to traditional correlated double sampling (CDS). It has the advantage of requiring only one read, as compared to two for CDS, and no external storage or subtraction is needed. The technique reduced input-referred temporal noise by a factor of 2.5, to 12.8 e{sup -}. Finally, a column-level active reset technique is explored that suppresses kT/C noise during pixel reset. In tests, noise was reduced by a factor of 7.6 times, to an estimated 5.1 e{sup -} input-referred noise. The technique also dramatically reduces fixed pattern (pedestal) noise, by up to a factor of 21 in our tests. The latter feature may possibly reduce pixel-by-pixel pedestal differences to levels low enough to permit sparse data scan without per-pixel offset corrections.

  13. A CMOS Pressure Sensor Tag Chip for Passive Wireless Applications

    PubMed Central

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-01-01

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of ?20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation. PMID:25806868

  14. 950 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 46, NO. 8, AUGUST 1999 Dynamic and Short-Circuit Power of CMOS

    E-print Network

    Ismail, Yehea

    . 8, AUGUST 1999 Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines and short-circuit power consumption of a complementary metal­oxide­semidconductor (CMOS) gate driving in this paper. Closed-form solutions for the output voltage and short- circuit power of a CMOS gate driving

  15. 178 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 2, FEBRUARY 2004 The Analysis of Dark Signals in the CMOS APS

    E-print Network

    Lee, Jong Duk

    46 10 13 cm2 respectively. Index Terms--CMOS active pixel sensor (APS), dark signals, deep-level bulk- ation in the deep submicron CMOS technology. To implement a low dark current CMOS APS with a deep178 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 2, FEBRUARY 2004 The Analysis of Dark

  16. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 5, MAY 2009 1629 CMOS RF Biosensor Utilizing Nuclear

    E-print Network

    Sun, Nan

    IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 5, MAY 2009 1629 CMOS RF Biosensor Utilizing-cost diagnostics in a portable platform. Index Terms--Biosensor, CMOS integrated circuit, low noise amplifier. Researchers from many areas of science and engi- neering are developing a variety of biosensors, aiming at in

  17. Noise Reduction in CMOS Image Sensors for High Quality Imaging: The Autocorrelation Function Filter on Burst Image Sequences

    E-print Network

    Nielsen, Frank

    : Source and classification of the two types of noise in a CMOS image sensor. The `W' and `C' attributesNoise Reduction in CMOS Image Sensors for High Quality Imaging: The Autocorrelation Function Filter-hiro@waseda.jp Abstract We propose a new method for image noise detection and reduction in complementary metal oxide semi

  18. A Self-Cascoding CMOS Circuit for Low-Power Applications Bedabrata Pain, Robert C. Schober, and Eric R. Fossum

    E-print Network

    Fossum, Eric R.

    A Self-Cascoding CMOS Circuit for Low-Power Applications Bedabrata Pain, Robert C. Schober Institute of Technology, Pasadena, CA, 91109 USA ABSTRACT A self-cascading CMOS circuit for operation in weak inversion is presented. The self-cascoding MOSFET circuit has been shown to exhibit greater than

  19. Abstract --We describe a MEMS-on-CMOS microsystem to encage, culture, and monitor cells. The system was designed

    E-print Network

    Maryland at College Park, University of

    Abstract -- We describe a MEMS-on-CMOS microsystem to encage, culture, and monitor cells. A MEMS process flow was developed for the fabrication of closeable micro-vials to contain each cell, a custom bio-amplifier CMOS chip was designed, fabricated, and tested, and the fabrication of the MEMS

  20. 544 IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 22, NO. 8, APRIL 15, 2010 Photonic Device Layout Within the Foundry CMOS

    E-print Network

    Ram, Rajeev J.

    the Foundry CMOS Design Environment Jason S. Orcutt and Rajeev J. Ram Abstract--A design methodology to layout photonic devices within standard electronic complementary metal­oxide­semicon- ductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs in three foundry scaled

  1. Towards Robust Nano-CMOS Sense Amplifier Design: A Dual-Threshold versus Dual-Oxide Perspective

    E-print Network

    Mohanty, Saraju P.

    Towards Robust Nano-CMOS Sense Amplifier Design: A Dual-Threshold versus Dual-Oxide Perspective research leading to robust nano-CMOS sense amplifier design by incorporating process variation early voltage sense amplifier which is used in most DRAMs. A parametric study is performed through circuit

  2. A Novel High Frequency, High-Efficiency, Differential Class-E Power Amplifier in 0.18m CMOS

    E-print Network

    Heydari, Payam

    for wireless communications in a standard 0.18µm CMOS technology. The power amplifier employs a fully differential class-E topology to achieve high power efficiency by exploiting its soft-switching property) (smaller than 2%), and high power efficiency (in excess of 50%) in the mainstream CMOS technology remains

  3. 1764 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 10, OCTOBER 1997 Frame-Transfer CMOS Active

    E-print Network

    Fossum, Eric R.

    for passive pixels [6], in CMOS APS by a slight change in timing [7], and in more complex compression Active Pixel Sensor with Pixel Binning Zhimin Zhou, Student Member, IEEE, Bedabrata Pain, Member, IEEE, and Eric R. Fossum, Senior Member, IEEE Abstract--The first frame-transfer CMOS active pixel sensor (APS

  4. Impedance Matching Wilkinson Power Dividers in 0.35m SiGe BiCMOS Technology

    E-print Network

    Yanikoglu, Berrin

    1 Impedance Matching Wilkinson Power Dividers in 0.35µm SiGe BiCMOS Technology Ercan Kaymaksut miniature Impedance Matching Wilkinson Power Divider circuits in 0.35µm SiGe BiCMOS technology for on-chip power combining techniques for WLAN applications. The Impedance Matching Wilkinson Power Divider

  5. Lunar Commercialization Workshop

    NASA Technical Reports Server (NTRS)

    Martin, Gary L.

    2008-01-01

    This slide presentation describes the goals and rules of the workshop on Lunar Commercialization. The goal of the workshop is to explore the viability of using public-private partnerships to open the new space frontier. The bulk of the workshop was a team competition to create a innovative business plan for the commercialization of the moon. The public private partnership concept is reviewed, and the open architecture as an infrastructure for potential external cooperation. Some possible lunar commercialization elements are reviewed.

  6. A 0.18 ?m CMOS low-power radiation sensor for asynchronous event-driven UWB wireless transmission

    NASA Astrophysics Data System (ADS)

    Bastianini, S.; Crepaldi, M.; Demarchi, D.; Gabrielli, A.; Lolli, M.; Margotti, A.; Villani, G.; Zhang, Z.; Zoccoli, G.

    2013-12-01

    The paper describes the design of a readout element, proposed as a radiation monitor, which implements an embedded sensor based on a floating-gate transistor. The paper shows the design of a microelectronic circuit composed of a sensor, an oscillator, a modulator, a transmitter and an integrated antenna. A prototype chip has recently been fabricated and tested exploiting a commercial 180 nm, four metal CMOS technology. Simulation results of the entire behavior of the circuit before submission are presented along with some measurements of the actual chip response. In addition, preliminary tests of the performance of the Ultra-Wide Band transmission via the integrated antenna are summarized. As the complete chip prototype area is less than 1 mm2, the chip fits a large variety of applications, from spot radiation monitoring systems in medicine to punctual measurements of radiation level in High-Energy Physics experiments. A sensitivity of 1 mV/rad was estimated within an absorbed dose range up to 10 krad and a total power consumption of about 165 ?W.

  7. Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Lee, M. J.; Brown, D. N.; Chang, J. K.; Ding, D.; Gnani, D.; Grace, C. R.; Jones, J. A.; Kolomensky, Y. G.; von der Lippe, H.; Mcvittie, P. J.; Stettler, M. W.; Walder, J.-P.

    2015-06-01

    We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

  8. A CMOS Time-Resolved Fluorescence Lifetime Analysis Micro-System

    PubMed Central

    Rae, Bruce R.; Muir, Keith R.; Gong, Zheng; McKendry, Jonathan; Girkin, John M.; Gu, Erdan; Renshaw, David; Dawson, Martin D.; Henderson, Robert K.

    2009-01-01

    We describe a CMOS-based micro-system for time-resolved fluorescence lifetime analysis. It comprises a 16 × 4 array of single-photon avalanche diodes (SPADs) fabricated in 0.35 ?m high-voltage CMOS technology with in-pixel time-gated photon counting circuitry and a second device incorporating an 8 × 8 AlInGaN blue micro-pixellated light-emitting diode (micro-LED) array bump-bonded to an equivalent array of LED drivers realized in a standard low-voltage 0.35 ?m CMOS technology, capable of producing excitation pulses with a width of 777 ps (FWHM). This system replaces instrumentation based on lasers, photomultiplier tubes, bulk optics and discrete electronics with a PC-based micro-system. Demonstrator lifetime measurements of colloidal quantum dot and Rhodamine samples are presented. PMID:22291564

  9. A CMOS-compatible, surface-micromachined pressure sensor for aqueous ultrasonic application

    SciTech Connect

    Eaton, W.P.; Smith, J.H.

    1994-12-31

    A surface micromachined pressure sensor array is under development at the Integrated Micromechanics, Microsensors, and CMOS Technologies organization at Sandia National Laboratories. This array is designed to sense absolute pressures from ambient pressure to 650 psia with frequency responses from DC to 2 MHz. The sensor is based upon a sealed, deformable, circular LPCVD silicon nitride diaphragm. Absolute pressure is determined from diaphragm deflection, which is sensed with low-stress, micromechanical, LPCVD polysilicon piezoresistors. All materials and processes used for sensor fabrication are CMOS compatible, and are part of Sandia`s ongoing effort of CMOS integration with Micro-ElectroMechanical Systems (MEMS). Test results of individual sensors are presented along with process issues involving the release etch and metal step coverage.

  10. An arrayed accelerometer device of a wide range of detection for integrated CMOS-MEMS technology

    NASA Astrophysics Data System (ADS)

    Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

    2014-02-01

    This paper reports the design and experimental results of an arrayed accelerometer device in 3 × 3 format that can detect wide range of acceleration between 1G and 20G (1G = 9.8 m/s2). Implemented in a single chip has been performed by gold electroplating for integrated complementary metal oxide semiconductor-microelectromechanical systems (CMOS-MEMS) technology. An equivalent circuit of a MEMS accelerometer has been developed with an electrical circuit simulator to demonstrate the mixed-behavior of the arrayed sensor device and sensing CMOS circuits. Mechanical and electrical crosstalk between the arrayed elements is analyzed on the electrical field distributions. Experimental results show that the resonant frequency and readout capacitance as a function of applied acceleration have been well explained by the results of the multi-physics simulation. As a result, it is confirmed that the proposed device is applicable to an integrated CMOS-MEMS arrayed accelerometer.

  11. Simple BiCMOS CCCTA Design and Resistorless Analog Function Realization

    PubMed Central

    Tangsrirat, Worapong

    2014-01-01

    The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA) in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (Rx) and current transfer (io/iz), are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35??m BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed. PMID:25133230

  12. CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results

    NASA Astrophysics Data System (ADS)

    Rivetti, A.; Battaglia, M.; Bisello, D.; Caselle, M.; Chalmet, P.; Costa, M.; Demaria, N.; Giubilato, P.; Ikemoto, Y.; Kloukinas, K.; Mansuy, C.; Marchioro, A.; Mugnier, H.; Pantano, D.; Potenza, A.; Rousset, J.; Silvestrin, L.; Wyss, J.

    2013-12-01

    The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400 ? cm, which is at least one order of magnitude greater than the typical value (1 - 10 ? cm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported.

  13. Transient radiation hardened CMOS (complementary metal oxide semiconductor) operational amplifiers. Master's thesis

    SciTech Connect

    Trombley, G.J.

    1989-01-01

    General strategies are developed for designing radiation hardened bulk and silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) operational amplifiers. Comparisons are made between each technology concerning photocurrent mechanisms and the inherent advantages of SOI CMOS. Methods are presented for analysing circuit designs and minimizing the net photocurrent responses. Analysis is performed on standard operational amplifier circuits and subcircuits to demonstrate the usefulness of these methods. Radiation hardening topics discussed include superior radiation hardened topologies, photocurrent compensation and its limitations, and methods to ensure a preferred direction of photocurrent response. Several operational amplifier subcircuits are compared for their hardness characteristics. Folded cascode and three-stage operational amplifiers were fabricated on an SOI CMOS test chip supported by Texas Instruments, Incorporated. At the time of publication, the circuit operation was verified but radiation data were not yet available.

  14. Volumetric imaging using single chip integrated CMUT-on-CMOS IVUS array.

    PubMed

    Tekes, Coskun; Zahorian, Jaime; Gurun, Gokce; Satir, Sarp; Xu, Toby; Hochman, Michael; Degertekin, F Levent

    2012-01-01

    An intravascular ultrasound (IVUS) catheter that can provide forward viewing volumetric ultrasound images would be an invaluable clinical tool for guiding interventions. Single chip integration of front-end electronics with capacitive micromachined ultrasonic transducers (CMUTs) is highly desirable to reduce the interconnection complexity and enable miniaturization in IVUS catheters. For this purpose we use the monolithic CMUT-on-CMOS integration where CMUTs are fabricated directly on top of pre-processed CMOS wafers. This minimizes parasitic capacitances associated with connection lines. We have recently implemented a system design including all the required electronics using 0.35-µm CMOS process integrated with a 1.4-mm diameter CMUT array. In this study, we present the experimental volumetric imaging results from an ex-vivo chicken heart phantom. The imaging results demonstrate that the single-chip forward looking IVUS (FL-IVUS) system with monolithically integrated electronics has potential to visualize the front view of coronary arteries. PMID:23366605

  15. Implementation of the CMOS MEMS Condenser Microphone with Corrugated Metal Diaphragm and Silicon Back-Plate

    PubMed Central

    Huang, Chien-Hsin; Lee, Chien-Hsing; Hsieh, Tsung-Min; Tsao, Li-Chi; Wu, Shaoyi; Liou, Jhyy-Cheng; Wang, Ming-Yi; Chen, Li-Che; Yip, Ming-Chuen; Fang, Weileun

    2011-01-01

    This study reports a CMOS-MEMS condenser microphone implemented using the standard thin film stacking of 0.35 ?m UMC CMOS 3.3/5.0 V logic process, and followed by post-CMOS micromachining steps without introducing any special materials. The corrugated diaphragm for the microphone is designed and implemented using the metal layer to reduce the influence of thin film residual stresses. Moreover, a silicon substrate is employed to increase the stiffness of the back-plate. Measurements show the sensitivity of microphone is ?42 ± 3 dBV/Pa at 1 kHz (the reference sound-level is 94 dB) under 6 V pumping voltage, the frequency response is 100 Hz–10 kHz, and the S/N ratio >55 dB. It also has low power consumption of less than 200 ?A, and low distortion of less than 1% (referred to 100 dB). PMID:22163953

  16. Studies for a 10 ?s, thin, high resolution CMOS pixel sensor for future vertex detectors

    NASA Astrophysics Data System (ADS)

    Voutsinas, G.; Amar-Youcef, S.; Baudot, J.; Bertolone, G.; Brogna, A.; Chon-Sen, N.; Claus, G.; Colledani, C.; Dorokhov, A.; Dozière, G.; Dulinski, W.; Degerli, Y.; De Masi, R.; Deveaux, M.; Gelin, M.; Goffe, M.; Hu-Guo, Ch.; Himmi, A.; Jaaskelainen, K.; Koziel, M.; Morel, F.; Müntz, C.; Orsini, F.; Santos, C.; Schrader, C.; Specht, M.; Stroth, J.; Valin, I.; Wagner, F. M.; Winter, M.

    2011-06-01

    Future high energy physics (HEP) experiments require detectors with unprecedented performances for track and vertex reconstruction. These requirements call for high precision sensors, with low material budget and short integration time. The development of CMOS sensors for HEP applications was initiated at IPHC Strasbourg more than 10 years ago, motivated by the needs for vertex detectors at the International Linear Collider (ILC) [R. Turchetta et al, NIM A 458 (2001) 677]. Since then several other applications emerged. The first real scale digital CMOS sensor MIMOSA26 equips Flavour Tracker at RHIC, as well as for the microvertex detector of the CBM experiment at FAIR. MIMOSA sensors may also offer attractive performances for the ALICE upgrade at LHC. This paper will demonstrate the substantial performance improvement of CMOS sensors based on a high resistivity epitaxial layer. First studies for integrating the sensors into a detector system will be addressed and finally the way to go to a 10 ?s readout sensor will be discussed.

  17. A modular process for integrating thick polysilicon MEMS devices with sub-micron CMOS

    NASA Astrophysics Data System (ADS)

    Yasaitis, John A.; Judy, Michael; Brosnihan, Tim; Garone, Peter M.; Pokrovskiy, Nikolay; Sniderman, Debbie; Limb, Scott; Howe, Roger T.; Boser, Bernhard E.; Palaniapan, Moorthi; Jiang, Xuesong; Bhave, Sunil

    2003-01-01

    A new MEMS process module, called Mod MEMS, has been developed to monolithically integrate thick (5-10um), multilayer polysilicon MEMS structures with sub-micron CMOS. This process is particularly useful for advanced inertial MEMS products such as automotive airbag accelerometers where reduced cost and increased functionality is required, or low cost, high performance gyroscopes where thick polysilicon (>6um) and CMOS integration is required to increase poly mass and stiffness, and reduce electrical parasitics in order to optimize angular rate sensing. In this paper we will describe the new modular process flow, development of the critical unit process steps, integration of the module with a foundry sub-micron CMOS process, and provide test data on several inertial designs fabricated with this process.

  18. Integrated microsystems in standard CMOS technology with applications in the field of chemical sensors

    NASA Astrophysics Data System (ADS)

    Baglio, Salvatore; Ando, Bruno; Savalli, Nicolo

    2001-04-01

    In this paper some recent results, regarding the research activity currently in progress in the field of MEMS at the DEES, University of Catania, are reported. In particular some microsystem prototypes, realized by using a standard CMOS process (AMS 0.8 micrometers CMOS) through the EuroPractice service, are described. A novel IC has been realized, it contains several different structures designed both for particular applications and for technology characterization purposes. A set of devices has been realized through 'front side bulk micromachining' and some other novel structures where the polysilicon layer is used as sacrificial layer have been investigated. In order to ensure fully compatibility with CMOS electronics, a wet etching process has been performed by using TMAH. Characterizations of the wet etching process are being performed in order to exploit the absence of crystallographic structure in polysilicon to allow for isotropic etching micromachining. Some applications of Microsystems in different fields are also presented.

  19. Amorphous selenium direct detection CMOS digital x-ray imager with 25 micron pixel pitch

    NASA Astrophysics Data System (ADS)

    Scott, Christopher C.; Abbaszadeh, Shiva; Ghanbarzadeh, Sina; Allan, Gary; Farrier, Michael; Cunningham, Ian A.; Karim, Karim S.

    2014-03-01

    We have developed a high resolution amorphous selenium (a-Se) direct detection imager using a large-area compatible back-end fabrication process on top of a CMOS active pixel sensor having 25 micron pixel pitch. Integration of a-Se with CMOS technology requires overcoming CMOS/a-Se interfacial strain, which initiates nucleation of crystalline selenium and results in high detector dark currents. A CMOS-compatible polyimide buffer layer was used to planarize the backplane and provide a low stress and thermally stable surface for a-Se. The buffer layer inhibits crystallization and provides detector stability that is not only a performance factor but also critical for favorable long term cost-benefit considerations in the application of CMOS digital x-ray imagers in medical practice. The detector structure is comprised of a polyimide (PI) buffer layer, the a-Se layer, and a gold (Au) top electrode. The PI layer is applied by spin-coating and is patterned using dry etching to open the backplane bond pads for wire bonding. Thermal evaporation is used to deposit the a-Se and Au layers, and the detector is operated in hole collection mode (i.e. a positive bias on the Au top electrode). High resolution a-Se diagnostic systems typically use 70 to 100 ?m pixel pitch and have a pre-sampling modulation transfer function (MTF) that is significantly limited by the pixel aperture. Our results confirm that, for a densely integrated 25 ?m pixel pitch CMOS array, the MTF approaches the fundamental material limit, i.e. where the MTF begins to be limited by the a-Se material properties and not the pixel aperture. Preliminary images demonstrating high spatial resolution have been obtained from a frst prototype imager.

  20. III-V/Ge channel MOS device technologies in nano CMOS era

    NASA Astrophysics Data System (ADS)

    Takagi, Shinichi; Zhang, Rui; Suh, Junkyo; Kim, Sang-Hyeon; Yokoyama, Masafumi; Nishi, Koichi; Takenaka, Mitsuru

    2015-06-01

    CMOS utilizing high-mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high-performance and low power advanced LSIs in the future, because of its enhanced carrier transport properties. However, there are many critical issues and difficult challenges for realizing III-V/Ge-based CMOS on the Si platform such as (1) the formation of high-crystal-quality Ge/III-V films on Si substrates, (2) gate stack technologies to realize superior MOS/MIS interface quality, (3) the formation of a source/drain (S/D) with low resistivity and low leakage current, (4) process integration to realize ultrashort channel devices, and (5) total CMOS integration including Si CMOS. In this paper, we review the recent progress in III-V/Ge MOS devices and process technologies as viable approaches to solve the above critical problems on the basis of our recent research activities. The technologies include MOS gate stack formation, high-quality channel formation, low-resistance S/D formation, and CMOS integration. For the Ge device technologies, we focus on the gate stack technology and Ge channel formation on Si. Also, for the III-V MOS device technologies, we mainly address the gate stack technology, III-V channel formation on Si, the metal S/D technology, and implementation of these technologies into short-channel III-V-OI MOSFETs on Si substrates. On the basis of the present status of the achievements, we finally discuss the possibility of various CMOS structures using III-V/Ge channels.

  1. Indium bump array fabrication on small CMOS circuit for flip-chip bonding

    NASA Astrophysics Data System (ADS)

    Yuyang, Huang; Yuxiang, Zhang; Zhizhen, Yin; Guoxin, Cui; C, Liu H.; Lifeng, Bian; Hui, Yang; Yaohui, Zhang

    2011-11-01

    We demonstrate a novel method for indium bump fabrication on a small CMOS circuit chip that is to be flip-chip bonded with a GaAs/AlGaAs multiple quantum well spatial light modulator. A chip holder with a via hole is used to coat the photoresist for indium bump lift-off. The 1000 ?m-wide photoresist edge bead around the circuit chip can be reduced to less than 500 ?m, which ensures the integrity of the indium bump array. 64 × 64 indium arrays with 20 ?m-high, 30 ?m-diameter bumps are successfully formed on a 5 × 6.5 mm2 CMOS chip.

  2. Development of CMOS Pixel Sensors fully adapted to the ILD Vertex Detector Requirements

    E-print Network

    Winter, Marc; Besson, Auguste; Claus, Gilles; Dorokhov, Andrei; Goffe, Mathieu; Hu-Guo, Christine; Morel, Frederic; Valin, Isabelle; Voutsinas, Georgios; Zhang, Liang

    2012-01-01

    CMOS Pixel Sensors are making steady progress towards the specifications of the ILD vertex detector. Recent developments are summarised, which show that these devices are close to comply with all major requirements, in particular the read-out speed needed to cope with the beam related background. This achievement is grounded on the double- sided ladder concept, which allows combining signals generated by a single particle in two different sensors, one devoted to spatial resolution and the other to time stamp, both assembled on the same mechanical support. The status of the development is overviewed as well as the plans to finalise it using an advanced CMOS process.

  3. Highly Unidirectional Uniform Optical Grating Couplers, Fabricated in Standard 45nm SOI-CMOS Foundry Process

    E-print Network

    Uroševi?, Stevan Lj

    2014-01-01

    This paper defines new structures of highly unidirectional uniform optical grating couplers which are all within constraints of the standard 45nm SOI-CMOS foundry process. Analysis in terms of unidirectivity and coupling efficiency is done. Maximum achieved unidirectivity (power radiation in one direction) is 98%. Unidirectional uniform gratings are fabricated in the standard 45nm SOI-CMOS foundry process. These gratings are measured and compared, using the new method of comparison, with typical bidirectional uniform gratings fabricated in the same process, in terms of coupling efficiency (in this case unidirectivity) with the standard singlemode fiber. For both types of gratings spectrum is given, measured with optical spectrum analyzer.

  4. Compact low-cost high-sensitivity CMOS radar-on-chip integration for security applications

    NASA Astrophysics Data System (ADS)

    Li, Changzhi; Lin, Jenshan

    2010-04-01

    Based on the measurement results of a 5 GHz CMOS radar microchip, it is shown that low power CMOS radar-on-chip integration can have high detection sensitivity despite the large flicker noise and phase noise contributions around the signal of interest. Key technologies to further increase the detection sensitivity will be discussed, including software configured DC offset calibration, noise suppression using tunable baseband bandwidth limiter, and special receiver architecture for flicker noise reduction. The applications of low-cost high-sensitivity on-chip radar will be focused on surveillance and reconnaissance, sensing through-wall radar, ground penetration radar, border monitoring, and moving target detection.

  5. Experimental investigation of factors influencing design of small-signal CMOS amplifiers

    NASA Astrophysics Data System (ADS)

    Vernon, Emerson; Bryson, Damian; Motayed, Abhishek; Noor Mohammad, S.

    2001-01-01

    Physical analysis of the factors influencing experimental design of small-signal complementary metal-oxide-semiconductor (CMOS) amplifiers has been performed in some details. The role of the current mirror in supplying constant current source has been elucidated. It has been shown how variable resistances resulting from MOS resistors provide significant flexibility to the circuit. CMOS amplifier design employing MOS resistors yield voltage gain almost in quantitative agreement with the theoretical results. This voltage gain increases with increasing supply voltage VSS. Further, output signal, which is out of phase of the input signal by 180°, is least distorted in the amplifier circuit.

  6. Prediction and measurement of radiation damage to CMOS devices on board spacecraft

    NASA Technical Reports Server (NTRS)

    Cliff, R. A.; Danchenko, V.; Stassinopoulos, E. G.; Sing, M.; Brucker, G. J.; Ohanian, R. S.

    1976-01-01

    The initial results obtained from the Complementary Metal Oxide Semiconductors Radiation Effects Measurement experiment are presented. Predictions of radiation damage to C-MOS devices are based on standard environment models and computational techniques. A comparison of the shifts in CMOS threshold potentials, that is, those measured in space to those obtained from the on the ground simulation experiment with Co 60, indicated that the measured space damage is greater than predicted by a factor of two for shields thicker than 100 mils (2.54 mm), but agrees well with predictions for the thinner shields.

  7. A programmable multi-channel CMOS pulser chip to drive ultrasonic array transducers

    SciTech Connect

    Scales, N.R.; Hicks, P.J.; Armitage, A.D.; Payne, P.A.; Chen, Q.X.; Hatfield, J.V. )

    1994-08-01

    This paper describes the development of a 16-channel programmable pulse generator Application Specific Integrated Circuit (ASIC). The General Purpose Pulser Chip (GPPC-16) can supply pulses delayed by up to 0.5 ms with a 1 ns time resolution. By employing novel design techniques, this has been achieved in standard CMOS technology. The design employs a CMOS delay line in conjunction with a phase-locked-loop. In this way a 16-phase clock is generated, which can drive 16 programmable counters. Currently the chip is being used to drive ultrasonic transducer arrays. The construction of these piezoelectric polymer arrays is also briefly discussed.

  8. Second Generation Monolithic Full-depletion Radiation Sensor with Integrated CMOS Circuitry

    SciTech Connect

    Segal, J.D.; Kenney, C.J.; Parker, S.I.; Aw, C.H.; Snoeys, W.J.; Wooley, B.; Plummer, J.D.; /Stanford U., Elect. Eng. Dept.

    2011-05-20

    A second-generation monolithic silicon radiation sensor has been built and characterized. This pixel detector has CMOS circuitry fabricated directly in the high-resistivity floatzone substrate. The bulk is fully depleted from bias applied to the backside diode. Within the array, PMOS pixel circuitry forms the first stage amplifiers. Full CMOS circuitry implementing further amplification as well as column and row logic is located in the periphery of the pixel array. This allows a sparse-field readout scheme where only pixels with signals above a certain threshold are readout. We describe the fabrication process, circuit design, system performance, and results of gamma-ray radiation tests.

  9. Integrated CMOS dew point sensors for relative humidity measurement

    NASA Astrophysics Data System (ADS)

    Savalli, Nicolo; Baglio, Salvatore; Castorina, Salvatore; Sacco, Vincenzo; Tringali, Cristina

    2004-07-01

    This work deals with the development of integrated relative humidity dew point sensors realized by adopting standard CMOS technology for applications in various fields. The proposed system is composed by a suspended plate that is cooled by exploiting integrated Peltier cells. The cold junctions of the cells have been spread over the plate surface to improve the homogeneity of the temperature distribution over its surface, where cooling will cause the water condensation. The temperature at which water drops occur, named dew point temperature, is a function of the air humidity. Measurement of such dew point temperature and the ambient temperature allows to know the relative humidity. The detection of water drops is achieved by adopting a capacitive sensing strategy realized by interdigited fixed combs, composed by the upper layer of the adopted process. Such a capacitive sensor, together with its conditioning circuit, drives a trigger that stops the cooling of the plate and enables the reading of the dew point temperature. Temperature measurements are achieved by means of suitably integrated thermocouples. The analytical model of the proposed system has been developed and has been used to design a prototype device and to estimate its performances. In such a prototype, the thermoelectric cooler is composed by 56 Peltier cells, made by metal 1/poly 1 junctions. The plate has a square shape with 200 ?m side, and it is realized by exploiting the oxide layers. Starting from the ambient temperature a temperature variation of ?T = 15 K can be reached in 10 ms thus allowing to measure a relative humidity greater than 40%.

  10. sCMOS detector for imaging VNIR spectrometry

    NASA Astrophysics Data System (ADS)

    Eckardt, Andreas; Reulke, Ralf; Schwarzer, Horst; Venus, Holger; Neumann, Christian

    2013-09-01

    The facility Optical Information Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the scientific results of the institute of leading edge instruments and focal plane designs for EnMAP VIS/NIR spectrograph. EnMAP (Environmental Mapping and Analysis Program) is one of the selected proposals for the national German Space Program. The EnMAP project includes the technological design of the hyper spectral space borne instrument and the algorithms development of the classification. The EnMAP project is a joint response of German Earth observation research institutions, value-added resellers and the German space industry like Kayser-Threde GmbH (KT) and others to the increasing demand on information about the status of our environment. The Geo Forschungs Zentrum (GFZ) Potsdam is the Principal Investigator of EnMAP. DLR OS and KT were driving the technology of new detectors and the FPA design for this project, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generations of space borne sensor systems are focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large swath and high spectral resolution with intelligent synchronization control, fast-readout ADC chains and new focal-plane concepts open the door to new remote-sensing and smart deep space instruments. The paper gives an overview over the detector verification program at DLR on FPA level, new control possibilities for sCMOS detectors in global shutter mode and key parameters like PRNU, DSNU, MTF, SNR, Linearity, Spectral Response, Quantum Efficiency, Flatness and Radiation Tolerance will be discussed in detail.

  11. Commercialism in Intercollegiate Athletics.

    ERIC Educational Resources Information Center

    Delany, James E.

    1997-01-01

    Outlines the history of intercollegiate athletics and the evolution of commercialization in college sports, particularly through television. Argues that few Division I programs could be self-sufficient; the issue is the degree to which sports are commercialized for revenue, and the challenge to balance schools' needs, private sector interests, and…

  12. Lunar Commercialization Workshop

    NASA Technical Reports Server (NTRS)

    Martin, Gary L.

    2009-01-01

    This slide presentation outlines a competition that has as its goal to explores the viability of using public-private partnerships to open space frontier for commercial uses. The teams have the objective of designing a business plan to open the space frontier to commercial interests.

  13. Technology Transfer and Commercialization

    NASA Technical Reports Server (NTRS)

    Martin, Katherine; Chapman, Diane; Giffith, Melanie; Molnar, Darwin

    2001-01-01

    During concurrent sessions for Materials and Structures for High Performance and Emissions Reduction, the UEET Intellectual Property Officer and the Technology Commercialization Specialist will discuss the UEET Technology Transfer and Commercialization goals and efforts. This will include a review of the Technology Commercialization Plan for UEET and what UEET personnel are asked to do to further the goals of the Plan. The major goal of the Plan is to define methods for how UEET assets can best be infused into industry. The National Technology Transfer Center will conduct a summary of its efforts in assessing UEET technologies in the areas of materials and emissions reduction for commercial potential. NTTC is assisting us in completing an inventory and prioritization by commercialization potential. This will result in increased exposure of UEET capabilities to the private sector. The session will include audience solicitation of additional commercializable technologies.

  14. -1- E.R. Fossum 2015 CMOS Image Sensors

    E-print Network

    Fossum, Eric R.

    Many kinds of digital cameras Photography Camera phone Digital single lens reflex (DSLR) Mirrorless.R. Fossum 2015 Technology Innovation and Entrepreneurship Arc Innovation: The process of translating to Micron Fossum leaves Micron 1992 2014 Nearly a Full Arc Story Invention Innovation Commercialization Life

  15. Commercial Biomedical Experiments Payload

    NASA Technical Reports Server (NTRS)

    2003-01-01

    Experiments to seek solutions for a range of biomedical issues are at the heart of several investigations that will be hosted by the Commercial Instrumentation Technology Associates (ITA), Inc. The biomedical experiments CIBX-2 payload is unique, encompassing more than 20 separate experiments including cancer research, commercial experiments, and student hands-on experiments from 10 schools as part of ITA's ongoing University Among the stars program. Here, Astronaut Story Musgrave activates the CMIX-5 (Commercial MDA ITA experiment) payload in the Space Shuttle mid deck during the STS-80 mission in 1996 which is similar to CIBX-2. The experiments are sponsored by NASA's Space Product Development Program (SPD).

  16. A 90nm CMOS Direct Conversion Transmitter for WCDMA Xuemin Yang1

    E-print Network

    cancellation is applied to driver amplifier to achiever single end output power +9.6 dBm with -43.2dBc ACLR@5. Considering the driver amplifier to be a class AB amplifier for achieving reasonable power efficiency IBM, Burlington, VT Abstract -- A linear high output power CMOS direct conversion transmitter for wide

  17. On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

    NASA Technical Reports Server (NTRS)

    Samoska, Lorene; Man Fung, King; Gaier, Todd; Huang, Daquan; Larocca, Tim; Chang, M. F.; Campbell, Richard; Andrews, Michael

    2008-01-01

    The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.

  18. CMOS-compatible, athermal silicon ring modulators clad with titanium dioxide

    E-print Network

    Yoo, S. J. Ben

    CMOS-compatible, athermal silicon ring modulators clad with titanium dioxide Stevan S. Djordjevic,1-optic contribution with that from the amorphous titanium dioxide (a-TiO2) overcladding with a negative thermo-compatible Titanium Dioxide Deposition for Athermalization of Silicon Waveguides," accepted for publication

  19. High frequency continuous-time circuits and built-in-self-test using CMOS RMS detector 

    E-print Network

    Venkatasubramanian, Radhika

    2007-04-25

    as the DUT on 0.35 �µm CMOS technology. The HF RMS detector occupies 0.07 mm2 and has an input capacitance of 7 fF. The HF RMS detector has a dynamic range greater than 24 dB starting from -38 dBm of input power. The bandwidth and boost of the filter have...

  20. Ionizing Radiation Effects on CMOS Imagers Manufactured in Deep Submicron Process

    E-print Network

    Mailhes, Corinne

    Ionizing Radiation Effects on CMOS Imagers Manufactured in Deep Submicron Process Vincent Goiffona, ionizing radiation, total dose, dark current, STI, hardening by design, RHDB 1. INTRODUCTION Ionizing are rarely studied and whose sensitivity to ionizing radiation is not totally quantified. The aim of our work

  1. Overview of CMOS process and design options for image sensor dedicated to space applications

    NASA Astrophysics Data System (ADS)

    Martin-Gonthier, P.; Magnan, P.; Corbiere, F.

    2005-10-01

    With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35?m generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques.

  2. Low Power CMOS Re-programmable Pulse Generator for UWB Systems Kevin Marsden1

    E-print Network

    Arslan, Hüseyin

    Low Power CMOS Re-programmable Pulse Generator for UWB Systems Kevin Marsden1 , Hyung-Jin Lee1 pulse generator for impulse-based UWB systems. The basic structure of our design involves a power amplifier with four control taps, which essentially decides the shape of the generated pulse. The design

  3. Broadband CMOS-Compatible Silicon Photonic Electro-Optic Switch for Photonic Networks-on-Chip

    E-print Network

    Bergman, Keren

    as the functional ubiquity of the silicon photonic microring resonator, the silicon-on-insulator (SOI) platform has work [2,3]. In this work, we demonstrate experimentally for the first time a silicon photonic microringBroadband CMOS-Compatible Silicon Photonic Electro-Optic Switch for Photonic Networks

  4. Method for implementation of back-illuminated CMOS or CCD imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor)

    2008-01-01

    A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.

  5. Quasi-planar bulk CMOS technology for improved SRAM scalability Changhwan Shin a,

    E-print Network

    Zakhor, Avideh

    voltage scaling. Examples include the fully depleted silicon-on-insulator (FD-SOI) MOSFET with thin buried-oxide Article history: Available online 18 July 2011 Keywords: Variability MOSFET SRAM CMOS a b s t r a c t A simple approach for manufacturing quasi-planar bulk MOSFET structures is demonstrated and shown

  6. Battery-assisted and Photovoltaic-sourced Switched-inductor CMOS Harvesting ChargerSupply

    E-print Network

    Rincon-Mora, Gabriel A.

    Battery-assisted and Photovoltaic-sourced Switched-inductor CMOS Harvesting Charger­Supply Rajiv--A challenge wireless microsensors and other microsystems face is short lifetime, because tiny batteries store percentage of what solar light can, which means the PV cell needs assistance from a battery. Mixing PV

  7. Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS.

    PubMed

    Shainline, Jeffrey M; Orcutt, Jason S; Wade, Mark T; Nammari, Kareem; Moss, Benjamin; Georgas, Michael; Sun, Chen; Ram, Rajeev J; Stojanovi?, Vladimir; Popovi?, Miloš A

    2013-08-01

    We demonstrate the first (to the best of our knowledge) depletion-mode carrier-plasma optical modulator fabricated in a standard advanced complementary metal-oxide-semiconductor (CMOS) logic process (45 nm node SOI CMOS) with no process modifications. The zero-change CMOS photonics approach enables this device to be monolithically integrated into state-of-the-art microprocessors and advanced electronics. Because these processes support lateral p-n junctions but not efficient ridge waveguides, we accommodate these constraints with a new type of resonant modulator. It is based on a hybrid microring/disk cavity formed entirely in the sub-90 nm thick monocrystalline silicon transistor body layer. Electrical contact of both polarities is made along the inner radius of the multimode ring cavity via an array of silicon spokes. The spokes connect to p and n regions formed using transistor well implants, which form radially extending lateral junctions that provide index modulation. We show 5 Gbps data modulation at 1265 nm wavelength with 5.2 dB extinction ratio and an estimated 40 fJ/bit energy consumption. Broad thermal tuning is demonstrated across 3.2 THz (18 nm) with an efficiency of 291 GHz/mW. A single postprocessing step to remove the silicon handle wafer was necessary to support low-loss optical confinement in the device layer. This modulator is an important step toward monolithically integrated CMOS photonic interconnects. PMID:23903103

  8. Prospects for Building Cortex-Scale CMOL/CMOS Circuits: A Design Space Exploration

    E-print Network

    Hammerstrom, Dan

    vendors struggle to parallelize existing software and to develop new parallel applications and programming exploration methodology to investigate various architectures/designs, and their relative performance/price trade- offs. Using this methodology, we investigate CMOS and hybrid nano-scale (CMOL) based digital

  9. Implementation of CMOS Neuron for Robot Motion Control Unit , Jing Yang1

    E-print Network

    Ayers, Joseph

    of biological motion control unit is of the most important in designing such a bio-mimetic robot. Figure 1 contingencies and clumsy reaction due to intrinsic discrete time control. Motivated by biological discoveriesImplementation of CMOS Neuron for Robot Motion Control Unit CJing Lu1 , Jing Yang1 , Yong-Bin Kim1

  10. Fixed-and Variable-Length Ring Oscillators for Variability Characterization in 45nm CMOS

    E-print Network

    Zakhor, Avideh

    Fixed- and Variable-Length Ring Oscillators for Variability Characterization in 45nm CMOS Ji, Inc. Abstract- Fixed- and variable-length ring oscillators (RO's) are designed for characterization characterize the impact of circuit topology on gate delay variability by measuring ring oscillator frequencies

  11. Ka-Band, RF MEMS Switches on CMOS Grade Silicon with a Polyimide Interface Layer

    NASA Technical Reports Server (NTRS)

    Ponchak, George E.; Varaljay, Nicholas C.; Papapolymerou, John

    2003-01-01

    For the first time, RF MEMS switcbes on CMOS grade Si witb a polyimide interface layer are fabricated and characterized. At Ka-Band (36.6 GHz), an insertion loss of 0.52 dB and an isolation of 20 dB is obtained.

  12. Design of CMOS integrated frequency synthesizers for ultra-wideband wireless communications systems 

    E-print Network

    Tong, Haitao

    2009-05-15

    on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5¬GHz CSD¬QVCO in 0.18 µm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its...

  13. Time and Frequency Domain Transient Signal Analysis for Defect Detection in CMOS Digital ICs

    E-print Network

    Plusquellic, James

    Time and Frequency Domain Transient Signal Analysis for Defect Detection in CMOS Digital ICs James approach to testing digital integrated circuits. Defect detection is accomplished in TSA by analyzing variations in the transient waveforms, TSA can detect the presence of defects at test points

  14. Nonlinear enhancement in photonic crystal slow light waveguides fabricated using CMOS-

    E-print Network

    Baba, Toshihiko

    Nonlinear enhancement in photonic crystal slow light waveguides fabricated using CMOS- compatible have studied low-dispersion slow light and its nonlinear enhancement in photonic crystal waveguides functionalities in Si photonics, while loss reduction is desired for ensuring the advantage of slow light. ©2011

  15. Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies

    E-print Network

    Mahmoodi, Hamid

    Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies functionality of circuits such as sense amplifiers. In this paper, we will analyze the impact of process variations on sense amplifier circuits in detail. We will explore statistical design and optimization

  16. Design and fabrication of a CMOS-compatible MHP gas sensor

    SciTech Connect

    Li, Ying; Yu, Jun Wu, Hao; Tang, Zhenan

    2014-03-15

    A novel micro-hotplate (MHP) gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO{sub 2} film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ?19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3%) in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.

  17. Demonstration of a fast-reconfigurable silicon CMOS optical lattice filter

    E-print Network

    Yoo, S. J. Ben

    Demonstration of a fast-reconfigurable silicon CMOS optical lattice filter Salah Ibrahim,1 Nicolas@ucdavis.edu Abstract: We demonstrate a fully-reconfigurable fourth-order optical lattice filter built by cascading lattice filters. ©2011 Optical Society of America OCIS codes: (070.5753) Resonators; (070.6020) Continuous

  18. INTEGRATED MEMS STRUCTURES AND CMOS CIRCUITS FOR BIOELECTRONIC INTERFACE WITH SINGLE CELLS

    E-print Network

    Maryland at College Park, University of

    INTEGRATED MEMS STRUCTURES AND CMOS CIRCUITS FOR BIOELECTRONIC INTERFACE WITH SINGLE CELLS N each vial are integrated bio-amplifiers and/or other sensing circuits to form a biolab-on-a-chip. We. INTRODUCTION The integration of living cells with electronics can be used for fast medical diagnosis [1

  19. CMOS image sensor-based immunodetection by refractive-index change.

    PubMed

    Devadhasan, Jasmine P; Kim, Sanghyo

    2012-01-01

    A complementary metal oxide semiconductor (CMOS) image sensor is an intriguing technology for the development of a novel biosensor. Indeed, the CMOS image sensor mechanism concerning the detection of the antigen-antibody (Ag-Ab) interaction at the nanoscale has been ambiguous so far. To understand the mechanism, more extensive research has been necessary to achieve point-of-care diagnostic devices. This research has demonstrated a CMOS image sensor-based analysis of cardiovascular disease markers, such as C-reactive protein (CRP) and troponin I, Ag-Ab interactions on indium nanoparticle (InNP) substrates by simple photon count variation. The developed sensor is feasible to detect proteins even at a fg/mL concentration under ordinary room light. Possible mechanisms, such as dielectric constant and refractive-index changes, have been studied and proposed. A dramatic change in the refractive index after protein adsorption on an InNP substrate was observed to be a predominant factor involved in CMOS image sensor-based immunoassay. PMID:22975915

  20. Why is CMOS scaling coming to an END? Nor Zaidi Haron Said Hamdioui

    E-print Network

    its boundary at size of 22 nm technology by 2018. This paper discusses and analyzes the main, Delft University of Technology Mekelweg 4, 2628 CD Delft, The Netherlands {N.Z.B.Haron, S challenges and limitations of CMOS scaling, not only from physical and technological point of view, but also

  1. Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

    PubMed Central

    Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

    2012-01-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 ?m two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/?Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

  2. Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

    PubMed

    Gurun, Gokce; Hasler, Paul; Degertekin, F

    2011-08-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-?m two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/?Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz. PMID:21859585

  3. Radiation Tolerance of CMOS Monolithic Active Pixel Sensors with Self-Biased Pixels

    E-print Network

    M. Deveaux; S. Amar-Youcef; A. Besson; G. Claus; C. Colledani; M. Dorokhov; C. Dritsa; W. Dulinski; I. Froehlich; M. Goffe; D. Grandjean; S. Heini; A. Himmi; C. Hu; K. Jaaskelainen; C. Muentz; A. Shabetai; J. Stroth; M. Szelezniak; I. Valin; M. Winter

    2009-08-28

    CMOS Monolithic Active Pixel Sensors (MAPS) are proposed as a technology for various vertex detectors in nuclear and particle physics. We discuss the mechanisms of ionizing radiation damage on MAPS hosting the the dead time free, so-called self bias pixel. Moreover, we discuss radiation hardened sensor designs which allow operating detectors after exposing them to irradiation doses above 1 Mrad

  4. Radiation tolerance of CMOS monolithic active pixel sensors with self-biased pixels

    NASA Astrophysics Data System (ADS)

    Deveaux, M.; Amar-Youcef, S.; Besson, A.; Claus, G.; Colledani, C.; Dorokhov, M.; Dritsa, C.; Dulinski, W.; Fröhlich, I.; Goffe, M.; Grandjean, D.; Heini, S.; Himmi, A.; Hu, C.; Jaaskelainen, K.; Müntz, C.; Shabetai, A.; Stroth, J.; Szelezniak, M.; Valin, I.; Winter, M.

    2010-12-01

    CMOS monolithic active pixel sensors (MAPS) are proposed as a technology for various vertex detectors in nuclear and particle physics. We discuss the mechanisms of ionizing radiation damage on MAPS hosting the dead time free, so-called self bias pixel. Moreover, we introduce radiation hardened sensor designs which allow operating detectors after exposing them to irradiation doses above 1 Mrad.

  5. A CMOS image sensor for low light applications Honghao Ji, Pamela A. Abshire

    E-print Network

    Maryland at College Park, University of

    A CMOS image sensor for low light applications Honghao Ji, Pamela A. Abshire Department pixel for high speed, low light imaging applications. The new pixel achieves lower dark current and scientific applications are their relatively large dark current and random noise, especially at low light

  6. AN INTEGRATE AND FIRE PIXEL WITH CONTRAST OUTPUTS FOR A CMOS IMAGER

    E-print Network

    Slatton, Clint

    AN INTEGRATE AND FIRE PIXEL WITH CONTRAST OUTPUTS FOR A CMOS IMAGER Thomas A. Holz and John G. Harris Computational Neuro-Engineering Laboratory, University of Florida P.O. Box 116130, Gainesville by the integrate and fire neurons in biological vision systems to improve the dynamic range and output bandwidth

  7. Die-level Photolithography and Etchless Parylene Packaging Processes for on-CMOS Electrochemical

    E-print Network

    Mason, Andrew

    Die-level Photolithography and Etchless Parylene Packaging Processes for on-CMOS Electrochemical parylene packaging reduces processing time and improves fabrication yield. These techniques enable imposed on wire bonds. Another approach involves the use of parylene as the encapsulation material [14

  8. A CMOS Image Sensor for DNA Microarrays Samir Parikh, Glenn Gulak, Paul Chow

    E-print Network

    Chow, Paul

    A CMOS Image Sensor for DNA Microarrays Samir Parikh, Glenn Gulak, Paul Chow University of Toronto-to-digital converter. I. INTRODUCTION DNA microarrays are commonly used to search for DNA sequences. A DNA microarray containing the target ssDNA is introduced to the DNA microarray leading to a pairing or unpairing process

  9. Comprehensive Analysis and Optimization of CMOS Neural Amplifiers for Wireless Recording

    E-print Network

    Mason, Andrew

    Comprehensive Analysis and Optimization of CMOS Neural Amplifiers for Wireless Recording Implants, {lihaitao, mason}@msu.edu Abstract--Neural amplifiers play a critical role in the bandwidth, power comprehensive analysis of neural amplifier design to optimize these performance characteristics. Amplifier

  10. A CMOS integrated circuit for multichannel multiple-subject biotelemetry using bidirectional optical transmissions.

    PubMed

    Kawahito, S; Ueda, S; Ishida, M; Nakamura, T; Usui, S; Nagaoka, S

    1994-04-01

    A CMOS integrated circuit for a noninvasive biological-signal telemetry system specified for use in medical and physiological studies of the influence of weightlessness in space is presented. The system can monitor multichannel (4 channels maximum) biological signals from multiple subjects (4 subjects maximum) in real time by using time multiplexing. A key technique, so-called synchronized multiple-subject telemetry, to achieve multiple-subject telemetry has been proposed. This technique utilizes bidirectional optical transmissions with direct and scattered infrared lights between an observer and each of the subjects. An experimental CMOS IC to give a small light-weight low-power, and smart telemetry instrument for use on animals has been developed. This IC is for evaluating circuit blocks of the implantable monolithic telemetry instrument. The major circuit blocks include CMOS digital circuits for synchronization, subject selection and time multiplexing, analog circuits for pulse interval modulation (PIM), and other blocks such as a CMOS optical pulse receiver and an LED driver. A preliminary experimental multichannel telemetry from two subjects has been performed with the implemented IC chips, and the principal operation of the multiple-subject optical biotelemetry has been demonstrated. PMID:8063309

  11. Repackaging and characterizing a HgCdTe CMOS infrared camera for the New Solar Telescope

    E-print Network

    Repackaging and characterizing a HgCdTe CMOS infrared camera for the New Solar Telescope Wenda Jersey Institute of Technology, 323 Martin Luther King Blvd., Newark, NJ 07102; bBig Bear Solar in the near infrared (NIR). In order to satisfy the diverse observational requirements of these scientific

  12. CMOS ASIC for MHz Silicon BAW Gyroscope Jalpa Shah, Houri Johari, Ajit Sharma and Farrokh Ayazi

    E-print Network

    Ayazi, Farrokh

    CMOS ASIC for MHz Silicon BAW Gyroscope Jalpa Shah, Houri Johari, Ajit Sharma and Farrokh Ayazi actuation and read-out a 6MHz Silicon Bulk Acoustic Wave (BAW) gyroscope. The supporting electronics for a high quality factor (Q>100,000) BAW gyroscope include: an electro-mechanical drive oscillator loop

  13. Transistor Sizing for Minimizing Power Consumption of CMOS Circuits under Delay Constraint

    E-print Network

    He, Lei

    Transistor Sizing for Minimizing Power Consumption of CMOS Circuits under Delay Constraint Manjit University Park, PA 16802 Mary Jane Irwin Abstract We consider the problem of transistor sizing in a static that the transistors of a gate with high fan-out load should be enlarged to minimize the power consumption

  14. An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization

    E-print Network

    Sapatnekar, Sachin

    An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization topology, the delay can be controlled by varying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the channel lengths in a digital circuit

  15. Membrane Protein Biosensor with Multi-Channel CMOS Impedance Extractor and Digitizer

    E-print Network

    Mason, Andrew

    of diseases, and discovery of new and effective drugs, tBLM biosensors merit the development of newMembrane Protein Biosensor with Multi-Channel CMOS Impedance Extractor and Digitizer Chao Yang the development of biosensor arrays that harness the unique sensitivity and selectivity of membrane proteins

  16. 77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-12-14

    ... (``CalTech''). 77 FR 33488 (June 6, 2012). The complaint alleged violations of section 337 of the Tariff... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations... products containing the same based on infringement of three United States patents. The notice...

  17. Quad-phase synchronous light detection with 64 3 64 CMOS modulated light camera

    E-print Network

    Exeter, University of

    Quad-phase synchronous light detection with 64 3 64 CMOS modulated light camera N.S. Johnston, C scheme allows for the detection of signals hidden within even harmonics of a large magnitude. Overview of sensor: Each pixel provides a buffered continuous voltage that is logarithmically proportional

  18. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking

    PubMed Central

    Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

    2011-01-01

    This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process. PMID:22400126

  19. Direct and Selective Synthesis of a Wide Range of Carbon Nanomaterials by CVD at CMOS

    E-print Network

    De Micheli, Giovanni

    --multi-site biosensors, carbon nanomaterials, CVD, CMOS-compatible temperatures I. INTRODUCTION FAST and simultaneous monitoring of many metabo- lites is an urgent need in fields as medicine, environ- ment and food analysis scalability to wafer size and (iii) the well- established presence in the semiconductor industry. In our

  20. A CMOS-MEMS arrayed resonant-gate field effect transistor (RGFET) oscillator

    NASA Astrophysics Data System (ADS)

    Chin, Chi-Hang; Li, Ming-Huang; Chen, Chao-Yu; Wang, Yu-Lin; Li, Sheng-Shian

    2015-11-01

    A high-frequency CMOS-MEMS arrayed resonant-gate field effect transistor (RGFET) fabricated by a standard 0.35 ?m 2-poly-4-metal CMOS-MEMS platform is implemented to enable a Pierce-type oscillator. The proposed arrayed RGFET exhibits low motional impedance of only 5 k? under a purely capacitive transduction and decent power handling capability. With such features, the implemented oscillator shows impressive phase noise of??-117 dBc Hz-1 at the far-from-carrier offset (1 MHz). In this work, we design a clamped-clamped beam (CCB) arrayed resonator utilizing a high-velocity mechanical coupling scheme to serve as the resonant-gate array. To achieve a functional arrayed RGFET, a corresponding FET array is directly placed underneath the resonant gate array to convert the motional current on the resonant-gate array into a voltage output with a tunable transconductance gain. To understand the behavior of the proposed device, an equivalent circuit model consisting of the resonant unit and FET is also provided. To verify the effects of the post-CMOS process on device performance, a conventional MOS I D current measurement is carried out. Finally, a CMOS-MEMS arrayed RGFET oscillator is realized by utilizing a Pierce oscillator architecture, showing decent phase noise performance that benefits from the array design to alleviate the nonlinear effect of the resonant gate.

  1. Phase Noise in CMOS Differential LC Oscillators Ali Hajimiri, Thomas H. Lee

    E-print Network

    Hajimiri, Ali

    5.1 Phase Noise in CMOS Differential LC Oscillators Ali Hajimiri, Thomas H. Lee Center for Integrated Systems, Stanford, CA 94305-4070,USA Abstract An analysis of phase noise in differential cross of the complementary cross-coupled pair is analyzed and verified experimentally. A 1.8GHz LC oscillator with a phase

  2. Phase Noise in CMOS Differential LC Oscillators Ali Hajimiri, Thomas H. Lee

    E-print Network

    Lee, Thomas H.

    Phase Noise in CMOS Differential LC Oscillators Ali Hajimiri, Thomas H. Lee Abstract An analysis of phase noise in differential cross-coupled tuned tank voltage controlled oscillators is presented experimentally. A 1.8GHz LC oscillator with a phase noise of -121dBc/Hz at 600kHz is demonstrated, dissipating 6m

  3. COMMERCIALIZATION OF BIOCONTROL

    Technology Transfer Automated Retrieval System (TEKTRAN)

    Successful commercialization of biocontrol products requires the marriage of science and industry. From a science perspective, some of the issues to be addressed include knowledge of efficacy under various environmental conditions, inoculum density relationships, formulation, and when, where and ho...

  4. Commercial Fisheries Biological Laboratory

    E-print Network

    of algae, outdoor arti- ficial ponds for shrimp culture, a sedimentology labor- atory, a chemical commercial shrimp farming in the United States. From studies on the early life history of penaeid shrimp

  5. NASA commercial programs

    NASA Technical Reports Server (NTRS)

    1990-01-01

    Highlights of NASA-sponsored and assisted commercial space activities of 1989 are presented. Industrial R and D in space, centers for the commercial development of space, and new cooperative agreements are addressed in the U.S. private sector in space section. In the building U.S. competitiveness through technology section, the following topics are presented: (1) technology utilization as a national priority; (2) an exploration of benefits; and (3) honoring Apollo-Era spinoffs. International and domestic R and D trends, and the space sector are discussed in the section on selected economic indicators. Other subjects included in this report are: (1) small business innovation; (2) budget highlights and trends; (3) commercial programs management; and (4) the commercial programs advisory committee.

  6. Technology Commercialization Program 1991

    SciTech Connect

    Not Available

    1991-11-01

    This reference compilation describes the Technology Commercialization Program of the Department of Energy, Defense Programs. The compilation consists of two sections. Section 1, Plans and Procedures, describes the plans and procedures of the Defense Programs Technology Commercialization Program. The second section, Legislation and Policy, identifies legislation and policy related to the Program. The procedures for implementing statutory and regulatory requirements are evolving with time. This document will be periodically updated to reflect changes and new material.

  7. ERC commercialization activities

    SciTech Connect

    Maru, H.C.

    1995-12-01

    The ERC family of companies is anticipating market entry of their first commercial product, a 2.8-MR power plant, in the second quarter of 1999. The present Cooperative Agreement provides for: (1) Commercialization planning and organizational development, (2) Completion of the pre-commercial DFC technology development, (3) Systems and plant design, (4) Manufacturing processes` scale-up to full- sized stack components and assemblies, (5) Upgrades to ERC`s test facility for full-sized stack testing, and (6) Sub-scale testing of a DFC Stack and BOP fueled with landfill gas. This paper discusses the first item, that of preparing for commercialization. ERC`s formal commercialization program began in 1990 with the selection of the 2-MR Direct Fuel Cell power plant by the American Public Power Association (APPA) for promotion to the over 2000 municipal utilities comprising APPA`s segment of the utility sector. Since that beginning, the APPA core group expanded to become the Fuel Cell Commercialization Group (FCCG) which includes representation from all markets - utilities and other power generation equipment buyers.

  8. Design and Fabrication of High-Efficiency CMOS/CCD Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2007-01-01

    An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

  9. Results of benchmarking of advanced CD-SEMs at the 90-nm CMOS technology node

    NASA Astrophysics Data System (ADS)

    Bunday, Benjamin D.; Bishop, Michael; Allgair, John A.

    2004-05-01

    The Advanced Metrology Advisory Group (AMAG) is a council composed of the chief CD-metrologists from the International SEMATECH Manufacturing Initiative (ISMI) consortium"s Member Companies and from the National Institute of Standards (NIST). The AMAG wrote and, in 2002, with CD-SEM supplier involvement, updated the "Unified Advanced CD-SEM Specification for Sub-130nm Technology (Version 2002)" to be a living document which outlines the required performance of advanced CD-SEMs for supplier compliance to the 2003 International Technology Roadmap for Semiconductors, and also conveys member companies" other collective needs to vendors. Through applying this specification during the mid-2003 timeframe, a benchmarking effort of the currently available advanced CD-SEMs has been performed. These results are presented here. The AMAG Unified Specification includes sections outlining the test methodologies, metrics, and wafer-target requirements for each parameter included in the benchmark, and, when applicable, prescribes a target specification compatible with the ITRS and methodologies compatible with the demands of 90nm technology. Parameters to be considered include: ×Precision, Repeatability and Reproducibility ×Accuracy, Apparent Beam Width and Resolution ×Charging and Contamination ×Tool-to-Tool Matching ×Pattern Recognition and Navigation Accuracy ×Throughput ×Instrumentation Outputs ×Tool Automation and Utility ×Precision and Accuracy of Profile Measurement ×Precision and Accuracy of Roughness Measurement. Previous studies under this same project have been published, with the initial version of the International Sematech Unified Specification in 1998, and multi-supplier benchmarks in 1999 and 2001. The results for the 2003 benchmark will be shown and compared to the ITRS, and composite viewpoints showing these 2003 benchmark results compared to the past results are also shown, demonstrating interesting CD-SEM industry trends.

  10. 1470 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 57, NO. 7, JULY 2008 A Broadband CMOS Amplitude Detector for

    E-print Network

    --This paper presents a CMOS RF amplitude detec- tor as a practical integrated test device and demonstrates its, the limited observability in high-frequency SoCs slows down the tasks of design verification, debugging

  11. Integrated CMOS Energy Harvesting Converter with Digital Maximum Power Point Tracking for a Portable Thermophotovoltaic Power Generator

    E-print Network

    Pilawa-Podgurski, Robert

    This paper presents an integrated maximum power point tracking system for use with a thermophotovoltaic (TPV) portable power generator. The design, implemented in 0.35 ?m CMOS technology, consists of a low-power control ...

  12. 104 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 20, NO. 1, FEBRUARY 2011 Modeling and Characterization of CMOS-Fabricated

    E-print Network

    White, Robert D.

    and Characterization of CMOS-Fabricated Capacitive Micromachined Ultrasound Transducers Christopher B. Doody, Member)-compatible capacitive micromachined ultrasound trans- ducers (CMUTs). The transducers are fabricated using the inter--Acoustic models, acoustic transducers, capacitive micromachined ultrasound transducers (CMUTs), finite

  13. Progress and challenges in the direct monolithic integration of III-V devices and Si CMOS on silicon substrates

    E-print Network

    Fitzgerald, Eugene A.

    We present results on the direct monolithic integration of III-V devices and Si CMOS on a silicon substrate. Through optimization of device fabrication and material growth processes III-V devices with electrical performance ...

  14. BioLabs-On-A-Chip: Monitoring Cells Using CMOS Biosensors Somashekar B. Prakash, Nicole M. Nelson,

    E-print Network

    Maryland at College Park, University of

    BioLabs-On-A-Chip: Monitoring Cells Using CMOS Biosensors Somashekar B. Prakash, Nicole M. Nelson integrated biosensors is an ob- vious one: how to keep the electrical leads dry and insulated, while exposing

  15. A 1.2V, 60-GHz radio receiver with on-chip transformers and inductors in 90-nm CMOS

    E-print Network

    Voinigescu, Sorin Petre

    isolation suitable for home and office applications. Receiver front-ends in this frequency range have-GHz radio transceiver in a standard CMOS process. II. RECEIVER OVERVIEW The block diagram of the mm

  16. Detection of On-chip Temperature Gradient Using a 1.5V Low Power CMOS Temperature Sensor

    E-print Network

    Maryland at College Park, University of

    Detection of On-chip Temperature Gradient Using a 1.5V Low Power CMOS Temperature Sensor Yiming@glue.umd.edu Abstract--We present a 1.5V low power CMOS temperature sensor for detection of on-chip temperature gradients. The temperature sensor has measured accuracy of +/- 0.25ºC over a temperature range from 25º

  17. Increasing Linear Dynamic Range of a CMOS Image Sensor

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2007-01-01

    A generic design and a corresponding operating sequence have been developed for increasing the linear-response dynamic range of a complementary metal oxide/semiconductor (CMOS) image sensor. The design provides for linear calibrated dual-gain pixels that operate at high gain at a low signal level and at low gain at a signal level above a preset threshold. Unlike most prior designs for increasing dynamic range of an image sensor, this design does not entail any increase in noise (including fixed-pattern noise), decrease in responsivity or linearity, or degradation of photometric calibration. The figure is a simplified schematic diagram showing the circuit of one pixel and pertinent parts of its column readout circuitry. The conventional part of the pixel circuit includes a photodiode having a small capacitance, CD. The unconventional part includes an additional larger capacitance, CL, that can be connected to the photodiode via a transfer gate controlled in part by a latch. In the high-gain mode, the signal labeled TSR in the figure is held low through the latch, which also helps to adapt the gain on a pixel-by-pixel basis. Light must be coupled to the pixel through a microlens or by back illumination in order to obtain a high effective fill factor; this is necessary to ensure high quantum efficiency, a loss of which would minimize the efficacy of the dynamic- range-enhancement scheme. Once the level of illumination of the pixel exceeds the threshold, TSR is turned on, causing the transfer gate to conduct, thereby adding CL to the pixel capacitance. The added capacitance reduces the conversion gain, and increases the pixel electron-handling capacity, thereby providing an extension of the dynamic range. By use of an array of comparators also at the bottom of the column, photocharge voltages on sampling capacitors in each column are compared with a reference voltage to determine whether it is necessary to switch from the high-gain to the low-gain mode. Depending upon the built-in offset in each pixel and in each comparator, the point at which the gain change occurs will be different, adding gain-dependent fixed pattern noise in each pixel. The offset, and hence the fixed pattern noise, is eliminated by sampling the pixel readout charge four times by use of four capacitors (instead of two such capacitors as in conventional design) connected to the bottom of the column via electronic switches SHS1, SHR1, SHS2, and SHR2, respectively, corresponding to high and low values of the signals TSR and RST. The samples are combined in an appropriate fashion to cancel offset-induced errors, and provide spurious-free imaging with extended dynamic range.

  18. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

  19. Commercial Fisheries Surveys

    USGS Publications Warehouse

    Fabrizio, Mary C.; Richards, R. Anne

    1996-01-01

    In this chapter, we describe methods for sampling commercial fisheries and identify factors affecting the design of sampling plans. When sampled properly, commercial fisheries can provide important information on the response of aquatic organisms to exploitation; such information can be used by management agencies to develop regulations for ensuring long-term production of the resource and long-term economic benefit. Fishery statistics are typically used to estimate abundance, mortality, recruitment, growth, and other vital characterisitcs of populations. Fishery statistics can also be used to study changes in fish community composition resulting from differential exploitation of species.

  20. Commercial Biomedical Experiments

    NASA Technical Reports Server (NTRS)

    2003-01-01

    Experiments to seek solutions for a range of biomedical issues are at the heart of several investigations that will be hosted by the Commercial Instrumentation Technology Associates (ITA), Inc. Biomedical Experiments (CIBX-2) payload. CIBX-2 is unique, encompassing more than 20 separate experiments including cancer research, commercial experiments, and student hands-on experiments from 10 schools as part of ITA's ongoing University Among the Stars program. Valerie Cassanto of ITA checks the Canadian Protein Crystallization Experiment (CAPE) carried by STS-86 to Mir in 1997. The experiments are sponsored by NASA's Space Product Development Program (SPD).

  1. Commercialization of the Internet.

    ERIC Educational Resources Information Center

    Weis, Allan H.

    1992-01-01

    Traces the growth of the Internet from its beginnings as the Defense Advanced Research Project Agency's ARPAnet. Discusses key issues facing network service providers including: acceptable use policies, liability exposure, the integration of research and production networks, the commercialization of the networks, and the need for global planning.…

  2. Commercial Earth Observation

    NASA Technical Reports Server (NTRS)

    1995-01-01

    Through the Earth Observation Commercial Applications Program (EOCAP) at Stennis Space Center, Applied Analysis, Inc. developed a new tool for analyzing remotely sensed data. The Applied Analysis Spectral Analytical Process (AASAP) detects or classifies objects smaller than a pixel and removes the background. This significantly enhances the discrimination among surface features in imagery. ERDAS, Inc. offers the system as a modular addition to its ERDAS IMAGINE software package for remote sensing applications. EOCAP is a government/industry cooperative program designed to encourage commercial applications of remote sensing. Projects can run three years or more and funding is shared by NASA and the private sector participant. Through the Earth Observation Commercial Applications Program (EOCAP), Ocean and Coastal Environmental Sensing (OCENS) developed SeaStation for marine users. SeaStation is a low-cost, portable, shipboard satellite groundstation integrated with vessel catch and product monitoring software. Linked to the Global Positioning System, SeaStation provides real time relationships between vessel position and data such as sea surface temperature, weather conditions and ice edge location. This allows the user to increase fishing productivity and improve vessel safety. EOCAP is a government/industry cooperative program designed to encourage commercial applications of remote sensing. Projects can run three years or more and funding is shared by NASA and the private sector participant.

  3. Commercial applications of telemedicine

    NASA Technical Reports Server (NTRS)

    Natiello, Thomas A.

    1991-01-01

    Telemedicine Systems Corporation was established in 1976 and is a private commercial supplier of telemedicine systems. These systems are various combinations of communications and diagnostic technology, designed to allow the delivery of health care services to remote facilities. The technology and the health care services are paid for by the remote facilities, such as prisons.

  4. Commercializing Biological Control

    ERIC Educational Resources Information Center

    LeLeu, K. L.; Young, M. A.

    1973-01-01

    Describes the only commercial establishment involved in biological control in Australia. The wasp Aphitis melinus, which parasitizes the insect Red Scale, is bred in large numbers and released in the citrus groves where Red Scale is causing damage to the fruit. (JR)

  5. Measuring the Temperature of the Ithaca College MOT Cloud using a CMOS Camera

    NASA Astrophysics Data System (ADS)

    Smucker, Jonathan; Thompson, Bruce

    2015-03-01

    We present our work on measuring the temperature of Rubidium atoms cooled using a magneto-optical trap (MOT). The MOT uses laser trapping methods and Doppler cooling to trap and cool Rubidium atoms to form a cloud that is visible to a CMOS Camera. The Rubidium atoms are cooled further using optical molasses cooling after they are released from the trap (by removing the magnetic field). In order to measure the temperature of the MOT we take pictures of the cloud using a CMOS camera as it expands and calculate the temperature based on the free expansion of the cloud. Results from the experiment will be presented along with a summary of the method used.

  6. An implantable CMOS device for blood-flow imaging during experiments on freely moving rats

    NASA Astrophysics Data System (ADS)

    Haruta, Makito; Kitsumoto, Chikara; Sunaga, Yoshinori; Takehara, Hironari; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Ohta, Jun

    2014-01-01

    An observation technique for animal brain activity under freely moving conditions is important to understand brain functions because brain activity under an anesthetized condition is different from that under a nonanesthetized condition. We have developed an ultrasmall CMOS imaging device for brain activity observation under freely moving conditions. This device is composed of a CMOS image sensor chip and nine LEDs for illumination. It weighs only 0.02 g and its small size enables experiments to be performed without restricting animal movement. This feature is advantageous for brain imaging, particularly in freely moving situations. In this study, we have demonstrated blood-flow imaging using the device for the stable observation of brain activity over a long period. The blood flow can be observed without staining the brain during optical imaging. We have successfully estimated the blood-flow velocity under freely moving conditions.

  7. A highly sensitive CMOS digital Hall sensor for low magnetic field applications.

    PubMed

    Xu, Yue; Pan, Hong-Bin; He, Shu-Zhuan; Li, Li

    2012-01-01

    Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 ?m high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ± 2 mT magnetic field and output a digital Hall signal in a wide temperature range from -40 °C to 120 °C. PMID:22438758

  8. A low-power CMOS smart temperature sensor for RFID application

    NASA Astrophysics Data System (ADS)

    Liangbo, Xie; Jiaxin, Liu; Yao, Wang; Guangjun, Wen

    2014-11-01

    This paper presents the design and implement of a CMOS smart temperature sensor, which consists of a low power analog front-end and a 12-bit low-power successive approximation register (SAR) analog-to-digital converter (ADC). The analog front-end generates a proportional-to-absolute-temperature (PTAT) voltage with MOSFET circuits operating in the sub-threshold region. A reference voltage is also generated and optimized in order to minimize the temperature error and the 12-bit SAR ADC is used to digitize the PTAT voltage. Using 0.18 ?m CMOS technology, measurement results show that the temperature error is -0.69/+0.85 °C after one-point calibration over a temperature range of -40 to 100 °C. Under a conversion speed of 1K samples/s, the power consumption is only 2.02 ?W while the chip area is 230 × 225 ?m2, and it is suitable for RFID application.

  9. An acquisition system for CMOS imagers with a genuine 10 Gbit/s bandwidth

    NASA Astrophysics Data System (ADS)

    Guérin, C.; Mahroug, J.; Tromeur, W.; Houles, J.; Calabria, P.; Barbier, R.

    2012-12-01

    This paper presents a high data throughput acquisition system for pixel detector readout such as CMOS imagers. This CMOS acquisition board offers a genuine 10 Gbit/s bandwidth to the workstation and can provide an on-line and continuous high frame rate imaging capability. On-line processing can be implemented either on the Data Acquisition Board or on the multi-cores workstation depending on the complexity of the algorithms. The different parts composing the acquisition board have been designed to be used first with a single-photon detector called LUSIPHER (800×800 pixels), developed in our laboratory for scientific applications ranging from nano-photonics to adaptive optics. The architecture of the acquisition board is presented and the performances achieved by the produced boards are described. The future developments (hardware and software) concerning the on-line implementation of algorithms dedicated to single-photon imaging are tackled.

  10. CMOS-compatible, athermal silicon ring modulators clad with titanium dioxide.

    PubMed

    Djordjevic, Stevan S; Shang, Kuanping; Guan, Binbin; Cheung, Stanley T S; Liao, Ling; Basak, Juthika; Liu, Hai-Feng; Yoo, S J B

    2013-06-17

    We present the design, fabrication and characterization of athermal nano-photonic silicon ring modulators. The athermalization method employs compensation of the silicon core thermo-optic contribution with that from the amorphous titanium dioxide (a-TiO(2)) overcladding with a negative thermo-optic coefficient. We developed a new CMOS-compatible fabrication process involving low temperature RF magnetron sputtering of high-density and low-loss a-TiO(2) that can withstand subsequent elevated-temperature CMOS processes. Silicon ring resonators with 275 nm wide rib waveguide clad with a-TiO(2) showed near complete athermalization and moderate optical losses. Small-signal testing of the micro-resonator modulators showed high extinction ratio and gigahertz bandwidth. PMID:23787585

  11. Temperature coefficient of frequency modeling for CMOS-MEMS bulk mode composite resonators.

    PubMed

    Wang, Siping; Chen, Wen-Chien; Bahr, Bichoy; Fang, Weileun; Li, Sheng-Shian; Weinstein, Dana

    2015-06-01

    CMOS-MEMS resonators, which are promising building blocks for achieving monolithic integration of MEMS structure, can be used for timing and filtering applications, and control circuitry. SiO2 has been used to make MEMS resonators with quality factor Q > 10(4), but temperature instability remains a major challenge. In this paper, a design that uses an embedded metal block for temperature compensation is proposed and shows sub-ppm temperature stability (-0.21 ppm/K). A comprehensive analytical model is derived and applied to analyze and optimize the temperature coefficient of frequency (TCF) of the CMOS-MEMS composite material resonator. Comparison with finite element method simulation demonstrates good accuracy. The model can also be applied to predict and analyze the TCF of MEMS resonators with arbitrary mode shape, and its integration with simulation packages enables interactive and efficient design process. PMID:26067051

  12. Differential Wide Temperature Range CMOS Interface Circuit for Capacitive MEMS Pressure Sensors

    PubMed Central

    Wang, Yucai; Chodavarapu, Vamsy P.

    2015-01-01

    We describe a Complementary Metal-Oxide Semiconductor (CMOS) differential interface circuit for capacitive Micro-Electro-Mechanical Systems (MEMS) pressure sensors that is functional over a wide temperature range between ?55 °C and 225 °C. The circuit is implemented using IBM 0.13 ?m CMOS technology with 2.5 V power supply. A constant-gm biasing technique is used to mitigate performance degradation at high temperatures. The circuit offers the flexibility to interface with MEMS sensors with a wide range of the steady-state capacitance values from 0.5 pF to 10 pF. Simulation results show that the circuitry has excellent linearity and stability over the wide temperature range. Experimental results confirm that the temperature effects on the circuitry are small, with an overall linearity error around 2%. PMID:25686312

  13. A Highly Sensitive CMOS Digital Hall Sensor for Low Magnetic Field Applications

    PubMed Central

    Xu, Yue; Pan, Hong-Bin; He, Shu-Zhuan; Li, Li

    2012-01-01

    Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 ?m high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ±2 mT magnetic field and output a digital Hall signal in a wide temperature range from ?40 °C to 120 °C. PMID:22438758

  14. A CMOS analog front-end chip for amperometric electrochemical sensors

    NASA Astrophysics Data System (ADS)

    Zhichao, Li; Yuntao, Liu; Min, Chen; Jingbo, Xiao; Jie, Chen

    2015-07-01

    This paper reports a complimentary metal-oxide-semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I2C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma-delta analog to digital converter (?-? ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-?m CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm2. Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. Project supported by the National Key Basic Research and Development Project (No. 2015CB352103).

  15. Break-before-make CMOS inverter for power-efficient delay implementation.

    PubMed

    Puhan, Janez; Rai?, Dušan; Tuma, Tadej; B?rmen, Árpád

    2014-01-01

    A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell. PMID:25538951

  16. Break-before-Make CMOS Inverter for Power-Efficient Delay Implementation

    PubMed Central

    Rai?, Dušan

    2014-01-01

    A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell. PMID:25538951

  17. Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique.

    PubMed

    Fong, Chien-Fu; Dai, Ching-Liang; Wu, Chyan-Chyi

    2015-01-01

    A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm. PMID:26512671

  18. Measurements on HV-CMOS Active Sensors After Irradiation to HL-LHC fluences

    E-print Network

    B. Ristic; for the ATLAS CMOS pixel collaboration

    2015-01-13

    During the long shutdown (LS) 3 beginning 2022 the LHC will be upgraded for higher luminosities pushing the limits especially for the inner tracking detectors of the LHC experiments. In order to cope with the increased particle rate and radiation levels the ATLAS Inner Detector will be completely replaced by a purely silicon based one. Novel sensors based on HV-CMOS processes prove to be good candidates in terms of spatial resolution and radiation hardness. In this paper measurements conducted on prototypes built in the AMS H18 HV-CMOS process and irradiated to fluences of up to $2\\cdot10^{16}\\,\\text{n}_\\text{eq}\\text{cm}^{-2}$ are presented.

  19. Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique

    PubMed Central

    Fong, Chien-Fu; Dai, Ching-Liang; Wu, Chyan-Chyi

    2015-01-01

    A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm. PMID:26512671

  20. A Low-Noise CMOS Pixel Direct Charge Sensor, Topmetal-II-

    E-print Network

    An, Mangmang; Gao, Chaosong; Han, Mikyung; Ji, Rong; Li, Xiaoting; Mei, Yuan; Sun, Quan; Sun, Xiangming; Wang, Kai; Xiao, Le; Xu, Nu; Yang, Ping; Zhou, Wei

    2015-01-01

    We report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35um CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that the sensor achieved a sensor is capable of detecting both electrons and ions drifting in gas. These characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments.