Sample records for access memories drams

  1. Unified random access memory (URAM) by integration of a nanocrystal floating gate for nonvolatile memory and a partially depleted floating body for capacitorless 1T-DRAM

    NASA Astrophysics Data System (ADS)

    Ryu, Seong-Wan; Han, Jin-Woo; Kim, Chung-Jin; Kim, Sungho; Choi, Yang-Kyu

    2009-03-01

    This paper describes a unified memory (URAM) that utilizes a nanocrystal SOI MOSFET for multi-functional applications of both nonvolatile memory (NVM) and capacitorless 1T-DRAM. By using a discrete storage node (Ag nanocrystal) as the floating gate of the NVM, high defect immunity and 2-bit/cell operation were achieved. The embedded nanocrystal NVM also showed 1T-DRAM operation (program/erase time = 100 ns) characteristics, which were realized by storing holes in the floating body of the SOI MOSFET, without requiring an external capacitor. Three-bit/cell operation was accomplished for different applications - 2-bits for nonvolatility and 1-bit for fast operation.

  2. A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters

    NASA Astrophysics Data System (ADS)

    Cristoloveanu, S.; Lee, K. H.; Parihar, M. S.; El Dirani, H.; Lacord, J.; Martinie, S.; Le Royer, C.; Barbe, J.-Ch.; Mescot, X.; Fonteneau, P.; Galy, Ph.; Gamiz, F.; Navarro, C.; Cheng, B.; Duan, M.; Adamu-Lema, F.; Asenov, A.; Taur, Y.; Xu, Y.; Kim, Y.-T.; Wan, J.; Bawedin, M.

    2018-05-01

    The band-modulation and sharp-switching mechanisms in Z2-FET device operated as a capacitorless 1T-DRAM memory are reviewed. The main parameters that govern the memory performance are discussed based on detailed experiments and simulations. This 1T-DRAM memory does not suffer from super-coupling effect and can be integrated in sub-10 nm thick SOI films. It offers low leakage current, high current margin, long retention, low operating voltage especially for programming, and high speed. The Z2-FET is suitable for embedded memory applications.

  3. Capacitorless 1T-DRAM on crystallized poly-Si TFT.

    PubMed

    Kim, Min Soo; Cho, Won Ju

    2011-07-01

    The single-transistor dynamic random-access memory (1T-DRAM) using a polycrystalline-silicon thin-film transistor (poly-Si TFT) was investigated. A 100-nm amorphous silicon thin film was deposited onto a 200-nm oxidized silicon wafer via low-pressure chemical vapor deposition (LPCVD), and the amorphous silicon layer was crystallized via eximer laser annealing (ELA) with a KrF source of 248 nm wavelength and 400 mJ/cm2 power. The fabricated capacitor less 1T-DRAM on the poly-Si TFT was evaluated via impact ionization and gate-induced drain leakage (GIDL) current programming. The device showed a clear memory margin between the "1" and "0" states, and as the channel length decreased, a floating body effect which induces a kink effect increases with high mobility. Furthermore, the GIDL current programming showed improved memory properties compared to the impact ionization method. Although the sensing margins and retention times in both program methods are commercially insufficient, it was confirmed the feasibility of the application of 1T-DRAM operation to TFTs.

  4. New modeling method for the dielectric relaxation of a DRAM cell capacitor

    NASA Astrophysics Data System (ADS)

    Choi, Sujin; Sun, Wookyung; Shin, Hyungsoon

    2018-02-01

    This study proposes a new method for automatically synthesizing the equivalent circuit of the dielectric relaxation (DR) characteristic in dynamic random access memory (DRAM) without frequency dependent capacitance measurement. Charge loss due to DR can be observed by a voltage drop at the storage node and this phenomenon can be analyzed by an equivalent circuit. The Havariliak-Negami model is used to accurately determine the electrical characteristic parameters of an equivalent circuit. The DRAM sensing operation is performed in HSPICE simulations to verify this new method. The simulation demonstrates that the storage node voltage drop resulting from DR and the reduction in the sensing voltage margin, which has a critical impact on DRAM read operation, can be accurately estimated using this new method.

  5. 32-Bit-Wide Memory Tolerates Failures

    NASA Technical Reports Server (NTRS)

    Buskirk, Glenn A.

    1990-01-01

    Electronic memory system of 32-bit words corrects bit errors caused by some common type of failures - even failure of entire 4-bit-wide random-access-memory (RAM) chip. Detects failure of two such chips, so user warned that ouput of memory may contain errors. Includes eight 4-bit-wide DRAM's configured so each bit of each DRAM assigned to different one of four parallel 8-bit words. Each DRAM contributes only 1 bit to each 8-bit word.

  6. Deviation from the law of energy equipartition in a small dynamic-random-access memory

    NASA Astrophysics Data System (ADS)

    Carles, Pierre-Alix; Nishiguchi, Katsuhiko; Fujiwara, Akira

    2015-06-01

    A small dynamic-random-access memory (DRAM) coupled with a high charge sensitivity electrometer based on a silicon field-effect transistor is used to study the law of equipartition of energy. By statistically analyzing the movement of single electrons in the DRAM at various temperature and voltage conditions in thermal equilibrium, we are able to observe a behavior that differs from what is predicted by the law of equipartition energy: when the charging energy of the capacitor of the DRAM is comparable to or smaller than the thermal energy kBT/2, random electron motion is ruled perfectly by thermal energy; on the other hand, when the charging energy becomes higher in relation to the thermal energy kBT/2, random electron motion is suppressed which indicates a deviation from the law of equipartition of energy. Since the law of equipartition is analyzed using the DRAM, one of the most familiar devices, we believe that our results are perfectly universal among all electronic devices.

  7. The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET.

    PubMed

    Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

    2017-09-06

    The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool-Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding "1". The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading "1" to reading "0" (10 7 ) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM.

  8. The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

    NASA Astrophysics Data System (ADS)

    Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

    2017-09-01

    The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool—Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding "1". The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading "1" to reading "0" (107) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM.

  9. Improving energy efficiency of Embedded DRAM Caches for High-end Computing Systems

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Mittal, Sparsh; Vetter, Jeffrey S; Li, Dong

    2014-01-01

    With increasing system core-count, the size of last level cache (LLC) has increased and since SRAM consumes high leakage power, power consumption of LLCs is becoming a significant fraction of processor power consumption. To address this, researchers have used embedded DRAM (eDRAM) LLCs which consume low-leakage power. However, eDRAM caches consume a significant amount of energy in the form of refresh energy. In this paper, we propose ESTEEM, an energy saving technique for embedded DRAM caches. ESTEEM uses dynamic cache reconfiguration to turn-off a portion of the cache to save both leakage and refresh energy. It logically divides the cachemore » sets into multiple modules and turns-off possibly different number of ways in each module. Microarchitectural simulations confirm that ESTEEM is effective in improving performance and energy efficiency and provides better results compared to a recently-proposed eDRAM cache energy saving technique, namely Refrint. For single and dual-core simulations, the average saving in memory subsystem (LLC+main memory) on using ESTEEM is 25.8% and 32.6%, respectively and average weighted speedup are 1.09X and 1.22X, respectively. Additional experiments confirm that ESTEEM works well for a wide-range of system parameters.« less

  10. Patterning optimization for 55nm design rule DRAM/flash memory using production-ready customized illuminations

    NASA Astrophysics Data System (ADS)

    Chen, Ting; Van Den Broeke, Doug; Hsu, Stephen; Hsu, Michael; Park, Sangbong; Berger, Gabriel; Coskun, Tamer; de Vocht, Joep; Chen, Fung; Socha, Robert; Park, JungChul; Gronlund, Keith

    2005-11-01

    Illumination optimization, often combined with optical proximity corrections (OPC) to the mask, is becoming one of the critical components for a production-worthy lithography process for 55nm-node DRAM/Flash memory devices and beyond. At low-k1, e.g. k1<0.31, both resolution and imaging contrast can be severely limited by the current imaging tools while using the standard illumination sources. Illumination optimization is a process where the source shape is varied, in both profile and intensity distribution, to achieve enhancement in the final image contrast as compared to using the non-optimized sources. The optimization can be done efficiently for repetitive patterns such as DRAM/Flash memory cores. However, illumination optimization often produces source shapes that are "free-form" like and they can be too complex to be directly applicable for production and lack the necessary radial and annular symmetries desirable for the diffractive optical element (DOE) based illumination systems in today's leading lithography tools. As a result, post-optimization rendering and verification of the optimized source shape are often necessary to meet the production-ready or manufacturability requirements and ensure optimal performance gains. In this work, we describe our approach to the illumination optimization for k1<0.31 DRAM/Flash memory patterns, using an ASML XT:1400i at NA 0.93, where the all necessary manufacturability requirements are fully accounted for during the optimization. The imaging contrast in the resist is optimized in a reduced solution space constrained by the manufacturability requirements, which include minimum distance between poles, minimum opening pole angles, minimum ring width and minimum source filling factor in the sigma space. For additional performance gains, the intensity within the optimized source can vary in a gray-tone fashion (eight shades used in this work). Although this new optimization approach can sometimes produce closely spaced

  11. Combinatorial Investigation of ZrO2-Based Dielectric Materials for Dynamic Random-Access Memory Capacitors

    NASA Astrophysics Data System (ADS)

    Kiyota, Yuji; Itaka, Kenji; Iwashita, Yuta; Adachi, Tetsuya; Chikyow, Toyohiro; Ogura, Atsushi

    2011-06-01

    We investigated zirconia (ZrO2)-based material libraries in search of new dielectric materials for dynamic random-access memory (DRAM) by combinatorial-pulsed laser deposition (combi-PLD). We found that the substitution of yttrium (Y) to Zr sites in the ZrO2 system suppressed the leakage current effectively. The metal-insulator-metal (MIM) capacitor property of this system showed a leakage current density of less than 5×10-7 A/cm2 and the dielectric constant was 20. Moreover, the addition of titanium (Ti) or tantalum (Ta) to this system caused the dielectric constant to increase to ˜25 within the allowed leakage level of 5×10-7 A/cm2. Therefore, Zr-Y-Ti-O and Zr-Y-Ta-O systems have good potentials for use as new materials with high dielectric constants of DRAM capacitors instead of silicon dioxides (SiO2).

  12. Cost aware cache replacement policy in shared last-level cache for hybrid memory based fog computing

    NASA Astrophysics Data System (ADS)

    Jia, Gangyong; Han, Guangjie; Wang, Hao; Wang, Feng

    2018-04-01

    Fog computing requires a large main memory capacity to decrease latency and increase the Quality of Service (QoS). However, dynamic random access memory (DRAM), the commonly used random access memory, cannot be included into a fog computing system due to its high consumption of power. In recent years, non-volatile memories (NVM) such as Phase-Change Memory (PCM) and Spin-transfer torque RAM (STT-RAM) with their low power consumption have emerged to replace DRAM. Moreover, the currently proposed hybrid main memory, consisting of both DRAM and NVM, have shown promising advantages in terms of scalability and power consumption. However, the drawbacks of NVM, such as long read/write latency give rise to potential problems leading to asymmetric cache misses in the hybrid main memory. Current last level cache (LLC) policies are based on the unified miss cost, and result in poor performance in LLC and add to the cost of using NVM. In order to minimize the cache miss cost in the hybrid main memory, we propose a cost aware cache replacement policy (CACRP) that reduces the number of cache misses from NVM and improves the cache performance for a hybrid memory system. Experimental results show that our CACRP behaves better in LLC performance, improving performance up to 43.6% (15.5% on average) compared to LRU.

  13. Diagnosis of NMOS DRAM functional performance as affected by a picosecond dye laser

    NASA Technical Reports Server (NTRS)

    Kim, Q.; Schwartz, H. R.; Edmonds, L. D.; Zoutendyk, J. A.

    1992-01-01

    A picosec pulsed dye laser beam was at selected wavelengths successfully used to simulate heavy-ion single-event effects (SEEs) in negative channel NMOS DRAMs. A DRAM was used to develop the test technique because bit-mapping capability and previous heavy-ion upset data were available. The present analysis is the first to establish such a correlation between laser and heavy-ion data for devices, such as the NMOS DRAM, where charge collection is dominated by long-range diffusion, which is controlled by carrier density at remote distances from a depletion region. In the latter case, penetration depth is an important parameter and is included in the present analysis. A single-pulse picosecond dye laser beam (1.5 microns diameter) focused onto a single cell component can upset a single memory cell; clusters of memory cell upsets (multiple errors) were observed when the laser energy was increased above the threshold energy. The multiple errors were analyzed as a function of the bias voltage and total energy of a single pulse. A diffusion model to distinguish the multiple upsets from the laser-induced charge agreed well with previously reported heavy ion data.

  14. Space Radiation Effects in Advanced Flash Memories

    NASA Technical Reports Server (NTRS)

    Johnston, A. H.

    2001-01-01

    Memory storage requirements in space systems have steadily increased, much like storage requirements in terrestrial systems. Large arrays of dynamic memories (DRAMs) have been used in solid-state recorders, relying on a combination of shielding and error-detection-and correction (EDAC) to overcome the extreme sensitivity of DRAMs to space radiation. For example, a 2-Gbit memory (with 4-Mb DRAMs) used on the Clementine mission functioned perfectly during its moon mapping mission, in spite of an average of 71 memory bit flips per day from heavy ions. Although EDAC worked well with older types of memory circuits, newer DRAMs use extremely complex internal architectures which has made it increasingly difficult to implement EDAC. Some newer DRAMs have also exhibited catastrophic latchup. Flash memories are an intriguing alternative to DRAMs because of their nonvolatile storage and extremely high storage density, particularly for applications where writing is done relatively infrequently. This paper discusses radiation effects in advanced flash memories, including general observations on scaling and architecture as well as the specific experience obtained at the Jet Propulsion Laboratory in evaluating high-density flash memories for use on the NASA mission to Europa, one of Jupiter's moons. This particular mission must pass through the Jovian radiation belts, which imposes a very demanding radiation requirement.

  15. Towards Terabit Memories

    NASA Astrophysics Data System (ADS)

    Hoefflinger, Bernd

    Memories have been the major yardstick for the continuing validity of Moore's law. In single-transistor-per-Bit dynamic random-access memories (DRAM), the number of bits per chip pretty much gives us the number of transistors. For decades, DRAM's have offered the largest storage capacity per chip. However, DRAM does not scale any longer, both in density and voltage, severely limiting its power efficiency to 10 fJ/b. A differential DRAM would gain four-times in density and eight-times in energy. Static CMOS RAM (SRAM) with its six transistors/cell is gaining in reputation because it scales well in cell size and operating voltage so that its fundamental advantage of speed, non-destructive read-out and low-power standby could lead to just 2.5 electrons/bit in standby and to a dynamic power efficiency of 2aJ/b. With a projected 2020 density of 16 Gb/cm², the SRAM would be as dense as normal DRAM and vastly better in power efficiency, which would mean a major change in the architecture and market scenario for DRAM versus SRAM. Non-volatile Flash memory have seen two quantum jumps in density well beyond the roadmap: Multi-Bit storage per transistor and high-density TSV (through-silicon via) technology. The number of electrons required per Bit on the storage gate has been reduced since their first realization in 1996 by more than an order of magnitude to 400 electrons/Bit in 2010 for a complexity of 32Gbit per chip at the 32 nm node. Chip stacking of eight chips with TSV has produced a 32GByte solid-state drive (SSD). A stack of 32 chips with 2 b/cell at the 16 nm node will reach a density of 2.5 Terabit/cm². Non-volatile memory with a density of 10 × 10 nm²/Bit is the target for widespread development. Phase-change memory (PCM) and resistive memory (RRAM) lead in cell density, and they will reach 20 Gb/cm² in 2D and higher with 3D chip stacking. This is still almost an order-of-magnitude less than Flash. However, their read-out speed is ~10-times faster, with as yet

  16. Random Telegraph Signal-Like Fluctuation Created by Fowler-Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

    NASA Astrophysics Data System (ADS)

    Kim, Heesang; Oh, Byoungchan; Kim, Kyungdo; Cha, Seon-Yong; Jeong, Jae-Goan; Hong, Sung-Joo; Lee, Jong-Ho; Park, Byung-Gook; Shin, Hyungcheol

    2010-09-01

    We generated traps inside gate oxide in gate-drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler-Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal-oxide-semiconductor field-effect transistors (MOSFETs).

  17. Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines

    NASA Technical Reports Server (NTRS)

    Biswas, Rupak; Gaeke, Brian R.; Husbands, Parry; Li, Xiaoye S.; Oliker, Leonid; Yelick, Katherine A.; Biegel, Bryan (Technical Monitor)

    2002-01-01

    The increasing gap between processor and memory performance has lead to new architectural models for memory-intensive applications. In this paper, we explore the performance of a set of memory-intensive benchmarks and use them to compare the performance of conventional cache-based microprocessors to a mixed logic and DRAM processor called VIRAM. The benchmarks are based on problem statements, rather than specific implementations, and in each case we explore the fundamental hardware requirements of the problem, as well as alternative algorithms and data structures that can help expose fine-grained parallelism or simplify memory access patterns. The benchmarks are characterized by their memory access patterns, their basic control structures, and the ratio of computation to memory operation.

  18. Accessing memory

    DOEpatents

    Yoon, Doe Hyun; Muralimanohar, Naveen; Chang, Jichuan; Ranganthan, Parthasarathy

    2017-09-26

    A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips. A data access is performed on only the first independently selectable logical sub-rank to access second data via the wide internal data bus. The example method also involves locating a first portion of the first data, a second portion of the first data, and the second data on the narrow external data bus during separate data transfers.

  19. Two-level main memory co-design: Multi-threaded algorithmic primitives, analysis, and simulation

    DOE PAGES

    Bender, Michael A.; Berry, Jonathan W.; Hammond, Simon D.; ...

    2017-01-03

    A challenge in computer architecture is that processors often cannot be fed data from DRAM as fast as CPUs can consume it. Therefore, many applications are memory-bandwidth bound. With this motivation and the realization that traditional architectures (with all DRAM reachable only via bus) are insufficient to feed groups of modern processing units, vendors have introduced a variety of non-DDR 3D memory technologies (Hybrid Memory Cube (HMC),Wide I/O 2, High Bandwidth Memory (HBM)). These offer higher bandwidth and lower power by stacking DRAM chips on the processor or nearby on a silicon interposer. We will call these solutions “near-memory,” andmore » if user-addressable, “scratchpad.” High-performance systems on the market now offer two levels of main memory: near-memory on package and traditional DRAM further away. In the near term we expect the latencies near-memory and DRAM to be similar. Here, it is natural to think of near-memory as another module on the DRAM level of the memory hierarchy. Vendors are expected to offer modes in which the near memory is used as cache, but we believe that this will be inefficient.« less

  20. Light sensitivity of a one transistor-one capacitor memory cell when used as a micromirror actuator in projector applications

    NASA Astrophysics Data System (ADS)

    Huffman, James Douglas

    2001-11-01

    The most important issue facing the future business success of the Digital Micromirror Device or DMD™ produced by Texas Instruments is the cost of the actual device. As the business and consumer markets call for higher resolution displays, the array size will have to be increased to incorporate more pixels. The manufacturing costs associated with building these higher resolution displays follow an exponential relation with the number of pixels due to yield loss and reduced number of chips per silicon wafer. Each pixel is actuated by electrostatics that are provided by a memory cell that is built in the underlying silicon substrate. One way to decrease cost of the wafer is to change the memory cell architecture from a static random access configuration or SRAM to a dynamic random access configuration or DRAM. This change has the benefits of having fewer components per area and a lower metal density. This reduction in the component count and metal density has a dramatic effect on the yield of the memory array by reducing the particle sensitivity of the underlying cell. The main drawback to using a DRAM configuration in a display application is the light sensitivity of a charge storage device built in the silicon substrate. As the photons pass through the mechanical micromirrors and illuminate the DRAM cell, the effective electrostatic potential of the memory element used for the mirror actuation is reduced. This dissertation outlines the issues associated with the light sensitivity of a DRAM memory cell as the actuation element for a micromirror. The concept of charge depletion on a silicon capacitor due to recombination of photogenerated carriers is explored and experimentally verified. The effects of the reduced potential on the capacitor on the micromirror are also explored. Optical modeling is used to determine the incoming photon flux to determine the benefits of adding a charge recombination region as part of the DRAM memory cell. Several options are explored

  1. Atomic memory access hardware implementations

    DOEpatents

    Ahn, Jung Ho; Erez, Mattan; Dally, William J

    2015-02-17

    Atomic memory access requests are handled using a variety of systems and methods. According to one example method, a data-processing circuit having an address-request generator that issues requests to a common memory implements a method of processing the requests using a memory-access intervention circuit coupled between the generator and the common memory. The method identifies a current atomic-memory access request from a plurality of memory access requests. A data set is stored that corresponds to the current atomic-memory access request in a data storage circuit within the intervention circuit. It is determined whether the current atomic-memory access request corresponds to at least one previously-stored atomic-memory access request. In response to determining correspondence, the current request is implemented by retrieving data from the common memory. The data is modified in response to the current request and at least one other access request in the memory-access intervention circuit.

  2. Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

    NASA Astrophysics Data System (ADS)

    Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

    2018-04-01

    In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

  3. Non-volatile, high density, high speed, Micromagnet-Hall effect Random Access Memory (MHRAM)

    NASA Technical Reports Server (NTRS)

    Wu, Jiin C.; Katti, Romney R.; Stadler, Henry L.

    1991-01-01

    The micromagnetic Hall effect random access memory (MHRAM) has the potential of replacing ROMs, EPROMs, EEPROMs, and SRAMs because of its ability to achieve non-volatility, radiation hardness, high density, and fast access times, simultaneously. Information is stored magnetically in small magnetic elements (micromagnets), allowing unlimited data retention time, unlimited numbers of rewrite cycles, and inherent radiation hardness and SEU immunity, making the MHRAM suitable for ground based as well as spaceflight applications. The MHRAM device design is not affected by areal property fluctuations in the micromagnet, so high operating margins and high yield can be achieved in large scale integrated circuit (IC) fabrication. The MHRAM has short access times (less than 100 nsec). Write access time is short because on-chip transistors are used to gate current quickly, and magnetization reversal in the micromagnet can occur in a matter of a few nanoseconds. Read access time is short because the high electron mobility sensor (InAs or InSb) produces a large signal voltage in response to the fringing magnetic field from the micromagnet. High storage density is achieved since a unit cell consists only of two transistors and one micromagnet Hall effect element. By comparison, a DRAM unit cell has one transistor and one capacitor, and a SRAM unit cell has six transistors.

  4. PIMS: Memristor-Based Processing-in-Memory-and-Storage.

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Cook, Jeanine

    Continued progress in computing has augmented the quest for higher performance with a new quest for higher energy efficiency. This has led to the re-emergence of Processing-In-Memory (PIM) ar- chitectures that offer higher density and performance with some boost in energy efficiency. Past PIM work either integrated a standard CPU with a conventional DRAM to improve the CPU- memory link, or used a bit-level processor with Single Instruction Multiple Data (SIMD) control, but neither matched the energy consumption of the memory to the computation. We originally proposed to develop a new architecture derived from PIM that more effectively addressed energymore » efficiency for high performance scientific, data analytics, and neuromorphic applications. We also originally planned to implement a von Neumann architecture with arithmetic/logic units (ALUs) that matched the power consumption of an advanced storage array to maximize energy efficiency. Implementing this architecture in storage was our original idea, since by augmenting storage (in- stead of memory), the system could address both in-memory computation and applications that accessed larger data sets directly from storage, hence Processing-in-Memory-and-Storage (PIMS). However, as our research matured, we discovered several things that changed our original direc- tion, the most important being that a PIM that implements a standard von Neumann-type archi- tecture results in significant energy efficiency improvement, but only about a O(10) performance improvement. In addition to this, the emergence of new memory technologies moved us to propos- ing a non-von Neumann architecture, called Superstrider, implemented not in storage, but in a new DRAM technology called High Bandwidth Memory (HBM). HBM is a stacked DRAM tech- nology that includes a logic layer where an architecture such as Superstrider could potentially be implemented.« less

  5. Quantum random access memory.

    PubMed

    Giovannetti, Vittorio; Lloyd, Seth; Maccone, Lorenzo

    2008-04-25

    A random access memory (RAM) uses n bits to randomly address N=2(n) distinct memory cells. A quantum random access memory (QRAM) uses n qubits to address any quantum superposition of N memory cells. We present an architecture that exponentially reduces the requirements for a memory call: O(logN) switches need be thrown instead of the N used in conventional (classical or quantum) RAM designs. This yields a more robust QRAM algorithm, as it in general requires entanglement among exponentially less gates, and leads to an exponential decrease in the power needed for addressing. A quantum optical implementation is presented.

  6. A method to monitor the quality of ultra-thin nitride for trench DRAM with a buried strap structure

    NASA Astrophysics Data System (ADS)

    Wu, Yung-Hsien; Wang, Chun-Yao; Chang, Ian; Kao, Chien-Kang; Kuo, Chia-Ming; Ku, Alex

    2007-02-01

    A new approach to monitor the quality of an ultra-thin nitride film has been proposed. The nitride quality is monitored by observing the oxide thickness for the nitride film after wet oxidation since the resistance to oxidation strongly depends on its quality. To obtain a stable oxide thickness without interference from extrinsic factors for process monitoring, monitor wafers without dilute HF solution clean are suggested because the native-oxide containing surface is less sensitive to oxygen and therefore forms the nitride film with stable quality. In addition, the correlation between variable retention time (VRT) performance of a real dynamic random access memory (DRAM) product and oxide thickness from different nitride process temperatures can be successfully explained and this correlation can also be used to establish the appropriate oxide thickness range for process monitoring.

  7. Non-volatile main memory management methods based on a file system.

    PubMed

    Oikawa, Shuichi

    2014-01-01

    There are upcoming non-volatile (NV) memory technologies that provide byte addressability and high performance. PCM, MRAM, and STT-RAM are such examples. Such NV memory can be used as storage because of its data persistency without power supply while it can be used as main memory because of its high performance that matches up with DRAM. There are a number of researches that investigated its uses for main memory and storage. They were, however, conducted independently. This paper presents the methods that enables the integration of the main memory and file system management for NV memory. Such integration makes NV memory simultaneously utilized as both main memory and storage. The presented methods use a file system as their basis for the NV memory management. We implemented the proposed methods in the Linux kernel, and performed the evaluation on the QEMU system emulator. The evaluation results show that 1) the proposed methods can perform comparably to the existing DRAM memory allocator and significantly better than the page swapping, 2) their performance is affected by the internal data structures of a file system, and 3) the data structures appropriate for traditional hard disk drives do not always work effectively for byte addressable NV memory. We also performed the evaluation of the effects caused by the longer access latency of NV memory by cycle-accurate full-system simulation. The results show that the effect on page allocation cost is limited if the increase of latency is moderate.

  8. Memory availability and referential access

    PubMed Central

    Johns, Clinton L.; Gordon, Peter C.; Long, Debra L.; Swaab, Tamara Y.

    2013-01-01

    Most theories of coreference specify linguistic factors that modulate antecedent accessibility in memory; however, whether non-linguistic factors also affect coreferential access is unknown. Here we examined the impact of a non-linguistic generation task (letter transposition) on the repeated-name penalty, a processing difficulty observed when coreferential repeated names refer to syntactically prominent (and thus more accessible) antecedents. In Experiment 1, generation improved online (event-related potentials) and offline (recognition memory) accessibility of names in word lists. In Experiment 2, we manipulated generation and syntactic prominence of antecedent names in sentences; both improved online and offline accessibility, but only syntactic prominence elicited a repeated-name penalty. Our results have three important implications: first, the form of a referential expression interacts with an antecedent’s status in the discourse model during coreference; second, availability in memory and referential accessibility are separable; and finally, theories of coreference must better integrate known properties of the human memory system. PMID:24443621

  9. Programmable digital memory devices based on nanoscale thin films of a thermally dimensionally stable polyimide

    NASA Astrophysics Data System (ADS)

    Lee, Taek Joon; Chang, Cha-Wen; Hahm, Suk Gyu; Kim, Kyungtae; Park, Samdae; Kim, Dong Min; Kim, Jinchul; Kwon, Won-Sang; Liou, Guey-Sheng; Ree, Moonhor

    2009-04-01

    We have fabricated electrically programmable memory devices with thermally and dimensionally stable poly(N-(N',N'-diphenyl-N'-1,4-phenyl)-N,N-4,4'-diphenylene hexafluoroisopropylidene-diphthalimide) (6F-2TPA PI) films and investigated their switching characteristics and reliability. 6F-2TPA PI films were found to reveal a conductivity of 1.0 × 10-13-1.0 × 10-14 S cm-1. The 6F-2TPA PI films exhibit versatile memory characteristics that depend on the film thickness. All the PI films are initially present in the OFF state. The PI films with a thickness of >15 to <100 nm exhibit excellent write-once-read-many-times (WORM) (i.e. fuse-type) memory characteristics with and without polarity depending on the thickness. The WORM memory devices are electrically stable, even in air ambient, for a very long time. The devices' ON/OFF current ratio is high, up to 1010. Therefore, these WORM memory devices can provide an efficient, low-cost means of permanent data storage. On the other hand, the 100 nm thick PI films exhibit excellent dynamic random access memory (DRAM) characteristics with polarity. The ON/OFF current ratio of the DRAM devices is as high as 1011. The observed electrical switching behaviors were found to be governed by trap-limited space-charge-limited conduction and local filament formation and further dependent on the differences between the highest occupied molecular orbital and the lowest unoccupied molecular orbital energy levels of the PI film and the work functions of the top and bottom electrodes as well as the PI film thickness. In summary, the excellent memory properties of 6F-2TPA PI make it a promising candidate material for the low-cost mass production of high density and very stable digital nonvolatile WORM and volatile DRAM memory devices.

  10. Programmable digital memory devices based on nanoscale thin films of a thermally dimensionally stable polyimide.

    PubMed

    Lee, Taek Joon; Chang, Cha-Wen; Hahm, Suk Gyu; Kim, Kyungtae; Park, Samdae; Kim, Dong Min; Kim, Jinchul; Kwon, Won-Sang; Liou, Guey-Sheng; Ree, Moonhor

    2009-04-01

    We have fabricated electrically programmable memory devices with thermally and dimensionally stable poly(N-(N',N'-diphenyl-N'-1,4-phenyl)-N,N-4,4'-diphenylene hexafluoroisopropylidene-diphthalimide) (6F-2TPA PI) films and investigated their switching characteristics and reliability. 6F-2TPA PI films were found to reveal a conductivity of 1.0 x 10(-13)-1.0 x 10(-14) S cm(-1). The 6F-2TPA PI films exhibit versatile memory characteristics that depend on the film thickness. All the PI films are initially present in the OFF state. The PI films with a thickness of >15 to <100 nm exhibit excellent write-once-read-many-times (WORM) (i.e. fuse-type) memory characteristics with and without polarity depending on the thickness. The WORM memory devices are electrically stable, even in air ambient, for a very long time. The devices' ON/OFF current ratio is high, up to 10(10). Therefore, these WORM memory devices can provide an efficient, low-cost means of permanent data storage. On the other hand, the 100 nm thick PI films exhibit excellent dynamic random access memory (DRAM) characteristics with polarity. The ON/OFF current ratio of the DRAM devices is as high as 10(11). The observed electrical switching behaviors were found to be governed by trap-limited space-charge-limited conduction and local filament formation and further dependent on the differences between the highest occupied molecular orbital and the lowest unoccupied molecular orbital energy levels of the PI film and the work functions of the top and bottom electrodes as well as the PI film thickness. In summary, the excellent memory properties of 6F-2TPA PI make it a promising candidate material for the low-cost mass production of high density and very stable digital nonvolatile WORM and volatile DRAM memory devices.

  11. Overview of emerging nonvolatile memory technologies

    PubMed Central

    2014-01-01

    Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

  12. Overview of emerging nonvolatile memory technologies.

    PubMed

    Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

    2014-01-01

    Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

  13. Opportunities for nonvolatile memory systems in extreme-scale high-performance computing

    DOE PAGES

    Vetter, Jeffrey S.; Mittal, Sparsh

    2015-01-12

    For extreme-scale high-performance computing systems, system-wide power consumption has been identified as one of the key constraints moving forward, where DRAM main memory systems account for about 30 to 50 percent of a node's overall power consumption. As the benefits of device scaling for DRAM memory slow, it will become increasingly difficult to keep memory capacities balanced with increasing computational rates offered by next-generation processors. However, several emerging memory technologies related to nonvolatile memory (NVM) devices are being investigated as an alternative for DRAM. Moving forward, NVM devices could offer solutions for HPC architectures. Researchers are investigating how to integratemore » these emerging technologies into future extreme-scale HPC systems and how to expose these capabilities in the software stack and applications. In addition, current results show several of these strategies could offer high-bandwidth I/O, larger main memory capacities, persistent data structures, and new approaches for application resilience and output postprocessing, such as transaction-based incremental checkpointing and in situ visualization, respectively.« less

  14. A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Mittal, Sparsh; Vetter, Jeffrey S; Li, Dong

    Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large increase in the size of on-chip caches. Since SRAM has low density and consumes large amount of leakage power, its use in designing on-chip caches has become more challenging. To address this issue, researchers are exploring the use of several emerging memory technologies, such as embedded DRAM, spin transfer torque RAM, resistive RAM, phase change RAM and domain wall memory. In this paper, we survey the architectural approaches proposed for designing memory systems and, specifically, caches with these emerging memory technologies. To highlight theirmore » similarities and differences, we present a classification of these technologies and architectural approaches based on their key characteristics. We also briefly summarize the challenges in using these technologies for architecting caches. We believe that this survey will help the readers gain insights into the emerging memory device technologies, and their potential use in designing future computing systems.« less

  15. Angular dependence of DRAM upset susceptibility

    NASA Technical Reports Server (NTRS)

    Guertin, S. M.; Swift, G. M.; Edmonds, L. D.

    2000-01-01

    Heavy ion irradiations of two types of commercial DRAMs reveal unexpected angular responses. One device's cross section varied by two orders of magnitude with azimuthal angle. Accurate prediction of space rates requires accommodating this effect.

  16. An FPGA-Based Test-Bed for Reliability and Endurance Characterization of Non-Volatile Memory

    NASA Technical Reports Server (NTRS)

    Rao, Vikram; Patel, Jagdish; Patel, Janak; Namkung, Jeffrey

    2001-01-01

    Memory technologies are divided into two categories. The first category, nonvolatile memories, are traditionally used in read-only or read-mostly applications because of limited write endurance and slow write speed. These memories are derivatives of read only memory (ROM) technology, which includes erasable programmable ROM (EPROM), electrically-erasable programmable ROM (EEPROM), Flash, and more recent ferroelectric non-volatile memory technology. Nonvolatile memories are able to retain data in the absence of power. The second category, volatile memories, are random access memory (RAM) devices including SRAM and DRAM. Writing to these memories is fast and write endurance is unlimited, so they are most often used to store data that change frequently, but they cannot store data in the absence of power. Nonvolatile memory technologies with better future potential are FRAM, Chalcogenide, GMRAM, Tunneling MRAM, and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) EEPROM.

  17. Garnet Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R.

    1995-01-01

    Random-access memory (RAM) devices of proposed type exploit magneto-optical properties of magnetic garnets exhibiting perpendicular anisotropy. Magnetic writing and optical readout used. Provides nonvolatile storage and resists damage by ionizing radiation. Because of basic architecture and pinout requirements, most likely useful as small-capacity memory devices.

  18. Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

    DOEpatents

    Ohmacht, Martin

    2017-08-15

    In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

  19. Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

    DOEpatents

    Ohmacht, Martin

    2014-09-09

    In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

  20. Experimental realization of a multiplexed quantum memory with 225 individually accessible memory cells

    PubMed Central

    Pu, Y-F; Jiang, N.; Chang, W.; Yang, H-X; Li, C.; Duan, L-M

    2017-01-01

    To realize long-distance quantum communication and quantum network, it is required to have multiplexed quantum memory with many memory cells. Each memory cell needs to be individually addressable and independently accessible. Here we report an experiment that realizes a multiplexed DLCZ-type quantum memory with 225 individually accessible memory cells in a macroscopic atomic ensemble. As a key element for quantum repeaters, we demonstrate that entanglement with flying optical qubits can be stored into any neighboring memory cells and read out after a programmable time with high fidelity. Experimental realization of a multiplexed quantum memory with many individually accessible memory cells and programmable control of its addressing and readout makes an important step for its application in quantum information technology. PMID:28480891

  1. Experimental realization of a multiplexed quantum memory with 225 individually accessible memory cells.

    PubMed

    Pu, Y-F; Jiang, N; Chang, W; Yang, H-X; Li, C; Duan, L-M

    2017-05-08

    To realize long-distance quantum communication and quantum network, it is required to have multiplexed quantum memory with many memory cells. Each memory cell needs to be individually addressable and independently accessible. Here we report an experiment that realizes a multiplexed DLCZ-type quantum memory with 225 individually accessible memory cells in a macroscopic atomic ensemble. As a key element for quantum repeaters, we demonstrate that entanglement with flying optical qubits can be stored into any neighboring memory cells and read out after a programmable time with high fidelity. Experimental realization of a multiplexed quantum memory with many individually accessible memory cells and programmable control of its addressing and readout makes an important step for its application in quantum information technology.

  2. The future of memory

    NASA Astrophysics Data System (ADS)

    Marinella, M.

    In the not too distant future, the traditional memory and storage hierarchy of may be replaced by a single Storage Class Memory (SCM) device integrated on or near the logic processor. Traditional magnetic hard drives, NAND flash, DRAM, and higher level caches (L2 and up) will be replaced with a single high performance memory device. The Storage Class Memory paradigm will require high speed (< 100 ns read/write), excellent endurance (> 1012), nonvolatility (retention > 10 years), and low switching energies (< 10 pJ per switch). The International Technology Roadmap for Semiconductors (ITRS) has recently evaluated several potential candidates SCM technologies, including Resistive (or Redox) RAM, Spin Torque Transfer RAM (STT-MRAM), and phase change memory (PCM). All of these devices show potential well beyond that of current flash technologies and research efforts are underway to improve the endurance, write speeds, and scalabilities to be on-par with DRAM. This progress has interesting implications for space electronics: each of these emerging device technologies show excellent resistance to the types of radiation typically found in space applications. Commercially developed, high density storage class memory-based systems may include a memory that is physically radiation hard, and suitable for space applications without major shielding efforts. This paper reviews the Storage Class Memory concept, emerging memory devices, and possible applicability to radiation hardened electronics for space.

  3. Is random access memory random?

    NASA Technical Reports Server (NTRS)

    Denning, P. J.

    1986-01-01

    Most software is contructed on the assumption that the programs and data are stored in random access memory (RAM). Physical limitations on the relative speeds of processor and memory elements lead to a variety of memory organizations that match processor addressing rate with memory service rate. These include interleaved and cached memory. A very high fraction of a processor's address requests can be satified from the cache without reference to the main memory. The cache requests information from main memory in blocks that can be transferred at the full memory speed. Programmers who organize algorithms for locality can realize the highest performance from these computers.

  4. 75 FR 9438 - Samsung Austin Semiconductor, LLC, DRAM Fab 1, a Subsidiary of Samsung Electronics Corporation...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-03-02

    ... Semiconductor, LLC, DRAM Fab 1, a Subsidiary of Samsung Electronics Corporation, Including On-Site Leased... Semiconductor, LLC, a subsidiary of Samsung Electronics Corporation, DRAM Fab 1, including on-site leased.... The workers are engaged in activities related to the production of DRAM chips for use in electronics...

  5. Rutger's CAM2000 chip architecture

    NASA Technical Reports Server (NTRS)

    Smith, Donald E.; Hall, J. Storrs; Miyake, Keith

    1993-01-01

    This report describes the architecture and instruction set of the Rutgers CAM2000 memory chip. The CAM2000 combines features of Associative Processing (AP), Content Addressable Memory (CAM), and Dynamic Random Access Memory (DRAM) in a single chip package that is not only DRAM compatible but capable of applying simple massively parallel operations to memory. This document reflects the current status of the CAM2000 architecture and is continually updated to reflect the current state of the architecture and instruction set.

  6. CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

    NASA Astrophysics Data System (ADS)

    Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

    2018-04-01

    Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

  7. Materials and other needs for advanced phase change memory (Presentation Recording)

    NASA Astrophysics Data System (ADS)

    Sosa, Norma E.

    2015-09-01

    Phase change memory (PCM), with its long history, may now hold its brightest promise to date. This bright future is being fueled by the "push" from big data. PCM is a non-volatile memory technology used to create solid-state random access memory devices that operate based the resistance properties of materials. Employing the electrical resistance differences-as opposed to differences in charge stored-between the amorphous and crystalline phases of the material, PCM can store bits, namely one's and zero's. Indeed, owing to the method of storage, PCM can in fact be designed to hold multiple bits thus leading to a high-density technology twice the storage density and less than half the cost of DRAM, the main kind found in typical personal computers. It has been long known that PCM can fill a need gap that spans 3 decades in performance from DRAM to solid state drive (NAND Flash). Furthermore, PCM devices can lead to performance and reliability improvements essential to enabling significant steps forward to supporting big data centric computing. This talk will focus on the science and challenges of aggressive scaling to realize the density needed, how this scaling challenge is intertwined with materials needs for endurance into the giga-cycles, and the associated forefront research aiming to realizing multi-level functionality into these nanoscale programmable resistor devices.

  8. Low latency memory access and synchronization

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.

    A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processormore » only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.« less

  9. Low latency memory access and synchronization

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.

    A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Bach processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processormore » only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.« less

  10. Memory Benchmarks for SMP-Based High Performance Parallel Computers

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Yoo, A B; de Supinski, B; Mueller, F

    2001-11-20

    As the speed gap between CPU and main memory continues to grow, memory accesses increasingly dominates the performance of many applications. The problem is particularly acute for symmetric multiprocessor (SMP) systems, where the shared memory may be accessed concurrently by a group of threads running on separate CPUs. Unfortunately, several key issues governing memory system performance in current systems are not well understood. Complex interactions between the levels of the memory hierarchy, buses or switches, DRAM back-ends, system software, and application access patterns can make it difficult to pinpoint bottlenecks and determine appropriate optimizations, and the situation is even moremore » complex for SMP systems. To partially address this problem, we formulated a set of multi-threaded microbenchmarks for characterizing and measuring the performance of the underlying memory system in SMP-based high-performance computers. We report our use of these microbenchmarks on two important SMP-based machines. This paper has four primary contributions. First, we introduce a microbenchmark suite to systematically assess and compare the performance of different levels in SMP memory hierarchies. Second, we present a new tool based on hardware performance monitors to determine a wide array of memory system characteristics, such as cache sizes, quickly and easily; by using this tool, memory performance studies can be targeted to the full spectrum of performance regimes with many fewer data points than is otherwise required. Third, we present experimental results indicating that the performance of applications with large memory footprints remains largely constrained by memory. Fourth, we demonstrate that thread-level parallelism further degrades memory performance, even for the latest SMPs with hardware prefetching and switch-based memory interconnects.« less

  11. Method and apparatus for managing access to a memory

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    DeBenedictis, Erik

    A method and apparatus for managing access to a memory of a computing system. A controller transforms a plurality of operations that represent a computing job into an operational memory layout that reduces a size of a selected portion of the memory that needs to be accessed to perform the computing job. The controller stores the operational memory layout in a plurality of memory cells within the selected portion of the memory. The controller controls a sequence by which a processor in the computing system accesses the memory to perform the computing job using the operational memory layout. The operationalmore » memory layout reduces an amount of energy consumed by the processor to perform the computing job.« less

  12. Layout optimization of DRAM cells using rigorous simulation model for NTD

    NASA Astrophysics Data System (ADS)

    Jeon, Jinhyuck; Kim, Shinyoung; Park, Chanha; Yang, Hyunjo; Yim, Donggyu; Kuechler, Bernd; Zimmermann, Rainer; Muelders, Thomas; Klostermann, Ulrich; Schmoeller, Thomas; Do, Mun-hoe; Choi, Jung-Hoe

    2014-03-01

    DRAM chip space is mainly determined by the size of the memory cell array patterns which consist of periodic memory cell features and edges of the periodic array. Resolution Enhancement Techniques (RET) are used to optimize the periodic pattern process performance. Computational Lithography such as source mask optimization (SMO) to find the optimal off axis illumination and optical proximity correction (OPC) combined with model based SRAF placement are applied to print patterns on target. For 20nm Memory Cell optimization we see challenges that demand additional tool competence for layout optimization. The first challenge is a memory core pattern of brick-wall type with a k1 of 0.28, so it allows only two spectral beams to interfere. We will show how to analytically derive the only valid geometrically limited source. Another consequence of two-beam interference limitation is a "super stable" core pattern, with the advantage of high depth of focus (DoF) but also low sensitivity to proximity corrections or changes of contact aspect ratio. This makes an array edge correction very difficult. The edge can be the most critical pattern since it forms the transition from the very stable regime of periodic patterns to non-periodic periphery, so it combines the most critical pitch and highest susceptibility to defocus. Above challenge makes the layout correction to a complex optimization task demanding a layout optimization that finds a solution with optimal process stability taking into account DoF, exposure dose latitude (EL), mask error enhancement factor (MEEF) and mask manufacturability constraints. This can only be achieved by simultaneously considering all criteria while placing and sizing SRAFs and main mask features. The second challenge is the use of a negative tone development (NTD) type resist, which has a strong resist effect and is difficult to characterize experimentally due to negative resist profile taper angles that perturb CD at bottom characterization by

  13. DRAM Triggers Lysosomal Membrane Permeabilization and Cell Death in CD4+ T Cells Infected with HIV

    PubMed Central

    Laforge, Mireille; Limou, Sophie; Harper, Francis; Casartelli, Nicoletta; Rodrigues, Vasco; Silvestre, Ricardo; Haloui, Houda; Zagury, Jean-Francois; Senik, Anna; Estaquier, Jerome

    2013-01-01

    Productive HIV infection of CD4+ T cells leads to a caspase-independent cell death pathway associated with lysosomal membrane permeabilization (LMP) and cathepsin release, resulting in mitochondrial outer membrane permeabilization (MOMP). Herein, we demonstrate that HIV infection induces damage-regulated autophagy modulator (DRAM) expression in a p53-dependent manner. Knocking down the expression of DRAM and p53 genes with specific siRNAs inhibited autophagy and LMP. However, inhibition of Atg5 and Beclin genes that prevents autophagy had a minor effect on LMP and cell death. The knock down of DRAM gene inhibited cytochrome C release, MOMP and cell death. However, knocking down DRAM, we increased viral infection and production. Our study shows for the first time the involvement of DRAM in host-pathogen interactions, which may represent a mechanism of defense via the elimination of infected cells. PMID:23658518

  14. Programmable Direct-Memory-Access Controller

    NASA Technical Reports Server (NTRS)

    Hendry, David F.

    1990-01-01

    Proposed programmable direct-memory-access controller (DMAC) operates with computer systems of 32000 series, which have 32-bit data buses and use addresses of 24 (or potentially 32) bits. Controller functions with or without help of central processing unit (CPU) and starts itself. Includes such advanced features as ability to compare two blocks of memory for equality and to search block of memory for specific value. Made as single very-large-scale integrated-circuit chip.

  15. Plated wire random access memories

    NASA Technical Reports Server (NTRS)

    Gouldin, L. D.

    1975-01-01

    A program was conducted to construct 4096-work by 18-bit random access, NDRO-plated wire memory units. The memory units were subjected to comprehensive functional and environmental tests at the end-item level to verify comformance with the specified requirements. A technical description of the unit is given, along with acceptance test data sheets.

  16. Fast Magnetoresistive Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

    1991-01-01

    Magnetoresistive binary digital memories of proposed new type expected to feature high speed, nonvolatility, ability to withstand ionizing radiation, high density, and low power. In memory cell, magnetoresistive effect exploited more efficiently by use of ferromagnetic material to store datum and adjacent magnetoresistive material to sense datum for readout. Because relative change in sensed resistance between "zero" and "one" states greater, shorter sampling and readout access times achievable.

  17. The storage system of PCM based on random access file system

    NASA Astrophysics Data System (ADS)

    Han, Wenbing; Chen, Xiaogang; Zhou, Mi; Li, Shunfen; Li, Gezi; Song, Zhitang

    2016-10-01

    Emerging memory technologies such as Phase change memory (PCM) tend to offer fast, random access to persistent storage with better scalability. It's a hot topic of academic and industrial research to establish PCM in storage hierarchy to narrow the performance gap. However, the existing file systems do not perform well with the emerging PCM storage, which access storage medium via a slow, block-based interface. In this paper, we propose a novel file system, RAFS, to bring about good performance of PCM, which is built in the embedded platform. We attach PCM chips to the memory bus and build RAFS on the physical address space. In the proposed file system, we simplify traditional system architecture to eliminate block-related operations and layers. Furthermore, we adopt memory mapping and bypassed page cache to reduce copy overhead between the process address space and storage device. XIP mechanisms are also supported in RAFS. To the best of our knowledge, we are among the first to implement file system on real PCM chips. We have analyzed and evaluated its performance with IOZONE benchmark tools. Our experimental results show that the RAFS on PCM outperforms Ext4fs on SDRAM with small record lengths. Based on DRAM, RAFS is significantly faster than Ext4fs by 18% to 250%.

  18. Evaluation of a controlled drinking minimal intervention for problem drinkers in general practice (the DRAMS scheme)

    PubMed Central

    Heather, Nick; Campion, Peter D.; Neville, Ronald G.; Maccabe, David

    1987-01-01

    Sixteen general practitioners participated in a controlled trial of the Scottish Health Education Group's DRAMS (drinking reasonably and moderately with self-control) scheme. The scheme was evaluated by randomly assigning 104 heavy or problem drinkers to three groups – a group participating in the DRAMS scheme (n = 34), a group given simple advice only (n = 32) and a non-intervention control group (n = 38). Six month follow-up information was obtained for 91 subjects (87.5% of initial sample). There were no significant differences between the groups in reduction in alcohol consumption, but patients in the DRAMS group showed a significantly greater reduction in a logarithmic measure of serum gamma-glutamyl-transpeptidase than patients in the group receiving advice only. Only 14 patients in the DRAMS group completed the full DRAMS procedure. For the sample as a whole, there was a significant reduction in alcohol consumption, a significant improvement on a measure of physical health and well-being, and significant reductions in the logarithmic measure of serum gamma-glutamyl transpeptidase and in mean corpuscular volume. The implications of these findings for future research into controlled drinking minimal interventions in general practice are discussed. PMID:3448228

  19. 78 FR 24234 - Certain Semiconductor Chips With DRAM Circuitry, and Modules and Products Containing Same; Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-04-24

    ... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-819] Certain Semiconductor Chips With DRAM Circuitry, and Modules and Products Containing Same; Notice of Request for Statements on the... order barring the entry of unlicensed DRAM semiconductor chips manufactured by Nanya Technology...

  20. Working memory capacity and retrieval limitations from long-term memory: an examination of differences in accessibility.

    PubMed

    Unsworth, Nash; Spillers, Gregory J; Brewer, Gene A

    2012-01-01

    In two experiments, the locus of individual differences in working memory capacity and long-term memory recall was examined. Participants performed categorical cued and free recall tasks, and individual differences in the dynamics of recall were interpreted in terms of a hierarchical-search framework. The results from this study are in accordance with recent theorizing suggesting a strong relation between working memory capacity and retrieval from long-term memory. Furthermore, the results also indicate that individual differences in categorical recall are partially due to differences in accessibility. In terms of accessibility of target information, two important factors drive the difference between high- and low-working-memory-capacity participants. Low-working-memory-capacity participants fail to utilize appropriate retrieval strategies to access cues, and they also have difficulty resolving cue overload. Thus, when low-working-memory-capacity participants were given specific cues that activated a smaller set of potential targets, their recall performance was the same as that of high-working-memory-capacity participants.

  1. Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

    NASA Astrophysics Data System (ADS)

    Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

    2013-06-01

    In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

  2. Non-volatile magnetic random access memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Stadler, Henry L. (Inventor); Wu, Jiin-Chuan (Inventor)

    1994-01-01

    Improvements are made in a non-volatile magnetic random access memory. Such a memory is comprised of an array of unit cells, each having a Hall-effect sensor and a thin-film magnetic element made of material having an in-plane, uniaxial anisotropy and in-plane, bipolar remanent magnetization states. The Hall-effect sensor is made more sensitive by using a 1 m thick molecular beam epitaxy grown InAs layer on a silicon substrate by employing a GaAs/AlGaAs/InAlAs superlattice buffering layer. One improvement avoids current shunting problems of matrix architecture. Another improvement reduces the required magnetizing current for the micromagnets. Another improvement relates to the use of GaAs technology wherein high electron-mobility GaAs MESFETs provide faster switching times. Still another improvement relates to a method for configuring the invention as a three-dimensional random access memory.

  3. The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor.

    PubMed

    Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

    2018-03-05

    The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the reduction of reading "0" current and extension of retention time. The simulation results show that spacers at the source and drain sides should apply the low-k and high-k dielectrics, respectively, which can enhance the reading "1" current and reduce reading "0" current. Applying this optimized spacer engineering, the DGTFET DRAM obtains the optimum performance-extremely low reading "0" current (10 -14 A/μm) and large retention time (10s), which decreases its static power consumption and dynamic refresh rate. And the low reading "0" current also enhances its current ratio (10 7 ) of reading "1" to reading "0". Furthermore, the analysis about scalability reveals its inherent shortcoming, which offers the further investigation direction for DGTFET DRAM.

  4. The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

    NASA Astrophysics Data System (ADS)

    Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

    2018-03-01

    The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the reduction of reading "0" current and extension of retention time. The simulation results show that spacers at the source and drain sides should apply the low-k and high-k dielectrics, respectively, which can enhance the reading "1" current and reduce reading "0" current. Applying this optimized spacer engineering, the DGTFET DRAM obtains the optimum performance-extremely low reading "0" current (10-14A/μm) and large retention time (10s), which decreases its static power consumption and dynamic refresh rate. And the low reading "0" current also enhances its current ratio (107) of reading "1" to reading "0". Furthermore, the analysis about scalability reveals its inherent shortcoming, which offers the further investigation direction for DGTFET DRAM.

  5. Efficient accesses of data structures using processing near memory

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Jayasena, Nuwan S.; Zhang, Dong Ping; Diez, Paula Aguilera

    Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory wheremore » the atomic queue is allocated.« less

  6. The analysis method of the DRAM cell pattern hotspot

    NASA Astrophysics Data System (ADS)

    Lee, Kyusun; Lee, Kweonjae; Chang, Jinman; Kim, Taeheon; Han, Daehan; Hong, Aeran; Kim, Yonghyeon; Kang, Jinyoung; Choi, Bumjin; Lee, Joosung; Lee, Jooyoung; Hong, Hyeongsun; Lee, Kyupil; Jin, Gyoyoung

    2015-03-01

    It is increasingly difficult to determine degree of completion of the patterning and the distribution at the DRAM Cell Patterns. When we research DRAM Device Cell Pattern, there are three big problems currently, it is as follows. First, due to etch loading, it is difficult to predict the potential defect. Second, due to under layer topology, it is impossible to demonstrate the influence of the hotspot. Finally, it is extremely difficult to predict final ACI pattern by the photo simulation, because current patterning process is double patterning technology which means photo pattern is completely different from final etch pattern. Therefore, if the hotspot occurs in wafer, it is very difficult to find it. CD-SEM is the most common pattern measurement tool in semiconductor fabrication site. CD-SEM is used to accurately measure small region of wafer pattern primarily. Therefore, there is no possibility of finding places where unpredictable defect occurs. Even though, "Current Defect detector" can measure a wide area, every chip has same pattern issue, the detector cannot detect critical hotspots. Because defect detecting algorithm of bright field machine is based on image processing, if same problems occur on compared and comparing chip, the machine cannot identify it. Moreover this instrument is not distinguished the difference of distribution about 1nm~3nm. So, "Defect detector" is difficult to handle the data for potential weak point far lower than target CD. In order to solve those problems, another method is needed. In this paper, we introduce the analysis method of the DRAM Cell Pattern Hotspot.

  7. Exploration of perpendicular magnetic anisotropy material system for application in spin transfer torque - Random access memory

    NASA Astrophysics Data System (ADS)

    Natarajarathinam, Anusha

    Perpendicular magnetic anisotropy (PMA) materials have unique advantages when used in magnetic tunnel junctions (MTJ) which are the most critical part of spin-torque transfer random access memory devices (STT-RAMs) that are being researched intensively as future non-volatile memory technology. They have high magnetoresistance which improves their sensitivity. The STT-RAM has several advantages over competing technologies, for instance, low power consumption, non-volatility, ultra-fast read and write speed and high endurance. In personal computers, it can replace SRAM for high-speed applications, Flash for non-volatility, and PSRAM and DRAM for high-speed program execution. The main aim of this research is to identify and optimize the best perpendicular magnetic anisotropy (PMA) material system for application to STT-RAM technology. Preliminary search for perpendicular magnetic anisotropy (PMA) materials for pinned layer for MTJs started with the exploration and optimization of crystalline alloys such as Co50Pd50 alloy, Mn50Al50 and amorphous alloys such as Tb21Fe72Co7 and are first presented in this work. Further optimization includes the study of Co/[Pd/Pt]x multilayers (ML), and the development of perpendicular synthetic antiferromagnets (SAF) utilizing these multilayers. Focused work on capping and seed layers to evaluate interfacial perpendicular anisotropy in free layers for pMTJs is then discussed. Optimization of the full perpendicular magnetic tunnel junction (pMTJ) includes the CoFeB/MgO/CoFeB trilayer coupled to a pinned/pinning layer with perpendicular Co/[Pd/Pt]x SAF and a thin Ta seeded CoFeB free layer. Magnetometry, simulations, annealing studies, transport measurements and TEM analysis on these samples will then be presented.

  8. Synchrotron radiation x-ray photoelectron spectroscopy study on the interface chemistry of high-k PrxAl2-xO3 (x=0-2) dielectrics on TiN for dynamic random access memory applications

    NASA Astrophysics Data System (ADS)

    Schroeder, T.; Lupina, G.; Sohal, R.; Lippert, G.; Wenger, Ch.; Seifarth, O.; Tallarida, M.; Schmeisser, D.

    2007-07-01

    Engineered dielectrics combined with compatible metal electrodes are important materials science approaches to scale three-dimensional trench dynamic random access memory (DRAM) cells. Highly insulating dielectrics with high dielectric constants were engineered in this study on TiN metal electrodes by partly substituting Al in the wide band gap insulator Al2O3 by Pr cations. High quality PrAlO3 metal-insulator-metal capacitors were processed with a dielectric constant of 19, three times higher than in the case of Al2O3 reference cells. As a parasitic low dielectric constant interface layer between PrAlO3 and TiN limits the total performance gain, a systematic nondestructive synchrotron x-ray photoelectron spectroscopy study on the interface chemistry of PrxAl2-xO3 (x =0-2) dielectrics on TiN layers was applied to unveil its chemical origin. The interface layer results from the decreasing chemical reactivity of PrxAl2-xO3 dielectrics with increasing Pr content x to reduce native Ti oxide compounds present on unprotected TiN films. Accordingly, PrAlO3 based DRAM capacitors require strict control of the surface chemistry of the TiN electrode, a parameter furthermore of importance to engineer the band offsets of PrxAl2-xO3/TiN heterojunctions.

  9. Accessibility Limits Recall from Visual Working Memory

    ERIC Educational Resources Information Center

    Rajsic, Jason; Swan, Garrett; Wilson, Daryl E.; Pratt, Jay

    2017-01-01

    In this article, we demonstrate limitations of accessibility of information in visual working memory (VWM). Recently, cued-recall has been used to estimate the fidelity of information in VWM, where the feature of a cued object is reproduced from memory (Bays, Catalao, & Husain, 2009; Wilken & Ma, 2004; Zhang & Luck, 2008). Response…

  10. 76 FR 55417 - In the Matter of Certain Dynamic Random Access Memory and Nand Flash Memory Devices and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-09-07

    ... Access Memory and Nand Flash Memory Devices and Products Containing Same; Notice of Institution of... importation, and the sale within the United States after importation of certain dynamic random access memory and NAND flash memory devices and products containing same by reason of infringement of certain claims...

  11. MIR144* inhibits antimicrobial responses against Mycobacterium tuberculosis in human monocytes and macrophages by targeting the autophagy protein DRAM2.

    PubMed

    Kim, Jin Kyung; Lee, Hye-Mi; Park, Ki-Sun; Shin, Dong-Min; Kim, Tae Sung; Kim, Yi Sak; Suh, Hyun-Woo; Kim, Soo Yeon; Kim, In Soo; Kim, Jin-Man; Son, Ji-Woong; Sohn, Kyung Mok; Jung, Sung Soo; Chung, Chaeuk; Han, Sang-Bae; Yang, Chul-Su; Jo, Eun-Kyeong

    2017-02-01

    Autophagy is an important antimicrobial effector process that defends against Mycobacterium tuberculosis (Mtb), the human pathogen causing tuberculosis (TB). MicroRNAs (miRNAs), endogenous noncoding RNAs, are involved in various biological functions and act as post-transcriptional regulators to target mRNAs. The process by which miRNAs affect antibacterial autophagy and host defense mechanisms against Mtb infections in human monocytes and macrophages is largely uncharacterized. In this study, we show that Mtb significantly induces the expression of MIR144*/hsa-miR-144-5p, which targets the 3'-untranslated region of DRAM2 (DNA damage regulated autophagy modulator 2) in human monocytes and macrophages. Mtb infection downregulated, whereas the autophagy activators upregulated, DRAM2 expression in human monocytes and macrophages by activating AMP-activated protein kinase. In addition, overexpression of MIR144* decreased DRAM2 expression and formation of autophagosomes in human monocytes, whereas inhibition of MIR144* had the opposite effect. Moreover, the levels of MIR144* were elevated, whereas DRAM2 levels were reduced, in human peripheral blood cells and tissues in TB patients, indicating the clinical significance of MIR144* and DRAM2 in human TB. Notably, DRAM2 interacted with BECN1 and UVRAG, essential components of the autophagic machinery, leading to displacement of RUBCN from the BECN1 complex and enhancement of Ptdlns3K activity. Furthermore, MIR144* and DRAM2 were critically involved in phagosomal maturation and enhanced antimicrobial effects against Mtb. Our findings identify a previously unrecognized role of human MIR144* in the inhibition of antibacterial autophagy and the innate host immune response to Mtb. Additionally, these data reveal that DRAM2 is a key coordinator of autophagy activation that enhances antimicrobial activity against Mtb.

  12. A Cerebellar-model Associative Memory as a Generalized Random-access Memory

    NASA Technical Reports Server (NTRS)

    Kanerva, Pentti

    1989-01-01

    A versatile neural-net model is explained in terms familiar to computer scientists and engineers. It is called the sparse distributed memory, and it is a random-access memory for very long words (for patterns with thousands of bits). Its potential utility is the result of several factors: (1) a large pattern representing an object or a scene or a moment can encode a large amount of information about what it represents; (2) this information can serve as an address to the memory, and it can also serve as data; (3) the memory is noise tolerant--the information need not be exact; (4) the memory can be made arbitrarily large and hence an arbitrary amount of information can be stored in it; and (5) the architecture is inherently parallel, allowing large memories to be fast. Such memories can become important components of future computers.

  13. Dielectric relaxation of barium strontium titanate and application to thin films for DRAM capacitors

    NASA Astrophysics Data System (ADS)

    Baniecki, John David

    This thesis examines the issues associated with incorporating the high dielectric constant material Barium Strontium Titanate (BSTO) in to the storage capacitor of a dynamic random access memory (DRAM). The research is focused on two areas: characterizing and understanding the factors that control charge retention in BSTO thin films and modifying the electrical properties using ion implantation. The dielectric relaxation of BSTO thin films deposited by metal-organic chemical vapor deposition (MOCVD) is investigated in the time and frequency domains. It is shown that the frequency dispersion of the complex capacitance of BSTO thin films can be understood in terms of a power-law frequency dependence from 1mHz to 20GHz. From the correspondence between the time and frequency domain measurements, it is concluded that the power-law relaxation currents extend back to the nano second regime of DRAM operation. The temperature, field, and annealing dependence of the dielectric relaxation currents are also investigated and mechanisms for the observed power law relaxation are explored. An equivalent circuit model of a high dielectric constant thin film capacitor is developed based on the electrical measurements and implemented in PSPICE. Excellent agreement is found between the experimental and simulated electrical characteristics showing the utility of the equivalent circuit model in simulating the electrical properties of high dielectric constant thin films. Using the equivalent circuit model, it is shown that the greatest charge loss due to dielectric relaxation occurs during the first read after a refresh time following a write to the opposite logic state for a capacitor that has been written to the same logic state for a long time (opposite state write charge loss). A theoretical closed form expression that is a function of three material parameters is developed which estimates the opposite state write charge loss due to dielectric relaxation. Using the closed form

  14. Memory Circuit Fault Simulator

    NASA Technical Reports Server (NTRS)

    Sheldon, Douglas J.; McClure, Tucker

    2013-01-01

    Spacecraft are known to experience significant memory part-related failures and problems, both pre- and postlaunch. These memory parts include both static and dynamic memories (SRAM and DRAM). These failures manifest themselves in a variety of ways, such as pattern-sensitive failures, timingsensitive failures, etc. Because of the mission critical nature memory devices play in spacecraft architecture and operation, understanding their failure modes is vital to successful mission operation. To support this need, a generic simulation tool that can model different data patterns in conjunction with variable write and read conditions was developed. This tool is a mathematical and graphical way to embed pattern, electrical, and physical information to perform what-if analysis as part of a root cause failure analysis effort.

  15. Radiation Effects of Commercial Resistive Random Access Memories

    NASA Technical Reports Server (NTRS)

    Chen, Dakai; LaBel, Kenneth A.; Berg, Melanie; Wilcox, Edward; Kim, Hak; Phan, Anthony; Figueiredo, Marco; Buchner, Stephen; Khachatrian, Ani; Roche, Nicolas

    2014-01-01

    We present results for the single-event effect response of commercial production-level resistive random access memories. We found that the resistive memory arrays are immune to heavy ion-induced upsets. However, the devices were susceptible to single-event functional interrupts, due to upsets from the control circuits. The intrinsic radiation tolerant nature of resistive memory makes the technology an attractive consideration for future space applications.

  16. Emerging memories

    NASA Astrophysics Data System (ADS)

    Baldi, Livio; Bez, Roberto; Sandhu, Gurtej

    2014-12-01

    Memory is a key component of any data processing system. Following the classical Turing machine approach, memories hold both the data to be processed and the rules for processing them. In the history of microelectronics, the distinction has been rather between working memory, which is exemplified by DRAM, and storage memory, exemplified by NAND. These two types of memory devices now represent 90% of all memory market and 25% of the total semiconductor market, and have been the technology drivers in the last decades. Even if radically different in characteristics, they are however based on the same storage mechanism: charge storage, and this mechanism seems to be near to reaching its physical limits. The search for new alternative memory approaches, based on more scalable mechanisms, has therefore gained new momentum. The status of incumbent memory technologies and their scaling limitations will be discussed. Emerging memory technologies will be analyzed, starting from the ones that are already present for niche applications, and which are getting new attention, thanks to recent technology breakthroughs. Maturity level, physical limitations and potential for scaling will be compared to existing memories. At the end the possible future composition of memory systems will be discussed.

  17. Integrated semiconductor-magnetic random access memory system

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Blaes, Brent R. (Inventor)

    2001-01-01

    The present disclosure describes a non-volatile magnetic random access memory (RAM) system having a semiconductor control circuit and a magnetic array element. The integrated magnetic RAM system uses CMOS control circuit to read and write data magnetoresistively. The system provides a fast access, non-volatile, radiation hard, high density RAM for high speed computing.

  18. Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order

    NASA Technical Reports Server (NTRS)

    Schwab, Andrew J. (Inventor); Aylor, James (Inventor); Hitchcock, Charles Young (Inventor); Wulf, William A. (Inventor); McKee, Sally A. (Inventor); Moyer, Stephen A. (Inventor); Klenke, Robert (Inventor)

    2000-01-01

    A data processing system is disclosed which comprises a data processor and memory control device for controlling the access of information from the memory. The memory control device includes temporary storage and decision ability for determining what order to execute the memory accesses. The compiler detects the requirements of the data processor and selects the data to stream to the memory control device which determines a memory access order. The order in which to access said information is selected based on the location of information stored in the memory. The information is repeatedly accessed from memory and stored in the temporary storage until all streamed information is accessed. The information is stored until required by the data processor. The selection of the order in which to access information maximizes bandwidth and decreases the retrieval time.

  19. Magnet/Hall-Effect Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

    1991-01-01

    In proposed magnet/Hall-effect random-access memory (MHRAM), bits of data stored magnetically in Perm-alloy (or equivalent)-film memory elements and read out by using Hall-effect sensors to detect magnetization. Value of each bit represented by polarity of magnetization. Retains data for indefinite time or until data rewritten. Speed of Hall-effect sensors in MHRAM results in readout times of about 100 nanoseconds. Other characteristics include high immunity to ionizing radiation and storage densities of order 10(Sup6)bits/cm(Sup 2) or more.

  20. An Investigation of Unified Memory Access Performance in CUDA

    PubMed Central

    Landaverde, Raphael; Zhang, Tiansheng; Coskun, Ayse K.; Herbordt, Martin

    2015-01-01

    Managing memory between the CPU and GPU is a major challenge in GPU computing. A programming model, Unified Memory Access (UMA), has been recently introduced by Nvidia to simplify the complexities of memory management while claiming good overall performance. In this paper, we investigate this programming model and evaluate its performance and programming model simplifications based on our experimental results. We find that beyond on-demand data transfers to the CPU, the GPU is also able to request subsets of data it requires on demand. This feature allows UMA to outperform full data transfer methods for certain parallel applications and small data sizes. We also find, however, that for the majority of applications and memory access patterns, the performance overheads associated with UMA are significant, while the simplifications to the programming model restrict flexibility for adding future optimizations. PMID:26594668

  1. Electronics Industry Study Report: Semiconductors and Defense Electronics

    DTIC Science & Technology

    2003-01-01

    Access Memory (DRAM) chips and microprocessors. Samsung , Micron, Hynix, and Infineon control almost three-fourths of the DRAM market,8 while Intel alone...Country 2001 Sales ($B) 2002 Sales ($B) % Change % 2002 Mkt 1 1 Intel U.S. 23.7 24.0 1% 16.9% 2 3 Samsung Semiconductor S. Korea 6.3...located in four major regions: the United States, Europe, Japan, and the Asia-Pacific region (includes South Korea, China, Singapore, Malaysia , Taiwan

  2. Individual differences in memory span: the contribution of rehearsal, access to lexical memory, and output speed.

    PubMed

    Tehan, G; Lalor, D M

    2000-11-01

    Rehearsal speed has traditionally been seen to be the prime determinant of individual differences in memory span. Recent studies, in the main using young children as the subject population, have suggested other contributors to span performance, notably contributions from long-term memory and forgetting and retrieval processes occurring during recall. In the current research we explore individual differences in span with respect to measures of rehearsal, output time, and access to lexical memory. We replicate standard short-term phenomena; we show that the variables that influence children's span performance influence adult performance in the same way; and we show that lexical memory access appears to be a more potent source of individual differences in span than either rehearsal speed or output factors.

  3. 76 FR 80964 - Certain Dynamic Random Access Memory Devices, and Products Containing Same; Institution of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-12-27

    ... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-821] Certain Dynamic Random Access Memory... importation, and the sale within the United States after importation of certain dynamic random access memory... certain dynamic random access memory devices, and products containing same that infringe one or more of...

  4. DOE Office of Scientific and Technical Information (OSTI.GOV)

    Bender, Michael A.; Berry, Jonathan W.; Hammond, Simon D.

    A challenge in computer architecture is that processors often cannot be fed data from DRAM as fast as CPUs can consume it. Therefore, many applications are memory-bandwidth bound. With this motivation and the realization that traditional architectures (with all DRAM reachable only via bus) are insufficient to feed groups of modern processing units, vendors have introduced a variety of non-DDR 3D memory technologies (Hybrid Memory Cube (HMC),Wide I/O 2, High Bandwidth Memory (HBM)). These offer higher bandwidth and lower power by stacking DRAM chips on the processor or nearby on a silicon interposer. We will call these solutions “near-memory,” andmore » if user-addressable, “scratchpad.” High-performance systems on the market now offer two levels of main memory: near-memory on package and traditional DRAM further away. In the near term we expect the latencies near-memory and DRAM to be similar. Here, it is natural to think of near-memory as another module on the DRAM level of the memory hierarchy. Vendors are expected to offer modes in which the near memory is used as cache, but we believe that this will be inefficient.« less

  5. Circuit-Switched Memory Access in Photonic Interconnection Networks for High-Performance Embedded Computing

    DTIC Science & Technology

    2010-07-22

    dependent , providing a natural bandwidth match between compute cores and the memory subsystem. • High Bandwidth Dcnsity. Waveguides crossing the chip...simulate this memory access architecture on a 2S6-core chip with a concentrated 64-node network lIsing detailed traces of high-performance embedded...memory modulcs, wc placc memory access poi nts (MAPs) around the pcriphery of the chip connected to thc nctwork. These MAPs, shown in Figure 4, contain

  6. Accessing sparse arrays in parallel memories

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Banerjee, U.; Gajski, D.; Kuck, D.

    The concept of dense and sparse execution of arrays is introduced. Arrays themselves can be stored in a dense or sparse manner in a parallel memory with m memory modules. The paper proposes hardware for speeding up the execution of array operations of the form c(c/sub 0/+ci)=a(a/sub 0/+ai) op b(b/sub 0/+bi), where a/sub 0/, a, b/sub 0/, b, c/sub 0/, c are integer constants and i is an index variable. The hardware handles 'sparse execution', in which the operation op is not executed for every value of i. The hardware also makes provision for 'sparse storage', in which memory spacemore » is not provided for every array element. It is shown how to access array elements of the above form without conflict in an efficient way. The efficiency is obtained by using some specialised units which are basically smart memories with priority detection, one's counting or associative searching. Generalisation to multidimensional arrays is shown possible under restrictions defined in the paper. 12 references.« less

  7. Processing-in-Memory Enabled Graphics Processors for 3D Rendering

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Xie, Chenhao; Song, Shuaiwen; Wang, Jing

    2017-02-06

    The performance of 3D rendering of Graphics Processing Unit that convents 3D vector stream into 2D frame with 3D image effects significantly impact users’ gaming experience on modern computer systems. Due to the high texture throughput in 3D rendering, main memory bandwidth becomes a critical obstacle for improving the overall rendering performance. 3D stacked memory systems such as Hybrid Memory Cube (HMC) provide opportunities to significantly overcome the memory wall by directly connecting logic controllers to DRAM dies. Based on the observation that texel fetches significantly impact off-chip memory traffic, we propose two architectural designs to enable Processing-In-Memory based GPUmore » for efficient 3D rendering.« less

  8. Accessibility versus Accuracy in Retrieving Spatial Memory: Evidence for Suboptimal Assumed Headings

    ERIC Educational Resources Information Center

    Yerramsetti, Ashok; Marchette, Steven A.; Shelton, Amy L.

    2013-01-01

    Orientation dependence in spatial memory has often been interpreted in terms of accessibility: Object locations are encoded relative to a reference orientation that affords the most accurate access to spatial memory. An open question, however, is whether people naturally use this "preferred" orientation whenever recalling the space. We…

  9. The Dynamics of Access to Groups in Working Memory

    ERIC Educational Resources Information Center

    Farrell, Simon; Lelievre, Anna

    2012-01-01

    The finding that participants leave a pause between groups when attempting serial recall of temporally grouped lists has been taken to indicate access to a hierarchical representation of the list in working memory. An alternative explanation is that the dynamics of serial recall solely reflect output (rather than memorial) processes, with the…

  10. Measurement methods to assess diastasis of the rectus abdominis muscle (DRAM): A systematic review of their measurement properties and meta-analytic reliability generalisation.

    PubMed

    van de Water, A T M; Benjamin, D R

    2016-02-01

    Systematic literature review. Diastasis of the rectus abdominis muscle (DRAM) has been linked with low back pain, abdominal and pelvic dysfunction. Measurement is used to either screen or to monitor DRAM width. Determining which methods are suitable for screening and monitoring DRAM is of clinical value. To identify the best methods to screen for DRAM presence and monitor DRAM width. AMED, Embase, Medline, PubMed and CINAHL databases were searched for measurement property studies of DRAM measurement methods. Population characteristics, measurement methods/procedures and measurement information were extracted from included studies. Quality of all studies was evaluated using 'quality rating criteria'. When possible, reliability generalisation was conducted to provide combined reliability estimations. Thirteen studies evaluated measurement properties of the 'finger width'-method, tape measure, calipers, ultrasound, CT and MRI. Ultrasound was most evaluated. Methodological quality of these studies varied widely. Pearson's correlations of r = 0.66-0.79 were found between calipers and ultrasound measurements. Calipers and ultrasound had Intraclass Correlation Coefficients (ICC) of 0.78-0.97 for test-retest, inter- and intra-rater reliability. The 'finger width'-method had weighted Kappa's of 0.73-0.77 for test-retest reliability, but moderate agreement (63%; weighted Kappa = 0.53) between raters. Comparing calipers and ultrasound, low measurement error was found (above the umbilicus), and the methods had good agreement (83%; weighted Kappa = 0.66) for discriminative purposes. The available information support ultrasound and calipers as adequate methods to assess DRAM. For other methods limited measurement information of low to moderate quality is available and further evaluation of their measurement properties is required. Copyright © 2015 Elsevier Ltd. All rights reserved.

  11. Kokkos: Enabling manycore performance portability through polymorphic memory access patterns

    DOE PAGES

    Carter Edwards, H.; Trott, Christian R.; Sunderland, Daniel

    2014-07-22

    The manycore revolution can be characterized by increasing thread counts, decreasing memory per thread, and diversity of continually evolving manycore architectures. High performance computing (HPC) applications and libraries must exploit increasingly finer levels of parallelism within their codes to sustain scalability on these devices. We found that a major obstacle to performance portability is the diverse and conflicting set of constraints on memory access patterns across devices. Contemporary portable programming models address manycore parallelism (e.g., OpenMP, OpenACC, OpenCL) but fail to address memory access patterns. The Kokkos C++ library enables applications and domain libraries to achieve performance portability on diversemore » manycore architectures by unifying abstractions for both fine-grain data parallelism and memory access patterns. In this paper we describe Kokkos’ abstractions, summarize its application programmer interface (API), present performance results for unit-test kernels and mini-applications, and outline an incremental strategy for migrating legacy C++ codes to Kokkos. Furthermore, the Kokkos library is under active research and development to incorporate capabilities from new generations of manycore architectures, and to address a growing list of applications and domain libraries.« less

  12. Paging memory from random access memory to backing storage in a parallel computer

    DOEpatents

    Archer, Charles J; Blocksome, Michael A; Inglett, Todd A; Ratterman, Joseph D; Smith, Brian E

    2013-05-21

    Paging memory from random access memory (`RAM`) to backing storage in a parallel computer that includes a plurality of compute nodes, including: executing a data processing application on a virtual machine operating system in a virtual machine on a first compute node; providing, by a second compute node, backing storage for the contents of RAM on the first compute node; and swapping, by the virtual machine operating system in the virtual machine on the first compute node, a page of memory from RAM on the first compute node to the backing storage on the second compute node.

  13. 76 FR 73676 - Certain Dynamic Random Access Memory Devices, and Products Containing Same; Receipt of Complaint...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-11-29

    ... INTERNATIONAL TRADE COMMISSION [DN 2859] Certain Dynamic Random Access Memory Devices, and.... International Trade Commission has received a complaint entitled In Re Certain Dynamic Random Access Memory... certain dynamic random access memory devices, and products containing same. The complaint names Elpida...

  14. 75 FR 16507 - In the Matter of Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-04-01

    ... Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same... synchronous dynamic random access memory controllers and products containing same by reason of infringement of... semiconductor chips having synchronous dynamic random access memory controllers and products containing same...

  15. 75 FR 14467 - In the Matter of: Certain Dynamic Random Access Memory Semiconductors and Products Containing...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-03-25

    ... Access Memory Semiconductors and Products Containing Same, Including Memory Modules; Notice of... the sale within the United States after importation of certain dynamic random access memory semiconductors and products containing same, including memory modules, by reason of infringement of certain...

  16. Enhancing Memory Access for Less Skilled Readers

    ERIC Educational Resources Information Center

    Smith, Emily R.; O'Brien, Edward J.

    2016-01-01

    Less skilled readers' comprehension often suffers because they have an impoverished representation of text in long-term memory; this, in turn, increases the difficulty of gaining access to backgrounded information necessary for maintaining coherence. The results of four experiments demonstrated that providing less skilled readers with additional…

  17. Messier: A Detailed NVM-Based DIMM Model for the SST Simulation Framework.

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Awad, Amro; Voskuilen, Gwendolyn Renae; Rodrigues, Arun F.

    2017-02-01

    DRAM technology is the main building block of main memory, however, DRAM scaling is becoming very challenging. The main issues for DRAM scaling are the increasing error rates with each new generation, the geometric and physical constraints of scaling the capacitor part of the DRAM cells, and the high power consumption caused by the continuous need for refreshing cell values. At the same time, emerging Non- Volatile Memory (NVM) technologies, such as Phase-Change Memory (PCM), are emerging as promising replacements for DRAM. NVMs, when compared to current technologies e.g., NAND-based ash, have latencies comparable to DRAM. Additionally, NVMs are non-volatile,more » which eliminates the need for refresh power and enables persistent memory applications. Finally, NVMs have promising densities and the potential for multi-level cell (MLC) storage.« less

  18. A novel barium strontium titanate/nickel/titanium nitride/silicon structure for gigabit-scale DRAM capacitors

    NASA Astrophysics Data System (ADS)

    Ritums, Dwight Lenards

    A materials system has been developed for advanced oxide high permittivity capacitors for use in Dynamic Random Access Memory (DRAM) applications. A capacitor test structure has been fabricated, demonstrating the integration of this materials system onto Si. It is a 3-D stacked electrode structure which uses the high-K dielectric material Ba1- xSrxTiO 3 (BST) and a novel Ni/TiN bottom electrode system. The structure was grown using pulsed laser deposition (PLD), photo-assisted metal-organic chemical vapor deposition (PhA-MOCVD), and electron beam deposition, and resulted in thin film capacitors with dielectric constants over 500. Other advanced oxides, principally SrVO3, were also investigated for use as electrode materials. The fabricated test structure is 3 μgm wide and 1 μm thick. RIE was used to generate the 3-D structure, and an etch gas recipe was developed to pattern the 3-D electrode structure onto the TiN. The Ni was deposited by electron beam deposition, and the BST was grown by PLD and PhA-MOCVD. Conformal coating of the electrode by the BST was achieved. The film structure was analyzed with XRD, SEM, EDS, XPS, AES, and AFM, and the electronic properties of the devices were characterized. Permittivites of up to 500 were seen in the PLD-grown films, and values up to 700 were seen in the MOCVD- deposited films. The proof of concept of a high permittivity material directly integrated onto Si has been demonstrated for this capacitor materials system. With further lithographic developments, this system can be applied toward gigabit device fabrication.

  19. Performance Evaluation of Remote Memory Access (RMA) Programming on Shared Memory Parallel Computers

    NASA Technical Reports Server (NTRS)

    Jin, Hao-Qiang; Jost, Gabriele; Biegel, Bryan A. (Technical Monitor)

    2002-01-01

    The purpose of this study is to evaluate the feasibility of remote memory access (RMA) programming on shared memory parallel computers. We discuss different RMA based implementations of selected CFD application benchmark kernels and compare them to corresponding message passing based codes. For the message-passing implementation we use MPI point-to-point and global communication routines. For the RMA based approach we consider two different libraries supporting this programming model. One is a shared memory parallelization library (SMPlib) developed at NASA Ames, the other is the MPI-2 extensions to the MPI Standard. We give timing comparisons for the different implementation strategies and discuss the performance.

  20. More than a feeling: Emotional cues impact the access and experience of autobiographical memories.

    PubMed

    Sheldon, Signy; Donahue, Julia

    2017-07-01

    Remembering is impacted by several factors of retrieval, including the emotional content of a memory cue. Here we tested how musical retrieval cues that differed on two dimensions of emotion-valence (positive and negative) and arousal (high and low)-impacted the following aspects of autobiographical memory recall: the response time to access a past personal event, the experience of remembering (ratings of memory vividness), the emotional content of a cued memory (ratings of event arousal and valence), and the type of event recalled (ratings of event energy, socialness, and uniqueness). We further explored how cue presentation affected autobiographical memory retrieval by administering cues of similar arousal and valence levels in a blocked fashion to one half of the tested participants, and randomly to the other half. We report three main findings. First, memories were accessed most quickly in response to musical cues that were highly arousing and positive in emotion. Second, we observed a relation between a cue and the elicited memory's emotional valence but not arousal; however, both the cue valence and arousal related to the nature of the recalled event. Specifically, high cue arousal led to lower memory vividness and uniqueness ratings, but cues with both high arousal and positive valence were associated with memories rated as more social and energetic. Finally, cue presentation impacted both how quickly and specifically memories were accessed and how cue valence affected the memory vividness ratings. The implications of these findings for views of how emotion directs the access to memories and the experience of remembering are discussed.

  1. Nonvolatile GaAs Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R.; Stadler, Henry L.; Wu, Jiin-Chuan

    1994-01-01

    Proposed random-access integrated-circuit electronic memory offers nonvolatile magnetic storage. Bits stored magnetically and read out with Hall-effect sensors. Advantages include short reading and writing times and high degree of immunity to both single-event upsets and permanent damage by ionizing radiation. Use of same basic material for both transistors and sensors simplifies fabrication process, with consequent benefits in increased yield and reduced cost.

  2. Effects of Dram Shop, Responsible Beverage Service Training, and State Alcohol Control Laws on Underage Drinking Driver Fatal Crash Ratios.

    PubMed

    Scherer, Michael; Fell, James C; Thomas, Sue; Voas, Robert B

    2015-01-01

    In this study, we aimed to determine whether three minimum legal drinking age 21 (MLDA-21) laws-dram shop liability, responsible beverage service (RBS) training, and state control of alcohol sales-have had an impact on underage drinking and driving fatal crashes using annual state-level data, and compared states with strong laws to those with weak laws to examine their effect on beer consumption and fatal crash ratios. Using the Fatality Analysis Reporting System, we calculated the ratio of drinking to nondrinking drivers under age 21 involved in fatal crashes as our key outcome measure. We used structural equation modeling to evaluate the three MLDA-21 laws. We controlled for covariates known to impact fatal crashes including: 17 additional MLDA-21 laws; administrative license revocation; blood alcohol concentration limits of.08 and.10 for driving; seat belt laws; sobriety checkpoint frequency; unemployment rates; and vehicle miles traveled. Outcome variables, in addition to the fatal crash ratios of drinking to nondrinking drivers under age 21 included state per capita beer consumption. Dram shop liability laws were associated with a 2.4% total effect decrease (direct effects: β =.019, p =.018). Similarly, RBS training laws were associated with a 3.6% total effect decrease (direct effect: β =.048, p =.001) in the ratio of drinking to nondrinking drivers under age 21 involved in fatal crashes. There was a significant relationship between dram shop liability law strength and per capita beer consumption, F (4, 1528) = 24.32, p <.001, partial η(2) =.016, showing states with strong dram shop liability laws (Mean (M) = 1.276) averaging significantly lower per capita beer consumption than states with weak laws (M = 1.340). Dram shop liability laws and RBS laws were both associated with significantly reduced per capita beer consumption and fatal crash ratios. In practical terms, this means that dram shop liability laws are currently associated with saving an estimated

  3. Effects of Dram Shop, Responsible Beverage Service Training, and State Alcohol Control Laws on Underage Drinking Driver Fatal Crash Ratios

    PubMed Central

    Scherer, Michael; Fell, James C.; Thomas, Sue; Voas, Robert B.

    2015-01-01

    Objectives In this study, we aimed to determine whether three minimum legal drinking age 21 (MLDA-21) laws—dram shop liability, responsible beverage service (RBS) training, and state control of alcohol sales—have had an impact on underage drinking-and-driving fatal crashes using annual state-level data, and compared states with strong laws to those with weak laws to examine their effect on beer consumption and fatal crash ratios. Methods Using the Fatality Analysis Reporting System, we calculated the ratio of drinking to nondrinking drivers under age 21 involved in fatal crashes as our key outcome measure. We used structural equation modeling to evaluate the three MLDA-21 laws. We controlled for covariates known to impact fatal crashes including: 17 additional MLDA-21 laws; administrative license revocation; blood alcohol concentration limits of .08 and .10 for driving; seat belt laws; sobriety checkpoint frequency; unemployment rates; and vehicle miles traveled. Outcome variables, in addition to the fatal crash ratios of drinking to nondrinking drivers under age 21 included state per capita beer consumption. Results Dram shop liability laws were associated with a 2.4% total effect decrease (direct effects: β = .019, p = .018). Similarly, RBS training laws were associated with a 3.6% total effect decrease (direct effects: β = .048, p = .001) in the ratio of drinking to nondrinking drivers under age 21 involved in fatal crashes. There was a significant relationship between dram shop liability law strength and per capita beer consumption, F (4, 1528) = 24.32, p < .001, partial η2 = .016, showing states with strong dram shop liability laws (Mean (M) = 1.276) averaging significantly lower per capita beer consumption than states with weak laws (M = 1.340). Conclusions Dram shop liability laws and RBS laws were both associated with significantly reduced per capita beer consumption and fatal crash ratios. In practical terms, this means that dram shop liability laws

  4. Data Movement Dominates: Final Report

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Jacob, Bruce L.

    Over the past three years in this project, what we have observed is that the primary reason for data movement in large-scale systems is that the per-node capacity is not large enough—i.e., one of the solutions to the data-movement problem (certainly not the only solution that is required, but a significant one nonetheless) is to increase per-node capacity so that inter-node traffic is reduced. This unfortunately is not as simple as it sounds. Today’s main memory systems for datacenters, enterprise computing systems, and supercomputers, fail to provide high per-socket capacity [Dirik & Jacob 2009; Cooper-Balis et al. 2012], except atmore » extremely high price points (factors of 10–100x the cost/bit of consumer main-memory systems) [Stokes 2008]. The reason is that our choice of technology for today’s main memory systems—i.e., DRAM, which we have used as a main-memory technology since the 1970s [Jacob et al. 2007]—can no longer keep up with our needs for density and price per bit. Main memory systems have always been built from the cheapest, densest, lowest-power memory technology available, and DRAM is no longer the cheapest, the densest, nor the lowest-power storage technology out there. It is now time for DRAM to go the way that SRAM went: move out of the way for a cheaper, slower, denser storage technology, and become a cache instead. This inflection point has happened before, in the context of SRAM yielding to DRAM. There was once a time that SRAM was the storage technology of choice for all main memories [Tomasulo 1967; Thornton 1970; Kidder 1981]. However, once DRAM hit volume production in the 1970s and 80s, it supplanted SRAM as a main memory technology because it was cheaper, and it was denser. It also happened to be lower power, but that was not the primary consideration of the day. At the time, it was recognized that DRAM was much slower than SRAM, but it was only at the supercomputer level (For instance the Cray X-MP in the 1980s and its

  5. Accessibility limits recall from visual working memory.

    PubMed

    Rajsic, Jason; Swan, Garrett; Wilson, Daryl E; Pratt, Jay

    2017-09-01

    In this article, we demonstrate limitations of accessibility of information in visual working memory (VWM). Recently, cued-recall has been used to estimate the fidelity of information in VWM, where the feature of a cued object is reproduced from memory (Bays, Catalao, & Husain, 2009; Wilken & Ma, 2004; Zhang & Luck, 2008). Response error in these tasks has been largely studied with respect to failures of encoding and maintenance; however, the retrieval operations used in these tasks remain poorly understood. By varying the number and type of object features provided as a cue in a visual delayed-estimation paradigm, we directly assess the nature of retrieval errors in delayed estimation from VWM. Our results demonstrate that providing additional object features in a single cue reliably improves recall, largely by reducing swap, or misbinding, responses. In addition, performance simulations using the binding pool model (Swan & Wyble, 2014) were able to mimic this pattern of performance across a large span of parameter combinations, demonstrating that the binding pool provides a possible mechanism underlying this pattern of results that is not merely a symptom of one particular parametrization. We conclude that accessing visual working memory is a noisy process, and can lead to errors over and above those of encoding and maintenance limitations. (PsycINFO Database Record (c) 2017 APA, all rights reserved).

  6. Spin-based single-photon transistor, dynamic random access memory, diodes, and routers in semiconductors

    NASA Astrophysics Data System (ADS)

    Hu, C. Y.

    2016-12-01

    The realization of quantum computers and quantum Internet requires not only quantum gates and quantum memories, but also transistors at single-photon levels to control the flow of information encoded on single photons. Single-photon transistor (SPT) is an optical transistor in the quantum limit, which uses a single photon to open or block a photonic channel. In sharp contrast to all previous SPT proposals which are based on single-photon nonlinearities, here I present a design for a high-gain and high-speed (up to THz) SPT based on a linear optical effect: giant circular birefringence induced by a single spin in a double-sided optical microcavity. A gate photon sets the spin state via projective measurement and controls the light propagation in the optical channel. This spin-cavity transistor can be directly configured as diodes, routers, DRAM units, switches, modulators, etc. Due to the duality as quantum gate and transistor, the spin-cavity unit provides a solid-state platform ideal for future Internet: a mixture of all-optical Internet with quantum Internet.

  7. Vortex-Core Reversal Dynamics: Towards Vortex Random Access Memory

    NASA Astrophysics Data System (ADS)

    Kim, Sang-Koog

    2011-03-01

    An energy-efficient, ultrahigh-density, ultrafast, and nonvolatile solid-state universal memory is a long-held dream in the field of information-storage technology. The magnetic random access memory (MRAM) along with a spin-transfer-torque switching mechanism is a strong candidate-means of realizing that dream, given its nonvolatility, infinite endurance, and fast random access. Magnetic vortices in patterned soft magnetic dots promise ground-breaking applications in information-storage devices, owing to the very stable twofold ground states of either their upward or downward core magnetization orientation and plausible core switching by in-plane alternating magnetic fields or spin-polarized currents. However, two technologically most important but very challenging issues --- low-power recording and reliable selection of each memory cell with already existing cross-point architectures --- have not yet been resolved for the basic operations in information storage, that is, writing (recording) and readout. Here, we experimentally demonstrate a magnetic vortex random access memory (VRAM) in the basic cross-point architecture. This unique VRAM offers reliable cell selection and low-power-consumption control of switching of out-of-plane core magnetizations using specially designed rotating magnetic fields generated by two orthogonal and unipolar Gaussian-pulse currents along with optimized pulse width and time delay. Our achievement of a new device based on a new material, that is, a medium composed of patterned vortex-state disks, together with the new physics on ultrafast vortex-core switching dynamics, can stimulate further fruitful research on MRAMs that are based on vortex-state dot arrays.

  8. 78 FR 35645 - Certain Static Random Access Memories and Products Containing Same; Commission Determination...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-06-13

    ... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-792] Certain Static Random Access Memories and Products Containing Same; Commission Determination Affirming a Final Initial Determination..., and the sale within the United States after importation of certain static random access memories and...

  9. Built-in self-repair of VLSI memories employing neural nets

    NASA Astrophysics Data System (ADS)

    Mazumder, Pinaki

    1998-10-01

    The decades of the Eighties and the Nineties have witnessed the spectacular growth of VLSI technology, when the chip size has increased from a few hundred devices to a staggering multi-millon transistors. This trend is expected to continue as the CMOS feature size progresses towards the nanometric dimension of 100 nm and less. SIA roadmap projects that, where as the DRAM chips will integrate over 20 billion devices in the next millennium, the future microprocessors may incorporate over 100 million transistors on a single chip. As the VLSI chip size increase, the limited accessibility of circuit components poses great difficulty for external diagnosis and replacement in the presence of faulty components. For this reason, extensive work has been done in built-in self-test techniques, but little research is known concerning built-in self-repair. Moreover, the extra hardware introduced by conventional fault-tolerance techniques is also likely to become faulty, therefore causing the circuit to be useless. This research demonstrates the feasibility of implementing electronic neural networks as intelligent hardware for memory array repair. Most importantly, we show that the neural network control possesses a robust and degradable computing capability under various fault conditions. Overall, a yield analysis performed on 64K DRAM's shows that the yield can be improved from as low as 20 percent to near 99 percent due to the self-repair design, with overhead no more than 7 percent.

  10. 75 FR 44283 - In the Matter of Certain Dynamic Random Access Memory Semiconductors and Products Containing Same...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-07-28

    ... Random Access Memory Semiconductors and Products Containing Same, Including Memory Modules; Notice of a... importation of certain dynamic random access memory semiconductors and products containing same, including memory modules, by reason of infringement of certain claims of U.S. Patent Nos. 5,480,051; 5,422,309; 5...

  11. Making working memory work: The effects of extended practice on focus capacity and the processes of updating, forward access, and random access

    PubMed Central

    Price, John M.; Colflesh, Gregory J. H.; Cerella, John; Verhaeghen, Paul

    2014-01-01

    We investigated the effects of 10 hours of practice on variations of the N-Back task to investigate the processes underlying possible expansion of the focus of attention within working memory. Using subtractive logic, we showed that random access (i.e., Sternberg-like search) yielded a modest effect (a 50% increase in speed) whereas the processes of forward access (i.e., retrieval in order, as in a standard N-Back task) and updating (i.e., changing the contents of working memory) were executed about 5 times faster after extended practice. We additionally found that extended practice increased working memory capacity as measured by the size of the focus of attention for the forward-access task, but not for variations where probing was in random order. This suggests that working memory capacity may depend on the type of search process engaged, and that certain working-memory-related cognitive processes are more amenable to practice than others. PMID:24486803

  12. Making working memory work: the effects of extended practice on focus capacity and the processes of updating, forward access, and random access.

    PubMed

    Price, John M; Colflesh, Gregory J H; Cerella, John; Verhaeghen, Paul

    2014-05-01

    We investigated the effects of 10h of practice on variations of the N-Back task to investigate the processes underlying possible expansion of the focus of attention within working memory. Using subtractive logic, we showed that random access (i.e., Sternberg-like search) yielded a modest effect (a 50% increase in speed) whereas the processes of forward access (i.e., retrieval in order, as in a standard N-Back task) and updating (i.e., changing the contents of working memory) were executed about 5 times faster after extended practice. We additionally found that extended practice increased working memory capacity as measured by the size of the focus of attention for the forward-access task, but not for variations where probing was in random order. This suggests that working memory capacity may depend on the type of search process engaged, and that certain working-memory-related cognitive processes are more amenable to practice than others. Copyright © 2014 Elsevier B.V. All rights reserved.

  13. Aspects of GPU perfomance in algorithms with random memory access

    NASA Astrophysics Data System (ADS)

    Kashkovsky, Alexander V.; Shershnev, Anton A.; Vashchenkov, Pavel V.

    2017-10-01

    The numerical code for solving the Boltzmann equation on the hybrid computational cluster using the Direct Simulation Monte Carlo (DSMC) method showed that on Tesla K40 accelerators computational performance drops dramatically with increase of percentage of occupied GPU memory. Testing revealed that memory access time increases tens of times after certain critical percentage of memory is occupied. Moreover, it seems to be the common problem of all NVidia's GPUs arising from its architecture. Few modifications of the numerical algorithm were suggested to overcome this problem. One of them, based on the splitting the memory into "virtual" blocks, resulted in 2.5 times speed up.

  14. BCH codes for large IC random-access memory systems

    NASA Technical Reports Server (NTRS)

    Lin, S.; Costello, D. J., Jr.

    1983-01-01

    In this report some shortened BCH codes for possible applications to large IC random-access memory systems are presented. These codes are given by their parity-check matrices. Encoding and decoding of these codes are discussed.

  15. 78 FR 25767 - Certain Static Random Access Memories and Products Containing Same; Commission Determination To...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-05-02

    ... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-792] Certain Static Random Access Memories and Products Containing Same; Commission Determination To Review in Part a Final Initial... States after importation of certain static random access memories and products containing the same by...

  16. BLACKCOMB2: Hardware-software co-design for non-volatile memory in exascale systems

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Mudge, Trevor

    This work was part of a larger project, Blackcomb2, centered at Oak Ridge National Labs (Jeff Vetter PI) to investigate the opportunities for replacing or supplementing DRAM main memory with nonvolatile memory (NVmemory) in Exascale memory systems. The goal was to reduce the energy consumed by in future supercomputer memory systems and to improve their resiliency. Building on the accomplishments of the original Blackcomb Project, funded in 2010, the goal for Blackcomb2 was to identify, evaluate, and optimize the most promising emerging memory technologies, architecture hardware and software technologies, which are essential to provide the necessary memory capacity, performance, resilience,more » and energy efficiency in Exascale systems. Capacity and energy are the key drivers.« less

  17. Development of Curie point switching for thin film, random access, memory device

    NASA Technical Reports Server (NTRS)

    Lewicki, G. W.; Tchernev, D. I.

    1967-01-01

    Managanese bismuthide films are used in the development of a random access memory device of high packing density and nondestructive readout capability. Memory entry is by Curie point switching using a laser beam. Readout is accomplished by microoptical or micromagnetic scanning.

  18. Complex dynamics of semantic memory access in reading

    PubMed Central

    Baggio, Giosué; Fonseca, André

    2012-01-01

    Understanding a word in context relies on a cascade of perceptual and conceptual processes, starting with modality-specific input decoding, and leading to the unification of the word's meaning into a discourse model. One critical cognitive event, turning a sensory stimulus into a meaningful linguistic sign, is the access of a semantic representation from memory. Little is known about the changes that activating a word's meaning brings about in cortical dynamics. We recorded the electroencephalogram (EEG) while participants read sentences that could contain a contextually unexpected word, such as ‘cold’ in ‘In July it is very cold outside’. We reconstructed trajectories in phase space from single-trial EEG time series, and we applied three nonlinear measures of predictability and complexity to each side of the semantic access boundary, estimated as the onset time of the N400 effect evoked by critical words. Relative to controls, unexpected words were associated with larger prediction errors preceding the onset of the N400. Accessing the meaning of such words produced a phase transition to lower entropy states, in which cortical processing becomes more predictable and more regular. Our study sheds new light on the dynamics of information flow through interfaces between sensory and memory systems during language processing. PMID:21715401

  19. Complex dynamics of semantic memory access in reading.

    PubMed

    Baggio, Giosué; Fonseca, André

    2012-02-07

    Understanding a word in context relies on a cascade of perceptual and conceptual processes, starting with modality-specific input decoding, and leading to the unification of the word's meaning into a discourse model. One critical cognitive event, turning a sensory stimulus into a meaningful linguistic sign, is the access of a semantic representation from memory. Little is known about the changes that activating a word's meaning brings about in cortical dynamics. We recorded the electroencephalogram (EEG) while participants read sentences that could contain a contextually unexpected word, such as 'cold' in 'In July it is very cold outside'. We reconstructed trajectories in phase space from single-trial EEG time series, and we applied three nonlinear measures of predictability and complexity to each side of the semantic access boundary, estimated as the onset time of the N400 effect evoked by critical words. Relative to controls, unexpected words were associated with larger prediction errors preceding the onset of the N400. Accessing the meaning of such words produced a phase transition to lower entropy states, in which cortical processing becomes more predictable and more regular. Our study sheds new light on the dynamics of information flow through interfaces between sensory and memory systems during language processing.

  20. Electrical memory characteristics of a nondoped pi-conjugated polymer bearing carbazole moieties.

    PubMed

    Park, Samdae; Lee, Taek Joon; Kim, Dong Min; Kim, Jin Chul; Kim, Kyungtae; Kwon, Wonsang; Ko, Yong-Gi; Choi, Heungyeal; Chang, Taihyun; Ree, Moonhor

    2010-08-19

    Poly[bis(9H-carbazole-9-ethyl)dipropargylmalonate] (PCzDPM) is a novel pi-conjugated polymer bearing carbazole moieties that has been synthesized by polymerization of bis(9H-carbazole-9-ethyl)dipropargylmalonate with the aid of molybdenum chloride solution as the catalyst. This polymer is thermally stable up to 255 degrees C under a nitrogen atmosphere and 230 degrees C in air ambient; its glass-transition temperature is 147 or 128 degrees C, depending on the polymer chain conformation (helical or planar structure). The charge-transport characteristics of PCzDPM in nanometer-scaled thin films were studied as a function of temperature and film thickness. PCzDPM films with a thickness of 15-30 nm were found to exhibit very stable dynamic random access memory (DRAM) characteristics without polarity. Furthermore, the polymer films retain DRAM characteristics up to 180 degrees C. The ON-state current is dominated by Ohmic conduction, and the OFF-state current appears to undergo a transition from Ohmic to space-charge-limited conduction with a shallow-trap distribution. The ON/OFF switching of the devices is mainly governed by filament formation. The filament formation mechanism for the switching process is supported by the metallic properties of the PCzDPM film, which result in the temperature dependence of the ON-state current. In addition, the structure of this pi-conjugated polymer was found to vary with its thermal history; this change in structure can affect filament formation in the polymer film.

  1. Adult Age Differences in Accessing and Retrieving Information from Long-Term Memory.

    ERIC Educational Resources Information Center

    Petros, Thomas V.; And Others

    1983-01-01

    Investigated adult age differences in accessing and retrieving information from long-term memory. Results showed that older adults (N=26) were slower than younger adults (N=35) at feature extraction, lexical access, and accessing category information. The age deficit was proportionally greater when retrieval of category information was required.…

  2. Automatic alternative phase-shift mask CAD layout tool for gate shrinkage of embedded DRAM in logic below 0.18 μm

    NASA Astrophysics Data System (ADS)

    Ohnuma, Hidetoshi; Kawahira, Hiroichi

    1998-09-01

    An automatic alternative phase shift mask (PSM) pattern layout tool has been newly developed. This tool is dedicated for embedded DRAM in logic device to shrink gate line width with improving line width controllability in lithography process with a design rule below 0.18 micrometers by the KrF excimer laser exposure. The tool can crete Levenson type PSM used being coupled with a binary mask adopting a double exposure method for positive photo resist. By using graphs, this tool automatically creates alternative PSM patterns. Moreover, it does not give any phase conflicts. By adopting it to actual embedded DRAM in logic cells, we have provided 0.16 micrometers gate resist patterns at both random logic and DRAM areas. The patterns were fabricated using two masks with the double exposure method. Gate line width has been well controlled under a practical exposure-focus window.

  3. Artificial intelligence applications of fast optical memory access

    NASA Astrophysics Data System (ADS)

    Henshaw, P. D.; Todtenkopf, A. B.

    The operating principles and performance of rapid laser beam-steering (LBS) techniques are reviewed and illustrated with diagrams; their applicability to fast optical-memory (disk) access is evaluated; and the implications of fast access for the design of expert systems are discussed. LBS methods examined include analog deflection (source motion, wavefront tilt, and phased arrays), digital deflection (polarization modulation, reflectivity modulation, interferometric switching, and waveguide deflection), and photorefractive LBS. The disk-access problem is considered, and typical LBS requirements are listed as 38,000 beam positions, rotational latency 25 ms, one-sector rotation time 1.5 ms, and intersector space 87 microsec. The value of rapid access for increasing the power of expert systems (by permitting better organization of blocks of information) is illustrated by summarizing the learning process of the MVP-FORTH system (Park, 1983).

  4. Improving memory after interruption: exploiting soft constraints and manipulating information access cost.

    PubMed

    Morgan, Phillip L; Patrick, John; Waldron, Samuel M; King, Sophia L; Patrick, Tanya

    2009-12-01

    Forgetting what one was doing prior to interruption is an everyday problem. The recent soft constraints hypothesis (Gray, Sims, Fu, & Schoelles, 2006) emphasizes the strategic adaptation of information processing strategy to the task environment. It predicts that increasing information access cost (IAC: the time, and physical and mental effort involved in accessing information) encourages a more memory-intensive strategy. Like interruptions, access costs are also intrinsic to most work environments, such as when opening documents and e-mails. Three experiments investigated whether increasing IAC during a simple copying task can be an effective method for reducing forgetting following interruption. IAC was designated Low (all information permanently visible), Medium (a mouse movement to uncover target information), or High (an additional few seconds to uncover such information). Experiment 1 found that recall improved across all three levels of IAC. Subsequent experiments found that High IAC facilitated resumption after interruption, particularly when interruption occurred on half of all trials (Experiment 2), and improved prospective memory following two different interrupting tasks, even when one involved the disruptive effect of using the same type of resource as the primary task (Experiment 3). The improvement of memory after interruption with increased IAC supports the prediction of the soft constraints hypothesis. The main disadvantage of a high access cost was a reduction in speed of task completion. The practicality of manipulating IAC as a design method for inducing a memory-intensive strategy to protect against forgetting is discussed. Copyright 2009 APA

  5. Integrated, nonvolatile, high-speed analog random access memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor)

    1994-01-01

    This invention provides an integrated, non-volatile, high-speed random access memory. A magnetically switchable ferromagnetic or ferrimagnetic layer is sandwiched between an electrical conductor which provides the ability to magnetize the magnetically switchable layer and a magneto resistive or Hall effect material which allows sensing the magnetic field which emanates from the magnetization of the magnetically switchable layer. By using this integrated three-layer form, the writing process, which is controlled by the conductor, is separated from the storage medium in the magnetic layer and from the readback process which is controlled by the magnetoresistive layer. A circuit for implementing the memory in CMOS or the like is disclosed.

  6. MRAM Technology Status

    NASA Technical Reports Server (NTRS)

    Heidecker, Jason

    2013-01-01

    Magnetoresistive Random Access Memory (MRAM) is much different from conventional types of memory like SRAM, DRAM, and Flash, where electric charge is used to store information. Instead of exploiting the charge of an electron, MRAM uses its spin to store data. This new type of electronics is known as "spintronics." The primary focus of this report is the current generation of MRAM technology, and its reliability, vendors, and space-readiness.

  7. Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Gala, Alan; Ohmacht, Martin

    A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memorymore » access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.« less

  8. Electrical and dielectric properties of (barium, strontium) titanium trioxide thin film capacitors for ultra-high density dynamic random access memories

    NASA Astrophysics Data System (ADS)

    Basceri, Cem

    The electrical and dielectric properties of fiber-textured, MOCVD (Basb{0.7}Srsb{0.3})TiOsb3 (BST) thin film capacitors appropriate for ultra-large scale integration (ULSI) dynamic random access memory (DRAM) applications have been analyzed. Dielectric relaxation, leakage, resistance degradation, and dielectric response phenomena, within a comprehensive matrix of external and material parameters, have been investigated. The phenomenology of the dielectric response of our BST films has been shown to be well-described by Curie-von Schweidler behavior, although the microscopic origin of this behavior has not been presently agreed upon. The time-dependent polarization behavior has been linked to the dispersion in permittivity with respect to frequency. The leakage current through our BST films has been found to be primarily limited by interfacial Schottky barriers whose properties depend on the electrode material, interface microstructure, and deposition conditions. Its temperature and voltage dependence have been interpreted via a thermionic emission model. Analysis in terms of Schottky-barrier limited current flow gave acceptable values for the cathode barrier height. The results have indicated that our BST films, appropriate for DRAM applications, do not possess depletion layers at the film-electrode interfaces. Instead, they must be considered as depleted of charge carriers across their entire thickness. Resistance degradation has been found to be thermally activated and voltage/field dependent. The results have indicated that there is a film thickness effect, which manifests itself as a decrease in the activation energy with respect to temperature for thicker films. A significant stoichiometry effect on the measured resistance degradation lifetimes has been observed. The analyses of the leakage and capacitance-voltage behaviors for the degraded samples have indicated that a demixing of oxygen vacancies occurs during resistance degradation, which causes the

  9. Effects of dram shop liability and enhanced overservice law enforcement initiatives on excessive alcohol consumption and related harms: Two community guide systematic reviews.

    PubMed

    Rammohan, Veda; Hahn, Robert A; Elder, Randy; Brewer, Robert; Fielding, Jonathan; Naimi, Timothy S; Toomey, Traci L; Chattopadhyay, Sajal K; Zometa, Carlos

    2011-09-01

    Dram shop liability holds the owner or server(s) at a bar, restaurant, or other location where a patron, adult or underage, consumed his or her last alcoholic beverage responsible for harms subsequently inflicted by the patron on others. Liability in a state can be established by case law or statute. Overservice laws prohibit the sale of alcoholic beverages to intoxicated patrons drinking in on-premises retail alcohol outlets (i.e., premises where the alcohol is consumed where purchased); enhanced enforcement of these laws is intended to ensure compliance by premises personnel. Both of these interventions are ultimately designed to promote responsible beverage service by reducing sales to intoxicated patrons, underage youth, or both. This review assesses the effectiveness of dram shop liability and the enhanced enforcement of overservice laws for preventing excessive alcohol consumption and related harms. Studies assessing alcohol-related harms in states adopting dram shop laws were evaluated, as were studies assessing alcohol-related harms in regions with enhanced overservice enforcement. Methods previously developed for systematic reviews for the Guide to Community Preventive Services were used. Eleven studies assessed the association of state dram shop liability with various outcomes, including all-cause motor vehicle crash deaths, alcohol-related motor vehicle crash deaths (the most common outcome assessed in the studies reviewed), alcohol consumption, and other alcohol-related harms. There was a median reduction of 6.4% (range of values 3.7% to 11.3% reduction) in alcohol-related motor vehicle fatalities associated with the presence of dram shop liability in jurisdictions where premises are licensed. Other alcohol-related outcomes also showed a reduction. Only two studies assessed the effects of enhanced enforcement initiatives on alcohol-related outcomes; findings were inconsistent, some indicating benefit and others none. According to Community Guide rules

  10. Boosting the FM-Index on the GPU: Effective Techniques to Mitigate Random Memory Access.

    PubMed

    Chacón, Alejandro; Marco-Sola, Santiago; Espinosa, Antonio; Ribeca, Paolo; Moure, Juan Carlos

    2015-01-01

    The recent advent of high-throughput sequencing machines producing big amounts of short reads has boosted the interest in efficient string searching techniques. As of today, many mainstream sequence alignment software tools rely on a special data structure, called the FM-index, which allows for fast exact searches in large genomic references. However, such searches translate into a pseudo-random memory access pattern, thus making memory access the limiting factor of all computation-efficient implementations, both on CPUs and GPUs. Here, we show that several strategies can be put in place to remove the memory bottleneck on the GPU: more compact indexes can be implemented by having more threads work cooperatively on larger memory blocks, and a k-step FM-index can be used to further reduce the number of memory accesses. The combination of those and other optimisations yields an implementation that is able to process about two Gbases of queries per second on our test platform, being about 8 × faster than a comparable multi-core CPU version, and about 3 × to 5 × faster than the FM-index implementation on the GPU provided by the recently announced Nvidia NVBIO bioinformatics library.

  11. Accessing Information in Working Memory: Can the Focus of Attention Grasp Two Elements at the Same Time?

    ERIC Educational Resources Information Center

    Oberauer, Klaus; Bialkova, Svetlana

    2009-01-01

    Processing information in working memory requires selective access to a subset of working-memory contents by a focus of attention. Complex cognition often requires joint access to 2 items in working memory. How does the focus select 2 items? Two experiments with an arithmetic task and 1 with a spatial task investigate time demands for successive…

  12. 76 FR 2336 - Dynamic Random Access Memory Semiconductors From the Republic of Korea: Final Results of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-01-13

    ... DEPARTMENT OF COMMERCE International Trade Administration [C-580-851] Dynamic Random Access Memory... administrative review of the countervailing duty order on dynamic random access memory semiconductors from the... following events have occurred since the publication of the preliminary results of this review. See Dynamic...

  13. The introduction of dram shop legislation in the United States and the advent of server training.

    PubMed

    Saltz, R F

    1993-01-01

    This paper discusses the relationship of research to policy in the matter of dram shop liability and server training in the USA. The discussion is made difficult by the apparent lack of any such relationship. While research in the area has only just been published, dram shop liability in the USA actually dates to the nineteenth century, with its current form shaped by the repeal of prohibition in 1933. Because liability law and liability insurance vary from state to state, current movements for reform and server training arise somewhat spontaneously in different localities and with different emphases. Research constitutes only a minor influence among several others more salient to the political process of policy formation. The advent of mandatory server training in the state of Oregon is used to illustrate the somewhat capricious nature of progress in responsible beverage service.

  14. A novel ternary content addressable memory design based on resistive random access memory with high intensity and low search energy

    NASA Astrophysics Data System (ADS)

    Han, Runze; Shen, Wensheng; Huang, Peng; Zhou, Zheng; Liu, Lifeng; Liu, Xiaoyan; Kang, Jinfeng

    2018-04-01

    A novel ternary content addressable memory (TCAM) design based on resistive random access memory (RRAM) is presented. Each TCAM cell consists of two parallel RRAM to both store and search for ternary data. The cell size of the proposed design is 8F2, enable a ∼60× cell area reduction compared with the conventional static random access memory (SRAM) based implementation. Simulation results also show that the search delay and energy consumption of the proposed design at the 64-bit word search are 2 ps and 0.18 fJ/bit/search respectively at 22 nm technology node, where significant improvements are achieved compared to previous works. The desired characteristics of RRAM for implementation of the high performance TCAM search chip are also discussed.

  15. What versus where: Investigating how autobiographical memory retrieval differs when accessed with thematic versus spatial information.

    PubMed

    Sheldon, Signy; Chu, Sonja

    2017-09-01

    Autobiographical memory research has investigated how cueing distinct aspects of a past event can trigger different recollective experiences. This research has stimulated theories about how autobiographical knowledge is accessed and organized. Here, we test the idea that thematic information organizes multiple autobiographical events whereas spatial information organizes individual past episodes by investigating how retrieval guided by these two forms of information differs. We used a novel autobiographical fluency task in which participants accessed multiple memory exemplars to event theme and spatial (location) cues followed by a narrative description task in which they described the memories generated to these cues. Participants recalled significantly more memory exemplars to event theme than to spatial cues; however, spatial cues prompted faster access to past memories. Results from the narrative description task revealed that memories retrieved via event theme cues compared to spatial cues had a higher number of overall details, but those recalled to the spatial cues were recollected with a greater concentration on episodic details than those retrieved via event theme cues. These results provide evidence that thematic information organizes and integrates multiple memories whereas spatial information prompts the retrieval of specific episodic content from a past event.

  16. Taxing Working Memory during Retrieval of Emotional Memories Does Not Reduce Memory Accessibility When Cued with Reminders

    PubMed Central

    van Schie, Kevin; Engelhard, Iris M.; van den Hout, Marcel A.

    2015-01-01

    Earlier studies have shown that when individuals recall an emotional memory while simultaneously doing a demanding dual-task [e.g., playing Tetris, mental arithmetic, making eye movements (EM)], this reduces self-reported vividness and emotionality of the memory. These effects have been found up to 1 week later, but have largely been confined to self-report ratings. This study examined whether this dual-tasking intervention reduces memory performance (i.e., accessibility of emotional memories). Undergraduates (N = 60) studied word-image pairs and rated the retrieved image on vividness and emotionality when cued with the word. Then they viewed the cues and recalled the images with or without making EM. Finally, they re-rated the images on vividness and emotionality. Additionally, fragments from images from all conditions were presented and participants identified which fragment was paired earlier with which cue. Findings showed no effect of the dual-task manipulation on self-reported ratings and latency responses. Several possible explanations for the lack of effects are discussed, but the cued recall procedure in our experiment seems to explain the absence of effects best. The study demonstrates boundaries to the effects of the “dual-tasking” procedure. PMID:25729370

  17. Large Capacity of Conscious Access for Incidental Memories in Natural Scenes.

    PubMed

    Kaunitz, Lisandro N; Rowe, Elise G; Tsuchiya, Naotsugu

    2016-09-01

    When searching a crowd, people can detect a target face only by direct fixation and attention. Once the target is found, it is consciously experienced and remembered, but what is the perceptual fate of the fixated nontarget faces? Whereas introspection suggests that one may remember nontargets, previous studies have proposed that almost no memory should be retained. Using a gaze-contingent paradigm, we asked subjects to visually search for a target face within a crowded natural scene and then tested their memory for nontarget faces, as well as their confidence in those memories. Subjects remembered up to seven fixated, nontarget faces with more than 70% accuracy. Memory accuracy was correlated with trial-by-trial confidence ratings, which implies that the memory was consciously maintained and accessed. When the search scene was inverted, no more than three nontarget faces were remembered. These findings imply that incidental memory for faces, such as those recalled by eyewitnesses, is more reliable than is usually assumed. © The Author(s) 2016.

  18. Attacking the One-Out-Of-m Multicore Problem by Combining Hardware Management with Mixed-Criticality Provisioning

    DTIC Science & Technology

    2015-05-01

    LLC and DRAM banks. For each µB task and isolation configuration, we ran experiments with all 256 possible LLC area sizes (given by 1 to 16 ways and 1...isolation on multicoore platforms. In RTAS ’14. [29] H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha . Memory access control in multiprocessor

  19. 75 FR 20564 - Dynamic Random Access Memory Semiconductors from the Republic of Korea: Extension of Time Limit...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-04-20

    ... DEPARTMENT OF COMMERCE International Trade Administration [C-580-851] Dynamic Random Access Memory Semiconductors from the Republic of Korea: Extension of Time Limit for Preliminary Results of Countervailing Duty... access memory semiconductors from the Republic of Korea, covering the period January 1, 2008 through...

  20. Children's Access to Public Library Services: Prince George's County Memorial Public Library, Maryland, 1980.

    ERIC Educational Resources Information Center

    Gerhardt, Lillian N.

    1981-01-01

    Evaluates the Prince George's County Memorial Public Library's approach to providing access to its services for children, and examines policies, regulations, practices, and conditions that affect such access. Six references are cited. (FM)

  1. Memory access in shared virtual memory

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Berrendorf, R.

    1992-01-01

    Shared virtual memory (SVM) is a virtual memory layer with a single address space on top of a distributed real memory on parallel computers. We examine the behavior and performance of SVM running a parallel program with medium-grained, loop-level parallelism on top of it. A simulator for the underlying parallel architecture can be used to examine the behavior of SVM more deeply. The influence of several parameters, such as the number of processors, page size, cold or warm start, and restricted page replication, is studied.

  2. Memory access in shared virtual memory

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Berrendorf, R.

    1992-09-01

    Shared virtual memory (SVM) is a virtual memory layer with a single address space on top of a distributed real memory on parallel computers. We examine the behavior and performance of SVM running a parallel program with medium-grained, loop-level parallelism on top of it. A simulator for the underlying parallel architecture can be used to examine the behavior of SVM more deeply. The influence of several parameters, such as the number of processors, page size, cold or warm start, and restricted page replication, is studied.

  3. Makalu: fast recoverable allocation of non-volatile memory

    DOE PAGES

    Bhandari, Kumud; Chakrabarti, Dhruva R.; Boehm, Hans-J.

    2016-10-19

    Byte addressable non-volatile memory (NVRAM) is likely to supplement, and perhaps eventually replace, DRAM. Applications can then persist data structures directly in memory instead of serializing them and storing them onto a durable block device. However, failures during execution can leave data structures in NVRAM unreachable or corrupt. In this paper, we present Makalu, a system that addresses non-volatile memory management. Makalu offers an integrated allocator and recovery-time garbage collector that maintains internal consistency, avoids NVRAM memory leaks, and is efficient, all in the face of failures. We show that a careful allocator design can support a less restrictive andmore » a much more familiar programming model than existing persistent memory allocators. Our allocator significantly reduces the per allocation persistence overhead by lazily persisting non-essential metadata and by employing a post-failure recovery-time garbage collector. Experimental results show that the resulting online speed and scalability of our allocator are comparable to well-known transient allocators, and significantly better than state-of-the-art persistent allocators.« less

  4. Makalu: fast recoverable allocation of non-volatile memory

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Bhandari, Kumud; Chakrabarti, Dhruva R.; Boehm, Hans-J.

    Byte addressable non-volatile memory (NVRAM) is likely to supplement, and perhaps eventually replace, DRAM. Applications can then persist data structures directly in memory instead of serializing them and storing them onto a durable block device. However, failures during execution can leave data structures in NVRAM unreachable or corrupt. In this paper, we present Makalu, a system that addresses non-volatile memory management. Makalu offers an integrated allocator and recovery-time garbage collector that maintains internal consistency, avoids NVRAM memory leaks, and is efficient, all in the face of failures. We show that a careful allocator design can support a less restrictive andmore » a much more familiar programming model than existing persistent memory allocators. Our allocator significantly reduces the per allocation persistence overhead by lazily persisting non-essential metadata and by employing a post-failure recovery-time garbage collector. Experimental results show that the resulting online speed and scalability of our allocator are comparable to well-known transient allocators, and significantly better than state-of-the-art persistent allocators.« less

  5. Remote direct memory access over datagrams

    DOEpatents

    Grant, Ryan Eric; Rashti, Mohammad Javad; Balaji, Pavan; Afsahi, Ahmad

    2014-12-02

    A communication stack for providing remote direct memory access (RDMA) over a datagram network is disclosed. The communication stack has a user level interface configured to accept datagram related input and communicate with an RDMA enabled network interface card (NIC) via an NIC driver. The communication stack also has an RDMA protocol layer configured to supply one or more data transfer primitives for the datagram related input of the user level. The communication stack further has a direct data placement (DDP) layer configured to transfer the datagram related input from a user storage to a transport layer based on the one or more data transfer primitives by way of a lower layer protocol (LLP) over the datagram network.

  6. Apparatus and Method for Compensating for Process, Voltage, and Temperature Variation of the Time Delay of a Digital Delay Line

    NASA Technical Reports Server (NTRS)

    Seefeldt, James (Inventor); Feng, Xiaoxin (Inventor); Roper, Weston (Inventor)

    2013-01-01

    A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

  7. Power reduction by power gating in differential pair type spin-transfer-torque magnetic random access memories for low-power nonvolatile cache memories

    NASA Astrophysics Data System (ADS)

    Ohsawa, Takashi; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

    2014-01-01

    Array operation currents in spin-transfer-torque magnetic random access memories (STT-MRAMs) that use four differential pair type magnetic tunnel junction (MTJ)-based memory cells (4T2MTJ, two 6T2MTJs and 8T2MTJ) are simulated and compared with that in SRAM. With L3 cache applications in mind, it is assumed that the memories are composed of 32 Mbyte capacity to be accessed in 64 byte in parallel. All the STT-MRAMs except for the 8T2MTJ one are designed with 32 bit fine-grained power gating scheme applied to eliminate static currents in the memory cells that are not accessed. The 8T2MTJ STT-MRAM, the cell’s design concept being not suitable for the fine-grained power gating, loads and saves 32 Mbyte data in 64 Mbyte unit per 1 Mbit sub-array in 2 × 103 cycles. It is shown that the array operation current of the 4T2MTJ STT-MRAM is 70 mA averaged in 15 ns write cycles at Vdd = 0.9 V. This is the smallest among the STT-MRAMs, about the half of the low standby power (LSTP) SRAM whose array operation current is totally dominated by the cells’ subthreshold leakage.

  8. Conductance Quantization in Resistive Random Access Memory

    NASA Astrophysics Data System (ADS)

    Li, Yang; Long, Shibing; Liu, Yang; Hu, Chen; Teng, Jiao; Liu, Qi; Lv, Hangbing; Suñé, Jordi; Liu, Ming

    2015-10-01

    The intrinsic scaling-down ability, simple metal-insulator-metal (MIM) sandwich structure, excellent performances, and complementary metal-oxide-semiconductor (CMOS) technology-compatible fabrication processes make resistive random access memory (RRAM) one of the most promising candidates for the next-generation memory. The RRAM device also exhibits rich electrical, thermal, magnetic, and optical effects, in close correlation with the abundant resistive switching (RS) materials, metal-oxide interface, and multiple RS mechanisms including the formation/rupture of nanoscale to atomic-sized conductive filament (CF) incorporated in RS layer. Conductance quantization effect has been observed in the atomic-sized CF in RRAM, which provides a good opportunity to deeply investigate the RS mechanism in mesoscopic dimension. In this review paper, the operating principles of RRAM are introduced first, followed by the summarization of the basic conductance quantization phenomenon in RRAM and the related RS mechanisms, device structures, and material system. Then, we discuss the theory and modeling of quantum transport in RRAM. Finally, we present the opportunities and challenges in quantized RRAM devices and our views on the future prospects.

  9. Conductance Quantization in Resistive Random Access Memory.

    PubMed

    Li, Yang; Long, Shibing; Liu, Yang; Hu, Chen; Teng, Jiao; Liu, Qi; Lv, Hangbing; Suñé, Jordi; Liu, Ming

    2015-12-01

    The intrinsic scaling-down ability, simple metal-insulator-metal (MIM) sandwich structure, excellent performances, and complementary metal-oxide-semiconductor (CMOS) technology-compatible fabrication processes make resistive random access memory (RRAM) one of the most promising candidates for the next-generation memory. The RRAM device also exhibits rich electrical, thermal, magnetic, and optical effects, in close correlation with the abundant resistive switching (RS) materials, metal-oxide interface, and multiple RS mechanisms including the formation/rupture of nanoscale to atomic-sized conductive filament (CF) incorporated in RS layer. Conductance quantization effect has been observed in the atomic-sized CF in RRAM, which provides a good opportunity to deeply investigate the RS mechanism in mesoscopic dimension. In this review paper, the operating principles of RRAM are introduced first, followed by the summarization of the basic conductance quantization phenomenon in RRAM and the related RS mechanisms, device structures, and material system. Then, we discuss the theory and modeling of quantum transport in RRAM. Finally, we present the opportunities and challenges in quantized RRAM devices and our views on the future prospects.

  10. Processing/structure/property Relationships of Barium Strontium Titanate Thin Films for Dynamic Random Access Memory Application.

    NASA Astrophysics Data System (ADS)

    Peng, Cheng-Jien

    The purpose of this study is to see the application feasibility of barium strontium titanate (BST) thin films on ultra large scale integration (ULSI) dynamic random access memory (DRAM) capacitors through the understanding of the relationships among processing, structure and electrical properties. Thin films of BST were deposited by multi-ion -beam reactive sputtering (MIBERS) technique and metallo -organic decomposition (MOD) method. The processing parameters such as Ba/Sr ratio, substrate temperature, annealing temperature and time, film thickness and doping concentration were correlated with the structure and electric properties of the films. Some effects of secondary low-energy oxygen ion bombardment were also examined. Microstructures of BST thin films could be classified into two types: (a) Type I structures, with multi-grains through the film thickness, for amorphous as-grown films after high temperature annealing, and (b) columnar structure (Type II) which remained even after high temperature annealing, for well-crystallized films deposited at high substrate temperatures. Type I films showed Curie-von Schweidler response, while Type II films showed Debted type behavior. Type I behavior may be attributed to the presence of a high density of disordered grain boundaries. Two types of current -voltage characteristics could be seen in non-bombarded films depending on the chemistry of the films (doped or undoped) and substrate temperature during deposition. Only the MIBERS films doped with high donor concentration and deposited at high substrate temperature showed space-charge -limited conduction (SCLC) with discrete shallow traps embedded in trap-distributed background at high electric field. All other non-bombarded films, including MOD films, showed trap-distributed SCLC behavior with a slope of {~}7.5-10 due to the presence of grain boundaries through film thickness or traps induced by unavoidable acceptor impurities in the films. Donor-doping could

  11. Single-electron thermal noise

    NASA Astrophysics Data System (ADS)

    Nishiguchi, Katsuhiko; Ono, Yukinori; Fujiwara, Akira

    2014-07-01

    We report the observation of thermal noise in the motion of single electrons in an ultimately small dynamic random access memory (DRAM). The nanometer-scale transistors that compose the DRAM resolve the thermal noise in single-electron motion. A complete set of fundamental tests conducted on this single-electron thermal noise shows that the noise perfectly follows all the aspects predicted by statistical mechanics, which include the occupation probability, the law of equipartition, a detailed balance, and the law of kT/C. In addition, the counting statistics on the directional motion (i.e., the current) of the single-electron thermal noise indicate that the individual electron motion follows the Poisson process, as it does in shot noise.

  12. Single-electron thermal noise.

    PubMed

    Nishiguchi, Katsuhiko; Ono, Yukinori; Fujiwara, Akira

    2014-07-11

    We report the observation of thermal noise in the motion of single electrons in an ultimately small dynamic random access memory (DRAM). The nanometer-scale transistors that compose the DRAM resolve the thermal noise in single-electron motion. A complete set of fundamental tests conducted on this single-electron thermal noise shows that the noise perfectly follows all the aspects predicted by statistical mechanics, which include the occupation probability, the law of equipartition, a detailed balance, and the law of kT/C. In addition, the counting statistics on the directional motion (i.e., the current) of the single-electron thermal noise indicate that the individual electron motion follows the Poisson process, as it does in shot noise.

  13. Design of Unstructured Adaptive (UA) NAS Parallel Benchmark Featuring Irregular, Dynamic Memory Accesses

    NASA Technical Reports Server (NTRS)

    Feng, Hui-Yu; VanderWijngaart, Rob; Biswas, Rupak; Biegel, Bryan (Technical Monitor)

    2001-01-01

    We describe the design of a new method for the measurement of the performance of modern computer systems when solving scientific problems featuring irregular, dynamic memory accesses. The method involves the solution of a stylized heat transfer problem on an unstructured, adaptive grid. A Spectral Element Method (SEM) with an adaptive, nonconforming mesh is selected to discretize the transport equation. The relatively high order of the SEM lowers the fraction of wall clock time spent on inter-processor communication, which eases the load balancing task and allows us to concentrate on the memory accesses. The benchmark is designed to be three-dimensional. Parallelization and load balance issues of a reference implementation will be described in detail in future reports.

  14. Unique method for controlling device level overlay with high-NA optical overlay technique using YieldStar in a DRAM HVM environment

    NASA Astrophysics Data System (ADS)

    Park, Dong-Kiu; Kim, Hyun-Sok; Seo, Moo-Young; Ju, Jae-Wuk; Kim, Young-Sik; Shahrjerdy, Mir; van Leest, Arno; Soco, Aileen; Miceli, Giacomo; Massier, Jennifer; McNamara, Elliott; Hinnen, Paul; Böcker, Paul; Oh, Nang-Lyeom; Jung, Sang-Hoon; Chai, Yvon; Lee, Jun-Hyung

    2018-03-01

    This paper demonstrates the improvement using the YieldStar S-1250D small spot, high-NA, after-etch overlay in-device measurements in a DRAM HVM environment. It will be demonstrated that In-device metrology (IDM) captures after-etch device fingerprints more accurately compared to the industry-standard CDSEM. Also, IDM measurements (acquiring both CD and overlay) can be executed significantly faster increasing the wafer sampling density that is possible within a realistic metrology budget. The improvements to both speed and accuracy open the possibility of extended modeling and correction capabilities for control. The proof-book data of this paper shows a 36% improvement of device overlay after switching to control in a DRAM HVM environment using indevice metrology.

  15. Direct memory access transfer completion notification

    DOEpatents

    Chen, Dong; Giampapa, Mark E.; Heidelberger, Philip; Kumar, Sameer; Parker, Jeffrey J.; Steinmacher-Burow, Burkhard D.; Vranas, Pavlos

    2010-07-27

    Methods, compute nodes, and computer program products are provided for direct memory access (`DMA`) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (`FIFO`) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.

  16. Parallel Optical Random Access Memory (PORAM)

    NASA Technical Reports Server (NTRS)

    Alphonse, G. A.

    1989-01-01

    It is shown that the need to minimize component count, power and size, and to maximize packing density require a parallel optical random access memory to be designed in a two-level hierarchy: a modular level and an interconnect level. Three module designs are proposed, in the order of research and development requirements. The first uses state-of-the-art components, including individually addressed laser diode arrays, acousto-optic (AO) deflectors and magneto-optic (MO) storage medium, aimed at moderate size, moderate power, and high packing density. The next design level uses an electron-trapping (ET) medium to reduce optical power requirements. The third design uses a beam-steering grating surface emitter (GSE) array to reduce size further and minimize the number of components.

  17. Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

    NASA Astrophysics Data System (ADS)

    Okamoto, Shin-ichi; Maekawa, Kei-ichi; Kawashima, Yoshiyuki; Shiba, Kazutoshi; Sugiyama, Hideki; Inoue, Masao; Nishida, Akio

    2015-04-01

    High quality static random access memory (SRAM) for 40-nm embedded MONOS flash memory with split gate (SG-MONOS) was developed. Marginal failure, which results in threshold voltage/drain current tailing and outliers of SRAM transistors, occurs when using a conventional SRAM structure. These phenomena can be explained by not only gate depletion but also partial depletion and percolation path formation in the MOS channel. A stacked poly-Si gate structure can suppress these phenomena and achieve high quality SRAM without any defects in the 6σ level and with high affinity to the 40-nm SG-MONOS process was developed.

  18. Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

    NASA Astrophysics Data System (ADS)

    Ando, K.; Fujita, S.; Ito, J.; Yuasa, S.; Suzuki, Y.; Nakatani, Y.; Miyazaki, T.; Yoda, H.

    2014-05-01

    Most parts of present computer systems are made of volatile devices, and the power to supply them to avoid information loss causes huge energy losses. We can eliminate this meaningless energy loss by utilizing the non-volatile function of advanced spin-transfer torque magnetoresistive random-access memory (STT-MRAM) technology and create a new type of computer, i.e., normally off computers. Critical tasks to achieve normally off computers are implementations of STT-MRAM technologies in the main memory and low-level cache memories. STT-MRAM technology for applications to the main memory has been successfully developed by using perpendicular STT-MRAMs, and faster STT-MRAM technologies for applications to the cache memory are now being developed. The present status of STT-MRAMs and challenges that remain for normally off computers are discussed.

  19. NRAM: a disruptive carbon-nanotube resistance-change memory.

    PubMed

    Gilmer, D C; Rueckes, T; Cleveland, L

    2018-04-03

    Advanced memory technology based on carbon nanotubes (CNTs) (NRAM) possesses desired properties for implementation in a host of integrated systems due to demonstrated advantages of its operation including high speed (nanotubes can switch state in picoseconds), high endurance (over a trillion), and low power (with essential zero standby power). The applicable integrated systems for NRAM have markets that will see compound annual growth rates (CAGR) of over 62% between 2018 and 2023, with an embedded systems CAGR of 115% in 2018-2023 (http://bccresearch.com/pressroom/smc/bcc-research-predicts:-nram-(finally)-to-revolutionize-computer-memory). These opportunities are helping drive the realization of a shift from silicon-based to carbon-based (NRAM) memories. NRAM is a memory cell made up of an interlocking matrix of CNTs, either touching or slightly separated, leading to low or higher resistance states respectively. The small movement of atoms, as opposed to moving electrons for traditional silicon-based memories, renders NRAM with a more robust endurance and high temperature retention/operation which, along with high speed/low power, is expected to blossom in this memory technology to be a disruptive replacement for the current status quo of DRAM (dynamic RAM), SRAM (static RAM), and NAND flash memories.

  20. NRAM: a disruptive carbon-nanotube resistance-change memory

    NASA Astrophysics Data System (ADS)

    Gilmer, D. C.; Rueckes, T.; Cleveland, L.

    2018-04-01

    Advanced memory technology based on carbon nanotubes (CNTs) (NRAM) possesses desired properties for implementation in a host of integrated systems due to demonstrated advantages of its operation including high speed (nanotubes can switch state in picoseconds), high endurance (over a trillion), and low power (with essential zero standby power). The applicable integrated systems for NRAM have markets that will see compound annual growth rates (CAGR) of over 62% between 2018 and 2023, with an embedded systems CAGR of 115% in 2018-2023 (http://bccresearch.com/pressroom/smc/bcc-research-predicts:-nram-(finally)-to-revolutionize-computer-memory). These opportunities are helping drive the realization of a shift from silicon-based to carbon-based (NRAM) memories. NRAM is a memory cell made up of an interlocking matrix of CNTs, either touching or slightly separated, leading to low or higher resistance states respectively. The small movement of atoms, as opposed to moving electrons for traditional silicon-based memories, renders NRAM with a more robust endurance and high temperature retention/operation which, along with high speed/low power, is expected to blossom in this memory technology to be a disruptive replacement for the current status quo of DRAM (dynamic RAM), SRAM (static RAM), and NAND flash memories.

  1. Design of a memory-access controller with 3.71-times-enhanced energy efficiency for Internet-of-Things-oriented nonvolatile microcontroller unit

    NASA Astrophysics Data System (ADS)

    Natsui, Masanori; Hanyu, Takahiro

    2018-04-01

    In realizing a nonvolatile microcontroller unit (MCU) for sensor nodes in Internet-of-Things (IoT) applications, it is important to solve the data-transfer bottleneck between the central processing unit (CPU) and the nonvolatile memory constituting the MCU. As one circuit-oriented approach to solving this problem, we propose a memory access minimization technique for magnetoresistive-random-access-memory (MRAM)-embedded nonvolatile MCUs. In addition to multiplexing and prefetching of memory access, the proposed technique realizes efficient instruction fetch by eliminating redundant memory access while considering the code length of the instruction to be fetched and the transition of the memory address to be accessed. As a result, the performance of the MCU can be improved while relaxing the performance requirement for the embedded MRAM, and compact and low-power implementation can be performed as compared with the conventional cache-based one. Through the evaluation using a system consisting of a general purpose 32-bit CPU and embedded MRAM, it is demonstrated that the proposed technique increases the peak efficiency of the system up to 3.71 times, while a 2.29-fold area reduction is achieved compared with the cache-based one.

  2. Fault-tolerant NAND-flash memory module for next-generation scientific instruments

    NASA Astrophysics Data System (ADS)

    Lange, Tobias; Michel, Holger; Fiethe, Björn; Michalik, Harald; Walter, Dietmar

    2015-10-01

    Remote sensing instruments on today's space missions deliver a high amount of data which is typically evaluated on ground. Especially for deep space missions the telemetry downlink is very limited which creates the need for the scientific evaluation and thereby a reduction of data volume already on-board the spacecraft. A demanding example is the Polarimetric and Helioseismic Imager (PHI) instrument on Solar Orbiter. To enable on-board offline processing for data reduction, the instrument has to be equipped with a high capacity memory module. The module is based on non-volatile NAND-Flash technology, which requires more advanced operation than volatile DRAM. Unlike classical mass memories, the module is integrated into the instrument and allows readback of data for processing. The architecture and safe operation of such kind of memory module is described in the following paper.

  3. The special role of item-context associations in the direct-access region of working memory.

    PubMed

    Campoy, Guillermo

    2017-09-01

    The three-embedded-component model of working memory (WM) distinguishes three representational states corresponding to three WM regions: activated long-term memory, direct-access region (DAR), and focus of attention. Recent neuroimaging research has revealed that access to the DAR is associated with enhanced hippocampal activity. Because the hippocampus mediates the encoding and retrieval of item-context associations, it has been suggested that this hippocampal activation is a consequence of the fact that item-context associations are particularly strong and accessible in the DAR. This study provides behavioral evidence for this view using an item-recognition task to assess the effect of non-intentional encoding and maintenance of item-location associations across WM regions. Five pictures of human faces were sequentially presented in different screen locations followed by a recognition probe. Visual cues immediately preceding the probe indicated the location thereof. When probe stimuli appeared in the same location that they had been presented within the memory set, the presentation of the cue was expected to elicit the activation of the corresponding WM representation through the just-established item-location association, resulting in faster recognition. Results showed this same-location effect, but only for items that, according to their serial position within the memory set, were held in the DAR.

  4. MPEG-1 low-cost encoder solution

    NASA Astrophysics Data System (ADS)

    Grueger, Klaus; Schirrmeister, Frank; Filor, Lutz; von Reventlow, Christian; Schneider, Ulrich; Mueller, Gerriet; Sefzik, Nicolai; Fiedrich, Sven

    1995-02-01

    A solution for real-time compression of digital YCRCB video data to an MPEG-1 video data stream has been developed. As an additional option, motion JPEG and video telephone streams (H.261) can be generated. For MPEG-1, up to two bidirectional predicted images are supported. The required computational power for motion estimation and DCT/IDCT, memory size and memory bandwidth have been the main challenges. The design uses fast-page-mode memory accesses and requires only one single 80 ns EDO-DRAM with 256 X 16 organization for video encoding. This can be achieved only by using adequate access and coding strategies. The architecture consists of an input processing and filter unit, a memory interface, a motion estimation unit, a motion compensation unit, a DCT unit, a quantization control, a VLC unit and a bus interface. For using the available memory bandwidth by the processing tasks, a fixed schedule for memory accesses has been applied, that can be interrupted for asynchronous events. The motion estimation unit implements a highly sophisticated hierarchical search strategy based on block matching. The DCT unit uses a separated fast-DCT flowgraph realized by a switchable hardware unit for both DCT and IDCT operation. By appropriate multiplexing, only one multiplier is required for: DCT, quantization, inverse quantization, and IDCT. The VLC unit generates the video-stream up to the video sequence layer and is directly coupled with an intelligent bus-interface. Thus, the assembly of video, audio and system data can easily be performed by the host computer. Having a relatively low complexity and only small requirements for DRAM circuits, the developed solution can be applied to low-cost encoding products for consumer electronics.

  5. Research on Optical Transmitter and Receiver Module Used for High-Speed Interconnection between CPU and Memory

    NASA Astrophysics Data System (ADS)

    He, Huimin; Liu, Fengman; Li, Baoxia; Xue, Haiyun; Wang, Haidong; Qiu, Delong; Zhou, Yunyan; Cao, Liqiang

    2016-11-01

    With the development of the multicore processor, the bandwidth and capacity of the memory, rather than the memory area, are the key factors in server performance. At present, however, the new architectures, such as fully buffered DIMM (FBDIMM), hybrid memory cube (HMC), and high bandwidth memory (HBM), cannot be commercially applied in the server. Therefore, a new architecture for the server is proposed. CPU and memory are separated onto different boards, and optical interconnection is used for the communication between them. Each optical module corresponds to each dual inline memory module (DIMM) with 64 channels. Compared to the previous technology, not only can the architecture realize high-capacity and wide-bandwidth memory, it also can reduce power consumption and cost, and be compatible with the existing dynamic random access memory (DRAM). In this article, the proposed module with system-in-package (SiP) integration is demonstrated. In the optical module, the silicon photonic chip is included, which is a promising technology to be applied in the next-generation data exchanging centers. And due to the bandwidth-distance performance of the optical interconnection, SerDes chips are introduced to convert the 64-bit data at 800 Mbps from/to 4-channel data at 12.8 Gbps after/before they are transmitted though optical fiber. All the devices are packaged on cheap organic substrates. To ensure the performance of the whole system, several optimization efforts have been performed on the two modules. High-speed interconnection traces have been designed and simulated with electromagnetic simulation software. Steady-state thermal characteristics of the transceiver module have been evaluated by ANSYS APLD based on finite-element methodology (FEM). Heat sinks are placed at the hotspot area to ensure the reliability of all working chips. Finally, this transceiver system based on silicon photonics is measured, and the eye diagrams of data and clock signals are verified.

  6. Template Based Low Data Rate Speech Encoder

    DTIC Science & Technology

    1993-09-30

    Nasality Distinguishes In/ from d/ 95.6 96.9 1m/ from /b/, etc. Sustention Distinguishes /f/ from /p/, $7.5 88.3 ibi from N/, Al from /0 8. etc. Sibilation...processor performs mainly Processor Workstation input/output (I/O) operations. The dynamic random access memory (DRAM) has 16 million bytes of...storage capacity. To execute the 800-b/s voice algorithm, the following amount of memory is needed: 5 MB for tables, 1.5 MB for it "program, and 30 KB for

  7. 3D Stacked Memory Final Report CRADA No. TC-0494-93

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Bernhardt, A.; Beene, G.

    TI and LLNL demonstrated: (1) a process for the fabrication of 3-D memory using stacked DRAM chips, and (2) a fast prototyping process for 3-D stacks and MCMs. The metallization to route the chip pads to the sides of the die was carried out in a single high-speed masking step. The mask was not the usual physical one in glass and chrome, but was simply a computer file used to control the laser patterning process. Changes in either chip or customer circuit-board pad layout were easily and inexpensively accommodated, so that prototyping was a natural consequence of the laser patterningmore » process. As in the current TI process, a dielectric layer was added to the wafer, and vias to the chip I/0 pads were formed. All of the steps in Texas Instruments earlier process that were required to gold bump the pads were eliminated, significantly reducing fabrication cost and complexity. Pads were created on the sides of ·the die, which became pads on the side of the stack. In order to extend the process to accommodate non-memory devices with substantially greater I/0 than is required for DRAMs, pads were patterned on two sides of the memory stacks as a proof of principle. Stacking and bonding were done using modifications of the current TI process. After stacking and bonding, the pads on the sides of the dice were connected by application of a polyimide insulator film with laser ablation of the polyimide to form contacts to the pads. Then metallization was accomplished in the same manner as on the individual die.« less

  8. Remote direct memory access

    DOEpatents

    Archer, Charles J.; Blocksome, Michael A.

    2012-12-11

    Methods, parallel computers, and computer program products are disclosed for remote direct memory access. Embodiments include transmitting, from an origin DMA engine on an origin compute node to a plurality target DMA engines on target compute nodes, a request to send message, the request to send message specifying a data to be transferred from the origin DMA engine to data storage on each target compute node; receiving, by each target DMA engine on each target compute node, the request to send message; preparing, by each target DMA engine, to store data according to the data storage reference and the data length, including assigning a base storage address for the data storage reference; sending, by one or more of the target DMA engines, an acknowledgment message acknowledging that all the target DMA engines are prepared to receive a data transmission from the origin DMA engine; receiving, by the origin DMA engine, the acknowledgement message from the one or more of the target DMA engines; and transferring, by the origin DMA engine, data to data storage on each of the target compute nodes according to the data storage reference using a single direct put operation.

  9. Optimizing NEURON Simulation Environment Using Remote Memory Access with Recursive Doubling on Distributed Memory Systems.

    PubMed

    Shehzad, Danish; Bozkuş, Zeki

    2016-01-01

    Increase in complexity of neuronal network models escalated the efforts to make NEURON simulation environment efficient. The computational neuroscientists divided the equations into subnets amongst multiple processors for achieving better hardware performance. On parallel machines for neuronal networks, interprocessor spikes exchange consumes large section of overall simulation time. In NEURON for communication between processors Message Passing Interface (MPI) is used. MPI_Allgather collective is exercised for spikes exchange after each interval across distributed memory systems. The increase in number of processors though results in achieving concurrency and better performance but it inversely affects MPI_Allgather which increases communication time between processors. This necessitates improving communication methodology to decrease the spikes exchange time over distributed memory systems. This work has improved MPI_Allgather method using Remote Memory Access (RMA) by moving two-sided communication to one-sided communication, and use of recursive doubling mechanism facilitates achieving efficient communication between the processors in precise steps. This approach enhanced communication concurrency and has improved overall runtime making NEURON more efficient for simulation of large neuronal network models.

  10. Optimizing NEURON Simulation Environment Using Remote Memory Access with Recursive Doubling on Distributed Memory Systems

    PubMed Central

    Bozkuş, Zeki

    2016-01-01

    Increase in complexity of neuronal network models escalated the efforts to make NEURON simulation environment efficient. The computational neuroscientists divided the equations into subnets amongst multiple processors for achieving better hardware performance. On parallel machines for neuronal networks, interprocessor spikes exchange consumes large section of overall simulation time. In NEURON for communication between processors Message Passing Interface (MPI) is used. MPI_Allgather collective is exercised for spikes exchange after each interval across distributed memory systems. The increase in number of processors though results in achieving concurrency and better performance but it inversely affects MPI_Allgather which increases communication time between processors. This necessitates improving communication methodology to decrease the spikes exchange time over distributed memory systems. This work has improved MPI_Allgather method using Remote Memory Access (RMA) by moving two-sided communication to one-sided communication, and use of recursive doubling mechanism facilitates achieving efficient communication between the processors in precise steps. This approach enhanced communication concurrency and has improved overall runtime making NEURON more efficient for simulation of large neuronal network models. PMID:27413363

  11. Cost effective solution using inverse lithography OPC for DRAM random contact layer

    NASA Astrophysics Data System (ADS)

    Jun, Jinhyuck; Hwang, Jaehee; Choi, Jaeseung; Oh, Seyoung; Park, Chanha; Yang, Hyunjo; Dam, Thuc; Do, Munhoe; Lee, Dong Chan; Xiao, Guangming; Choi, Jung-Hoe; Lucas, Kevin

    2017-04-01

    Many different advanced devices and design layers currently employ double patterning technology (DPT) as a means to overcome lithographic and OPC limitations at low k1 values. Certainly device layers with k1 value below 0.25 require DPT or other pitch splitting methodologies. DPT has also been used to improve patterning of certain device layers with k1 values slightly above 0.25, due to the difficulty of achieving sufficient pattern fidelity with only a single exposure. Unfortunately, this broad adoption of DPT also came with a significant increase in patterning process cost. In this paper, we discuss the development of a single patterning technology process using an integrated Inverse Lithography Technology (ILT) flow for mask synthesis. A single pattering technology flow will reduce the manufacturing cost for a k1 > 0.25 full chip random contact layer in a memory device by replacing the more expensive DPT process with ILT flow, while also maintaining good lithographic production quality and manufacturable OPC/RET production metrics. This new integrated flow consists of applying ILT to the difficult core region and traditional rule-based assist features (RBAFs) with OPC to the peripheral region of a DRAM contact layer. Comparisons of wafer results between the ILT process and the non-ILT process showed the lithographic benefits of ILT and its ability to enable a robust single patterning process for this low-k1 device layer. Advanced modeling with a negative tone develop (NTD) process achieved the accuracy levels needed for ILT to control feature shapes through dose and focus. Details of these afore mentioned results will be described in the paper.

  12. Reed Solomon codes for error control in byte organized computer memory systems

    NASA Technical Reports Server (NTRS)

    Lin, S.; Costello, D. J., Jr.

    1984-01-01

    A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation are presented. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative algorithm to find the error locator polynomial.

  13. Administering an epoch initiated for remote memory access

    DOEpatents

    Blocksome, Michael A; Miller, Douglas R

    2014-03-18

    Methods, systems, and products are disclosed for administering an epoch initiated for remote memory access that include: initiating, by an origin application messaging module on an origin compute node, one or more data transfers to a target compute node for the epoch; initiating, by the origin application messaging module after initiating the data transfers, a closing stage for the epoch, including rejecting any new data transfers after initiating the closing stage for the epoch; determining, by the origin application messaging module, whether the data transfers have completed; and closing, by the origin application messaging module, the epoch if the data transfers have completed.

  14. Administering an epoch initiated for remote memory access

    DOEpatents

    Blocksome, Michael A; Miller, Douglas R

    2012-10-23

    Methods, systems, and products are disclosed for administering an epoch initiated for remote memory access that include: initiating, by an origin application messaging module on an origin compute node, one or more data transfers to a target compute node for the epoch; initiating, by the origin application messaging module after initiating the data transfers, a closing stage for the epoch, including rejecting any new data transfers after initiating the closing stage for the epoch; determining, by the origin application messaging module, whether the data transfers have completed; and closing, by the origin application messaging module, the epoch if the data transfers have completed.

  15. Administering an epoch initiated for remote memory access

    DOEpatents

    Blocksome, Michael A.; Miller, Douglas R.

    2013-01-01

    Methods, systems, and products are disclosed for administering an epoch initiated for remote memory access that include: initiating, by an origin application messaging module on an origin compute node, one or more data transfers to a target compute node for the epoch; initiating, by the origin application messaging module after initiating the data transfers, a closing stage for the epoch, including rejecting any new data transfers after initiating the closing stage for the epoch; determining, by the origin application messaging module, whether the data transfers have completed; and closing, by the origin application messaging module, the epoch if the data transfers have completed.

  16. A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

    NASA Astrophysics Data System (ADS)

    Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

    2006-04-01

    A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

  17. Optical interconnection network for parallel access to multi-rank memory in future computing systems.

    PubMed

    Wang, Kang; Gu, Huaxi; Yang, Yintang; Wang, Kun

    2015-08-10

    With the number of cores increasing, there is an emerging need for a high-bandwidth low-latency interconnection network, serving core-to-memory communication. In this paper, aiming at the goal of simultaneous access to multi-rank memory, we propose an optical interconnection network for core-to-memory communication. In the proposed network, the wavelength usage is delicately arranged so that cores can communicate with different ranks at the same time and broadcast for flow control can be achieved. A distributed memory controller architecture that works in a pipeline mode is also designed for efficient optical communication and transaction address processes. The scaling method and wavelength assignment for the proposed network are investigated. Compared with traditional electronic bus-based core-to-memory communication, the simulation results based on the PARSEC benchmark show that the bandwidth enhancement and latency reduction are apparent.

  18. Soft errors in commercial off-the-shelf static random access memories

    NASA Astrophysics Data System (ADS)

    Dilillo, L.; Tsiligiannis, G.; Gupta, V.; Bosser, A.; Saigne, F.; Wrobel, F.

    2017-01-01

    This article reviews state-of-the-art techniques for the evaluation of the effect of radiation on static random access memory (SRAM). We detailed irradiation test techniques and results from irradiation experiments with several types of particles. Two commercial SRAMs, in 90 and 65 nm technology nodes, were considered as case studies. Besides the basic static and dynamic test modes, advanced stimuli for the irradiation tests were introduced, as well as statistical post-processing techniques allowing for deeper analysis of the correlations between bit-flip cross-sections and design/architectural characteristics of the memory device. Further insight is provided on the response of irradiated stacked layer devices and on the use of characterized SRAM devices as particle detectors.

  19. The differential effects of ecstasy/polydrug use on executive components: shifting, inhibition, updating and access to semantic memory.

    PubMed

    Montgomery, Catharine; Fisk, John E; Newcombe, Russell; Murphy, Phillip N

    2005-10-01

    Recent theoretical models suggest that the central executive may not be a unified structure. The present study explored the nature of central executive deficits in ecstasy users. In study 1, 27 ecstasy users and 34 non-users were assessed using tasks to tap memory updating (computation span; letter updating) and access to long-term memory (a semantic fluency test and the Chicago Word Fluency Test). In study 2, 51 ecstasy users and 42 non-users completed tasks that assess mental set switching (number/letter and plus/minus) and inhibition (random letter generation). MANOVA revealed that ecstasy users performed worse on both tasks used to assess memory updating and on tasks to assess access to long-term memory (C- and S-letter fluency). However, notwithstanding the significant ecstasy group-related effects, indices of cocaine and cannabis use were also significantly correlated with most of the executive measures. Unexpectedly, in study 2, ecstasy users performed significantly better on the inhibition task, producing more letters than non-users. No group differences were observed on the switching tasks. Correlations between indices of ecstasy use and number of letters produced were significant. The present study provides further support for ecstasy/polydrug-related deficits in memory updating and in access to long-term memory. The surplus evident on the inhibition task should be treated with some caution, as this was limited to a single measure and has not been supported by our previous work.

  20. Dual operation characteristics of resistance random access memory in indium-gallium-zinc-oxide thin film transistors

    NASA Astrophysics Data System (ADS)

    Yang, Jyun-Bao; Chang, Ting-Chang; Huang, Jheng-Jie; Chen, Yu-Chun; Chen, Yu-Ting; Tseng, Hsueh-Chih; Chu, Ann-Kuo; Sze, Simon M.

    2014-04-01

    In this study, indium-gallium-zinc-oxide thin film transistors can be operated either as transistors or resistance random access memory devices. Before the forming process, current-voltage curve transfer characteristics are observed, and resistance switching characteristics are measured after a forming process. These resistance switching characteristics exhibit two behaviors, and are dominated by different mechanisms. The mode 1 resistance switching behavior is due to oxygen vacancies, while mode 2 is dominated by the formation of an oxygen-rich layer. Furthermore, an easy approach is proposed to reduce power consumption when using these resistance random access memory devices with the amorphous indium-gallium-zinc-oxide thin film transistor.

  1. Fencing direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOEpatents

    Blocksome, Michael A.; Mamidala, Amith R.

    2013-09-03

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  2. Fencing direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOEpatents

    Blocksome, Michael A; Mamidala, Amith R

    2014-02-11

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  3. The dynamics of access to groups in working memory.

    PubMed

    Farrell, Simon; Lelièvre, Anna

    2012-11-01

    The finding that participants leave a pause between groups when attempting serial recall of temporally grouped lists has been taken to indicate access to a hierarchical representation of the list in working memory. An alternative explanation is that the dynamics of serial recall solely reflect output (rather than memorial) processes, with the temporal pattern at input merely suggesting a basis for the pattern of output buffering. Three experiments are presented here that disentangle input structure from output buffering in serial recall. In Experiment 1, participants were asked to recall a subset of visually presented digits from a temporally grouped list in their original order, where either within-group position or group position was kept constant. In Experiment 2, participants performed more standard serial recall of spoken digits, and input and output position were dissociated by asking participants to initiate recall from a post-cued position in the list. In Experiment 3, participants were asked to serially recall temporally grouped lists of visually presented digits where the grouping structure was unpredictable, under either articulatory suppression or silent conditions. The 3 experiments point to a tight linkage between implied memorial structures (i.e., the pattern of grouping at encoding) and the output structure implied by retrieval times and call into question a purely motoric account of the dynamics of recall.

  4. Making Physical Activity Accessible to Older Adults with Memory Loss: A Feasibility Study

    ERIC Educational Resources Information Center

    Logsdon, Rebecca G.; McCurry, Susan M.; Pike, Kenneth C.; Teri, Linda

    2009-01-01

    Purpose: For individuals with mild cognitive impairment (MCI), memory loss may prevent successful engagement in exercise, a key factor in preventing additional disability. The Resources and Activities for Life Long Independence (RALLI) program uses behavioral principles to make exercise more accessible for these individuals. Exercises are broken…

  5. Immigration, Language Proficiency, and Autobiographical Memories: Lifespan Distribution and Second-Language Access

    PubMed Central

    Esposito, Alena G.; Baker-Ward, Lynne

    2015-01-01

    This investigation examined two controversies in the autobiographical literature: how cross-language immigration affects the distribution of autobiographical memories across the lifespan and under what circumstances language-dependent recall is observed. Both Spanish/English bilingual immigrants and English monolingual non-immigrants participated in a cue word study, with the bilingual sample taking part in a within-subject language manipulation. The expected bump in the number of memories from early life was observed for non-immigrants but not immigrants, who reported more memories for events surrounding immigration. Aspects of the methodology addressed possible reasons for past discrepant findings. Language-dependent recall was influenced by second-language proficiency. Results were interpreted as evidence that bilinguals with high second-language proficiency, in contrast to those with lower second-language proficiency, access a single conceptual store through either language. The final multi-level model predicting language-dependent recall, including second-language proficiency, age of immigration, internal language, and cue word language, explained ¾ of the between-person variance and ⅕ of the within-person variance. We arrive at two conclusions. First, major life transitions influence the distribution of memories. Second, concept representation across multiple languages follows a developmental model. In addition, the results underscore the importance of considering language experience in research involving memory reports. PMID:26274061

  6. Immigration, language proficiency, and autobiographical memories: Lifespan distribution and second-language access.

    PubMed

    Esposito, Alena G; Baker-Ward, Lynne

    2016-08-01

    This investigation examined two controversies in the autobiographical literature: how cross-language immigration affects the distribution of autobiographical memories across the lifespan and under what circumstances language-dependent recall is observed. Both Spanish/English bilingual immigrants and English monolingual non-immigrants participated in a cue word study, with the bilingual sample taking part in a within-subject language manipulation. The expected bump in the number of memories from early life was observed for non-immigrants but not immigrants, who reported more memories for events surrounding immigration. Aspects of the methodology addressed possible reasons for past discrepant findings. Language-dependent recall was influenced by second-language proficiency. Results were interpreted as evidence that bilinguals with high second-language proficiency, in contrast to those with lower second-language proficiency, access a single conceptual store through either language. The final multi-level model predicting language-dependent recall, including second-language proficiency, age of immigration, internal language, and cue word language, explained ¾ of the between-person variance and (1)/5 of the within-person variance. We arrive at two conclusions. First, major life transitions influence the distribution of memories. Second, concept representation across multiple languages follows a developmental model. In addition, the results underscore the importance of considering language experience in research involving memory reports.

  7. A Design Methodology for Optoelectronic VLSI

    DTIC Science & Technology

    2007-01-01

    current gets converted to a CMOS voltage level through a transimpedance amplifier circuit called a receiver. The output of the receiver is then...change the current flowing from the diode to a voltage that the logic inputs can use. That circuit is called a receiver. It is a transimpedance amplifier ...incorpo- rate random access memory circuits, SRAM or dynamic RAM (DRAM). These circuits use weak internal analog signals that are amplified by sense

  8. Constraints on Access: Costs and Benefits (Spontaneous Memory for Relevant Experiences)

    DTIC Science & Technology

    1989-05-01

    F. I. M. Craik (Eds.), Levels of processing and human memory. Hillsdale, NJ: Erlbaum. Dewey, J. (1963). How we think. Portions published in R. M...transfer. Pictures (vs. words) and levels of processing and elaborative encoding manipulations are shown to affect directed access but are found to have...includes most 5 6 list-learning experiments, research on schema/script abstraction, and studies of remembering which might manipulate levels of processing

  9. SSD Market Overview

    NASA Astrophysics Data System (ADS)

    Wong, G.

    The unparalleled cost and form factor advantages of NAND flash memory has driven 35 mm photographic film, floppy disks and one-inch hard drives to extinction. Due to its compelling price/performance characteristics, NAND Flash memory is now expanding its reach into the once-exclusive domain of hard disk drives and DRAM in the form of Solid State Drives (SSDs). Driven by the proliferation of thin and light mobile devices and the need for near-instantaneous accessing and sharing of content through the cloud, SSDs are expected to become a permanent fixture in the computing infrastructure.

  10. Electrical Evaluation of RCA MWS5501D Random Access Memory, Volume 2, Appendix a

    NASA Technical Reports Server (NTRS)

    Klute, A.

    1979-01-01

    The electrical characterization and qualification test results are presented for the RCA MWS5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. The address access time, address readout time, the data hold time, and the data setup time are some of the results surveyed.

  11. Ga-doped indium oxide nanowire phase change random access memory cells

    NASA Astrophysics Data System (ADS)

    Jin, Bo; Lim, Taekyung; Ju, Sanghyun; Latypov, Marat I.; Kim, Hyoung Seop; Meyyappan, M.; Lee, Jeong-Soo

    2014-02-01

    Phase change random access memory (PCRAM) devices are usually constructed using tellurium based compounds, but efforts to seek other materials providing desirable memory characteristics have continued. We have fabricated PCRAM devices using Ga-doped In2O3 nanowires with three different Ga compositions (Ga/(In+Ga) atomic ratio: 2.1%, 11.5% and 13.0%), and investigated their phase switching properties. The nanowires (˜40 nm in diameter) can be repeatedly switched between crystalline and amorphous phases, and Ga concentration-dependent memory switching behavior in the nanowires was observed with ultra-fast set/reset rates of 80 ns/20 ns, which are faster than for other competitive phase change materials. The observations of fast set/reset rates and two distinct states with a difference in resistance of two to three orders of magnitude appear promising for nonvolatile information storage. Moreover, we found that increasing the Ga concentration can reduce the power consumption and resistance drift; however, too high a level of Ga doping may cause difficulty in achieving the phase transition.

  12. Encoding and Retrieval Processes Involved in the Access of Source Information in the Absence of Item Memory

    ERIC Educational Resources Information Center

    Ball, B. Hunter; DeWitt, Michael R.; Knight, Justin B.; Hicks, Jason L.

    2014-01-01

    The current study sought to examine the relative contributions of encoding and retrieval processes in accessing contextual information in the absence of item memory using an extralist cuing procedure in which the retrieval cues used to query memory for contextual information were "related" to the target item but never actually studied.…

  13. ViSA: a neurodynamic model for visuo-spatial working memory, attentional blink, and conscious access.

    PubMed

    Simione, Luca; Raffone, Antonino; Wolters, Gezinus; Salmas, Paola; Nakatani, Chie; Belardinelli, Marta Olivetti; van Leeuwen, Cees

    2012-10-01

    Two separate lines of study have clarified the role of selectivity in conscious access to visual information. Both involve presenting multiple targets and distracters: one simultaneously in a spatially distributed fashion, the other sequentially at a single location. To understand their findings in a unified framework, we propose a neurodynamic model for Visual Selection and Awareness (ViSA). ViSA supports the view that neural representations for conscious access and visuo-spatial working memory are globally distributed and are based on recurrent interactions between perceptual and access control processors. Its flexible global workspace mechanisms enable a unitary account of a broad range of effects: It accounts for the limited storage capacity of visuo-spatial working memory, attentional cueing, and efficient selection with multi-object displays, as well as for the attentional blink and associated sparing and masking effects. In particular, the speed of consolidation for storage in visuo-spatial working memory in ViSA is not fixed but depends adaptively on the input and recurrent signaling. Slowing down of consolidation due to weak bottom-up and recurrent input as a result of brief presentation and masking leads to the attentional blink. Thus, ViSA goes beyond earlier 2-stage and neuronal global workspace accounts of conscious processing limitations. PsycINFO Database Record (c) 2012 APA, all rights reserved.

  14. Fencing direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Blocksome, Michael A.; Mamidala, Amith R.

    2013-09-03

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segmentmore » of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.« less

  15. Deciding with the eye: how the visually manipulated accessibility of information in memory influences decision behavior.

    PubMed

    Platzer, Christine; Bröder, Arndt; Heck, Daniel W

    2014-05-01

    Decision situations are typically characterized by uncertainty: Individuals do not know the values of different options on a criterion dimension. For example, consumers do not know which is the healthiest of several products. To make a decision, individuals can use information about cues that are probabilistically related to the criterion dimension, such as sugar content or the concentration of natural vitamins. In two experiments, we investigated how the accessibility of cue information in memory affects which decision strategy individuals rely on. The accessibility of cue information was manipulated by means of a newly developed paradigm, the spatial-memory-cueing paradigm, which is based on a combination of the looking-at-nothing phenomenon and the spatial-cueing paradigm. The results indicated that people use different decision strategies, depending on the validity of easily accessible information. If the easily accessible information is valid, people stop information search and decide according to a simple take-the-best heuristic. If, however, information that comes to mind easily has a low predictive validity, people are more likely to integrate all available cue information in a compensatory manner.

  16. Nonvolatile random access memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor); Katti, Romney R. (Inventor)

    1994-01-01

    A nonvolatile magnetic random access memory can be achieved by an array of magnet-Hall effect (M-H) elements. The storage function is realized with a rectangular thin-film ferromagnetic material having an in-plane, uniaxial anisotropy and inplane bipolar remanent magnetization states. The thin-film magnetic element is magnetized by a local applied field, whose direction is used to form either a 0 or 1 state. The element remains in the 0 or 1 state until a switching field is applied to change its state. The stored information is detcted by a Hall-effect sensor which senses the fringing field from the magnetic storage element. The circuit design for addressing each cell includes transistor switches for providing a current of selected polarity to store a binary digit through a separate conductor overlying the magnetic element of the cell. To read out a stored binary digit, transistor switches are employed to provide a current through a row of Hall-effect sensors connected in series and enabling a differential voltage amplifier connected to all Hall-effect sensors of a column in series. To avoid read-out voltage errors due to shunt currents through resistive loads of the Hall-effect sensors of other cells in the same column, at least one transistor switch is provided between every pair of adjacent cells in every row which are not turned on except in the row of the selected cell.

  17. Spin-transfer torque switched magnetic tunnel junctions in magnetic random access memory

    NASA Astrophysics Data System (ADS)

    Sun, Jonathan Z.

    2016-10-01

    Spin-transfer torque (or spin-torque, or STT) based magnetic tunnel junction (MTJ) is at the heart of a new generation of magnetism-based solid-state memory, the so-called spin-transfer-torque magnetic random access memory, or STT-MRAM. Over the past decades, STT-based switchable magnetic tunnel junction has seen progress on many fronts, including the discovery of (001) MgO as the most favored tunnel barrier, which together with (bcc) Fe or FeCo alloy are yielding best demonstrated tunnel magneto-resistance (TMR); the development of perpendicularly magnetized ultrathin CoFeB-type of thin films sufficient to support high density memories with junction sizes demonstrated down to 11nm in diameter; and record-low spin-torque switching threshold current, giving best reported switching efficiency over 5 kBT/μA. Here we review the basic device properties focusing on the perpendicularly magnetized MTJs, both in terms of switching efficiency as measured by sub-threshold, quasi-static methods, and of switching speed at super-threshold, forced switching. We focus on device behaviors important for memory applications that are rooted in fundamental device physics, which highlights the trade-off of device parameters for best suitable system integration.

  18. Emerging Applications for High K Materials in VLSI Technology

    PubMed Central

    Clark, Robert D.

    2014-01-01

    The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

  19. Working memory capacity and controlled serial memory search.

    PubMed

    Mızrak, Eda; Öztekin, Ilke

    2016-08-01

    The speed-accuracy trade-off (SAT) procedure was used to investigate the relationship between working memory capacity (WMC) and the dynamics of temporal order memory retrieval. High- and low-span participants (HSs, LSs) studied sequentially presented five-item lists, followed by two probes from the study list. Participants indicated the more recent probe. Overall, accuracy was higher for HSs compared to LSs. Crucially, in contrast to previous investigations that observed no impact of WMC on speed of access to item information in memory (e.g., Öztekin & McElree, 2010), recovery of temporal order memory was slower for LSs. While accessing an item's representation in memory can be direct, recovery of relational information such as temporal order information requires a more controlled serial memory search. Collectively, these data indicate that WMC effects are particularly prominent during high demands of cognitive control, such as serial search operations necessary to access temporal order information from memory. Copyright © 2016 Elsevier B.V. All rights reserved.

  20. Recommendations on dram shop liability and overservice law enforcement initiatives to prevent excessive alcohol consumption and related harms.

    PubMed

    2011-09-01

    The Task Force on Community Preventive Services recommends the use of dram shop liability laws, on the basis of strong evidence of effectiveness in preventing and reducing alcohol-related harms. The Task Force found insufficient evidence to determine the effectiveness of overservice law enforcement initiatives as a means to reduce excessive alcohol consumption and related harms, because too few studies were identified and findings were inconsistent. Published by Elsevier Inc.

  1. Multiple social identities and stereotype threat: imbalance, accessibility, and working memory.

    PubMed

    Rydell, Robert J; McConnell, Allen R; Beilock, Sian L

    2009-05-01

    In 4 experiments, the authors showed that concurrently making positive and negative self-relevant stereotypes available about performance in the same ability domain can eliminate stereotype threat effects. Replicating past work, the authors demonstrated that introducing negative stereotypes about women's math performance activated participants' female social identity and hurt their math performance (i.e., stereotype threat) by reducing working memory. Moving beyond past work, it was also demonstrated that concomitantly presenting a positive self-relevant stereotype (e.g., college students are good at math) increased the relative accessibility of females' college student identity and inhibited their gender identity, eliminating attendant working memory deficits and contingent math performance decrements. Furthermore, subtle manipulations in questions presented in the demographic section of a math test eliminated stereotype threat effects that result from women reporting their gender before completing the test. This work identifies the motivated processes through which people's social identities became active in situations in which self-relevant stereotypes about a stigmatized group membership and a nonstigmatized group membership were available. In addition, it demonstrates the downstream consequences of this pattern of activation on working memory and performance. Copyright (c) 2009 APA, all rights reserved.

  2. Single-event effects in avionics

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Normand, E.

    1996-04-01

    The occurrence of single-event upset (SEU) in aircraft electronics has evolved from a series of interesting anecdotal incidents to accepted fact. A study completed in 1992 demonstrated that SEU`s are real, that the measured in-flight rates correlate with the atmospheric neutron flux, and that the rates can be calculated using laboratory SEU data. Once avionics DEU was shown to be an actual effect, it had to be dealt with in avionics designs. The major concern is in random access memories (RAM`s), both static (SRAM`s) and dynamic (DRAM`s), because these microelectronic devices contain the largest number of bits, but other parts,more » such as microprocessors, are also potentially susceptible to upset. In addition, other single-event effects (SEE`s), specifically latch-up and burnout, can also be induced by atmospheric neutrons.« less

  3. Random Access Memories: A New Paradigm for Target Detection in High Resolution Aerial Remote Sensing Images.

    PubMed

    Zou, Zhengxia; Shi, Zhenwei

    2018-03-01

    We propose a new paradigm for target detection in high resolution aerial remote sensing images under small target priors. Previous remote sensing target detection methods frame the detection as learning of detection model + inference of class-label and bounding-box coordinates. Instead, we formulate it from a Bayesian view that at inference stage, the detection model is adaptively updated to maximize its posterior that is determined by both training and observation. We call this paradigm "random access memories (RAM)." In this paradigm, "Memories" can be interpreted as any model distribution learned from training data and "random access" means accessing memories and randomly adjusting the model at detection phase to obtain better adaptivity to any unseen distribution of test data. By leveraging some latest detection techniques e.g., deep Convolutional Neural Networks and multi-scale anchors, experimental results on a public remote sensing target detection data set show our method outperforms several other state of the art methods. We also introduce a new data set "LEarning, VIsion and Remote sensing laboratory (LEVIR)", which is one order of magnitude larger than other data sets of this field. LEVIR consists of a large set of Google Earth images, with over 22 k images and 10 k independently labeled targets. RAM gives noticeable upgrade of accuracy (an mean average precision improvement of 1% ~ 4%) of our baseline detectors with acceptable computational overhead.

  4. Low-power resistive random access memory by confining the formation of conducting filaments

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Huang, Yi-Jen; Lee, Si-Chen, E-mail: sclee@ntu.edu.tw; Shen, Tzu-Hsien

    2016-06-15

    Owing to their small physical size and low power consumption, resistive random access memory (RRAM) devices are potential for future memory and logic applications in microelectronics. In this study, a new resistive switching material structure, TiO{sub x}/silver nanoparticles/TiO{sub x}/AlTiO{sub x}, fabricated between the fluorine-doped tin oxide bottom electrode and the indium tin oxide top electrode is demonstrated. The device exhibits excellent memory performances, such as low operation voltage (<±1 V), low operation power, small variation in resistance, reliable data retention, and a large memory window. The current-voltage measurement shows that the conducting mechanism in the device at the high resistancemore » state is via electron hopping between oxygen vacancies in the resistive switching material. When the device is switched to the low resistance state, conducting filaments are formed in the resistive switching material as a result of accumulation of oxygen vacancies. The bottom AlTiO{sub x} layer in the device structure limits the formation of conducting filaments; therefore, the current and power consumption of device operation are significantly reduced.« less

  5. Daily Access to Sucrose Impairs Aspects of Spatial Memory Tasks Reliant on Pattern Separation and Neural Proliferation in Rats

    ERIC Educational Resources Information Center

    Reichelt, Amy C.; Morris, Margaret J.; Westbrook, Reginald Frederick

    2016-01-01

    High sugar diets reduce hippocampal neurogenesis, which is required for minimizing interference between memories, a process that involves "pattern separation." We provided rats with 2 h daily access to a sucrose solution for 28 d and assessed their performance on a spatial memory task. Sucrose consuming rats discriminated between objects…

  6. Plastic Deformation and Failure Analysis of Phase Change Random Access Memory

    NASA Astrophysics Data System (ADS)

    Yang; Hongxin; Shi; Luping; Lee; Koon, Hock; Zhao; Rong; Li; Jianming; Lim; Guan, Kian; Chong; Chong, Tow

    2009-04-01

    Although lateral phase change random access memory (PCRAM) has attracted a lot of interest due to its simpler fabrication process and lower current compared to ovonic unified memory (OUM), it faces a problem of poor lifetime. This paper studied relation between plastic deformation and the failure of PCRAM through both experiment and simulation. OUM and lateral PCRAM incorporating Ge2Sb2Te5 were fabricated and tested. The overwriting test showed that lifetime of OUM exceeded 106 while that of lateral PCRAM was only about 100. Using atomic force microscopy (AFM), it was found that the plastic deformation after 106 overwriting reached several tens of nm for lateral PCRAM while it was negligible for OUM. The thermo-mechanical simulation results confirmed the similar results on larger plastic deformation of lateral PCRAM than that of OUM during overwriting. As plastic deformation involves of atomic bonds breaking and reforming in phase change material, the plastic deformation may be one main reason for the failure of lateral PCRAM.

  7. Elevated-Confined Phase-Change Random Access Memory Cells

    NASA Astrophysics Data System (ADS)

    Lee; Koon, Hock; Shi; Luping; Zhao; Rong; Yang; Hongxin; Lim; Guan, Kian; Li; Jianming; Chong; Chong, Tow

    2010-04-01

    A new elevated-confined phase-change random access memory (PCRAM) cell structure to reduce power consumption was proposed. In this proposed structure, the confined phase-change region is sitting on top of a small metal column enclosed by a dielectric at the sides. Hence, more heat can be effectively sustained underneath the phase-change region. As for the conventional structure, the confined phase-change region is sitting directly above a large planar bottom metal electrode, which can easily conduct most of the induced heat away. From simulations, a more uniform temperature profile around the active region and a higher peak temperature at the phase-change layer (PCL) in an elevated-confined structure were observed. Experimental results showed that the elevated-confined PCRAM cell requires a lower programming power and has a better scalability than a conventional confined PCRAM cell.

  8. Spectrotemporal processing drives fast access to memory traces for spoken words.

    PubMed

    Tavano, A; Grimm, S; Costa-Faidella, J; Slabu, L; Schröger, E; Escera, C

    2012-05-01

    The Mismatch Negativity (MMN) component of the event-related potentials is generated when a detectable spectrotemporal feature of the incoming sound does not match the sensory model set up by preceding repeated stimuli. MMN is enhanced at frontocentral scalp sites for deviant words when compared to acoustically similar deviant pseudowords, suggesting that automatic access to long-term memory traces for spoken words contributes to MMN generation. Does spectrotemporal feature matching also drive automatic lexical access? To test this, we recorded human auditory event-related potentials (ERPs) to disyllabic spoken words and pseudowords within a passive oddball paradigm. We first aimed at replicating the word-related MMN enhancement effect for Spanish, thereby adding to the available cross-linguistic evidence (e.g., Finnish, English). We then probed its resilience to spectrotemporal perturbation by inserting short (20 ms) and long (120 ms) silent gaps between first and second syllables of deviant and standard stimuli. A significantly enhanced, frontocentrally distributed MMN to deviant words was found for stimuli with no gap. The long gap yielded no deviant word MMN, showing that prior expectations of word form limits in a given language influence deviance detection processes. Crucially, the insertion of a short gap suppressed deviant word MMN enhancement at frontocentral sites. We propose that spectrotemporal point-wise matching constitutes a core mechanism for fast serial computations in audition and language, bridging sensory and long-term memory systems. Copyright © 2012 Elsevier Inc. All rights reserved.

  9. Encoding and retrieval processes involved in the access of source information in the absence of item memory.

    PubMed

    Ball, B Hunter; DeWitt, Michael R; Knight, Justin B; Hicks, Jason L

    2014-09-01

    The current study sought to examine the relative contributions of encoding and retrieval processes in accessing contextual information in the absence of item memory using an extralist cuing procedure in which the retrieval cues used to query memory for contextual information were related to the target item but never actually studied. In Experiments 1 and 2, participants studied 1 category member (e.g., onion) from a variety of different categories and at test were presented with an unstudied category label (e.g., vegetable) to probe memory for item and source information. In Experiments 3 and 4, 1 member of unidirectional (e.g., credit or card) or bidirectional (e.g., salt or pepper) associates was studied, whereas the other unstudied member served as a test probe. When recall failed, source information was accessible only when items were processed deeply during encoding (Experiments 1 and 2) and when there was strong forward associative strength between the retrieval cue and target (Experiments 3 and 4). These findings suggest that a retrieval probe diagnostic of semantically related item information reinstantiates information bound in memory during encoding that results in reactivation of associated contextual information, contingent upon sufficient learning of the item itself and the association between the item and its context information.

  10. Single Event Upset in Static Random Access Memories in Atmospheric Neutron Environments

    NASA Astrophysics Data System (ADS)

    Arita, Yutaka; Takai, Mikio; Ogawa, Izumi; Kishimoto, Tadafumi

    2003-07-01

    Single-event upsets (SEUs) in a 0.4 μm 4 Mbit complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) were investigated in various atmospheric neutron environments at sea level, at an altitude of 2612 m mountain, at an altitude of commercial airplane, and at an underground depth of 476 m. Neutron-induced SEUs increase with the increase in altitude. For a device with a borophosphosilicate glass (BPSG) film, SEU rates induced by thermal neutrons increase with the decrease in the cell charge of a memory cell. A thermal neutron-induced SEU is significant in SRAMs with a small cell charge. With the conditions of small cell charge, thermal neutron-induced SEUs account for 60% or more of the total neutron-induced SEUs. The SEU rate induced by atmospheric thermal neutrons can be estimated by an acceleration test using 252Cf.

  11. Memory for recently accessed visual attributes.

    PubMed

    Jiang, Yuhong V; Shupe, Joshua M; Swallow, Khena M; Tan, Deborah H

    2016-08-01

    Recent reports have suggested that the attended features of an item may be rapidly forgotten once they are no longer relevant for an ongoing task (attribute amnesia). This finding relies on a surprise memory procedure that places high demands on declarative memory. We used intertrial priming to examine whether the representation of an item's identity is lost completely once it becomes task irrelevant. If so, then the identity of a target on one trial should not influence performance on the next trial. In 3 experiments, we replicated the finding that a target's identity is poorly recognized in a surprise memory test. However, we also observed location and identity repetition priming across consecutive trials. These data suggest that, although explicit recognition on a surprise memory test may be impaired, some information about a particular target's identity can be retained after it is no longer needed for a task. (PsycINFO Database Record (c) 2016 APA, all rights reserved).

  12. Twin-bit via resistive random access memory in 16 nm FinFET logic technologies

    NASA Astrophysics Data System (ADS)

    Shih, Yi-Hong; Hsu, Meng-Yin; King, Ya-Chin; Lin, Chrong Jung

    2018-04-01

    A via resistive random access memory (RRAM) cell fully compatible with the standard CMOS logic process has been successfully demonstrated for high-density logic nonvolatile memory (NVM) modules in advanced FinFET circuits. In this new cell, the transition metal layers are formed on both sides of a via, given two storage bits per via. In addition to its compact cell area (1T + 14 nm × 32 nm), the twin-bit via RRAM cell features a low operation voltage, a large read window, good data retention, and excellent cycling capability. As fine alignments between mask layers become possible, the twin-bit via RRAM cell is expected to be highly scalable in advanced FinFET technology.

  13. Direct access inter-process shared memory

    DOEpatents

    Brightwell, Ronald B; Pedretti, Kevin; Hudson, Trammell B

    2013-10-22

    A technique for directly sharing physical memory between processes executing on processor cores is described. The technique includes loading a plurality of processes into the physical memory for execution on a corresponding plurality of processor cores sharing the physical memory. An address space is mapped to each of the processes by populating a first entry in a top level virtual address table for each of the processes. The address space of each of the processes is cross-mapped into each of the processes by populating one or more subsequent entries of the top level virtual address table with the first entry in the top level virtual address table from other processes.

  14. High-density magnetoresistive random access memory operating at ultralow voltage at room temperature.

    PubMed

    Hu, Jia-Mian; Li, Zheng; Chen, Long-Qing; Nan, Ce-Wen

    2011-11-22

    The main bottlenecks limiting the practical applications of current magnetoresistive random access memory (MRAM) technology are its low storage density and high writing energy consumption. Although a number of proposals have been reported for voltage-controlled memory device in recent years, none of them simultaneously satisfy the important device attributes: high storage capacity, low power consumption and room temperature operation. Here we present, using phase-field simulations, a simple and new pathway towards high-performance MRAMs that display significant improvements over existing MRAM technologies or proposed concepts. The proposed nanoscale MRAM device simultaneously exhibits ultrahigh storage capacity of up to 88 Gb inch(-2), ultralow power dissipation as low as 0.16 fJ per bit and room temperature high-speed operation below 10 ns.

  15. High-density magnetoresistive random access memory operating at ultralow voltage at room temperature

    PubMed Central

    Hu, Jia-Mian; Li, Zheng; Chen, Long-Qing; Nan, Ce-Wen

    2011-01-01

    The main bottlenecks limiting the practical applications of current magnetoresistive random access memory (MRAM) technology are its low storage density and high writing energy consumption. Although a number of proposals have been reported for voltage-controlled memory device in recent years, none of them simultaneously satisfy the important device attributes: high storage capacity, low power consumption and room temperature operation. Here we present, using phase-field simulations, a simple and new pathway towards high-performance MRAMs that display significant improvements over existing MRAM technologies or proposed concepts. The proposed nanoscale MRAM device simultaneously exhibits ultrahigh storage capacity of up to 88 Gb inch−2, ultralow power dissipation as low as 0.16 fJ per bit and room temperature high-speed operation below 10 ns. PMID:22109527

  16. Commercial host (dram shop) liability: current status and trends.

    PubMed

    Mosher, James F; Cohen, Elena N; Jernigan, David H

    2013-09-01

    Commercial host liability (CHL, also called dram shop liability) holds alcohol retailers liable for alcohol-attributable harm caused by serving alcohol, illegally, to a patron who is already intoxicated (adult liability) or underage (underage liability). The Community Preventive Services Task Force, based on a systematic research literature review, concluded that CHL is an effective strategy for reducing excessive alcohol consumption. The current article describes the key components of CHL, its grounding in American jurisprudence, its adoption in the 50 states, and changes since 1989, when a similar assessment of these policies was conducted. The current paper focuses on three legislatively enacted restrictions: (1) increased evidentiary requirements; (2) limitations on damage awards; and (3) limitations on who may be sued. Data were collected in 2011 and analyzed in 2012 and 2013. There has been substantial erosion of CHL during the past 2 decades. Fewer states recognized CHL in 2011 than in 1989, and more statutory restrictions were imposed during the study period among states that did recognize CHL; states are more likely to recognize underage than adult liability; and six states recognized a Responsible Beverage Services Practices affirmative defense in both 1989 and 2011. Implications of these findings for public health practitioners are discussed. Copyright © 2013 American Journal of Preventive Medicine. All rights reserved.

  17. Memory for Recently Accessed Visual Attributes

    ERIC Educational Resources Information Center

    Jiang, Yuhong V.; Shupe, Joshua M.; Swallow, Khena M.; Tan, Deborah H.

    2016-01-01

    Recent reports have suggested that the attended features of an item may be rapidly forgotten once they are no longer relevant for an ongoing task (attribute amnesia). This finding relies on a surprise memory procedure that places high demands on declarative memory. We used intertrial priming to examine whether the representation of an item's…

  18. The contribution to immediate serial recall of rehearsal, search speed, access to lexical memory, and phonological coding: an investigation at the construct level.

    PubMed

    Tehan, Gerald; Fogarty, Gerard; Ryan, Katherine

    2004-07-01

    Rehearsal speed has traditionally been seen to be the prime determinant of individual differences in memory span. Recent studies, in the main using young children as the participant population, have suggested other contributors to span performance. In the present research, we used structural equation modeling to explore, at the construct level, individual differences in immediate serial recall with respect to rehearsal, search, phonological coding, and speed of access to lexical memory. We replicated standard short-term phenomena; we showed that the variables that influence children's span performance influence adult performance in the same way; and we showed that speed of access to lexical memory and facility with phonological codes appear to be more potent sources of individual differences in immediate memory than is either rehearsal speed or search factors.

  19. Improved Writing-Conductor Designs For Magnetic Memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

    1994-01-01

    Writing currents reduced to practical levels. Improved conceptual designs for writing conductors in micromagnet/Hall-effect random-access integrated-circuit memory reduces electrical current needed to magnetize micromagnet in each memory cell. Basic concept of micromagnet/Hall-effect random-access memory presented in "Magnetic Analog Random-Access Memory" (NPO-17999).

  20. Nanoscale CuO solid-electrolyte-based conductive-bridging, random-access memory cell with a TiN liner

    NASA Astrophysics Data System (ADS)

    Lee, Jong-Sun; Kim, Dong-Won; Kim, Hea-Jee; Jin, Soo-Min; Song, Myung-Jin; Kwon, Ki-Hyun; Park, Jea-Gun; Jalalah, Mohammed; Al-Hajry, Ali

    2018-01-01

    The Conductive-bridge random-access memory (CBRAM) cell is a promising candidate for a terabit-level non-volatile memory due to its remarkable advantages. We present for the first time TiN as a diffusion barrier in CBRAM cells for enhancing their reliability. CuO solid-electrolyte-based CBRAM cells implemented with a 0.1-nm TiN liner demonstrated better non-volatile memory characteristics such as 106 AC write/erase endurance cycles with 100-μs AC pulse width and a long retention time of 7.4-years at 85 °C. In addition, the analysis of Ag diffusion in the CBRAM cell suggests that the morphology of the Ag filaments in the electrolyte can be effectively controlled by tuning the thickness of the TiN liner. These promising results pave the way for faster commercialization of terabit-level non-volatile memories.

  1. Temperature dependent characteristics of the random telegraph noise on contact resistive random access memory

    NASA Astrophysics Data System (ADS)

    Chang, Liang-Shun; Lin, Chrong Jung; King, Ya-Chin

    2014-01-01

    The temperature dependent characteristics of the random telegraphic noise (RTN) on contact resistive random access memory (CRRAM) are studied in this work. In addition to the bi-level switching, the occurrences of the middle states in the RTN signal are investigated. Based on the unique its temperature dependent characteristics, a new temperature sensing scheme is proposed for applications in ultra-low power sensor modules.

  2. Distributed multiport memory architecture

    NASA Technical Reports Server (NTRS)

    Kohl, W. H. (Inventor)

    1983-01-01

    A multiport memory architecture is diclosed for each of a plurality of task centers connected to a command and data bus. Each task center, includes a memory and a plurality of devices which request direct memory access as needed. The memory includes an internal data bus and an internal address bus to which the devices are connected, and direct timing and control logic comprised of a 10-state ring counter for allocating memory devices by enabling AND gates connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence. One device is a network bus adapter which serially shifts onto the command and data bus, a data word (8 bits plus control and parity bits) during the next ten direct memory access intervals after it has been granted access. The NBA is therefore allocated only one access in every ten intervals, which is a predetermined interval for all centers. The ring counters of all centers are periodically synchronized by DMA SYNC signal to assure that all NBAs be able to function in synchronism for data transfer from one center to another.

  3. Attentional priorities and access to short-term memory: parietal interactions.

    PubMed

    Gillebert, Céline R; Dyrholm, Mads; Vangkilde, Signe; Kyllingsbæk, Søren; Peeters, Ronald; Vandenberghe, Rik

    2012-09-01

    The intraparietal sulcus (IPS) has been implicated in selective attention as well as visual short-term memory (VSTM). To contrast mechanisms of target selection, distracter filtering, and access to VSTM, we combined behavioral testing, computational modeling and functional magnetic resonance imaging. Sixteen healthy subjects participated in a change detection task in which we manipulated both target and distracter set sizes. We directly compared the IPS response as a function of the number of targets and distracters in the display and in VSTM. When distracters were not present, the posterior and middle segments of IPS showed the predicted asymptotic activity increase with an increasing target set size. When distracters were added to a single target, activity also increased as predicted. However, the addition of distracters to multiple targets suppressed both middle and posterior IPS activities, thereby displaying a significant interaction between the two factors. The interaction between target and distracter set size in IPS could not be accounted for by a simple explanation in terms of number of items accessing VSTM. Instead, it led us to a model where items accessing VSTM receive differential weights depending on their behavioral relevance, and secondly, a suppressive effect originates during the selection phase when multiple targets and multiple distracters are simultaneously present. The reverse interaction between target and distracter set size was significant in the right temporoparietal junction (TPJ), where activity was highest for a single target compared to any other condition. Our study reconciles the role of middle IPS in attentional selection and biased competition with its role in VSTM access. Copyright © 2012 Elsevier Inc. All rights reserved.

  4. Response of the Ubiquitin-Proteasome System to Memory Retrieval After Extended-Access Cocaine or Saline Self-Administration.

    PubMed

    Werner, Craig T; Milovanovic, Mike; Christian, Daniel T; Loweth, Jessica A; Wolf, Marina E

    2015-12-01

    The ubiquitin-proteasome system (UPS) has been implicated in the retrieval-induced destabilization of cocaine- and fear-related memories in Pavlovian paradigms. However, nothing is known about its role in memory retrieval after self-administration of cocaine, an operant paradigm, or how the length of withdrawal from cocaine may influence retrieval mechanisms. Here, we examined UPS activity after an extended-access cocaine self-administration regimen that leads to withdrawal-dependent incubation of cue-induced cocaine craving. Controls self-administered saline. In initial experiments, memory retrieval was elicited via a cue-induced seeking/retrieval test on withdrawal day (WD) 50-60, when craving has incubated. We found that retrieval of cocaine- and saline-associated memories produced similar increases in polyubiquitinated proteins in the nucleus accumbens (NAc), compared with rats that did not undergo a seeking/retrieval test. Measures of proteasome catalytic activity confirmed similar activation of the UPS after retrieval of saline and cocaine memories. However, in a subsequent experiment in which testing was conducted on WD1, proteasome activity in the NAc was greater after retrieval of cocaine memory than saline memory. Analysis of other brain regions confirmed that effects of cocaine memory retrieval on proteasome activity, relative to saline memory retrieval, depend on withdrawal time. These results, combined with prior studies, suggest that the relationship between UPS activity and memory retrieval depends on training paradigm, brain region, and time elapsed between training and retrieval. The observation that mechanisms underlying cocaine memory retrieval change depending on the age of the memory has implications for development of memory destabilization therapies for cue-induced relapse in cocaine addicts.

  5. Optical mass memories

    NASA Technical Reports Server (NTRS)

    Bailey, G. A.

    1976-01-01

    Optical and magnetic variants in the design of trillion-bit read/write memories are compared and tabulated. Components and materials suitable for a random access read/write nonmoving memory system are examined, with preference given to holography and photoplastic materials. Advantages and deficiencies of photoplastics are reviewed. Holographic page composer design, essential features of an optical memory with no moving parts, fiche-oriented random access memory design, and materials suitable for an efficient photoplastic fiche are considered. The optical variants offer advantages in lower volume and weight at data transfer rates near 1 Mbit/sec, but power drain is of the same order as for the magnetic variants (tape memory, disk memory). The mechanical properties of photoplastic film materials still leave much to be desired.

  6. Processing and properties of Pb(Mg(1/3)Nb(2/3))O3--PbTiO3 thin films by pulsed laser deposition

    NASA Astrophysics Data System (ADS)

    Tantigate, C.; Lee, J.; Safari, A.

    1995-03-01

    The objectives of this study were to prepare in situ Pb(Mg(1/3)Nb(2/3))O3 (PMN) and PMN-PT thin films by pulsed laser deposition and to investigate the electrical features of thin films for possible dynamic random access memory (DRAM) and microactuator applications. The impact of processing parameters such compositions, substrate temperature, and oxygen pressure on perovskite phase formation and dielectric characteristics were reported. It was found that the highest dielectric constant, measured at room temperature and 10 kHz, was attained from the PMN with 99% perovskite.

  7. Parity of access to memory services in London for the BAME population: a cross-sectional study.

    PubMed

    Cook, Laura; Mukherjee, Sujoy; McLachlan, Tim; Shah, Rajendra; Livingston, Gill; Mukadam, Naaheed

    2018-03-12

    To investigate whether referrals to memory services in London reflect the ethnic diversity of the population. Memory service data including referral rates of BAME was collected from London Clinical Commissioning Groups (CCGs). The expected percentage of BAME referrals using census data was compared against White British population percentages using the chi squared test. We found that within 13,166 referrals to memory services across London, the percentage of people from BAME groups was higher than would be expected (20.3 versus 19.4%; χ 2 = 39.203, d.f. = 1, p < 0.0001) indicating that generally people from BAME groups are accessing memory services. Seventy-nine percent of memory services had more referrals than expected or no significant difference for all BAME groups. When there were fewer referrals then expected, the largest difference in percentage for an individual ethnic group was 3.3%. Results are encouraging and may indicate a significant improvement in awareness of dementia and help seeking behaviour among BAME populations. Prevalence of dementia in some ethnic groups may be higher so these numbers could still indicate under-referral. Due to the data available we were unable to compare disease severity or diagnosis type.

  8. Optical memories in digital computing

    NASA Technical Reports Server (NTRS)

    Alford, C. O.; Gaylord, T. K.

    1979-01-01

    High capacity optical memories with relatively-high data-transfer rate and multiport simultaneous access capability may serve as basis for new computer architectures. Several computer structures that might profitably use memories are: a) simultaneous record-access system, b) simultaneously-shared memory computer system, and c) parallel digital processing structure.

  9. Carbon nanomaterials for non-volatile memories

    NASA Astrophysics Data System (ADS)

    Ahn, Ethan C.; Wong, H.-S. Philip; Pop, Eric

    2018-03-01

    Carbon can create various low-dimensional nanostructures with remarkable electronic, optical, mechanical and thermal properties. These features make carbon nanomaterials especially interesting for next-generation memory and storage devices, such as resistive random access memory, phase-change memory, spin-transfer-torque magnetic random access memory and ferroelectric random access memory. Non-volatile memories greatly benefit from the use of carbon nanomaterials in terms of bit density and energy efficiency. In this Review, we discuss sp2-hybridized carbon-based low-dimensional nanostructures, such as fullerene, carbon nanotubes and graphene, in the context of non-volatile memory devices and architectures. Applications of carbon nanomaterials as memory electrodes, interfacial engineering layers, resistive-switching media, and scalable, high-performance memory selectors are investigated. Finally, we compare the different memory technologies in terms of writing energy and time, and highlight major challenges in the manufacturing, integration and understanding of the physical mechanisms and material properties.

  10. A Compute Capable SSD Architecture for Next-Generation Non-volatile Memories

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    De, Arup

    2014-01-01

    Existing storage technologies (e.g., disks and ash) are failing to cope with the processor and main memory speed and are limiting the overall perfor- mance of many large scale I/O or data-intensive applications. Emerging fast byte-addressable non-volatile memory (NVM) technologies, such as phase-change memory (PCM), spin-transfer torque memory (STTM) and memristor are very promising and are approaching DRAM-like performance with lower power con- sumption and higher density as process technology scales. These new memories are narrowing down the performance gap between the storage and the main mem- ory and are putting forward challenging problems on existing SSD architecture, I/O interfacemore » (e.g, SATA, PCIe) and software. This dissertation addresses those challenges and presents a novel SSD architecture called XSSD. XSSD o oads com- putation in storage to exploit fast NVMs and reduce the redundant data tra c across the I/O bus. XSSD o ers a exible RPC-based programming framework that developers can use for application development on SSD without dealing with the complication of the underlying architecture and communication management. We have built a prototype of XSSD on the BEE3 FPGA prototyping system. We implement various data-intensive applications and achieve speedup and energy ef- ciency of 1.5-8.9 and 1.7-10.27 respectively. This dissertation also compares XSSD with previous work on intelligent storage and intelligent memory. The existing ecosystem and these new enabling technologies make this system more viable than earlier ones.« less

  11. Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator

    NASA Astrophysics Data System (ADS)

    Nishikata, Daisuke; Ali, Mohammad Alimudin Bin Mohd; Hosoda, Kento; Matsumoto, Hiroshi; Nakamura, Kazuyuki

    2018-04-01

    A 36-bit × 32-entry fully digital ternary content addressable memory (TCAM) using the ratioless static random access memory (RL-SRAM) technology and fully complementary hierarchical-AND matching comparators (HAMCs) was developed. Since its fully complementary and digital operation enables the effect of device variabilities to be avoided, it can operate with a quite low supply voltage. A test chip incorporating a conventional TCAM and a proposed 24-transistor ratioless TCAM (RL-TCAM) cells and HAMCs was developed using a 0.18 µm CMOS process. The minimum operating voltage of 0.25 V of the developed RL-TCAM, which is less than half of that of the conventional TCAM, was measured via the conventional CMOS push–pull output buffers with the level-shifting and flipping technique using optimized pull-up voltage and resistors.

  12. Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 5, Appendix D

    NASA Technical Reports Server (NTRS)

    Klute, A.

    1979-01-01

    The electrical characterization and qualification test results are presented for the RCA MWS 5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. Average input high current, worst case input high current, output low current, and data setup time are some of the results presented.

  13. Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 4, Appendix C

    NASA Technical Reports Server (NTRS)

    Klute, A.

    1979-01-01

    The electrical characterization and qualification test results are presented for the RCA MWS5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. Statistical analysis data is supplied along with write pulse width, read cycle time, write cycle time, and chip enable time data.

  14. Accessing long-term memory representations during visual change detection.

    PubMed

    Beck, Melissa R; van Lamsweerde, Amanda E

    2011-04-01

    In visual change detection tasks, providing a cue to the change location concurrent with the test image (post-cue) can improve performance, suggesting that, without a cue, not all encoded representations are automatically accessed. Our studies examined the possibility that post-cues can encourage the retrieval of representations stored in long-term memory (LTM). Participants detected changes in images composed of familiar objects. Performance was better when the cue directed attention to the post-change object. Supporting the role of LTM in the cue effect, the effect was similar regardless of whether the cue was presented during the inter-stimulus interval, concurrent with the onset of the test image, or after the onset of the test image. Furthermore, the post-cue effect and LTM performance were similarly influenced by encoding time. These findings demonstrate that monitoring the visual world for changes does not automatically engage LTM retrieval.

  15. Influence of ultraviolet irradiation on data retention characteristics in resistive random access memory

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Kimura, K.; Ohmi, K.; Tottori University Electronic Display Research Center, 101 Minami4-chome, Koyama-cho, Tottori-shi, Tottori 680-8551

    With increasing density of memory devices, the issue of generating soft errors by cosmic rays is becoming more and more serious. Therefore, the irradiation resistance of resistance random access memory (ReRAM) to cosmic radiation has to be elucidated for practical use. In this paper, we investigated the data retention characteristics of ReRAM against ultraviolet irradiation with a Pt/NiO/ITO structure. Soft errors were confirmed to be caused by ultraviolet irradiation in both low- and high-resistance states. An analysis of the wavelength dependence of light irradiation on data retention characteristics suggested that electronic excitation from the valence to the conduction band andmore » to the energy level generated due to the introduction of oxygen vacancies caused the errors. Based on a statistically estimated soft error rates, the errors were suggested to be caused by the cohesion and dispersion of oxygen vacancies owing to the generation of electron-hole pairs and valence changes by the ultraviolet irradiation.« less

  16. Nonvolatile reconfigurable sequential logic in a HfO2 resistive random access memory array.

    PubMed

    Zhou, Ya-Xiong; Li, Yi; Su, Yu-Ting; Wang, Zhuo-Rui; Shih, Ling-Yi; Chang, Ting-Chang; Chang, Kuan-Chang; Long, Shi-Bing; Sze, Simon M; Miao, Xiang-Shui

    2017-05-25

    Resistive random access memory (RRAM) based reconfigurable logic provides a temporal programmable dimension to realize Boolean logic functions and is regarded as a promising route to build non-von Neumann computing architecture. In this work, a reconfigurable operation method is proposed to perform nonvolatile sequential logic in a HfO 2 -based RRAM array. Eight kinds of Boolean logic functions can be implemented within the same hardware fabrics. During the logic computing processes, the RRAM devices in an array are flexibly configured in a bipolar or complementary structure. The validity was demonstrated by experimentally implemented NAND and XOR logic functions and a theoretically designed 1-bit full adder. With the trade-off between temporal and spatial computing complexity, our method makes better use of limited computing resources, thus provides an attractive scheme for the construction of logic-in-memory systems.

  17. Enhancement of Speed Margins for 16× Digital Versatile Disc-Random Access Memory

    NASA Astrophysics Data System (ADS)

    Watanabe, Koichi; Minemura, Hiroyuki; Miyamoto, Makoto; Iimura, Makoto

    2006-02-01

    We have evaluated the speed margins of write/read 16× digital versatile disc-random access memory (DVD-RAM) test discs using write strategies for 6--16× constant angular velocity (CAV) control. Our approach is to determine the writing parameters for the middle zones by interpolating the zone numbers. Using this interpolation strategy, we successfully obtained overwrite jitter values of less than 8% and bit error rates of less than 10-5 in 6--16× DVD-RAM. Moreover, we confirmed that the speed margins were ± 20% for a 6--16× CAV.

  18. Tuning resistance states by thickness control in an electroforming-free nanometallic complementary resistance random access memory

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Yang, Xiang; Lu, Yang; Lee, Jongho

    2016-01-04

    Tuning low resistance state is crucial for resistance random access memory (RRAM) that aims to achieve optimal read margin and design flexibility. By back-to-back stacking two nanometallic bipolar RRAMs with different thickness into a complementary structure, we have found that its low resistance can be reliably tuned over several orders of magnitude. Such high tunability originates from the exponential thickness dependence of the high resistance state of nanometallic RRAM, in which electron wave localization in a random network gives rise to the unique scaling behavior. The complementary nanometallic RRAM provides electroforming-free, multi-resistance-state, sub-100 ns switching capability with advantageous characteristics formore » memory arrays.« less

  19. Hydrogen doping in HfO{sub 2} resistance change random access memory

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Duncan, D.; Magyari-Köpe, B.; Nishi, Y.

    2016-01-25

    The structures and energies of hydrogen-doped monoclinic hafnium dioxide were calculated using density-functional theory. The electronic interactions are described within the LDA + U formalism, where on-site Coulomb corrections are applied to the 5d orbital electrons of Hf atoms and 2p orbital electrons of the O atoms. The effects of charge state, defect-defect interactions, and hydrogenation are investigated and compared with experiment. It is found that hydrogenation of HfO{sub 2} resistance-change random access memory devices energetically stabilizes the formation of oxygen vacancies and conductive vacancy filaments through multiple mechanisms, leading to improved switching characteristic and device yield.

  20. Random access memory immune to single event upset using a T-resistor

    DOEpatents

    Ochoa, Jr., Agustin

    1989-01-01

    In a random access memory cell, a resistance "T" decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell.

  1. Evaluation of Data Retention Characteristics for Ferroelectric Random Access Memories (FRAMs)

    NASA Technical Reports Server (NTRS)

    Sharma, Ashok K.; Teverovsky, Alexander

    2001-01-01

    Data retention and fatigue characteristics of 64 Kb lead zirconate titanate (PZT)-based Ferroelectric Random Access Memories (FRAMs) microcircuits manufactured by Ramtron were examined over temperature range from -85 C to +310 C for ceramic packaged parts and from -85 C to +175 C for plastic parts, during retention periods up to several thousand hours. Intrinsic failures, which were caused by a thermal degradation of the ferroelectric cells, occurred in ceramic parts after tens or hundreds hours of aging at temperatures above 200 C. The activation energy of the retention test failures was 1.05 eV and the extrapolated mean-time-to-failure (MTTF) at room temperature was estimated to be more than 280 years. Multiple write-read cycling (up to 3x10(exp 7)) during the fatigue testing of plastic and ceramic parts did not result in any parametric or functional failures. However, operational currents linearly decreased with the logarithm of number of cycles thus indicating fatigue process in PZT films. Plastic parts, that had more recent date code as compared to ceramic parts, appeared to be using die with improved process technology and showed significantly smaller changes in operational currents and data access times.

  2. Autophagy is induced through the ROS-TP53-DRAM1 pathway in response to mitochondrial protein synthesis inhibition.

    PubMed

    Xie, Xiaolei; Le, Li; Fan, Yanxin; Lv, Lin; Zhang, Junjie

    2012-07-01

    Mitoribosome in mammalian cells is responsible for synthesis of 13 mtDNA-encoded proteins, which are integral parts of four mitochondrial respiratory chain complexes (I, III, IV and V). ERAL1 is a nuclear-encoded GTPase important for the formation of the 28S small mitoribosomal subunit. Here, we demonstrate that knockdown of ERAL1 by RNA interference inhibits mitochondrial protein synthesis and promotes reactive oxygen species (ROS) generation, leading to autophagic vacuolization in HeLa cells. Cells that lack ERAL1 expression showed a significant conversion of LC3-I to LC3-II and an enhanced accumulation of autophagic vacuoles carrying the LC3 marker, all of which were blocked by the autophagy inhibitor 3-MA as well as by the ROS scavenger NAC. Inhibition of mitochondrial protein synthesis either by ERAL1 siRNA or chloramphenicol (CAP), a specific inhibitor of mitoribosomes, induced autophagy in HTC-116 TP53 (+/+) cells, but not in HTC-116 TP53 (-/-) cells, indicating that tumor protein 53 (TP53) is essential for the autophagy induction. The ROS elevation resulting from mitochondrial protein synthesis inhibition induced TP53 expression at transcriptional levels by enhancing TP53 promoter activity, and increased TP53 protein stability by suppressing TP53 ubiquitination through MAPK14/p38 MAPK-mediated TP53 phosphorylation. Upregulation of TP53 and its downstream target gene DRAM1, but not CDKN1A/p21, was required for the autophagy induction in ERAL1 siRNA or CAP-treated cells. Altogether, these data indicate that autophagy is induced through the ROS-TP53-DRAM1 pathway in response to mitochondrial protein synthesis inhibition.

  3. High density submicron magnetoresistive random access memory (invited)

    NASA Astrophysics Data System (ADS)

    Tehrani, S.; Chen, E.; Durlam, M.; DeHerrera, M.; Slaughter, J. M.; Shi, J.; Kerszykowski, G.

    1999-04-01

    Various giant magnetoresistance material structures were patterned and studied for their potential as memory elements. The preferred memory element, based on pseudo-spin valve structures, was designed with two magnetic stacks (NiFeCo/CoFe) of different thickness with Cu as an interlayer. The difference in thickness results in dissimilar switching fields due to the shape anisotropy at deep submicron dimensions. It was found that a lower switching current can be achieved when the bits have a word line that wraps around the bit 1.5 times. Submicron memory elements integrated with complementary metal-oxide-semiconductor (CMOS) transistors maintained their characteristics and no degradation to the CMOS devices was observed. Selectivity between memory elements in high-density arrays was demonstrated.

  4. Selective memory retrieval can impair and improve retrieval of other memories.

    PubMed

    Bäuml, Karl-Heinz T; Samenieh, Anuscheh

    2012-03-01

    Research from the past decades has shown that retrieval of a specific memory (e.g., retrieving part of a previous vacation) typically attenuates retrieval of other memories (e.g., memories for other details of the event), causing retrieval-induced forgetting. More recently, however, it has been shown that retrieval can both attenuate and aid recall of other memories (K.-H. T. Bäuml & A. Samenieh, 2010). To identify the circumstances under which retrieval aids recall, the authors examined retrieval dynamics in listwise directed forgetting, context-dependent forgetting, proactive interference, and in the absence of any induced memory impairment. They found beneficial effects of selective retrieval in listwise directed forgetting and context-dependent forgetting but detrimental effects in all the other conditions. Because context-dependent forgetting and listwise directed forgetting arguably reflect impaired context access, the results suggest that memory retrieval aids recall of memories that are subject to impaired context access but attenuates recall in the absence of such circumstances. The findings are consistent with a 2-factor account of memory retrieval and suggest the existence of 2 faces of memory retrieval. 2012 APA, all rights reserved

  5. Multiple core computer processor with globally-accessible local memories

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Shalf, John; Donofrio, David; Oliker, Leonid

    A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality ofmore » processor cores.« less

  6. Low power consumption resistance random access memory with Pt/InOx/TiN structure

    NASA Astrophysics Data System (ADS)

    Yang, Jyun-Bao; Chang, Ting-Chang; Huang, Jheng-Jie; Chen, Yu-Ting; Tseng, Hsueh-Chih; Chu, Ann-Kuo; Sze, Simon M.; Tsai, Ming-Jinn

    2013-09-01

    In this study, the resistance switching characteristics of a resistive random access memory device with Pt/InOx/TiN structure is investigated. Unstable bipolar switching behavior is observed during the initial switching cycle, which then stabilizes after several switching cycles. Analyses indicate that the current conduction mechanism in the resistance state is dominated by Ohmic conduction. The decrease in electrical conductance can be attributed to the reduction of the cross-sectional area of the conduction path. Furthermore, the device exhibits low operation voltage and power consumption.

  7. DESTINY

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    2015-03-10

    DESTINY is a comprehensive tool for modeling 3D and 2D cache designs using SRAM,embedded DRAM (eDRAM), spin transfer torque RAM (STT-RAM), resistive RAM (ReRAM), and phase change RAM (PCN). In its purpose, it is similar to CACTI, CACTI-3DD or NVSim. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g. latency, area or energy-delay product) for agiven memory technology, choosing the suitable memory technology or fabrication method (i.e. 2D v/s 3D) for a given optimization target, etc. DESTINY has been validated against several cache prototypes. DESTINY is expected to boost studies ofmore » next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers.« less

  8. Development of Next Generation Memory Test Experiment for Deployment on a Small Satellite

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd; Ho, Fat D.

    2012-01-01

    The original Memory Test Experiment successfully flew on the FASTSAT satellite launched in November 2010. It contained a single Ramtron 512K ferroelectric memory. The memory device went through many thousands of read/write cycles and recorded any errors that were encountered. The original mission length was schedule to last 6 months but was extended to 18 months. New opportunities exist to launch a similar satellite and considerations for a new memory test experiment should be examined. The original experiment had to be designed and integrated in less than two months, so the experiment was a simple design using readily available parts. The follow-on experiment needs to be more sophisticated and encompass more technologies. This paper lays out the considerations for the design and development of this follow-on flight memory experiment. It also details the results from the original Memory Test Experiment that flew on board FASTSAT. Some of the design considerations for the new experiment include the number and type of memory devices to be used, the kinds of tests that will be performed, other data needed to analyze the results, and best use of limited resources on a small satellite. The memory technologies that are considered are FRAM, FLASH, SONOS, Resistive Memory, Phase Change Memory, Nano-wire Memory, Magneto-resistive Memory, Standard DRAM, and Standard SRAM. The kinds of tests that could be performed are read/write operations, non-volatile memory retention, write cycle endurance, power measurements, and testing Error Detection and Correction schemes. Other data that may help analyze the results are GPS location of recorded errors, time stamp of all data recorded, radiation measurements, temperature, and other activities being perform by the satellite. The resources of power, volume, mass, temperature, processing power, and telemetry bandwidth are extremely limited on a small satellite. Design considerations must be made to allow the experiment to not interfere

  9. 76 FR 45295 - In the Matter of Certain Static Random Access Memories and Products Containing Same; Notice of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-07-28

    ... supplementing the amended complaint was filed on June 28, 2011. A second amended complaint was filed on July 13... of certain static random access memories and products containing same by reason of infringement of... 13 of the `937 patent, and whether an industry in the United States exists as required by subsection...

  10. High speed magneto-resistive random access memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor); Katti, Romney R. (Inventor)

    1992-01-01

    A high speed read MRAM memory element is configured from a sandwich of magnetizable, ferromagnetic film surrounding a magneto-resistive film which may be ferromagnetic or not. One outer ferromagnetic film has a higher coercive force than the other and therefore remains magnetized in one sense while the other may be switched in sense by a switching magnetic field. The magneto-resistive film is therefore sensitive to the amplitude of the resultant field between the outer ferromagnetic films and may be constructed of a high resistivity, high magneto-resistive material capable of higher sensing currents. This permits higher read voltages and therefore faster read operations. Alternate embodiments with perpendicular anisotropy, and in-plane anisotropy are shown, including an embodiment which uses high permeability guides to direct the closing flux path through the magneto-resistive material. High density, high speed, radiation hard, memory matrices may be constructed from these memory elements.

  11. Bubble memory module for spacecraft application

    NASA Technical Reports Server (NTRS)

    Hayes, P. J.; Looney, K. T.; Nichols, C. D.

    1985-01-01

    Bubble domain technology offers an all-solid-state alternative for data storage in onboard data systems. A versatile modular bubble memory concept was developed. The key module is the bubble memory module which contains all of the storage devices and circuitry for accessing these devices. This report documents the bubble memory module design and preliminary hardware designs aimed at memory module functional demonstration with available commercial bubble devices. The system architecture provides simultaneous operation of bubble devices to attain high data rates. Banks of bubble devices are accessed by a given bubble controller to minimize controller parts. A power strobing technique is discussed which could minimize the average system power dissipation. A fast initialization method using EEPROM (electrically erasable, programmable read-only memory) devices promotes fast access. Noise and crosstalk problems and implementations to minimize these are discussed. Flight memory systems which incorporate the concepts and techniques of this work could now be developed for applications.

  12. A random access memory immune to single event upset using a T-Resistor

    DOEpatents

    Ochoa, A. Jr.

    1987-10-28

    In a random access memory cell, a resistance ''T'' decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell. 4 figs.

  13. Gilgamesh: A Multithreaded Processor-In-Memory Architecture for Petaflops Computing

    NASA Technical Reports Server (NTRS)

    Sterling, T. L.; Zima, H. P.

    2002-01-01

    Processor-in-Memory (PIM) architectures avoid the von Neumann bottleneck in conventional machines by integrating high-density DRAM and CMOS logic on the same chip. Parallel systems based on this new technology are expected to provide higher scalability, adaptability, robustness, fault tolerance and lower power consumption than current MPPs or commodity clusters. In this paper we describe the design of Gilgamesh, a PIM-based massively parallel architecture, and elements of its execution model. Gilgamesh extends existing PIM capabilities by incorporating advanced mechanisms for virtualizing tasks and data and providing adaptive resource management for load balancing and latency tolerance. The Gilgamesh execution model is based on macroservers, a middleware layer which supports object-based runtime management of data and threads allowing explicit and dynamic control of locality and load balancing. The paper concludes with a discussion of related research activities and an outlook to future work.

  14. Episodic memories.

    PubMed

    Conway, Martin A

    2009-09-01

    An account of episodic memories is developed that focuses on the types of knowledge they represent, their properties, and the functions they might serve. It is proposed that episodic memories consist of episodic elements, summary records of experience often in the form of visual images, associated to a conceptual frame that provides a conceptual context. Episodic memories are embedded in a more complex conceptual system in which they can become the basis of autobiographical memories. However, the function of episodic memories is to keep a record of progress with short-term goals and access to most episodic memories is lost soon after their formation. Finally, it is suggested that developmentally episodic memories form the basis of the conceptual system and it is from sets of episodic memories that early non-verbal conceptual knowledge is abstracted.

  15. Soft-error tolerance and energy consumption evaluation of embedded computer with magnetic random access memory in practical systems using computer simulations

    NASA Astrophysics Data System (ADS)

    Nebashi, Ryusuke; Sakimura, Noboru; Sugibayashi, Tadahiko

    2017-08-01

    We evaluated the soft-error tolerance and energy consumption of an embedded computer with magnetic random access memory (MRAM) using two computer simulators. One is a central processing unit (CPU) simulator of a typical embedded computer system. We simulated the radiation-induced single-event-upset (SEU) probability in a spin-transfer-torque MRAM cell and also the failure rate of a typical embedded computer due to its main memory SEU error. The other is a delay tolerant network (DTN) system simulator. It simulates the power dissipation of wireless sensor network nodes of the system using a revised CPU simulator and a network simulator. We demonstrated that the SEU effect on the embedded computer with 1 Gbit MRAM-based working memory is less than 1 failure in time (FIT). We also demonstrated that the energy consumption of the DTN sensor node with MRAM-based working memory can be reduced to 1/11. These results indicate that MRAM-based working memory enhances the disaster tolerance of embedded computers.

  16. Set statistics in conductive bridge random access memory device with Cu/HfO{sub 2}/Pt structure

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Zhang, Meiyun; Long, Shibing, E-mail: longshibing@ime.ac.cn; Wang, Guoming

    2014-11-10

    The switching parameter variation of resistive switching memory is one of the most important challenges in its application. In this letter, we have studied the set statistics of conductive bridge random access memory with a Cu/HfO{sub 2}/Pt structure. The experimental distributions of the set parameters in several off resistance ranges are shown to nicely fit a Weibull model. The Weibull slopes of the set voltage and current increase and decrease logarithmically with off resistance, respectively. This experimental behavior is perfectly captured by a Monte Carlo simulator based on the cell-based set voltage statistics model and the Quantum Point Contact electronmore » transport model. Our work provides indications for the improvement of the switching uniformity.« less

  17. Access to Attitude-Relevant Information in Memory as a Determinant of Persuasion: The Role of Message and Communicator Attributes.

    ERIC Educational Resources Information Center

    Wood, Wendy; And Others

    Research literature shows that people with access to attitude-relevant information in memory are able to draw on relevant beliefs and prior experiences when analyzing a persuasive message. This suggests that people who can retrieve little attitude-relevant information should be less able to engage in systematic processing. Two experiments were…

  18. Affect, accessibility of material in memory, and behavior: a cognitive loop?

    PubMed

    Isen, A M; Shalker, T E; Clark, M; Karp, L

    1978-01-01

    Two studies investigated the effect of good mood on cognitive processes. In the first study, conducted in a shopping mall, a positive feeling state was induced by giving subjects a free gift, and good mood, thus induced, was found to improve subjects' evaluations of the performance and service records of products they owned. In the second study, in which affect was induced by having subjects win or lose a computer game in a laboratory setting, subjects who had won the game were found to be better able to recall positive material in memory. The results of the two studies are discussed in terms of the effect that feelings have on accessibility of cognitions. In addition, the nature of affect and the relationship between good mood and behavior (such as helping) are discussed in terms of this proposed cognitive process.

  19. Stream specificity and asymmetries in feature binding and content-addressable access in visual encoding and memory.

    PubMed

    Huynh, Duong L; Tripathy, Srimant P; Bedell, Harold E; Ögmen, Haluk

    2015-01-01

    Human memory is content addressable-i.e., contents of the memory can be accessed using partial information about the bound features of a stored item. In this study, we used a cross-feature cuing technique to examine how the human visual system encodes, binds, and retains information about multiple stimulus features within a set of moving objects. We sought to characterize the roles of three different features (position, color, and direction of motion, the latter two of which are processed preferentially within the ventral and dorsal visual streams, respectively) in the construction and maintenance of object representations. We investigated the extent to which these features are bound together across the following processing stages: during stimulus encoding, sensory (iconic) memory, and visual short-term memory. Whereas all features examined here can serve as cues for addressing content, their effectiveness shows asymmetries and varies according to cue-report pairings and the stage of information processing and storage. Position-based indexing theories predict that position should be more effective as a cue compared to other features. While we found a privileged role for position as a cue at the stimulus-encoding stage, position was not the privileged cue at the sensory and visual short-term memory stages. Instead, the pattern that emerged from our findings is one that mirrors the parallel processing streams in the visual system. This stream-specific binding and cuing effectiveness manifests itself in all three stages of information processing examined here. Finally, we find that the Leaky Flask model proposed in our previous study is applicable to all three features.

  20. On Using the Volatile Mem-Capacitive Effect of TiO2 Resistive Random Access Memory to Mimic the Synaptic Forgetting Process

    NASA Astrophysics Data System (ADS)

    Sarkar, Biplab; Mills, Steven; Lee, Bongmook; Pitts, W. Shepherd; Misra, Veena; Franzon, Paul D.

    2018-02-01

    In this work, we report on mimicking the synaptic forgetting process using the volatile mem-capacitive effect of a resistive random access memory (RRAM). TiO2 dielectric, which is known to show volatile memory operations due to migration of inherent oxygen vacancies, was used to achieve the volatile mem-capacitive effect. By placing the volatile RRAM candidate along with SiO2 at the gate of a MOS capacitor, a volatile capacitance change resembling the forgetting nature of a human brain is demonstrated. Furthermore, the memory operation in the MOS capacitor does not require a current flow through the gate dielectric indicating the feasibility of obtaining low power memory operations. Thus, the mem-capacitive effect of volatile RRAM candidates can be attractive to the future neuromorphic systems for implementing the forgetting process of a human brain.

  1. Working memory at work: how the updating process alters the nature of working memory transfer.

    PubMed

    Zhang, Yanmin; Verhaeghen, Paul; Cerella, John

    2012-01-01

    In three N-Back experiments, we investigated components of the process of working memory (WM) updating, more specifically access to items stored outside the focus of attention and transfer from the focus to the region of WM outside the focus. We used stimulus complexity as a marker. We found that when WM transfer occurred under full attention, it was slow and highly sensitive to stimulus complexity, much more so than WM access. When transfer occurred in conjunction with access, however, it was fast and no longer sensitive to stimulus complexity. Thus the updating context altered the nature of WM processing: The dual-task situation (transfer in conjunction with access) drove memory transfer into a more efficient mode, indifferent to stimulus complexity. In contrast, access times consistently increased with complexity, unaffected by the processing context. This study reinforces recent reports that retrieval is a (perhaps the) key component of working memory functioning. Copyright © 2011 Elsevier B.V. All rights reserved.

  2. Working Memory at Work: How the Updating Process Alters the Nature of Working Memory Transfer

    PubMed Central

    Zhang, Yanmin; Verhaeghen, Paul; Cerella, John

    2011-01-01

    In three N-Back experiments, we investigated components of the process of working memory (WM) updating, more specifically access to items stored outside the focus of attention and transfer from the focus to the region of WM outside the focus. We used stimulus complexity as a marker. We found that when WM transfer occurred under full attention, it was slow and highly sensitive to stimulus complexity, much more so than WM access. When transfer occurred in conjunction with access, however, it was fast and no longer sensitive to stimulus complexity. Thus the updating context altered the nature of WM processing: The dual-task situation (transfer in conjunction with access) drove memory transfer into a more efficient mode, indifferent to stimulus complexity. In contrast, access times consistently increased with complexity, unaffected by the processing context. This study reinforces recent reports that retrieval is a (perhaps the) key component of working memory functioning. PMID:22105718

  3. Optoelectronic-cache memory system architecture.

    PubMed

    Chiarulli, D M; Levitan, S P

    1996-05-10

    We present an investigation of the architecture of an optoelectronic cache that can integrate terabit optical memories with the electronic caches associated with high-performance uniprocessors and multiprocessors. The use of optoelectronic-cache memories enables these terabit technologies to provide transparently low-latency secondary memory with frame sizes comparable with disk pages but with latencies that approach those of electronic secondary-cache memories. This enables the implementation of terabit memories with effective access times comparable with the cycle times of current microprocessors. The cache design is based on the use of a smart-pixel array and combines parallel free-space optical input-output to-and-from optical memory with conventional electronic communication to the processor caches. This cache and the optical memory system to which it will interface provide a large random-access memory space that has a lower overall latency than that of magnetic disks and disk arrays. In addition, as a consequence of the high-bandwidth parallel input-output capabilities of optical memories, fault service times for the optoelectronic cache are substantially less than those currently achievable with any rotational media.

  4. One bipolar transistor selector - One resistive random access memory device for cross bar memory array

    NASA Astrophysics Data System (ADS)

    Aluguri, R.; Kumar, D.; Simanjuntak, F. M.; Tseng, T.-Y.

    2017-09-01

    A bipolar transistor selector was connected in series with a resistive switching memory device to study its memory characteristics for its application in cross bar array memory. The metal oxide based p-n-p bipolar transistor selector indicated good selectivity of about 104 with high retention and long endurance showing its usefulness in cross bar RRAM devices. Zener tunneling is found to be the main conduction phenomena for obtaining high selectivity. 1BT-1R device demonstrated good memory characteristics with non-linearity of 2 orders, selectivity of about 2 orders and long retention characteristics of more than 105 sec. One bit-line pull-up scheme shows that a 650 kb cross bar array made with this 1BT1R devices works well with more than 10 % read margin proving its ability in future memory technology application.

  5. Dual representation of item positions in verbal short-term memory: Evidence for two access modes.

    PubMed

    Lange, Elke B; Verhaeghen, Paul; Cerella, John

    Memory sets of N = 1~5 digits were exposed sequentially from left-to-right across the screen, followed by N recognition probes. Probes had to be compared to memory list items on identity only (Sternberg task) or conditional on list position. Positions were probed randomly or in left-to-right order. Search functions related probe response times to set size. Random probing led to ramped, "Sternbergian" functions whose intercepts were elevated by the location requirement. Sequential probing led to flat search functions-fast responses unaffected by set size. These results suggested that items in STM could be accessed either by a slow search-on-identity followed by recovery of an associated location tag, or in a single step by following item-to-item links in study order. It is argued that this dual coding of location information occurs spontaneously at study, and that either code can be utilised at retrieval depending on test demands.

  6. An amorphous titanium dioxide metal insulator metal selector device for resistive random access memory crossbar arrays with tunable voltage margin

    NASA Astrophysics Data System (ADS)

    Cortese, Simone; Khiat, Ali; Carta, Daniela; Light, Mark E.; Prodromakis, Themistoklis

    2016-01-01

    Resistive random access memory (ReRAM) crossbar arrays have become one of the most promising candidates for next-generation non volatile memories. To become a mature technology, the sneak path current issue must be solved without compromising all the advantages that crossbars offer in terms of electrical performances and fabrication complexity. Here, we present a highly integrable access device based on nickel and sub-stoichiometric amorphous titanium dioxide (TiO2-x), in a metal insulator metal crossbar structure. The high voltage margin of 3 V, amongst the highest reported for monolayer selector devices, and the good current density of 104 A/cm2 make it suitable to sustain ReRAM read and write operations, effectively tackling sneak currents in crossbars without compromising fabrication complexity in a 1 Selector 1 Resistor (1S1R) architecture. Furthermore, the voltage margin is found to be tunable by an annealing step without affecting the device's characteristics.

  7. Efficient Memory Access with NumPy Global Arrays using Local Memory Access

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Daily, Jeffrey A.; Berghofer, Dan C.

    This paper discusses the work completed working with Global Arrays of data on distributed multi-computer systems and improving their performance. The tasks completed were done at Pacific Northwest National Laboratory in the Science Undergrad Laboratory Internship program in the summer of 2013 for the Data Intensive Computing Group in the Fundamental and Computational Sciences DIrectorate. This work was done on the Global Arrays Toolkit developed by this group. This toolkit is an interface for programmers to more easily create arrays of data on networks of computers. This is useful because scientific computation is often done on large amounts of datamore » sometimes so large that individual computers cannot hold all of it. This data is held in array form and can best be processed on supercomputers which often consist of a network of individual computers doing their computation in parallel. One major challenge for this sort of programming is that operations on arrays on multiple computers is very complex and an interface is needed so that these arrays seem like they are on a single computer. This is what global arrays does. The work done here is to use more efficient operations on that data that requires less copying of data to be completed. This saves a lot of time because copying data on many different computers is time intensive. The way this challenge was solved is when data to be operated on with binary operations are on the same computer, they are not copied when they are accessed. When they are on separate computers, only one set is copied when accessed. This saves time because of less copying done although more data access operations were done.« less

  8. Effect of embedded metal nanocrystals on the resistive switching characteristics in NiN-based resistive random access memory cells

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Yun, Min Ju; Kim, Hee-Dong; Man Hong, Seok

    2014-03-07

    The metal nanocrystals (NCs) embedded-NiN-based resistive random access memory cells are demonstrated using several metal NCs (i.e., Pt, Ni, and Ti) with different physical parameters in order to investigate the metal NC's dependence on resistive switching (RS) characteristics. First, depending on the electronegativity of metal, the size of metal NCs is determined and this affects the operating current of memory cells. If metal NCs with high electronegativity are incorporated, the size of the NCs is reduced; hence, the operating current is reduced owing to the reduced density of the electric field around the metal NCs. Second, the potential wells aremore » formed by the difference of work function between the metal NCs and active layer, and the barrier height of the potential wells affects the level of operating voltage as well as the conduction mechanism of metal NCs embedded memory cells. Therefore, by understanding these correlations between the active layer and embedded metal NCs, we can optimize the RS properties of metal NCs embedded memory cells as well as predict their conduction mechanisms.« less

  9. Multiple memory stores and operant conditioning: a rationale for memory's complexity.

    PubMed

    Meeter, Martijn; Veldkamp, Rob; Jin, Yaochu

    2009-02-01

    Why does the brain contain more than one memory system? Genetic algorithms can play a role in elucidating this question. Here, model animals were constructed containing a dorsal striatal layer that controlled actions, and a ventral striatal layer that controlled a dopaminergic learning signal. Both layers could gain access to three modeled memory stores, but such access was penalized as energy expenditure. Model animals were then selected on their fitness in simulated operant conditioning tasks. Results suggest that having access to multiple memory stores and their representations is important in learning to regulate dopamine release, as well as in contextual discrimination. For simple operant conditioning, as well as stimulus discrimination, hippocampal compound representations turned out to suffice, a counterintuitive result given findings that hippocampal lesions tend not to affect performance in such tasks. We argue that there is in fact evidence to support a role for compound representations and the hippocampus in even the simplest conditioning tasks.

  10. Remote Memory Access Protocol Target Node Intellectual Property

    NASA Technical Reports Server (NTRS)

    Haddad, Omar

    2013-01-01

    The MagnetoSpheric Multiscale (MMS) mission had a requirement to use the Remote Memory Access Protocol (RMAP) over its SpaceWire network. At the time, no known intellectual property (IP) cores were available for purchase. Additionally, MMS preferred to implement the RMAP functionality with control over the low-level details of the design. For example, not all the RMAP standard functionality was needed, and it was desired to implement only the portions of the RMAP protocol that were needed. RMAP functionality had been previously implemented in commercial off-the-shelf (COTS) products, but the IP core was not available for purchase. The RMAP Target IP core is a VHDL (VHSIC Hardware Description Language description of a digital logic design suitable for implementation in an FPGA (field-programmable gate array) or ASIC (application-specific integrated circuit) that parses SpaceWire packets that conform to the RMAP standard. The RMAP packet protocol allows a network host to access and control a target device using address mapping. This capability allows SpaceWire devices to be managed in a standardized way that simplifies the hardware design of the device, as well as the development of the software that controls the device. The RMAP Target IP core has some features that are unique and not specified in the RMAP standard. One such feature is the ability to automatically abort transactions if the back-end logic does not respond to read/write requests within a predefined time. When a request times out, the RMAP Target IP core automatically retracts the request and returns a command response with an appropriate status in the response packet s header. Another such feature is the ability to control the SpaceWire node or router using RMAP transactions in the extended address range. This allows the SpaceWire network host to manage the SpaceWire network elements using RMAP packets, which reduces the number of protocols that the network host needs to support.

  11. Building more powerful less expensive supercomputers using Processing-In-Memory (PIM) LDRD final report.

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Murphy, Richard C.

    2009-09-01

    This report details the accomplishments of the 'Building More Powerful Less Expensive Supercomputers Using Processing-In-Memory (PIM)' LDRD ('PIM LDRD', number 105809) for FY07-FY09. Latency dominates all levels of supercomputer design. Within a node, increasing memory latency, relative to processor cycle time, limits CPU performance. Between nodes, the same increase in relative latency impacts scalability. Processing-In-Memory (PIM) is an architecture that directly addresses this problem using enhanced chip fabrication technology and machine organization. PIMs combine high-speed logic and dense, low-latency, high-bandwidth DRAM, and lightweight threads that tolerate latency by performing useful work during memory transactions. This work examines the potential ofmore » PIM-based architectures to support mission critical Sandia applications and an emerging class of more data intensive informatics applications. This work has resulted in a stronger architecture/implementation collaboration between 1400 and 1700. Additionally, key technology components have impacted vendor roadmaps, and we are in the process of pursuing these new collaborations. This work has the potential to impact future supercomputer design and construction, reducing power and increasing performance. This final report is organized as follow: this summary chapter discusses the impact of the project (Section 1), provides an enumeration of publications and other public discussion of the work (Section 1), and concludes with a discussion of future work and impact from the project (Section 1). The appendix contains reprints of the refereed publications resulting from this work.« less

  12. Some pitfalls in measuring memory in animals.

    PubMed

    Thorpe, Christina M; Jacova, Claudia; Wilkie, Donald M

    2004-11-01

    Because the presence or absence of memories in the brain cannot be directly observed, scientists must rely on indirect measures and use inferential reasoning to make statements about the status of memories. In humans, memories are often accessed through spoken or written language. In animals, memory is accessed through overt behaviours such as running down an arm in a maze, pressing a lever, or visiting a food cache site. Because memory is measured by these indirect methods, errors in the veracity of statements about memory can occur. In this brief paper, we identify three areas that may serve as pitfalls in reasoning about memory in animals: (1) the presence of 'silent associations', (2) intrusions of species-typical behaviours on memory tasks, and (3) improper mapping between human and animals memory tasks. There are undoubtedly other areas in which scientists should act cautiously when reasoning about the status of memory.

  13. Implementation of nitrogen-doped titanium-tungsten tunable heater in phase change random access memory and its effects on device performance

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Tan, Chun Chia; Zhao, Rong, E-mail: zhao-rong@sutd.edu.sg; Chong, Tow Chong

    2014-10-13

    Nitrogen-doped titanium-tungsten (N-TiW) was proposed as a tunable heater in Phase Change Random Access Memory (PCRAM). By tuning N-TiW's material properties through doping, the heater can be tailored to optimize the access speed and programming current of PCRAM. Experiments reveal that N-TiW's resistivity increases and thermal conductivity decreases with increasing nitrogen-doping ratio, and N-TiW devices displayed (∼33% to ∼55%) reduced programming currents. However, there is a tradeoff between the current and speed for heater-based PCRAM. Analysis of devices with different N-TiW heaters shows that N-TiW doping levels could be optimized to enable low RESET currents and fast access speeds.

  14. Maximization of DRAM yield by control of surface charge and particle addition during high dose implantation

    NASA Astrophysics Data System (ADS)

    Horvath, J.; Moffatt, S.

    1991-04-01

    Ion implantation processing exposes semiconductor devices to an energetic ion beam in order to deposit dopant ions in shallow layers. In addition to this primary process, foreign materials are deposited as particles and surface films. The deposition of particles is a major cause of IC yield loss and becomes even more significant as device dimensions are decreased. Control of particle addition in a high-volume production environment requires procedures to limit beamline and endstation sources, control of particle transport, cleaning procedures and a well grounded preventative maintenance philosophy. Control of surface charge by optimization of the ion beam and electron shower conditions and measurement with a real-time charge sensor has been effective in improving the yield of NMOS and CMOS DRAMs. Control of surface voltages to a range between 0 and -20 V was correlated with good implant yield with PI9200 implanters for p + and n + source-drain implants.

  15. The dynamic interplay between acute psychosocial stress, emotion and autobiographical memory.

    PubMed

    Sheldon, Signy; Chu, Sonja; Nitschke, Jonas P; Pruessner, Jens C; Bartz, Jennifer A

    2018-06-06

    Although acute psychosocial stress can impact autobiographical memory retrieval, the nature of this effect is not entirely clear. One reason for this ambiguity is because stress can have opposing effects on the different stages of autobiographical memory retrieval. We addressed this issue by testing how acute stress affects three stages of the autobiographical memory retrieval - accessing, recollecting and reconsolidating a memory. We also investigate the influence of emotion valence on this effect. In a between-subjects design, participants were first exposed to an acute psychosocial stressor or a control task. Next, the participants were shown positive, negative or neutral retrieval cues and asked to access and describe autobiographical memories. After a three to four day delay, participants returned for a second session in which they described these autobiographical memories. During initial retrieval, stressed participants were slower to access memories than were control participants; moreover, cortisol levels were positively associated with response times to access positively-cued memories. There were no effects of stress on the amount of details used to describe memories during initial retrieval, but stress did influence memory detail during session two. During session two, stressed participants recovered significantly more details, particularly emotional ones, from the remembered events than control participants. Our results indicate that the presence of stress impairs the ability to access consolidated autobiographical memories; moreover, although stress has no effect on memory recollection, stress alters how recollected experiences are reconsolidated back into memory traces.

  16. A stochastic simulation method for the assessment of resistive random access memory retention reliability

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Berco, Dan, E-mail: danny.barkan@gmail.com; Tseng, Tseung-Yuen, E-mail: tseng@cc.nctu.edu.tw

    This study presents an evaluation method for resistive random access memory retention reliability based on the Metropolis Monte Carlo algorithm and Gibbs free energy. The method, which does not rely on a time evolution, provides an extremely efficient way to compare the relative retention properties of metal-insulator-metal structures. It requires a small number of iterations and may be used for statistical analysis. The presented approach is used to compare the relative robustness of a single layer ZrO{sub 2} device with a double layer ZnO/ZrO{sub 2} one, and obtain results which are in good agreement with experimental data.

  17. A Pilot Memory Café for People with Learning Disabilities and Memory Difficulties

    ERIC Educational Resources Information Center

    Kiddle, Hannah; Drew, Neil; Crabbe, Paul; Wigmore, Jonathan

    2016-01-01

    Memory cafés have been found to normalise experiences of dementia and provide access to an accepting social network. People with learning disabilities are at increased risk of developing dementia, but the possible benefits of attending a memory café are not known. This study evaluates a 12-week pilot memory café for people with learning…

  18. System and method for programmable bank selection for banked memory subsystems

    DOEpatents

    Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan

    2010-09-07

    A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

  19. Unexpected surface implanted layer in static random access memory devices observed by microwave impedance microscope

    NASA Astrophysics Data System (ADS)

    Kundhikanjana, W.; Yang, Y.; Tanga, Q.; Zhang, K.; Lai, K.; Ma, Y.; Kelly, M. A.; Li, X. X.; Shen, Z.-X.

    2013-02-01

    Real-space mapping of doping concentration in semiconductor devices is of great importance for the microelectronics industry. In this work, a scanning microwave impedance microscope (MIM) is employed to resolve the local conductivity distribution of a static random access memory sample. The MIM electronics can also be adjusted to the scanning capacitance microscopy (SCM) mode, allowing both measurements on the same region. Interestingly, while the conventional SCM images match the nominal device structure, the MIM results display certain unexpected features, which originate from a thin layer of the dopant ions penetrating through the protective layers during the heavy implantation steps.

  20. RAPID: A random access picture digitizer, display, and memory system

    NASA Technical Reports Server (NTRS)

    Yakimovsky, Y.; Rayfield, M.; Eskenazi, R.

    1976-01-01

    RAPID is a system capable of providing convenient digital analysis of video data in real-time. It has two modes of operation. The first allows for continuous digitization of an EIA RS-170 video signal. Each frame in the video signal is digitized and written in 1/30 of a second into RAPID's internal memory. The second mode leaves the content of the internal memory independent of the current input video. In both modes of operation the image contained in the memory is used to generate an EIA RS-170 composite video output signal representing the digitized image in the memory so that it can be displayed on a monitor.

  1. Attention, working memory, and phenomenal experience of WM content: memory levels determined by different types of top-down modulation.

    PubMed

    Jacob, Jane; Jacobs, Christianne; Silvanto, Juha

    2015-01-01

    What is the role of top-down attentional modulation in consciously accessing working memory (WM) content? In influential WM models, information can exist in different states, determined by allocation of attention; placing the original memory representation in the center of focused attention gives rise to conscious access. Here we discuss various lines of evidence indicating that such attentional modulation is not sufficient for memory content to be phenomenally experienced. We propose that, in addition to attentional modulation of the memory representation, another type of top-down modulation is required: suppression of all incoming visual information, via inhibition of early visual cortex. In this view, there are three distinct memory levels, as a function of the top-down control associated with them: (1) Nonattended, nonconscious associated with no attentional modulation; (2) attended, phenomenally nonconscious memory, associated with attentional enhancement of the actual memory trace; (3) attended, phenomenally conscious memory content, associated with enhancement of the memory trace and top-down suppression of all incoming visual input.

  2. Memory protection

    NASA Technical Reports Server (NTRS)

    Denning, Peter J.

    1988-01-01

    Accidental overwriting of files or of memory regions belonging to other programs, browsing of personal files by superusers, Trojan horses, and viruses are examples of breakdowns in workstations and personal computers that would be significantly reduced by memory protection. Memory protection is the capability of an operating system and supporting hardware to delimit segments of memory, to control whether segments can be read from or written into, and to confine accesses of a program to its segments alone. The absence of memory protection in many operating systems today is the result of a bias toward a narrow definition of performance as maximum instruction-execution rate. A broader definition, including the time to get the job done, makes clear that cost of recovery from memory interference errors reduces expected performance. The mechanisms of memory protection are well understood, powerful, efficient, and elegant. They add to performance in the broad sense without reducing instruction execution rate.

  3. How intention and monitoring your thoughts influence characteristics of autobiographical memories.

    PubMed

    Barzykowski, Krystian; Staugaard, Søren Risløv

    2018-05-01

    Involuntary autobiographical memories come to mind effortlessly and unintended, but the mechanisms of their retrieval are not fully understood. We hypothesize that involuntary retrieval depends on memories that are highly accessible (e.g., intense, unusual, recent, rehearsed), while the elaborate search that characterizes voluntary retrieval also produces memories that are mundane, repeated or distant - memories with low accessibility. Previous research provides some evidence for this 'threshold hypothesis'. However, in almost every prior study, participants have been instructed to report only memories while ignoring other thoughts. It is possible that such an instruction can modify the phenomenological characteristics of involuntary memories. This study aimed to investigate the effects of retrieval intentionality (i.e., wanting to retrieve a memory) and selective monitoring (i.e., instructions to report only memories) on the phenomenology of autobiographical memories. Participants were instructed to (1) intentionally retrieve autobiographical memories, (2) intentionally retrieve any type of thought (3) wait for an autobiographical memory to spontaneously appear, or (4) wait for any type of thought to spontaneously appear. They rated the mental content on a number of phenomenological characteristics both during retrieval and retrospectively following retrieval. The results support the prediction that highly accessible memories mostly enter awareness unintended and without selective monitoring, while memories with low accessibility rely on intention and selective monitoring. We discuss the implications of these effects. © 2017 The British Psychological Society.

  4. Spin-transfer-torque efficiency enhanced by edge-damage of perpendicular magnetic random access memories

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Song, Kyungmi; Lee, Kyung-Jin, E-mail: kj-lee@korea.ac.kr; Department of Materials Science and Engineering, Korea University, Seoul 136-713

    2015-08-07

    We numerically investigate the effect of magnetic and electrical damages at the edge of a perpendicular magnetic random access memory (MRAM) cell on the spin-transfer-torque (STT) efficiency that is defined by the ratio of thermal stability factor to switching current. We find that the switching mode of an edge-damaged cell is different from that of an undamaged cell, which results in a sizable reduction in the switching current. Together with a marginal reduction of the thermal stability factor of an edge-damaged cell, this feature makes the STT efficiency large. Our results suggest that a precise edge control is viable formore » the optimization of STT-MRAM.« less

  5. Forming-free and self-rectifying resistive switching of the simple Pt/TaOx/n-Si structure for access device-free high-density memory application

    NASA Astrophysics Data System (ADS)

    Gao, Shuang; Zeng, Fei; Li, Fan; Wang, Minjuan; Mao, Haijun; Wang, Guangyue; Song, Cheng; Pan, Feng

    2015-03-01

    The search for self-rectifying resistive memories has aroused great attention due to their potential in high-density memory applications without additional access devices. Here we report the forming-free and self-rectifying bipolar resistive switching behavior of a simple Pt/TaOx/n-Si tri-layer structure. The forming-free phenomenon is attributed to the generation of a large amount of oxygen vacancies, in a TaOx region that is in close proximity to the TaOx/n-Si interface, via out-diffusion of oxygen ions from TaOx to n-Si. A maximum rectification ratio of ~6 × 102 is obtained when the Pt/TaOx/n-Si devices stay in a low resistance state, which originates from the existence of a Schottky barrier between the formed oxygen vacancy filament and the n-Si electrode. More importantly, numerical simulation reveals that the self-rectifying behavior itself can guarantee a maximum crossbar size of 212 × 212 (~44 kbit) on the premise of 10% read margin. Moreover, satisfactory switching uniformity and retention performance are observed based on this simple tri-layer structure. All of these results demonstrate the great potential of this simple Pt/TaOx/n-Si tri-layer structure for access device-free high-density memory applications.The search for self-rectifying resistive memories has aroused great attention due to their potential in high-density memory applications without additional access devices. Here we report the forming-free and self-rectifying bipolar resistive switching behavior of a simple Pt/TaOx/n-Si tri-layer structure. The forming-free phenomenon is attributed to the generation of a large amount of oxygen vacancies, in a TaOx region that is in close proximity to the TaOx/n-Si interface, via out-diffusion of oxygen ions from TaOx to n-Si. A maximum rectification ratio of ~6 × 102 is obtained when the Pt/TaOx/n-Si devices stay in a low resistance state, which originates from the existence of a Schottky barrier between the formed oxygen vacancy filament and the n

  6. Cost-effective, transfer-free, flexible resistive random access memory using laser-scribed reduced graphene oxide patterning technology.

    PubMed

    Tian, He; Chen, Hong-Yu; Ren, Tian-Ling; Li, Cheng; Xue, Qing-Tang; Mohammad, Mohammad Ali; Wu, Can; Yang, Yi; Wong, H-S Philip

    2014-06-11

    Laser scribing is an attractive reduced graphene oxide (rGO) growth and patterning technology because the process is low-cost, time-efficient, transfer-free, and flexible. Various laser-scribed rGO (LSG) components such as capacitors, gas sensors, and strain sensors have been demonstrated. However, obstacles remain toward practical application of the technology where all the components of a system are fabricated using laser scribing. Memory components, if developed, will substantially broaden the application space of low-cost, flexible electronic systems. For the first time, a low-cost approach to fabricate resistive random access memory (ReRAM) using laser-scribed rGO as the bottom electrode is experimentally demonstrated. The one-step laser scribing technology allows transfer-free rGO synthesis directly on flexible substrates or non-flat substrates. Using this time-efficient laser-scribing technology, the patterning of a memory-array area up to 100 cm(2) can be completed in 25 min. Without requiring the photoresist coating for lithography, the surface of patterned rGO remains as clean as its pristine state. Ag/HfOx/LSG ReRAM using laser-scribing technology is fabricated in this work. Comprehensive electrical characteristics are presented including forming-free behavior, stable switching, reasonable reliability performance and potential for 2-bit storage per memory cell. The results suggest that laser-scribing technology can potentially produce more cost-effective and time-effective rGO-based circuits and systems for practical applications.

  7. Neural Correlates of Conceptual Implicit Memory and Their Contamination of Putative Neural Correlates of Explicit Memory

    ERIC Educational Resources Information Center

    Voss, Joel L.; Paller, Ken A.

    2007-01-01

    During episodic recognition tests, meaningful stimuli such as words can engender both conscious retrieval (explicit memory) and facilitated access to meaning that is distinct from the awareness of remembering (conceptual implicit memory). Neuroimaging investigations of one type of memory are frequently subject to the confounding influence of the…

  8. Metal oxide resistive random access memory based synaptic devices for brain-inspired computing

    NASA Astrophysics Data System (ADS)

    Gao, Bin; Kang, Jinfeng; Zhou, Zheng; Chen, Zhe; Huang, Peng; Liu, Lifeng; Liu, Xiaoyan

    2016-04-01

    The traditional Boolean computing paradigm based on the von Neumann architecture is facing great challenges for future information technology applications such as big data, the Internet of Things (IoT), and wearable devices, due to the limited processing capability issues such as binary data storage and computing, non-parallel data processing, and the buses requirement between memory units and logic units. The brain-inspired neuromorphic computing paradigm is believed to be one of the promising solutions for realizing more complex functions with a lower cost. To perform such brain-inspired computing with a low cost and low power consumption, novel devices for use as electronic synapses are needed. Metal oxide resistive random access memory (ReRAM) devices have emerged as the leading candidate for electronic synapses. This paper comprehensively addresses the recent work on the design and optimization of metal oxide ReRAM-based synaptic devices. A performance enhancement methodology and optimized operation scheme to achieve analog resistive switching and low-energy training behavior are provided. A three-dimensional vertical synapse network architecture is proposed for high-density integration and low-cost fabrication. The impacts of the ReRAM synaptic device features on the performances of neuromorphic systems are also discussed on the basis of a constructed neuromorphic visual system with a pattern recognition function. Possible solutions to achieve the high recognition accuracy and efficiency of neuromorphic systems are presented.

  9. The potential of multi-port optical memories in digital computing

    NASA Technical Reports Server (NTRS)

    Alford, C. O.; Gaylord, T. K.

    1975-01-01

    A high-capacity memory with a relatively high data transfer rate and multi-port simultaneous access capability may serve as the basis for new computer architectures. The implementation of a multi-port optical memory is discussed. Several computer structures are presented that might profitably use such a memory. These structures include (1) a simultaneous record access system, (2) a simultaneously shared memory computer system, and (3) a parallel digital processing structure.

  10. Thermal characterization and analysis of phase change random access memory

    NASA Astrophysics Data System (ADS)

    Giraud, V.; Cluzel, J.; Sousa, V.; Jacquot, A.; Dauscher, A.; Lenoir, B.; Scherrer, H.; Romer, S.

    2005-07-01

    The cross-plane thermal conductivity of Ge2Sb2Te5, either in its amorphous state or fcc crystallized state, and titanium nitride (TiN) thin films has been measured at room temperature by the 3ω method. These materials are involved in the fabrication of phase change random access memory (PC-RAM), Ge2Sb2Te5 and TiN being the PC and pseudoelectrode materials, respectively. The thermal conductivity of insulating SiO2 and ZnS :SiO2 layers was determined too. Each thermal conductivity measurement was performed by the means of at least two strip widths in order to check both the measurement self-consistency and the measurement accuracy. The performance of PC-RAM cells, i.e., the time needed to reach the melting temperature of the PC material and the cooling speed, has been evaluated as a function of both the measured thermal conductivity of the PC material and the reset current intensity independently of the thermal properties of the pseudoelectrodes by the way of analytical formula. The influence of the thickness and the thermal properties of the pseudoelectrodes on the performances have been determined by numerical simulations.

  11. Kanerva's sparse distributed memory: An associative memory algorithm well-suited to the Connection Machine

    NASA Technical Reports Server (NTRS)

    Rogers, David

    1988-01-01

    The advent of the Connection Machine profoundly changes the world of supercomputers. The highly nontraditional architecture makes possible the exploration of algorithms that were impractical for standard Von Neumann architectures. Sparse distributed memory (SDM) is an example of such an algorithm. Sparse distributed memory is a particularly simple and elegant formulation for an associative memory. The foundations for sparse distributed memory are described, and some simple examples of using the memory are presented. The relationship of sparse distributed memory to three important computational systems is shown: random-access memory, neural networks, and the cerebellum of the brain. Finally, the implementation of the algorithm for sparse distributed memory on the Connection Machine is discussed.

  12. zorder-lib: Library API for Z-Order Memory Layout

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Nowell, Lucy; Edward W. Bethel

    2015-04-01

    This document describes the motivation for, elements of, and use of the zorder-lib, a library API that implements organization of and access to data in memory using either a-order (also known as "row-major" order) or z-order memory layouts. The primary motivation for this work is to improve the performance of many types of data- intensive codes by increasing both spatial and temporal locality of memory accesses. The basic idea is that the cost associated with accessing a datum is less when it is nearby in either space or time.

  13. Review of optical memory technologies

    NASA Technical Reports Server (NTRS)

    Chen, D.

    1972-01-01

    Optical technologies for meeting the demands of large capacity fast access time memory are discussed in terms of optical phenomena and laser applications. The magneto-optic and electro-optic approaches are considered to be the most promising memory approaches.

  14. Radiation dosimetry using three-dimensional optical random access memories

    NASA Technical Reports Server (NTRS)

    Moscovitch, M.; Phillips, G. W.

    2001-01-01

    Three-dimensional optical random access memories (3D ORAMs) are a new generation of high-density data storage devices. Binary information is stored and retrieved via a light induced reversible transformation of an ensemble of bistable photochromic molecules embedded in a polymer matrix. This paper describes the application of 3D ORAM materials to radiation dosimetry. It is shown both theoretically and experimentally, that ionizing radiation in the form of heavy charged particles is capable of changing the information originally stored on the ORAM material. The magnitude and spatial distribution of these changes are used as a measure of the absorbed dose, particle type and energy. The effects of exposure on 3D ORAM materials have been investigated for a variety of particle types and energies, including protons, alpha particles and 12C ions. The exposed materials are observed to fluoresce when exposed to laser light. The intensity and the depth of the fluorescence is dependent on the type and energy of the particle to which the materials were exposed. It is shown that these effects can be modeled using Monte Carlo calculations. The model provides a better understanding of the properties of these materials. which should prove useful for developing systems for charged particle and neutron dosimetry/detector applications. c2001 Published by Elsevier Science B.V.

  15. Simulation study on heat conduction of a nanoscale phase-change random access memory cell.

    PubMed

    Kim, Junho; Song, Ki-Bong

    2006-11-01

    We have investigated heat transfer characteristics of a nano-scale phase-change random access memory (PRAM) cell using finite element method (FEM) simulation. Our PRAM cell is based on ternary chalcogenide alloy, Ge2Sb2Te5 (GST), which is used as a recording layer. For contact area of 100 x 100 nm2, simulations of crystallization and amorphization processes were carried out. Physical quantities such as electric conductivity, thermal conductivity, and specific heat were treated as temperature-dependent parameters. Through many simulations, it is concluded that one can reduce set current by decreasing both electric conductivities of amorphous GST and crystalline GST, and in addition to these conditions by decreasing electric conductivity of molten GST one can also reduce reset current significantly.

  16. Frontal activations associated with accessing and evaluating information in working memory: an fMRI study.

    PubMed

    Zhang, John X; Leung, Hoi-Chung; Johnson, Marcia K

    2003-11-01

    To investigate the involvement of frontal cortex in accessing and evaluating information in working memory, we used a variant of a Sternberg paradigm and compared brain activations between positive and negative responses (known to differentially tax access/evaluation processes). Participants remembered two trigrams in each trial and were then cued to discard one of them and maintain the other one as the target set. After a delay, a probe letter was presented and participants made decisions about whether or not it was in the target set. Several frontal areas--anterior cingulate (BA32), middle frontal gyrus (bilateral BA9, right BA10, and right BA46), and left inferior frontal gyrus (BA44/45)--showed increased activity when participants made correct negative responses relative to when they made correct positive responses. No areas activated significantly more for the positive responses than for the negative responses. It is suggested that the multiple frontal areas involved in the test phase of this task may reflect several component processes that underlie more general frontal functions.

  17. Retrieval practice enhances the accessibility but not the quality of memory.

    PubMed

    Sutterer, David W; Awh, Edward

    2016-06-01

    Numerous studies have demonstrated that retrieval from long-term memory (LTM) can enhance subsequent memory performance, a phenomenon labeled the retrieval practice effect. However, the almost exclusive reliance on categorical stimuli in this literature leaves open a basic question about the nature of this improvement in memory performance. It has not yet been determined whether retrieval practice improves the probability of successful memory retrieval or the quality of the retrieved representation. To answer this question, we conducted three experiments using a mixture modeling approach (Zhang & Luck, 2008) that provides a measure of both the probability of recall and the quality of the recalled memories. Subjects attempted to memorize the color of 400 unique shapes. After every 10 images were presented, subjects either recalled the last 10 colors (the retrieval practice condition) by clicking on a color wheel with each shape as a retrieval cue or they participated in a control condition that involved no further presentations (Experiment 1) or restudy of the 10 shape/color associations (Experiments 2 and 3). Performance in a subsequent delayed recall test revealed a robust retrieval practice effect. Subjects recalled a significantly higher proportion of items that they had previously retrieved relative to items that were untested or that they had restudied. Interestingly, retrieval practice did not elicit any improvement in the precision of the retrieved memories. The same empirical pattern also was observed following delays of greater than 24 hours. Thus, retrieval practice increases the probability of successful memory retrieval but does not improve memory quality.

  18. Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 1

    NASA Technical Reports Server (NTRS)

    Klute, A.

    1979-01-01

    Electrical characterization and qualification tests were performed on the RCA MWS5001D, 1024 by 1-bit, CMOS, random access memory. Characterization tests were performed on five devices. The tests included functional tests, AC parametric worst case pattern selection test, determination of worst-case transition for setup and hold times and a series of schmoo plots. The qualification tests were performed on 32 devices and included a 2000 hour burn in with electrical tests performed at 0 hours and after 168, 1000, and 2000 hours of burn in. The tests performed included functional tests and AC and DC parametric tests. All of the tests in the characterization phase, with the exception of the worst-case transition test, were performed at ambient temperatures of 25, -55 and 125 C. The worst-case transition test was performed at 25 C. The preburn in electrical tests were performed at 25, -55, and 125 C. All burn in endpoint tests were performed at 25, -40, -55, 85, and 125 C.

  19. Implementing a bubble memory hierarchy system

    NASA Technical Reports Server (NTRS)

    Segura, R.; Nichols, C. D.

    1979-01-01

    This paper reports on implementation of a magnetic bubble memory in a two-level hierarchial system. The hierarchy used a major-minor loop device and RAM under microprocessor control. Dynamic memory addressing, dual bus primary memory, and hardware data modification detection are incorporated in the system to minimize access time. It is the objective of the system to incorporate the advantages of bipolar memory with that of bubble domain memory to provide a smart, optimal memory system which is easy to interface and independent of user's system.

  20. Application of phase-change materials in memory taxonomy.

    PubMed

    Wang, Lei; Tu, Liang; Wen, Jing

    2017-01-01

    Phase-change materials are suitable for data storage because they exhibit reversible transitions between crystalline and amorphous states that have distinguishable electrical and optical properties. Consequently, these materials find applications in diverse memory devices ranging from conventional optical discs to emerging nanophotonic devices. Current research efforts are mostly devoted to phase-change random access memory, whereas the applications of phase-change materials in other types of memory devices are rarely reported. Here we review the physical principles of phase-change materials and devices aiming to help researchers understand the concept of phase-change memory. We classify phase-change memory devices into phase-change optical disc, phase-change scanning probe memory, phase-change random access memory, and phase-change nanophotonic device, according to their locations in memory hierarchy. For each device type we discuss the physical principles in conjunction with merits and weakness for data storage applications. We also outline state-of-the-art technologies and future prospects.

  1. Application of phase-change materials in memory taxonomy

    PubMed Central

    Wang, Lei; Tu, Liang; Wen, Jing

    2017-01-01

    Abstract Phase-change materials are suitable for data storage because they exhibit reversible transitions between crystalline and amorphous states that have distinguishable electrical and optical properties. Consequently, these materials find applications in diverse memory devices ranging from conventional optical discs to emerging nanophotonic devices. Current research efforts are mostly devoted to phase-change random access memory, whereas the applications of phase-change materials in other types of memory devices are rarely reported. Here we review the physical principles of phase-change materials and devices aiming to help researchers understand the concept of phase-change memory. We classify phase-change memory devices into phase-change optical disc, phase-change scanning probe memory, phase-change random access memory, and phase-change nanophotonic device, according to their locations in memory hierarchy. For each device type we discuss the physical principles in conjunction with merits and weakness for data storage applications. We also outline state-of-the-art technologies and future prospects. PMID:28740557

  2. Staging memory for massively parallel processor

    NASA Technical Reports Server (NTRS)

    Batcher, Kenneth E. (Inventor)

    1988-01-01

    The invention herein relates to a computer organization capable of rapidly processing extremely large volumes of data. A staging memory is provided having a main stager portion consisting of a large number of memory banks which are accessed in parallel to receive, store, and transfer data words simultaneous with each other. Substager portions interconnect with the main stager portion to match input and output data formats with the data format of the main stager portion. An address generator is coded for accessing the data banks for receiving or transferring the appropriate words. Input and output permutation networks arrange the lineal order of data into and out of the memory banks.

  3. Context controls access to working and reference memory in the pigeon (Columba livia).

    PubMed

    Roberts, William A; Macpherson, Krista; Strang, Caroline

    2016-01-01

    The interaction between working and reference memory systems was examined under conditions in which salient contextual cues were presented during memory retrieval. Ambient colored lights (red or green) bathed the operant chamber during the presentation of comparison stimuli in delayed matching-to-sample training (working memory) and during the presentation of the comparison stimuli as S+ and S- cues in discrimination training (reference memory). Strong competition between memory systems appeared when the same contextual cue appeared during working and reference memory training. When different contextual cues were used, however, working memory was completely protected from reference memory interference. © 2016 Society for the Experimental Analysis of Behavior.

  4. False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation

    NASA Astrophysics Data System (ADS)

    Sawada, Takuya; Takata, Hidehiro; Nii, Koji; Nagata, Makoto

    2013-04-01

    Static random access memory (SRAM) cores exhibit susceptibility against power supply voltage variation. False operation is investigated among SRAM cells under sinusoidal voltage variation on power lines introduced by direct RF power injection. A standard SRAM core of 16 kbyte in a 90 nm 1.5 V technology is diagnosed with built-in self test and on-die noise monitor techniques. The sensitivity of bit error rate is shown to be high against the frequency of injected voltage variation, while it is not greatly influenced by the difference in frequency and phase against SRAM clocking. It is also observed that the distribution of false bits is substantially random in a cell array.

  5. Memory hierarchy using row-based compression

    DOEpatents

    Loh, Gabriel H.; O'Connor, James M.

    2016-10-25

    A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. The second memory includes a plurality of rows, each row including a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks. Each tag block represents a corresponding compressed data block of the row. The device further includes decompression logic to decompress data blocks accessed from the second memory. The device further includes compression logic to compress data blocks to be stored in the second memory.

  6. Solution-processed flexible NiO resistive random access memory device

    NASA Astrophysics Data System (ADS)

    Kim, Soo-Jung; Lee, Heon; Hong, Sung-Hoon

    2018-04-01

    Non-volatile memories (NVMs) using nanocrystals (NCs) as active materials can be applied to soft electronic devices requiring a low-temperature process because NCs do not require a heat treatment process for crystallization. In addition, memory devices can be implemented simply by using a patterning technique using a solution process. In this study, a flexible NiO ReRAM device was fabricated using a simple NC patterning method that controls the capillary force and dewetting of a NiO NC solution at low temperature. The switching behavior of a NiO NC based memory was clearly observed by conductive atomic force microscopy (c-AFM).

  7. Measuring autobiographical fluency in the self-memory system.

    PubMed

    Rathbone, Clare J; Moulin, Chris J A

    2014-01-01

    Autobiographical memory is widely considered to be fundamentally related to concepts of self and identity. However, few studies have sought to test models of self and memory directly using experimental designs. Using a novel autobiographical fluency paradigm, the present study investigated memory accessibility for different levels of self-related knowledge. Forty participants generated 20 "I am" statements about themselves, from which the 1st, 5th, 10th, 15th, and 20th were used as cues in a two-minute autobiographical fluency task. The most salient aspects of the self, measured by both serial position and ratings of personal significance, were associated with more accessible sets of autobiographical memories. This finding supports theories that view the self as a powerful organizational structure in memory. Results are discussed with reference to models of self and memory.

  8. Oscillatory mechanisms of process binding in memory.

    PubMed

    Klimesch, Wolfgang; Freunberger, Roman; Sauseng, Paul

    2010-06-01

    A central topic in cognitive neuroscience is the question, which processes underlie large scale communication within and between different neural networks. The basic assumption is that oscillatory phase synchronization plays an important role for process binding--the transient linking of different cognitive processes--which may be considered a special type of large scale communication. We investigate this question for memory processes on the basis of different types of oscillatory synchronization mechanisms. The reviewed findings suggest that theta and alpha phase coupling (and phase reorganization) reflect control processes in two large memory systems, a working memory and a complex knowledge system that comprises semantic long-term memory. It is suggested that alpha phase synchronization may be interpreted in terms of processes that coordinate top-down control (a process guided by expectancy to focus on relevant search areas) and access to memory traces (a process leading to the activation of a memory trace). An analogous interpretation is suggested for theta oscillations and the controlled access to episodic memories. Copyright (c) 2009 Elsevier Ltd. All rights reserved.

  9. A Calendar Savant with Episodic Memory Impairments

    PubMed Central

    Olson, Ingrid R.; Berryhill, Marian E.; Drowos, David B.; Brown, Lawrence; Chatterjee, Anjan

    2010-01-01

    Patients with memory disorders have severely restricted learning and memory. For instance, patients with anterograde amnesia can learn motor procedures as well as retaining some restricted ability to learn new words and factual information. However, such learning is inflexible and frequently inaccessible to conscious awareness. Here we present a case of patient AC596, a 25-year old male with severe episodic memory impairments, presumably due to anoxia during a preterm birth. In contrast to his poor episodic memory, he exhibits savant-like memory for calendar information that can be flexibly accessed by day, month, and year cues. He also has the ability to recollect the exact date of a wide range of personal experiences over the past 20 years. The patient appears to supplement his generally poor episodic memory by using memorized calendar information as a retrieval cue for autobiographical events. These findings indicate that islands of preserved memory functioning, such as a highly developed semantic memory system, can exist in individuals with severely impaired episodic memory systems. In this particular case, our patient’s memory for dates far outstripped that of normal individuals and served as a keen retrieval cue, allowing him to access information that was otherwise unavailable. PMID:20104390

  10. A Concept of Corporate Memory

    DTIC Science & Technology

    1979-05-17

    34 social memory", in the broader context of society. This paper explores some of the possibilities of creating a computer based corporate memory...NUMBER 79-04-03 2. COVT ACCESSION NO. 3. RECIPIENT’S CATALOG NUMBER «. TITLE f«n<* SubfU/.; A CONCEPT OF- CORPORATE MEMORY S. TYPE OF...It. SUPPLEMENTARY NOTES • IJ. KEY WORDS fCon<Jnu» on r»r»r»» mid* It nmcammmrj and Idmntltr bf block numbmr) corporate memory, office

  11. A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching

    NASA Astrophysics Data System (ADS)

    Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

    2017-04-01

    A high-density nonvolatile associative memory (NV-AM) based on spin transfer torque magnetoresistive random access memory (STT-MRAM), which achieves highly concurrent and ultralow-power nearest neighbor search with full adaptivity of the template data format, has been proposed and fabricated using the 90 nm CMOS/70 nm perpendicular-magnetic-tunnel-junction hybrid process. A truly compact current-mode circuitry is developed to realize flexibly controllable and high-parallel similarity evaluation, which makes the NV-AM adaptable to any dimensionality and component-bit of template data. A compact dual-stage time-domain minimum searching circuit is also developed, which can freely extend the system for more template data by connecting multiple NM-AM cores without additional circuits for integrated processing. Both the embedded STT-MRAM module and the computing circuit modules in this NV-AM chip are synchronously power-gated to completely eliminate standby power and maximally reduce operation power by only activating the currently accessed circuit blocks. The operations of a prototype chip at 40 MHz are demonstrated by measurement. The average operation power is only 130 µW, and the circuit density is less than 11 µm2/bit. Compared with the latest conventional works in both volatile and nonvolatile approaches, more than 31.3% circuit area reductions and 99.2% power improvements are achieved, respectively. Further power performance analyses are discussed, which verify the special superiority of the proposed NV-AM in low-power and large-memory-based VLSIs.

  12. a-SiNx:H-based ultra-low power resistive random access memory with tunable Si dangling bond conduction paths.

    PubMed

    Jiang, Xiaofan; Ma, Zhongyuan; Xu, Jun; Chen, Kunji; Xu, Ling; Li, Wei; Huang, Xinfan; Feng, Duan

    2015-10-28

    The realization of ultra-low power Si-based resistive switching memory technology will be a milestone in the development of next generation non-volatile memory. Here we show that a high performance and ultra-low power resistive random access memory (RRAM) based on an Al/a-SiNx:H/p(+)-Si structure can be achieved by tuning the Si dangling bond conduction paths. We reveal the intrinsic relationship between the Si dangling bonds and the N/Si ratio x for the a-SiNx:H films, which ensures that the programming current can be reduced to less than 1 μA by increasing the value of x. Theoretically calculated current-voltage (I-V) curves combined with the temperature dependence of the I-V characteristics confirm that, for the low-resistance state (LRS), the Si dangling bond conduction paths obey the trap-assisted tunneling model. In the high-resistance state (HRS), conduction is dominated by either hopping or Poole-Frenkel (P-F) processes. Our introduction of hydrogen in the a-SiNx:H layer provides a new way to control the Si dangling bond conduction paths, and thus opens up a research field for ultra-low power Si-based RRAM.

  13. Ion beam synthesis of indium-oxide nanocrystals for improvement of oxide resistive random-access memories

    NASA Astrophysics Data System (ADS)

    Bonafos, C.; Benassayag, G.; Cours, R.; Pécassou, B.; Guenery, P. V.; Baboux, N.; Militaru, L.; Souifi, A.; Cossec, E.; Hamga, K.; Ecoffey, S.; Drouin, D.

    2018-01-01

    We report on the direct ion beam synthesis of a delta-layer of indium oxide nanocrystals (In2O3-NCs) in silica matrices by using ultra-low energy ion implantation. The formation of the indium oxide phase can be explained by (i) the affinity of indium with oxygen, (ii) the generation of a high excess of oxygen recoils generated by the implantation process in the region where the nanocrystals are formed and (iii) the proximity of the indium-based nanoparticles with the free surface and oxidation from the air. Taking advantage of the selective diffusivity of implanted indium in SiO2 with respect to Si3N4, In2O3-NCs have been inserted in the SiO2 switching oxide of micrometric planar oxide-based resistive random access memory (OxRAM) devices fabricated using the nanodamascene process. Preliminary electrical measurements show switch voltage from high to low resistance state. The devices with In2O3-NCs have been cycled 5 times with identical operating voltages and RESET current meanwhile no switch has been observed for non implanted devices. This first measurement of switching is very promising for the concept of In2O3-NCs based OxRAM memories.

  14. Individual differences in susceptibility to false memories: The effect of memory specificity.

    PubMed

    Dewhurst, Stephen A; Anderson, Rachel J; Berry, Donna M; Garner, Sarah R

    2017-06-25

    Previous research has highlighted the wide individual variability in susceptibility to the false memories produced by the Deese/Roediger-McDermott (DRM) procedure [Deese, J. (1959). On the prediction of occurrence of particular verbal intrusions in immediate recall. Journal of Experimental Psychology, 58, 17-22; Roediger, H. L., III, & McDermott, K. B. (1995). Creating false memories: Remembering words not presented in lists. Journal of Experimental Psychology: Learning, Memory, & Cognition, 21, 803-814]. The current study investigated whether susceptibility to false memories is influenced by individual differences in the specificity of autobiographical memory retrieval. Memory specificity was measured using the Sentence Completion for Events from the Past Test (SCEPT) [Raes, F., Hermans, D., Williams, J. M. G., & Eelen, P. (2007). A sentence completion procedure as an alternative to the Autobiographical Memory Test for assessing overgeneral memory in non-clinical populations. Memory, 15, 495-507]. Memory specificity did not correlate with correct recognition, but a specific retrieval style was positively correlated with levels of false recognition. It is proposed that the contextual details that frequently accompany false memories of nonstudied lures are more accessible in individuals with specific retrieval styles.

  15. Integrated Vertical Bloch Line (VBL) memory

    NASA Technical Reports Server (NTRS)

    Katti, R. R.; Wu, J. C.; Stadler, H. L.

    1991-01-01

    Vertical Bloch Line (VBL) Memory is a recently conceived, integrated, solid state, block access, VLSI memory which offers the potential of 1 Gbit/sq cm areal storage density, data rates of hundreds of megabits/sec, and submillisecond average access time simultaneously at relatively low mass, volume, and power values when compared to alternative technologies. VBLs are micromagnetic structures within magnetic domain walls which can be manipulated using magnetic fields from integrated conductors. The presence or absence of BVL pairs are used to store binary information. At present, efforts are being directed at developing a single chip memory using 25 Mbit/sq cm technology in magnetic garnet material which integrates, at a single operating point, the writing, storage, reading, and amplification functions needed in a memory. The current design architecture, functional elements, and supercomputer simulation results are described which are used to assist the design process.

  16. Enhancing Memory in Your Students: COMPOSE Yourself!

    ERIC Educational Resources Information Center

    Rotter, Kathleen M.

    2009-01-01

    The essence of teaching is, in fact, creating new memories for your students. The teacher's role is to help students store the correct information (memories) in ways that make recall and future access and use likely. Therefore, choosing techniques to enhance memory is possibly the most critical aspect of instructional design. COMPOSE is an acronym…

  17. Accessing global data from accelerator devices

    DOEpatents

    Bertolli, Carlo; O'Brien, John K.; Sallenave, Olivier H.; Sura, Zehra N.

    2016-12-06

    An aspect includes a table of contents (TOC) that was generated by a compiler being received at an accelerator device. The TOC includes an address of global data in a host memory space. The global data is copied from the address in the host memory space to an address in the device memory space. The address in the host memory space is obtained from the received TOC. The received TOC is updated to indicate that global data is stored at the address in the device memory space. A kernel that accesses the global data from the address in the device memory space is executed. The address in the device memory space is obtained based on contents of the updated TOC. When the executing is completed, the global data from the address in the device memory space is copied to the address in the host memory space.

  18. Accessing global data from accelerator devices

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Bertolli, Carlo; O'Brien, John K.; Sallenave, Olivier H.

    2016-12-06

    An aspect includes a table of contents (TOC) that was generated by a compiler being received at an accelerator device. The TOC includes an address of global data in a host memory space. The global data is copied from the address in the host memory space to an address in the device memory space. The address in the host memory space is obtained from the received TOC. The received TOC is updated to indicate that global data is stored at the address in the device memory space. A kernel that accesses the global data from the address in the devicemore » memory space is executed. The address in the device memory space is obtained based on contents of the updated TOC. When the executing is completed, the global data from the address in the device memory space is copied to the address in the host memory space.« less

  19. Organic Ferroelectric-Based 1T1T Random Access Memory Cell Employing a Common Dielectric Layer Overcoming the Half-Selection Problem.

    PubMed

    Zhao, Qiang; Wang, Hanlin; Ni, Zhenjie; Liu, Jie; Zhen, Yonggang; Zhang, Xiaotao; Jiang, Lang; Li, Rongjin; Dong, Huanli; Hu, Wenping

    2017-09-01

    Organic electronics based on poly(vinylidenefluoride/trifluoroethylene) (P(VDF-TrFE)) dielectric is facing great challenges in flexible circuits. As one indispensable part of integrated circuits, there is an urgent demand for low-cost and easy-fabrication nonvolatile memory devices. A breakthrough is made on a novel ferroelectric random access memory cell (1T1T FeRAM cell) consisting of one selection transistor and one ferroelectric memory transistor in order to overcome the half-selection problem. Unlike complicated manufacturing using multiple dielectrics, this system simplifies 1T1T FeRAM cell fabrication using one common dielectric. To achieve this goal, a strategy for semiconductor/insulator (S/I) interface modulation is put forward and applied to nonhysteretic selection transistors with high performances for driving or addressing purposes. As a result, high hole mobility of 3.81 cm 2 V -1 s -1 (average) for 2,6-diphenylanthracene (DPA) and electron mobility of 0.124 cm 2 V -1 s -1 (average) for N,N'-1H,1H-perfluorobutyl dicyanoperylenecarboxydiimide (PDI-FCN 2 ) are obtained in selection transistors. In this work, we demonstrate this technology's potential for organic ferroelectric-based pixelated memory module fabrication. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  20. Nanoscale chemical state analysis of resistance random access memory device reacting with Ti

    NASA Astrophysics Data System (ADS)

    Shima, Hisashi; Nakano, Takashi; Akinaga, Hiro

    2010-05-01

    The thermal stability of the resistance random access memory material in the reducing atmosphere at the elevated temperature was improved by the addition of Ti. The unipolar resistance switching before and after the postdeposition annealing (PDA) process at 400 °C was confirmed in Pt/CoO/Ti(5 nm)/Pt device, while the severe degradation of the initial resistance occurs in the Pt/CoO/Pt and Pt/CoO/Ti(50 nm)/Pt devices. By investigating the chemical bonding states of Co, O, and Ti using electron energy loss spectroscopy combined with transmission electron microscopy, it was revealed that excess Ti induces the formation of metallic Co, while the thermal stability was improved by trace Ti. Moreover, it was indicated that the filamentary conduction path can be thermally induced after PDA in the oxide layer by analyzing electrical properties of the degraded devices. The adjustment of the reducing elements is quite essential in order to participate in their profits.

  1. Plated wire memory subsystem

    NASA Technical Reports Server (NTRS)

    Carpenter, K. H.

    1974-01-01

    The design, construction, and test history of a 4096 word by 18 bit random access NDRO Plated Wire Memory for use in conjunction with a spacecraft input/output and central processing unit is reported. A technical and functional description is given along with diagrams illustrating layout and systems operation. Test data is shown on the procedures and results of system level and memory stack testing, and hybrid circuit screening. A comparison of the most significant physical and performance characteristics of the memory unit versus the specified requirements is also included.

  2. Plated wire memory subsystem

    NASA Technical Reports Server (NTRS)

    Reynolds, L.; Tweed, H.

    1972-01-01

    The work performed entailed the design, development, construction and testing of a 4000 word by 18 bit random access, NDRO plated wire memory for use in conjunction with a spacecraft imput/output unit and central processing unit. The primary design parameters, in order of importance, were high reliability, low power, volume and weight. A single memory unit, referred to as a qualification model, was delivered.

  3. Asymmetrical access to color and location in visual working memory.

    PubMed

    Rajsic, Jason; Wilson, Daryl E

    2014-10-01

    Models of visual working memory (VWM) have benefitted greatly from the use of the delayed-matching paradigm. However, in this task, the ability to recall a probed feature is confounded with the ability to maintain the proper binding between the feature that is to be reported and the feature (typically location) that is used to cue a particular item for report. Given that location is typically used as a cue-feature, we used the delayed-estimation paradigm to compare memory for location to memory for color, rotating which feature was used as a cue and which was reported. Our results revealed several novel findings: 1) the likelihood of reporting a probed object's feature was superior when reporting location with a color cue than when reporting color with a location cue; 2) location report errors were composed entirely of swap errors, with little to no random location reports; and 3) both colour and location reports greatly benefitted from the presence of nonprobed items at test. This last finding suggests that it is uncertainty over the bindings between locations and colors at memory retrieval that drive swap errors, not at encoding. We interpret our findings as consistent with a representational architecture that nests remembered object features within remembered locations.

  4. Static power reduction for midpoint-terminated busses

    DOEpatents

    Coteus, Paul W [Yorktown Heights, NY; Takken, Todd [Brewster, NY

    2011-01-18

    A memory system is disclosed which is comprised of a memory controller and addressable memory devices such as DRAMs. The invention provides a programmable register to control the high vs. low drive state of each bit of a memory system address and control bus during periods of bus inactivity. In this way, termination voltage supply current can be minimized, while permitting selected bus bits to be driven to a required state. This minimizes termination power dissipation while not affecting memory system performance. The technique can be extended to work for other high-speed busses as well.

  5. Blanket Gate Would Address Blocks Of Memory

    NASA Technical Reports Server (NTRS)

    Lambe, John; Moopenn, Alexander; Thakoor, Anilkumar P.

    1988-01-01

    Circuit-chip area used more efficiently. Proposed gate structure selectively allows and restricts access to blocks of memory in electronic neural-type network. By breaking memory into independent blocks, gate greatly simplifies problem of reading from and writing to memory. Since blocks not used simultaneously, share operational amplifiers that prompt and read information stored in memory cells. Fewer operational amplifiers needed, and chip area occupied reduced correspondingly. Cost per bit drops as result.

  6. a-SiNx:H-based ultra-low power resistive random access memory with tunable Si dangling bond conduction paths

    PubMed Central

    Jiang, Xiaofan; Ma, Zhongyuan; Xu, Jun; Chen, Kunji; Xu, Ling; Li, Wei; Huang, Xinfan; Feng, Duan

    2015-01-01

    The realization of ultra-low power Si-based resistive switching memory technology will be a milestone in the development of next generation non-volatile memory. Here we show that a high performance and ultra-low power resistive random access memory (RRAM) based on an Al/a-SiNx:H/p+-Si structure can be achieved by tuning the Si dangling bond conduction paths. We reveal the intrinsic relationship between the Si dangling bonds and the N/Si ratio x for the a-SiNx:H films, which ensures that the programming current can be reduced to less than 1 μA by increasing the value of x. Theoretically calculated current-voltage (I–V ) curves combined with the temperature dependence of the I–V characteristics confirm that, for the low-resistance state (LRS), the Si dangling bond conduction paths obey the trap-assisted tunneling model. In the high-resistance state (HRS), conduction is dominated by either hopping or Poole–Frenkel (P–F) processes. Our introduction of hydrogen in the a-SiNx:H layer provides a new way to control the Si dangling bond conduction paths, and thus opens up a research field for ultra-low power Si-based RRAM. PMID:26508086

  7. Physical principles and current status of emerging non-volatile solid state memories

    NASA Astrophysics Data System (ADS)

    Wang, L.; Yang, C.-H.; Wen, J.

    2015-07-01

    Today the influence of non-volatile solid-state memories on persons' lives has become more prominent because of their non-volatility, low data latency, and high robustness. As a pioneering technology that is representative of non-volatile solidstate memories, flash memory has recently seen widespread application in many areas ranging from electronic appliances, such as cell phones and digital cameras, to external storage devices such as universal serial bus (USB) memory. Moreover, owing to its large storage capacity, it is expected that in the near future, flash memory will replace hard-disk drives as a dominant technology in the mass storage market, especially because of recently emerging solid-state drives. However, the rapid growth of the global digital data has led to the need for flash memories to have larger storage capacity, thus requiring a further downscaling of the cell size. Such a miniaturization is expected to be extremely difficult because of the well-known scaling limit of flash memories. It is therefore necessary to either explore innovative technologies that can extend the areal density of flash memories beyond the scaling limits, or to vigorously develop alternative non-volatile solid-state memories including ferroelectric random-access memory, magnetoresistive random-access memory, phase-change random-access memory, and resistive random-access memory. In this paper, we review the physical principles of flash memories and their technical challenges that affect our ability to enhance the storage capacity. We then present a detailed discussion of novel technologies that can extend the storage density of flash memories beyond the commonly accepted limits. In each case, we subsequently discuss the physical principles of these new types of non-volatile solid-state memories as well as their respective merits and weakness when utilized for data storage applications. Finally, we predict the future prospects for the aforementioned solid-state memories for

  8. Active non-volatile memory post-processing

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Kannan, Sudarsun; Milojicic, Dejan S.; Talwar, Vanish

    A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.

  9. Magnetic vortex racetrack memory

    NASA Astrophysics Data System (ADS)

    Geng, Liwei D.; Jin, Yongmei M.

    2017-02-01

    We report a new type of racetrack memory based on current-controlled movement of magnetic vortices in magnetic nanowires with rectangular cross-section and weak perpendicular anisotropy. Data are stored through the core polarity of vortices and each vortex carries a data bit. Besides high density, non-volatility, fast data access, and low power as offered by domain wall racetrack memory, magnetic vortex racetrack memory has additional advantages of no need for constrictions to define data bits, changeable information density, adjustable current magnitude for data propagation, and versatile means of ultrafast vortex core switching. By using micromagnetic simulations, current-controlled motion of magnetic vortices in cobalt nanowire is demonstrated for racetrack memory applications.

  10. Short-term memory to long-term memory transition in a nanoscale memristor.

    PubMed

    Chang, Ting; Jo, Sung-Hyun; Lu, Wei

    2011-09-27

    "Memory" is an essential building block in learning and decision-making in biological systems. Unlike modern semiconductor memory devices, needless to say, human memory is by no means eternal. Yet, forgetfulness is not always a disadvantage since it releases memory storage for more important or more frequently accessed pieces of information and is thought to be necessary for individuals to adapt to new environments. Eventually, only memories that are of significance are transformed from short-term memory into long-term memory through repeated stimulation. In this study, we show experimentally that the retention loss in a nanoscale memristor device bears striking resemblance to memory loss in biological systems. By stimulating the memristor with repeated voltage pulses, we observe an effect analogous to memory transition in biological systems with much improved retention time accompanied by additional structural changes in the memristor. We verify that not only the shape or the total number of stimuli is influential, but also the time interval between stimulation pulses (i.e., the stimulation rate) plays a crucial role in determining the effectiveness of the transition. The memory enhancement and transition of the memristor device was explained from the microscopic picture of impurity redistribution and can be qualitatively described by the same equations governing biological memories. © 2011 American Chemical Society

  11. Influence of Thermal Annealing Treatment on Bipolar Switching Properties of Vanadium Oxide Thin-Film Resistance Random-Access Memory Devices

    NASA Astrophysics Data System (ADS)

    Chen, Kai-Huang; Cheng, Chien-Min; Kao, Ming-Cheng; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Wu, Sean; Su, Feng-Yi

    2017-04-01

    The bipolar switching properties and electrical conduction mechanism of vanadium oxide thin-film resistive random-access memory (RRAM) devices obtained using a rapid thermal annealing (RTA) process have been investigated in high-resistive status/low-resistive status (HRS/LRS) and are discussed herein. In addition, the resistance switching properties and quality improvement of the vanadium oxide thin-film RRAM devices were measured by x-ray diffraction (XRD) analysis, x-ray photoelectron spectrometry (XPS), scanning electron microscopy (SEM), atomic force microscopy (AFM), and current-voltage ( I- V) measurements. The activation energy of the hopping conduction mechanism in the devices was investigated based on Arrhenius plots in HRS and LRS. The hopping conduction distance and activation energy barrier were obtained as 12 nm and 45 meV, respectively. The thermal annealing process is recognized as a candidate method for fabrication of thin-film RRAM devices, being compatible with integrated circuit technology for nonvolatile memory devices.

  12. Age, memory type, and the phenomenology of autobiographical memory: findings from an Italian sample.

    PubMed

    Montebarocci, Ornella; Luchetti, Martina; Sutin, Angelina R

    2014-01-01

    The present research explored differences in phenomenology between two types of memories, a general self-defining memory and an earliest childhood memory. A sample of 76 Italian participants were selected and categorised into two age groups: 20-30 years and 31-40 years. The Memory Experiences Questionnaire (MEQ) was administered, taking note of latency and duration times of the narratives. Consistent with the literature, the self-defining memory differed significantly from the earliest childhood memory in terms of phenomenology, with the recency of the memory associated with more intense phenomenological experience. The self-defining memory took longer to retrieve and narrate than the earliest childhood memory. Meaningful differences also emerged between the two age groups: Participants in their 30s rated their self-defining memory as more vivid, coherent, and accessible than participants in their 20s. According to latency findings, these differences suggest an expanded period of identity consolidation for younger adults. Further applications of the MEQ should be carried out to replicate these results with other samples of young adults.

  13. Logical Access Control Mechanisms in Computer Systems.

    ERIC Educational Resources Information Center

    Hsiao, David K.

    The subject of access control mechanisms in computer systems is concerned with effective means to protect the anonymity of private information on the one hand, and to regulate the access to shareable information on the other hand. Effective means for access control may be considered on three levels: memory, process and logical. This report is a…

  14. Providing the Public with Online Access to Large Bibliographic Data Bases.

    ERIC Educational Resources Information Center

    Firschein, Oscar; Summit, Roger K.

    DIALOG, an interactive, computer-based information retrieval language, consists of a series of computer programs designed to make use of direct access memory devices in order to provide the user with a rapid means of identifying records within a specific memory bank. Using the system, a library user can be provided access to sixteen distinct and…

  15. Implementation of Ferroelectric Memories for Space Applications

    NASA Technical Reports Server (NTRS)

    Philpy, Stephen C.; Derbenwick, Gary F.; Kamp, David A.; Isaacson, Alan F.

    2000-01-01

    Ferroelectric random access semiconductor memories (FeRAMs) are an ideal nonvolatile solution for space applications. These memories have low power performance, high endurance and fast write times. By combining commercial ferroelectric memory technology with radiation hardened CMOS technology, nonvolatile semiconductor memories for space applications can be attained. Of the few radiation hardened semiconductor manufacturers, none have embraced the development of radiation hardened FeRAMs, due a limited commercial space market and funding limitations. Government funding may be necessary to assure the development of radiation hardened ferroelectric memories for space applications.

  16. MemAxes: Visualization and Analytics for Characterizing Complex Memory Performance Behaviors.

    PubMed

    Gimenez, Alfredo; Gamblin, Todd; Jusufi, Ilir; Bhatele, Abhinav; Schulz, Martin; Bremer, Peer-Timo; Hamann, Bernd

    2018-07-01

    Memory performance is often a major bottleneck for high-performance computing (HPC) applications. Deepening memory hierarchies, complex memory management, and non-uniform access times have made memory performance behavior difficult to characterize, and users require novel, sophisticated tools to analyze and optimize this aspect of their codes. Existing tools target only specific factors of memory performance, such as hardware layout, allocations, or access instructions. However, today's tools do not suffice to characterize the complex relationships between these factors. Further, they require advanced expertise to be used effectively. We present MemAxes, a tool based on a novel approach for analytic-driven visualization of memory performance data. MemAxes uniquely allows users to analyze the different aspects related to memory performance by providing multiple visual contexts for a centralized dataset. We define mappings of sampled memory access data to new and existing visual metaphors, each of which enabling a user to perform different analysis tasks. We present methods to guide user interaction by scoring subsets of the data based on known performance problems. This scoring is used to provide visual cues and automatically extract clusters of interest. We designed MemAxes in collaboration with experts in HPC and demonstrate its effectiveness in case studies.

  17. Quantifying data retention of perpendicular spin-transfer-torque magnetic random access memory chips using an effective thermal stability factor method

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Thomas, Luc, E-mail: luc.thomas@headway.com; Jan, Guenole; Le, Son

    The thermal stability of perpendicular Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) devices is investigated at chip level. Experimental data are analyzed in the framework of the Néel-Brown model including distributions of the thermal stability factor Δ. We show that in the low error rate regime important for applications, the effect of distributions of Δ can be described by a single quantity, the effective thermal stability factor Δ{sub eff}, which encompasses both the median and the standard deviation of the distributions. Data retention of memory chips can be assessed accurately by measuring Δ{sub eff} as a function of device diameter andmore » temperature. We apply this method to show that 54 nm devices based on our perpendicular STT-MRAM design meet our 10 year data retention target up to 120 °C.« less

  18. Optically Addressable, Ferroelectric Memory With NDRO

    NASA Technical Reports Server (NTRS)

    Thakoor, Sarita

    1994-01-01

    For readout, memory cells addressed via on-chip semiconductor lasers. Proposed thin-film ferroelectric memory device features nonvolatile storage, optically addressable, nondestructive readout (NDRO) with fast access, and low vulnerability to damage by ionizing radiation. Polarization switched during recording and erasure, but not during readout. As result, readout would not destroy contents of memory, and operating life in specific "read-intensive" applications increased up to estimated 10 to the 16th power cycles.

  19. Monitoring oxygen movement by Raman spectroscopy of resistive random access memory with a graphene-inserted electrode.

    PubMed

    Tian, He; Chen, Hong-Yu; Gao, Bin; Yu, Shimeng; Liang, Jiale; Yang, Yi; Xie, Dan; Kang, Jinfeng; Ren, Tian-Ling; Zhang, Yuegang; Wong, H-S Philip

    2013-02-13

    In this paper, we employed Ramen spectroscopy to monitor oxygen movement at the electrode/oxide interface by inserting single-layer graphene (SLG). Raman area mapping and single-point measurements show noticeable changes in the D-band, G-band, and 2D-band signals of the SLG during consecutive electrical programming repeated for nine cycles. In addition, the inserted SLG enables the reduction of RESET current by 22 times and programming power consumption by 47 times. Collectively, our results show that monitoring the oxygen movement by Raman spectroscopy for a resistive random access memory (RRAM) is made possible by inserting a single-layer graphene at electrode/oxide interface. This may open up an important analysis tool for investigation of switching mechanism of RRAM.

  20. Long-term memory following transient global amnesia: an investigation of episodic and semantic memory.

    PubMed

    Guillery-Girard, B; Quinette, P; Desgranges, B; Piolino, P; Viader, F; de la Sayette, V; Eustache, F

    2006-11-01

    Several studies noted persistence of memory impairment following an episode of transient global amnesia (TGA) with standard tests. To specify long-term memory impairments in a group of patients selected with stringent criteria. Both retrograde and anterograde memory were investigated in 32 patients 13-67 months after a TGA episode with original tasks encompassing retrograde semantic memory (academic, public and personal knowledge), retrograde episodic memory (autobiographical events) and anterograde episodic memory. Patients had preserved academic and public knowledge. Pathological scores were obtained in personal verbal fluency for the two most recent periods, and patients produced less autobiographical events than controls. However, when they were provided time to detail, memories were as episodic as in controls regardless of their remoteness. Anterograde episodic tasks revealed a mild but significant impairment of the capacity of re-living the condition of encoding, i.e. the moment at which words were presented. Patients who have suffered from an episode of TGA manifest deficits of memory focused on the retrieval of both recent semantic information and episodic memories and especially the capacity of re-living. These deficits may not result from a deterioration of memory per se but rather from difficulties in accessing memories.

  1. Saying what’s on your mind: Working memory effects on sentence production

    PubMed Central

    Slevc, L. Robert

    2011-01-01

    The role of working memory (WM) in sentence comprehension has received considerable interest, but little work has investigated how sentence production relies on memory mechanisms. These three experiments investigated speakers’ tendency to produce syntactic structures that allow for early production of material that is accessible in memory. In Experiment 1, speakers produced accessible information early less often when under a verbal WM load than when under no load. Experiment 2 found the same pattern for given-new ordering, i.e., when accessibility was manipulated by making information given. Experiment 3 addressed the possibility that these effects do not reflect WM mechanisms but rather increased task difficulty by relying on the distinction between verbal and spatial WM: Speakers’ tendency to produce sentences respecting given-new ordering was reduced more by a verbal than by a spatial WM load. These patterns show that accessibility effects do in fact reflect accessibility in verbal WM, and that representations in sentence production are vulnerable to interference from other information in memory. PMID:21767058

  2. Chromatin accessibility prediction via convolutional long short-term memory networks with k-mer embedding

    PubMed Central

    Min, Xu; Zeng, Wanwen; Chen, Ning; Chen, Ting; Jiang, Rui

    2017-01-01

    Abstract Motivation: Experimental techniques for measuring chromatin accessibility are expensive and time consuming, appealing for the development of computational approaches to predict open chromatin regions from DNA sequences. Along this direction, existing methods fall into two classes: one based on handcrafted k-mer features and the other based on convolutional neural networks. Although both categories have shown good performance in specific applications thus far, there still lacks a comprehensive framework to integrate useful k-mer co-occurrence information with recent advances in deep learning. Results: We fill this gap by addressing the problem of chromatin accessibility prediction with a convolutional Long Short-Term Memory (LSTM) network with k-mer embedding. We first split DNA sequences into k-mers and pre-train k-mer embedding vectors based on the co-occurrence matrix of k-mers by using an unsupervised representation learning approach. We then construct a supervised deep learning architecture comprised of an embedding layer, three convolutional layers and a Bidirectional LSTM (BLSTM) layer for feature learning and classification. We demonstrate that our method gains high-quality fixed-length features from variable-length sequences and consistently outperforms baseline methods. We show that k-mer embedding can effectively enhance model performance by exploring different embedding strategies. We also prove the efficacy of both the convolution and the BLSTM layers by comparing two variations of the network architecture. We confirm the robustness of our model to hyper-parameters by performing sensitivity analysis. We hope our method can eventually reinforce our understanding of employing deep learning in genomic studies and shed light on research regarding mechanisms of chromatin accessibility. Availability and implementation: The source code can be downloaded from https://github.com/minxueric/ismb2017_lstm. Contact: tingchen@tsinghua.edu.cn or ruijiang

  3. Investigation of multi-state charge-storage properties of redox-active organic molecules in silicon-molecular hybrid devices for DRAM and Flash applications

    NASA Astrophysics Data System (ADS)

    Gowda, Srivardhan Shivappa

    Molecular electronics has recently spawned a considerable amount of interest with several molecules possessing charge-conduction and charge-storage properties proposed for use in electronic devices. Hybrid silicon-molecular technology has the promise of augmenting the current silicon technology and provide for a transitional path to future molecule-only technology. The focus of this dissertation work has been on developing a class of hybrid silicon-molecular electronic devices for DRAM and Flash memory applications utilizing redox-active molecules. This work exploits the ability of molecules to store charges with single-electron precision at room temperature. The hybrid devices are fabricated by forming self-assembled monolayers of redox-active molecules on Si and oxide (SiO2 and HfO2) surfaces via formation of covalent linkages. The molecules possess discrete quantum states from which electrons can tunnel to the Si substrate at discrete applied voltages (oxidation process, cell write), leaving behind a positively charged layer of molecules. The reduction (erase) process, which is the process of electrons tunneling back from Si to the molecules, neutralizes the positively charged molecular monolayer. Hybrid silicon-molecular capacitor test structures were electrically characterized with an electrolyte gate using cyclic voltammetry (CyV) and impedance spectroscopy (CV) techniques. The redox voltages, kinetics (write/erase speeds) and charge-retention characteristics were found to be strongly dependent on the Si doping type and densities, and ambient light. It was also determined that the redox energy states in the molecules communicate with the valence band of the Si substrate. This allows tuning of write and read states by modulating minority carriers in n- and p-Si substrates. Ultra-thin dielectric tunnel barriers (SiO2, HfO2) were placed between the molecules and the Si substrate to augment charge-retention for Flash memory applications. The redox response was

  4. Non-Volatile Memory Technology Symposium 2001: Proceedings

    NASA Technical Reports Server (NTRS)

    Aranki, Nazeeh; Daud, Taher; Strauss, Karl

    2001-01-01

    This publication contains the proceedings for the Non-Volatile Memory Technology Symposium 2001 that was held on November 7-8, 2001 in San Diego, CA. The proceedings contains a a wide range of papers that cover current and new memory technologies including Flash memories, Magnetic Random Access Memories (MRAM and GMRAM), Ferro-electric RAM (FeRAM), and Chalcogenide RAM (CRAM). The papers presented in the proceedings address the use of these technologies for space applications as well as radiation effects and packaging issues.

  5. Full-switching FSF-type superconducting spin-triplet magnetic random access memory element

    NASA Astrophysics Data System (ADS)

    Lenk, D.; Morari, R.; Zdravkov, V. I.; Ullrich, A.; Khaydukov, Yu.; Obermeier, G.; Müller, C.; Sidorenko, A. S.; von Nidda, H.-A. Krug; Horn, S.; Tagirov, L. R.; Tidecks, R.

    2017-11-01

    In the present work a superconducting Co/CoOx/Cu41Ni59 /Nb/Cu41Ni59 nanoscale thin film heterostructure is investigated, which exhibits a superconducting transition temperature, Tc, depending on the history of magnetic field applied parallel to the film plane. In more detail, around zero applied field, Tc is lower when the field is changed from negative to positive polarity (with respect to the cooling field), compared to the opposite case. We interpret this finding as the result of the generation of the odd-in-frequency triplet component of superconductivity arising at noncollinear orientation of the magnetizations in the Cu41Ni59 layer adjacent to the CoOx layer. This interpretation is supported by superconducting quantum interference device magnetometry, which revealed a correlation between details of the magnetic structure and the observed superconducting spin-valve effects. Readout of information is possible at zero applied field and, thus, no permanent field is required to stabilize both states. Consequently, this system represents a superconducting magnetic random access memory element for superconducting electronics. By applying increased transport currents, the system can be driven to the full switching mode between the completely superconducting and the normal state.

  6. Comparison and statistical analysis of four write stability metrics in bulk CMOS static random access memory cells

    NASA Astrophysics Data System (ADS)

    Qiu, Hao; Mizutani, Tomoko; Saraya, Takuya; Hiramoto, Toshiro

    2015-04-01

    The commonly used four metrics for write stability were measured and compared based on the same set of 2048 (2k) six-transistor (6T) static random access memory (SRAM) cells by the 65 nm bulk technology. The preferred one should be effective for yield estimation and help predict edge of stability. Results have demonstrated that all metrics share the same worst SRAM cell. On the other hand, compared to butterfly curve with non-normality and write N-curve where no cell state flip happens, bit-line and word-line margins have good normality as well as almost perfect correlation. As a result, both bit line method and word line method prove themselves preferred write stability metrics.

  7. Library API for Z-Order Memory Layout

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Bethel, E. Wes

    This library provides a simple-to-use API for implementing an altnerative to traditional row-major order in-memory layout, one based on a Morton- order space filling curve (SFC) , specifically, a Z-order variant of the Morton order curve. The library enables programmers to, after a simple initialization step, to convert a multidimensional array from row-major to Z- order layouts, then use a single, generic API call to access data from any arbitrary (i,j,k) location from within the array, whether it it be stored in row- major or z-order format. The motivation for using a SFC in-memory layout is for improved spatial locality,more » which results in increased use of local high speed cache memory. The basic idea is that with row-major order layouts, a data access to some location that is nearby in index space is likely far away in physical memory, resulting in poor spatial locality and slow runtime. On the other hand, with a SFC-based layout, accesses that are nearby in index space are much more likely to also be nearby in physical memory, resulting in much better spatial locality, and better runtime performance. Numerous studies over the years have shown significant runtime performance gains are realized by using a SFC-based memory layout compared to a row-major layout, sometimes by as much as 50%, which result from the better use of the memory and cache hierarchy that are attendant with a SFC-based layout (see, for example, [Beth2012]). This library implementation is intended for use with codes that work with structured, array-based data in 2 or 3 dimensions. It is not appropriate for use with unstructured or point-based data.« less

  8. Performance of Compiler-Assisted Memory Safety Checking

    DTIC Science & Technology

    2014-08-01

    software developer has in mind a particular object to which the pointer should point, the intended referent. A memory access error occurs when an ac...Performance of Compiler-Assisted Memory Safety Checking David Keaton Robert C. Seacord August 2014 TECHNICAL NOTE CMU/SEI-2014-TN...based memory safety checking tool and the performance that can be achieved with two such tools whose source code is freely available. The note then

  9. The influence of training and experience on memory strategy.

    PubMed

    Patrick, John; Morgan, Phillip L; Smy, Victoria; Tiley, Leyanne; Seeby, Helen; Patrick, Tanya; Evans, Jonathan

    2015-07-01

    This paper investigates whether, and if so how much, prior training and experience overwrite the influence of the constraints of the task environment on strategy deployment. This evidence is relevant to the theory of soft constraints that focuses on the role of constraints in the task environment (Gray, Simms, Fu, & Schoelles, Psychological Review, 113: 461-482, 2006). The theory explains how an increase in the cost of accessing information induces a more memory-based strategy involving more encoding and planning. Experiments 1 and 3 adopt a traditional training and transfer design using the Blocks World Task in which participants were exposed to training trials involving a 2.5-s delay in accessing goal-state information before encountering transfer trials in which there was no access delay. The effect of prior training was assessed by the degree of memory-based strategy adopted in the transfer trials. Training with an access delay had a substantial carry-over effect and increased the subsequent degree of memory-based strategy adopted in the transfer environment. However, such effects do not necessarily occur if goal-state access cost in training is less costly than in transfer trials (Experiment 2). Experiment 4 used a fine-grained intra-trial design to examine the effect of experiencing access cost on one, two, or three occasions within the same trial and found that such experience on two consecutive occasions was sufficient to induce a more memory-based strategy. This paper establishes some effects of training that are relevant to the soft constraints theory and also discusses practical implications.

  10. Electrical characteristics of paraelectric lead lanthanum zirconium titanate thin films for dynamic random access memory applications

    NASA Astrophysics Data System (ADS)

    Jones, R. E., Jr.; Maniar, P. D.; Olowolafe, J. O.; Campbell, A. C.; Mogab, C. J.

    1992-02-01

    Paraelectric lead lanthanum zirconium titanate (PLZT) films, 150 nm thick, were deposited using a spin-coat, sol-gel process followed by a 650 °C oxygen anneal. X-ray diffraction indicated complete conversion to the perovskite phase. Sputter-deposited platinum electrodes were employed with the PLZT films to form thin-film capacitors with the best combination of high charge storage density (26.1 μC/cm2 at 3 V and 36.4 μC/cm2 at 5 V) and leakage current density (0.2 μA/cm2 at 3 V and 0.5 μA/cm2 at 5 V ) reported to date. The electrical characteristics of these thin-film capacitors meet the requirements for a planar bit cell capacitor for 64-Mbit dynamic random access memories.

  11. Improving the effectiveness of an interruption lag by inducing a memory-based strategy.

    PubMed

    Morgan, Phillip L; Patrick, John; Tiley, Leyanne

    2013-01-01

    The memory for goals model (Altmann & Trafton, 2002) posits the importance of a short delay (the 'interruption lag') before an interrupting task to encode suspended goals for retrieval post-interruption. Two experiments used the theory of soft constraints (Gray, Simms, Fu & Schoelles, 2006) to investigate whether the efficacy of an interruption lag could be improved by increasing goal-state access cost to induce a more memory-based encoding strategy. Both experiments used a copying task with three access cost conditions (Low, Medium, and High) and a 5-s interruption lag with a no lag control condition. Experiment 1 found that the participants in the High access cost condition resumed more interrupted trials and executed more actions correctly from memory when coupled with an interruption lag. Experiment 2 used a prospective memory test post-interruption and an eyetracker recorded gaze activity during the interruption lag. The participants in the High access cost condition with an interruption lag were best at encoding target information during the interruption lag, evidenced by higher scores on the prospective memory measure and more gaze activity on the goal-state during the interruption lag. Theoretical and practical issues regarding the use of goal-state access cost and an interruption lag are discussed. Copyright © 2012. Published by Elsevier B.V.

  12. Columbia Crew added to Astronaut Memorial Mirror

    NASA Image and Video Library

    2003-07-15

    Workers add to the Astronaut Memorial Mirror the names of the Columbia crew who died in the STS-107 accident. Dedicated May 9, 1991, the Astronaut Memorial honors U.S. astronauts who gave their lives for space exploration. The "Space Mirror," 42 1/2 feet high by 50 feet wide, illuminates the names of the fallen astronauts cut through the monument's black granite surface. The Memorial Mirror is accessible through the KSC Visitor Complex.

  13. 45 CFR 2490.150 - Program accessibility: Existing facilities.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... 45 Public Welfare 4 2013-10-01 2013-10-01 false Program accessibility: Existing facilities. 2490.150 Section 2490.150 Public Welfare Regulations Relating to Public Welfare (Continued) JAMES MADISON... ACTIVITIES CONDUCTED BY THE JAMES MADISON MEMORIAL FELLOWSHIP FOUNDATION § 2490.150 Program accessibility...

  14. 45 CFR 2490.150 - Program accessibility: Existing facilities.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 45 Public Welfare 4 2012-10-01 2012-10-01 false Program accessibility: Existing facilities. 2490.150 Section 2490.150 Public Welfare Regulations Relating to Public Welfare (Continued) JAMES MADISON... ACTIVITIES CONDUCTED BY THE JAMES MADISON MEMORIAL FELLOWSHIP FOUNDATION § 2490.150 Program accessibility...

  15. 45 CFR 2490.150 - Program accessibility: Existing facilities.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 45 Public Welfare 4 2014-10-01 2014-10-01 false Program accessibility: Existing facilities. 2490.150 Section 2490.150 Public Welfare Regulations Relating to Public Welfare (Continued) JAMES MADISON... ACTIVITIES CONDUCTED BY THE JAMES MADISON MEMORIAL FELLOWSHIP FOUNDATION § 2490.150 Program accessibility...

  16. 45 CFR 2490.150 - Program accessibility: Existing facilities.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 45 Public Welfare 4 2011-10-01 2011-10-01 false Program accessibility: Existing facilities. 2490.150 Section 2490.150 Public Welfare Regulations Relating to Public Welfare (Continued) JAMES MADISON... ACTIVITIES CONDUCTED BY THE JAMES MADISON MEMORIAL FELLOWSHIP FOUNDATION § 2490.150 Program accessibility...

  17. A review of emerging non-volatile memory (NVM) technologies and applications

    NASA Astrophysics Data System (ADS)

    Chen, An

    2016-11-01

    This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

  18. Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application

    NASA Astrophysics Data System (ADS)

    Mizutani, Tomoko; Takeuchi, Kiyoshi; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

    2018-04-01

    We propose a new version of the post fabrication static random access memory (SRAM) self-improvement technique, which utilizes multiple stress application. It is demonstrated that, using a device matrix array (DMA) test element group (TEG) with intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) SRAM cells fabricated by the 65 nm technology, the lowering of data retention voltage (DRV) is more effectively achieved than using the previously proposed single stress technique.

  19. Improved characteristics of amorphous indium-gallium-zinc-oxide-based resistive random access memory using hydrogen post-annealing

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Kang, Dae Yun; Lee, Tae-Ho; Kim, Tae Geun, E-mail: tgkim1@korea.ac.kr

    The authors report an improvement in resistive switching (RS) characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO)-based resistive random access memory devices using hydrogen post-annealing. Because this a-IGZO thin film has oxygen off-stoichiometry in the form of deficient and excessive oxygen sites, the film properties can be improved by introducing hydrogen atoms through the annealing process. After hydrogen post-annealing, the device exhibited a stable bipolar RS, low-voltage set and reset operation, long retention (>10{sup 5 }s), good endurance (>10{sup 6} cycles), and a narrow distribution in each current state. The effect of hydrogen post-annealing is also investigated by analyzing the sample surface using X-raymore » photon spectroscopy and atomic force microscopy.« less

  20. An energy efficient and high speed architecture for convolution computing based on binary resistive random access memory

    NASA Astrophysics Data System (ADS)

    Liu, Chen; Han, Runze; Zhou, Zheng; Huang, Peng; Liu, Lifeng; Liu, Xiaoyan; Kang, Jinfeng

    2018-04-01

    In this work we present a novel convolution computing architecture based on metal oxide resistive random access memory (RRAM) to process the image data stored in the RRAM arrays. The proposed image storage architecture shows performances of better speed-device consumption efficiency compared with the previous kernel storage architecture. Further we improve the architecture for a high accuracy and low power computing by utilizing the binary storage and the series resistor. For a 28 × 28 image and 10 kernels with a size of 3 × 3, compared with the previous kernel storage approach, the newly proposed architecture shows excellent performances including: 1) almost 100% accuracy within 20% LRS variation and 90% HRS variation; 2) more than 67 times speed boost; 3) 71.4% energy saving.

  1. Recollection Rejection: How Children Edit Their False Memories.

    ERIC Educational Resources Information Center

    Brainerd, C. J.; Reyna, V. F.

    2002-01-01

    Presents new measure of children's use of an editing operation that suppresses false memories by accessing verbatim traces of true events. Application of the methodology showed that false-memory editing increased dramatically between early and middle childhood. Measure reacted appropriately to experimental manipulations. Developmental reductions…

  2. Retracing Memories

    ERIC Educational Resources Information Center

    Harrison, David L.

    2005-01-01

    There are plenty of paths to poetry but few are as accessible as retracing ones own memories. When students are asked to write about something they remember, they are given them the gift of choosing from events that are important enough to recall. They remember because what happened was funny or scary or embarrassing or heartbreaking or silly.…

  3. Effect of Atomic Layer Depositions (ALD)-Deposited Titanium Oxide (TiO2) Thickness on the Performance of Zr40Cu35Al15Ni10 (ZCAN)/TiO2/Indium (In)-Based Resistive Random Access Memory (RRAM) Structures

    DTIC Science & Technology

    2015-08-01

    metal structures, memristors, resistive random access memory, RRAM, titanium dioxide, Zr40Cu35Al15Ni10, ZCAN, resistive memory, tunnel junction 16...TiO2 thickness ........................6 1 1. Introduction Resistive-switching memory elements based on metal-insulator-metal (MIM) diodes ...have attracted great interest due to their potential as components for simple, inexpensive, and high-density non-volatile storage devices. MIM diodes

  4. The aftermath of memory retrieval for recycling visual working memory representations.

    PubMed

    Park, Hyung-Bum; Zhang, Weiwei; Hyun, Joo-Seok

    2017-07-01

    We examined the aftermath of accessing and retrieving a subset of information stored in visual working memory (VWM)-namely, whether detection of a mismatch between memory and perception can impair the original memory of an item while triggering recognition-induced forgetting for the remaining, untested items. For this purpose, we devised a consecutive-change detection task wherein two successive testing probes were displayed after a single set of memory items. Across two experiments utilizing different memory-testing methods (whole vs. single probe), we observed a reliable pattern of poor performance in change detection for the second test when the first test had exhibited a color change. The impairment after a color change was evident even when the same memory item was repeatedly probed; this suggests that an attention-driven, salient visual change made it difficult to reinstate the previously remembered item. The second change detection, for memory items untested during the first change detection, was also found to be inaccurate, indicating that recognition-induced forgetting had occurred for the unprobed items in VWM. In a third experiment, we conducted a task that involved change detection plus continuous recall, wherein a memory recall task was presented after the change detection task. The analyses of the distributions of recall errors with a probabilistic mixture model revealed that the memory impairments from both visual changes and recognition-induced forgetting are explained better by the stochastic loss of memory items than by their degraded resolution. These results indicate that attention-driven visual change and recognition-induced forgetting jointly influence the "recycling" of VWM representations.

  5. 76 FR 79215 - Certain Semiconductor Chips With Dram Circuitry, and Modules and Products Containing Same...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-12-21

    ... 1930, as amended, 19 U.S.C. 1337, on behalf of Elpida Memory, Inc. of Tokyo, Japan and Elpida Memory... of investigation shall be served: (a) The complainants are: Elpida Memory, Inc., Sumitomo Seimei Yaesu Bldg. 3F, 2-1 Yaesu 2-chome, Chuo-ku, Tokyo 104-0028, Japan. Elpida Memory (USA) Inc., 1175 Sonora...

  6. A Case for Tamper-Resistant and Tamper-Evident Computer Systems

    DTIC Science & Technology

    2007-02-01

    such as Kerberos is hard to apply [2] B . Gassend, G. Sub, D. Clarke, M. Dijk, and S. Devadas . Caches and Hash Trees for Efficient Memory Integrity...the block’s data from DRAM. For authentication, Merkle [14] G. Suh, D. Clarke, B . Gassend, M. van Dijk, and S. Devadas . Efficient Memory Integrity...wwi4serverwatch.com/news/article.php/ tion where a data block is encrypted or decrypted through an XOR 1399451, 2000. [11] B . Rogers, Y. Solihin

  7. 45 CFR 2490.150 - Program accessibility: Existing facilities.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... ACTIVITIES CONDUCTED BY THE JAMES MADISON MEMORIAL FELLOWSHIP FOUNDATION § 2490.150 Program accessibility: Existing facilities. (a) General. The agency shall operate each program or activity so that the program or activity, when viewed in its entirety, is readily accessible to and usable by individuals with handicaps...

  8. Event memory and moving in a well-known environment.

    PubMed

    Tamplin, Andrea K; Krawietz, Sabine A; Radvansky, Gabriel A; Copeland, David E

    2013-11-01

    Research in narrative comprehension has repeatedly shown that when people read about characters moving in well-known environments, the accessibility of object information follows a spatial gradient. That is, the accessibility of objects is best when they are in the same room as the protagonist, and it becomes worse the farther away they are see, e.g., Morrow, Greenspan, & Bower, (Journal of Memory and Language, 26, 165-187, 1987). In the present study, we assessed this finding using an interactive environment in which we had people memorize a map and navigate a virtual simulation of the area. During navigation, people were probed with pairs of object names and indicated whether both objects were in the same room. In contrast to the narrative studies described above, several experiments showed no evidence of a clear spatial gradient. Instead, memory for objects in currently occupied locations (e.g., the location room) was more accessible, especially after a small delay, but no clear decline was evident in the accessibility of information in memory with increased distance. Also, memory for objects along the pathway of movement (i.e., rooms that a person only passed through) showed a transitory suppression effect that was present immediately after movement, but attenuated over time. These results were interpreted in light of the event horizon model of event cognition.

  9. The relationships of 'ecstasy' (MDMA) and cannabis use to impaired executive inhibition and access to semantic long-term memory.

    PubMed

    Murphy, Philip N; Erwin, Philip G; Maciver, Linda; Fisk, John E; Larkin, Derek; Wareing, Michelle; Montgomery, Catharine; Hilton, Joanne; Tames, Frank J; Bradley, Belinda; Yanulevitch, Kate; Ralley, Richard

    2011-10-01

    This study aimed to examine the relationship between the consumption of ecstasy (3,4-methylenedioxymethamphetamine (MDMA)) and cannabis, and performance on the random letter generation task which generates dependent variables drawing upon executive inhibition and access to semantic long-term memory (LTM). The participant group was a between-participant independent variable with users of both ecstasy and cannabis (E/C group, n = 15), users of cannabis but not ecstasy (CA group, n = 13) and controls with no exposure to these drugs (CO group, n = 12). Dependent variables measured violations of randomness: number of repeat sequences, number of alphabetical sequences (both drawing upon inhibition) and redundancy (drawing upon access to semantic LTM). E/C participants showed significantly higher redundancy than CO participants but did not differ from CA participants. There were no significant effects for the other dependent variables. A regression model comprising intelligence measures and estimates of ecstasy and cannabis consumption predicted redundancy scores, but only cannabis consumption contributed significantly to this prediction. Impaired access to semantic LTM may be related to cannabis consumption, although the involvement of ecstasy and other stimulant drugs cannot be excluded here. Executive inhibitory functioning, as measured by the random letter generation task, is unrelated to ecstasy and cannabis consumption. Copyright © 2011 John Wiley & Sons, Ltd.

  10. Chromatin accessibility prediction via convolutional long short-term memory networks with k-mer embedding.

    PubMed

    Min, Xu; Zeng, Wanwen; Chen, Ning; Chen, Ting; Jiang, Rui

    2017-07-15

    Experimental techniques for measuring chromatin accessibility are expensive and time consuming, appealing for the development of computational approaches to predict open chromatin regions from DNA sequences. Along this direction, existing methods fall into two classes: one based on handcrafted k -mer features and the other based on convolutional neural networks. Although both categories have shown good performance in specific applications thus far, there still lacks a comprehensive framework to integrate useful k -mer co-occurrence information with recent advances in deep learning. We fill this gap by addressing the problem of chromatin accessibility prediction with a convolutional Long Short-Term Memory (LSTM) network with k -mer embedding. We first split DNA sequences into k -mers and pre-train k -mer embedding vectors based on the co-occurrence matrix of k -mers by using an unsupervised representation learning approach. We then construct a supervised deep learning architecture comprised of an embedding layer, three convolutional layers and a Bidirectional LSTM (BLSTM) layer for feature learning and classification. We demonstrate that our method gains high-quality fixed-length features from variable-length sequences and consistently outperforms baseline methods. We show that k -mer embedding can effectively enhance model performance by exploring different embedding strategies. We also prove the efficacy of both the convolution and the BLSTM layers by comparing two variations of the network architecture. We confirm the robustness of our model to hyper-parameters by performing sensitivity analysis. We hope our method can eventually reinforce our understanding of employing deep learning in genomic studies and shed light on research regarding mechanisms of chromatin accessibility. The source code can be downloaded from https://github.com/minxueric/ismb2017_lstm . tingchen@tsinghua.edu.cn or ruijiang@tsinghua.edu.cn. Supplementary materials are available at

  11. Breaking the current density threshold in spin-orbit-torque magnetic random access memory

    NASA Astrophysics Data System (ADS)

    Zhang, Yin; Yuan, H. Y.; Wang, X. S.; Wang, X. R.

    2018-04-01

    Spin-orbit-torque magnetic random access memory (SOT-MRAM) is a promising technology for the next generation of data storage devices. The main bottleneck of this technology is the high reversal current density threshold. This outstanding problem is now solved by a new strategy in which the magnitude of the driven current density is fixed while the current direction varies with time. The theoretical limit of minimal reversal current density is only a fraction (the Gilbert damping coefficient) of the threshold current density of the conventional strategy. The Euler-Lagrange equation for the fastest magnetization reversal path and the optimal current pulse is derived for an arbitrary magnetic cell and arbitrary spin-orbit torque. The theoretical limit of minimal reversal current density and current density for a GHz switching rate of the new reversal strategy for CoFeB/Ta SOT-MRAMs are, respectively, of the order of 105 A/cm 2 and 106 A/cm 2 far below 107 A/cm 2 and 108 A/cm 2 in the conventional strategy. Furthermore, no external magnetic field is needed for a deterministic reversal in the new strategy.

  12. Cerebellar models of associative memory: Three papers from IEEE COMPCON spring 1989

    NASA Technical Reports Server (NTRS)

    Raugh, Michael R. (Editor)

    1989-01-01

    Three papers are presented on the following topics: (1) a cerebellar-model associative memory as a generalized random-access memory; (2) theories of the cerebellum - two early models of associative memory; and (3) intelligent network management and functional cerebellum synthesis.

  13. Electrical Characterization of the RCA CDP1822SD Random Access Memory, Volume 1, Appendix a

    NASA Technical Reports Server (NTRS)

    Klute, A.

    1979-01-01

    Electrical characteristization tests were performed on 35 RCA CDP1822SD, 256-by-4-bit, CMOS, random access memories. The tests included three functional tests, AC and DC parametric tests, a series of schmoo plots, rise/fall time screening, and a data retention test. All tests were performed on an automated IC test system with temperatures controlled by a thermal airstream unit. All the functional tests, the data retention test, and the AC and DC parametric tests were performed at ambient temperatures of 25 C, -20 C, -55 C, 85 C, and 125 C. The schmoo plots were performed at ambient temperatures of 25 C, -55 C, and 125 C. The data retention test was performed at 25 C. Five devices failed one or more functional tests and four of these devices failed to meet the expected limits of a number of AC parametric tests. Some of the schmoo plots indicated a small degree of interaction between parameters.

  14. Working Memory Underpins Cognitive Development, Learning, and Education

    PubMed Central

    Cowan, Nelson

    2014-01-01

    Working memory is the retention of a small amount of information in a readily accessible form. It facilitates planning, comprehension, reasoning, and problem-solving. I examine the historical roots and conceptual development of the concept and the theoretical and practical implications of current debates about working memory mechanisms. Then I explore the nature of cognitive developmental improvements in working memory, the role of working memory in learning, and some potential implications of working memory and its development for the education of children and adults. The use of working memory is quite ubiquitous in human thought, but the best way to improve education using what we know about working memory is still controversial. I hope to provide some directions for research and educational practice. PMID:25346585

  15. Unstructured Adaptive Meshes: Bad for Your Memory?

    NASA Technical Reports Server (NTRS)

    Biswas, Rupak; Feng, Hui-Yu; VanderWijngaart, Rob

    2003-01-01

    This viewgraph presentation explores the need for a NASA Advanced Supercomputing (NAS) parallel benchmark for problems with irregular dynamical memory access. This benchmark is important and necessary because: 1) Problems with localized error source benefit from adaptive nonuniform meshes; 2) Certain machines perform poorly on such problems; 3) Parallel implementation may provide further performance improvement but is difficult. Some examples of problems which use irregular dynamical memory access include: 1) Heat transfer problem; 2) Heat source term; 3) Spectral element method; 4) Base functions; 5) Elemental discrete equations; 6) Global discrete equations. Nonconforming Mesh and Mortar Element Method are covered in greater detail in this presentation.

  16. Working Memory Underpins Cognitive Development, Learning, and Education

    ERIC Educational Resources Information Center

    Cowan, Nelson

    2014-01-01

    Working memory is the retention of a small amount of information in a readily accessible form. It facilitates planning, comprehension, reasoning, and problem solving. I examine the historical roots and conceptual development of the concept and the theoretical and practical implications of current debates about working memory mechanisms. Then, I…

  17. Sparse distributed memory: Principles and operation

    NASA Technical Reports Server (NTRS)

    Flynn, M. J.; Kanerva, P.; Bhadkamkar, N.

    1989-01-01

    Sparse distributed memory is a generalized random access memory (RAM) for long (1000 bit) binary words. Such words can be written into and read from the memory, and they can also be used to address the memory. The main attribute of the memory is sensitivity to similarity, meaning that a word can be read back not only by giving the original write address but also by giving one close to it as measured by the Hamming distance between addresses. Large memories of this kind are expected to have wide use in speech recognition and scene analysis, in signal detection and verification, and in adaptive control of automated equipment, in general, in dealing with real world information in real time. The memory can be realized as a simple, massively parallel computer. Digital technology has reached a point where building large memories is becoming practical. Major design issues were resolved which were faced in building the memories. The design is described of a prototype memory with 256 bit addresses and from 8 to 128 K locations for 256 bit words. A key aspect of the design is extensive use of dynamic RAM and other standard components.

  18. Collective input/output under memory constraints

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Lu, Yin; Chen, Yong; Zhuang, Yu

    2014-12-18

    Compared with current high-performance computing (HPC) systems, exascale systems are expected to have much less memory per node, which can significantly reduce necessary collective input/output (I/O) performance. In this study, we introduce a memory-conscious collective I/O strategy that takes into account memory capacity and bandwidth constraints. The new strategy restricts aggregation data traffic within disjointed subgroups, coordinates I/O accesses in intranode and internode layers, and determines I/O aggregators at run time considering memory consumption among processes. We have prototyped the design and evaluated it with commonly used benchmarks to verify its potential. The evaluation results demonstrate that this strategy holdsmore » promise in mitigating the memory pressure, alleviating the contention for memory bandwidth, and improving the I/O performance for projected extreme-scale systems. Given the importance of supporting increasingly data-intensive workloads and projected memory constraints on increasingly larger scale HPC systems, this new memory-conscious collective I/O can have a significant positive impact on scientific discovery productivity.« less

  19. Multiple Memory Stores and Operant Conditioning: A Rationale for Memory's Complexity

    ERIC Educational Resources Information Center

    Meeter, Martijn; Veldkamp, Rob; Jin, Yaochu

    2009-01-01

    Why does the brain contain more than one memory system? Genetic algorithms can play a role in elucidating this question. Here, model animals were constructed containing a dorsal striatal layer that controlled actions, and a ventral striatal layer that controlled a dopaminergic learning signal. Both layers could gain access to three modeled memory…

  20. Are There Multiple Visual Short-Term Memory Stores?

    PubMed Central

    Sligte, Ilja G.; Scholte, H. Steven; Lamme, Victor A. F.

    2008-01-01

    Background Classic work on visual short-term memory (VSTM) suggests that people store a limited amount of items for subsequent report. However, when human observers are cued to shift attention to one item in VSTM during retention, it seems as if there is a much larger representation, which keeps additional items in a more fragile VSTM store. Thus far, it is not clear whether the capacity of this fragile VSTM store indeed exceeds the traditional capacity limits of VSTM. The current experiments address this issue and explore the capacity, stability, and duration of fragile VSTM representations. Methodology/Principal Findings We presented cues in a change-detection task either just after off-set of the memory array (iconic-cue), 1,000 ms after off-set of the memory array (retro-cue) or after on-set of the probe array (post-cue). We observed three stages in visual information processing 1) iconic memory with unlimited capacity, 2) a four seconds lasting fragile VSTM store with a capacity that is at least a factor of two higher than 3) the robust and capacity-limited form of VSTM. Iconic memory seemed to depend on the strength of the positive after-image resulting from the memory display and was virtually absent under conditions of isoluminance or when intervening light masks were presented. This suggests that iconic memory is driven by prolonged retinal activation beyond stimulus duration. Fragile VSTM representations were not affected by light masks, but were completely overwritten by irrelevant pattern masks that spatially overlapped the memory array. Conclusions/Significance We find that immediately after a stimulus has disappeared from view, subjects can still access information from iconic memory because they can see an after-image of the display. After that period, human observers can still access a substantial, but somewhat more limited amount of information from a high-capacity, but fragile VSTM that is overwritten when new items are presented to the eyes. What

  1. Are there multiple visual short-term memory stores?

    PubMed

    Sligte, Ilja G; Scholte, H Steven; Lamme, Victor A F

    2008-02-27

    Classic work on visual short-term memory (VSTM) suggests that people store a limited amount of items for subsequent report. However, when human observers are cued to shift attention to one item in VSTM during retention, it seems as if there is a much larger representation, which keeps additional items in a more fragile VSTM store. Thus far, it is not clear whether the capacity of this fragile VSTM store indeed exceeds the traditional capacity limits of VSTM. The current experiments address this issue and explore the capacity, stability, and duration of fragile VSTM representations. We presented cues in a change-detection task either just after off-set of the memory array (iconic-cue), 1,000 ms after off-set of the memory array (retro-cue) or after on-set of the probe array (post-cue). We observed three stages in visual information processing 1) iconic memory with unlimited capacity, 2) a four seconds lasting fragile VSTM store with a capacity that is at least a factor of two higher than 3) the robust and capacity-limited form of VSTM. Iconic memory seemed to depend on the strength of the positive after-image resulting from the memory display and was virtually absent under conditions of isoluminance or when intervening light masks were presented. This suggests that iconic memory is driven by prolonged retinal activation beyond stimulus duration. Fragile VSTM representations were not affected by light masks, but were completely overwritten by irrelevant pattern masks that spatially overlapped the memory array. We find that immediately after a stimulus has disappeared from view, subjects can still access information from iconic memory because they can see an after-image of the display. After that period, human observers can still access a substantial, but somewhat more limited amount of information from a high-capacity, but fragile VSTM that is overwritten when new items are presented to the eyes. What is left after that is the traditional VSTM store, with a limit of

  2. Direct memory access transfer completion notification

    DOEpatents

    Archer, Charles J [Rochester, MN; Blocksome, Michael A [Rochester, MN; Parker, Jeffrey J [Rochester, MN

    2011-02-15

    DMA transfer completion notification includes: inserting, by an origin DMA engine on an origin node in an injection first-in-first-out (`FIFO`) buffer, a data descriptor for an application message to be transferred to a target node on behalf of an application on the origin node; inserting, by the origin DMA engine, a completion notification descriptor in the injection FIFO buffer after the data descriptor for the message, the completion notification descriptor specifying a packet header for a completion notification packet; transferring, by the origin DMA engine to the target node, the message in dependence upon the data descriptor; sending, by the origin DMA engine, the completion notification packet to a local reception FIFO buffer using a local memory FIFO transfer operation; and notifying, by the origin DMA engine, the application that transfer of the message is complete in response to receiving the completion notification packet in the local reception FIFO buffer.

  3. Overgeneral Autobiographical Memory and Traumatic Events: An Evaluative Review

    ERIC Educational Resources Information Center

    Moore, Sally A.; Zoellner, Lori A.

    2007-01-01

    Does trauma exposure impair retrieval of autobiographical memories? Many theorists have suggested that the reduced ability to access specific memories of life events, termed overgenerality, is a protective mechanism helping attenuate painful emotions associated with trauma. The authors addressed this question by reviewing 24 studies that assessed…

  4. Marijuana effects on long-term memory assessment and retrieval.

    PubMed

    Darley, C F; Tinklenberg, J R; Roth, W T; Vernon, S; Kopell, B S

    1977-05-09

    The ability of 16 college-educated male subjects to recall from long-term memory a series of common facts was tested during intoxication with marijuana extract calibrated to 0.3 mg/kg delta-9-tetrahydrocannabinol and during placebo conditions. The subjects' ability to assess their memory capabilities was then determined by measuring how certain they were about the accuracy of their recall performance and by having them predict their performance on a subsequent recognition test involving the same recall items. Marijuana had no effect on recall or recognition performance. These results do not support the view that marijuana provides access to facts in long-term storage which are inaccessible during non-intoxication. During both marijuana and placebo conditions, subjects could accurately predict their recognition memory performance. Hence, marijuana did not alter the subjects' ability to accurately assess what information resides in long-term memory even though they did not have complete access to that information.

  5. A multilevel nonvolatile magnetoelectric memory

    NASA Astrophysics Data System (ADS)

    Shen, Jianxin; Cong, Junzhuang; Shang, Dashan; Chai, Yisheng; Shen, Shipeng; Zhai, Kun; Sun, Young

    2016-09-01

    The coexistence and coupling between magnetization and electric polarization in multiferroic materials provide extra degrees of freedom for creating next-generation memory devices. A variety of concepts of multiferroic or magnetoelectric memories have been proposed and explored in the past decade. Here we propose a new principle to realize a multilevel nonvolatile memory based on the multiple states of the magnetoelectric coefficient (α) of multiferroics. Because the states of α depends on the relative orientation between magnetization and polarization, one can reach different levels of α by controlling the ratio of up and down ferroelectric domains with external electric fields. Our experiments in a device made of the PMN-PT/Terfenol-D multiferroic heterostructure confirm that the states of α can be well controlled between positive and negative by applying selective electric fields. Consequently, two-level, four-level, and eight-level nonvolatile memory devices are demonstrated at room temperature. This kind of multilevel magnetoelectric memory retains all the advantages of ferroelectric random access memory but overcomes the drawback of destructive reading of polarization. In contrast, the reading of α is nondestructive and highly efficient in a parallel way, with an independent reading coil shared by all the memory cells.

  6. Multi-step resistive switching behavior of Li-doped ZnO resistance random access memory device controlled by compliance current

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Lin, Chun-Cheng; Department of Mathematic and Physical Sciences, R.O.C. Air Force Academy, Kaohsiung 820, Taiwan; Tang, Jian-Fu

    2016-06-28

    The multi-step resistive switching (RS) behavior of a unipolar Pt/Li{sub 0.06}Zn{sub 0.94}O/Pt resistive random access memory (RRAM) device is investigated. It is found that the RRAM device exhibits normal, 2-, 3-, and 4-step RESET behaviors under different compliance currents. The transport mechanism within the device is investigated by means of current-voltage curves, in-situ transmission electron microscopy, and electrochemical impedance spectroscopy. It is shown that the ion transport mechanism is dominated by Ohmic behavior under low electric fields and the Poole-Frenkel emission effect (normal RS behavior) or Li{sup +} ion diffusion (2-, 3-, and 4-step RESET behaviors) under high electric fields.

  7. Skilled memory in expert figure skaters.

    PubMed

    Deakin, J M; Allard, F

    1991-01-01

    The present studies extend skilled-memory theory to a domain involving the performance of motor sequences. Skilled figure skaters were better able than their less skilled counterparts to perform short skating sequences that were choreographed, rather than randomly constructed. Expert skaters encoded sequences for performance very differently from the way in which they encoded sequences that were verbally presented for verbal recall. Tasks interpolated between sequence and recall showed no significant influence on recall accuracy, implicating long-term memory in skating memory. There was little evidence for the use of retrieval structures when skaters learned the brief sequences used throughout these studies. Finally, expert skaters were able to judge the similarity of two skating elements faster than less skilled skaters, indicating a faster access to semantic memory for experts. The data indicate that skaters show many of the same skilled-memory characteristics as have been described in other skill domains involving memorization, such as digit span and memory for dinner orders.

  8. Biodegradable Shape Memory Polymers in Medicine.

    PubMed

    Peterson, Gregory I; Dobrynin, Andrey V; Becker, Matthew L

    2017-11-01

    Shape memory materials have emerged as an important class of materials in medicine due to their ability to change shape in response to a specific stimulus, enabling the simplification of medical procedures, use of minimally invasive techniques, and access to new treatment modalities. Shape memory polymers, in particular, are well suited for such applications given their excellent shape memory performance, tunable materials properties, minimal toxicity, and potential for biodegradation and resorption. This review provides an overview of biodegradable shape memory polymers that have been used in medical applications. The majority of biodegradable shape memory polymers are based on thermally responsive polyesters or polymers that contain hydrolyzable ester linkages. These materials have been targeted for use in applications pertaining to embolization, drug delivery, stents, tissue engineering, and wound closure. The development of biodegradable shape memory polymers with unique properties or responsiveness to novel stimuli has the potential to facilitate the optimization and development of new medical applications. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  9. Synaptic Correlates of Working Memory Capacity.

    PubMed

    Mi, Yuanyuan; Katkov, Mikhail; Tsodyks, Misha

    2017-01-18

    Psychological studies indicate that human ability to keep information in readily accessible working memory is limited to four items for most people. This extremely low capacity severely limits execution of many cognitive tasks, but its neuronal underpinnings remain unclear. Here we show that in the framework of synaptic theory of working memory, capacity can be analytically estimated to scale with characteristic time of short-term synaptic depression relative to synaptic current time constant. The number of items in working memory can be regulated by external excitation, enabling the system to be tuned to the desired load and to clear the working memory of currently held items to make room for new ones. Copyright © 2017 Elsevier Inc. All rights reserved.

  10. The removal of information from working memory.

    PubMed

    Lewis-Peacock, Jarrod A; Kessler, Yoav; Oberauer, Klaus

    2018-05-09

    What happens to goal-relevant information in working memory after it is no longer needed? Here, we review evidence for a selective removal process that operates on outdated information to limit working memory load and hence facilitates the maintenance of goal-relevant information. Removal alters the representations of irrelevant content so as to reduce access to it, thereby improving access to the remaining relevant content and also facilitating the encoding of new information. Both behavioral and neural evidence support the existence of a removal process that is separate from forgetting due to decay or interference. We discuss the potential mechanisms involved in removal and characterize the time course and duration of the process. In doing so, we propose the existence of two forms of removal: one is temporary, and reversible, which modifies working memory content without impacting content-to-context bindings, and another is permanent, which unbinds the content from its context in working memory (without necessarily impacting long-term forgetting). Finally, we discuss limitations on removal and prescribe conditions for evaluating evidence for or against this process. © 2018 New York Academy of Sciences.

  11. Dynamic Neural Networks Supporting Memory Retrieval

    PubMed Central

    St. Jacques, Peggy L.; Kragel, Philip A.; Rubin, David C.

    2011-01-01

    How do separate neural networks interact to support complex cognitive processes such as remembrance of the personal past? Autobiographical memory (AM) retrieval recruits a consistent pattern of activation that potentially comprises multiple neural networks. However, it is unclear how such large-scale neural networks interact and are modulated by properties of the memory retrieval process. In the present functional MRI (fMRI) study, we combined independent component analysis (ICA) and dynamic causal modeling (DCM) to understand the neural networks supporting AM retrieval. ICA revealed four task-related components consistent with the previous literature: 1) Medial Prefrontal Cortex (PFC) Network, associated with self-referential processes, 2) Medial Temporal Lobe (MTL) Network, associated with memory, 3) Frontoparietal Network, associated with strategic search, and 4) Cingulooperculum Network, associated with goal maintenance. DCM analysis revealed that the medial PFC network drove activation within the system, consistent with the importance of this network to AM retrieval. Additionally, memory accessibility and recollection uniquely altered connectivity between these neural networks. Recollection modulated the influence of the medial PFC on the MTL network during elaboration, suggesting that greater connectivity among subsystems of the default network supports greater re-experience. In contrast, memory accessibility modulated the influence of frontoparietal and MTL networks on the medial PFC network, suggesting that ease of retrieval involves greater fluency among the multiple networks contributing to AM. These results show the integration between neural networks supporting AM retrieval and the modulation of network connectivity by behavior. PMID:21550407

  12. Characterization of PZT Capacitor Structures with Various Electrode Materials Processed In-Situ Using AN Automated, Rotating Elemental Target, Ion Beam Deposition System

    NASA Astrophysics Data System (ADS)

    Gifford, Kenneth Douglas

    Ferroelectric thin film capacitor structures containing lead zirconate titanate (PZT) as the dielectric, with the chemical formula Pb(rm Zr_{x }Ti_{1-x})O_3, were synthesized in-situ with an automated ion beam sputter deposition system. Platinum (Pt), conductive ruthenium oxide (RuO_2), and two types of Pt-RuO_2 hybrid electrodes were used as the electrode materials. The capacitor structures are characterized in terms of microstructure and electrical characteristics. Reduction or elimination of non-ferroelectric phases, that nucleate during PZT processing on Pt/TiO _2/MgO and RuO_2/MgO substrates, is achieved by reducing the thickness of the individually deposited layers and by interposing a buffer layer (~100-200A) of PbTiO _3 (PT) between the bottom electrode and the PZT film. Capacitor structures containing a Pt electrode exhibit poor fatigue resistance, irregardless of the PZT microstructure or the use of a PT buffer layer. From these results, and results from similar capacitors synthesized with sol-gel and laser ablation, PZT-based capacitor structures containing Pt electrodes are considered to be unsuitable for use in memory devices. Using a PT buffer layer, in capacitor structures containing RuO_2 top and bottom electrodes and polycrystalline, highly (101) oriented PZT, reduces or eliminates the nucleation of zirconium-titanium oxide, non-ferroelectric species at the bottom electrode interface during processing. This results in good fatigue resistance up to ~2times10^ {10} switching cycles. DC leakage current density vs. time measurements follow the Curie-von Schweidler law, J(t) ~ t^ {rm -n}. Identification of the high electric field current conduction mechanism is inconclusive. The good fatigue resistance, low dc leakage current, and excellent retention, qualifies the use of these capacitor structures in non-volatile random access (NVRAM) and dynamic random access (DRAM) memory devices. Excellent fatigue resistance (10% loss in remanent polarization up to

  13. Three-dimensional magnetic bubble memory system

    NASA Technical Reports Server (NTRS)

    Stadler, Henry L. (Inventor); Katti, Romney R. (Inventor); Wu, Jiin-Chuan (Inventor)

    1994-01-01

    A compact memory uses magnetic bubble technology for providing data storage. A three-dimensional arrangement, in the form of stacks of magnetic bubble layers, is used to achieve high volumetric storage density. Output tracks are used within each layer to allow data to be accessed uniquely and unambiguously. Storage can be achieved using either current access or field access magnetic bubble technology. Optical sensing via the Faraday effect is used to detect data. Optical sensing facilitates the accessing of data from within the three-dimensional package and lends itself to parallel operation for supporting high data rates and vector and parallel processing.

  14. Belief Inhibition in Children's Reasoning: Memory-Based Evidence

    ERIC Educational Resources Information Center

    Steegen, Sara; Neys, Wim De

    2012-01-01

    Adult reasoning has been shown as mediated by the inhibition of intuitive beliefs that are in conflict with logic. The current study introduces a classic procedure from the memory field to investigate belief inhibition in 12- to 17-year-old reasoners. A lexical decision task was used to probe the memory accessibility of beliefs that were cued…

  15. Distributed shared memory for roaming large volumes.

    PubMed

    Castanié, Laurent; Mion, Christophe; Cavin, Xavier; Lévy, Bruno

    2006-01-01

    We present a cluster-based volume rendering system for roaming very large volumes. This system allows to move a gigabyte-sized probe inside a total volume of several tens or hundreds of gigabytes in real-time. While the size of the probe is limited by the total amount of texture memory on the cluster, the size of the total data set has no theoretical limit. The cluster is used as a distributed graphics processing unit that both aggregates graphics power and graphics memory. A hardware-accelerated volume renderer runs in parallel on the cluster nodes and the final image compositing is implemented using a pipelined sort-last rendering algorithm. Meanwhile, volume bricking and volume paging allow efficient data caching. On each rendering node, a distributed hierarchical cache system implements a global software-based distributed shared memory on the cluster. In case of a cache miss, this system first checks page residency on the other cluster nodes instead of directly accessing local disks. Using two Gigabit Ethernet network interfaces per node, we accelerate data fetching by a factor of 4 compared to directly accessing local disks. The system also implements asynchronous disk access and texture loading, which makes it possible to overlap data loading, volume slicing and rendering for optimal volume roaming.

  16. A Neuroanatomical Model of Prefrontal Inhibitory Modulation of Memory Retrieval

    PubMed Central

    Depue, Brendan E.

    2012-01-01

    Memory of past experience is essential for guiding goal-related behavior. Being able to control accessibility of memory through modulation of retrieval enables humans to flexibly adapt to their environment. Understanding the specific neural pathways of how this control is achieved has largely eluded cognitive neuroscience. Accordingly, in the current paper I review literature that examines the overt control over retrieval in order to reduce accessibility. I first introduce three hypotheses of inhibition of retrieval. These hypotheses involve: i) attending to other stimuli as a form of diversionary attention, ii) inhibiting the specific individual neural representation of the memory, and iii) inhibiting the hippocampus and retrieval process more generally to prevent reactivation of the representation. I then analyze literature taken from the White Bear Suppression, Directed Forgetting and Think/No-Think tasks to provide evidence for these hypotheses. Finally, a neuroanatomical model is developed to indicate three pathways from PFC to the hippocampal complex that support inhibition of memory retrieval. Describing these neural pathways increases our understanding of control over memory in general. PMID:22374224

  17. The two faces of selective memory retrieval: recall specificity of the detrimental but not the beneficial effect.

    PubMed

    Bäuml, Karl-Heinz T; Dobler, Ina M

    2015-01-01

    Depending on the degree to which the original study context is accessible, selective memory retrieval can be detrimental or beneficial for the recall of other memories (Bäuml & Samenieh, 2012). Prior work has shown that the detrimental effect of memory retrieval is typically recall specific and does not arise after restudy trials, whereas recall specificity of the beneficial effect has not been examined to date. Addressing the issue, we compared in 2 experiments the effects of retrieval and restudy on recall of other items, when access to the study context was (largely) maintained and when access to the study context was impaired (in Experiment 1 by using the listwise directed-forgetting task, in Experiment 2 by using a prolonged retention interval). In both experiments, selective retrieval but not restudy induced forgetting of other items when context access was maintained, which replicates prior work. In contrast, when context access was impaired, both selective retrieval and restudy induced beneficial effects on other memories. These findings suggest that the detrimental but not the beneficial effect of selective memory retrieval is recall specific. The results are consistent with a recent 2-factor account of selective memory retrieval that attributes the detrimental effect to inhibition or blocking but the beneficial effect to context reactivation processes. PsycINFO Database Record (c) 2015 APA, all rights reserved.

  18. Contexts and Control Operations Used in Accessing List-Specific, Generalized, and Semantic Memories

    ERIC Educational Resources Information Center

    Humphreys, Michael S.; Murray, Krista L.; Maguire, Angela M.

    2009-01-01

    The human ability to focus memory retrieval operations on a particular list, episode or memory structure has not been fully appreciated or documented. In Experiment 1-3, we make it increasingly difficult for participants to switch between a less recent list (multiple study opportunities), and a more recent list (single study opportunity). Task…

  19. Loss of object recognition memory produced by extended access to methamphetamine self-administration is reversed by positive allosteric modulation of metabotropic glutamate receptor 5.

    PubMed

    Reichel, Carmela M; Schwendt, Marek; McGinty, Jacqueline F; Olive, M Foster; See, Ronald E

    2011-03-01

    Chronic methamphetamine (meth) abuse can lead to persisting cognitive deficits. Here, we utilized a long-access meth self-administration (SA) protocol to assess recognition memory and metabotropic glutamate receptor (mGluR) expression, and the possible reversal of cognitive impairments with the mGluR5 allosteric modulator, 3-cyano-N-(1,3-diphenyl-1H-pyrazol-5-yl) benzamide (CDPPB). Male, Long-Evans rats self-administered i.v. meth (0.02 mg/infusion) on an FR1 schedule of reinforcement or received yoked-saline infusions. After seven daily 1-h sessions, rats were switched to 6-h daily sessions for 14 days, and then underwent drug abstinence. Rats were tested for object recognition memory at 1 week after meth SA at 90 min and 24 h retention intervals. In a separate experiment, rats underwent the same protocol, but received either vehicle or CDPPB (30 mg/kg) after familiarization. Rats were killed on day 8 or 14 post-SA and brain tissue was obtained. Meth intake escalated over the extended access period. Additionally, meth-experienced rats showed deficits in both short- and long-term recognition memory, demonstrated by a lack of novel object exploration. The deficit at 90 min was reversed by CDPPB treatment. On day 8, meth intake during SA negatively correlated with mGluR expression in the perirhinal and prefrontal cortex, and mGluR5 receptor expression was decreased 14 days after discontinuation of meth. This effect was specific to mGluR5 levels in the perirhinal cortex, as no differences were identified in the hippocampus or in mGluR2/3 receptors. These results from a clinically-relevant animal model of addiction suggest that mGluR5 receptor modulation may be a potential treatment of cognitive dysfunction in meth addiction.

  20. Memory Loss: When to Seek Help

    MedlinePlus

    ... a set of symptoms, including impairment in memory, reasoning, judgment, language and other thinking skills. Dementia usually ... et al. Mild cognitive impairment: Epidemiology, pathology and clinical assessment. http://www.uptodate.com/home. Accessed March ...

  1. Semantic Memory and Verbal Working Memory Correlates of N400 to Subordinate Homographs

    ERIC Educational Resources Information Center

    Salisbury, Dean F.

    2004-01-01

    N400 is an event-related brain potential that indexes operations in semantic memory conceptual space, whether elicited by language or some other representation (e.g., drawings). Language models typically propose three stages: lexical access or orthographic- and phonological-level analysis; lexical selection or word-level meaning and associate…

  2. In-memory interconnect protocol configuration registers

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Cheng, Kevin Y.; Roberts, David A.

    Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mappingmore » decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.« less

  3. Autobiographical Memory Disturbances in Depression: A Novel Therapeutic Target?

    PubMed Central

    Köhler, Cristiano A.; Carvalho, André F.; Alves, Gilberto S.; McIntyre, Roger S.; Hyphantis, Thomas N.; Cammarota, Martín

    2015-01-01

    Major depressive disorder (MDD) is characterized by a dysfunctional processing of autobiographical memories. We review the following core domains of deficit: systematic biases favoring materials of negative emotional valence; diminished access and response to positive memories; a recollection of overgeneral memories in detriment of specific autobiographical memories; and the role of ruminative processes and avoidance when dealing with autobiographical memories. Furthermore, we review evidence from functional neuroimaging studies of neural circuits activated by the recollection of autobiographical memories in both healthy and depressive individuals. Disruptions in autobiographical memories predispose and portend onset and maintenance of depression. Thus, we discuss emerging therapeutics that target memory difficulties in those with depression. We review strategies for this clinical domain, including memory specificity training, method-of-loci, memory rescripting, and real-time fMRI neurofeedback training of amygdala activity in depression. We propose that the manipulation of the reconsolidation of autobiographical memories in depression might represent a novel yet largely unexplored, domain-specific, therapeutic opportunity for depression treatment. PMID:26380121

  4. A Novel Ni/WOX/W Resistive Random Access Memory with Excellent Retention and Low Switching Current

    NASA Astrophysics Data System (ADS)

    Chien, Wei-Chih; Chen, Yi-Chou; Lee, Feng-Ming; Lin, Yu-Yu; Lai, Erh-Kun; Yao, Yeong-Der; Gong, Jeng; Horng, Sheng-Fu; Yeh, Chiao-Wen; Tsai, Shih-Chang; Lee, Ching-Hsiung; Huang, Yu-Kai; Chen, Chun-Fu; Kao, Hsiao-Feng; Shih, Yen-Hao; Hsieh, Kuang-Yeu; Lu, Chih-Yuan

    2011-04-01

    The behavior of WOX resistive random access memory (ReRAM) is a strong function of the top electrode material, which controls the conduction mechanism and the forming process. When using a top electrode with low work function, the current conduction is limited by space charges. On the other hand, the mechanism becomes thermionic emission for devices with a high work function top electrode. These (thermionic) devices are also found to have higher initial resistance, reduced forming current, and larger resistance window. Based on these insights and considering the compatibility to complementary metal-oxide-semiconductor (CMOS) process, we proposed to use Ni as the top electrode for high performance WOX ReRAM devices. The new Ni/WOX/W device can be switched at a low current density less than 8×105 A/cm2, with RESET/SET resistance ratio greater than 100, and extremely good data retention of more than 300 years at 85 °C.

  5. Silent store detection and recording in memory storage

    DOEpatents

    Bose, Pradip; Cher, Chen-Yong; Nair, Ravi

    2017-03-07

    An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.

  6. Silent store detection and recording in memory storage

    DOEpatents

    Bose, Pradip; Cher, Chen-Yong; Nair, Ravi

    2016-09-20

    An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.

  7. SODR Memory Control Buffer Control ASIC

    NASA Technical Reports Server (NTRS)

    Hodson, Robert F.

    1994-01-01

    The Spacecraft Optical Disk Recorder (SODR) is a state of the art mass storage system for future NASA missions requiring high transmission rates and a large capacity storage system. This report covers the design and development of an SODR memory buffer control applications specific integrated circuit (ASIC). The memory buffer control ASIC has two primary functions: (1) buffering data to prevent loss of data during disk access times, (2) converting data formats from a high performance parallel interface format to a small computer systems interface format. Ten 144 p in, 50 MHz CMOS ASIC's were designed, fabricated and tested to implement the memory buffer control function.

  8. Programming distributed memory architectures using Kali

    NASA Technical Reports Server (NTRS)

    Mehrotra, Piyush; Vanrosendale, John

    1990-01-01

    Programming nonshared memory systems is more difficult than programming shared memory systems, in part because of the relatively low level of current programming environments for such machines. A new programming environment is presented, Kali, which provides a global name space and allows direct access to remote data values. In order to retain efficiency, Kali provides a system on annotations, allowing the user to control those aspects of the program critical to performance, such as data distribution and load balancing. The primitives and constructs provided by the language is described, and some of the issues raised in translating a Kali program for execution on distributed memory systems are also discussed.

  9. Sparse distributed memory prototype: Principles of operation

    NASA Technical Reports Server (NTRS)

    Flynn, Michael J.; Kanerva, Pentti; Ahanin, Bahram; Bhadkamkar, Neal; Flaherty, Paul; Hickey, Philip

    1988-01-01

    Sparse distributed memory is a generalized random access memory (RAM) for long binary words. Such words can be written into and read from the memory, and they can be used to address the memory. The main attribute of the memory is sensitivity to similarity, meaning that a word can be read back not only by giving the original right address but also by giving one close to it as measured by the Hamming distance between addresses. Large memories of this kind are expected to have wide use in speech and scene analysis, in signal detection and verification, and in adaptive control of automated equipment. The memory can be realized as a simple, massively parallel computer. Digital technology has reached a point where building large memories is becoming practical. The research is aimed at resolving major design issues that have to be faced in building the memories. The design of a prototype memory with 256-bit addresses and from 8K to 128K locations for 256-bit words is described. A key aspect of the design is extensive use of dynamic RAM and other standard components.

  10. A memory module for experimental data handling

    NASA Astrophysics Data System (ADS)

    De Blois, J.

    1985-02-01

    A compact CAMAC memory module for experimental data handling was developed to eliminate the need of direct memory access in computer controlled measurements. When using autonomous controllers it also makes measurements more independent of the program and enlarges the available space for programs in the memory of the micro-computer. The memory module has three modes of operation: an increment-, a list- and a fifo mode. This is achieved by connecting the main parts, being: the memory (MEM), the fifo buffer (FIFO), the address buffer (BUF), two counters (AUX and ADDR) and a readout register (ROR), by an internal 24-bit databus. The time needed for databus operations is 1 μs, for measuring cycles as well as for CAMAC cycles. The FIFO provides temporary data storage during CAMAC cycles and separates the memory part from the application part. The memory is variable from 1 to 64K (24 bits) by using different types of memory chips. The application part, which forms 1/3 of the module, will be specially designed for each application and is added to the memory chian internal connector. The memory unit will be used in Mössbauer experiments and in thermal neutron scattering experiments.

  11. The influence of aging on attentional refreshing and articulatory rehearsal during working memory on later episodic memory performance.

    PubMed

    Loaiza, Vanessa M; McCabe, David P

    2013-01-01

    We investigated age-related changes in two proposed mechanisms of maintenance in working memory, articulatory rehearsal, and attentional refreshing, by examining the consequences of manipulating the opportunity for each on delayed recall. Both experiments utilized modified operation span tasks to vary the opportunity for articulatory rehearsal (Experiment 1) and attentional refreshing opportunities (Experiment 2). In both experiments, episodic memory was tested for items that had been initially studied during the respective operation span task. Older adults' episodic memory benefited less from opportunities for refreshing than younger adults. In contrast, articulatory rehearsal opportunities did not influence episodic memory for either age group. The results suggest that attentional refreshing, and not articulatory rehearsal, is important during working memory in order to bind more accessible traces at later tests, which appears to be more deficient in older adults than younger adults.

  12. Multiple-choice tests stabilize access to marginal knowledge.

    PubMed

    Cantor, Allison D; Eslick, Andrea N; Marsh, Elizabeth J; Bjork, Robert A; Bjork, Elizabeth Ligon

    2015-02-01

    Marginal knowledge refers to knowledge that is stored in memory, but is not accessible at a given moment. For example, one might struggle to remember who wrote The Call of the Wild, even if that knowledge is stored in memory. Knowing how best to stabilize access to marginal knowledge is important, given that new learning often requires accessing and building on prior knowledge. While even a single opportunity to restudy marginal knowledge boosts its later accessibility (Berger, Hall, & Bahrick, 1999), in many situations explicit relearning opportunities are not available. Our question is whether multiple-choice tests (which by definition expose the learner to the correct answers) can also serve this function and, if so, how testing compares to restudying given that tests can be particularly powerful learning devices (Roediger & Karpicke, 2006). In four experiments, we found that multiple-choice testing had the power to stabilize access to marginal knowledge, and to do so for at least up to a week. Importantly, such tests did not need to be paired with feedback, although testing was no more powerful than studying. Overall, the results support the idea that one's knowledge base is unstable, with individual pieces of information coming in and out of reach. The present findings have implications for a key educational challenge: ensuring that students have continuing access to information they have learned.

  13. Conversational assessment in memory clinic encounters: interactional profiling for differentiating dementia from functional memory disorders.

    PubMed

    Jones, Danielle; Drew, Paul; Elsey, Christopher; Blackburn, Daniel; Wakefield, Sarah; Harkness, Kirsty; Reuber, Markus

    2016-01-01

    In the UK dementia is under-diagnosed, there is limited access to specialist memory clinics, and many of the patients referred to such clinics are ultimately found to have functional (non-progressive) memory disorders (FMD), rather than a neurodegenerative disorder. Government initiatives on 'timely diagnosis' aim to improve the rate and quality of diagnosis for those with dementia. This study seeks to improve the screening and diagnostic process by analysing communication between clinicians and patients during initial specialist clinic visits. Establishing differential conversational profiles could help the timely differential diagnosis of memory complaints. This study is based on video- and audio recordings of 25 initial consultations between neurologists and patients referred to a UK memory clinic. Conversation analysis was used to explore recurrent communicative practices associated with each diagnostic group. Two discrete conversational profiles began to emerge, to help differentiate between patients with dementia and functional memory complaints, based on (1) whether the patient is able to answer questions about personal information; (2) whether they can display working memory in interaction; (3) whether they are able to respond to compound questions; (4) the time taken to respond to questions; and (5) the level of detail they offer when providing an account of their memory failure experiences. The distinctive conversational profiles observed in patients with functional memory complaints on the one hand and neurodegenerative memory conditions on the other suggest that conversational profiling can support the differential diagnosis of functional and neurodegenerative memory disorders.

  14. Psychological Processes Underlying Cultivation Effects: Further Tests of Construct Accessibility.

    ERIC Educational Resources Information Center

    Shrum, L. J.

    1996-01-01

    Describes a study that tested whether the accessibility of information in memory mediates the cultivation effect (the effect of television viewing on social perceptions), consistent with the availability heuristic. Shows that heavy viewers gave higher frequency estimates (cultivation effect) and responded faster (accessibility effect) than did…

  15. Trinary Associative Memory Would Recognize Machine Parts

    NASA Technical Reports Server (NTRS)

    Liu, Hua-Kuang; Awwal, Abdul Ahad S.; Karim, Mohammad A.

    1991-01-01

    Trinary associative memory combines merits and overcomes major deficiencies of unipolar and bipolar logics by combining them in three-valued logic that reverts to unipolar or bipolar binary selectively, as needed to perform specific tasks. Advantage of associative memory: one obtains access to all parts of it simultaneously on basis of content, rather than address, of data. Consequently, used to exploit fully parallelism and speed of optical computing.

  16. Architectural design and simulation of a virtual memory

    NASA Technical Reports Server (NTRS)

    Kwok, G.; Chu, Y.

    1971-01-01

    Virtual memory is an imaginary main memory with a very large capacity which the programmer has at his disposal. It greatly contributes to the solution of the dynamic storage allocation problem. The architectural design of a virtual memory is presented which implements by hardware the idea of queuing and scheduling the page requests to a paging drum in such a way that the access of the paging drum is increased many times. With the design, an increase of up to 16 times in page transfer rate is achievable when the virtual memory is heavily loaded. This in turn makes feasible a great increase in the system throughput.

  17. Test Procedures for Semiconductor Random Access Memories

    DTIC Science & Technology

    1979-11-01

    of each cell exactly complement to each other, the read operations on the base cell in (g) of step 2 following operations ko S odd and in (p) of step...contents of Sko (these cells this address. Furthermore, when more than one contained I at test time and even if the con- cell is accessed then the output

  18. An Account of Performance in Accessing Information Stored in Long-Term Memory. A Fixed-Links Model Approach

    ERIC Educational Resources Information Center

    Altmeyer, Michael; Schweizer, Karl; Reiss, Siegbert; Ren, Xuezhu; Schreiner, Michael

    2013-01-01

    Performance in working memory and short-term memory tasks was employed for predicting performance in a long-term memory task in order to find out about the underlying processes. The types of memory were represented by versions of the Posner Task, the Backward Counting Task and the Sternberg Task serving as measures of long-term memory, working…

  19. Conditional load and store in a shared memory

    DOEpatents

    Blumrich, Matthias A; Ohmacht, Martin

    2015-02-03

    A method, system and computer program product for implementing load-reserve and store-conditional instructions in a multi-processor computing system. The computing system includes a multitude of processor units and a shared memory cache, and each of the processor units has access to the memory cache. In one embodiment, the method comprises providing the memory cache with a series of reservation registers, and storing in these registers addresses reserved in the memory cache for the processor units as a result of issuing load-reserve requests. In this embodiment, when one of the processor units makes a request to store data in the memory cache using a store-conditional request, the reservation registers are checked to determine if an address in the memory cache is reserved for that processor unit. If an address in the memory cache is reserved for that processor, the data are stored at this address.

  20. A Collective Study on Modeling and Simulation of Resistive Random Access Memory

    NASA Astrophysics Data System (ADS)

    Panda, Debashis; Sahu, Paritosh Piyush; Tseng, Tseung Yuen

    2018-01-01

    In this work, we provide a comprehensive discussion on the various models proposed for the design and description of resistive random access memory (RRAM), being a nascent technology is heavily reliant on accurate models to develop efficient working designs and standardize its implementation across devices. This review provides detailed information regarding the various physical methodologies considered for developing models for RRAM devices. It covers all the important models reported till now and elucidates their features and limitations. Various additional effects and anomalies arising from memristive system have been addressed, and the solutions provided by the models to these problems have been shown as well. All the fundamental concepts of RRAM model development such as device operation, switching dynamics, and current-voltage relationships are covered in detail in this work. Popular models proposed by Chua, HP Labs, Yakopcic, TEAM, Stanford/ASU, Ielmini, Berco-Tseng, and many others have been compared and analyzed extensively on various parameters. The working and implementations of the window functions like Joglekar, Biolek, Prodromakis, etc. has been presented and compared as well. New well-defined modeling concepts have been discussed which increase the applicability and accuracy of the models. The use of these concepts brings forth several improvements in the existing models, which have been enumerated in this work. Following the template presented, highly accurate models would be developed which will vastly help future model developers and the modeling community.

  1. Guilt as a Motivator for Moral Judgment: An Autobiographical Memory Study

    PubMed Central

    Knez, Igor; Nordhall, Ola

    2017-01-01

    The aim was to investigate the phenomenology of self-defining moral memory and its relations to self-conscious feelings of guilt and willingness to do wrong (moral intention) in social and economic moral situations. We found that people use guilt as a moral motivator for their moral intention. The reparative function of guilt varied, however, with type of situation; that is, participants felt guiltier and were less willing to do wrong in economic compared to social moral situations. The self-defining moral memory was shown to be relatively more easy to access (accessibility), logically structured (coherence), vivid, seen from the first-person perspective (visual perspective), real (sensory detail); but was relatively less positive (valence), emotionally intense, chronologically clear (time perspective), in agreement with the present self (distancing), and shared. Finally, it was indicated that the more guilt people felt the more hidden/denied (less accessible), but more real (more sensory details), the self-defining moral memory. PMID:28539906

  2. Fencing network direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOEpatents

    Blocksome, Michael A.; Mamidala, Amith R.

    2015-07-07

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to a deterministic data communications network through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and the deterministic data communications network; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  3. Fencing network direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOEpatents

    Blocksome, Michael A.; Mamidala, Amith R.

    2015-07-14

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to a deterministic data communications network through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and the deterministic data communications network; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  4. Radiation Tolerant Intelligent Memory Stack (RTIMS)

    NASA Technical Reports Server (NTRS)

    Ng, Tak-kwong; Herath, Jeffrey A.

    2006-01-01

    The Radiation Tolerant Intelligent Memory Stack (RTIMS), suitable for both geostationary and low earth orbit missions, has been developed. The memory module is fully functional and undergoing environmental and radiation characterization. A self-contained flight-like module is expected to be completed in 2006. RTIMS provides reconfigurable circuitry and 2 gigabits of error corrected or 1 gigabit of triple redundant digital memory in a small package. RTIMS utilizes circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuitries are stacked into a module of 42.7mm x 42.7mm x 13.00mm. Triple module redundancy, current limiting, configuration scrubbing, and single event function interrupt detection are employed to mitigate radiation effects. The mitigation techniques significantly simplify system design. RTIMS is well suited for deployment in real-time data processing, reconfigurable computing, and memory intensive applications.

  5. The dynamics of sensory buffers: geometric, spatial, and experience-dependent shaping of iconic memory.

    PubMed

    Graziano, Martin; Sigman, Mariano

    2008-05-23

    When a stimulus is presented, its sensory trace decays rapidly, lasting for approximately 1000 ms. This brief and labile memory, referred as iconic memory, serves as a buffer before information is transferred to working memory and executive control. Here we explored the effect of different factors--geometric, spatial, and experience--with respect to the access and the maintenance of information in iconic memory and the progressive distortion of this memory. We studied performance in a partial report paradigm, a design wherein recall of only part of a stimulus array is required. Subjects had to report the identity of a letter in a location that was cued in a variable delay after the stimulus onset. Performance decayed exponentially with time, and we studied the different parameters (time constant, zero-delay value, and decay amplitude) as a function of the different factors. We observed that experience (determined by letter frequency) affected the access to iconic memory but not the temporal decay constant. On the contrary, spatial position affected the temporal course of delay. The entropy of the error distribution increased with time reflecting a progressive morphological distortion of the iconic buffer. We discuss our results on the context of a model of information access to executive control and how it is affected by learning and attention.

  6. ACCESS: A Communicating and Cooperating Expert Systems System.

    DTIC Science & Technology

    1988-01-31

    therefore more quickly accepted by programmers. This is in part due to the already familiar concepts of multi-processing environments (e.g. semaphores ...Di68] and monitors [Br75]) which can be viewed as a special case of synchronized shared memory models [Di6S]. Heterogeneous systems however, are by...locality of nodes is not possible and frequent access of memory is required. Synchronization of processes also suffers from a loss of efficiency in

  7. Spatial transposition gradients in visual working memory.

    PubMed

    Rerko, Laura; Oberauer, Klaus; Lin, Hsuan-Yu

    2014-01-01

    In list memory, access to individual items reflects limits of temporal distinctiveness. This is reflected in the finding that neighbouring list items tend to be confused most often. This article investigates the analogous effect of spatial proximity in a visual working-memory task. Items were presented in different locations varying in spatial distance. A retro-cue indicated the location of the item relevant for the subsequent memory test. In two recognition experiments, probes matching spatially close neighbours of the relevant item led to more false alarms than probes matching distant neighbours or non-neighbouring memory items. In two probed-recall experiments, one with simultaneous, the other with sequential memory item presentation, items closer to the cued location were more frequently chosen for recall than more distant items. These results reflect a spatial transposition gradient analogous to the temporal transposition gradient in serial recall and challenge fixed-capacity models of visual working memory (WM).

  8. A wide bandwidth CCD buffer memory system

    NASA Technical Reports Server (NTRS)

    Siemens, K.; Wallace, R. W.; Robinson, C. R.

    1978-01-01

    A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. CCD shift register memories (8K bit) were used to construct a feasibility model 128 K-bit buffer memory system. Serial data that can have rates between 150 kHz and 4.0 MHz can be stored in 4K-bit, randomly-accessible memory blocks. Peak power dissipation during a data transfer is less than 7 W, while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. System expansion to accommodate parallel inputs or a greater number of memory blocks can be performed in a modular fashion. Since the control logic does not increase proportionally to increase in memory capacity, the power requirements per bit of storage can be reduced significantly in a larger system.

  9. Memory, language, and ageing.

    PubMed Central

    Burke, D M; Mackay, D G

    1997-01-01

    This overview provides both theoretical and empirical reasons for emphasizing practice and familiar skills as a practical strategy for enhancing cognitive functioning in old age. Our review of empirical research on age-related changes in memory and language reveals a consistent pattern of spared and impaired abilities in normal old age. Relatively preserved in old age is memory performance involving highly practised skills and familiar information, including factual, semantic and autobiographical information. Relatively impaired in old age is memory performance that requires the formation of new connections, for example, recall of recent autobiographical experiences, new facts or the source of newly acquired facts. This pattern of impaired new learning versus preserved old learning cuts across distinctions between semantic memory, episodic memory, explicit memory and perhaps also implicit memory. However, familiar verbal information is not completely preserved when accessed on the output side rather than the input side: aspects of language production, namely word finding and spelling, exhibit significant age-related declines. This emerging pattern of preserved and impaired abilities presents a fundamental challenge for theories of cognitive ageing, which must explain why some aspects of language and memory are more vulnerable to the effects of ageing than others. Information-universal theories, involving mechanisms such as general slowing that are independent of the type or structure of the information being processed, require additional mechanisms to account for this pattern of cognitive aging. Information-specific theories, where the type or structure of the postulated memory units can influence the effects of cognitive ageing, are able to account for this emerging pattern, but in some cases require further development to account for comprehensive cognitive changes such as general slowing. PMID:9460069

  10. Memory inhibition as a critical factor preventing creative problem solving.

    PubMed

    Gómez-Ariza, Carlos J; Del Prete, Francesco; Prieto Del Val, Laura; Valle, Tania; Bajo, M Teresa; Fernandez, Angel

    2017-06-01

    The hypothesis that reduced accessibility to relevant information can negatively affect problem solving in a remote associate test (RAT) was tested by using, immediately before the RAT, a retrieval practice procedure to hinder access to target solutions. The results of 2 experiments clearly showed that, relative to baseline, target words that had been competitors during selective retrieval were much less likely to be provided as solutions in the RAT, demonstrating that performance in the problem-solving task was strongly influenced by the predetermined accessibility status of the solutions in memory. Importantly, this was so even when participants were unaware of the relationship between the memory and the problem-solving procedures in the experiments. This finding is consistent with an inhibitory account of retrieval-induced forgetting effects and, more generally, constitutes support for the idea that the activation status of mental representations originating in a given task (e.g., episodic memory) can unwittingly have significant consequences for a different, unrelated task (e.g., problem solving). (PsycINFO Database Record (c) 2017 APA, all rights reserved).

  11. Application of holographic optical techniques to bulk memory.

    NASA Technical Reports Server (NTRS)

    Anderson, L. K.

    1971-01-01

    Current efforts to exploit the spatial redundancy and built-in imaging of holographic optical techniques to provide high information densities without critical alignment and tight mechanical tolerances are reviewed. Read-write-erase in situ operation is possible but is presently impractical because of limitations in available recording media. As these are overcome, it should prove feasible to build holographic bulk memories with mechanically replaceable hologram plates featuring very fast (less than 2 microsec) random access to large (greater than 100 million bit) data blocks and very high throughput (greater than 500 Mbit/sec). Using volume holographic storage it may eventually be possible to realize random-access mass memories which require no mechanical motion and yet provide very high capacity.

  12. In-Memory Business Intelligence: Concepts and Performance

    NASA Astrophysics Data System (ADS)

    Rantung, V. P.; Kembuan, O.; Rompas, P. T. D.; Mewengkang, A.; Liando, O. E. S.; Sumayku, J.

    2018-02-01

    This research aims to discuss in-memory Business Intelligent (BI) and to model the business analysis questions to know the performance of the in-memory BI. By using, the Qlickview application found BI dashboards that easily accessed and modified. The dashboards are developed together using an agile development approach such as pre-study, planning, iterative execution, implementation, and evaluation. At the end, this research helping analyzer in choosing a right implementation for BI solution.

  13. Memory-efficient table look-up optimized algorithm for context-based adaptive variable length decoding in H.264/advanced video coding

    NASA Astrophysics Data System (ADS)

    Wang, Jianhua; Cheng, Lianglun; Wang, Tao; Peng, Xiaodong

    2016-03-01

    Table look-up operation plays a very important role during the decoding processing of context-based adaptive variable length decoding (CAVLD) in H.264/advanced video coding (AVC). However, frequent table look-up operation can result in big table memory access, and then lead to high table power consumption. Aiming to solve the problem of big table memory access of current methods, and then reduce high power consumption, a memory-efficient table look-up optimized algorithm is presented for CAVLD. The contribution of this paper lies that index search technology is introduced to reduce big memory access for table look-up, and then reduce high table power consumption. Specifically, in our schemes, we use index search technology to reduce memory access by reducing the searching and matching operations for code_word on the basis of taking advantage of the internal relationship among length of zero in code_prefix, value of code_suffix and code_lengh, thus saving the power consumption of table look-up. The experimental results show that our proposed table look-up algorithm based on index search can lower about 60% memory access consumption compared with table look-up by sequential search scheme, and then save much power consumption for CAVLD in H.264/AVC.

  14. A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications

    NASA Astrophysics Data System (ADS)

    Liu, Chunsen; Yan, Xiao; Song, Xiongfei; Ding, Shijin; Zhang, David Wei; Zhou, Peng

    2018-05-01

    As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

  15. Object selection costs in visual working memory: A diffusion model analysis of the focus of attention.

    PubMed

    Sewell, David K; Lilburn, Simon D; Smith, Philip L

    2016-11-01

    A central question in working memory research concerns the degree to which information in working memory is accessible to other cognitive processes (e.g., decision-making). Theories assuming that the focus of attention can only store a single object at a time require the focus to orient to a target representation before further processing can occur. The need to orient the focus of attention implies that single-object accounts typically predict response time costs associated with object selection even when working memory is not full (i.e., memory load is less than 4 items). For other theories that assume storage of multiple items in the focus of attention, predictions depend on specific assumptions about the way resources are allocated among items held in the focus, and how this affects the time course of retrieval of items from the focus. These broad theoretical accounts have been difficult to distinguish because conventional analyses fail to separate components of empirical response times related to decision-making from components related to selection and retrieval processes associated with accessing information in working memory. To better distinguish these response time components from one another, we analyze data from a probed visual working memory task using extensions of the diffusion decision model. Analysis of model parameters revealed that increases in memory load resulted in (a) reductions in the quality of the underlying stimulus representations in a manner consistent with a sample size model of visual working memory capacity and (b) systematic increases in the time needed to selectively access a probed representation in memory. The results are consistent with single-object theories of the focus of attention. The results are also consistent with a subset of theories that assume a multiobject focus of attention in which resource allocation diminishes both the quality and accessibility of the underlying representations. (PsycINFO Database Record (c) 2016

  16. 77 FR 33240 - Certain Semiconductor Chips With DRAM Circuitry, and Modules and Products Containing Same...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-06-05

    ... viewed on the Commission's electronic docket (EDIS) at http://edis.usitc.gov . Hearing-impaired persons... December 21, 2011, based on a complaint filed by Elpida Memory, Inc. of Tokyo, Japan and Elpida Memory (USA...

  17. Supporting shared data structures on distributed memory architectures

    NASA Technical Reports Server (NTRS)

    Koelbel, Charles; Mehrotra, Piyush; Vanrosendale, John

    1990-01-01

    Programming nonshared memory systems is more difficult than programming shared memory systems, since there is no support for shared data structures. Current programming languages for distributed memory architectures force the user to decompose all data structures into separate pieces, with each piece owned by one of the processors in the machine, and with all communication explicitly specified by low-level message-passing primitives. A new programming environment is presented for distributed memory architectures, providing a global name space and allowing direct access to remote parts of data values. The analysis and program transformations required to implement this environment are described, and the efficiency of the resulting code on the NCUBE/7 and IPSC/2 hypercubes are described.

  18. Memory Loss and Retrieval

    ERIC Educational Resources Information Center

    Reid, Ian

    2016-01-01

    Underlying the generally oblivious attitude of teachers and learners towards the past is insufficient respect for the role of memory in giving meaning to experience and access to knowledge. We shape our identity by making sense of our past and its relationship to present and future selves, a process that should be intensively cultivated when we…

  19. Left Ventrolateral Prefrontal Cortex and the Cognitive Control of Memory

    ERIC Educational Resources Information Center

    Badre, David; Wagner, Anthony D.

    2007-01-01

    Cognitive control mechanisms permit memory to be accessed strategically, and so aid in bringing knowledge to mind that is relevant to current goals and actions. In this review, we consider the contribution of left ventrolateral prefrontal cortex (VLPFC) to the cognitive control of memory. Reviewed evidence supports a two-process model of mnemonic…

  20. Patterns of Autobiographical Memory in Adults with Autism Spectrum Disorder

    ERIC Educational Resources Information Center

    Crane, Laura; Pring, Linda; Jukes, Kaylee; Goddard, Lorna

    2012-01-01

    Two studies are presented that explored the effects of experimental manipulations on the quality and accessibility of autobiographical memories in adults with autism spectrum disorder (ASD), relative to a typical comparison group matched for age, gender and IQ. Both studies found that the adults with ASD generated fewer specific memories than the…

  1. Hemispheric Differences in the Organization of Memory for Text Ideas

    ERIC Educational Resources Information Center

    Long, Debra L.; Johns, Clinton L.; Jonathan, Eunike

    2012-01-01

    The goal of this study was to examine hemispheric asymmetries in episodic memory for discourse. Access to previously comprehended information is essential for mapping incoming information to representations of "who did what to whom" in memory. An item-priming-in-recognition paradigm was used to examine differences in how the hemispheres represent…

  2. Vertical bloch line memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Stadler, Henry L. (Inventor); Wu, Jiin-chuan (Inventor)

    1995-01-01

    A new read gate design for the vertical Bloch line (VBL) memory is disclosed which offers larger operating margin than the existing read gate designs. In the existing read gate designs, a current is applied to all the stripes. The stripes that contain a VBL pair are chopped, while the stripes that do not contain a VBL pair are not chopped. The information is then detected by inspecting the presence or absence of the bubble. The margin of the chopping current amplitude is very small, and sometimes non-existent. A new method of reading Vertical Bloch Line memory is also disclosed. Instead of using the wall chirality to separate the two binary states, the spatial deflection of the stripe head is used. Also disclosed herein is a compact memory which uses vertical Bloch line (VBL) memory technology for providing data storage. A three-dimensional arrangement in the form of stacks of VBL memory layers is used to achieve high volumetric storage density. High data transfer rate is achieved by operating all the layers in parallel. Using Hall effect sensing, and optical sensing via the Faraday effect to access the data from within the three-dimensional packages, an even higher data transfer rate can be achieved due to parallel operation within each layer.

  3. Radiation Test Challenges for Scaled Commerical Memories

    NASA Technical Reports Server (NTRS)

    LaBel, Kenneth A.; Ladbury, Ray L.; Cohn, Lewis M.; Oldham, Timothy

    2007-01-01

    As sub-100nm CMOS technologies gather interest, the radiation effects performance of these technologies provide a significant challenge. In this talk, we shall discuss the radiation testing challenges as related to commercial memory devices. The focus will be on complex test and failure modes emerging in state-of-the-art Flash non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs), which are volatile. Due to their very high bit density, these device types are highly desirable for use in the natural space environment. In this presentation, we shall discuss these devices with emphasis on considerations for test and qualification methods required.

  4. Thin Co/Ni-based bottom pinned spin-transfer torque magnetic random access memory stacks with high annealing tolerance

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Tomczak, Y., E-mail: Yoann.Tomczak@imec.be; Department of Chemistry, KU Leuven; Swerts, J.

    2016-01-25

    Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as a replacement for next generation embedded and stand-alone memory applications. One of the main challenges in the STT-MRAM stack development is the compatibility of the stack with CMOS process flows in which thermal budgets up to 400 °C are applied. In this letter, we report on a perpendicularly magnetized MgO-based tunnel junction (p-MTJ) on a thin Co/Ni perpendicular synthetic antiferromagnetic layer with high annealing tolerance. Tunnel magneto resistance (TMR) loss after annealing occurs when the reference layer loses its perpendicular magnetic anisotropy due to reduction of the CoFeB/MgO interfacial anisotropy. Amore » stable Co/Ni based p-MTJ stack with TMR values of 130% at resistance-area products of 9 Ω μm{sup 2} after 400 °C anneal is achieved via moment control of the Co/Ta/CoFeB reference layer. Thinning of the CoFeB polarizing layer down to 0.8 nm is the key enabler to achieve 400 °C compatibility with limited TMR loss. Thinning the Co below 0.6 nm leads to a loss of the antiferromagnetic interlayer exchange coupling strength through Ru. Insight into the thickness and moment engineering of the reference layer is displayed to obtain the best magnetic properties and high thermal stability for thin Co/Ni SAF-based STT-MRAM stacks.« less

  5. Memory Dynamics and Decision Making in Younger and Older Adults

    ERIC Educational Resources Information Center

    Lechuga, M. Teresa; Gomez-Ariza, Carlos J.; Iglesias-Parro, Sergio; Pelegrina, Santiago

    2012-01-01

    The main aim of this research was to study whether memory dynamics influence older people's choices to the same extent as younger's ones. To do so, we adapted the retrieval-practice paradigm to produce variations in memory accessibility of information on which decisions were made later. Based on previous results, we expected to observe…

  6. A Simple Solution to Providing Remote Access to CD-ROM.

    ERIC Educational Resources Information Center

    Garnham, Carla T.; Brodie, Kent

    1990-01-01

    A pilot project at the Medical College of Wisconsin illustrates how even small computing organizations with limited financial and staff resources can provide remote access to CD-ROM (Compact Disc-Read-Only-Memory) databases, and that providing such convenient access to a vast array of useful information can greatly benefit faculty and students.…

  7. Retrieval of memories with the help of music in Alzheimer's disease.

    PubMed

    Chevreau, Priscilia; Nizard, Ingrid; Allain, Philippe

    2017-09-01

    This study focuses on music as a mediator facilitating access to autobiographical memory in Alzheimer's disease (AD). Studies on this topic are rare, but available data have shown a beneficial effect of music on autobiographical performance in AD patients. Based on the "index word" method, we developed the "index music" method for the evaluation of autobiographical memory. The subjects had to tell a memory of their choice from the words or music presented to them. The task was proposed to 54 patients with diagnosis of AD according to DSM IV and NINCDS-ADRDA criteria. All of them had a significant cognitive decline on the MMSE (mean score: 14.5). Patients were matched by age, sex and level of education with 48 control subjects without cognitive impairment (mean score on the MMSE: 28). Results showed that autobiographical memory quantity scores of AD patients were significantly lower than those of healthy control in both methods. However, autobiographical memory quality scores of AD patients increased with "index music" whereas autobiographical memory quality scores of healthy control decreased. Also, the autobiographical performance of patients with AD in condition index music was not correlated with cognitive performance in contrast to the autobiographical performances in index word. These results confirm that music improves access to personal memories in patients with AD. Personal memories could be preserved in patients with AD and music could constitute an interesting way to stimulate recollection.

  8. Genome accessibility is widely preserved and locally modulated during mitosis

    PubMed Central

    Hsiung, Chris C.-S.; Morrissey, Christapher S.; Udugama, Maheshi; Frank, Christopher L.; Keller, Cheryl A.; Baek, Songjoon; Giardine, Belinda; Crawford, Gregory E.; Sung, Myong-Hee; Hardison, Ross C.

    2015-01-01

    Mitosis entails global alterations to chromosome structure and nuclear architecture, concomitant with transient silencing of transcription. How cells transmit transcriptional states through mitosis remains incompletely understood. While many nuclear factors dissociate from mitotic chromosomes, the observation that certain nuclear factors and chromatin features remain associated with individual loci during mitosis originated the hypothesis that such mitotically retained molecular signatures could provide transcriptional memory through mitosis. To understand the role of chromatin structure in mitotic memory, we performed the first genome-wide comparison of DNase I sensitivity of chromatin in mitosis and interphase, using a murine erythroblast model. Despite chromosome condensation during mitosis visible by microscopy, the landscape of chromatin accessibility at the macromolecular level is largely unaltered. However, mitotic chromatin accessibility is locally dynamic, with individual loci maintaining none, some, or all of their interphase accessibility. Mitotic reduction in accessibility occurs primarily within narrow, highly DNase hypersensitive sites that frequently coincide with transcription factor binding sites, whereas broader domains of moderate accessibility tend to be more stable. In mitosis, proximal promoters generally maintain their accessibility more strongly, whereas distal regulatory elements tend to lose accessibility. Large domains of DNA hypomethylation mark a subset of promoters that retain accessibility during mitosis and across many cell types in interphase. Erythroid transcription factor GATA1 exerts site-specific changes in interphase accessibility that are most pronounced at distal regulatory elements, but has little influence on mitotic accessibility. We conclude that features of open chromatin are remarkably stable through mitosis, but are modulated at the level of individual genes and regulatory elements. PMID:25373146

  9. Amorphous Semiconductors: From Photocatalyst to Computer Memory

    NASA Astrophysics Data System (ADS)

    Sundararajan, Mayur

    encouraging but inconclusive. Then the method was successfully demonstrated on mesoporous TiO2SiO 2 by showing a shift in its optical bandgap. One of the special class of amorphous semiconductors is chalcogenide glasses, which exhibit high ionic conductivity even at room temperature. When metal doped chalcogenide glasses are under an electric field, they become electronically conductive. These properties are exploited in the computer memory storage application of Conductive Bridging Random Access Memory (CBRAM). CBRAM is a non-volatile memory that is a strong contender to replace conventional volatile RAMs such as DRAM, SRAM, etc. This technology has already been commercialized, but the working mechanism is still not clearly understood especially the nature of the conductive bridge filament. In this project, the CBRAM memory cells are fabricated by thermal evaporation method with Agx(GeSe 2)1-x as the solid electrolyte layer, Ag as the active electrode and Au as the inert electrode. By careful use of cyclic voltammetry, the conductive filaments were grown on the surface and the bulk of the solid electrolyte. The comparison between the two filaments revealed major differences leading to contradiction with the existing working mechanism. After compiling all the results, a modified working mechanism is proposed. SAXS is a powerful tool to characterize nanostructure of glasses. The analysis of the SAXS data to get useful information are usually performed by different programs. In this project, Irena and GIFT programs were compared by performing the analysis of the SAXS data of glass and glass ceramics samples. Irena was shown to be not suitable for the analysis of SAXS data that has a significant contribution from interparticle interactions. GIFT was demonstrated to be better suited for such analysis. Additionally, the results obtained by programs for samples with low interparticle interactions were shown to be consistent.

  10. Episodic-like memory in the rat.

    PubMed

    Babb, Stephanie J; Crystal, Jonathon D

    2006-07-11

    A fundamental question in comparative cognition is whether animals remember unique, personal past experiences. It has long been argued that memories for specific events (referred to as episodic memory) are unique to humans. Recently, considerable evidence has accumulated to show that food-storing birds possess critical behavioral elements of episodic memory, referred to as episodic-like memory in acknowledgment of the fact that behavioral criteria do not assess subjective experiences. Here we show that rats have a detailed representation of remembered events and meet behavioral criteria for episodic-like memory. We provided rats with access to locations baited with distinctive (e.g., grape and raspberry) or nondistinctive (regular chow) flavors. Locations with a distinctive flavor replenished after a long but not a short delay, and locations with the nondistinctive flavor never replenished. One distinctive flavor was devalued after encoding its location by prefeeding that flavor (satiation) or by pairing it with lithium chloride (acquired taste aversion), while the other distinctive flavor was not devalued. The rats selectively decreased revisits to the devalued distinctive flavor but not to the nondevalued distinctive flavor. The present studies demonstrate that rats selectively encode the content of episodic-like memories.

  11. Resonator memories and optical novelty filters

    NASA Astrophysics Data System (ADS)

    Anderson, Dana Z.; Erle, Marie C.

    Optical resonators having holographic elements are potential candidates for storing information that can be accessed through content addressable or associative recall. Closely related to the resonator memory is the optical novelty filter, which can detect the differences between a test object and a set of reference objects. We discuss implementations of these devices using continuous optical media such as photorefractive materials. The discussion is framed in the context of neural network models. There are both formal and qualitative similarities between the resonator memory and optical novelty filter and network models. Mode competition arises in the theory of the resonator memory, much as it does in some network models. We show that the role of the phenomena of "daydreaming" in the real-time programmable optical resonator is very much akin to the role of "unlearning" in neural network memories. The theory of programming the real-time memory for a single mode is given in detail. This leads to a discussion of the optical novelty filter. Experimental results for the resonator memory, the real-time programmable memory, and the optical tracking novelty filter are reviewed. We also point to several issues that need to be addressed in order to implement more formal models of neural networks.

  12. Resonator Memories And Optical Novelty Filters

    NASA Astrophysics Data System (ADS)

    Anderson, Dana Z.; Erie, Marie C.

    1987-05-01

    Optical resonators having holographic elements are potential candidates for storing information that can be accessed through content-addressable or associative recall. Closely related to the resonator memory is the optical novelty filter, which can detect the differences between a test object and a set of reference objects. We discuss implementations of these devices using continuous optical media such as photorefractive ma-terials. The discussion is framed in the context of neural network models. There are both formal and qualitative similarities between the resonator memory and optical novelty filter and network models. Mode competition arises in the theory of the resonator memory, much as it does in some network models. We show that the role of the phenomena of "daydream-ing" in the real-time programmable optical resonator is very much akin to the role of "unlearning" in neural network memories. The theory of programming the real-time memory for a single mode is given in detail. This leads to a discussion of the optical novelty filter. Experimental results for the resonator memory, the real-time programmable memory, and the optical tracking novelty filter are reviewed. We also point to several issues that need to be addressed in order to implement more formal models of neural networks.

  13. Evaluating OpenSHMEM Explicit Remote Memory Access Operations and Merged Requests

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Boehm, Swen; Pophale, Swaroop S; Gorentla Venkata, Manjunath

    The OpenSHMEM Library Specification has evolved consid- erably since version 1.0. Recently, non-blocking implicit Remote Memory Access (RMA) operations were introduced in OpenSHMEM 1.3. These provide a way to achieve better overlap between communication and computation. However, the implicit non-blocking operations do not pro- vide a separate handle to track and complete the individual RMA opera- tions. They are guaranteed to be completed after either a shmem quiet(), shmem barrier() or a shmem barrier all() is called. These are global com- pletion and synchronization operations. Though this semantic is expected to achieve a higher message rate for the applications, themore » drawback is that it does not allow fine-grained control over the completion of RMA operations. In this paper, first, we introduce non-blocking RMA operations with requests, where each operation has an explicit request to track and com- plete the operation. Second, we introduce interfaces to merge multiple requests into a single request handle. The merged request tracks multiple user-selected RMA operations, which provides the flexibility of tracking related communication operations with one request handle. Lastly, we explore the implications in terms of performance, productivity, usability and the possibility of defining different patterns of communication via merging of requests. Our experimental results show that a well designed and implemented OpenSHMEM stack can hide the overhead of allocating and managing the requests. The latency of RMA operations with requests is similar to blocking and implicit non-blocking RMA operations. We test our implementation with the Scalable Synthetic Compact Applications (SSCA #1) benchmark and observe that using RMA operations with requests and merging of these requests outperform the implementation using blocking RMA operations and implicit non-blocking operations by 49% and 74% respectively.« less

  14. Non-volatile memory based on the ferroelectric photovoltaic effect

    PubMed Central

    Guo, Rui; You, Lu; Zhou, Yang; Shiuh Lim, Zhi; Zou, Xi; Chen, Lang; Ramesh, R.; Wang, Junling

    2013-01-01

    The quest for a solid state universal memory with high-storage density, high read/write speed, random access and non-volatility has triggered intense research into new materials and novel device architectures. Though the non-volatile memory market is dominated by flash memory now, it has very low operation speed with ~10 μs programming and ~10 ms erasing time. Furthermore, it can only withstand ~105 rewriting cycles, which prevents it from becoming the universal memory. Here we demonstrate that the significant photovoltaic effect of a ferroelectric material, such as BiFeO3 with a band gap in the visible range, can be used to sense the polarization direction non-destructively in a ferroelectric memory. A prototype 16-cell memory based on the cross-bar architecture has been prepared and tested, demonstrating the feasibility of this technique. PMID:23756366

  15. `Unlearning' has a stabilizing effect in collective memories

    NASA Astrophysics Data System (ADS)

    Hopfield, J. J.; Feinstein, D. I.; Palmer, R. G.

    1983-07-01

    Crick and Mitchison1 have presented a hypothesis for the functional role of dream sleep involving an `unlearning' process. We have independently carried out mathematical and computer modelling of learning and `unlearning' in a collective neural network of 30-1,000 neurones. The model network has a content-addressable memory or `associative memory' which allows it to learn and store many memories. A particular memory can be evoked in its entirety when the network is stimulated by any adequate-sized subpart of the information of that memory2. But different memories of the same size are not equally easy to recall. Also, when memories are learned, spurious memories are also created and can also be evoked. Applying an `unlearning' process, similar to the learning processes but with a reversed sign and starting from a noise input, enhances the performance of the network in accessing real memories and in minimizing spurious ones. Although our model was not motivated by higher nervous function, our system displays behaviours which are strikingly parallel to those needed for the hypothesized role of `unlearning' in rapid eye movement (REM) sleep.

  16. A short cut to the past: Cueing via concrete objects improves autobiographical memory retrieval in Alzheimer's disease patients.

    PubMed

    Kirk, Marie; Berntsen, Dorthe

    2018-02-01

    Older adults diagnosed with Alzheimer's disease (AD) have difficulties accessing autobiographical memories. However, this deficit tends to spare memories dated to earlier parts of their lives, and may partially reflect retrieval deficits rather than complete memory loss. Introducing a novel paradigm, the present study examines whether autobiographical memory recall can be improved in AD by manipulating the sensory richness, concreteness and cultural dating of the memory cues. Specifically, we examine whether concrete everyday objects historically dated to the participants' youth (e.g., a skipping rope), relative to verbal cues (i.e., the verbal signifiers for the objects) facilitate access to autobiographical memories. The study includes 49 AD patients, and 50 healthy, older matched control participants, all tested on word versus object-cued recall. Both groups recalled significantly more memories, when cued by objects relative to words, but the advantage was significantly larger in the AD group. In both groups, memory descriptions were longer and significantly more episodic in nature in response to object-cued recall. Together these findings suggest that the multimodal nature of the object cues (i.e. vision, olfaction, audition, somatic sensation) along with specific cue characteristics, such as time reference, texture, shape, may constrain the retrieval search, potentially minimizing executive function demands, and hence strategic processing requirements, thus easing access to autobiographical memories in AD. Copyright © 2017 Elsevier Ltd. All rights reserved.

  17. Silent store detection and recording in memory storage

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Bose, Pradip; Cher, Chen-Yong; Nair, Ravi

    An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memorymore » location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.« less

  18. Adiabatic quantum optimization for associative memory recall

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Seddiqi, Hadayat; Humble, Travis S.

    Hopfield networks are a variant of associative memory that recall patterns stored in the couplings of an Ising model. Stored memories are conventionally accessed as fixed points in the network dynamics that correspond to energetic minima of the spin state. We show that memories stored in a Hopfield network may also be recalled by energy minimization using adiabatic quantum optimization (AQO). Numerical simulations of the underlying quantum dynamics allow us to quantify AQO recall accuracy with respect to the number of stored memories and noise in the input key. We investigate AQO performance with respect to how memories are storedmore » in the Ising model according to different learning rules. Our results demonstrate that AQO recall accuracy varies strongly with learning rule, a behavior that is attributed to differences in energy landscapes. Consequently, learning rules offer a family of methods for programming adiabatic quantum optimization that we expect to be useful for characterizing AQO performance.« less

  19. Adiabatic Quantum Optimization for Associative Memory Recall

    NASA Astrophysics Data System (ADS)

    Seddiqi, Hadayat; Humble, Travis

    2014-12-01

    Hopfield networks are a variant of associative memory that recall patterns stored in the couplings of an Ising model. Stored memories are conventionally accessed as fixed points in the network dynamics that correspond to energetic minima of the spin state. We show that memories stored in a Hopfield network may also be recalled by energy minimization using adiabatic quantum optimization (AQO). Numerical simulations of the underlying quantum dynamics allow us to quantify AQO recall accuracy with respect to the number of stored memories and noise in the input key. We investigate AQO performance with respect to how memories are stored in the Ising model according to different learning rules. Our results demonstrate that AQO recall accuracy varies strongly with learning rule, a behavior that is attributed to differences in energy landscapes. Consequently, learning rules offer a family of methods for programming adiabatic quantum optimization that we expect to be useful for characterizing AQO performance.

  20. Adiabatic quantum optimization for associative memory recall

    DOE PAGES

    Seddiqi, Hadayat; Humble, Travis S.

    2014-12-22

    Hopfield networks are a variant of associative memory that recall patterns stored in the couplings of an Ising model. Stored memories are conventionally accessed as fixed points in the network dynamics that correspond to energetic minima of the spin state. We show that memories stored in a Hopfield network may also be recalled by energy minimization using adiabatic quantum optimization (AQO). Numerical simulations of the underlying quantum dynamics allow us to quantify AQO recall accuracy with respect to the number of stored memories and noise in the input key. We investigate AQO performance with respect to how memories are storedmore » in the Ising model according to different learning rules. Our results demonstrate that AQO recall accuracy varies strongly with learning rule, a behavior that is attributed to differences in energy landscapes. Consequently, learning rules offer a family of methods for programming adiabatic quantum optimization that we expect to be useful for characterizing AQO performance.« less

  1. Memory and consciousness: trace distinctiveness in memory retrievals.

    PubMed

    Brunel, Lionel; Oker, Ali; Riou, Benoit; Versace, Rémy

    2010-12-01

    The aim of this article was to provide experimental evidence that classical dissociation between levels of consciousness associated with memory retrieval (i.e., implicit or explicit) can be explained in terms of task dependency and distinctiveness of traces. In our study phase, we manipulated the level of isolation (partial vs. global) of the memory trace by means of an isolation paradigm (isolated words among non-isolated words). We then tested these two types of isolation in a series of tasks of increasing complexity: a lexical decision task, a recognition task, and a free recall task. The main result of this study was that distinctiveness effects were observed as a function of the type of isolation (level of isolation) and the nature of the task. We concluded that trace distinctiveness improves subsequent access to the trace, while the level of trace distinctiveness also appears to determine the possibility of conscious or explicit retrieval. Copyright © 2010 Elsevier Inc. All rights reserved.

  2. Memory-Based Approaches and Beyond

    ERIC Educational Resources Information Center

    Sanford, Anthony J.; Garrod, Simon C.

    2005-01-01

    In this article, we discuss 2 issues that we believe any theory of discourse comprehension has to take account of-accessing irrelevant information and granularity. Along the lines that have been suggested as demonstrating the memory-based account, we describe some work in favor of the recruitment of apparently irrelevant information from memory…

  3. Hybrid Shape Memory Alloy Composites for Extreme Environments

    DTIC Science & Technology

    2011-10-01

    Shape Memory Alloys in Oil Well Applications,” Sintef Petroleum Research, 1999, Trondheim, Norway. 5. Hartl , D. J., Lagoudas, D., Mabe , J., Calkins...Materials and Structures, Vol. 19, No. 1., 2009. 6. Hartl , D. J., Lagoudas, D., Mabe , J., Calkins, F., and Mooney, J., “Use of Ni60Ti Shape Memory...hydraulic actuators) and can thus be located in environments not previously accessible. SMA actuators can also be found in the aerospace ( Hartl and

  4. Optical memory development. Volume 2: Gain-assisted holographic storage media

    NASA Technical Reports Server (NTRS)

    Gange, R. A.; Mezrich, R. S.

    1972-01-01

    Thin deformable films were investigated for use as the storage medium in a holographic optical memory. The research was directed toward solving the problems of material fatigue, selective heat addressing, electrical charging of the film surface and charge patterning by light. A number of solutions to these problems were found but the main conclusion to be drawn from the work is that deformable media which employ heat in the recording process are not satisfactory for use in a high-speed random-access read/write holographic memory. They are, however, a viable approach in applications where either high speed or random-access is not required.

  5. Memory consolidation in humans: new evidence and opportunities

    PubMed Central

    Maguire, Eleanor A

    2014-01-01

    We are endlessly fascinated by memory; we desire to improve it and fear its loss. While it has long been recognized that brain regions such as the hippocampus are vital for supporting memories of our past experiences (autobiographical memories), we still lack fundamental knowledge about the mechanisms involved. This is because the study of specific neural signatures of autobiographical memories in vivo in humans presents a significant challenge. However, recent developments in high-resolution structural and functional magnetic resonance imaging coupled with advanced analytical methods now permit access to the neural substrates of memory representations that has hitherto been precluded in humans. Here, I describe how the application of ‘decoding’ techniques to brain-imaging data is beginning to disclose how individual autobiographical memory representations evolve over time, deepening our understanding of systems-level consolidation. In particular, this prompts new questions about the roles of the hippocampus and ventromedial prefrontal cortex and offers new opportunities to interrogate the elusive memory trace that has for so long confounded neuroscientists. PMID:24414174

  6. Rapid recovery from transient faults in the fault-tolerant processor with fault-tolerant shared memory

    NASA Technical Reports Server (NTRS)

    Harper, Richard E.; Butler, Bryan P.

    1990-01-01

    The Draper fault-tolerant processor with fault-tolerant shared memory (FTP/FTSM), which is designed to allow application tasks to continue execution during the memory alignment process, is described. Processor performance is not affected by memory alignment. In addition, the FTP/FTSM incorporates a hardware scrubber device to perform the memory alignment quickly during unused memory access cycles. The FTP/FTSM architecture is described, followed by an estimate of the time required for channel reintegration.

  7. A diary after dinner: How the time of event recording influences later accessibility of diary events.

    PubMed

    Szőllősi, Ágnes; Keresztes, Attila; Conway, Martin A; Racsmány, Mihály

    2015-01-01

    Recording the events of a day in a diary may help improve their later accessibility. An interesting question is whether improvements in long-term accessibility will be greater if the diary is completed at the end of the day, or after a period of sleep, the following morning. We investigated this question using an internet-based diary method. On each of five days, participants (n = 109) recorded autobiographical memories for that day or for the previous day. Recording took place either in the morning or in the evening. Following a 30-day retention interval, the diary events were free recalled. We found that participants who recorded their memories in the evening before sleep had best memory performance. These results suggest that the time of reactivation and recording of recent autobiographical events has a significant effect on the later accessibility of those diary events. We discuss our results in the light of related findings that show a beneficial effect of reduced interference during sleep on memory consolidation and reconsolidation.

  8. Ferroelectric tunneling element and memory applications which utilize the tunneling element

    DOEpatents

    Kalinin, Sergei V [Knoxville, TN; Christen, Hans M [Knoxville, TN; Baddorf, Arthur P [Knoxville, TN; Meunier, Vincent [Knoxville, TN; Lee, Ho Nyung [Oak Ridge, TN

    2010-07-20

    A tunneling element includes a thin film layer of ferroelectric material and a pair of dissimilar electrically-conductive layers disposed on opposite sides of the ferroelectric layer. Because of the dissimilarity in composition or construction between the electrically-conductive layers, the electron transport behavior of the electrically-conductive layers is polarization dependent when the tunneling element is below the Curie temperature of the layer of ferroelectric material. The element can be used as a basis of compact 1R type non-volatile random access memory (RAM). The advantages include extremely simple architecture, ultimate scalability and fast access times generic for all ferroelectric memories.

  9. Reasoning and Memory: People Make Varied Use of the Information Available in Working Memory

    ERIC Educational Resources Information Center

    Hardman, Kyle O.; Cowan, Nelson

    2016-01-01

    Working memory (WM) is used for storing information in a highly accessible state so that other mental processes, such as reasoning, can use that information. Some WM tasks require that participants not only store information, but also reason about that information to perform optimally on the task. In this study, we used visual WM tasks that had…

  10. Evaluating architecture impact on system energy efficiency

    PubMed Central

    Yu, Shijie; Wang, Rui; Luan, Zhongzhi; Qian, Depei

    2017-01-01

    As the energy consumption has been surging in an unsustainable way, it is important to understand the impact of existing architecture designs from energy efficiency perspective, which is especially valuable for High Performance Computing (HPC) and datacenter environment hosting tens of thousands of servers. One obstacle hindering the advance of comprehensive evaluation on energy efficiency is the deficient power measuring approach. Most of the energy study relies on either external power meters or power models, both of these two methods contain intrinsic drawbacks in their practical adoption and measuring accuracy. Fortunately, the advent of Intel Running Average Power Limit (RAPL) interfaces has promoted the power measurement ability into next level, with higher accuracy and finer time resolution. Therefore, we argue it is the exact time to conduct an in-depth evaluation of the existing architecture designs to understand their impact on system energy efficiency. In this paper, we leverage representative benchmark suites including serial and parallel workloads from diverse domains to evaluate the architecture features such as Non Uniform Memory Access (NUMA), Simultaneous Multithreading (SMT) and Turbo Boost. The energy is tracked at subcomponent level such as Central Processing Unit (CPU) cores, uncore components and Dynamic Random-Access Memory (DRAM) through exploiting the power measurement ability exposed by RAPL. The experiments reveal non-intuitive results: 1) the mismatch between local compute and remote memory node caused by NUMA effect not only generates dramatic power and energy surge but also deteriorates the energy efficiency significantly; 2) for multithreaded application such as the Princeton Application Repository for Shared-Memory Computers (PARSEC), most of the workloads benefit a notable increase of energy efficiency using SMT, with more than 40% decline in average power consumption; 3) Turbo Boost is effective to accelerate the workload execution

  11. Evaluating architecture impact on system energy efficiency.

    PubMed

    Yu, Shijie; Yang, Hailong; Wang, Rui; Luan, Zhongzhi; Qian, Depei

    2017-01-01

    As the energy consumption has been surging in an unsustainable way, it is important to understand the impact of existing architecture designs from energy efficiency perspective, which is especially valuable for High Performance Computing (HPC) and datacenter environment hosting tens of thousands of servers. One obstacle hindering the advance of comprehensive evaluation on energy efficiency is the deficient power measuring approach. Most of the energy study relies on either external power meters or power models, both of these two methods contain intrinsic drawbacks in their practical adoption and measuring accuracy. Fortunately, the advent of Intel Running Average Power Limit (RAPL) interfaces has promoted the power measurement ability into next level, with higher accuracy and finer time resolution. Therefore, we argue it is the exact time to conduct an in-depth evaluation of the existing architecture designs to understand their impact on system energy efficiency. In this paper, we leverage representative benchmark suites including serial and parallel workloads from diverse domains to evaluate the architecture features such as Non Uniform Memory Access (NUMA), Simultaneous Multithreading (SMT) and Turbo Boost. The energy is tracked at subcomponent level such as Central Processing Unit (CPU) cores, uncore components and Dynamic Random-Access Memory (DRAM) through exploiting the power measurement ability exposed by RAPL. The experiments reveal non-intuitive results: 1) the mismatch between local compute and remote memory node caused by NUMA effect not only generates dramatic power and energy surge but also deteriorates the energy efficiency significantly; 2) for multithreaded application such as the Princeton Application Repository for Shared-Memory Computers (PARSEC), most of the workloads benefit a notable increase of energy efficiency using SMT, with more than 40% decline in average power consumption; 3) Turbo Boost is effective to accelerate the workload execution

  12. Autobiographical memory decline in Alzheimer’s Disease

    PubMed Central

    EL HAJ, Mohamad; Antoine, Pascal; Nandrino, Jean-Louis; Kapogiannis, Dimitrios

    2016-01-01

    Autobiographical memory, or memory for personal experiences, allows individuals to define themselves and construct a meaningful life story. Decline of this ability, as observed in Alzheimer’s Disease (AD), results in an impaired sense of self and identity. We present a critical review of theories and findings regarding cognitive and neuroanatomical underpinnings of autobiographical memory and its decline in AD and highlight studies on its clinical rehabilitation. We propose that autobiographical recall in AD is mainly characterized by loss of associated episodic information, which leads to de-contextualisation of autobiographical memories and a shift from reliving past events to a general sense of familiarity. This decline refers to retrograde, but also anterograde amnesia that affects newly acquired memories besides remote ones. One consequence of autobiographical memory decline in AD is decreased access to memories that shape self-consciousness, self-knowledge, and self-images, leading to a diminished sense of self and identity. The link between autobiographical decline and compromised sense of self in AD can also manifest itself as low correspondence and coherence between past memories and current goals and beliefs. By linking cognitive, neuroanatomical, and clinical aspects of autobiographical decline in AD, our review provides a theoretical foundation, which may lead to better rehabilitation strategies. PMID:26876367

  13. Individual Differences in the Effects of Retrieval from Long-Term Memory

    ERIC Educational Resources Information Center

    Brewer, Gene A.; Unsworth, Nash

    2012-01-01

    The current study examined individual differences in the effects of retrieval from long-term memory (i.e., the testing effect). The effects of retrieving from memory make tested information more accessible for future retrieval attempts. Despite the broad applied ramifications of such a potent memorization technique there is a paucity of research…

  14. Episodic and Semantic Memory Influences on Picture Naming in Alzheimer's Disease

    ERIC Educational Resources Information Center

    Small, Jeff A.; Sandhu, Nirmaljeet

    2008-01-01

    This study investigated the relationship between semantic and episodic memory as they support lexical access by healthy younger and older adults and individuals with Alzheimer's disease (AD). In particular, we were interested in examining the pattern of semantic and episodic memory declines in AD (i.e., word-finding difficulty and impaired recent…

  15. Blackcomb: Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Schreiber, Robert

    Summary of technical results of Blackcomb Memory Devices We explored various different memory technologies (STTRAM, PCRAM, FeRAM, and ReRAM). The progress can be classified into three categories, below. Modeling and Tool Releases Various modeling tools have been developed over the last decade to help in the design of SRAM or DRAM-based memory hierarchies. To explore new design opportunities that NVM technologies can bring to the designers, we have developed similar high-level models for NVM, including PCRAMsim [Dong 2009], NVSim [Dong 2012], and NVMain [Poremba 2012]. NVSim is a circuit-level model for NVM performance, energy, and area estimation, which supports variousmore » NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies. On the other side, NVMain is a cycle accurate main memory simulator designed to simulate emerging nonvolatile memories at the architectural level. We have released these models as open source tools and provided contiguous support to them. We also proposed PS3-RAM, which is a fast, portable and scalable statistical STT-RAM reliability analysis model [Wen 2012]. Design Space Exploration and Optimization With the support of these models, we explore different device/circuit optimization techniques. For example, in [Niu 2012a] we studied the power reduction technique for the application of ECC scheme in ReRAM designs and proposed to use ECC code to relax the BER (Bit Error Rate) requirement of a single memory to improve the write energy consumption and latency for both 1T1R and cross-point ReRAM designs. In [Xu 2011], we proposed a methodology to design STT-RAM for different optimization goals such as read performance, write performance and write energy by leveraging the trade-off between write current and write time of MTJ. We also studied the tradeoffs in building a reliable

  16. Role of Al2O3 thin layer on improving the resistive switching properties of Ta5Si3-based conductive bridge random accesses memory device

    NASA Astrophysics Data System (ADS)

    Kumar, Dayanand; Aluguri, Rakesh; Chand, Umesh; Tseng, Tseung-Yuen

    2018-04-01

    Ta5Si3-based conductive bridge random access memory (CBRAM) devices have been investigated to improve their resistive switching characteristics for their application in future nonvolatile memory technology. Changes in the switching characteristics by the addition of a thin Al2O3 layer of different thicknesses at the bottom electrode interface of a Ta5Si3-based CBRAM devices have been studied. The double-layer device with a 1 nm Al2O3 layer has shown improved resistive switching characteristics over the single layer one with a high on/off resistance ratio of 102, high endurance of more than 104 cycles, and good retention for more than 105 s at the temperature of 130 °C. The higher thermal conductivity of Al2O3 over Ta5Si3 has been attributed to the enhanced switching properties of the double-layer devices.

  17. 78 FR 53159 - Certain Semiconductor Chips With Dram Circuitry, and Modules and Products Containing Same: Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-08-28

    ... instituted this investigation on December 21, 2011, based on a complaint filed by Elpida Memory, Inc., of Tokyo, Japan, and Elpida Memory (USA) Inc. of Sunnyvale, California (collectively, ``Elpida''). 76 FR...

  18. Autobiographical memory specificity in dissociative identity disorder.

    PubMed

    Huntjens, Rafaële J C; Wessel, Ineke; Hermans, Dirk; van Minnen, Agnes

    2014-05-01

    A lack of adequate access to autobiographical knowledge has been related to psychopathology. More specifically, patients suffering from depression or a history of trauma have been found to be characterized by overgeneral memory, in other words, they show a relative difficulty in retrieving a specific event from memory located in time and place. Previous studies of overgeneral memory have not included patients with dissociative disorders. These patients are interesting to consider, as they are hypothesized to have the ability to selectively compartmentalize information linked to negative emotions. This study examined avoidance and overgeneral memory in patients with dissociative identity disorder (DID; n = 12). The patients completed the autobiographical memory test (AMT). Their performance was compared with control groups of posttraumatic stress disorder (PTSD) patients (n = 26), healthy controls (n = 29), and DID simulators (n = 26). Specifically, we compared the performance of separate identity states in DID hypothesized to diverge in the use of avoidance as a coping strategy to deal with negative affect. No significant differences in memory specificity were found between the separate identities in DID. Irrespective of identity state, DID patients were characterized by a lack of memory specificity, which was similar to the lack of memory specificity found in PTSD patients. The converging results for DID and PTSD patients add empirical evidence for the role of overgeneral memory involved in the maintenance of posttraumatic psychopathology.

  19. Figuring fact from fiction: unbiased polling of memory T cells.

    PubMed

    Gerlach, Carmen; Loughhead, Scott M; von Andrian, Ulrich H

    2015-05-07

    Immunization generates several memory T cell subsets that differ in their migratory properties, anatomic distribution, and, hence, accessibility to investigation. In this issue, Steinert et al. demonstrate that what was believed to be a minor memory cell subset in peripheral tissues has been dramatically underestimated. Thus, current models of protective immunity require revision. Copyright © 2015 Elsevier Inc. All rights reserved.

  20. Genome accessibility is widely preserved and locally modulated during mitosis.

    PubMed

    Hsiung, Chris C-S; Morrissey, Christapher S; Udugama, Maheshi; Frank, Christopher L; Keller, Cheryl A; Baek, Songjoon; Giardine, Belinda; Crawford, Gregory E; Sung, Myong-Hee; Hardison, Ross C; Blobel, Gerd A

    2015-02-01

    Mitosis entails global alterations to chromosome structure and nuclear architecture, concomitant with transient silencing of transcription. How cells transmit transcriptional states through mitosis remains incompletely understood. While many nuclear factors dissociate from mitotic chromosomes, the observation that certain nuclear factors and chromatin features remain associated with individual loci during mitosis originated the hypothesis that such mitotically retained molecular signatures could provide transcriptional memory through mitosis. To understand the role of chromatin structure in mitotic memory, we performed the first genome-wide comparison of DNase I sensitivity of chromatin in mitosis and interphase, using a murine erythroblast model. Despite chromosome condensation during mitosis visible by microscopy, the landscape of chromatin accessibility at the macromolecular level is largely unaltered. However, mitotic chromatin accessibility is locally dynamic, with individual loci maintaining none, some, or all of their interphase accessibility. Mitotic reduction in accessibility occurs primarily within narrow, highly DNase hypersensitive sites that frequently coincide with transcription factor binding sites, whereas broader domains of moderate accessibility tend to be more stable. In mitosis, proximal promoters generally maintain their accessibility more strongly, whereas distal regulatory elements tend to lose accessibility. Large domains of DNA hypomethylation mark a subset of promoters that retain accessibility during mitosis and across many cell types in interphase. Erythroid transcription factor GATA1 exerts site-specific changes in interphase accessibility that are most pronounced at distal regulatory elements, but has little influence on mitotic accessibility. We conclude that features of open chromatin are remarkably stable through mitosis, but are modulated at the level of individual genes and regulatory elements. © 2015 Hsiung et al.; Published by

  1. Information and processes underlying semantic and episodic memory across tasks, items, and individuals.

    PubMed

    Cox, Gregory E; Hemmer, Pernille; Aue, William R; Criss, Amy H

    2018-04-01

    The development of memory theory has been constrained by a focus on isolated tasks rather than the processes and information that are common to situations in which memory is engaged. We present results from a study in which 453 participants took part in five different memory tasks: single-item recognition, associative recognition, cued recall, free recall, and lexical decision. Using hierarchical Bayesian techniques, we jointly analyzed the correlations between tasks within individuals-reflecting the degree to which tasks rely on shared cognitive processes-and within items-reflecting the degree to which tasks rely on the same information conveyed by the item. Among other things, we find that (a) the processes involved in lexical access and episodic memory are largely separate and rely on different kinds of information, (b) access to lexical memory is driven primarily by perceptual aspects of a word, (c) all episodic memory tasks rely to an extent on a set of shared processes which make use of semantic features to encode both single words and associations between words, and (d) recall involves additional processes likely related to contextual cuing and response production. These results provide a large-scale picture of memory across different tasks which can serve to drive the development of comprehensive theories of memory. (PsycINFO Database Record (c) 2018 APA, all rights reserved).

  2. 76 FR 72214 - Certain Semiconductor Chips with DRAM Circuitry, and Modules and Products Containing Same Receipt...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-11-22

    ...://edis.usitc.gov . Hearing-impaired persons are advised that information on this matter can be obtained... Commission has received a complaint filed on behalf of Elpida Memory, Inc. and Elpida Memory (USA) Inc. on...

  3. Media multitasking and memory: Differences in working memory and long-term memory.

    PubMed

    Uncapher, Melina R; K Thieu, Monica; Wagner, Anthony D

    2016-04-01

    Increasing access to media in the 21st century has led to a rapid rise in the prevalence of media multitasking (simultaneous use of multiple media streams). Such behavior is associated with various cognitive differences, such as difficulty filtering distracting information and increased trait impulsivity. Given the rise in media multitasking by children, adolescents, and adults, a full understanding of the cognitive profile of media multitaskers is imperative. Here we investigated the relationship between chronic media multitasking and working memory (WM) and long-term memory (LTM) performance. Four key findings are reported (1) heavy media multitaskers (HMMs) exhibited lower WM performance, regardless of whether external distraction was present or absent; (2) lower performance on multiple WM tasks predicted lower LTM performance; (3) media multitasking-related differences in memory reflected differences in discriminability rather than decision bias; and (4) attentional impulsivity correlated with media multitasking behavior and reduced WM performance. These findings suggest that chronic media multitasking is associated with a wider attentional scope/higher attentional impulsivity, which may allow goal-irrelevant information to compete with goal-relevant information. As a consequence, heavy media multitaskers are able to hold fewer or less precise goal-relevant representations in WM. HMMs' wider attentional scope, combined with their diminished WM performance, propagates forward to yield lower LTM performance. As such, chronic media multitasking is associated with a reduced ability to draw on the past--be it very recent or more remote--to inform present behavior.

  4. Media multitasking and memory: Differences in working memory and long-term memory

    PubMed Central

    Thieu, Monica K.; Wagner, Anthony D.

    2015-01-01

    Increasing access to media in the 21st century has led to a rapid rise in the prevalence of media multitasking (simultaneous use of multiple media streams). Such behavior is associated with various cognitive differences, such as difficulty filtering distracting information and increased trait impulsivity. Given the rise in media multitasking by children, adolescents, and adults, a full understanding of the cognitive profile of media multitaskers is imperative. Here we investigated the relationship between chronic media multitasking and working memory (WM) and long-term memory (LTM) performance. Four key findings are reported (1) heavy media multitaskers (HMMs) exhibited lower WM performance, regardless of whether external distraction was present or absent; (2) lower performance on multiple WM tasks predicted lower LTM performance; (3) media multitasking-related differences in memory reflected differences in discriminability rather than decision bias; and (4) attentional impulsivity correlated with media multitasking behavior and reduced WM performance. These findings suggest that chronic media multitasking is associated with a wider attentional scope/higher attentional impulsivity, which may allow goal-irrelevant information to compete with goal-relevant information. As a consequence, heavy media multitaskers are able to hold fewer or less precise goal-relevant representations in WM. HMMs’ wider attentional scope, combined with their diminished WM performance, propagates forward to yield lower LTM performance. As such, chronic media multitasking is associated with a reduced ability to draw on the past—be it very recent or more remote—to inform present behavior. PMID:26223469

  5. Respecting Relations: Memory Access and Antecedent Retrieval in Incremental Sentence Processing

    ERIC Educational Resources Information Center

    Kush, Dave W.

    2013-01-01

    This dissertation uses the processing of anaphoric relations to probe how linguistic information is encoded in and retrieved from memory during real-time sentence comprehension. More specifically, the dissertation attempts to resolve a tension between the demands of a linguistic processor implemented in a general-purpose cognitive architecture and…

  6. Insights from child development on the relationship between episodic and semantic memory.

    PubMed

    Robertson, Erin K; Köhler, Stefan

    2007-11-05

    The present study was motivated by a recent controversy in the neuropsychological literature on semantic dementia as to whether episodic encoding requires semantic processing or whether it can proceed solely based on perceptual processing. We addressed this issue by examining the effect of age-related limitations in semantic competency on episodic memory in 4-6-year-old children (n=67). We administered three different forced-choice recognition memory tests for pictures previously encountered in a single study episode. The tests varied in the degree to which access to semantically encoded information was required at retrieval. Semantic competency predicted recognition performance regardless of whether access to semantic information was required. A direct relation between picture naming at encoding and subsequent recognition was also found for all tests. Our findings emphasize the importance of semantic encoding processes even in retrieval situations that purportedly do not require access to semantic information. They also highlight the importance of testing neuropsychological models of memory in different populations, healthy and brain damaged, at both ends of the developmental continuum.

  7. A Role for Memory in Prospective Timing informs Timing in Prospective Memory

    PubMed Central

    Waldum, Emily R; Sahakyan, Lili

    2014-01-01

    Time-based prospective memory (TBPM) tasks require the estimation of time in passing – known as prospective timing. Prospective timing is said to depend on an attentionally-driven internal clock mechanism, and is thought to be unaffected by memory for interval information (for reviews see, Block, Hancock, & Zakay, 2010; Block & Zakay, 1997). A prospective timing task that required a verbal estimate following the entire interval (Experiment 1) and a TBPM task that required production of a target response during the interval (Experiment 2) were used to test an alternative view that episodic memory does influence prospective timing. In both experiments, participants performed an ongoing lexical decision task of fixed duration while a varying number of songs were played in the background. Experiment 1 results revealed that verbal time estimates became longer the more songs participants remembered from the interval, suggesting that memory for interval information influences prospective time estimates. In Experiment 2, participants who were asked to perform the TBPM task without the aid of an external clock made their target responses earlier as the number of songs increased, indicating that prospective estimates of elapsed time increased as more songs were experienced. For participants who had access to a clock, changes in clock-checking coincided with the occurrence of song boundaries, indicating that participants used both song information and clock information to estimate time. Finally, ongoing task performance and verbal reports in both experiments further substantiate a role for episodic memory in prospective timing. PMID:22984950

  8. Multi-Level Bitmap Indexes for Flash Memory Storage

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Wu, Kesheng; Madduri, Kamesh; Canon, Shane

    2010-07-23

    Due to their low access latency, high read speed, and power-efficient operation, flash memory storage devices are rapidly emerging as an attractive alternative to traditional magnetic storage devices. However, tests show that the most efficient indexing methods are not able to take advantage of the flash memory storage devices. In this paper, we present a set of multi-level bitmap indexes that can effectively take advantage of flash storage devices. These indexing methods use coarsely binned indexes to answer queries approximately, and then use finely binned indexes to refine the answers. Our new methods read significantly lower volumes of data atmore » the expense of an increased disk access count, thus taking full advantage of the improved read speed and low access latency of flash devices. To demonstrate the advantage of these new indexes, we measure their performance on a number of storage systems using a standard data warehousing benchmark called the Set Query Benchmark. We observe that multi-level strategies on flash drives are up to 3 times faster than traditional indexing strategies on magnetic disk drives.« less

  9. DOE Office of Scientific and Technical Information (OSTI.GOV)

    Chang, Choong Koo; Park, Hyo Jeong; Kim, In Chool

    Reserve margins of Korea Electric Power Corporation (KEPCO) was 12% in 1993, however it was reduced to less than 3% in the summer of 1994 due to increase of electric power consumption caused by life style change based on economic growth. Therefore stable supply of electric power to industrial plant was threatened during last summer`s peak. The process of semiconductor manufacturing is very precious and full processing time reaches several months. Furthermore interruption of power supply to the process causes abortion of every product in the process. Therefore, power failure of less than one (1) second, may result in enormousmore » loss of capital. In order to protect disaster caused by power shortage during summer peaks. Samsung Electronics Co., Ltd (SEC) planned to construct LNG combined cycle power plant for the Klheung semiconductor plant which is the world`s leading maker of dynamic random access memory (DRAM) chips.« less

  10. Energetics of intrinsic defects in NiO and the consequences for its resistive random access memory performance

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Dawson, J. A., E-mail: jad95@cam.ac.uk; Guo, Y.; Robertson, J.

    2015-09-21

    Energetics for a variety of intrinsic defects in NiO are calculated using state-of-the-art ab initio hybrid density functional theory calculations. At the O-rich limit, Ni vacancies are the lowest cost defect for all Fermi energies within the gap, in agreement with the well-known p-type behaviour of NiO. However, the ability of the metal electrode in a resistive random access memory metal-oxide-metal setup to shift the oxygen chemical potential towards the O-poor limit results in unusual NiO behaviour and O vacancies dominating at lower Fermi energy levels. Calculated band diagrams show that O vacancies in NiO are positively charged at themore » operating Fermi energy giving it the advantage of not requiring a scavenger metal layer to maximise drift. Ni and O interstitials are generally found to be higher in energy than the respective vacancies suggesting that significant recombination of O vacancies and interstitials does not take place as proposed in some models of switching behaviour.« less

  11. Analysis of the Bipolar Resistive Switching Behavior of a Biocompatible Glucose Film for Resistive Random Access Memory.

    PubMed

    Park, Sung Pyo; Tak, Young Jun; Kim, Hee Jun; Lee, Jin Hyeok; Yoo, Hyukjoon; Kim, Hyun Jae

    2018-06-01

    Resistive random access memory (RRAM) devices are fabricated through a simple solution process using glucose, which is a natural biomaterial for the switching layer of RRAM. The fabricated glucose-based RRAM device shows nonvolatile bipolar resistive switching behavior, with a switching window of 10 3 . In addition, the endurance and data retention capability of glucose-based RRAM exhibit stable characteristics up to 100 consecutive cycles and 10 4 s under constant voltage stress at 0.3 V. The interface between the top electrode and the glucose film is carefully investigated to demonstrate the bipolar switching mechanism of the glucose-based RRAM device. The glucose based-RRAM is also evaluated on a polyimide film to verify the possibility of a flexible platform. Additionally, a cross-bar array structure with a magnesium electrode is prepared on various substrates to assess the degradability and biocompatibility for the implantable bioelectronic devices, which are harmless and nontoxic to the human body. It is expected that this research can provide meaningful insights for developing the future bioelectronic devices. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  12. A polymer/semiconductor write-once read-many-times memory

    NASA Astrophysics Data System (ADS)

    Möller, Sven; Perlov, Craig; Jackson, Warren; Taussig, Carl; Forrest, Stephen R.

    2003-11-01

    Organic devices promise to revolutionize the extent of, and access to, electronics by providing extremely inexpensive, lightweight and capable ubiquitous components that are printed onto plastic, glass or metal foils. One key component of an electronic circuit that has thus far received surprisingly little attention is an organic electronic memory. Here we report an architecture for a write-once read-many-times (WORM) memory, based on the hybrid integration of an electrochromic polymer with a thin-film silicon diode deposited onto a flexible metal foil substrate. WORM memories are desirable for ultralow-cost permanent storage of digital images, eliminating the need for slow, bulky and expensive mechanical drives used in conventional magnetic and optical memories. Our results indicate that the hybrid organic/inorganic memory device is a reliable means for achieving rapid, large-scale archival data storage. The WORM memory pixel exploits a mechanism of current-controlled, thermally activated un-doping of a two-component electrochromic conducting polymer.

  13. Activation and Binding in Verbal Working Memory: A Dual-Process Model for the Recognition of Nonwords

    ERIC Educational Resources Information Center

    Oberauer, Klauss; Lange, Elke B.

    2009-01-01

    The article presents a mathematical model of short-term recognition based on dual-process models and the three-component theory of working memory [Oberauer, K. (2002). Access to information in working memory: Exploring the focus of attention. "Journal of Experimental Psychology: Learning, Memory, and Cognition, 28", 411-421]. Familiarity arises…

  14. Fuzzy-trace theory: dual processes in memory, reasoning, and cognitive neuroscience.

    PubMed

    Brainerd, C J; Reyna, V F

    2001-01-01

    reasoning. More explicitly, in childhood reasoning tasks, it is assumed that both verbatim and gist traces of problem information are stored. Responding accurately to memory tests for presented problem information depends primarily on verbatim memory abilities (preserving traces of that information and accessing them when the appropriate memory probes are administered). However, accurate solutions to reasoning problems depend primarily on gist-memory abilities (extracting the correct gist from problem information, focusing on that gist during reasoning, and accessing reasoning operations that process that gist). Because verbatim and gist memories exhibit considerable dissociation, both during storage and when they are subsequently accessed on memory tests, dissociations of verbatim-based memory performance from gist-based reasoning are predictable. Conversely, associations are predicted in situations in which memory and reasoning are based on the same verbatim traces (Brainerd & Reyna, 1988) and in situations in which memory and reasoning are based on the same gist traces (Reyna & Kiernan, 1994). Fuzzy-trace theory's memory and reasoning principles have been applied in other research domains. Four such domains are developmental cognitive neuroscience studies of false memory, studies of false memory in brain-damaged patients, studies of reasoning errors in judgment and decision making, and studies of retrieval mechanisms in recall. In the first domain, the principles of parallel verbatim-gist storage, dissociated verbatim-gist retrieval, and identity/similarity processes have been used to explain both spontaneous and implanted false reports in children and in the elderly. These explanations have produced some surprising predictions that have been verified: false reports do not merely decline with age during childhood but increase under theoretically specified conditions; reports of events that were not experienced can nevertheless be highly persistent over time; and false

  15. Parameter optimization for transitions between memory states in small arrays of Josephson junctions

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Rezac, Jacob D.; Imam, Neena; Braiman, Yehuda

    Coupled arrays of Josephson junctions possess multiple stable zero voltage states. Such states can store information and consequently can be utilized for cryogenic memory applications. Basic memory operations can be implemented by sending a pulse to one of the junctions and studying transitions between the states. In order to be suitable for memory operations, such transitions between the states have to be fast and energy efficient. Here in this article we employed simulated annealing, a stochastic optimization algorithm, to study parameter optimization of array parameters which minimizes times and energies of transitions between specifically chosen states that can be utilizedmore » for memory operations (Read, Write, and Reset). Simulation results show that such transitions occur with access times on the order of 10–100 ps and access energies on the order of 10 -19–5×10 -18 J. Numerical simulations are validated with approximate analytical results.« less

  16. Using DMA for copying performance counter data to memory

    DOEpatents

    Gara, Alan; Salapura, Valentina; Wisniewski, Robert W.

    2012-09-25

    A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.

  17. Using DMA for copying performance counter data to memory

    DOEpatents

    Gara, Alan; Salapura, Valentina; Wisniewski, Robert W

    2013-12-31

    A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance data.

  18. Sub-1-V-60 nm vertical body channel MOSFET-based six-transistor static random access memory array with wide noise margin and excellent power delay product and its optimization with the cell ratio on static random access memory cell

    NASA Astrophysics Data System (ADS)

    Ogasawara, Ryosuke; Endoh, Tetsuo

    2018-04-01

    In this study, with the aim to achieve a wide noise margin and an excellent power delay product (PDP), a vertical body channel (BC)-MOSFET-based six-transistor (6T) static random access memory (SRAM) array is evaluated by changing the number of pillars in each part of a SRAM cell, that is, by changing the cell ratio in the SRAM cell. This 60 nm vertical BC-MOSFET-based 6T SRAM array realizes 0.84 V operation under the best PDP and up to 31% improvement of PDP compared with the 6T SRAM array based on a 90 nm planar MOSFET whose gate length and channel width are the same as those of the 60 nm vertical BC-MOSFET. Additionally, the vertical BC-MOSFET-based 6T SRAM array achieves an 8.8% wider read static noise margin (RSNM), a 16% wider write margin (WM), and an 89% smaller leakage. Moreover, it is shown that changing the cell ratio brings larger improvements of RSNM, WM, and write time in the vertical BC-MOSFET-based 6T SRAM array.

  19. Kinetic Inductance Memory Cell and Architecture for Superconducting Computers

    NASA Astrophysics Data System (ADS)

    Chen, George J.

    Josephson memory devices typically use a superconducting loop containing one or more Josephson junctions to store information. The magnetic inductance of the loop in conjunction with the Josephson junctions provides multiple states to store data. This thesis shows that replacing the magnetic inductor in a memory cell with a kinetic inductor can lead to a smaller cell size. However, magnetic control of the cells is lost. Thus, a current-injection based architecture for a memory array has been designed to work around this problem. The isolation between memory cells that magnetic control provides is provided through resistors in this new architecture. However, these resistors allow leakage current to flow which ultimately limits the size of the array due to power considerations. A kinetic inductance memory array will be limited to 4K bits with a read access time of 320 ps for a 1 um linewidth technology. If a power decoder could be developed, the memory architecture could serve as the blueprint for a fast (<1 ns), large scale (>1 Mbit) superconducting memory array.

  20. Two Spatial Memories Are Not Better than One: Evidence of Exclusivity in Memory for Object Location

    ERIC Educational Resources Information Center

    Baguley, Thom; Lansdale, Mark W.; Lines, Lorna K.; Parkin, Jennifer K.

    2006-01-01

    This paper studies the dynamics of attempting to access two spatial memories simultaneously and its implications for the accuracy of recall. Experiment 1 demonstrates in a range of conditions that two cues pointing to different experiences of the same object location produce little or no higher recall than that observed with a single cue.…