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Sample records for circuit asic application

  1. Characteristics and development report for the SA3871 Intent Controller application specific integrated circuit (ASIC)

    SciTech Connect

    Simpson, R.L.; Meyer, B.T.

    1995-08-01

    This report describes the design and development activities that were involved in the SA3871 Intent Controller ASIC. The SA3871 is a digital gate array component developed for the MC4396 Trajectory Sensing Signal Generator for use in the B61-3/4/10 system as well as a possible future B61-MAST system.

  2. CAE (computer-aided engineering) tools' limitations case study: An SSI (small scale integrated) design to an ASIC (application specific integrated circuit)

    SciTech Connect

    Everts, J.

    1989-01-01

    Every computer-aided engineering (CAE) tool has its limitations and shortcomings. Knowing where the pitfalls lie and how to get around them is extremely valuable. This paper takes a look at the problems and limitations encountered using the Daisy Systems suite of digital design tools (on a Logician 386 and a PKK386 MegaLogician, running DNIX 5.02A) to redesign a 169 small scale integrated (SSI) component design into an application specific integrated circuit (ASIC) gate array. Deficiencies were found in the libraries, ACE, MDLS, DTA, MCFS, and the Hotline support. Some solutions and workarounds to these deficiencies are presented.

  3. ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

    NASA Technical Reports Server (NTRS)

    Vasile, Stefan; Lipson, Jerold

    2012-01-01

    The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

  4. Rad-Hard Structured ASIC Body of Knowledge

    NASA Technical Reports Server (NTRS)

    Heidecker, Jason

    2013-01-01

    Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

  5. Design for ASIC reliability for low-temperature applications

    NASA Technical Reports Server (NTRS)

    Chen, Yuan; Mojaradi, Mohammad; Westergard, Lynett; Billman, Curtis; Cozy, Scott; Burke, Gary; Kolawa, Elizabeth

    2005-01-01

    In this paper, we present a methodology to design for reliability for low temperature applications without requiring process improvement. The developed hot carrier aging lifetime projection model takes into account both the transistor substrate current profile and temperature profile to determine the minimum transistor size needed in order to meet reliability requirements. The methodology is applicable for automotive, military, and space applications, where there can be varying temperature ranges. A case study utilizing this methodology is given to design for reliability into a custom application-specific integrated circuit (ASIC) for a Mars exploration mission.

  6. Estimating Delays In ASIC's

    NASA Technical Reports Server (NTRS)

    Burke, Gary; Nesheiwat, Jeffrey; Su, Ling

    1994-01-01

    Verification is important aspect of process of designing application-specific integrated circuit (ASIC). Design must not only be functionally accurate, but must also maintain correct timing. IFA, Intelligent Front Annotation program, assists in verifying timing of ASIC early in design process. This program speeds design-and-verification cycle by estimating delays before layouts completed. Written in C language.

  7. Design and test of clock distribution circuits for the Macro Pixel ASIC

    NASA Astrophysics Data System (ADS)

    Gaioni, L.; De Canio, F.; Manghisoni, M.; Ratti, L.; Re, V.; Traversi, G.

    2016-07-01

    Clock distribution circuits account for a significant fraction of the power dissipation of the Macro Pixel ASIC (MPA), designed for the pixel layer readout of the so-called Pixel-Strip module in the innermost part of the CMS tracker at the High Luminosity LHC. A test chip including low power clock distribution circuits of the MPA has been designed in a 65 nm CMOS technology and thoroughly tested. This work summarizes the experimental results relevant to the prototype chip, focusing particularly on the power and speed performance and compares such results with those coming from circuit simulations.

  8. An Energy-Efficient ASIC for Wireless Body Sensor Networks in Medical Applications.

    PubMed

    Xiaoyu Zhang; Hanjun Jiang; Lingwei Zhang; Chun Zhang; Zhihua Wang; Xinkai Chen

    2010-02-01

    An energy-efficient application-specific integrated circuit (ASIC) featured with a work-on-demand protocol is designed for wireless body sensor networks (WBSNs) in medical applications. Dedicated for ultra-low-power wireless sensor nodes, the ASIC consists of a low-power microcontroller unit (MCU), a power-management unit (PMU), reconfigurable sensor interfaces, communication ports controlling a wireless transceiver, and an integrated passive radio-frequency (RF) receiver with energy harvesting ability. The MCU, together with the PMU, provides quite flexible communication and power-control modes for energy-efficient operations. The always-on passive RF receiver with an RF energy harvesting block offers the sensor nodes the capability of work-on-demand with zero standby power. Fabricated in standard 0.18-¿m complementary metal-oxide semiconductor technology, the ASIC occupies a die area of 2 mm × 2.5 mm. A wireless body sensor network sensor-node prototype using this ASIC only consumes < 10-nA current under the passive standby mode, and < 10 ¿A under the active standby mode, when supplied by a 3-V battery. PMID:23853305

  9. A Batteryless Sensor ASIC for Implantable Bio-Impedance Applications.

    PubMed

    Rodriguez, Saul; Ollmar, Stig; Waqar, Muhammad; Rusu, Ana

    2016-06-01

    The measurement of the biological tissue's electrical impedance is an active research field that has attracted a lot of attention during the last decades. Bio-impedances are closely related to a large variety of physiological conditions; therefore, they are useful for diagnosis and monitoring in many medical applications. Measuring living tissues, however, is a challenging task that poses countless technical and practical problems, in particular if the tissues need to be measured under the skin. This paper presents a bio-impedance sensor ASIC targeting a battery-free, miniature size, implantable device, which performs accurate 4-point complex impedance extraction in the frequency range from 2 kHz to 2 MHz. The ASIC is fabricated in 150 nm CMOS, has a size of 1.22 mm × 1.22 mm and consumes 165 μA from a 1.8 V power supply. The ASIC is embedded in a prototype which communicates with, and is powered by an external reader device through inductive coupling. The prototype is validated by measuring the impedances of different combinations of discrete components, measuring the electrochemical impedance of physiological solution, and performing ex vivo measurements on animal organs. The proposed ASIC is able to extract complex impedances with around 1 Ω resolution; therefore enabling accurate wireless tissue measurements. PMID:26372646

  10. ASIC design of a digital fuzzy system on chip for medical diagnostic applications.

    PubMed

    Roy Chowdhury, Shubhajit; Roy, Aniruddha; Saha, Hiranmay

    2011-04-01

    The paper presents the ASIC design of a digital fuzzy logic circuit for medical diagnostic applications. The system on chip under consideration uses fuzzifier, memory and defuzzifier for fuzzifying the patient data, storing the membership function values and defuzzifying the membership function values to get the output decision. The proposed circuit uses triangular trapezoidal membership functions for fuzzification patients' data. For minimizing the transistor count, the proposed circuit uses 3T XOR gates and 8T adders for its design. The entire work has been carried out using TSMC 0.35 µm CMOS process. Post layout TSPICE simulation of the whole circuit indicates a delay of 31.27 ns and the average power dissipation of the system on chip is 123.49 mW which indicates a less delay and less power dissipation than the comparable embedded systems reported earlier. PMID:20703567

  11. Test chips and ASIC qualification

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Blaes, B. R.; Lin, Y.-S.; Zamani, N.; Lieneweg, U.

    1991-01-01

    A test chip set being developed to aid in the qualification of spaceborne Application Specific Integrated Circuits (ASICs) is described. The chip set consists of a process monitor for process parameter verification, a fault chip for yield analysis, a reliability chip for ASIC failure rate analysis, and total ionizing dose and single event upset chips for radiation effect analysis. The test structures contained in these chips are discussed along with representative test results.

  12. Sidecar Asic at ESO

    NASA Astrophysics Data System (ADS)

    Dorn, Reinhold J.; Eschbaumer, Siegfried; Finger, Gert; Ives, Derek; Meyer, Manfred; Stegmeier, Joerg

    2010-07-01

    Teledyne Imaging Sensors (TIS) has developed a CMOS device known as the SIDECAR application-specific integrated circuit (ASIC). This single chip provides all the functionality of FPA drive electronics to operate visible and infrared imaging detectors with a fully digital interface. A Teledyne 2K ×2K silicon PIN diode array hybridized to a Hawaii-2RG multiplexer, the Hybrid Visible Silicon Imager (HyViSI) was read out with the ESO standard IR detector controller IRACE, which delivers detector limited performance. We have tested the H2RG HyViSI detector with the TIS SIDECAR ASIC in 32 channel readout mode at cryogenic temperatures. The SIDECAR has been evaluated down to 105 Kelvin operating temperature and performance results have been compared to those obtained with external electronics. Furthermore ESO has developed its own interface card to replace the JADE USB card provided by Teledyne. The ASIC controller is now being embedded in the ESO standard VLT hard and software environment. This paper provides an update on the recent development of the new ESO ASIC interface card. We find that the SIDECAR ASIC provides performance equal to external electronics.

  13. Predicting Lifetimes Of CMOS ASIC's From Test Data

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.; Zamani, Nasser; Zoutendyk, John A.

    1993-01-01

    Concise report discusses recent developments in use of semiempirical mathematical models to predict rates of failure and operating lifetimes of complementary metal oxide/semiconductor (CMOS) application-specific integrated circuits (ASIC's). Each model represents specific mechanism of failure. Once failure mechanisms and models relevant to given ASIC chosen, adjustable parameters in models fitted to life-test data acquired from representative integrated-circuit structures on test coupons fabricated along with ASIC's. Then design parameters of ASIC's incorporated into models, and models yield lifetimes.

  14. Development of a CdTe pixel detector with a window comparator ASIC for high energy X-ray applications

    NASA Astrophysics Data System (ADS)

    Hirono, T.; Toyokawa, H.; Furukawa, Y.; Honma, T.; Ikeda, H.; Kawase, M.; Koganezawa, T.; Ohata, T.; Sato, M.; Sato, G.; Takagaki, M.; Takahashi, T.; Watanabe, S.

    2011-09-01

    We have developed a photon-counting-type CdTe pixel detector (SP8-01). SP8-01 was designed as a prototype of a high-energy X-ray imaging detector for experiments using synchrotron radiation. SP8-01 has a CdTe sensor of 500 μm thickness, which has an absorption efficiency of almost 100% up to 50 keV and 45% even at 100 keV. A full-custom application specific integrated circuit (ASIC) was designed as a readout circuit of SP8-01, which is equipped with a window-type discriminator. The upper discriminator realizes a low-background measurement, because X-ray beams from the monochromator contain higher-order components beside the fundamental X-rays in general. ASIC chips were fabricated with a TSMC 0.25 μm CMOS process, and CdTe sensors were bump-bonded to the ASIC chips by a gold-stud bonding technique. Beam tests were performed at SPring-8. SP8-01 detected X-rays up to 120 keV. The capability of SP8-01 as an imaging detector for high-energy X-ray synchrotron radiation was evaluated with its performance characteristics.

  15. SODR Memory Control Buffer Control ASIC

    NASA Technical Reports Server (NTRS)

    Hodson, Robert F.

    1994-01-01

    The Spacecraft Optical Disk Recorder (SODR) is a state of the art mass storage system for future NASA missions requiring high transmission rates and a large capacity storage system. This report covers the design and development of an SODR memory buffer control applications specific integrated circuit (ASIC). The memory buffer control ASIC has two primary functions: (1) buffering data to prevent loss of data during disk access times, (2) converting data formats from a high performance parallel interface format to a small computer systems interface format. Ten 144 p in, 50 MHz CMOS ASIC's were designed, fabricated and tested to implement the memory buffer control function.

  16. ASIC For Complex Fixed-Point Arithmetic

    NASA Technical Reports Server (NTRS)

    Petilli, Stephen G.; Grimm, Michael J.; Olson, Erlend M.

    1995-01-01

    Application-specific integrated circuit (ASIC) performs 24-bit, fixed-point arithmetic operations on arrays of complex-valued input data. High-performance, wide-band arithmetic logic unit (ALU) designed for use in computing fast Fourier transforms (FFTs) and for performing ditigal filtering functions. Other applications include general computations involved in analysis of spectra and digital signal processing.

  17. An Energy efficient application specific integrated circuit for electrocardiogram feature detection and its potential for ambulatory cardiovascular disease detection.

    PubMed

    Jain, Sanjeev Kumar; Bhaumik, Basabi

    2016-03-01

    A novel algorithm based on forward search is developed for real-time electrocardiogram (ECG) signal processing and implemented in application specific integrated circuit (ASIC) for QRS complex related cardiovascular disease diagnosis. The authors have evaluated their algorithm using MIT-BIH database and achieve sensitivity of 99.86% and specificity of 99.93% for QRS complex peak detection. In this Letter, Physionet PTB diagnostic ECG database is used for QRS complex related disease detection. An ASIC for cardiovascular disease detection is fabricated using 130-nm CMOS high-speed process technology. The area of the ASIC is 0.5 mm(2). The power dissipation is 1.73 μW at the operating frequency of 1 kHz with a supply voltage of 0.6 V. The output from the ASIC is fed to their Android application that generates diagnostic report and can be sent to a cardiologist through email. Their ASIC result shows average failed detection rate of 0.16% for six leads data of 290 patients in PTB diagnostic ECG database. They also have implemented a low-leakage version of their ASIC. The ASIC dissipates only 45 pJ with a supply voltage of 0.9 V. Their proposed ASIC is most suitable for energy efficient telemetry cardiovascular disease detection system. PMID:27284458

  18. An Energy efficient application specific integrated circuit for electrocardiogram feature detection and its potential for ambulatory cardiovascular disease detection

    PubMed Central

    Bhaumik, Basabi

    2016-01-01

    A novel algorithm based on forward search is developed for real-time electrocardiogram (ECG) signal processing and implemented in application specific integrated circuit (ASIC) for QRS complex related cardiovascular disease diagnosis. The authors have evaluated their algorithm using MIT-BIH database and achieve sensitivity of 99.86% and specificity of 99.93% for QRS complex peak detection. In this Letter, Physionet PTB diagnostic ECG database is used for QRS complex related disease detection. An ASIC for cardiovascular disease detection is fabricated using 130-nm CMOS high-speed process technology. The area of the ASIC is 0.5 mm2. The power dissipation is 1.73 μW at the operating frequency of 1 kHz with a supply voltage of 0.6 V. The output from the ASIC is fed to their Android application that generates diagnostic report and can be sent to a cardiologist through email. Their ASIC result shows average failed detection rate of 0.16% for six leads data of 290 patients in PTB diagnostic ECG database. They also have implemented a low-leakage version of their ASIC. The ASIC dissipates only 45 pJ with a supply voltage of 0.9 V. Their proposed ASIC is most suitable for energy efficient telemetry cardiovascular disease detection system. PMID:27284458

  19. Command Interface ASIC - Analog Interface ASIC Chip Set

    NASA Technical Reports Server (NTRS)

    Ruiz, Baldes; Jaffe, Burton; Burke, Gary; Lung, Gerald; Pixler, Gregory; Plummer, Joe; Katanyoutanant,, Sunant; Whitaker, William

    2003-01-01

    A command interface application-specific integrated circuit (ASIC) and an analog interface ASIC have been developed as a chip set for remote actuation and monitoring of a collection of switches, which can be used to control generic loads, pyrotechnic devices, and valves in a high-radiation environment. The command interface ASIC (CIA) can be used alone or in combination with the analog interface ASIC (AIA). Designed primarily for incorporation into spacecraft control systems, they are also suitable for use in high-radiation terrestrial environments (e.g., in nuclear power plants and facilities that process radioactive materials). The primary role of the CIA within a spacecraft or other power system is to provide a reconfigurable means of regulating the power bus, actuating all valves, firing all pyrotechnic devices, and controlling the switching of power to all switchable loads. The CIA is a mixed-signal (analog and digital) ASIC that includes an embedded microcontroller with supporting fault-tolerant switch control and monitoring circuitry that is capable of connecting to a redundant set of interintegrated circuit (I(sup 2)C) buses. Commands and telemetry requests are communicated to the CIA. Adherence to the I(sup 2)C bus standard helps to reduce development costs by facilitating the use of previously developed, commercially available components. The AIA is a mixed-signal ASIC that includes the analog circuitry needed to connect the CIA to a custom higher powered version of the I(sup 2)C bus. The higher-powered version is designed to enable operation with bus cables longer than those contemplated in the I(sup 2)C standard. If there are multiple higher-power I(sup 2)C-like buses, then there must an AIA between the CIA and each such bus. The AIA includes two identical interface blocks: one for the side-A I(sup 2)C clock and data buses and the other for the side B buses. All the AIAs on each side are powered from a common power converter module (PCM). Sides A and B

  20. STiC — a mixed mode silicon photomultiplier readout ASIC for time-of-flight applications

    NASA Astrophysics Data System (ADS)

    Harion, T.; Briggl, K.; Chen, H.; Fischer, P.; Gil, A.; Kiworra, V.; Ritzert, M.; Schultz-Coulon, H.-C.; Shen, W.; Stankova, V.

    2014-02-01

    STiC is an application specific integrated circuit (ASIC) for the readout of silicon photomultipliers. The chip has been designed to provide a very high timing resolution for time-of-flight applications in medical imaging and particle physics. It is dedicated in particular to the EndoToFPET-US project, which is developing an endoscopic PET detector combined with ultrasound imaging for early pancreas and prostate cancer detection. This PET system aims to provide a spatial resolution of 1 mm and a time-of-flight resolution of 200 ps FWHM. The analog frontend of STiC can use either a differential or single ended connection to the SiPM. The time and energy information of the detector signal is encoded into two time stamps. A special linearized time-over-threshold method is used to obtain a linear relation between the signal charge and the measured signal width, improving the energy resolution. The trigger signals are digitized by an integrated TDC module with a resolution of less than 20 ps. The TDC data is stored in an internal memory and transfered over a 160 MBit/s serial link using 8/10 bit encoding. First coincidence measurements using a 3.1 × 3.1 × 15 mm3 LYSO crystal and a S10362-33-50 Hamamtsu MPPC show a coincidence time resolution of less than 285 ps. We present details on the chip design as well as first characterization measurements.

  1. Multichannel readout ASIC design flow for high energy physics and cosmic rays experiments

    NASA Astrophysics Data System (ADS)

    Voronin, A.; Malankin, E.

    2016-02-01

    In the large-scale high energy physics and astrophysics experiments multi-channel readout application specific integrated circuits (ASICs) are widely used. The ASICs for such experiments are complicated systems, which usually include both analog and digital building blocks. The complexity and large number of channels in such ASICs require the proper methodological approach to their design. The paper represents the mixed-signal design flow of the ASICs for high energy physics and cosmic rays experiments. This flow was successfully embedded to the development of the read-out ASIC prototype for the muon chambers of the CBM experiment. The approach was approved in UMC CMOS MMRF 180 nm process. The design flow enable to analyse the mixed-signal system operation on the different levels: functional, behavioural, schematic and post layout including parasitic elements. The proposed design flow allows reducing the simulation period and eliminating the functionality mismatches on the very early stage of the design.

  2. ASIC Development for Three-Dimensional Silicon Imaging Array for Cold Neutrons

    SciTech Connect

    Britton, C.L.; Jagadish, U.; Bryan, W.L.

    2004-05-19

    An Integrated Circuit (IC) readout chip with four channels arranged so as to receive input charge from the corners of the chip was designed for use with 5- to 7-mm pixel detectors. This Application Specific IC (ASIC) can be used for cold neutron imaging, for study of structural order in materials using cold neutron scattering or for particle physics experiments. The ASIC is fabricated in a 0.5-{micro}m n-well AMI process. The design of the ASIC and the test measurements made is reported. Noise measurements are also reported.

  3. Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

    NASA Technical Reports Server (NTRS)

    Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

    2015-01-01

    Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

  4. Thermal Radiometer Signal Processing using Radiation Hard CMOS Application Specific Integrated Circuits for use in Harsh Planetary Environments

    NASA Astrophysics Data System (ADS)

    Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

    2015-10-01

    Thermal radiometers such as proposed for the Europa Clipper flyby mission [1] require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-cm2/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

  5. A 2D 4×4 Channel Readout ASIC for Pixelated CdTe Detectors for Medical Imaging Applications

    PubMed Central

    Macias-Montero, Jose-Gabriel; Sarraj, Maher; Chmeissani, Mokhtar; Martínez, Ricardo; Puigdengoles, Carles

    2015-01-01

    We present a 16-channel readout integrated circuit (ROIC) with nanosecond-resolution time to digital converter (TDC) for pixelated Cadmium Telluride (CdTe) gamma-ray detectors. The 4 × 4 pixel array ROIC is the proof of concept of the 10 × 10 pixel array readout ASIC for positron-emission tomography (PET) scanner, positron-emission mammography (PEM) scanner, and Compton gamma camera. The electronics of each individual pixel integrates an analog front-end with switchable gain, an analog to digital converter (ADC), configuration registers, and a 4-state digital controller. For every detected photon, the pixel electronics provides the energy deposited in the detector with 10-bit resolution, and a fast trigger signal for time stamp. The ASIC contains the 16-pixel matrix electronics, a digital controller, five global voltage references, a TDC, a temperature sensor, and a band-gap based current reference. The ASIC has been fabricated with TSMC 0.25 μm mixed-signal CMOS technology and occupies an area of 5.3 mm × 6.8 mm. The TDC shows a resolution of 95.5 ps, a precision of 600 ps at full width half maximum (FWHM), and a power consumption of 130 μW. In acquisition mode, the total power consumption of every pixel is 200 μW. An equivalent noise charge (ENC) of 160 e−RMS at maximum gain and negative polarity conditions has been measured at room temperature. PMID:26744545

  6. Monolithical integration of polymer-based microfluidic structures on application-specific integrated circuits

    NASA Astrophysics Data System (ADS)

    Chemnitz, Steffen; Schafer, Heiko; Schumacher, Stephanie; Koziy, Volodymyr; Fischer, Alexander; Meixner, Alfred J.; Ehrhardt, Dietmar; Bohm, Markus

    2003-04-01

    In this paper, a concept for a monolithically integrated chemical lab on microchip is presented. It contains an ASIC (Application Specific Integrated Circuit), an interface to the polymer based microfluidic layer and a Pyrex glass cap. The top metal layer of the ASIC is etched off and replaced by a double layer metallization, more suitable to microfluidic and electrophoresis systems. The metallization consists of an approximately 50 nm gold layer and a 10 nm chromium layer, acting as adhesion promoter. A necessary prerequisite is a planarized ASIC topography. SU-8 is used to serve as microfluidic structure because of its excellent aspect ratio. This polymer layer contains reservoirs, channels, mixers and electrokinetic micro pumps. The typical channel cross section is 10μm"10μm. First experimental results on a microfluidic pump, consisting of pairs of interdigitated electrodes on the bottom of the channel and without any moving parts show a flow of up to 50μm per second for low AC-voltages in the range of 5 V for aqueous fluids. The microfluidic system is irreversibly sealed with a 150μm thick Pyrex glass plate bonded to the SU-8-layer, supported by oxygen plasma. Due to capillary forces and surfaces properties of the walls the system is self-priming. The technologies for the fabrication of the microfluidic system and the preparation of the interface between the lab layer and the ASIC are presented.

  7. In application specific integrated circuit and data acquisition system for digital X-ray imaging

    NASA Astrophysics Data System (ADS)

    Beuville, E.; Cederström, B.; Danielsson, M.; Luo, L.; Nygren, D.; Oltman, E.; Vestlund, J.

    1998-02-01

    We have developed an Application Specific Integrated Circuit (ASIC) and data acquisition system for digital X-ray imaging. The chip consists of 16 parallel channels, each containing preamplifier, shaper, comparator and a 16 bit counter. We have demonstrated noiseless single-photon counting over a threshold of 7.2 keV using Silicon detectors and are presently capable of maximum counting rates of 2 MHz per channel. The ASIC is controlled by a personal computer through a commercial PCI card, which is also used for data acquisition. The content of the 16 bit counters are loaded into a shift register and transferred to the PC at any time at a rate of 20 MHz. The system is non-complicated, low cost and high performance and is optimised for digital X-ray imaging applications.

  8. ASIC-enabled High Resolution Optical Time Domain Reflectometer

    NASA Astrophysics Data System (ADS)

    Skendzic, Sandra

    Fiber optics has become the preferred technology in communication systems because of what it has to offer: high data transmission rates, immunity to electromagnetic interference, and lightweight, flexible cables. An optical time domain reflectometer (OTDR) provides a convenient method of locating and diagnosing faults (e.g. break in a fiber) along a fiber that can obstruct crucial optical pathways. Both the ability to resolve the precise location of the fault and distinguish between two discrete, closely spaced faults are figures of merit. This thesis presents an implementation of a high resolution OTDR through the use of a compact and programmable ASIC (application specific integrated circuit). The integration of many essential OTDR functions on a single chip is advantageous over existing commercial instruments because it enables small, lightweight packaging, and offers low power and cost efficiency. Furthermore, its compactness presents the option of placing multiple ASICs in parallel, which can conceivably ease the characterization of densely populated fiber optic networks. The OTDR ASIC consists of a tunable clock, pattern generator, precise timer, electrical receiver, and signal sampling circuit. During OTDR operation, the chip generates narrow electrical pulse, which can then be converted to optical format when coupled with an external laser diode driver. The ASIC also works with an external photodetector to measure the timing and amplitude of optical reflections in a fiber. It has a 1 cm sampling resolution, which allows for a 2 cm spatial resolution. While this OTDR ASIC has been previously demonstrated for multimode fiber fault diagnostics, this thesis focuses on extending its functionality to single mode fiber. To validate this novel approach to OTDR, this thesis is divided into five chapters: (1) introduction, (2) implementation, (3), performance of ASIC-based OTDR, (4) exploration in optical pre-amplification with a semiconductor optical amplifier, and

  9. Performance of VATA64HDR16 ASIC for medical physics applications based on continuous crystals and SiPMs

    NASA Astrophysics Data System (ADS)

    Barrio, J.; Etxebeste, A.; Lacasta, C.; Muñoz, E.; Oliver, J. F.; Solaz, C.; Llosá, G.

    2015-12-01

    Detectors based on Silicon Photomultipliers (SiPMs) coupled to continuous crystals are being tested in medical physics applications due to their potential high resolution and sensitivity. To cope with the high granularity required for a very good spatial resolution, SiPM matrices with a large amount of elements are needed. To be able to read the information coming from each individual channel, dedicated ASICs are employed. The VATA64HDR16 ASIC is a 64-channel, charge-sensitive amplifier that converts the collected charge into a proportional current or voltage signal. A complete assessment of the suitability of that ASIC for medical physics applications based on continuous crystals and SiPMs has been carried out. The input charge range is linear from 0-2 pC up to 55 pC. The energy resolution obtained at 511 keV is 10% FWHM with a LaBr3 crystal and 16% FWHM with a LYSO crystal. A coincidence timing resolution of 24 ns FWHM is obtained with two LYSO crystals.

  10. An application specific integrated circuit based multi-anode microchannel array readout system

    NASA Technical Reports Server (NTRS)

    Smeins, Larry G.; Stechman, John M.; Cole, Edward H.

    1991-01-01

    Size reduction of two new multi-anode microchannel array (MAMA) readout systems is described. The systems are based on two analog and one digital application specific integrated circuits (ASICs). The new readout systems reduce volume over previous discrete designs by 80 percent while improving electrical performance on virtually every significant parameter. Emphasis is made on the packaging used to achieve the volume reduction. Surface mount technology (SMT) is combined with modular construction for the analog portion of the readout. SMT reliability concerns and the board area impact of MIL SPEC SMT components is addressed. Package selection for the analog ASIC is discussed. Future sytems will require even denser packaging and the volume reduction progression is shown.

  11. ASIC for SDD-Based X-Ray Spectrometers

    SciTech Connect

    G De Geronimo; P Rehak; K Ackley; G Carini; W Chen; J Fried; J Keister; S Li; Z Li; et al.

    2011-12-31

    We present an application-specific integrated circuit (ASIC) for high-resolution x-ray spectrometers (XRS). The ASIC reads out signals from pixelated silicon drift detectors (SDDs). The pixel does not have an integrated field effect transistor (FET); rather, readout is accomplished by wire-bonding the anodes to the inputs of the ASIC. The ASIC dissipates 32 mW, and offers 16 channels of low-noise charge amplification, high-order shaping with baseline stabilization, discrimination, a novel pile-up rejector, and peak detection with an analog memory. The readout is sparse and based on custom low-power tristatable low-voltage differential signaling (LPT-LVDS). A unit of 64 SDD pixels, read out by four ASICs, covers an area of 12.8 cm{sup 2} and dissipates with the sensor biased about 15 mW/cm{sup 2}. As a tile-based system, the 64-pixel units cover a large detection area. Our preliminary measurements at -44 C show a FWHM of 145 eV at the 5.9 keV peak of a {sup 55}Fe source, and less than 80 eV on a test-pulse line at 200 eV.

  12. ASIC for SDD-Based X-ray Spectrometers

    SciTech Connect

    De Geronimo, G.; Fried, J.; Rehak, P.; Ackley, K.; Carini, G.; Chen, W.; Keister, J.; Li, S.; Li, Z.; Pinelli, D.A.; Siddons, D.P.; Vernon, E.; Gaskin, J.A.; Ramsey, B.D.; Tyson, T.A.

    2010-06-16

    We present an application-specific integrated circuit (ASIC) for high-resolution x-ray spectrometers (XRS). The ASIC reads out signals from pixelated silicon drift detectors (SDDs). The pixel does not have an integrated field effect transistor (FET); rather, readout is accomplished by wire-bonding the anodes to the inputs of the ASIC. The ASIC dissipates 32 mW, and offers 16 channels of low-noise charge amplification, high-order shaping with baseline stabilization, discrimination, a novel pile-up rejector, and peak detection with an analog memory. The readout is sparse and based on custom low-power tristatable low-voltage differential signaling (LPT-LVDS). A unit of 64 SDD pixels, read out by four ASICs, covers an area of 12.8 cm{sup 2} and dissipates with the sensor biased about 15 mW/cm{sup 2}. As a tile-based system, the 64-pixel units cover a large detection area. Our preliminary measurements at -44 C show a FWHM of 145 eV at the 5.9 keV peak of a {sup 55}Fe source, and less than 80 eV on a test-pulse line at 200 eV.

  13. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    NASA Technical Reports Server (NTRS)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  14. Low-cost photovoltaic inverters incorporating application-specific integrated circuits

    SciTech Connect

    O`Sullivan, G.A.; O`Sullivan, J.A.

    1993-10-01

    The positive impact of designing a power conditioner control system for photovoltaic applications with an application-specific integrated circuit (ASIC) as the main control element was demonstrated with detailed computer simulations in Phase I of a two phase Small Business Innovative Research Grant issued by the US Department of Energy. Completion of the design, building and testing of three prototypes using different power semiconductors was successfully accomplished in Phase II. The power rating for the residential utility intertied Sunverters Model 753-4-200 is 5 kW. A stand-alone inverter suitable for operation from a photovoltaic array with or without a battery for energy storage was also developed in this effort. A much needed intermediate power level 50-kW three-phase power conditioner, Sunverter Model 759-4-200, was the third product to evolve from the research and development. All designs take advantage of the ASIC and a complementary microprocessor sampled-data control system. The ASIC-controlled power conditioners provide the high reliability, high efficiency, and low cost needed for photovoltaic applications. They cover the power range from the residential level to utility-sized installations.

  15. TOFPET2: a high-performance ASIC for time and amplitude measurements of SiPM signals in time-of-flight applications

    NASA Astrophysics Data System (ADS)

    Di Francesco, A.; Bugalho, R.; Oliveira, L.; Pacher, L.; Rivetti, A.; Rolo, M.; Silva, J. C.; Silva, R.; Varela, J.

    2016-03-01

    We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with 320 pF capacitance the circuit has 24 (30) dB SNR, 75(39) ps r.m.s. resolution, and 4(8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.

  16. The Pulse Width Modulator ASIC for Deep Space Missions

    NASA Technical Reports Server (NTRS)

    Carr, Gregory A.; Wester, Gene W.; Lam, Barbara; Bennett, Johnny; Franco, Lauro; Woo, Erika

    2004-01-01

    The Jet Propulsion Laboratory has started the development of a Pulse Width Modulator Application Specific Integrated Circuit (PWMA). This development is leveraging the previous development of the Switch Control ASIC (SCA). The purpose of the development is to provide the control for a selected range of power converter topologies and to meet the stringent environmental requirements of deep space missions. The PWMA will include several power control functions that are not normally included on the off-the-shelf components available today. One key functional requirement is the ability to implement an N + K redundant power converter with the ability to control the charging of a battery. Other applications will be the typical point of load isolated and non-isolated power converters. The purpose the development is not only to provide a much needed flight part, but also to accelerate the engineering process by using a standard cell library from previous ASIC developments. Under previous developments with Boeing and Lockheed Martin, JPL has produced three ASICs. Each ASIC has been implemented by using an analog standard cell library. One such development was the SCA, which is design to provide a floating power switch control. The functional verification of this ASIC has been completed and the cells used have been targeted for the new development of the PWMA. The primary function of the PWMA is to provide the control function of a point of load power converter. The design is an isolated 60 W converter with a 33 V output. In architecting the design, several functions were left up to the power converter design in order to make the ASIC more generic. The ASIC can be used for several power converter topologies and power levels. Some additional features have been added to the ASIC to provide the interfaces for multi-phase topologies and battery control functions. An N+K fault tolerant strategy has been implemented in order to provide the battery control functions. The PWMA has

  17. Digital circuits for computer applications: A compilation

    NASA Technical Reports Server (NTRS)

    1972-01-01

    The innovations in this updated series of compilations dealing with electronic technology represent a carefully selected collection of digital circuits which have direct application in computer oriented systems. In general, the circuits have been selected as representative items of each section and have been included on their merits of having universal applications in digital computers and digital data processing systems. As such, they should have wide appeal to the professional engineer and scientist who encounter the fundamentals of digital techniques in their daily activities. The circuits are grouped as digital logic circuits, analog to digital converters, and counters and shift registers.

  18. Using advanced microelectronic test chips to qualify ASIC's for space

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Blaes, B. R.; Lin, Y-S.

    1990-01-01

    Qualification procedures for complex integrated circuits are being developed under a U.S. government program known as Qualified Manufacturing Lines (QML). This effort is focused on circuits designed by IC manufacturers and has not addressed application specific IC's (ASIC's) designed at system houses. The qualification procedures described here are intended to be responsive to the needs of system houses who design their own ASIC's and have them fabricated at Silicon foundries. A particular focus of this presentation will be the use of the TID (total Ionizing Dose) Chip to evaluate CMOS foundry processes and to provide parameters for circuit simulators. This chip is under development as a standard chip for qualifying the total dose aspects of ASIC's. The benefits of standardization are that the results will be well understood and easy to interpret. Data is presented and compared for 1.6 micron and 3.0 micron CMOS. The data shows that 1.6 micron CMOS is significantly harder than 3.0 micron CMOS. Two failure modes are explored: (1) the radiation-induced degradation of timing delays; and (2) radiation-induced leakage currents.

  19. A miniaturized ASIC-based multichannel scaler instrument

    SciTech Connect

    Ericson, M.N.; Turner, G.W.; McMillan, D.E.; Hoffheins, B.S.; Todd, R.A.; Hiller, J.M.

    1993-12-31

    A miniaturized multichannel scaler instrument has been developed to address size and operational constraints for data acquisition in a portable laser-induced luminescence system. The multichannel scaling (MCS) function is implemented as a programmable application specific integrated circuit (ASIC) with standard interfaces for control and data acquisition. The instrument is microcontroller-based with sufficient computing power for data manipulation and algorithmic processing. The unit includes electronics for laser control, and amplification and pulse height discrimination of PMT pulses. Modification of the instrument should allow use in nuclear, chemical, and spectroscopy related applications including Mossbauer experiments. Interfaces are incorporated allowing both computer-controlled and stand alone operation. Implementation of the MCS function as an ASIC and comparison with conventional implementations are discussed. Full characterization of the MCS is presented including differential non-linearity (DNL), bin dead time, and bandwidth measurements.

  20. Small Microprocessor for ASIC or FPGA Implementation

    NASA Technical Reports Server (NTRS)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  1. Microwave integrated circuits for space applications

    NASA Technical Reports Server (NTRS)

    Leonard, Regis F.; Romanofsky, Robert R.

    1991-01-01

    Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.

  2. Automated radiation hard ASIC design tool

    NASA Technical Reports Server (NTRS)

    White, Mike; Bartholet, Bill; Baze, Mark

    1993-01-01

    A commercial based, foundry independent, compiler design tool (ChipCrafter) with custom radiation hardened library cells is described. A unique analysis approach allows low hardness risk for Application Specific IC's (ASIC's). Accomplishments, radiation test results, and applications are described.

  3. Dedicated multichannel readout ASIC coupled with single crystal diamond for dosimeter application

    NASA Astrophysics Data System (ADS)

    Fabbri, A.; Falco, M. D.; De Notaristefani, F.; Galasso, M.; Marinelli, M.; Orsolini Cencelli, V.; Tortora, L.; Verona, C.; Verona Rinati, G.

    2013-02-01

    This paper reports on the tests of a low-noise, multi-channel readout integrated circuit used as a readout electronic front-end for a diamond multi-pixel dosimeter. The system is developed for dose distribution measurement in radiotherapy applications. The first 10-channel prototype chip was designed and fabricated in a 0.18 um CMOS process. Every channel includes a charge integrator with a 10 pF capacitor and a double slope A/D converter. The diamond multi-pixel detector, based on CVD synthetic single crystal diamond Schottky diodes, is made by a 3 × 3 sensor matrix. The overall device has been tested under irradiation with 6 MeV radio therapeutic photon beams at the Policlinico ``Tor Vergata'' (PTV) hospital. Measurements show a 20 fA RMS leakage current from the front-end input stage and a negligible dark current from the diamond detector, a stable temporal response and a good linear behaviour as a function of both dose and dose rate. These characteristics were common to each tested channel.

  4. ASIC-based design of NMR system health monitor for mission/safety-critical applications.

    PubMed

    Balasubramanian, P

    2016-01-01

    N-modular redundancy (NMR) is a generic fault tolerance scheme that is widely used in safety-critical circuit/system designs to guarantee the correct operation with enhanced reliability. In passive NMR, at least a majority (N + 1)/2 out of N function modules is expected to operate correctly at any time, where N is odd. Apart from a conventional realization of the NMR system, it would be useful to provide a concurrent indication of the system's health so that an appropriate remedial action may be initiated depending upon an application's safety criticality. In this context, this article presents the novel design of a generic NMR system health monitor which features: (i) early fault warning logic, that is activated upon the production of a conflicting result by even one output of any arbitrary function module, and (ii) error signalling logic, which signals an error when the number of faulty function modules unfortunately attains a majority and the system outputs may no more be reliable. Two sample implementations of NMR systems viz. triple modular redundancy and quintuple modular redundancy with the proposed system health monitoring are presented in this work, with a 4-bit ALU used for the function modules. The simulations are performed using a 32/28 nm CMOS process technology. PMID:27330894

  5. A High-Performance Deformable Mirror with Integrated Driver ASIC for Space Based Active Optics

    NASA Astrophysics Data System (ADS)

    Shelton, Chris

    Direct imaging of exoplanets is key to fully understanding these systems through spectroscopy and astrometry. The primary impediment to direct imaging of exoplanets is the extremely high brightness ratio between the planet and its parent star. Direct imaging requires a technique for contrast suppression, which include coronagraphs, and nulling interferometers. Deformable mirrors (DMs) are essential to both of these techniques. With space missions in mind, Microscale is developing a novel DM with direct integration of DM and its electronic control functions in a single small envelope. The Application Specific Integrated Circuit (ASIC) is key to the shrinking of the electronic control functions to a size compatible with direct integration with the DM. Through a NASA SBIR project, Microscale, with JPL oversight, has successfully demonstrated a unique deformable mirror (DM) driver ASIC prototype based on an ultra-low power switch architecture. Microscale calls this the Switch-Mode ASIC, or SM-ASIC, and has characterized it for a key set of performance parameters, and has tested its operation with a variety of actuator loads, such as piezo stack and unimorph, and over a wide temperature range. These tests show the SM-ASIC's capability of supporting active optics in correcting aberrations of a telescope in space. Microscale has also developed DMs to go with the SM-ASIC driver. The latest DM version produced uses small piezo stack elements in an 8x8 array, bonded to a novel silicon facesheet structure fabricated monolithically into a polished mirror on one side and mechanical linkage posts that connect to the piezoelectric stack actuators on the other. In this Supporting Technology proposal we propose to further develop the ASIC-DM and have assembled a very capable team to do so. It will be led by JPL, which has considerable expertise with DMs used in Adaptive Optics systems, with high-contrast imaging systems for exoplanet missions, and with designing DM driver

  6. Front End Spectroscopy ASIC for Germanium Detectors

    NASA Astrophysics Data System (ADS)

    Wulf, Eric

    the anode and cathode of the device to allow the depth of the interaction within the crystal to be determined. Dr. De Geronimo has developed similar timing circuits for CZT detector ASICs. Furthermore, the timing circuitry of the ASIC is at the very end of the analog section, simplifying and mitigating risks in the redesign. In the first year, we propose to tweak the gain settings and to add timing to the silicon ASIC to match the requirements of a germanium detector. The design specifications of the ASIC will include advice from our collaborators Dr. Boggs from COSI and Dr. Shih from GRIPS. By using a master ASIC designer to integrate his proven front-end and back-end with only minor modifications, we are maximizing the probability of success. NRL has a commercial cross-strip germanium detector with 30 pF of capacitance per strip, including the flex circuit from the detector to the outside of the cryostat. The COSI and GRIPS detectors have a similar capacitance per strip on the outside of their mechanically cooled cryostat. The second year of the program will be devoted to testing the newly fabricated germanium cross-strip ASIC with the NRL germanium detector. At the end of the second year, NASA will have a TRL 5 ASIC for germanium detectors, allowing future missions, including COSI, GRX, and GRIPS, to operate within their thermal and electrical envelopes. At the end of the third year, a detector on COSI will be instrumented with the new ASIC allowing for a TRL 6 demonstration during the following COSI balloon flight.

  7. Synthesis algorithm of VLSI multipliers for ASIC

    NASA Technical Reports Server (NTRS)

    Chua, O. H.; Eldin, A. G.

    1993-01-01

    Multipliers are critical sub-blocks in ASIC design, especially for digital signal processing and communications applications. A flexible multiplier synthesis tool is developed which is capable of generating multiplier blocks for word size in the range of 4 to 256 bits. A comparison of existing multiplier algorithms is made in terms of speed, silicon area, and suitability for automated synthesis and verification of its VLSI implementation. The algorithm divides the range of supported word sizes into sub-ranges and provides each sub-range with a specific multiplier architecture for optimal speed and area. The algorithm of the synthesis tool and the multiplier architectures are presented. Circuit implementation and the automated synthesis methodology are discussed.

  8. ASICs Approach for the Implementation of a Symmetric Triangular Fuzzy Coprocessor and Its Application to Adaptive Filtering

    NASA Technical Reports Server (NTRS)

    Starks, Scott; Abdel-Hafeez, Saleh; Usevitch, Bryan

    1997-01-01

    This paper discusses the implementation of a fuzzy logic system using an ASICs design approach. The approach is based upon combining the inherent advantages of symmetric triangular membership functions and fuzzy singleton sets to obtain a novel structure for fuzzy logic system application development. The resulting structure utilizes a fuzzy static RAM to store the rule-base and the end-points of the triangular membership functions. This provides advantages over other approaches in which all sampled values of membership functions for all universes must be stored. The fuzzy coprocessor structure implements the fuzzification and defuzzification processes through a two-stage parallel pipeline architecture which is capable of executing complex fuzzy computations in less than 0.55us with an accuracy of more than 95%, thus making it suitable for a wide range of applications. Using the approach presented in this paper, a fuzzy logic rule-base can be directly downloaded via a host processor to an onchip rule-base memory with a size of 64 words. The fuzzy coprocessor's design supports up to 49 rules for seven fuzzy membership functions associated with each of the chip's two input variables. This feature allows designers to create fuzzy logic systems without the need for additional on-board memory. Finally, the paper reports on simulation studies that were conducted for several adaptive filter applications using the least mean squared adaptive algorithm for adjusting the knowledge rule-base.

  9. ASIC Readout System for use with a Silicon Detector Array (SAND)

    NASA Astrophysics Data System (ADS)

    Marsh, Ian; Lesher, Shelly; Tan, Wanpeng; Smith, Mallory; Robbe, Mike; Aprahamian, Ani

    2012-10-01

    Silicon (Si) detectors are widely used throughout the scientific community, particularly in nuclear physics. Modern versions of Si detectors are getting larger and increasingly segmented, requiring many electronic channels to process the signals. NIM and VME modules have traditionally been used to process signals from various types of detectors. Applying this traditional method to a large array of Si-detectors, segmented or otherwise, would be very expensive and in most cases highly impractical. To handle this high density of signals from state-of-the-art Si detector arrays we have explored an Application Specific Integrated Circuit (ASIC) approach in collaboration with University of Washington in St. Louis. This involves ASIC chips developed for simultaneous signal processing with charge sensitive preamplifiers, shaping amplifiers, and constant fraction discriminators built in for 16 channels. One ASIC box is capable of housing 32 of these chips and thus processing signals directly from detectors through a total of 512 channels. Analog energy and timing signals are digitized through a pipeline ADC for the NSCL DAQ software to readout. I was a part of the ND effort to implement such an ASIC system. I conducted energy and timing calibrations as well as linearity, threshold, and resolution tests on the system. In collaboration with Indiana University at Bloomington the ASIC system will be applied to a silicon detector array (SAND) at ND for the study of nuclear astrophysics.

  10. ASICs and neuropeptides.

    PubMed

    Vick, Jonathan S; Askwith, Candice C

    2015-07-01

    The acid sensing ion channels (ASICs) are proton-gated cation channels expressed throughout the nervous system. ASICs are activated during acidic pH fluctuations, and recent work suggests that they are involved in excitatory synaptic transmission. ASICs can also induce neuronal degeneration and death during pathological extracellular acidosis caused by ischemia, autoimmune inflammation, and traumatic injury. Many endogenous neuromodulators target ASICs to affect their biophysical characteristics and contributions to neuronal activity. One of the most unconventional types of modulation occurs with the interaction of ASICs and neuropeptides. Collectively, FMRFamide-related peptides and dynorphins potentiate ASIC activity by decreasing the proton-sensitivity of steady state desensitization independent of G protein-coupled receptor activation. By decreasing the proton-sensitivity of steady state desensitization, the FMRFamide-related peptides and dynorphins permit ASICs to remain active at more acidic basal pH. Unlike the dynorphins, some FMRFamide-related peptides also potentiate ASIC activity by slowing inactivation and increasing the sustained current. Through mechanistic studies, the modulation of ASICs by FMRFamide-related peptides and dynorphins appears to be through distinct interactions with the extracellular domain of ASICs. Dynorphins are expressed throughout the nervous system and can increase neuronal death during prolonged extracellular acidosis, suggesting that the interaction between dynorphins and ASICs may have important consequences for the prevention of neurological injury. The overlap in expression of FMRFamide-related peptides with ASICs in the dorsal horn of the spinal cord suggests that their interaction may have important consequences for the treatment of pain during injury and inflammation. This article is part of the Special Issue entitled 'Acid-Sensing Ion Channels in the Nervous System'. PMID:25592215

  11. ASICS AND NEUROPEPTIDES

    PubMed Central

    Vick, Jonathan S.; Askwith, Candice C.

    2015-01-01

    The acid sensing ion channels (ASICs) are proton-gated cation channels expressed throughout the nervous system. ASICs are activated during acidic pH fluctuations, and recent work suggests that they are involved in excitatory synaptic transmission. ASICs can also induce neuronal degeneration and death during pathological extracellular acidosis caused by ischemia, autoimmune inflammation, and traumatic injury. Many endogenous neuromodulators target ASICs to affect their biophysical characteristics and contributions to neuronal activity. One of the most unconventional types of modulation occurs with the interaction of ASICs and neuropeptides. Collectively, FMRFamide-related peptides and dynorphins potentiate ASIC activity by decreasing the proton-sensitivity of steady state desensitization independent of G protein-coupled receptor activation. By decreasing the proton-sensitivity of steady state desensitization, the FMRFamide-related peptides and dynorphins permit ASICs to remain active at more acidic basal pH. Unlike the dynorphins, some FMRFamide-related peptides also potentiate ASIC activity by slowing inactivation and increasing the sustained current. Through mechanistic studies, the modulation of ASICs by FMRFamide-related peptides and dynorphins appears to be through distinct interactions with the extracellular domain of ASICs. Dynorphins are expressed throughout the nervous system and can increase neuronal death during prolonged extracellular acidosis, suggesting that the interaction between dynorphins and ASICs may have important consequences for the prevention of neurological injury. The overlap in expression of FMRFamide-related peptides with ASICs in the dorsal horn of the spinal cord suggests that their interaction may have important consequences for the treatment of pain during injury and inflammation. PMID:25592215

  12. ASICs and cardiovascular homeostasis.

    PubMed

    Abboud, François M; Benson, Christopher J

    2015-07-01

    In this review we address primarily the role of ASICs in determining sensory signals from arterial baroreceptors, peripheral chemoreceptors, and cardiopulmonary and somatic afferents. Alterations in these sensory signals during acute cardiovascular stresses result in changes in sympathetic and parasympathetic activities that restore cardiovascular homeostasis. In pathological states, however, chronic dysfunctions of these afferents result in serious sympatho-vagal imbalances with significant increases in mortality and morbidity. We identified a role for ASIC2 in the mechano-sensitivity of aortic baroreceptors and of ASIC3 in the pH sensitivity of carotid bodies. In spontaneously hypertensive rats, we reported decreased expression of ASIC2 in nodose ganglia neurons and overexpression of ASIC3 in carotid bodies. This reciprocal expression of ASIC2 and ASIC3 results in reciprocal changes in sensory sensitivity of baro- and chemoreceptors and a consequential synergistic exaggeration sympathetic nerve activity. A similar reciprocal sensory dysautonomia prevails in heart failure and increases the risk of mortality. There is also evidence that ASIC heteromers in skeletal muscle afferents contribute significantly to the exercise pressor reflex. In cardiac muscle afferents of the dorsal root ganglia, they contribute to nociception and to the detrimental sympathetic activation during ischemia. Finally, we report that an inhibitory influence of ASIC2-mediated baroreceptor activity suppresses the sympatho-excitatory reflexes of the chemoreceptors and skeletal muscle afferents, as well as the ASIC1a-mediated excitation of central neurons during fear, threat, or panic. The translational potential of activation of ASIC2 in cardiovascular disease states may be a beneficial sympatho-inhibition and parasympathetic activation. This article is part of the Special Issue entitled 'Acid-Sensing Ion Channels in the Nervous System'. PMID:25592213

  13. ASIC for High Rate 3D Position Sensitive Detectors

    SciTech Connect

    Vernon, E.; De Geronimo, G.; Ackley, K.; Fried, J.; He, Z.; Herman, C.; Zhang, F.

    2010-06-16

    We report on the development of an application specific integrated circuit (ASIC) for 3D position sensitive detectors (3D PSD). The ASIC is designed to operate with pixelated wide bandgap sensors like Cadmium-Zinc-Telluride (CZT), Mercuric Iodide (Hgl2) and Thallium Bromide (TIBr). It measures the amplitudes and timings associated with an ionizing event on 128 anodes, the anode grid, and the cathode. Each channel provides low-noise charge amplification, high-order shaping with peaking time adjustable from 250 ns to 12 {micro}s, gain adjustable to 20 mV/fC or 120 mV/fC (for a dynamic range of 3.2 MeV and 530 keV in CZT), amplitude discrimination with 5-bit trimming, and positive and negative peak and timing detections. The readout can be full or sparse, based on a flag and single- or multi-cycle token passing. All channels, triggered channels only, or triggered with neighbors can be read out thus increasing the rate capability of the system to more than 10 kcps. The ASIC dissipates 330 mW which corresponds to about 2.5 mW per channel.

  14. ASIC Design and Data Communications for the Boston Retinal Prosthesis

    PubMed Central

    Shire, Douglas B.; Ellersick, William; Kelly, Shawn K.; Doyle, Patrick; Priplata, Attila; Drohan, William; Mendoza, Oscar; Gingerich, Marcus; McKee, Bruce; Wyatt, John L.; Rizzo, Joseph F.

    2016-01-01

    We report on the design and testing of a custom application-specific integrated circuit (ASIC) that has been developed as a key component of the Boston retinal prosthesis. This device has been designed for patients who are blind due to age-related macular degeneration or retinitis pigmentosa. Key safety and communication features of the low-power ASIC are described, as are the highly configurable neural stimulation current waveforms that are delivered to its greater than 256 output electrodes. The ASIC was created using an 0.18 micron Si fabrication process utilizing standard 1.8 volt CMOS transistors as well as 20 volt lightly doped drain FETs. The communication system receives frequency-shift keyed inputs at 6.78 MHz from an implanted secondary coil, and transmits data back to the control unit through a lower-bandwidth channel that employs load-shift keying. The design’s safety is ensured by on-board electrode voltage monitoring, stimulus charge limits, error checking of data transmitted to the implant, and comprehensive self-test and performance monitoring features. Each stimulus cycle is initiated by a transmitted word with a full 32-bit error check code. Taken together, these features allow researchers to safely and wirelessly tailor retinal stimulation and vision recovery for each patient. PMID:23365888

  15. Laser applications in integrated circuit packaging

    NASA Astrophysics Data System (ADS)

    Lu, Yongfeng; Song, Wen D.; Ren, ZhongMin; An, Chengwu; Ye, Kaidong D.; Liu, DaMing; Wang, Weijie; Hong, Ming Hui; Chong, Tow Chong

    2002-06-01

    Laser processing has large potential in the packaging of integrated circuits (IC). It can be used in many applications such as laser cleaning of IC mold tools, laser deflash to remove mold flash form heat sinks and lead wires of IC packages, laser singulation of BGA and CSP, laser reflow of solder ball on GBA, laser marking on packages and on SI wafers. During the implementation of all these applications, laser parameters, material issues, throughput, yield, reliability and monitoring techniques have to b taken into account. Monitoring of laser-induced plasma and laser induced acoustic wave has been used to understand and to control the processes involved in these applications.

  16. The GBT-SerDes ASIC prototype

    NASA Astrophysics Data System (ADS)

    Moreira, P.; Baron, S.; Bonacini, S.; Cobanoglu, O.; Faccio, F.; Feger, S.; Francisco, R.; Gui, P.; Li, J.; Marchioro, A.; Paillard, C.; Porret, D.; Wyllie, K.

    2010-11-01

    In the framework of the GigaBit Transceiver project (GBT), a prototype, the GBT-SerDes ASIC, was developed, fabricated and tested. To sustain high radiation doses while operating at 4.8Gb/s, the ASIC was fabricated in a commercial 130 nm CMOS technology employing radiation tolerant techniques and circuits. The transceiver serializes-deserializes the data, Reed-Solomon encodes and decodes the data and scrambles and descrambles the data for transmission over optical fibre links. This paper describes the GBT-SerDes architecture, and presents the test results.

  17. Cryogenic SiGe ASICs for readout and multiplexing of superconducting detector arrays

    NASA Astrophysics Data System (ADS)

    Voisin, F.; Prêle, D.; Bréelle, E.; Piat, M.; Sou, G.; Klisnick, G.; Redon, M.

    2008-07-01

    This paper presents an ultra low noise instrumentation based on cryogenic electronic integrated circuits (ASICs : Application Specific Integrated Circuits). We have designed successively two ASICs in standard BiCMOS SiGe 0.35 μm technology that have proved to be operating at cryogenic temperatures. The main functions of these circuits are the readout and the multiplexing of SQUID/TES arrays. We report the cryogenic operation of a first ASIC version dedicated to the readout of a 2×4 pixel demonstrator array. We particularly emphasize on the development and the test phases of an ultra low noise (0.2 nV/√Hz) cryogenic amplifier designed with two multiplexed inputs. The cryogenic SiGe amplifier coupled to a SQUID in a FLL operating at 4.2 K is also presented. We finally report on the development of a second version of this circuit to readout a 3×8 detectors array with improved noise performances and upgraded functionalities.

  18. Cryogenic SiGe ASICs for readout and multiplexing of superconducting detector arrays

    NASA Astrophysics Data System (ADS)

    Sou, G.; Klisnick, G.; Redon, M.; Voisin, F.; Prêle, D.; Bréelle, E.; Piat, M.

    2009-11-01

    This paper presents an ultra low noise instrumentation based on cryogenic electronic integrated circuits (ASICs: Application Specific Integrated Circuits). We have designed successively two ASICs in standard BiCMOS SiGe 0.35 μm technology that have proved to be operating at cryogenic temperatures. The main functions of these circuits are the readout and the multiplexing of TES/SQUID arrays. We report the cryogenic operation of a first ASIC version dedicated to the readout of a 2 × 4 pixel demonstrator array. We particularly emphasize on the development and the test phases of an ultra low white noise (0.2 nV/sqrtHz) cryogenic amplifier designed with two multiplexed inputs. The cryogenic SiGe amplifier coupled to a SQUID in a FLL operating at 4.2 K is also presented. We finally report on the development of a second version of this circuit to readout a 3 × 8 detectors array with improved noise performances and upgraded functionalities.

  19. Diagnostic applications of nucleic acid circuits.

    PubMed

    Jung, Cheulhee; Ellington, Andrew D

    2014-06-17

    CONSPECTUS: While the field of DNA computing and molecular programming was engendered in large measure as a curiosity-driven exercise, it has taken on increasing importance for analytical applications. This is in large measure because of the modularity of DNA circuitry, which can serve as a programmable intermediate between inputs and outputs. These qualities may make nucleic acid circuits useful for making decisions relevant to diagnostic applications. This is especially true given that nucleic acid circuits can potentially directly interact with and be triggered by diagnostic nucleic acids and other analytes. Chemists are, by and large, unaware of many of these advances, and this Account provides a means of touching on what might seem to be an arcane field. We begin by explaining nucleic acid amplification reactions that can lead to signal amplification, such as catalytic hairpin assembly (CHA) and the hybridization chain reaction (HCR). In these circuits, a single-stranded input acts on kinetically trapped substrates via exposed toeholds and strand exchange reactions, refolding the substrates and allowing them to interact with one another. As multiple duplexes (CHA) or concatemers of increasing length (HCR) are generated, there are opportunities to couple these outputs to different analytical modalities, including transduction to fluorescent, electrochemical, and colorimetric signals. Because both amplification and transduction are at their root dependent on the programmability of Waston-Crick base pairing, nucleic acid circuits can be much more readily tuned and adapted to new applications than can many other biomolecular amplifiers. As an example, robust methods for real-time monitoring of isothermal amplification reactions have been developed recently. Beyond amplification, nucleic acid circuits can include logic gates and thresholding components that allow them to be used for analysis and decision making. Scalable and complex DNA circuits (seesaw gates

  20. A Framework for Robust Multivariable Optimization of Integrated Circuits in Space Applications

    NASA Technical Reports Server (NTRS)

    DuMonthier, Jeffrey; Suarez, George

    2013-01-01

    Application Specific Integrated Circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way which facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as framework of software modules, templates and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation. Templates provide a starting point for both while toolbox functions minimize the code required. Once a test bench has been coded to optimize a particular circuit, it is also used to verify the final design. The combination of test bench and cost function can then serve as a template for similar circuits or be re-used to migrate the design to different processes by re-running it with the

  1. Radio-Frequency Electronics, Circuits and Applications

    NASA Astrophysics Data System (ADS)

    Hagen, Jon B.

    This accessible and comprehensive book provides an introduction to the basic concepts and key circuits of radio frequency systems, covering fundamental principles which apply to all radio devices, from wireless data transceivers on semiconductor chips to high-power broadcast transmitters. Topics covered include filters, amplifiers, oscillators, modulators, low-noise amplifiers, phase-locked loops, and transformers. Applications of radio frequency systems are described in such areas as communications, radio and television broadcasting, radar, and radio astronomy. The book contains many exercises, and assumes only a knowledge of elementary electronics and circuit analysis. It will be an ideal textbook for advanced undergraduate and graduate courses in electrical engineering, as well as an invaluable reference for researchers and professional engineers in this area, or for those moving into the field of wireless communications.

  2. Robust Multivariable Optimization and Performance Simulation for ASIC Design

    NASA Technical Reports Server (NTRS)

    DuMonthier, Jeffrey; Suarez, George

    2013-01-01

    Application-specific-integrated-circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power, and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem, which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques, which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable, are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way that facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as a framework of software modules, templates, and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation.

  3. DS Sentry: an acquisition ASIC for smart, micro-power sensing applications

    NASA Astrophysics Data System (ADS)

    Liobe, John; Fiscella, Mark; Moule, Eric; Balon, Mark; Bocko, Mark; Ignjatovic, Zeljko

    2011-06-01

    Unattended ground monitoring that combines seismic and acoustic information can be a highly valuable tool in intelligence gathering; however there are several prerequisites for this approach to be viable. The first is high sensitivity as well as the ability to discriminate real threats from noise and other spurious signals. By combining ground sensing with acoustic and image monitoring this requirement may be achieved. Moreover, the DS Sentry®provides innate spurious signal rejection by the "active-filtering" technique employed as well as embedding some basic statistical analysis. Another primary requirement is spatial and temporal coverage. The ideal is uninterrupted, long-term monitoring of an area. Therefore, sensors should be densely deployed and consume very little power. Furthermore, sensors must be inexpensive and easily deployed to allow dense placements in critical areas. The ADVIS DS Sentry®, which is a fully-custom integrated circuit that enables smart, micro-power monitoring of dynamic signals, is the foundation of the proposed system. The core premise behind this technology is the use of an ultra-low power front-end for active monitoring of dynamic signals in conjunction with a highresolution, Σ Δ-based analog-to-digital converter, which utilizes a novel noise rejection technique and is only employed when a potential threat has been detected. The DS Sentry® can be integrated with seismic accelerometers and microphones and user-programmed to continuously monitor for signals with specific signatures such as impacts, footsteps, excavation noise, vehicle-induced ground vibrations, or speech, while consuming only microwatts of power. This will enable up to several years of continuous monitoring on a single small battery while concurrently mitigating false threats.

  4. Controller and data acquisition system for SIDECAR ASIC driven HAWAII detectors

    NASA Astrophysics Data System (ADS)

    Ramaprakash, Anamparambu; Burse, Mahesh; Chordia, Pravin; Chillal, Kalpesh; Kohok, Abhay; Mestry, Vilas; Punnadi, Sujit; Sinha, Sakya

    2010-07-01

    SIDECAR is an Application Specific Integrated Circuit (ASIC), which can be used for control and data acquisition from near-IR HAWAII detectors offered by Teledyne Imaging Sensors (TIS), USA. The standard interfaces provided by Teledyne are COM API and socket servers running under MS Windows platform. These interfaces communicate to the ASIC (and the detector) through an intermediate card called JWST ASIC Drive Electronics (JADE2). As part of an ongoing programme of several years, for developing astronomical focal plane array (CCDs, CMOS and Hybrid) controllers and data acquisition systems (CDAQs), IUCAA is currently developing the next generation controllers employing Virtex-5 family FPGA devices. We present here the capabilities which are built into these new CDAQs for handling HAWAII detectors. In our system, the computer which hosts the application programme, user interface and device drivers runs on a Linux platform. It communicates through a hot-pluggable USB interface (with an optional optical fibre extender) to the FPGA-based card which replaces the JADE2. The FPGA board in turn, controls the SIDECAR ASIC and through it a HAWAII-2RG detector, both of which are located in a cryogenic test Dewar set up which is liquid nitrogen cooled. The system can acquire data over 1, 4, or 32 readout channels, with or without binning, at different speeds, can define sub-regions for readout, offers various readout schemes like Fowler sampling, up-theramp etc. In this paper, we present the performance results obtained from a prototype system.

  5. A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond

    SciTech Connect

    Gass, Karl; Pierson, Lyndon G.; Robertson, Perry J.; Wilcox, D. Craig; Witzke, Edward L.

    1999-04-30

    The Sandia National Laboratories (SNL) Data Encryption Standard (DES) Application Specific Integrated Circuit (ASIC) is the fastest known implementation of the DES algorithm as defined in the Federal Information Processing Standards (FIPS) Publication 46-2. DES is used for protecting data by cryptographic means. The SNL DES ASIC, over 10 times faster than other currently available DES chips, is a high-speed, filly pipelined implementation offering encryption, decryption, unique key input, or algorithm bypassing on each clock cycle. Operating beyond 105 MHz on 64 bit words, this device is capable of data throughputs greater than 6.7 Billion bits per second (tester limited). Simulations predict proper operation up to 9.28 Billion bits per second. In low frequency, low data rate applications, the ASIC consumes less that one milliwatt of power. The device has features for passing control signals synchronized to throughput data. Three SNL DES ASICS may be easily cascaded to provide the much greater security of triple-key, triple-DES.

  6. VLSI circuits and systems for microphotonic applications

    NASA Astrophysics Data System (ADS)

    Lachowicz, S.; Rassau, A.; Kim, C.; Lee, S.-M.

    2005-12-01

    This paper describes various VLSI systems for microphotonic applications. The first project investigates an optimum phase design implementing a multi phase Opto-ULSI processor for multi-function capable optical networks. This research is oriented around the initial development of an 8 phase Opto-ULSI processor that implements a Beam Steering (BS) Opto-ULSI processor (OUP) for integrated intelligent photonic system (IIPS), while investigating the optimal phase characteristics and developing compensation for the nonlinearity of liquid crystal. The second part provides an insight into realisation of a novel 3-D configurable chip based on "sea-of-pixels" architecture, which is highly suitable for applications in multimedia systems as well as for computation of coefficients for generation of holograms required in optical switches. The paper explores strategies for implementation of distributed primitives for arithmetic processing. This entails optimisation of basic cells that would allow using these primitives as part of a 3-D "sea-of-pixel" configurable processing array. The concept of 3-D Soft-Chip Technology (SCT) entails integration of "Soft-Processing Circuits" with "Soft-Configurable Circuits", which effectively manipulates hardware primitives through vertical integration of control and data. Thus the notion of 3-D Soft-Chip emerges as a new design paradigm for content-rich multimedia, telecommunication and photonic-based networking system applications. Combined with the effective manipulation of configurable hardware arithmetic primitives, highly efficient and powerful soft configurable processing systems can be realized.

  7. A wireless capsule system with ASIC for monitoring the physiological signals of the human gastrointestinal tract.

    PubMed

    Xu, Fei; Yan, Guozheng; Zhao, Kai; Lu, Li; Gao, Jinyang; Liu, Gang

    2014-12-01

    This paper presents the design of a wireless capsule system for monitoring the physiological signals of the human gastrointestinal (GI) tract. The primary components of the system include a wireless capsule, a portable data recorder, and a workstation. Temperature, pH, and pressure sensors; an RF transceiver; a controlling and processing application specific integrated circuit (ASIC); and batteries were applied in a wireless capsule. Decreasing capsule size, improving sensor precision, and reducing power needs were the primary challenges; these were resolved by employing micro sensors, optimized architecture, and an ASIC design that include power management, clock management, a programmable gain amplifier (PGA), an A/D converter (ADC), and a serial peripheral interface (SPI) communication unit. The ASIC has been fabricated in 0.18- μm CMOS technology with a die area of 5.0 mm × 5.0 mm. The wireless capsule integrating the ASIC controller measures Φ 11 mm × 26 mm. A data recorder and a workstation were developed, and 20 cases of human experiments were conducted in hospitals. Preprocessing in the workstation can significantly improve the quality of the data, and 76 original features were determined by mathematical statistics. Based on the 13 optimal features achieved in the evaluation of the features, the clustering algorithm can identify the patients who lack GI motility with a recognition rate reaching 83.3%. PMID:25608285

  8. FRONT-END ASIC FOR HIGH RESOLUTION X-RAY SPECTROMETERS.

    SciTech Connect

    DE GERONIMO,G.; CHEN, W.; FRIED, J.; LI, Z.; PINELLI, D.A.; REHAK, P.; VERNON, E.; GASKIN, J.A.; RAMSEY, B.D.; ANELLI, G.

    2007-10-27

    We present an application specific integrated circuit (ASIC) for high-resolution x-ray spectrometers. The ASIC is designed to read out signals from a pixelated silicon drift detector (SDD). Each hexagonal pixel has an area of 15 mmz and an anode capacitance of less than 100 fF. There is no integrated Field Effect transistor (FET) in the pixel, rather, the readout is done by wirebonding the anodes to the inputs of the ASIC. The ASIC provides 14 channels of low-noise charge amplification, high-order shaping with baseline stabilization, and peak detection with analog memory. The readout is sparse and based on low voltage differential signaling. An interposer provides all the interconnections required to bias and operate the system. The channel dissipates 1.6 mW. The complete 14-pixel unit covers an area of 210 mm{sup 2}, dissipates 12 mW cm{sup -2}, and can be tiled to cover an arbitrarily large detection area. We measured a preliminary resolution of 172 eV at -35 C on the 6 keV peak of a {sup 55}Fe source.

  9. The GBT-SCA, a radiation tolerant ASIC for detector control and monitoring applications in HEP experiments

    NASA Astrophysics Data System (ADS)

    Caratelli, A.; Bonacini, S.; Kloukinas, K.; Marchioro, A.; Moreira, P.; De Oliveira, R.; Paillard, C.

    2015-03-01

    The future upgrades of the LHC experiments will increase the beam luminosity leading to a corresponding growth of the amounts of data to be treated by the data acquisition systems. To address these needs, the GBT (Giga-Bit Transceiver optical link [1,2]) architecture was developed to provide the simultaneous transfer of readout data, timing and trigger signals as well as slow control and monitoring data. The GBT-SCA ASIC, part of the GBT chip-set, has the purpose to distribute control and monitoring signals to the on-detector front-end electronics and perform monitoring operations of detector environmental parameters. In order to meet the requirements of different front-end ASICs used in the experiments, it provides various user-configurable interfaces capable to perform simultaneous operations. It is designed employing radiation tolerant design techniques to ensure robustness against SEUs and TID radiation effects and is implemented in a commercial 130 nm CMOS technology. This work presents the GBT-SCA architecture, the ASIC interfaces, the data transfer protocol, and its integration with the GBT optical link.

  10. An Analog Low-Power Frequency Readout ASIC for a SAW Array

    NASA Astrophysics Data System (ADS)

    Chiu, Shih-Wen; Li, Chen-Han; Tang, Kea-Tiong

    2011-11-01

    A polymer coated surface acoustic wave (SAW) array has potential as a gas sensing material for electronic nose (eNose) applications. But the bulky and costly SAW frequency readout instruments such as spectrum analyzers and frequency counters have made SAW based eNose applications unpopular for portable use. In previous research, SAW interface electronics comprising discrete components have been developed to implement a portable eNose. However, the system consumes considerable dynamic power due to SAW device operating at high center frequencies. This work proposes a low-power analog CMOS frequency readout application-specific integrated circuit (ASIC) for potential portable applications.

  11. Burst Mode ASIC-Based Modem

    NASA Technical Reports Server (NTRS)

    1997-01-01

    The NASA Lewis Research Center is sponsoring the Advanced Communication Technology Insertion (ACTION) for Commercial Space Applications program. The goal of the program is to expedite the development of new technology with a clear path towards productization and enhancing the competitiveness of U.S. manufacturers. The industry has made significant investment in developing ASIC-based modem technology for continuous-mode applications and has made investigations into East, reliable acquisition of burst-mode digital communication signals. With rapid advances in analog and digital communications ICs, it is expected that more functions will be integrated onto these parts in the near future. In addition custom ASIC's can also be developed to address the areas not covered by the other IC's. Using the commercial chips and custom ASIC's, lower-cost, compact, reliable, and high-performance modems can be built for demanding satellite communication application. This report outlines a frequency-hop burst modem design based on commercially available chips.

  12. NIRCA ASIC for the readout of focal plane arrays

    NASA Astrophysics Data System (ADS)

    Pâhlsson, Philip; Steenari, David; Øya, Petter; Otnes Berge, Hans Kristian; Meier, Dirk; Olsen, Alf; Hasanbegovic, Amir; Altan, Mehmet A.; Najafiuchevler, Bahram; Talebi, Jahanzad; Azman, Suleyman; Gheorghe, Codin; Ackermann, Jörg; Mæhlum, Gunnar; Johansen, Tor Magnus; Stein, Timo

    2016-05-01

    This work is a continuation of our preliminary tests on NIRCA - the Near Infrared Readout and Controller ASIC [1]. The primary application for NIRCA is future astronomical science and Earth observation missions where NIRCA will be used with mercury cadmium telluride image sensors (HgCdTe, or MCT) [2], [3]. Recently we have completed the ASIC tests in the cryogenic environment down to 77 K. We have verified that NIRCA provides to the readout integrated circuit (ROIC) regulated power, bias voltages, and fully programmable digital sequences with sample control of the analogue to digital converters (ADC). Both analog and digital output from the ROIC can be acquired and image data is 8b/10bencoded and delivered via serial interface. The NIRCA also provides temperature measurement, and monitors several analog and digital input channels. The preliminary work confirms that NIRCA is latch-up immune and able to operate down to 77 K. We have tested the performance of the 12-bit ADC with pre-amplifier to have 10.8 equivalent number of bits (ENOB) at 1.4 Msps and maximum sampling speed at 2 Msps. The 1.8-V and 3.3-V output regulators and the 10-bit DACs show good linearity and work as expected. A programmable sequencer is implemented as a micro-controller with a custom instruction set. Here we describe the special operations of the sequencer with regards to the applications and a novel approach to parallel real-time hardware outputs. The test results of the working prototype ASIC show good functionality and performance from room temperature down to 77 K. The versatility of the chip makes the architecture a possible candidate for other research areas, defense or industrial applications that require analog and digital acquisition, voltage regulation, and digital signal generation.

  13. ASIC proteins regulate smooth muscle cell migration.

    PubMed

    Grifoni, Samira C; Jernigan, Nikki L; Hamilton, Gina; Drummond, Heather A

    2008-03-01

    The purpose of the present study was to investigate Acid Sensing Ion Channel (ASIC) protein expression and importance in cellular migration. We recently demonstrated that Epithelial Na(+)Channel (ENaC) proteins are required for vascular smooth muscle cell (VSMC) migration; however, the role of the closely related ASIC proteins has not been addressed. We used RT-PCR and immunolabeling to determine expression of ASIC1, ASIC2, ASIC3 and ASIC4 in A10 cells. We used small interference RNA to silence individual ASIC expression and determine the importance of ASIC proteins in wound healing and chemotaxis (PDGF-bb)-initiated migration. We found ASIC1, ASIC2, and ASIC3, but not ASIC4, expression in A10 cells. ASIC1, ASIC2, and ASIC3 siRNA molecules significantly suppressed expression of their respective proteins compared to non-targeting siRNA (RISC) transfected controls by 63%, 44%, and 55%, respectively. Wound healing was inhibited by 10, 20, and 26% compared to RISC controls following suppression of ASIC1, ASIC2, and ASIC3, respectively. Chemotactic migration was inhibited by 30% and 45%, respectively, following suppression of ASIC1 and ASIC3. ASIC2 suppression produced a small, but significant, increase in chemotactic migration (4%). Our data indicate that ASIC expression is required for normal migration and may suggest a novel role for ASIC proteins in cellular migration. PMID:17936312

  14. XAMPS Detectors Readout ASIC for LCLS

    SciTech Connect

    Dragone, A; Pratte, J.F.; Rehak, P.; Carini, G.A.; Herbst, R.; O'Connor, P.; Siddons, D.P.; /BNL, NSLS

    2008-12-18

    An ASIC for the readout of signals from X-ray Active Matrix Pixel Sensor (XAMPS) detectors to be used at the Linac Coherent Light Source (LCLS) is presented. The X-ray Pump Probe (XPP) instrument, for which the ASIC has been designed, requires a large input dynamic range on the order of 104 photons at 8 keV with a resolution of half a photon FWHM. Due to the size of the pixel and the length of the readout line, large input capacitance is expected, leading to stringent requirement on the noise optimization. Furthermore, the large number of pixels needed for a good position resolution and the fixed LCLS beam period impose limitations on the time available for the single pixel readout. Considering the periodic nature of the LCLS beam, the ASIC developed for this application is a time-variant system providing low-noise charge integration, filtering and correlated double sampling. In order to cope with the large input dynamic range a charge pump scheme implementing a zero-balance measurement method has been introduced. It provides an on chip 3-bit coarse digital conversion of the integrated charge. The residual charge is sampled using correlated double sampling into analog memory and measured with the required resolution. The first 64 channel prototype of the ASIC has been fabricated in TSMC CMOS 0.25 {micro}m technology. In this paper, the ASIC architecture and performances are presented.

  15. Integrated circuit cell library

    NASA Technical Reports Server (NTRS)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

    2005-01-01

    According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

  16. 20 CFR 405.515 - Application of circuit court law.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 20 Employees' Benefits 2 2010-04-01 2010-04-01 false Application of circuit court law. 405.515 Section 405.515 Employees' Benefits SOCIAL SECURITY ADMINISTRATION ADMINISTRATIVE REVIEW PROCESS FOR ADJUDICATING INITIAL DISABILITY CLAIMS Judicial Review § 405.515 Application of circuit court law. We...

  17. 20 CFR 416.1485 - Application of circuit court law.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 20 Employees' Benefits 2 2010-04-01 2010-04-01 false Application of circuit court law. 416.1485... Determinations and Decisions Court Remand Cases § 416.1485 Application of circuit court law. The procedures which... court law. (a) General. We will apply a holding in a United States Court of Appeals decision that...

  18. 20 CFR 404.985 - Application of circuit court law.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 20 Employees' Benefits 2 2010-04-01 2010-04-01 false Application of circuit court law. 404.985... and Decisions Court Remand Cases § 404.985 Application of circuit court law. The procedures which... court law. (a) General. We will apply a holding in a United States Court of Appeals decision that...

  19. Trigger Data Serializer ASIC chip for the ATLAS New Small Wheel sTGC Detector

    NASA Astrophysics Data System (ADS)

    Meng, Xiangting; Wang, Jinhong; Guan, Liang; Sang, Ziru; Chapman, John; Zhou, Bing; Zhu, Junjie

    2015-04-01

    The small-strip thin-gap chambers (sTGC) will be used as the trigger device for the Phase-I upgrade of the ATLAS new small wheel (nSW) muon detector. An Application-Specific Integrated Circuit (ASIC) chip is needed to collect digital signals from both pad and strip detectors and serialize the outputs to the circuitry located on the rim of the nSW. The large number of input channels (128 differential input channels), short time available to prepare and transmit trigger data (<100 ns), high speed output data rate (4.8 Gbps), harsh radiation environment (about 300 kRad), and low power consumption (<1 W) impose great challenges for the design of this ASIC chip using the IBM 130 nm CMOS process. We will present our design and test results based on the prototype chip we build.

  20. Blind channel estimation for MLSE receiver in high speed optical communications: theory and ASIC implementation.

    PubMed

    Gorshtein, Albert; Levy, Omri; Katz, Gilad; Sadot, Dan

    2013-09-23

    Blind channel estimation is critical for digital signal processing (DSP) compensation of optical fiber communications links. The overall channel consists of deterministic distortions such as chromatic dispersion, as well as random and time varying distortions including polarization mode dispersion and timing jitter. It is critical to obtain robust acquisition and tracking methods for estimating these distortions effects, which, in turn, can be compensated by means of DSP such as Maximum Likelihood Sequence Estimation (MLSE). Here, a novel blind estimation algorithm is developed, accompanied by inclusive mathematical modeling, and followed by extensive set of real time experiments that verify quantitatively its performance and convergence. The developed blind channel estimation is used as the basis of an MLSE receiver. The entire scheme is fully implemented in a 65 nm CMOS Application Specific Integrated Circuit (ASIC). Experimental measurements and results are presented, including Bit Error Rate (BER) measurements, which demonstrate the successful data recovery by the MLSE ASIC under various channel conditions and distances. PMID:24104070

  1. Evaluation of the Teledyne SIDECAR ASIC at cryogenic temperature using a visible hybrid H2RG focal plane array in 32 channel readout mode

    NASA Astrophysics Data System (ADS)

    Dorn, Reinhold J.; Eschbaumer, Siegfried; Hall, Donald N. B.; Finger, Gert; Mehrgan, Leander; Meyer, Manfred; Stegmeier, Joerg

    2008-07-01

    Teledyne Imaging Sensors (TIS) has developed a new CMOS device known as the SIDECAR application-specific integrated circuit (ASIC). This single chip provides all the functionality of FPA drive electronics to operate visible and infrared imaging detectors with a fully digital interface. At the last SPIE conference we presented test and performance results of a Teledyne 2K×2K silicon PIN diode array hybridized to a Hawaii-2RG multiplexer, the Hybrid Visible Silicon Imager (HyViSI). This detector was read out with the ESO standard IR detector controller IRACE, which delivers detector limited performance. We have now tested the H2RG HyViSI detector with the new TIS SIDECAR ASIC in 32 channel readout mode at cryogenic temperatures. The SIDECAR has been evaluated down to 105 Kelvin operating temperature and performance results have been compared to those obtained with external electronics. We find that the SIDECAR ASIC provides performance equal to optimized external electronics.

  2. Front-End ASIC for Liquid Argon TPC

    SciTech Connect

    De Geronimo, G.; Li, S.; D'Andragora, A.; Nambiar, N.; Rescia, S.; Vernon, E.; Chen, H.; Lanni, F.; Makowiecki, D.; Radeka, V.; Thorn, C.; Yu, B.

    2011-06-15

    We present a front-end application-specific integrated circuit (ASIC) for a wire based time-projection-chamber (TPC) operating in liquid Argon (LAr). The LAr TPC will be used for long baseline neutrino oscillation experiments. The ASIC must provide a low-noise readout of the signals induced on the TPC wires, digitization of those signals at 2 MSamples/s, compression, buffering and multiplexing. A resolution of better than 1000 rms electrons at 200 pF input capacitance for an input range of 300 fC is required, along with low power and operation in LAr (at 87 K). We include the characterization of a commercial technology for operation in the cryogenic environment and the first experimental results on the analog front end. The results demonstrate that complementary metal-oxide semiconductor transistors have lower noise and much improved dc characteristics at LAr temperature. Finally, we introduce the concept of '1/f equivalent' to model the low-frequency component of the noise spectral density, for use in the input metal-oxide semiconductor field-effect transistor optimization.

  3. Replication of Space-Shuttle Computers in FPGAs and ASICs

    NASA Technical Reports Server (NTRS)

    Ferguson, Roscoe C.

    2008-01-01

    A document discusses the replication of the functionality of the onboard space-shuttle general-purpose computers (GPCs) in field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The purpose of the replication effort is to enable utilization of proven space-shuttle flight software and software-development facilities to the extent possible during development of software for flight computers for a new generation of launch vehicles derived from the space shuttles. The replication involves specifying the instruction set of the central processing unit and the input/output processor (IOP) of the space-shuttle GPC in a hardware description language (HDL). The HDL is synthesized to form a "core" processor in an FPGA or, less preferably, in an ASIC. The core processor can be used to create a flight-control card to be inserted into a new avionics computer. The IOP of the GPC as implemented in the core processor could be designed to support data-bus protocols other than that of a multiplexer interface adapter (MIA) used in the space shuttle. Hence, a computer containing the core processor could be tailored to communicate via the space-shuttle GPC bus and/or one or more other buses.

  4. READOUT ASIC FOR 3D POSITION-SENSITIVE DETECTORS.

    SciTech Connect

    DE GERONIMO,G.; VERNON, E.; ACKLEY, K.; DRAGONE, A.; FRIED, J.; OCONNOR, P.; HE, Z.; HERMAN, C.; ZHANG, F.

    2007-10-27

    We describe an application specific integrated circuit (ASIC) for 3D position-sensitive detectors. It was optimized for pixelated CZT sensors, and it measures, corresponding to an ionizing event, the energy and timing of signals from 121 anodes and one cathode. Each channel provides low-noise charge amplification, high-order shaping, along with peak- and timing-detection. The cathode's timing can be measured in three different ways: the first is based on multiple thresholds on the charge amplifier's voltage output; the second uses the threshold crossing of a fast-shaped signal; and the third measures the peak amplitude and timing from a bipolar shaper. With its power of 2 mW per channel the ASIC measures, on a CZT sensor Connected and biased, charges up to 100 fC with an electronic resolution better than 200 e{sup -} rms. Our preliminary spectral measurements applying a simple cathode/mode ratio correction demonstrated a single-pixel resolution of 4.8 keV (0.72 %) at 662 keV, with the electronics and leakage current contributing in total with 2.1 keV.

  5. Evaluation of a front-end ASIC for the readout of PMTs over a large dynamic range

    NASA Astrophysics Data System (ADS)

    Wu, Wei-Hao; Zhao, Lei; Liang, Yu; Yu, Li; Liu, Jian-Feng; Liu, Shu-Bin; An, Qi

    2015-12-01

    The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of the major detectors for searching for gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit), fabricated with Global Foundry 0.35 μm CMOS technology, has been developed for readout of photomultiplier tubes (PMTs) in the WCDA. This ASIC provides both time and charge measurement of PMT signals. The input charge is converted to a pulse width based on the Time-Over-Threshold (TOT) technique and linear discharge method; as for time measurement, leading edge discrimination is employed. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better than 400 ps and the charge resolution is better than 1% with large input signals and remains better than 15% @1 photoelectron (P.E.), both beyond the application requirement. Moreover, this ASIC has a weak ambient temperature dependence, low input rate dependence and high channel-to-channel isolation.

  6. High performance protection circuit for power electronics applications

    NASA Astrophysics Data System (ADS)

    Tudoran, Cristian D.; Dǎdârlat, Dorin N.; Toşa, Nicoleta; Mişan, Ioan

    2015-12-01

    In this paper we present a high performance protection circuit designed for the power electronics applications where the load currents can increase rapidly and exceed the maximum allowed values, like in the case of high frequency induction heating inverters or high frequency plasma generators. The protection circuit is based on a microcontroller and can be adapted for use on single-phase or three-phase power systems. Its versatility comes from the fact that the circuit can communicate with the protected system, having the role of a "sensor" or it can interrupt the power supply for protection, in this case functioning as an external, independent protection circuit.

  7. High performance protection circuit for power electronics applications

    SciTech Connect

    Tudoran, Cristian D. Dădârlat, Dorin N.; Toşa, Nicoleta; Mişan, Ioan

    2015-12-23

    In this paper we present a high performance protection circuit designed for the power electronics applications where the load currents can increase rapidly and exceed the maximum allowed values, like in the case of high frequency induction heating inverters or high frequency plasma generators. The protection circuit is based on a microcontroller and can be adapted for use on single-phase or three-phase power systems. Its versatility comes from the fact that the circuit can communicate with the protected system, having the role of a “sensor” or it can interrupt the power supply for protection, in this case functioning as an external, independent protection circuit.

  8. Simultaneous Disruption of Mouse ASIC1a, ASIC2 and ASIC3 Genes Enhances Cutaneous Mechanosensitivity

    PubMed Central

    Kang, Sinyoung; Jang, Jun Ho; Price, Margaret P.; Gautam, Mamta; Benson, Christopher J.; Gong, Huiyu; Welsh, Michael J.; Brennan, Timothy J.

    2012-01-01

    Three observations have suggested that acid-sensing ion channels (ASICs) might be mammalian cutaneous mechanoreceptors; they are structurally related to Caenorhabditis elegans mechanoreceptors, they are localized in specialized cutaneous mechanosensory structures, and mechanical displacement generates an ASIC-dependent depolarization in some neurons. However, previous studies of mice bearing a single disrupted ASIC gene showed only subtle or no alterations in cutaneous mechanosensitivity. Because functional redundancy of ASIC subunits might explain limited phenotypic alterations, we hypothesized that disrupting multiple ASIC genes would markedly impair cutaneous mechanosensation. We found the opposite. In behavioral studies, mice with simultaneous disruptions of ASIC1a, -2 and -3 genes (triple-knockouts, TKOs) showed increased paw withdrawal frequencies when mechanically stimulated with von Frey filaments. Moreover, in single-fiber nerve recordings of cutaneous afferents, mechanical stimulation generated enhanced activity in A-mechanonociceptors of ASIC TKOs compared to wild-type mice. Responses of all other fiber types did not differ between the two genotypes. These data indicate that ASIC subunits influence cutaneous mechanosensitivity. However, it is unlikely that ASICs directly transduce mechanical stimuli. We speculate that physical and/or functional association of ASICs with other components of the mechanosensory transduction apparatus contributes to normal cutaneous mechanosensation. PMID:22506072

  9. Improved On-Chip Measurement of Delay in an FPGA or ASIC

    NASA Technical Reports Server (NTRS)

    Chen, Yuan; Burke, Gary; Sheldon, Douglas

    2007-01-01

    An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

  10. Monolithic readout circuits for RHIC

    SciTech Connect

    O`Connor, P.; Harder, J.

    1991-12-31

    Several CMOS ASICs have been developed for a proposed RHIC experiment. This paper discusses why ASIC implementation was chosen for certain functions, circuit specifications and the design techniques used to meet them, and results of simulations and early prototypes. By working closely together from an early stage in the planning process, in-house ASIC designers and detector and data acquisition experimenters can achieve optimal use of this important technology.

  11. ASIC design in the KM3NeT detector

    NASA Astrophysics Data System (ADS)

    Gajanana, D.; Gromov, V.; Timmer, P.

    2013-02-01

    In the KM3NeT project [1], Cherenkov light from the muon interactions with transparent matter around the detector, is used to detect neutrinos. Photo multiplier tubes (PMT) used as photon sensor, are housed in a glass sphere (aka Optical Module) to detect single photons from the Cherenkov light. The PMT needs high operational voltage ( ~ 1.5 kV) and is generated by a Cockroft-Walton (CW) multiplier circuit. The electronics required to control the PMT's and collect the signals is integrated in two ASIC's namely: 1) a front-end mixed signal ASIC (PROMiS) for the readout of the PMT and 2) an analog ASIC (CoCo) to generate pulses for charging the CW circuit and to control the feedback of the CW circuit. In this article, we discuss the two integrated circuits and test results of the complete setup. PROMiS amplifies the input charge, converts it to a pulse width and delivers the information via LVDS signals. These LVDS signals carry accurate information on the Time of arrival ( < 2 ns) and Time over Threshold. A PROM block provides unique identification to the chip. The chip communicates with the control electronics via an I2C bus. This unique combination of the ASIC's results in a very cost and power efficient PMT base design.

  12. Acid-sensing ion channels (ASICs) in mouse skeletal muscle afferents are heteromers composed of ASIC1a, ASIC2, and ASIC3 subunits

    PubMed Central

    Gautam, Mamta; Benson, Christopher J.

    2013-01-01

    Acid-sensing ion channels (ASICs) are expressed in skeletal muscle afferents, in which they sense extracellular acidosis and other metabolites released during ischemia and exercise. ASICs are formed as homotrimers or heterotrimers of several isoforms (ASIC1a, ASIC1b, ASIC2a, ASIC2b, and ASIC3), with each channel displaying distinct properties. To dissect the ASIC composition in muscle afferents, we used whole-cell patch-clamp recordings to study the properties of acid-evoked currents (amplitude, pH sensitivity, the kinetics of desensitization and recovery from desensitization, and pharmacological modulation) in isolated, labeled mouse muscle afferents from wild-type (C57BL/6J) and specific ASIC−/− mice. We found that ASIC-like currents in wild-type muscle afferents displayed fast desensitization, indicating that they are carried by heteromeric channels. Currents from ASIC1a−/− muscle afferents were less pH-sensitive and displayed faster recovery, currents from ASIC2−/− mice showed diminished potentiation by zinc, and currents from ASIC3−/− mice displayed slower desensitization than those from wild-type mice. Finally, ASIC-like currents were absent from triple-null mice lacking ASIC1a, ASIC2a, and ASIC3. We conclude that ASIC1a, ASIC2a, and ASIC3 heteromers are the principle channels in skeletal muscle afferents. These results will help us understand the role of ASICs in exercise physiology and provide a molecular target for potential drug therapies to treat muscle pain.—Gautam, M., Benson, C. J. Acid-sensing ion channels (ASICs) in mouse skeletal muscle afferents are heteromers composed of ASIC1a, ASIC2, and ASIC3 subunits. PMID:23109675

  13. Latest generation of ASICs for photodetector readout

    NASA Astrophysics Data System (ADS)

    Seguin-Moreau, N.

    2013-08-01

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the "ROC" family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the "ROC" chips.

  14. The expression profile of acid-sensing ion channel (ASIC) subunits ASIC1a, ASIC1b, ASIC2a, ASIC2b, and ASIC3 in the esophageal vagal afferent nerve subtypes

    PubMed Central

    Dusenkova, Svetlana; Ru, Fei; Surdenikova, Lenka; Nassenstein, Christina; Hatok, Jozef; Dusenka, Robert; Banovcin, Peter; Kliment, Jan; Tatar, Milos

    2014-01-01

    Acid-sensing ion channels (ASICs) have been implicated in esophageal acid sensing and mechanotransduction. However, insufficient knowledge of ASIC subunit expression profile in esophageal afferent nerves hampers the understanding of their role. This knowledge is essential because ASIC subunits form heteromultimeric channels with distinct functional properties. We hypothesized that the esophageal putative nociceptive C-fiber nerves (transient receptor potential vanilloid 1, TRPV1-positive) express multiple ASIC subunits and that the ASIC expression profile differs between the nodose TRPV1-positive subtype developmentally derived from placodes and the jugular TRPV1-positive subtype derived from neural crest. We performed single cell RT-PCR on the vagal afferent neurons retrogradely labeled from the esophagus. In the guinea pig, nearly all (90%–95%) nodose and jugular esophageal TRPV1-positive neurons expressed ASICs, most often in a combination (65–75%). ASIC1, ASIC2, and ASIC3 were expressed in 65–75%, 55–70%, and 70%, respectively, of both nodose and jugular TRPV1-positive neurons. The ASIC1 splice variants ASIC1a and ASIC1b and the ASIC2 splice variant ASIC2b were similarly expressed in both nodose and jugular TRPV1-positive neurons. However, ASIC2a was found exclusively in the nodose neurons. In contrast to guinea pig, ASIC3 was almost absent from the mouse vagal esophageal TRPV1-positive neurons. However, ASIC3 was similarly expressed in the nonnociceptive TRPV1-negative (tension mechanoreceptors) neurons in both species. We conclude that the majority of esophageal vagal nociceptive neurons express multiple ASIC subunits. The placode-derived nodose neurons selectively express ASIC2a, known to substantially reduce acid sensitivity of ASIC heteromultimers. ASIC3 is expressed in the guinea pig but not in the mouse vagal esophageal TRPV1-positive neurons, indicating species differences in ASIC expression. PMID:25190475

  15. An analogue front-end ASIC prototype designed for PMT signal readout

    NASA Astrophysics Data System (ADS)

    Liu, Jian-Feng; Zhao, Lei; Yu, Li; Liang, Yu; Qin, Jia-Jun; Yang, Yun-Fan; Wu, Wei-Hao; Liu, Shu-Bin; An, Qi

    2016-06-01

    The Water Cherenkov Detector Array (WCDA) is one of the core detectors in the Large High Altitude Air Shower Observatory (LHAASO), and it consists of 3600 photomultiplier tubes (PMTs). Both high resolution time and charge measurement are required over a large dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated using Global Foundry 0.35 μm CMOS technology is designed to read out the PMT signal in the WCDA. This ASIC employs leading edge discrimination and an (RC)4 shaping structure. Combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge resolution is better than 10% at 1 P.E. and better than 1% with large input signals (300 P.E. to 4000 P.E.). Besides, this ASIC has a good channel-to-channel isolation of more than 84 dB and the temperature dependency of charge measurement is less than 5% in the range 0–50°C. Supported by Knowledge Innovation Program of Chinese Academy of Sciences (KJCX2-YW-N27), National Natural Science Foundation of China (11175174) and CAS Center for Excellence in Particle Physics (CCEPP)

  16. Towards Evolving Electronic Circuits for Autonomous Space Applications

    NASA Technical Reports Server (NTRS)

    Lohn, Jason D.; Haith, Gary L.; Colombano, Silvano P.; Stassinopoulos, Dimitris

    2000-01-01

    The relatively new field of Evolvable Hardware studies how simulated evolution can reconfigure, adapt, and design hardware structures in an automated manner. Space applications, especially those requiring autonomy, are potential beneficiaries of evolvable hardware. For example, robotic drilling from a mobile platform requires high-bandwidth controller circuits that are difficult to design. In this paper, we present automated design techniques based on evolutionary search that could potentially be used in such applications. First, we present a method of automatically generating analog circuit designs using evolutionary search and a circuit construction language. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm, we present experimental results for five design tasks. Second, we investigate the use of coevolution in automated circuit design. We examine fitness evaluation by comparing the effectiveness of four fitness schedules. The results indicate that solution quality is highest with static and co-evolving fitness schedules as compared to the other two dynamic schedules. We discuss these results and offer two possible explanations for the observed behavior: retention of useful information, and alignment of problem difficulty with circuit proficiency.

  17. 1998 technology roadmap for integrated circuits used in critical applications

    SciTech Connect

    Dellin, T.A.

    1998-09-01

    Integrated Circuits (ICs) are being extensively used in commercial and government applications that have extreme consequences of failure. The rapid evolution of the commercial microelectronics industry presents serious technical and supplier challenges to this niche critical IC marketplace. This Roadmap was developed in conjunction with the Using ICs in Critical Applications Workshop which was held in Albuquerque, NM, November 11--12, 1997.

  18. LEC GaAs for integrated circuit applications

    NASA Technical Reports Server (NTRS)

    Kirkpatrick, C. G.; Chen, R. T.; Homes, D. E.; Asbeck, P. M.; Elliott, K. R.; Fairman, R. D.; Oliver, J. D.

    1984-01-01

    Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.

  19. Acid-sensing ion channels 1a (ASIC1a) inhibit neuromuscular transmission in female mice

    PubMed Central

    Lino, Noelia G.; González-Inchauspe, Carlota M. F.; González, Laura E.; Colettis, Natalia; Vattino, Lucas G.; Wunsch, Amanda M.; Wemmie, John A.; Uchitel, Osvaldo D.

    2013-01-01

    Acid-sensing ion channels (ASIC) open in response to extracellular acidosis. ASIC1a, a particular subtype of these channels, has been described to have a postsynaptic distribution in the brain, being involved not only in ischemia and epilepsy, but also in fear and psychiatric pathologies. High-frequency stimulation of skeletal motor nerve terminals (MNTs) can induce presynaptic pH changes in combination with an acidification of the synaptic cleft, known to contribute to muscle fatigue. Here, we studied the role of ASIC1a channels on neuromuscular transmission. We combined a behavioral wire hanging test with electrophysiology, pharmacological, and immunofluorescence techniques to compare wild-type and ASIC1a lacking mice (ASIC1a −/− knockout). Our results showed that 1) ASIC1a −/− female mice were weaker than wild type, presenting shorter times during the wire hanging test; 2) spontaneous neurotransmitter release was reduced by ASIC1a activation, suggesting a presynaptic location of these channels at individual MNTs; 3) ASIC1a-mediated effects were emulated by extracellular local application of acid saline solutions (pH = 6.0; HEPES/MES-based solution); and 4) immunofluorescence techniques revealed the presence of ASIC1a antigens on MNTs. These results suggest that ASIC1a channels might be involved in controlling neuromuscular transmission, muscle contraction and fatigue in female mice. PMID:24336653

  20. Selective targeting of ASIC3 using artificial miRNAs inhibits primary and secondary hyperalgesia after muscle inflammation

    PubMed Central

    Walder, Roxanne Y.; Gautam, Mamta; Wilson, Steven P.; Benson, Christopher J.; Sluka, Kathleen A.

    2012-01-01

    Acid-sensing ion channels (ASICs) are activated by acidic pH and may play a significant role in the development of hyperalgesia. Earlier studies show ASIC3 is important for induction of hyperalgesia after muscle insult using ASIC3−/− mice. ASIC3−/− mice lack ASIC3 throughout the body, and the distribution and composition of ASICs could be different from wild-type mice. We therefore tested whether knockdown of ASIC3 in primary afferents innervating muscle of adult wild-type mice prevented development of hyper-algesia to muscle inflammation. We cloned and characterized artificial miRNAs (miR-ASIC3) directed against mouse ASIC3 (mASIC3) to downregulate ASIC3 expression in vitro and in vivo. In CHO-K1 cells transfected with mASIC3 cDNA in culture, the miR-ASIC3 constructs inhibited protein expression of mASIC3 and acidic pH-evoked currents and had no effect on protein expression or acidic pH-evoked currents of ASIC1a. When miR-ASIC3 was used in vivo, delivered into the muscle of mice using a herpes simplex viral vector, both muscle and paw mechanical hyperalgesia were reduced after carrageenan-induced muscle inflammation. ASIC3 mRNA in DRG and protein levels in muscle were decreased in vivo by miRASIC3. In CHO-K1 cells co-transfected with ASIC1a and ASIC3, miR-ASIC3 reduced the amplitude of acidic pH-evoked currents, suggesting an overall inhibition in the surface expression of heteromeric ASIC3-containing channels. Our results show, for the first time, that reducing ASIC3 in vivo in primary afferent fibers innervating muscle prevents the development of inflammatory hyperalgesia in wild-type mice, and thus, may have applications in the treatment of musculoskeletal pain in humans. PMID:21843914

  1. Printed circuits and their applications: Which way forward?

    NASA Astrophysics Data System (ADS)

    Cantatore, E.

    2015-09-01

    The continuous advancements in printed electronics make nowadays feasible the design of printed circuits which enable meaningful applications. Examples include ultra-low cost sensors embedded in food packaging, large-area sensing surfaces and biomedical assays. This paper offers an overview of state-of-the-art digital and analog circuit blocks, manufactured with a printed complementary organic TFT technology. An analog to digital converter and an RFID tag implemented exploiting these building blocks are also described. The main remaining drawbacks of the printed technology described are identified, and new approaches to further improve the state of the art, enabling more innovative applications are discussed.

  2. Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

    NASA Astrophysics Data System (ADS)

    Gao, W.; Gan, B.; Li, X.; Wei, T.; Gao, D.; Hu, Y.

    2015-04-01

    In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e- at zero farad plus 10 e- per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source 241Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si).

  3. Mongoose ASIC microcontroller programming guide

    NASA Astrophysics Data System (ADS)

    Smith, Brian S.

    1993-09-01

    The 'Mongoose' ASIC microcontroller is a radiation-hard implementation of the R3000 microprocessor. This document describes the internals of the microcontroller in a level of detail necessary for someone implementing a software design.

  4. Mongoose ASIC microcontroller programming guide

    NASA Technical Reports Server (NTRS)

    Smith, Brian S.

    1993-01-01

    The 'Mongoose' ASIC microcontroller is a radiation-hard implementation of the R3000 microprocessor. This document describes the internals of the microcontroller in a level of detail necessary for someone implementing a software design.

  5. Design Methodology: ASICs with complex in-pixel processing for Pixel Detectors

    SciTech Connect

    Fahim, Farah

    2014-10-31

    The development of Application Specific Integrated Circuits (ASIC) for pixel detectors with complex in-pixel processing using Computer Aided Design (CAD) tools that are, themselves, mainly developed for the design of conventional digital circuits requires a specialized approach. Mixed signal pixels often require parasitically aware detailed analog front-ends and extremely compact digital back-ends with more than 1000 transistors in small areas below 100μm x 100μm. These pixels are tiled to create large arrays, which have the same clock distribution and data readout speed constraints as in, for example, micro-processors. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout.

  6. MIC: Material and circuit evaluation for millimeter wave applications

    NASA Astrophysics Data System (ADS)

    Arndt, F.; Bornemann, J.; Grauerholz, D.; Vahldieck, R.; Christ, U.; Stolze, H.

    1981-02-01

    Surface roughness, dielectric constant, quality factor, and loss were measured and a literature survey was conducted to determine materials and circuits suitable for microwave application. The best materials found are RT/Duroid, Rexolite, Polyguide, SiOz, and Al2O3. Fin line, dielectric image line, microstrip line, slot line, waveguide coplanar line, and suspended substrate line are suitable circuits, as shown by the performance of 2 high Q fin line filters up to 33.7 GHz, 3 microstrip 3 dB-hybrid couplers up to 28.3 GHz, a fin line mixer up to 40 GHz, and a fin line printed probe coupler for 31.3 GHz. The design theory for high Q fin line filters is given, including the higher order mode propagation. The measured results vefify the theory. Two of the circuits built were successfully vibration tested.

  7. Hierarchical Test Development and Design-For for (a)synchronous Semi-Custom Asics.

    NASA Astrophysics Data System (ADS)

    Leenstra, Jentje

    The research, described in this thesis, deals in particular with several problems, which arise when trying to automate the process of testing low-volume semi-custom ASICs. For low-volume ASICs one of the major problems is the reduction of the test application costs. To reduce the costs of testing low-volume ASICs, the use of a semi -custom test method with associated design-for-testability techniques is proposed. To be able to start the detection and removal of testability problems during the design, a novel automated hierarchical test program development procedure is presented. It is shown how, by generating a test specification for each hierarchical module, the test program can be developed incrementally. As a result, the testability of each module becomes known and it circumvents the need to generate a complete new test program after changes. To reduce the ASIC test time, the hierarchical test development approach supports the synthesis of a reconfigurable scan path. Thereby, our novel scan path architecture circumvents the need to introduce explicit test controllers by simply loading the reconfiguration information through the scan path itself. Since the hierarchical ASIC test development method as well as the semi-custom test method requires that all test vectors can be applied through a synchronous (reconfigurable) scan path, it is also investigate how asynchronous control circuits can be designed in such a way that they are synchronously scan testable. An implementation model is presented, that uses an explicit stale register composed of SR flip-flops. It is shown that these controllers are synchronously testable and can be derived directly from a state diagram description. Finally, the possibility of using a dedicated test generation procedure is illustrated by showing how the test program for modules composed of a data path and a finite state machine controller can be derived by the use of a novel symbolic test assembly procedure. The automated

  8. Rad-Hard Microcontroller for Space Applications

    NASA Astrophysics Data System (ADS)

    Habinc, Sandi; Johansson, Fredrik; Sturesson, Fredrik; Simlastik, Martin; Hjorth, Magnus; Andersson, Jan; Redant, Steven; Sijbers, Wim; Thys, Geert; Monteleone, Claudio

    2015-09-01

    This paper describes a mixed-signal LEON3FT microcontroller ASIC (Application Specific Integrated Circuit) targeting embedded control applications with hard real-time requirements. The prototype device is currently in development at Cobham Gaisler, Sweden, and IMEC, Belgium, in the activity Microcontroller for embedded space applications, initiated and funded by the European Space Agency (ESA).

  9. Applications of the dynamic circuit theory to maglev suspension systems

    SciTech Connect

    He, Jian Liang; Rote, D.M.; Coffey, H.T.

    1993-11-01

    This paper discusses the applications of dynamic circuit theory to electrodynamic suspension EDS systems. In particular, the paper focuses on the loop-shaped coil and the figure-eight-shaped null-flux coil suspension systems. Mathematical models, including very general force expressions that can be used for the development of computer codes, are provided for each of these suspension systems. General applications and advantages of the dynamic circuit model are summarized. The paper emphasizes the transient and dynamic analysis and computer simulation of maglev systems. In general, the method discussed here can be applied to many EDS maglev design concepts. It is also suited for the computation of the performance of maglev propulsion systems. Numerical examples are presented in the paper to demonstrate the capability of the model.

  10. Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors

    NASA Astrophysics Data System (ADS)

    Bo, Gan; Tingcun, Wei; Wu, Gao; Yongcai, Hu

    2016-06-01

    In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 × 2.2 mm2. The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows: the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e‑ at zero farad plus 8.2 e‑ per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source 241Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si). Project supported by the National Key Scientific Instrument and Equipment Development Project (No. 2011YQ040082), the National Natural Science Foundation of China (Nos. 11475136, 11575144, 61176094), and the Shaanxi Natural Science Foundation of China (No. 2015JM1016).

  11. A 58 nW ECG ASIC With Motion-Tolerant Heartbeat Timing Extraction for Wearable Cardiovascular Monitoring.

    PubMed

    Da He, David; Sodini, Charles G

    2015-06-01

    An ASIC for wearable cardiovascular monitoring is implemented using a topology that takes advantage of the electrocardiogram's (ECG) waveform to replace the traditional ECG instrumentation amplifier, ADC, and signal processor with a single chip solution. The ASIC can extract heartbeat timings in the presence of baseline drift, muscle artifact, and signal clipping. The circuit can operate with ECGs ranging from the chest location to remote locations where the ECG magnitude is as low as 30 μV. Besides heartbeat detection, a midpoint estimation method can accurately extract the ECG R-wave timing, enabling the calculations of heart rate variability. With 58 nW of power consumption at 0.8 V supply voltage and 0.76 mm (2) of active die area in standard 0.18 μm CMOS technology, the ECG ASIC is sufficiently low power and compact to be suitable for long term and wearable cardiovascular monitoring applications under stringent battery and size constraints. PMID:25252285

  12. Millimeter-wave and optoelectronic applications of heterostructure integrated circuits

    NASA Technical Reports Server (NTRS)

    Pavlidis, Dimitris

    1991-01-01

    The properties are reviewed of heterostructure devices for microwave-monolithic-integrated circuits (MMICs) and optoelectronic integrated circuits (OICs). Specific devices examined include lattice-matched and pseudomorphic InAlAs/InGaAs high-electron mobility transistors (HEMTs), mixer/multiplier diodes, and heterojunction bipolar transistors (HBTs) developed with a number of materials. MMICs are reviewed that can be employed for amplification, mixing, and signal generation, and receiver/transmitter applications are set forth for OICs based on GaAs and InP heterostructure designs. HEMTs, HBTs, and junction-FETs can be utilized in combination with PIN, MSM, and laser diodes to develop novel communication systems based on technologies that combine microwave and photonic capabilities.

  13. Millimeter wave planar integrated circuit developments for communication applications

    NASA Astrophysics Data System (ADS)

    Chang, K.; Sun, C.

    Millimeter wave communication systems offer certain advantages over lower frequency systems. These advantages are related to wider bandwidth, larger data handling capacity, covert operation, and better immunity to jamming. Newer developments in the area of component technology for systems operating at millimeter wavelengths have utilized planar integrated circuits. Such circuits provide benefits of light weight, small size, and inherent low cost due to ease of high volume manufacturing. The present paper is concerned with a number of key IC components which have been developed. These components are ideally suited for direct application in advanced tactical, radar, and satellite communication systems. Attention is given to a rat-race microstrip balanced mixer, a crossbar stripline balanced mixer, and various subsystems developments.

  14. KLauS: an ASIC for silicon photomultiplier readout and its application in a setup for production testing of scintillating tiles

    NASA Astrophysics Data System (ADS)

    Briggl, K.; Dorn, M.; Hagdorn, R.; Harion, T.; Schultz-Coulon, H. C.; Shen, W.

    2014-02-01

    KLauS is an ASIC produced in the AMS 0.35 μm SiGe process to read out the charge signals from silicon photomultipliers. Developed as an analog front-end for future calorimeters with high granularity as pursued by the AHCAL concept in the CALICE collaboration, the ASIC is designed to measure the charge signal of the sensors in a large dynamic range and with low electronic noise contributions. In order to tune the operation voltage of each sensor individually, an 8-bit DAC to tune the voltage at the input terminal within a range of 2V is implemented. Using an integrated fast comparator with low jitter, the time information can be measured with sub-nanosecond resolution. The low power consumption of the ASIC can be further decreased using power gating techniques. Future versions of KLauS are under development and will incorporate an ADC with a resolution of up to 12-bits and blocks for digital data transmission. The chip is used in a setup for mass testing and characterization of scintillator tiles for the AHCAL test beam program.

  15. Digital circuits using universal logic gates

    NASA Technical Reports Server (NTRS)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)

    2004-01-01

    According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

  16. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    SciTech Connect

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  17. Integral Battery Power Limiting Circuit for Intrinsically Safe Applications

    NASA Technical Reports Server (NTRS)

    Burns, Bradley M.; Blalock, Norman N.

    2010-01-01

    A circuit topology has been designed to guarantee the output of intrinsically safe power for the operation of electrical devices in a hazardous environment. This design uses a MOSFET (metal oxide semiconductor field-effect transistor) as a switch to connect and disconnect power to a load. A test current is provided through a separate path to the load for monitoring by a comparator against a preset threshold level. The circuit is configured so that the test current will detect a fault in the load and open the switch before the main current can respond. The main current passes through the switch and then an inductor. When a fault occurs in the load, the current through the inductor cannot change immediately, but the voltage drops immediately to safe levels. The comparator detects this drop and opens the switch before the current in the inductor has a chance to respond. This circuit protects both the current and voltage from exceeding safe levels. Typically, this type of protection is accomplished by a fuse or a circuit breaker, but in order for a fuse or a circuit breaker to blow or trip, the current must exceed the safe levels momentarily, which may be just enough time to ignite anything in a hazardous environment. To prevent this from happening, a fuse is typically current-limited by the addition of the resistor to keep the current within safe levels while the fuse reacts. The use of a resistor is acceptable for non-battery applications where the wasted energy and voltage drop across the resistor can be tolerated. The use of the switch and inductor minimizes the wasted energy. For example, a circuit runs from a 3.6-V battery that must be current-limited to 200 mA. If the circuit normally draws 10 mA, then an 18-ohm resistor would drop 180 mV during normal operation, while a typical switch (0.02 ohm) and inductor (0.97 ohm) would only drop 9.9 mV. From a power standpoint, the current-limiting resistor protection circuit wastes about 18 times more power than the

  18. Delay locked loop integrated circuit.

    SciTech Connect

    Brocato, Robert Wesley

    2007-10-01

    This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed and fabricated in the IBM 8RF process, a 0.13 {micro}m CMOS process. It was designed to operate with a 300MHz clock and has been tested up to 500MHz.

  19. The use of hybrid integrated circuit techniques in biotelemetry applications

    NASA Technical Reports Server (NTRS)

    Fryer, T. B.

    1977-01-01

    A review is presented of some features of hybrid integrated circuits that make their use advantageous in miniature biotelemetry applications. The various techniques for fabricating resistors, capacitors and interconnections by both thin film and thick film technology are discussed. The use of chip capacitors, resistors, and especially standard IC chips on substrates with fired-on interconnection patterns is emphasized. The review is designed primarily to acquaint biotelemetry users and designers with an overview of this fabrication technique so that they can better communicate their needs with an understanding of its limitations and advantages to facilities specializing in hybrid construction.

  20. 3D probe array integrated with a front-end 100-channel neural recording ASIC

    NASA Astrophysics Data System (ADS)

    Cheng, Ming-Yuan; Yao, Lei; Tan, Kwan Ling; Lim, Ruiqi; Li, Peng; Chen, Weiguo

    2014-12-01

    Brain-machine interface technology can improve the lives of spinal cord injury victims and amputees. A neural interface system, consisting of a 3D probe array and a custom low-power (1 mW) 100-channel (100-ch) neural recording application-specific integrated circuit (ASIC), was designed and implemented to monitor neural activity. In this study, a microassembly 3D probe array method using a novel lead transfer technique was proposed to overcome the bonding plane mismatch encountered during orthogonal assembly. The proposed lead transfer technique can be completed using standard micromachining and packaging processes. The ASIC can be stacking-integrated with the probe array, minimizing the form factor of the assembled module. To minimize trauma to brain cells, the profile of the integrated probe array was controlled within 730 μm. The average impedance of the assembled probe was approximately 0.55 MΩ at 1 kHz. To verify the functionality of the integrated neural probe array, bench-top signal acquisitions were performed and discussed.

  1. Driving a CCD with two ASICs: CABAC and ASPIC

    NASA Astrophysics Data System (ADS)

    Juramy, Claire; Antilogus, Pierre; Bailly, Philippe; Baumont, Sylvain; Dhellot, Marc; El Berni, Mowafak; Jeglot, Jimmy; Lebbolo, Hervé; Martin, David; Qureshi, Aftab; Russo, Stefano; Terront, Diego; Tocut, Vanessa; Vallerand, Philippe

    2014-07-01

    We present two lines of ASICs dedicated to the control and readout of CCD sensors. The CABAC (Clocks And Biases ASIC for CCDs) provides all required bias voltages and clocks. The ASPIC (Analog Signal Processing Integrated Circuit) processes 8 CCD output channels: amplification, Correlated Double Sampling, conversion to differential signal. Both chips are highly configurable in order to fulfill a wide range of astronomical CCD readout needs, from fast readout of wide-field imaging arrays to slower speeds and higher gains for spectroscopy. Their sizes and temperature ranges allow to integrate them in-cryostat, close to the sensors, and they offer diagnostic capabilities to assist the integration. In addition to extensive stand-alone tests, these chips are integrated in the LSST REB (Raft Electronics Board), and have been tested driving the E2V prototype CCD for the LSST focal plane.

  2. Data encryption standard ASIC design and development report.

    SciTech Connect

    Robertson, Perry J.; Pierson, Lyndon George; Witzke, Edward L.

    2003-10-01

    This document describes the design, fabrication, and testing of the SNL Data Encryption Standard (DES) ASIC. This device was fabricated in Sandia's Microelectronics Development Laboratory using 0.6 {micro}m CMOS technology. The SNL DES ASIC was modeled using VHDL, then simulated, and synthesized using Synopsys, Inc. software and finally IC layout was performed using Compass Design Automation's CAE tools. IC testing was performed by Sandia's Microelectronic Validation Department using a HP 82000 computer aided test system. The device is a single integrated circuit, pipelined realization of DES encryption and decryption capable of throughputs greater than 6.5 Gb/s. Several enhancements accommodate ATM or IP network operation and performance scaling. This design is the latest step in the evolution of DES modules.

  3. Single event upset test structures for digital CMOS application specific integrated circuits

    SciTech Connect

    Baze, M.P.; Bartholet, W.G.; Braatz, J.C.; Dao, T.A. )

    1993-12-01

    An approach has been developed for the design and utilization of SEU test structures for digital CMOS ASICs. This approach minimizes the number of test structures required by categorizing ASIC library cells according to their SEU response and designing a structure to characterize each response for each category. Critical SEU response parameters extracted from these structures are used to evaluate the SEU hardness of ASIC libraries and predict the hardness of ASIC chips.

  4. Capturing a failure of an ASIC in-situ, using infrared radiometry and image processing software

    NASA Technical Reports Server (NTRS)

    Ruiz, Ronald P.

    2003-01-01

    Failures in electronic devices can sometimes be tricky to locate-especially if they are buried inside radiation-shielded containers designed to work in outer space. Such was the case with a malfunctioning ASIC (Application Specific Integrated Circuit) that was drawing excessive power at a specific temperature during temperature cycle testing. To analyze the failure, infrared radiometry (thermography) was used in combination with image processing software to locate precisely where the power was being dissipated at the moment the failure took place. The IR imaging software was used to make the image of the target and background, appear as unity. As testing proceeded and the failure mode was reached, temperature changes revealed the precise location of the fault. The results gave the design engineers the information they needed to fix the problem. This paper describes the techniques and equipment used to accomplish this failure analysis.

  5. VEGA: A low-power front-end ASIC for large area multi-linear X-ray silicon drift detectors: Design and experimental characterization

    NASA Astrophysics Data System (ADS)

    Ahangarianabhari, Mahdi; Macera, Daniele; Bertuccio, Giuseppe; Malcovati, Piero; Grassi, Marco

    2015-01-01

    We present the design and the first experimental characterization of VEGA, an Application Specific Integrated Circuit (ASIC) designed to read out large area monolithic linear Silicon Drift Detectors (SDD's). VEGA consists of an analog and a digital/mixed-signal section to accomplish all the functionalities and specifications required for high resolution X-ray spectroscopy in the energy range between 500 eV and 50 keV. The analog section includes a charge sensitive preamplifier, a shaper with 3-bit digitally selectable shaping times from 1.6 μs to 6.6 μs and a peak stretcher/sample-and-hold stage. The digital/mixed-signal section includes an amplitude discriminator with coarse and fine threshold level setting, a peak discriminator and a logic circuit to fulfill pile-up rejection, signal sampling, trigger generation, channel reset and the preamplifier and discriminators disabling functionalities. A Serial Peripherical Interface (SPI) is integrated in VEGA for loading and storing all configuration parameters in an internal register within few microseconds. The VEGA ASIC has been designed and manufactured in 0.35 μm CMOS mixed-signal technology in single and 32 channel versions with dimensions of 200 μm×500 μm per channel. A minimum intrinsic Equivalent Noise Charge (ENC) of 12 electrons r.m.s. at 3.6 μs peaking time and room temperature is measured and the linearity error is between -0.9% and +0.6% in the whole input energy range. The total power consumption is 481 μW and 420 μW per channel for the single and 32 channels version, respectively. A comparison with other ASICs for X-ray SDD's shows that VEGA has a suitable low noise and offers high functionality as ADC-ready signal processing but at a power consumption that is a factor of four lower than other similar existing ASICs.

  6. NMDAR-Mediated Hippocampal Neuronal Death is Exacerbated by Activities of ASIC1a

    PubMed Central

    Gao, Su; Yu, Yang; Ma, Zhi-Yuan; Sun, Hui; Zhang, Yong-Li; Wang, Xing-Tao; Wang, Chaoyun; Fan, Wei-Ming; Zheng, Qing-Yin

    2015-01-01

    NMDARs and ASIC1a both exist in central synapses and mediate important physiological and pathological conditions, but the functional relationship between them is unclear. Here we report several novel findings that may shed light on the functional relationship between these two ion channels in the excitatory postsynaptic membrane of mouse hippocampus. Firstly, NMDAR activation induced by either NMDA or OGD led to increased [Ca2+]i and greater apoptotic and necrotic cell deaths in cultured hippocampal neurons; these cell deaths were prevented by application of NMDAR antagonists. Secondly, ASIC1a activation induced by pH 6.0 extracellular solution (ECS) showed similar increases in apoptotic and necrotic cell deaths; these cell deaths were prevented by ASIC1a antagonists, and also by NMDAR antagonists. Since increased [Ca2+]i leads to increased cell deaths and since NMDAR exhibits much greater calcium permeability than ASIC1a, these data suggest that ASIC1a-induced neuronal death is mediated through activation of NMDARs. Thirdly, treatment of hippocampal cultures with both NMDA and acidic ECS induced greater degrees of cell deaths than either NMDA or acidic ECS treatment alone. These results suggest that ASIC1a activation up-regulates NMDAR function. Additional data supporting the functional relationship between ASIC1a and NMDAR are found in our electrophysiology experiments in hippocampal slices, where stimulation of ASIC1a induced a marked increase in NMDAR EPSC amplitude, and inhibition of ASIC1a resulted in a decrease in NMDAR EPSC amplitude. In summary, we present evidence that ASIC1a activity facilitates NMDAR function and exacerbates NMDAR-mediated neuronal death in pathological conditions. These findings are invaluable to the search for novel therapeutic targets in the treatment of brain ischemia. PMID:25947342

  7. A Prototype PZT Matrix Transducer With Low-Power Integrated Receive ASIC for 3-D Transesophageal Echocardiography.

    PubMed

    Chen, Chao; Raghunathan, Shreyas B; Yu, Zili; Shabanimotlagh, Maysam; Chen, Zhao; Chang, Zu-yao; Blaak, Sandra; Prins, Christian; Ponte, Jacco; Noothout, Emile; Vos, Hendrik J; Bosch, Johan G; Verweij, Martin D; de Jong, Nico; Pertijs, Michiel A P

    2016-01-01

    This paper presents the design, fabrication, and experimental evaluation of a prototype lead zirconium titanate (PZT) matrix transducer with an integrated receive ASIC, as a proof of concept for a miniature three-dimensional (3-D) transesophageal echocardiography (TEE) probe. It consists of an array of 9 ×12 piezoelectric elements mounted on the ASIC via an integration scheme that involves direct electrical connections between a bond-pad array on the ASIC and the transducer elements. The ASIC addresses the critical challenge of reducing cable count, and includes front-end amplifiers with adjustable gains and micro-beamformer circuits that locally process and combine echo signals received by the elements of each 3 ×3 subarray. Thus, an order-of-magnitude reduction in the number of receive channels is achieved. Dedicated circuit techniques are employed to meet the strict space and power constraints of TEE probes. The ASIC has been fabricated in a standard 0.18-μm CMOS process and consumes only 0.44 mW/channel. The prototype has been acoustically characterized in a water tank. The ASIC allows the array to be presteered across ±37° while achieving an overall dynamic range of 77 dB. Both the measured characteristics of the individual transducer elements and the performance of the ASIC are in good agreement with expectations, demonstrating the effectiveness of the proposed techniques. PMID:26540683

  8. Advanced polymer systems for optoelectronic integrated circuit applications

    NASA Astrophysics Data System (ADS)

    Eldada, Louay A.; Stengel, Kelly M. T.; Shacklette, Lawrence W.; Norwood, Robert A.; Xu, Chengzeng; Wu, Chengjiu; Yardley, James T.

    1997-01-01

    An advanced versatile low-cost polymeric waveguide technology is proposed for optoelectronic integrated circuit applications. We have developed high-performance organic polymeric materials that can be readily made into both multimode and single-mode optical waveguide structures of controlled numerical aperture (NA) and geometry. These materials are formed from highly crosslinked acrylate monomers with specific linkages that determine properties such as flexibility, toughness, loss, and stability against yellowing and humidity. These monomers are intermiscible, providing for precise adjustment of the refractive index from 1.30 to 1.60. Waveguides are formed photolithographically, with the liquid monomer mixture polymerizing upon illumination in the UV via either mask exposure or laser direct-writing. A wide range of rigid and flexible substrates can be used, including glass, quartz, oxidized silicon, glass-filled epoxy printed circuit board substrate, and flexible polyimide film. We discuss the use of these materials on chips and on multi-chip modules (MCMs), specifically in transceivers where we adaptively produced waveguides on vertical-cavity surface-emitting lasers (VCSELs) embedded in transmitter MCMs and on high- speed photodetector chips in receiver MCMs. Light coupling from and to chips is achieved by cutting 45 degree mirrors using excimer laser ablation. The fabrication of our polymeric structures directly on the modules provides for stability, ruggedness, and hermeticity in packaging.

  9. Laser applications in integrated circuits and photonics packaging

    NASA Astrophysics Data System (ADS)

    Lu, Yong Feng; Li, L. P.; Mendu, K.; Shi, J.

    2004-07-01

    Laser processing has large potential in the packaging of integrated circuits (IC). It can be used in many applications such as laser cleaning of IC mold tools, laser deflash to remove mold flash from heat sinks and lead wires of IC packages, laser singulation of BGA (ball grid array) and CSP (chip scale packages), laser reflow of solder ball on GBA, laser peeling for CSP, laser marking on packages and on Si wafers. Laser nanoimprinting of self-assembled nanoparticles has been recently developed to fabricate hemispherical cavity arrays on semiconductor surfaces. This process has the potential applications in fabrication and packaging of photonic devices such as waveguides and optical interconnections. During the implementation of all these applications, laser parameters, material issues, throughput, yield, reliability and monitoring techniques have to be taken into account. Monitoring of laser-induced plasma and laser induced acoustic wave has been used to understand and to control the processes involved in these applications. Numerical simulations can provide useful information on process analysis and optimization.

  10. Acid-Sensing Ion Channel 2a (ASIC2a) Promotes Surface Trafficking of ASIC2b via Heteromeric Assembly

    PubMed Central

    Kweon, Hae-Jin; Kim, Dong-Il; Bae, Yeonju; Park, Jae-Yong; Suh, Byung-Chang

    2016-01-01

    Acid-sensing ion channels (ASICs) are proton-activated cation channels that play important roles as typical proton sensors during pathophysiological conditions and normal synaptic activities. Among the ASIC subunits, ASIC2a and ASIC2b are alternative splicing products from the same gene, ACCN1. It has been shown that ASIC2 isoforms have differential subcellular distribution: ASIC2a targets the cell surface by itself, while ASIC2b resides in the ER. However, the underlying mechanism for this differential subcellular localization remained to be further elucidated. By constructing ASIC2 chimeras, we found that the first transmembrane (TM1) domain and the proximal post-TM1 domain (17 amino acids) of ASIC2a are critical for membrane targeting of the proteins. We also observed that replacement of corresponding residues in ASIC2b by those of ASIC2a conferred proton-sensitivity as well as surface expression to ASIC2b. We finally confirmed that ASIC2b is delivered to the cell surface from the ER by forming heteromers with ASIC2a, and that the N-terminal region of ASIC2a is additionally required for the ASIC2a-dependent membrane targeting of ASIC2b. Together, our study supports an important role of ASIC2a in membrane targeting of ASIC2b. PMID:27477936

  11. Acid-Sensing Ion Channel 2a (ASIC2a) Promotes Surface Trafficking of ASIC2b via Heteromeric Assembly.

    PubMed

    Kweon, Hae-Jin; Kim, Dong-Il; Bae, Yeonju; Park, Jae-Yong; Suh, Byung-Chang

    2016-01-01

    Acid-sensing ion channels (ASICs) are proton-activated cation channels that play important roles as typical proton sensors during pathophysiological conditions and normal synaptic activities. Among the ASIC subunits, ASIC2a and ASIC2b are alternative splicing products from the same gene, ACCN1. It has been shown that ASIC2 isoforms have differential subcellular distribution: ASIC2a targets the cell surface by itself, while ASIC2b resides in the ER. However, the underlying mechanism for this differential subcellular localization remained to be further elucidated. By constructing ASIC2 chimeras, we found that the first transmembrane (TM1) domain and the proximal post-TM1 domain (17 amino acids) of ASIC2a are critical for membrane targeting of the proteins. We also observed that replacement of corresponding residues in ASIC2b by those of ASIC2a conferred proton-sensitivity as well as surface expression to ASIC2b. We finally confirmed that ASIC2b is delivered to the cell surface from the ER by forming heteromers with ASIC2a, and that the N-terminal region of ASIC2a is additionally required for the ASIC2a-dependent membrane targeting of ASIC2b. Together, our study supports an important role of ASIC2a in membrane targeting of ASIC2b. PMID:27477936

  12. Hybrid planar lightwave circuits for defense and aerospace applications

    NASA Astrophysics Data System (ADS)

    Zhang, Hua; Bidnyk, Serge; Yang, Shiquan; Balakrishnan, Ashok; Pearson, Matt; O'Keefe, Sean

    2010-04-01

    We present innovations in Planar Lightwave Circuits (PLCs) that make them ideally suited for use in advanced defense and aerospace applications. We discuss PLCs that contain no micro-optic components, no moving parts, pose no spark or fire hazard, are extremely small and lightweight, and are capable of transporting and processing a range of optical signals with exceptionally high performance. This PLC platform is designed for on-chip integration of active components such as lasers and detectors, along with transimpedance amplifiers and other electronics. These active components are hybridly integrated with our silica-on-silicon PLCs using fully-automated robotics and image recognition technology. This PLC approach has been successfully applied to the design and fabrication of multi-channel transceivers for aerospace applications. The chips contain hybrid DFB lasers and high-efficiency detectors, each capable of running over 10 Gb/s, with mixed digital and analog traffic multiplexed to a single optical fiber. This highlyintegrated functionality is combined onto a silicon chip smaller than 4 x 10 mm, weighing < 5 grams. These chip-based transceivers have been measured to withstand harsh g-forces, including sinusoidal vibrations with amplitude of 20 g acceleration, followed by mechanical shock of 500 g acceleration. The components operate over a wide range of temperatures, with no device failures after extreme temperature cycling through a range of > 125 degC, and more than 2,000 hours operating at 95 degC ambient air temperature. We believe that these recent advancements in planar lightwave circuits are poised to revolutionize optical communications and interconnects in the aerospace and defense industries.

  13. The read-out ASIC for the Space NUCLEON project

    NASA Astrophysics Data System (ADS)

    Atkin, E.; Voronin, A.; Karmanov, D.; Kudryashov, I.; Podorozhniy, D.; Shumikhin, V.

    2015-04-01

    This paper summarizes the design results for the read-out ASIC for the space NUCLEON project of the Russian Federal Space Agency ROSCOSMOS. The ASIC with a unique high dynamic range (1-40 000 mip) at low power consumption (< 1.5 mW per channel) has been developed. It allows to record signals of relativistic particles and nuclei with charges from Z = 1 up to Z > 50, generated by silicon detectors, having capacitances up to 100 pF. The chip structure includes 32 analog channels, each consisting of a charge sensitive amplifier (CSA) with a p-MOS input transistor (W = 8 mm, L = 0.5 μ m), a shaper (peaking time of 2 us) and a T&H circuit. The ASIC showed a 120 pC dynamic range at a SNR of 2.5 for the particles with minimal ionization energy (1 mip). The chip was fabricated by the 0.35 um CMOS process via Europractice and tested both at lab conditions and in the SPS beam at CERN.

  14. A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

    NASA Technical Reports Server (NTRS)

    Smith, Edwyn D.

    1991-01-01

    Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

  15. AMPLITUDE AND TIME MEASUREMENT ASIC WITH ANALOG DERANDOMIZATION.

    SciTech Connect

    O CONNOR,P.; DE GERONIMO,G.; KANDASAMY,A.

    2002-11-10

    We describe a new ASIC for accurate and efficient processing of high-rate pulse signals from highly segmented detectors. In contrast to conventional approaches, this circuit affords a dramatic reduction in data volume through the use of analog techniques (precision peak detectors and time-to-amplitude converters) together with fast arbitration and sequencing logic to concentrate the data before digitization. In operation the circuit functions like a data-driven analog first-in, first-out (FIFO) memory between the preamplifiers and the ADC. Peak amplitudes of pulses arriving at any one of the 32 inputs are sampled, stored, and queued for readout and digitization through a single output port. Hit timing, pulse risetime, and channel address are also available at the output. Prototype chips have been fabricated in 0.35 micron CMOS and tested. First results indicate proper functionality for pulses down to 30 ns peaking time and input rates up to 1.6 MHz/channel. Amplitude accuracy of the peak detect and hold circuit is 0.3% (absolute). TAC accuracy is within 0.3% of full scale. Power consumption is less than 2 mW/channel. Compared with conventional techniques such as track-and-hold and analog memory, this new ASIC will enable efficient pulse height measurement at 20 to 300 times higher rates.

  16. STAR cluster-finder ASIC

    SciTech Connect

    Botlo, M.; LeVine, M.J.; Scheetz, R.A.

    1997-12-31

    The STAR experiment reads out a TPC and an SVT (silicon vertex tracker), both of which require in-line pedestal subtraction, compression of ADC values from 10-bit to 8-bit, and location of time sequences representing responses to charged-particle tracks. The STAR cluster finder ASIC responds to all of these needs. Pedestal subtraction and compression are performed using lookup tables in attached RAM. We describe its design and implementation, as well as testing methodology and results of tests performed on foundry prototypes.

  17. Application of telecom planar lightwave circuits for homeland security sensing

    NASA Astrophysics Data System (ADS)

    Veldhuis, Gert J.; Elders, Job; van Weerden, Harm; Amersfoort, Martin

    2004-03-01

    Over the past decade, a massive effort has been made in the development of planar lightwave circuits (PLCs) for application in optical telecommunications. Major advances have been made, on both the technological and functional performance front. Highly sophisticated software tools that are used to tailor designs to required functional performance support these developments. In addition extensive know-how in the field of packaging, testing, and failure mode and effects analysis (FMEA) has been built up in the struggle for meeting the stringent Telcordia requirements that apply to telecom products. As an example, silica-on-silicon is now a mature technology available at several industrial foundries around the world, where, on the performance front, the arrayed-waveguide grating (AWG) has evolved into an off-the-shelf product. The field of optical chemical-biological (CB) sensors for homeland security application can greatly benefit from the advances as described above. In this paper we discuss the currently available technologies, device concepts, and modeling tools that have emerged from the telecommunications arena and that can effectively be applied to the field of homeland security. Using this profound telecom knowledge base, standard telecom components can readily be tailored for detecting CB agents. Designs for telecom components aim at complete isolation from the environment to exclude impact of environmental parameters on optical performance. For sensing applications, the optical path must be exposed to the measurand, in this area additional development is required beyond what has already been achieved in telecom development. We have tackled this problem, and are now in a position to apply standard telecom components for CB sensing. As an example, the application of an AWG as a refractometer is demonstrated, and its performance evaluated.

  18. 20 CFR 410.670c - Application of circuit court law.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 20 Employees' Benefits 2 2010-04-01 2010-04-01 false Application of circuit court law. 410.670c... court law. The procedures which follow apply to administrative determinations or decisions on claims involving the application of circuit court law. (a) The Administration will apply a holding in a...

  19. Practical applications of digital integrated circuits. Part 3: Practical sequential theory and synchronous circuits

    NASA Technical Reports Server (NTRS)

    1973-01-01

    Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Discussed here are synchronous binary UP counters, synchronous DOWN and UP/DOWN counters, integrated circuit counters, shift registers, sequential techniques, and designing sequential counting machines.

  20. BAE Systems Radiation Hardened SpaceWire ASIC and Roadmap

    NASA Technical Reports Server (NTRS)

    Berger, Richard; Milliser, Myrna; Kapcio, Paul; Stanley, Dan; Moser, David; Koehler, Jennifer; Rakow, Glenn; Schnurr, Richard

    2006-01-01

    An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS, technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASlC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a 4-port SpaceWire router with two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, -and a memory controller for additional external memory use. The SpaceWire ASlC is planned for use on both the Geostationary Operational Environmental Satellites (GOES)-R and the Lunar Reconnaissance Orbiter (LRO). Engineering parts have already been delivered to both programs. This paper discusses the SpaceWire protocol and those elements of it that have been built into the current SpaceWire reusable core. There are features within the core that go beyond the current standard that can be enabled or disabled by the user and these will be described. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be discussed. Optional configurations within user systems will be shown. The physical imp!ementation of the design will be described and test results from the hardware will be discussed. Finally, the BAE Systems roadmap for SpaceWire developments will be discussed, including some products already in design as well as longer term plans.

  1. Rethinking ASIC design with next generation lithography and process integration

    NASA Astrophysics Data System (ADS)

    Vaidyanathan, Kaushik; Liu, Renzhi; Liebmann, Lars; Lai, Kafai; Strojwas, Andrzej; Pileggi, Larry

    2013-03-01

    Given the deployment delays for EUV, several next generation lithography (NGL) options are being actively researched. Several cost-effective NGL solutions, such as self-aligned double patterning through sidewall image transfer (SIT) and directed self-assembly (DSA), in conjunction with process integration challenges, mandate grating-like pattern design. As part of the GRATEdd project, we have evaluated the design cost of grating-based design for ASICs (application specific ICs). Based on our observations we have engineered fundamental changes to the primary ASIC design components to make scaling affordable and useful in deeply scaled sub-20 nm technologies: unidirectional-M1 based standard cells, application-specific smart SRAM synthesis, and statistical and self-healing analog design.

  2. An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras

    SciTech Connect

    Bolotnikov, A. E. Ackley, K.; Camarda, G. S.; Cherches, C.; Cui, Y.; De Geronimo, G.; Fried, J.; Hossain, A.; Mahler, G.; Maritato, M.; Roy, U.; Salwen, C.; Vernon, E.; Yang, G.; James, R. B.; Hodges, D.; Lee, W.; Petryk, M.

    2015-07-15

    We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm{sup 3} detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays’ performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

  3. An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras.

    PubMed

    Bolotnikov, A E; Ackley, K; Camarda, G S; Cherches, C; Cui, Y; De Geronimo, G; Fried, J; Hodges, D; Hossain, A; Lee, W; Mahler, G; Maritato, M; Petryk, M; Roy, U; Salwen, C; Vernon, E; Yang, G; James, R B

    2015-07-01

    We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm(3) detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays' performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects. PMID:26233363

  4. An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras

    NASA Astrophysics Data System (ADS)

    Bolotnikov, A. E.; Ackley, K.; Camarda, G. S.; Cherches, C.; Cui, Y.; De Geronimo, G.; Fried, J.; Hodges, D.; Hossain, A.; Lee, W.; Mahler, G.; Maritato, M.; Petryk, M.; Roy, U.; Salwen, C.; Vernon, E.; Yang, G.; James, R. B.

    2015-07-01

    We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm3 detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays' performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

  5. Structure, function, and pharmacology of acid-sensing ion channels (ASICs): focus on ASIC1a

    PubMed Central

    Gründer, Stefan; Chen, Xuanmao

    2010-01-01

    Acid-sensing ion channels (ASICs) are H+-gated Na+ channels, which are present in most, if not all, neurons. The typical ASIC current is transient and is elicited by a rapid drop in the extracellular pH. In the human genome, four genes for ASICs are present: asic1 – 4. In this review, we will focus on ASIC1a, one of the key subunits in the central nervous system. We will describe the structure of this channel, a topic that has enormously profited from the recent elucidation of the first crystal structure of an ASIC. We will then relate the ASIC1 structure to current models of the gating mechanism of ASICs. Finally, we will review the pharmacology of ASIC1a. Advances in the pharmacological inhibition of individual ASIC currents have greatly contributed to our current knowledge of the functional roles of this channel in physiology, including learning, memory, and fear conditioning, and in pathophysiological states, including the neurodegeneration accompanying stroke, and axonal degeneration in autoimmune inflammation. PMID:21383888

  6. Science Enabling ASICs and FEEs for the JUICE and JEO Missions

    NASA Technical Reports Server (NTRS)

    Paschalidis, Nicholas; Sittler, Ed; Cooper, John; Christian, Eric; Moore, Tom

    2011-01-01

    A family of science enabling radiation hard Application Specific Integrated Circuits (ASICs), Front End Electronics (FEEs) and Event Processing Systems, with flight heritage on many NASA missions, is presented. These technologies play an important role in the miniaturization of instruments -and spacecraft systems- at the same time increasing performance and reducing power. The technologies target time of flight, position sensing, and energy measurements as well as standard housekeeping and telemetry functions for particle and fields instruments, but find applications in other instrument categories too. More specifically the technologies include: the TOF chip, 1D and 2D Delay Lines with MCP detectors, for high precision fast and low power time of flight and position sensing; the Energy chip for multichannel SSD readout with time over threshold and standard voltage read out for TDC and ADC digitization; Fast multi channel read out chip with commandable thresholds; the TRIO chip for multiplexed ADC and housekeeping etc. It should be mentioned that the ASICs include basic trigger capabilities to enable random event processing in a heavy background of penetrators and UV foreground. Typical instruments include time of flight versus energy and look angle particle analyzers such as: plasma composition, energetic particle, neutral atom imaging as well as fast plasma and deltaE/E ion/electron telescopes. Flight missions include: Cassini/LEMMS, IMAGE/HENA, MESSENGER/EPPS/MLA/X-ray/MLA, STEREO, PLUTO-NH/PEPSSI/LORI, IBEX-Lo, JUNO/JEDI, RBSP/RBSPICE, MMS/HPCA/EPD, SO/SIS. Given the proven capability on heavy radiation missions such as JUNO, MMS and RBSB, as well diverse long duration missions such as MESSENGER, PLUTO and Cassini, it is expected that these technologies will play an important role in the particle and fields (at least) instruments on the upcoming JUICE and JEO missions.

  7. Design and fabrication of an infrared optical pyrometer ASIC as a diagnostic for shock physics experiments

    NASA Astrophysics Data System (ADS)

    Gordon, Jared

    Optical pyrometry is the sensing of thermal radiation emitted from an object using a photoconductive device to convert photons into electrons, and is an important diagnostic tool in shock physics experiments. Data obtained from an optical pyrometer can be used to generate a blackbody curve of the material prior to and after being shocked by a high speed projectile. The sensing element consists of an InGaAs photodiode array, biasing circuitry, and multiple transimpedance amplifiers to boost the weak photocurrent from the noisy dark current into a signal that can eventually be digitized. Once the circuit elements have been defined, more often than not commercial-off-the-shelf (COTS) components are inadequate to satisfy every requirement for the diagnostic, and therefore a custom application specific design has to be considered. This thesis outlines the initial challenges with integrating the photodiode array block with multiple COTS transimpedance amplifiers onto a single chip, and offers a solution to a comparable optical pyrometer that uses the same type of photodiodes in conjunction with a re-designed transimpedance amplifier integrated onto a single chip. The final design includes a thorough analysis of the transimpedance amplifier along with modeling the circuit behavior which entails schematics, simulations, and layout. An alternative circuit is also investigated that incorporates an approach to multiplex the signals from each photodiode onto one data line and not only increases the viable real estate on the chip, but also improves the behavior of the photodiodes as they are subjected to less thermal load. The optical pyrometer application specific integrated circuit (ASIC) for shock physic experiments includes a transimpedance amplifier (TIA) with a 100 kΩ gain operating at bandwidth of 30 MHz, and an input-referred noise RMS current of 50 nA that is capable of driving a 50 Ω load.

  8. ASIC for high-speed-gating and free running operation of SPADs

    NASA Astrophysics Data System (ADS)

    Rochas, Alexis; Guillaume-Gentil, Christophe; Gautier, Jean-Daniel; Pauchard, Alexandre; Ribordy, Gregoire; Zbinden, Hugo; Leblebici, Yusuf; Monat, Laurent

    2007-05-01

    Single photon detection at telecom wavelengths is of importance in many industrial applications ranging from quantum cryptography, quantum optics, optical time domain reflectometry, non-invasive testing of VLSI circuits, eye-safe LIDAR to laser ranging. In practical applications, the combination of an InGaAs/InP APD with an appropriate electronic circuit still stands as the best solution in comparison with emerging technologies such as superconducting single photon detectors, MCP-PMTs for the near IR or up-conversion technique. An ASIC dedicated to the operation of InGaAs/InP APDs in both gated mode and free-running mode is presented. The 1.6mm2 chip is fabricated in a CMOS technology. It combines a gate generator, a voltage limiter, a fast comparator, a precise timing circuit for the gate signal processing and an output stage. A pulse amplitude of up to +7V can be achieved, which allows the operation of commercially available APDs at a single photon detection probability larger than 25% at 1.55μm. The avalanche quenching process is extremely fast, thus reducing the afterpulsing effects. The packaging of the diode in close proximity with the quenching circuit enables high speed gating at frequencies larger than 10MHz. The reduced connection lengths combined with impedance adaptation technique provide excellent gate quality, free of oscillations or bumps. The excess bias voltage is thus constant over the gate width leading to a stable single photon detection probability and timing resolution. The CMOS integration guarantees long-term stability, reliability and compactness.

  9. Short Circuit Analysis of Induction Machines Wind Power Application

    SciTech Connect

    Starke, Michael R; Smith, Travis M; Howard, Dustin; Harley, Ronald

    2012-01-01

    he short circuit behavior of Type I (fixed speed) wind turbine-generators is analyzed in this paper to aid in the protection coordination of wind plants of this type. A simple network consisting of one wind turbine-generator is analyzed for two network faults: a three phase short circuit and a phase A to ground fault. Electromagnetic transient simulations and sequence network calculations are compared for the two fault scenarios. It is found that traditional sequence network calculations give accurate results for the short circuit currents in the balanced fault case, but are inaccurate for the un-faulted phases in the unbalanced fault case. The time-current behavior of the fundamental frequency component of the short circuit currents for both fault cases are described, and found to differ significantly in the unbalanced and balanced fault cases

  10. Development of thermionic integrated circuits for applications in hostile environments

    SciTech Connect

    McCormik, J.B.; Lynn, D.K.; Wilde, D.; Cowan, R.; Hamilton, D.J.; Kerwin, W.; Dooley, R.

    1984-04-10

    This report describes a class of devices known as thermionic integrated circuits (TICs) that are capable of extended operation in ambient temperatures up to 500/sup 0/C and in high radiation environments. The evolution of the TIC concept is discussed. A set of practical design and performance equations is demonstrated. Recent experimental results are discussed in which both devices and simple circuits have successfully operated in 500/sup 0/C environments for extended periods of time.

  11. Development of integrated thermionic circuits for high-temperature applications

    SciTech Connect

    McCormick, J.B.; Wilde, D.; Depp, S.; Hamilton, D.J.; Kerwin, W.

    1981-01-01

    This report describes a class of microminiature, thin film devices known as integrated thermionic circuits (ITC) capable of extended operation in ambient temperatures up to 500/sup 0/C. The evolution of the ITC concept is discussed. A set of practical design and performance equations is demonstrated. Recent experimental results are discussed in which both devices and simple circuits have successfully operated in 500/sup 0/C environments for extended periods of time (greater than 11,000 hours).

  12. Design and Characteristics of a Multichannel Front-End ASIC Using Current-Mode CSA for Small-Animal PET Imaging.

    PubMed

    Ollivier-Henry, N; Wu Gao; Xiaochao Fang; Mbow, N A; Brasse, D; Humbert, B; Hu-Guo, C; Colledani, C; Yann Hu

    2011-02-01

    This paper presents the design and characteristics of a front-end readout application-specific integrated circuit (ASIC) dedicated to a multichannel-plate photodetector coupled to LYSO scintillating crystals. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. Both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. A current-mode charge-sensitive amplifier is proposed for this application. This paper presents performance characteristics of a 10-channel prototype chip designed and fabricated in a 0.35-μm complementary metal-oxide semiconductor process. The main results of simulations and measurements are presented and discussed. The gain of the chip is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The signal-to-noise ratio is 39 dB and the rms noise is 300 μV/√(Hz). The nonlinearity is less than 3% and the crosstalk is about 0.2%. The power dissipation is less than 15 mW/channel. This prototype will be extended to a 64-channel circuit with integrated time-to-digital converter and analog-to-digital converter together for a high-sensitive small-animal positron emission tomography imaging system. PMID:23850981

  13. High Rate Digital Demodulator ASIC

    NASA Technical Reports Server (NTRS)

    Ghuman, Parminder; Sheikh, Salman; Koubek, Steve; Hoy, Scott; Gray, Andrew

    1998-01-01

    The architecture of High Rate (600 Mega-bits per second) Digital Demodulator (HRDD) ASIC capable of demodulating BPSK and QPSK modulated data is presented in this paper. The advantages of all-digital processing include increased flexibility and reliability with reduced reproduction costs. Conventional serial digital processing would require high processing rates necessitating a hardware implementation in other than CMOS technology such as Gallium Arsenide (GaAs) which has high cost and power requirements. It is more desirable to use CMOS technology with its lower power requirements and higher gate density. However, digital demodulation of high data rates in CMOS requires parallel algorithms to process the sampled data at a rate lower than the data rate. The parallel processing algorithms described here were developed jointly by NASA's Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL). The resulting all-digital receiver has the capability to demodulate BPSK, QPSK, OQPSK, and DQPSK at data rates in excess of 300 Mega-bits per second (Mbps) per channel. This paper will provide an overview of the parallel architecture and features of the HRDR ASIC. In addition, this paper will provide an over-view of the implementation of the hardware architectures used to create flexibility over conventional high rate analog or hybrid receivers. This flexibility includes a wide range of data rates, modulation schemes, and operating environments. In conclusion it will be shown how this high rate digital demodulator can be used with an off-the-shelf A/D and a flexible analog front end, both of which are numerically computer controlled, to produce a very flexible, low cost high rate digital receiver.

  14. Y-Ba-Cu-O superconducting/GaAs semiconducting hybrid circuits for microwave applications

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Toncich, S. S.; Chorey, C. M.; Rohrer, N. J.; Valco, G. J.

    1993-01-01

    A two pole superconducting bandpass filter was combined with a packaged GaAs low noise amplifier, and a superconducting X-band oscillator was designed, fabricated, and tested. Both circuits were compared to normal metal circuits at 77K. The results of these experiments, technical issues, and potential applications are presented.

  15. Design and Application of a Circuit for Measuring Frequency and Duty Cycle of Stimulated Bioelectrical Signal

    NASA Astrophysics Data System (ADS)

    Tang, Li-Ming; Chang, Ben-Kang; Liu, Tie-Bing; Wu, Min; Ling, Gang

    2002-12-01

    To design a new type of circuit for measuring frequency & duty cycle of stimulated bioelectrical signal for the project of 'the map of neuron-threshold in human brain and its clinical application'. This circuit was designed according to the character of stimulated bioelectrical signals. It was tested and improved and then used in the neuron -threshold stimulator. The circuit was found to be very accurate for measuring frequency and the error for measuring duty cycle was below 0.2%. This circuit is well-designed, simple, easy to use, and can be applied in many systems.

  16. Applications of modularized circuit designs in a new hyper-chaotic system circuit implementation

    NASA Astrophysics Data System (ADS)

    Wang, Rui; Sun, Hui; Wang, Jie-Zhi; Wang, Lu; Wang, Yan-Chao

    2015-02-01

    Modularized circuit designs for chaotic systems are introduced in this paper. Especially, a typical improved modularized design strategy is proposed and applied to a new hyper-chaotic system circuit implementation. In this paper, the detailed design procedures are described. Multisim simulations and physical experiments are conducted, and the simulation results are compared with Matlab simulation results for different system parameter pairs. These results are consistent with each other and they verify the existence of the hyper-chaotic attractor for this new hyper-chaotic system. Project supported by the Young Scientists Fund of the National Natural Science Foundation of China (Grant No. 61403395), the Natural Science Foundation of Tianjin, China (Grant No. 13JCYBJC39000), the Scientific Research Foundation for the Returned Overseas Chinese Scholars, State Education Ministry of China, the Fund from the Tianjin Key Laboratory of Civil Aircraft Airworthiness and Maintenance in Civil Aviation of China (Grant No. 104003020106), the National Basic Research Program of China (Grant No. 2014CB744904), and the Fund for the Scholars of Civil Aviation University of China (Grant No. 2012QD21x).

  17. Micropower circuits for bidirectional wireless telemetry in neural recording applications.

    PubMed

    Neihart, Nathan M; Harrison, Reid R

    2005-11-01

    State-of-the art neural recording systems require electronics allowing for transcutaneous, bidirectional data transfer. As these circuits will be implanted near the brain, they must be small and low power. We have developed micropower integrated circuits for recovering clock and data signals over a transcutaneous power link. The data recovery circuit produces a digital data signal from an ac power waveform that has been amplitude modulated. We have also developed an FM transmitter with the lowest power dissipation reported for biosignal telemetry. The FM transmitter consists of a low-noise biopotential amplifier and a voltage controlled oscillator used to transmit amplified neural signals at a frequency near 433 MHz. All circuits were fabricated in a standard 0.5-microm CMOS VLSI process. The resulting chip is powered through a wireless inductive link. The power consumption of the clock and data recovery circuits is measured to be 129 microW; the power consumption of the transmitter is measured to be 465 microW when using an external surface mount inductor. Using a parasitic antenna less than 2 mm long, a received power level was measured to be -59.73 dBm at a distance of one meter. PMID:16285399

  18. Development of the analog ASIC for multi-channel readout X-ray CCD camera

    NASA Astrophysics Data System (ADS)

    Nakajima, Hiroshi; Matsuura, Daisuke; Idehara, Toshihiro; Anabuki, Naohisa; Tsunemi, Hiroshi; Doty, John P.; Ikeda, Hirokazu; Katayama, Haruyoshi; Kitamura, Hisashi; Uchihori, Yukio

    2011-03-01

    We report on the performance of an analog application-specific integrated circuit (ASIC) developed aiming for the front-end electronics of the X-ray CCD camera system onboard the next X-ray astronomical satellite, ASTRO-H. It has four identical channels that simultaneously process the CCD signals. Distinctive capability of analog-to-digital conversion enables us to construct a CCD camera body that outputs only digital signals. As the result of the front-end electronics test, it works properly with low input noise of ≤30μV at the pixel rate below 100 kHz. The power consumption is sufficiently low of ˜150mW/chip. The input signal range of ±20 mV covers the effective energy range of the typical X-ray photon counting CCD (up to 20 keV). The integrated non-linearity is 0.2% that is similar as those of the conventional CCDs in orbit. We also performed a radiation tolerance test against the total ionizing dose (TID) effect and the single event effect. The irradiation test using 60Co and proton beam showed that the ASIC has the sufficient tolerance against TID up to 200 krad, which absolutely exceeds the expected amount of dose during the period of operating in a low-inclination low-earth orbit. The irradiation of Fe ions with the fluence of 5.2×108 Ion/cm2 resulted in no single event latchup (SEL), although there were some possible single event upsets. The threshold against SEL is higher than 1.68 MeV cm2/mg, which is sufficiently high enough that the SEL event should not be one of major causes of instrument downtime in orbit.

  19. A 290 mV Sub-V(T) ASIC for Real-Time Atrial Fibrillation Detection.

    PubMed

    Andersson, Oskar; Chon, Ki H; Sornmo, Leif; Rodrigues, Joachim Neves

    2015-06-01

    A real-time detector for episodes of atrial fibrillation is fabricated as an application specific integrated circuit (ASIC). The basis for detection is a set of three parameters for characterizing the RR interval series, i.e., turning point ratio, root mean square of successive differences, and Shannon entropy. The developed hardware architecture targets ultra-low voltage operation, suitable for implantable loop recorders with ultra-low energy requirements. Algorithmic and architectural optimizations are performed to minimize area and energy dissipation, with a total area footprint reduction of 44%. The design is fabricated in 65-nm CMOS low-leakage high-threshold technology. Measurements with aggressively scaled supply voltage (VDD) in the subthreshold (sub-VT) region show energy savings of up to 41 X when operating at 1 kHz with a VDD of 300 mV compared to a nominal VDD of 1.2 V. PMID:25343767

  20. Genetic mapping of ASIC4 and contrasting phenotype to ASIC1a in modulating innate fear and anxiety.

    PubMed

    Lin, Shing-Hong; Chien, Ya-Chih; Chiang, Wei-Wei; Liu, Yan-Zhen; Lien, Cheng-Chang; Chen, Chih-Cheng

    2015-06-01

    Although ASIC4 is a member of the acid-sensing ion channel (ASIC) family, we have limited knowledge of its expression and physiological function in vivo. To trace the expression of this ion channel, we generated the ASIC4-knockout/CreERT(2)-knockin (Asic4(Cre) (ERT) (2)) mouse line. After tamoxifen induction in the Asic4(Cre) (ERT)(2)::CAG-STOP(floxed)-Td-tomato double transgenic mice, we mapped the expression of ASIC4 at the cellular level in the central nervous system (CNS). ASIC4 was expressed in many brain regions, including the olfactory bulb, cerebral cortex, striatum, hippocampus, amygdala, thalamus, hypothalamus, brain stem, cerebellum, spinal cord and pituitary gland. Colocalisation studies further revealed that ASIC4 was expressed mainly in three types of cells in the CNS: (i) calretinin (CR)-positive and/or vasoactive intestine peptide (VIP)-positive interneurons; (ii) neural/glial antigen 2 (NG2)-positive glia, also known as oligodendrocyte precursor cells; and (iii) cerebellar granule cells. To probe the possible role of ASIC4, we hypothesised that ASIC4 could modulate the membrane expression of ASIC1a and thus ASIC1a signaling in vivo. We conducted behavioral phenotyping of Asic4(Cre) (ERT)(2) mice by screening many of the known behavioral phenotypes found in Asic1a knockouts and found ASIC4 not involved in shock-evoked fear learning and memory, seizure termination or psychostimulant-induced locomotion/rewarding effects. In contrast, ASIC4 might play an important role in modulating the innate fear response to predator odor and anxious state because ASIC4-mutant mice showed increased freezing response to 2,4,5-trimethylthiazoline and elevated anxiety-like behavior in both the open-field and elevated-plus maze. ASIC4 may modulate fear and anxiety by counteracting ASIC1a activity in the brain. PMID:25828470

  1. Development of an ASIC for the readout and control of near-infrared large array detectors

    NASA Astrophysics Data System (ADS)

    Meier, Dirk; Berge, Hans Kristian Otnes; Hasanbegovic, Amir; Altan, Mehmet A.; Najafiuchevler, Bahram; Azman, Suleyman; Talebi, Jahanzad; Olsen, Alf; Øya, Petter; Paahlsson, Philip; Gheorghe, Codin; Maehlum, Gunnar

    2014-07-01

    The article describes the near infrared readout and controller ASIC (NIRCA) developed by Integrated Detector Electronics AS (IDEAS). The project aims at future astronomical science and Earth observation missions, where the ASIC will be used with image sensors based on mercury cadmium telluride (HgCdTe, or MCT). NIRCA is designed to operate from cryogenic temperatures (77 K) to higher than room temperature (328 K) and in a high radiation environment (LET > 60 MeVcm2/mg). The ASIC connects to the readout integrated circuit (ROIC) and delivers fully digitized data via serial digital output. The ASIC contains an analogue front-end (AFE) with 4 analogue-to-digital converters (ADCs) and programmable gain amplifiers with offset adjustment. The ADCs have a differential input swing of +/-2 V, 12-bit resolution, and a maximum sample rate of 3 MSps. The ASIC contains a programmable sequencer (microcontroller) to generate up to 40 digital signals for the ROIC and to control the analogue front-end and DACs on the chip. The ASIC has two power supply voltage regulators that provide the ROIC with 1.8 V and 3.3 V, and programmable 10-bit DACs to generate 16 independent reference and bias voltages from 0.3 V to 3 V. In addition NIRCA allows one to read 8 external digital signals, and monitor external and internal analogue signals including onchip temperature. NIRCA can be programmed and controlled via SPI interface for all internal functions and allows data forwarding from and to the ROIC SPI interface.

  2. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    NASA Technical Reports Server (NTRS)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    1987-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  3. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    NASA Technical Reports Server (NTRS)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    1987-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMICs to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMICs is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  4. Packaging printed circuit boards: A production application of interactive graphics

    NASA Technical Reports Server (NTRS)

    Perrill, W. A.

    1975-01-01

    The structure and use of an Interactive Graphics Packaging Program (IGPP), conceived to apply computer graphics to the design of packaging electronic circuits onto printed circuit boards (PCB), were described. The intent was to combine the data storage and manipulative power of the computer with the imaginative, intuitive power of a human designer. The hardware includes a CDC 6400 computer and two CDC 777 terminals with CRT screens, light pens, and keyboards. The program is written in FORTRAN 4 extended with the exception of a few functions coded in COMPASS (assembly language). The IGPP performs four major functions for the designer: (1) data input and display, (2) component placement (automatic or manual), (3) conductor path routing (automatic or manual), and (4) data output. The most complex PCB packaged to date measured 16.5 cm by 19 cm and contained 380 components, two layers of ground planes and four layers of conductors mixed with ground planes.

  5. A CMOS ASIC Design for SiPM Arrays.

    PubMed

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2011-12-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

  6. Electrical Devices and Circuits for Low Temperature Space Applications

    NASA Technical Reports Server (NTRS)

    Patterson, R. L.; Hammond, A.; Dickman, J. E.; Gerber, S.; Overton, E.; Elbuluk, M.

    2003-01-01

    The environmental temperature in many NASA missions, such as deep space probes and outer planetary exploration, is significantly below the range for which conventional commercial-off-the-shelf electronics is designed. Presently, spacecraft operating in the cold environment of such deep space missions carry a large number of radioisotope or other heating units in order to maintain the surrounding temperature of the on-board electronics at approximately 20 C. Electronic devices and circuits capable of operation at cryogenic temperatures will not only tolerate the harsh environment of deep space but also will reduce system size and weight by eliminating or reducing the heating units and their associate structures; thereby reducing system development cost as well as launch costs. In addition, power electronic circuits designed for operation at low temperatures are expected to result in more efficient systems than those at room temperature. This improvement results from better behavior in the electrical and thermal properties of some semiconductor and dielectric materials at low temperatures. An on-going research and development program on low temperature electronics at the NASA Glenn Research Center focuses on the development of efficient electrical systems and circuits capable of surviving and exploiting the advantages of low temperature environments. An overview of the program will be presented in this paper. A description of the low temperature test facilities along with selected data obtained from in-house component testing will also be discussed. On-going research activities that are being performed in collaboration with various organizations will also be presented.

  7. σ-1 Receptor Inhibition of ASIC1a Channels is Dependent on a Pertussis Toxin-Sensitive G-Protein and an AKAP150/Calcineurin Complex.

    PubMed

    Mari, Yelenis; Katnik, Christopher; Cuevas, Javier

    2015-10-01

    ASIC1a channels play a major role in various pathophysiological conditions including depression, anxiety, epilepsy, and neurodegeneration following ischemic stroke. Sigma-1 (σ-1) receptor stimulation depresses the activity of ASIC1a channels in cortical neurons, but the mechanism(s) by which σ-1 receptors exert their influence on ASIC1a remains unknown. Experiments were undertaken to elucidate the signaling cascade linking σ-1 receptors to ASIC1a channels. Immunohistochemical studies showed that σ-1 receptors, ASIC1a and A-kinase anchoring peptide 150 colocalize in the plasma membrane of the cell body and processes of cortical neurons. Fluorometric Ca(2+) imaging experiments showed that disruption of the macromolecular complexes containing AKAP150 diminished the effects of the σ-1 on ASIC1a, as did application of the calcineurin inhibitors, cyclosporin A and FK-506. Moreover, whole-cell patch clamp experiments showed that σ-1 receptors were less effective at decreasing ASIC1a-mediated currents in the presence of the VIVIT peptide, which binds to calcineurin and prevents cellular effects dependent on AKAP150/calcineurin interaction. The coupling of σ-1 to ASIC1a was also disrupted by preincubation of the neurons in the G-protein inhibitor, pertussis toxin (PTX). Taken together, our data reveal that σ-1 receptor block of ASIC1a function is dependent on activation of a PTX-sensitive G-protein and stimulation of AKAP150 bound calcineurin. PMID:24925261

  8. Circuit for Communication Over Power Lines

    NASA Technical Reports Server (NTRS)

    Krasowski, Michael J.; Prokop, Normal F.; Greer, Lawrence C., III; Nappier, Jennifer

    2011-01-01

    Many distributed systems share common sensors and instruments along with a common power line supplying current to the system. A communication technique and circuit has been developed that allows for the simple inclusion of an instrument, sensor, or actuator node within any system containing a common power bus. Wherever power is available, a node can be added, which can then draw power for itself, its associated sensors, and actuators from the power bus all while communicating with other nodes on the power bus. The technique modulates a DC power bus through capacitive coupling using on-off keying (OOK), and receives and demodulates the signal from the DC power bus through the same capacitive coupling. The circuit acts as serial modem for the physical power line communication. The circuit and technique can be made of commercially available components or included in an application specific integrated circuit (ASIC) design, which allows for the circuit to be included in current designs with additional circuitry or embedded into new designs. This device and technique moves computational, sensing, and actuation abilities closer to the source, and allows for the networking of multiple similar nodes to each other and to a central processor. This technique also allows for reconfigurable systems by adding or removing nodes at any time. It can do so using nothing more than the in situ power wiring of the system.

  9. Regulation of ASIC activity by ASIC4--new insights into ASIC channel function revealed by a yeast two-hybrid assay.

    PubMed

    Donier, Emmanuelle; Rugiero, François; Jacob, Céline; Wood, John N

    2008-07-01

    ASIC4 is a member of the acid-sensing ion channel family that is broadly expressed in the mammalian nervous system, but has no known function. We demonstrate here that transfected ASIC4 is targeted to the plasma membrane in CHO-K1 cells, where it associates with ASIC1a and downregulates exogenous ASIC1a expression. This effect could also be observed on endogenous H+-gated currents in TSA-201 cells and ASIC3 currents in CHO-K1 cells, suggesting a physiological role for ASIC4 in regulating ASIC currents involved in pain mechanisms. Using a yeast two-hybrid assay we found that ASICs interact with proteins involved in diverse functions, including cytoskeletal proteins, enzymes, regulators of endocytosis and G-protein-coupled pathways. ASIC4 is the sole member of this ion channel class to interact strongly with polyubiquitin. The distinct functionally related sets of interacting proteins that bind individual ASICs identified in the yeast two-hybrid screen suggest potential roles for ASICs in a variety of cellular functions. PMID:18662336

  10. ASICs as therapeutic targets for migraine.

    PubMed

    Dussor, Greg

    2015-07-01

    Migraine is the most common neurological disorder and one of the most common chronic pain conditions. Despite its prevalence, the pathophysiology leading to migraine is poorly understood and the identification of new therapeutic targets has been slow. Several processes are currently thought to contribute to migraine including altered activity in the hypothalamus, cortical-spreading depression (CSD), and afferent sensory input from the cranial meninges. Decreased extracellular pH and subsequent activation of acid-sensing ion channels (ASICs) may contribute to each of these processes and may thus play a role in migraine pathophysiology. Although few studies have directly examined a role of ASICs in migraine, studies directly examining a connection have generated promising results including efficacy of ASIC blockers in both preclinical migraine models and in human migraine patients. The purpose of this review is to discuss the pathophysiology thought to contribute to migraine and findings that implicate decreased pH and/or ASICs in these events, as well as propose issues to be resolved in future studies of ASICs and migraine. This article is part of the Special Issue entitled 'Acid-Sensing Ion Channels in the Nervous System'. PMID:25582295

  11. ASICs as therapeutic targets for migraine

    PubMed Central

    2015-01-01

    Migraine is the most common neurological disorder and one of the most common chronic pain conditions. Despite its prevalence, the pathophysiology leading to migraine is poorly understood and the identification of new therapeutic targets has been slow. Several processes are currently thought to contribute to migraine including altered activity in the hypothalamus, cortical-spreading depression (CSD), and afferent sensory input from the cranial meninges. Decreased extracellular pH and subsequent activation of acid-sensing ion channels (ASICs) may contribute to each of these processes and may thus play a role in migraine pathophysiology. Although few studies have directly examined a role of ASICs in migraine, studies directly examining a connection have generated promising results including efficacy of ASIC blockers in both preclinical migraine models and in human migraine patients. The purpose of this review is to discuss the pathophysiology thought to contribute to migraine and findings that implicate decreased pH and/or ASICs in these events, as well as propose issues to be resolved in future studies of ASICs and migraine. PMID:25582295

  12. A DSP implementation of lifting based DWT for image processing applications

    NASA Astrophysics Data System (ADS)

    Gholipour, Morteza; Noubari, Hossein A.; Kamarei, Mahmoud

    2011-10-01

    Discrete Wavelet Transform (DWT) is widely used in signal processing applications. In this paper, we describe hardware implementation of a lifting-based DWT, which is used in image compression. The CDF(2,2) lifting-based wavelet transform is modeled and simulated using MATLAB. Based on DSP methodologies, the signal flow graph and dependence graph are derived. The dependence graph is optimized and used to implement the hardware description of the circuit in Verilog. We have synthesized and implemented the circuit using both Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) design approaches. To confirm the circuit operation, post-synthesis and post-layout simulations were done for FPGA and ASIC designs, respectively.

  13. High temperature superconducting thin film microwave circuits: Fabrication, characterization, and applications

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Warner, J. D.; Romanofsky, R. R.; Heinen, V. O.; Chorey, C. M.

    1990-01-01

    Epitaxial YBa2Cu3O7 films were grown on several microwave substrates. Surface resistance and penetration depth measurements were performed to determine the quality of these films. Here the properties of these films on key microwave substrates are described. The fabrication and characterization of a microwave ring resonator circuit to determine transmission line losses are presented. Lower losses than those observed in gold resonator circuits were observed at temperatures lower than critical transition temperature. Based on these results, potential applications of microwave superconducting circuits such as filters, resonators, oscillators, phase shifters, and antenna elements in space communication systems are identified.

  14. Small circuits for cryptography.

    SciTech Connect

    Torgerson, Mark Dolan; Draelos, Timothy John; Schroeppel, Richard Crabtree; Miller, Russell D.; Anderson, William Erik

    2005-10-01

    This report examines a number of hardware circuit design issues associated with implementing certain functions in FPGA and ASIC technologies. Here we show circuit designs for AES and SHA-1 that have an extremely small hardware footprint, yet show reasonably good performance characteristics as compared to the state of the art designs found in the literature. Our AES performance numbers are fueled by an optimized composite field S-box design for the Stratix chipset. Our SHA-1 designs use register packing and feedback functionalities of the Stratix LE, which reduce the logic element usage by as much as 72% as compared to other SHA-1 designs.

  15. Circuit-level simulation of transistor lasers and its application to modelling of microwave photonic links

    NASA Astrophysics Data System (ADS)

    Iezekiel, Stavros; Christou, Andreas

    2015-03-01

    Equivalent circuit models of a transistor laser are used to investigate the suitability of this relatively new device for analog microwave photonic links. The three-terminal nature of the device enables transistor-based circuit design techniques to be applied to optoelectronic transmitter design. To this end, we investigate the application of balanced microwave amplifier topologies in order to enable low-noise links to be realized with reduced intermodulation distortion and improved RF impedance matching compared to conventional microwave photonic links.

  16. Mixed application MMIC technologies - Progress in combining RF, digital and photonic circuits

    NASA Technical Reports Server (NTRS)

    Swirhun, S.; Bendett, M.; Sokolov, V.; Bauhahn, P.; Sullivan, C.; Mactaggart, R.; Mukherjee, S.; Hibbs-Brenner, M.; Mondal, J.

    1991-01-01

    Approaches for future 'mixed application' monolithic integrated circuits (ICs) employing optical receive/transmit, RF amplification and modulation and digital control functions are discussed. We focus on compatibility of the photonic component fabrication with conventional RF and digital IC technologies. Recent progress at Honeywell in integrating several parts of the desired RF/digital/photonic circuit integration suite required for construction of a future millimeter-wave optically-controlled phased-array element are illustrated.

  17. Mirrored Modified Howland Circuit for Bioimpedance Applications: Analytical Analysis

    NASA Astrophysics Data System (ADS)

    Bertemes-Filho, P.; Negri, L. H.; Felipe, A.; Vincence, V. C.

    2012-12-01

    Multifrequency Electrical Bioimpedance (MEB) has been widely used as a non-invasive technique for characterizing tissues. Most MEB systems use wideband current sources for injecting current to load and instrumentation amplifiers for measuring the resultant potential. Current sources should present intrinsically high output impedance in a very wide frequency range. The objective of this work is to investigate the performance of the Mirrored Modified Howland Current Source (MMHCS) by comparing the analytical solution with the SPICE simulation. It was implemented four MMHCS circuits by using four different operational amplifiers each one. The output current was set to 1 mAp (peak) in the frequency from 1 Hz to 100 MHz. Both techniques presented similar results at lower frequencies. It can be concluded that the output impedance of the circuit is highly dependent of the open-loop gain of the operation amplifier. The analytical solution showed that it is possible to project a current source by using only theirs output current and impedance equations.

  18. Basic structures of integrated photonic circuits for smart biosensor applications

    NASA Astrophysics Data System (ADS)

    Germer, S.; Cherkouk, C.; Rebohle, L.; Helm, M.; Skorupa, W.

    2013-05-01

    The breadth of opportunities for applied technologies for optical sensors ranges from environmental and biochemical control, medical diagnostics to process regulation. Thus the specified usage of the optical sensor system requires a particular design and functionalization. Especially biochemical sensors incorporate electronic and photonic devices for the detection of harmful substances e.g. in drinking water. Here we present recent developments in the integration of a Si-based light emitting device (LED) [1-3, 8] into a photonic circuit for an optical waveguide-based biodetection system. This concept includes the design, fabrication and characterization of the dielectric high contrast waveguide as an important component, beside the LED, in the photonic system circuit. First approaches involve simulations of Si3N4/SiO2-waveguides with the finite element method (FEM) and their fabrication by plasma enhanced chemical vapour deposition (PECVD), optical lithography and reactive ion etching (RIE). In addition, we characterized the deposited layers via ellipsometry and the etched structures by scanning electron microscopy (SEM). The obtained results establish a basis for optimized Si-based LED waveguide butt-coupling with adequate coupling efficiency, low attenuation loss and a high optical power throughput.

  19. Asynchronous data readout system for multichannel ASIC

    NASA Astrophysics Data System (ADS)

    Ivanov, P. Y.; Atkin, E. V.

    2016-02-01

    The data readout system of multichannel data-driven ASIC, requiring high-speed (320 Mb/s) output data serialization is described. Its structure, based on a limited number of FIFO blocks, provides a lossless data transfer. The solution has been realized as a separate test IP block in the prototyped 8 channel ASIC, intended for the muon chamber of CBM experiment at FAIR. The block was developed for the UMC 0.18 μm MMRF CMOS process and prototyped via Europractice. Main parameters of the chip are given.

  20. Practical applications of digital integrated circuits. Part 2: Minimization techniques, code conversion, flip-flops, and asynchronous circuits

    NASA Technical Reports Server (NTRS)

    1972-01-01

    Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be pointed out that the logic theory contained herein applies to all hardware. Binary numbers, simplification of logic circuits, code conversion circuits, basic flip-flop theory, details about series 54/7400, and asynchronous circuits are discussed.

  1. Plasmonic nanopatch array for optical integrated circuit applications

    PubMed Central

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-01-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle. PMID:24201454

  2. An application of carbon nanotubes for integrated circuit interconnects

    NASA Astrophysics Data System (ADS)

    Coiffic, J. C.; Foa Torres, L. E.; Le Poche, H.; Fayolle, M.; Roche, S.; Maitrejean, S.; Roualdes, S.; Ayral, A.

    2008-08-01

    Integrated circuits fabrication is soon reaching strong limitations. Help could come from using carbon nanotubes as conducting wires for interconnects. Although this solution was proposed six years ago, researchers still come up with many obstacles such as localization, low temperature growth on copper, contacting and reproducibility. The integration processes exposed here intend to meet the industrial requirements. Two approaches are then possibly followed. Either using densely packed single wall (SWCNT) (or very tiny multiwall) nanotubes, or filling up the whole interconnect diameter with a single large multiwall (MWCNT) nanotube. In this work, we focus on the integration of multiwall vertical interconnects. Densely packed MWCNTs are grown in via holes by CVD. Alternatively, we have developed a method to obtain a single large nanofibre grown by PECVD (MWCNF) in each via hole. Electrical measurements are performed on CVD and PECVD grown carbon nanotubes. The role of electron-phonon interaction in these devices is also briefly discussed.

  3. Plasmonic nanopatch array for optical integrated circuit applications.

    PubMed

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-01-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle. PMID:24201454

  4. Modeling and simulation of carbon nanotube field effect transistor and its circuit application

    NASA Astrophysics Data System (ADS)

    Singh, Amandeep; Saini, Dinesh Kumar; Agarwal, Dinesh; Aggarwal, Sajal; Khosla, Mamta; Raj, Balwinder

    2016-07-01

    The carbon nanotube field effect transistor (CNTFET) is modelled for circuit application. The model is based on the transport mechanism and it directly relates the transport mechanism with the chirality. Also, it does not consider self consistent equations and thus is used to develop the HSPICE compatible circuit model. For validation of the model, it is applied to the top gate CNTFET structure and the MATLAB simulation results are compared with the simulations of a similar structure created in NanoTCAD ViDES. For demonstrating the circuit compatibility of the model, two circuits viz. inverter and SRAM are designed and simulated in HSPICE. Finally, SRAM performance metrics are compared with those of device simulations from Nano TCAD ViDES.

  5. GEMMA and GEMINI, two dedicated mixed-signal ASICs for Triple-GEM detectors readout

    NASA Astrophysics Data System (ADS)

    Pezzotta, A.; Croci, G.; Costantini, A.; De Matteis, M.; Tagnani, D.; Corradi, G.; Murtas, F.; Gorini, G.; Baschirotto, A.

    2016-03-01

    GEMMA and GEMINI, two integrated-circuit front-ends for the Triple-GEM detector are presented. These two ASICs aim to improve detector readout performance in terms of count rate, adaptability, portability and power consumption. GEMMA target is to embed counting, timing and spectroscopic measurements in a single 8-channel device, managing a detector capacitance up to 15 pF. On the other hand, GEMINI is dedicated to counting measurements, embedding 16 channels with a detector capacitance up to 40 pF. Both prototypes, fabricated in 130 nm and 180 nm CMOS respectively, feature an automatic on-chip calibration circuit, compensating for process/temperature variations.

  6. Custom IC/Embedded IP design for histogram in video processing application

    NASA Astrophysics Data System (ADS)

    Pandey, Manoj; Chaturvedi, Richa; Rai, S. K.

    2016-03-01

    Histogram is an integral part of video processing applications. Either of the design methods ASIC or Embedded, histogram computation is an important functional block. This paper proposes the custom Integrated Circuit (IC) as an ASIC and an embedded IP to compute the colored histogram function. Histogram computation has two features: color and spatial. Color feature has been calculated using find_bin and spatial feature is calculated using kernel function. The design is verified using NCSIM Cadence tool, while it is synthesized using RTL compiler. Finally, the embedded IP has interfaced with Kernel based mean shift algorithm in tracking a moving object and implemented on Xilinx Spartan 6 LX150T FPGA.

  7. Application of the DRS4 chip for GHz waveform digitizing circuits

    NASA Astrophysics Data System (ADS)

    Yang, Hai-Bo; Su, Hong; Kong, Jie; Cheng, Ke; Chen, Jin-Da; Du, Cheng-Ming; Zhang, Jing-Zhe

    2015-05-01

    A new fast waveform sampling digitizing circuit based on the domino ring sampler (DRS), a switched capacitor array (SCA) chip, is presented in this paper, which is different from the traditional waveform digitizing circuit constructed with an analog to digital converter (ADC) or time to digital converter. A DRS4 chip is used as a core device in our circuit, which has a fast sampling rate up to five gigabit samples per second (GSPS). Quite satisfactory results are acquired by the preliminary performance test for this circuit board. Eight channels can be provided by one board, which has a 1 V input dynamic range for each channel. The circuit linearity is better than 0.1%, the noise is less than 0.5 mV (root mean square, RMS), and its time resolution is about 50 ps. Several boards can be cascaded to construct a multi-board system. The advantages of high resolution, low cost, low power dissipation, high channel density and small size make the circuit board useful not only for physics experiments, but also for other applications. Supported by National Natural Science Foundation of China (11305233), Specific Fund Research Based on Large-scale Science Instrument Facilities of China (2011YQ12009604)

  8. Acid-sensing ion channels (ASICs) are differentially modulated by anions dependent on their subunit composition

    PubMed Central

    Kusama, Nobuyoshi; Gautam, Mamta; Harding, Anne Marie S.; Snyder, Peter M.

    2013-01-01

    Acid-sensing ion channels (ASICs) are sodium channels gated by extracellular protons. ASIC1a channels possess intersubunit Cl−-binding sites in the extracellular domain, which are highly conserved between ASIC subunits. We previously found that anions modulate ASIC1a gating via these sites. Here we investigated the effect of anion substitution on native ASICs in rat sensory neurons and heterologously expressed ASIC2a and ASIC3 channels by whole cell patch clamp. Similar to ASIC1a, anions modulated the kinetics of desensitization of other ASIC channels. However, unlike ASIC1a, anions also modulated the pH dependence of activation. Moreover, the order of efficacy of different anions to modulate ASIC2a and -3 was very different from that of ASIC1a. More surprising, mutations of conserved residues that form an intersubunit Cl−-binding site in ASIC1a only partially abrogated the effects of anion modulation of ASIC2a and had no effect on anion modulation of ASIC3. The effects of anions on native ASICs in rat dorsal root ganglion neurons mimicked those in heterologously expressed ASIC1a/3 heteromeric channels. Our data show that anions modulate a variety of ASIC properties and are dependent on the subunit composition, and the mechanism of modulation for ASIC2a and -3 is distinct from that of ASIC1a. We speculate that modulation of ASIC gating by Cl− is a novel mechanism to sense shifts in extracellular fluid composition. PMID:23135698

  9. Preliminary validation results of an ASIC for the readout and control of near-infrared large array detectors

    NASA Astrophysics Data System (ADS)

    Pâhlsson, Philip; Meier, Dirk; Otnes Berge, Hans Kristian; Øya, Petter; Steenari, David; Olsen, Alf; Hasanbegovic, Amir; Altan, Mehmet A.; Najafiuchevler, Bahram; Talebi, Jahanzad; Azman, Suleyman; Gheorghe, Codin; Ackermann, Jörg; Mæhlum, Gunnar

    2015-06-01

    In this paper we present initial test results of the Near Infrared Readout and Controller ASIC (NIRCA), designed for large area image sensors under contract from the European Space Agency (ESA) and the Norwegian Space Center. The ASIC is designed to read out image sensors based on mercury cadmium telluride (HgCdTe, or MCT) operating down to 77 K. IDEAS has developed, designed and initiated testing of NIRCA with promising results, showing complete functionality of all ASIC sub-components. The ASIC generates programmable digital signals to clock out the contents of an image array and to amplify, digitize and transfer the resulting pixel charge. The digital signals can be programmed into the ASIC during run-time and allows for windowing and custom readout schemes. The clocked out voltages are amplified by programmable gain amplifiers and digitized by 12-bit, 3-Msps successive approximation register (SAR) analogue-to-digital converters (ADC). Digitized data is encoded using 8-bit to 10-bit encoding and transferred over LVDS to the readout system. The ASIC will give European researchers access to high spectral sensitivity, very low noise and radiation hardened readout electronics for astronomy and Earth observation missions operating at 77 K and room temperature. The versatility of the chip makes the architecture a possible candidate for other research areas, or defense or industrial applications that require analog and digital acquisition, voltage regulation, and digital signal generation.

  10. Abnormal Cardiac Autonomic Regulation in Mice Lacking ASIC3

    PubMed Central

    Cheng, Ching-Feng; Kuo, Terry B. J.; Chen, Wei-Nan

    2014-01-01

    Integration of sympathetic and parasympathetic outflow is essential in maintaining normal cardiac autonomic function. Recent studies demonstrate that acid-sensing ion channel 3 (ASIC3) is a sensitive acid sensor for cardiac ischemia and prolonged mild acidification can open ASIC3 and evoke a sustained inward current that fires action potentials in cardiac sensory neurons. However, the physiological role of ASIC3 in cardiac autonomic regulation is not known. In this study, we elucidate the role of ASIC3 in cardiac autonomic function using Asic3−/− mice. Asic3−/− mice showed normal baseline heart rate and lower blood pressure as compared with their wild-type littermates. Heart rate variability analyses revealed imbalanced autonomic regulation, with decreased sympathetic function. Furthermore, Asic3−/− mice demonstrated a blunted response to isoproterenol-induced cardiac tachycardia and prolonged duration to recover to baseline heart rate. Moreover, quantitative RT-PCR analysis of gene expression in sensory ganglia and heart revealed that no gene compensation for muscarinic acetylcholines receptors and beta-adrenalin receptors were found in Asic3−/− mice. In summary, we unraveled an important role of ASIC3 in regulating cardiac autonomic function, whereby loss of ASIC3 alters the normal physiological response to ischemic stimuli, which reveals new implications for therapy in autonomic nervous system-related cardiovascular diseases. PMID:24804235

  11. Abnormal cardiac autonomic regulation in mice lacking ASIC3.

    PubMed

    Cheng, Ching-Feng; Kuo, Terry B J; Chen, Wei-Nan; Lin, Chao-Chieh; Chen, Chih-Cheng

    2014-01-01

    Integration of sympathetic and parasympathetic outflow is essential in maintaining normal cardiac autonomic function. Recent studies demonstrate that acid-sensing ion channel 3 (ASIC3) is a sensitive acid sensor for cardiac ischemia and prolonged mild acidification can open ASIC3 and evoke a sustained inward current that fires action potentials in cardiac sensory neurons. However, the physiological role of ASIC3 in cardiac autonomic regulation is not known. In this study, we elucidate the role of ASIC3 in cardiac autonomic function using Asic3(-/-) mice. Asic3(-/-) mice showed normal baseline heart rate and lower blood pressure as compared with their wild-type littermates. Heart rate variability analyses revealed imbalanced autonomic regulation, with decreased sympathetic function. Furthermore, Asic3(-/-) mice demonstrated a blunted response to isoproterenol-induced cardiac tachycardia and prolonged duration to recover to baseline heart rate. Moreover, quantitative RT-PCR analysis of gene expression in sensory ganglia and heart revealed that no gene compensation for muscarinic acetylcholines receptors and beta-adrenalin receptors were found in Asic3(-/-) mice. In summary, we unraveled an important role of ASIC3 in regulating cardiac autonomic function, whereby loss of ASIC3 alters the normal physiological response to ischemic stimuli, which reveals new implications for therapy in autonomic nervous system-related cardiovascular diseases. PMID:24804235

  12. Single event effect characterization of the mixed-signal ASIC developed for CCD camera in space use

    NASA Astrophysics Data System (ADS)

    Nakajima, Hiroshi; Fujikawa, Mari; Mori, Hideki; Kan, Hiroaki; Ueda, Shutaro; Kosugi, Hiroko; Anabuki, Naohisa; Hayashida, Kiyoshi; Tsunemi, Hiroshi; Doty, John P.; Ikeda, Hirokazu; Kitamura, Hisashi; Uchihori, Yukio

    2013-12-01

    We present the single event effect (SEE) tolerance of a mixed-signal application-specific integrated circuit (ASIC) developed for a charge-coupled device camera onboard a future X-ray astronomical mission. We adopted proton and heavy ion beams at HIMAC/NIRS in Japan. The particles with high linear energy transfer (LET) of 57.9 MeV cm2/mg is used to measure the single event latch-up (SEL) tolerance, which results in a sufficiently low cross-section of σSEL<4.2×10-11 cm2/(Ion×ASIC). The single event upset (SEU) tolerance is estimated with various kinds of species with wide range of energy. Taking into account that a part of the protons creates recoiled heavy ions that have higher LET than that of the incident protons, we derived the probability of SEU event as a function of LET. Then the SEE event rate in a low-earth orbit is estimated considering a simulation result of LET spectrum. SEL rate is below once per 49 years, which satisfies the required latch-up tolerance. The upper limit of the SEU rate is derived to be 1.3×10-3 events/s. Although the SEU events cannot be distinguished from the signals of X-ray photons from astronomical objects, the derived SEU rate is below 1.3% of expected non-X-ray background rate of the detector and hence these events should not be a major component of the instrumental background.

  13. Development and evaluation of an ultra-fast ASIC for future PET scanners using TOF-capable MPPC array detectors

    NASA Astrophysics Data System (ADS)

    Ambe, T.; Ikeda, H.; Kataoka, J.; Matsuda, H.; Kato, T.

    2015-01-01

    We developed a front-end ASIC for future PET scanners with Time-Of-Flight (TOF) capability to be coupled with 4×4 Multi-Pixel Photon Counter (MPPC) arrays. The ASIC is designed based on the open-IP project proposed by JAXA and realized in TSMC 0.35 μm CMOS technology. The circuit comprises 16-channel, low impedance current conveyors for effectively acquiring fast MPPC signals. For precise measurement of the coincidence timing of 511-keV gamma rays, the leading-edge method was used to discriminate the signals. We first tested the time response of the ASIC by illuminating each channel of a MPPC array device 3×3 mm2 in size with a Pico-second Light Pulsar with a light emission peak of 655 nm and pulse duration of 54 ps (FWHM). We obtained 105 ps (FWHM) on average for each channel in time jitter measurements. Moreover, we compensated for the time lag of each channel with inner delay circuits and succeeded in suppressing about a 700-ps lag to only 15 ps. This paper reports TOF measurements using back-to-back 511-keV signals, and suggests that the ASIC can be a promising device for future TOF-PET scanners based on the MPPC array.

  14. System-Level Integrated Circuit (SLIC) development for phased array antenna applications

    NASA Technical Reports Server (NTRS)

    Shalkhauser, K. A.; Raquet, C. A.

    1991-01-01

    A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

  15. System-level integrated circuit (SLIC) development for phased array antenna applications

    NASA Technical Reports Server (NTRS)

    Shalkhauser, K. A.; Raquet, C. A.

    1991-01-01

    A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

  16. Characterization results of the JUNGFRAU full scale readout ASIC

    NASA Astrophysics Data System (ADS)

    Mozzanica, A.; Bergamaschi, A.; Brueckner, M.; Cartier, S.; Dinapoli, R.; Greiffenberg, D.; Jungmann-Smith, J.; Maliakal, D.; Mezza, D.; Ramilli, M.; Ruder, C.; Schaedler, L.; Schmitt, B.; Shi, X.; Tinti, G.

    2016-02-01

    The two-dimensional pixel detector JUNGFRAU is designed for high performance photon science applications at free electron lasers and synchrotron light sources. It is developed for the SwissFEL currently under construction at the Paul Scherrer Institut, Switzerland. The detector is a hybrid pixel detector with a charge integration readout ASIC characterized by single photon sensitivity and a low noise performance over a dynamic range of 104 12 keV photons. Geometrically, a JUNGFRAU readout chip consists of 256×256 pixels of 75×75 μm2. The chips are bump bonded to 320 μm thick silicon sensors. Arrays of 2×4 chips are tiled to form modules of 4×8 cm2 area. Several multi-module systems with up to 16 Mpixels per system will be delivered to the two end stations at SwissFEL. The JUNGFRAU full scale readout ASIC and module design are presented along with characterization results of the first systems. Experiments from fluorescence X-ray, visible light illumination, and synchrotron irradiation are shown. The results include an electronic noise of ~50 electrons r.m.s., which enables single photon detection energies below 2 keV and a noise well below the Poisson statistical limit over the entire dynamic range. First imaging experiments are also shown.

  17. Radiation hardness by design for mixed signal infrared readout circuit applications

    NASA Astrophysics Data System (ADS)

    Gaalema, Stephen; Gates, James; Dobyns, David; Pauls, Greg; Wall, Bruce

    2013-09-01

    Readout integrated circuits (ROICs) to support space-based infrared detection applications often have severe radiation tolerance requirements. Radiation hardness-by-design (RHBD) significantly enhances the radiation tolerance of commercially available CMOS and custom radiation hardened fabrication techniques are not required. The combination of application specific design techniques, enclosed gate architecture nFETs and intrinsic thin oxide radiation hardness of 180 nm process node commercial CMOS allows realization of high performance mixed signal circuits. Black Forest Engineering has used RHBD techniques to develop ROICs with integrated A/D conversion that operate over a wide range of temperatures (40K-300K) to support infrared detection. ROIC radiation tolerance capability for 256x256 LWIR area arrays and 1x128 thermopile linear arrays is presented. The use of 130 nm CMOS for future ROIC RHBD applications is discussed.

  18. Semi-custom integrated circuit amplifier and level discriminator for nuclear and space instruments

    SciTech Connect

    Hahn, S.F.; Cafferty, M.M.

    1990-01-01

    An extra fast current feedback amplifier and a level discriminator are developed employing a dielectrically-isolated bipolar, semi-custom Application Specific Integrated Circuit (ASIC) process. These devices are specifically designed for instruments aboard spacecrafts or in portable packages requiring low power and weight. The amplifier adopts current feedback for a unity-gain bandwidth of 90 MHz while consuming 50 mW. The level discriminator uses a complementary output driver for balanced positive and negative response times. The power consumption of these devices can be programmed by external resistors for optimal speed and power trade-off. 3 refs., 7 figs.

  19. A simple tachometer circuit

    NASA Technical Reports Server (NTRS)

    Dimeff, J.

    1972-01-01

    Electric circuit to measure frequency of repetitive sinusoidal or rectangular wave is presented. Components of electric circuit and method of operation are explained. Application of circuit as tachometer for automobile is discussed.

  20. Molecular and functional characterization of acid-sensing ion channel (ASIC) 1b.

    PubMed

    Bässler, E L; Ngo-Anh, T J; Geisler, H S; Ruppersberg, J P; Gründer, S

    2001-09-01

    Acid-sensing ion channels (ASICs) are activated by extracellular protons and are involved in neurotransmission in the central nervous system, in pain perception, as well as in mechanotransduction. Six different ASIC subunits have been cloned to date, which are encoded by four genes (ASIC1-ASIC4). Proton-gated currents have been described in isolated neurons from sensory ganglia as well as from central nervous system. However, it is largely unclear which of the cloned ASIC subunits underlie these native proton-gated currents. Recently, a splice variant, ASIC-beta, has been described for ASIC1a. In this variant about one-third of the protein is exchanged at the N terminus. Here we show that ASIC-beta has a longer N terminus than previously reported, extending the sequence divergence between ASIC1a and this new variant (ASIC1b). We investigated in detail kinetic and selectivity properties of ASIC1b in comparison to ASIC1a. Kinetics is similar for ASIC1b and ASIC1a. Ca(2+) permeability of ASIC1a is low, whereas ASIC1b is impermeable to Ca(2+). Currents through ASIC1a resemble currents, which have been described in sensory and central neurons, whereas the significance of ASIC1b remains to be established. Moreover, we show that a pre-transmembrane 1 domain controls the permeability to divalent cations in ASIC1, contributing to our understanding of the pore structure of these channels. PMID:11448963

  1. Seizure Termination by Acidosis Depends on ASIC1a

    PubMed Central

    Ziemann, Adam E.; Schnizler, Mikael K.; Albert, Gregory W.; Severson, Meryl A.; Howard, Matthew A.; Welsh, Michael J.; Wemmie, John A.

    2008-01-01

    SUMMARY Most seizures stop spontaneously. However, the molecular mechanisms remain unknown. Earlier observations that seizures reduce brain pH and that acidosis inhibits seizures indicated that acidosis halts epileptic activity. Because acid–sensing ion channel–1a (ASIC1a) shows exquisite sensitivity to extracellular pH and regulates neuron excitability, we hypothesized that acidosis might activate ASIC1a to terminate seizures. Disrupting mouse ASIC1a increased the severity of chemoconvulsant–induced seizures, whereas overexpressing ASIC1a had the opposite effect. ASIC1a did not affect seizure threshold or onset, but shortened seizure duration and prevented progression. CO2 inhalation, long known to lower brain pH and inhibit seizures, also required ASIC1a to interrupt tonic–clonic seizures. Acidosis activated inhibitory interneurons through ASIC1a, suggesting that ASIC1a might limit seizures by increasing inhibitory tone. These findings identify ASIC1a as a key element in seizure termination when brain pH falls. The results suggest a molecular mechanism for how the brain stops seizures and suggest new therapeutic strategies. PMID:18536711

  2. Lignan from Thyme Possesses Inhibitory Effect on ASIC3 Channel Current*

    PubMed Central

    Dubinnyi, Maxim A.; Osmakov, Dmitry I.; Koshelev, Sergey G.; Kozlov, Sergey A.; Andreev, Yaroslav A.; Zakaryan, Naira A.; Dyachenko, Igor A.; Bondarenko, Dmitry A.; Arseniev, Alexander S.; Grishin, Eugene V.

    2012-01-01

    A novel compound was identified in the acidic extract of Thymus armeniacus collected in the Lake Sevan region of Armenia. This compound, named “sevanol,” to our knowledge is the first low molecular weight natural molecule that has a reversible inhibition effect on both the transient and the sustained current of human ASIC3 channels expressed in Xenopus laevis oocytes. Sevanol completely blocked the transient component (IC50 353 ± 23 μm) and partially (∼45%) inhibited the amplitude of the sustained component (IC50 of 234 ± 53 μm). Other types of acid-sensing ion channel (ASIC) channels were intact to sevanol application, except ASIC1a, which showed more than six times less affinity to it as compared with the inhibitory action on the ASIC3 channel. To elucidate the structure of sevanol, the set of NMR spectra in two solvents (d6-DMSO and D2O) was collected, and the complete chemical structure was confirmed by liquid chromatography-mass spectrometry with electrospray ionization (LC-ESI+-MS) fragmentation. This compound is a new lignan built up of epiphyllic acid and two isocitryl esters in positions 9 and 10. In vivo administration of sevanol (1–10 mg/kg) significantly reversed thermal hyperalgesia induced by complete Freund's adjuvant injection and reduced response to acid in a writhing test. Thus, we assume the probable considerable role of sevanol in known analgesic and anti-inflammatory properties of thyme. PMID:22854960

  3. High-accuracy function synthesizer circuit with applications in signal processing

    NASA Astrophysics Data System (ADS)

    Popa, Cosmin

    2012-12-01

    An original low-voltage current-mode high-accuracy function synthesizer circuit will be presented, allowing to implement a multitude of continuous mathematical functions. The dynamic range is strongly extended as a result of the superior-order approximation of the implemented functions. The current-mode operation and the independence of the circuit performances on technological parameters are responsible for an additional improvement of structure accuracy. The advantages of reduced design costs per function represent an immediate consequence of the multiple functions realized by the proposed structure. The approximation error of the original function synthesizer circuit is 0.3% for an extended range of the input signal. The function synthesizer is designed for implementing in 0.18 μm CMOS technology and it is supplied at 1 V. An original application of the proposed function synthesizer circuit is represented by a new fourth-order approximation exponential function generator, having a dynamic range of approximately 33 dB, for an error smaller than 1 dB.

  4. Development of a dedicated readout ASIC for TPC based X-ray polarimeter

    NASA Astrophysics Data System (ADS)

    Zhang, Hongyan; Deng, Zhi; Li, Hong; Liu, Yinong; Feng, Hua

    2016-07-01

    X-ray polarimetry with time projection chambers was firstly proposed by JK Black in 2007 and has been greatly developed since then. It measured two dimensional photoelectron tracks with one dimensional strip and the other dimension was estimated by the drift time from the signal waveforms. A readout ASIC, APV25, originally developed for CMS silicon trackers was used and has shown some limitations such as waveform sampling depth. A dedicated ASIC was developed for TPC based X-ray polarimeters in this paper. It integrated 32 channel circuits and each channel consisted of an analog front-end and a waveform sampler based on switched capacitor array. The analog front-end has a charge sensitive preamplifier with a gain of 25 mV/fC, a CR-RC shaper with a peaking time of 25 ns, a baseline holder and a discriminator for self-triggering. The SCA has a buffer latency of 3.2 μs with 64 cells operating at 20 MSPS. The ASIC was fabricated in a 0.18 μm CMOS process. The equivalent noise charge (ENC) of the analog front-end was measured to be 274.8 e+34.6 e/pF. The effective resolution of the SCA was 8.8 bits at sampling rate up to 50 MSPS. The total power consumption was 2.8 mW per channel. The ASIC was also tested with real TPC detectors and two dimensional photoelectron tracks have been successfully acquired. More tests and analysis on the sensitivity to the polarimetry are undergoing and will be presented in this paper.

  5. Low power smartdust receiver with novel applications and improvements of an RF power harvesting circuit

    NASA Astrophysics Data System (ADS)

    Salter, Thomas Steven, Jr.

    Smartdust is the evolution of wireless sensor networks to cubic centimeter dimensions or less. Smartdust systems have advantages in cost, flexibility, and rapid deployment that make them ideal for many military, medical, and industrial applications. This work addresses the limitations of prior works of research to provide sufficient lifetime and performance for Smartdust sensor networks through the design, fabrication and testing of a novel low power receiver for use in a Smartdust transceiver. Through the novel optimization of a multi-stage LNA design and novel application of a power matched Villard voltage doubler circuit, a 1.0 V, 1.6 mW low power On-Off Key (OOK) receiver operating at 2.2 GHz is fabricated using 0.13 um CMOS technology. To facilitate data transfer in adverse RF propagation environments (1/r3 loss), the chip receives a 1 Mbps data signal with a sensitivity of -90 dBm while consuming just 1.6 nJ/bit. The receiver operates without the addition of any external passives facilitating its application in Smartdust scale (cm 3) wireless sensor networks. This represents an order of magnitude decrease in power consumption over receiver designs of comparable sensitivity. In an effort to further extend the lifetime of the Smartdust transceiver, RF power harvesting is explored as a power source. The small scale of Smartdust sensor networks poses unique challenges in the design of RF power scavenging systems. To meet these challenges, novel design improvements to an RF power scavenging circuit integrated directly onto CMOS are presented. These improvements include a reduction in the threshold voltage of diode connected MOSFET and sources of circuit parasitics that are unique to integrated circuits. Utilizing these improvements, the voltage necessary to drive Smartdust circuitry (1 V) with a greater than 20% RF to DC conversion efficiency was generated from RF energy levels measured in the environment (66 uW). This represents better than double the RF to DC

  6. Micro/nano-scale fabrication of integrated polymer optical wire circuit arrays for optical printed circuit board (O-PCB) application

    NASA Astrophysics Data System (ADS)

    Lee, El-Hang; Lee, Seung G.; Park, Se G.; Kim, Kyong H.; Kang, Jin K.; Chin, In J.; Kwon, Y. K.; Choi, Young W.

    2005-02-01

    We report on the results of our study on the micro/nano-scale design, fabrication and integration of waveguide arrays for optical printed circuit boards (O-PCBs) and VLSI micro/nano-photonic applications. The O-PCBs are designed to perform the functions of transporting, switching, routing and distributing optical signals on flat modular boards or substrates. We have assembled O-PCBs using optical waveguide arrays and circuits made of polymer materials and have examined information handling performances. We also designed power beam splitters and waveguide filters, using nano-scale photonic band-gap crystals, for VLSI photonic integration application. We discuss potential applications of polymer optical waveguide devices and arrays for O-PCB and VLSI micro/nano-photonics for computers, telecommunications, and transportation systems.

  7. Optical printed circuit board (O-PCB) for VLSI micro/nano-photonic application

    NASA Astrophysics Data System (ADS)

    Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Kim, K. H.; Kang, J. K.; Chin, I.; Kwon, Y. K.; Choi, Y. W.

    2005-01-01

    We present, in the form of review, the results of our study on the design, fabrication and assembly of optical printed circuit boards (O-PCBs) for VLSI micro/nano-photonic applications. The O-PCBs are designed to perform the functions of transporting, switching, routing and distributing optical signals on flat modular boards, substrates or chips, in a manner similar to the electrical printed circuit boards (E-PCBs). We have assembled and constructed O-PCBs using optical waveguide arrays and circuits made of polymer materials and have examined their information handling performances. We also designed power beam splitters and waveguide filters using nano-scale photonic band-gap crystals. We discuss scientific and technological issues concerning the processes of miniaturization, interconnection and integration of polymer optical waveguide devices and arrays for O-PCB and VLSI micro/nano-photonics as applicable to board-to-board, chip-to-chip, and intra-chip integration for computers, telecommunications, and transportation systems.

  8. The STAR cluster-finder ASIC

    SciTech Connect

    Botlo, M.; LeVine, M.J.; Scheetz, R.A.; Schulz, M.W.; Short, P.; Woods, J.; Crosetto, D.

    1997-12-01

    STAR is a large TPC-based experiment at RHIC, the relativistic heavy ion collider at Brookhaven National Laboratory. The STAR experiment reads out a TPC and an SVT (silicon vertex tracker), both of which require in-line pedestal subtraction, compression of ADC values from 10-bit to 8-bit, and location of time sequences representing responses to charged-particle tracks. The STAR cluster finder ASIC responds to all of these needs. Pedestal subtraction and compression are performed using lookup tables in attached RAM. The authors describe its design and implementation, as well as testing methodology and results of tests performed on foundry prototypes.

  9. The LENA ASIC: Emulating an Obsolete Processor

    NASA Astrophysics Data System (ADS)

    Carayon, J. L.; Mary, L.; Bertrand, J.; Manni, F.

    2013-08-01

    From 10 years, CNES and his partners TAS and Astrium have developed and flown with great success a serie of microsatellites (Demeter, Parasol, Picard etc..), which avionics is based onto a central OBC computer. The OBC is built around a central transputer IMST805 processor, which is now obsolete: the strategic procurement lot done at the beginning of the project is too old now for Quality insurance reasons. The paper describes the LENA ASIC (Logic Emulation for New Architectures) and the approach taken at CNES for the replacement of the Transputer T805 used for Myriade OBC computer to allow production of new microsatellites at a low cost in the next decade.

  10. AIDA: A 16-channel amplifier ASIC to read out the advanced implantation detector array for experiments in nuclear decay spectroscopy

    SciTech Connect

    Braga, D.; Coleman-Smith, P. J.; Davinson, T.; Lazarus, I. H.; Page, R. D.; Thomas, S.

    2011-07-01

    We have designed a read-out ASIC for nuclear decay spectroscopy as part of the AIDA project - the Advanced Implantation Detector Array. AIDA will be installed in experiments at the Facility for Antiproton and Ion Research in GSI, Darmstadt. The AIDA ASIC will measure the signals when unstable nuclei are implanted into the detector, followed by the much smaller signals when the nuclei subsequently decay. Implant energies can be as high as 20 GeV; decay products need to be measured down to 25 keV within just a few microseconds of the initial implants. The ASIC uses two amplifiers per detector channel, one covering the 20 GeV dynamic range, the other selectable over a 20 MeV or 1 GeV range. The amplifiers are linked together by bypass transistors which are normally switched off. The arrival of a large signal causes saturation of the low-energy amplifier and a fluctuation of the input voltage, which activates the link to the high-energy amplifier. The bypass transistors switch on and the input charge is integrated by the high-energy amplifier. The signal is shaped and stored by a peak-hold, then read out on a multiplexed output. Control logic resets the amplifiers and bypass circuit, allowing the low-energy amplifier to measure the subsequent decay signal. We present simulations and test results, demonstrating the AIDA ASIC operation over a wide range of input signals. (authors)

  11. Single superconducting thin film devices for applications in high T/sub c/ materials circuits

    SciTech Connect

    Martens, J.S.; Beyer, J.B.; Nordman, J.E.; Ginley, D.S.; Hohenwarter, G.K.G.; McGinnis, D.P.

    1989-03-01

    The authors have investigated several different devices based on regions of weak superconductivity and multiple parallel links in thin films. Hysteretic symmetric and asymmetric IV curves have been observed. Flux flow was indicated. Device switching properties and the dependence of the flux flow signature in the IV curve on applied magnetic field were explored. Both Nb and high T/sub c/ thin films were used in circuit fabrication. Contrary to vortex flow devices based on Josephson junctions those described here do not possess a tunneling barrier and are made of only a single superconducting layer. Hence they should be applicable to electronic circuits based on high T/sub c/ superconducting materials without the need for tunnel junctions.

  12. Expert System for ASIC Imaging

    NASA Astrophysics Data System (ADS)

    Gupta, Shri N.; Arshak, Khalil I.; McDonnell, Pearse; Boyce, Conor; Duggan, Andrew

    1989-07-01

    With the developments in the techniques of artificial intelligence over the last few years, development of advisory, scheduling and similar class of problems has become very convenient using tools such as PROLOG. In this paper an expert system has been described which helps lithographers and process engineers in several ways. The methodology used is to model each work station according to its input, output and control parameters, combine these work stations in a logical sequence based on past experience and work out process schedule for a job. In addition, all the requirements vis-a-vis a particular job parameters are converted into decision rules. One example is the exposure time, develop time for a wafer with different feature sizes would be different. This expert system has been written in Turbo Prolog. By building up a large number of rules, one can tune the program to any facility and use it for as diverse applications as advisory help, trouble shooting etc. Leitner (1) has described an advisory expert system that is being used at National Semiconductor. This system is quite different from the one being reported in the present paper. The approach is quite different for one. There is stress on job flow and process for another.

  13. A 200 C Universal Gate Driver Integrated Circuit for Extreme Environment Applications

    SciTech Connect

    Tolbert, Leon M; Huque, Mohammad A; Islam, Syed K; Blalock, Benjamin J

    2012-01-01

    High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 C. This new gate driver prototype has been designed and implemented in a 0.8 {micro}m, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature ({ge}220 C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 {micro}W for operating temperature up to 200 C.

  14. Recovery Act: High-Temperature Circuit Boards for use in Geothermal Well Monitoring Applications

    SciTech Connect

    Hooker, Matthew; Fabian, Paul

    2013-05-01

    The U.S. Department of Energy is leading the development of alternative energy sources that will ensure the long-term energy independence of our nation. One of the key renewable resources currently being advanced is geothermal energy. To tap into the large potential offered by generating power from the heat of the earth, and for geothermal energy to be more widely used, it will be necessary to drill deeper wells to reach the hot, dry rock located up to 10 km beneath the earth’s surface. In this instance, water will be introduced into the well to create a geothermal reservoir. A geothermal well produced in this manner is referred to as an enhanced geothermal system (EGS). EGS reservoirs are typically at depths of 3 to 10 km, and the temperatures at these depths have become a limiting factor in the application of existing downhole technologies. These high temperatures are especially problematic for electronic systems such as downhole data-logging tools, which are used to map and characterize the fractures and high-permeability regions in underground formations. Information provided by these tools is assessed so that underground formations capable of providing geothermal energy can be identified, and the subsequent drilling operations can be accurately directed to those locations. The mapping of geothermal resources involves the design and fabrication of sensor packages, including the electronic control modules, to quantify downhole conditions (300°C temperature, high pressure, seismic activity, etc.). Because of the extreme depths at which these measurements are performed, it is most desirable to perform the sensor signal processing downhole and then transmit the information to the surface. This approach necessitates the use of high-temperature electronics that can operate in the downhole environment. Downhole signal processing in EGS wells will require the development and demonstration of circuit boards that can withstand the elevated temperatures found at these

  15. Flexible active electrode arrays with ASICs that fit inside the rat's spinal canal.

    PubMed

    Giagka, Vasiliki; Demosthenous, Andreas; Donaldson, Nick

    2015-12-01

    Epidural spinal cord electrical stimulation (ESCS) has been used as a means to facilitate locomotor recovery in spinal cord injured humans. Electrode arrays, instead of conventional pairs of electrodes, are necessary to investigate the effect of ESCS at different sites. These usually require a large number of implanted wires, which could lead to infections. This paper presents the design, fabrication and evaluation of a novel flexible active array for ESCS in rats. Three small (1.7 mm(2)) and thin (100 μm) application specific integrated circuits (ASICs) are embedded in the polydimethylsiloxane-based implant. This arrangement limits the number of communication tracks to three, while ensuring maximum testing versatility by providing independent access to all 12 electrodes in any configuration. Laser-patterned platinum-iridium foil forms the implant's conductive tracks and electrodes. Double rivet bonds were employed for the dice microassembly. The active electrode array can deliver current pulses (up to 1 mA, 100 pulses per second) and supports interleaved stimulation with independent control of the stimulus parameters for each pulse. The stimulation timing and pulse duration are very versatile. The array was electrically characterized through impedance spectroscopy and voltage transient recordings. A prototype was tested for long term mechanical reliability when subjected to continuous bending. The results revealed no track or bond failure. To the best of the authors' knowledge, this is the first time that flexible active electrode arrays with embedded electronics suitable for implantation inside the rat's spinal canal have been proposed, developed and tested in vitro. PMID:26466839

  16. GATING CIRCUITS

    DOEpatents

    Merrill, L.C.

    1958-10-14

    Control circuits for vacuum tubes are described, and a binary counter having an improved trigger circuit is reported. The salient feature of the binary counter is the application of the input signal to the cathode of each of two vacuum tubes through separate capacitors and the connection of each cathode to ground through separate diodes. The control of the binary counter is achieved in this manner without special pulse shaping of the input signal. A further advantage of the circuit is the simplicity and minimum nuruber of components required, making its use particularly desirable in computer machines.

  17. Equivalent-circuit modeling of a MEMS phase detector for phase-locked loop applications

    NASA Astrophysics Data System (ADS)

    Han, Juzheng; Liao, Xiaoping

    2016-05-01

    This paper presents an equivalent-circuit model of a MEMS phase detector and deals with its application in phase-locked loops (PLLs). Due to the dc voltage output of the MEMS phase detector, the low-pass filter which is essential in a conventional PLL can be omitted. Thus, the layout area can be miniaturized and the consumed power can be saved. The signal transmission inside the phase detector is realized in circuit model by waveguide modules while the electric-thermal-electric conversion is illustrated in circuit term based on analogies between thermal and electrical variables. Losses are taken into consideration in the modeling. Measurement verifications for the phase detector model are conducted at different input powers 11, 14 and 17 dBm at 10 GHz. The maximum discrepancies between the simulated and measured results are 0.14, 0.42 and 1.13 mV, respectively. A new structure of PLL is constructed by connecting the presented model directly to a VCO module in the simulation platform. It allows to model the transient behaviors of the PLL at both locked and out of lock conditions. The VCO output frequency is revealed to be synchronized with the reference frequency within the hold range. All the modeling and simulation are performed in Advanced Design System (ADS) software.

  18. Monolithically fabricated germanium-on-SOI photodetector and Si CMOS circuit for integrated photonic applications

    NASA Astrophysics Data System (ADS)

    Ang, Kah-Wee; Liow, Tsung-Yang; Yu, Ming-Bin; Fang, Qing; Song, Junfeng; Lo, Guo Q.; Kwong, Dim-Lee

    2010-05-01

    In this paper, we report our design and fabrication approach towards realizing a monolithic integration of Ge photodetector and Si CMOS circuits on common SOI platform for integrated photonic applications. The approach, based on the Ge-on-SOI technology, enables the realization of high sensitivity and low noise photodetector that is capable of performing efficient optical-to-electrical encoding in the near-infrared wavelengths regime. When operated at a bias of -1.0V, a vertical PIN detector achieved a lower Idark of ~0.57μA as compared to a lateral PIN detector, a value that is below the typical ~1μA upper limit acceptable for high speed receiver design. Very high responsivity of ~0.92A/W was obtained in both detector designs for a wavelength of 1550nm, which corresponds to a quantum efficiency of ~73%. Impulse response measurements showed that a vertical PIN photodetector gives rise to a smaller FWHM of ~24.4ps, which corresponds to a -3dB bandwidth of ~11.3GHz where RC time delay is known to be the dominant factor limiting the speed performance. Eye patterns (PRBS 27-1) measurement further confirms the achievement of high speed and low noise photodetection at a bit-rate of 8.5Gb/s. In addition, we evaluate the DC characteristics of the monolithically fabricated Si CMOS inverter circuit. Excellent transfer and output characteristics were achieved by the integrated CMOS inverter circuits in addition to the well behaved logic functions. We also assess the impact of the additional thermal budget introduced by the Ge epitaxy growth on the threshold voltage variation of the short channel CMOS transistors and discuss the issues and potential for the seamless integration of electronic and photonic integrated circuits.

  19. Terahertz applications of integrated circuits based on intrinsic Josephson junctions in high Tc superconductors

    NASA Astrophysics Data System (ADS)

    Wang, Huabing; Wu, Peiheng; Yamashita, Tsutomu

    2001-10-01

    Using a newly developed double-side fabrication method, an IJJ stack plus a bow-tie antenna and chokes were integrated in a slice 200 nm thick and singled out from inside a bulk Bi2Sr2CaCu2O8+x (BSCCO) single crystal. The junctions in the fabricated stack were very uniform, and the number of junctions involved was rather controllable. In addition to this method, which can be used to fabricate integrated circuits based on intrinsic Josephson junctions in high temperature (Tc) superconductors, also reported will be terahertz responses of IJJs, and the possible applications in quantum voltage standard, spectroscopy, and so on.

  20. Performance and applications of gallium-nitride monolithic microwave integrated circuits (GaN MMICs)

    NASA Astrophysics Data System (ADS)

    Scott, Jonathan B.; Parker, Anthony E.

    2007-12-01

    The evolution of wide-bandgap semiconductor transistor technology is placed in historical context with other active device technologies. The relative rapidity of GaN transistor development is noted and is attributed to the great parallel activity in the lighting sector and the historical experience and business model from the III-V compound semiconductor sector. The physical performance expectations for wide-bandgap technologies such as Gallium-Nitride Field-Effect Transistors (GaN FETs) are reviewed. We present some device characteristics. Challenges met in characterising, and prospects for modeling GaN FETs are described. Reliability is identified as the final remaining hurdle facing would-be foundries. Evolutionary and unsurprising applications as well as novel and revolutionary applications are suggested. Novel applications include wholly monolithic switchmode power supplies, simplified tools for ablation and diathermy in tissue, and very wide dynamic range circuits for audio or low phase noise signal generation. We conclude that now is the time to embark on circuit design of MMICs in wide-bandgap technology. The potential for fabless design groups to capitalise upon design IP without strong geopraphic advantage is noted.

  1. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    NASA Astrophysics Data System (ADS)

    Gao, W.; Liu, H.; Gan, B.; Hu, Y.

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e- to 180,000e-, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e- at zero farad plus 5.4 e- per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  2. VHiSSI: Experimental Spacefibre Asic

    NASA Astrophysics Data System (ADS)

    Gonzalez Villafranca, Alberto; Ferrer, Albert; McLaren, David; McClements, Chris; Parkes, Steve

    2015-09-01

    SpaceFibreis the next generation data link and network technology being developed by University of Dundee for the European Space Agency. This high-speed technology runs over both copper and fibre optic cables and is backwards compatible with the ubiquitous SpaceWire technology. SpaceFibre provides 12 times the throughput of a SpW link (2.5 Gbps) with current flight qualified technology together with inbuilt QoS and FDIR capabilities. This paper details the first implementation of SpaceFibre in a radiation tolerant device in the frame of the VHiSSI project. The functionality of this ASIC chip is explained and the results of the functional and Total Ionising Dose and Single Event Effect radiation testing are detailed.

  3. Development of a multi-channel readout ASIC for a fast neutron spectrometer based on GEM-TPC

    NASA Astrophysics Data System (ADS)

    He, Li; Deng, Zhi; Liu, Yi-Nong; Li, Yu-Lan

    2014-10-01

    A multi-channel front-end ASIC has been developed for a fast neutron spectrometer based on Gas Electron Multiplier (GEM)-Time Projection Chamber (TPC). Charge Amplifier and Shaping Amplifier for GEM (CASAGEM) integrates 16+1 channels: 16 channels for anodes and 1 channel for cathode. The gain and the shaping time are adjustable from 2 to 40 mV/fC and from 20 to 80 ns, respectively. The prototype ASIC is fabricated in 0.35 μm CMOS process. An evaluation Print Circuit Board (PCB) was also developed for chip tests. In total 20 chips have been tested. The integrated nonlinearity is less than 1%. The equivalent noise electrons is less than 2000e when the input capacitor is 50 pF. The time jitter is less than 1 ns. The design and the test results are presented in the paper.

  4. Acid-sensing ion channels (ASICs) in the taste buds of adult zebrafish.

    PubMed

    Viña, E; Parisi, V; Cabo, R; Laurà, R; López-Velasco, S; López-Muñiz, A; García-Suárez, O; Germanà, A; Vega, J A

    2013-03-01

    In detecting chemical properties of food, different molecules and ion channels are involved including members of the acid-sensing ion channels (ASICs) family. Consistently ASICs are present in sensory cells of taste buds of mammals. In the present study the presence of ASICs (ASIC1, ASIC2, ASIC3 and ASIC4) was investigated in the taste buds of adult zebrafish (zASICs) using Western blot and immunohistochemistry. zASIC1 and zASIC3 were regularly absent from taste buds, whereas faint zASIC2 and robust zASIC4 immunoreactivities were detected in sensory cells. Moreover, zASIC2 also immunolabelled nerves supplying taste buds. The present results demonstrate for the first time the presence of zASICs in taste buds of teleosts, with different patterns to that occurring in mammals, probably due to the function of taste buds in aquatic environment and feeding. Nevertheless, the role of zASICs in taste remains to be demonstrated. PMID:23328442

  5. ASIC2 Subunits Facilitate Expression at the Cell Surface and Confer Regulation by PSD-95

    PubMed Central

    Harding, Anne Marie S.; Kusama, Nobuyoshi; Hattori, Tomonori; Gautam, Mamta; Benson, Christopher J.

    2014-01-01

    Acid-sensing ion channels (ASICs) are Na+ channels activated by changes in pH within the peripheral and central nervous systems. Several different isoforms of ASICs combine to form trimeric channels, and their properties are determined by their subunit composition. ASIC2 subunits are widely expressed throughout the brain, where they heteromultimerize with their partnering subunit, ASIC1a. However, ASIC2 contributes little to the pH sensitivity of the channels, and so its function is not well understood. We found that ASIC2 increased cell surface levels of the channel when it is coexpressed with ASIC1a, and genetic deletion of ASIC2 reduced acid-evoked current amplitude in mouse hippocampal neurons. Additionally, ASIC2a interacted with the neuronal synaptic scaffolding protein PSD-95, and PSD-95 reduced cell surface expression and current amplitude in ASICs that contain ASIC2a. Overexpression of PSD-95 also reduced acid-evoked current amplitude in hippocampal neurons. This result was dependent upon ASIC2 since the effect of PSD-95 was abolished in ASIC2−/− neurons. These results lend support to an emerging role of ASIC2 in the targeting of ASICs to surface membranes, and allows for interaction with PSD-95 to regulate these processes. PMID:24699665

  6. Nanomaterials, Devices and Interface Circuits: Applications for Optoelectronic and Energy Harvesting

    NASA Astrophysics Data System (ADS)

    Purahmad, Mohsen

    developed a model which strongly conciliates some strongly divergent opinions behind operation of the semiconductor piezoelectric nano-generators. In order to develop such a physics-based model, first the electrostatic potential and depletion width in piezoelectric semiconductor NWs are derived by considering a non-depleted region and a surface depleted region and solving the Poisson equation. By determining the piezoelectric induced charge density, in terms of equivalent density of charges, the effect of piezoelectric charges on the surface depletion region and the distributed electric potential in NW have been investigated. The numerical results demonstrate that the ZnO NWs with smaller radii have a larger surface depletion region which results in a stronger surface potential and depletion region perturbation by induced piezoelectric charges. In the last part of our study on piezoelectric energy harvesters the low power interface circuits which are one of the fundamental building blocks of any self-powered devices has been studied. Utilization of piezoelectric energy harvesters to power electronic devices has attracted significant attention recently. However, the power generated by a piezoelectric energy harvester is too small to power an electronic device directly. Hence, a low power, efficient interface circuit between the energy harvester and a storage unit is essential in any piezoelectric energy harvesting system. Here, a new interface circuit topology for piezoelectric energy harvesting applications is proposed and various design factors for circuit-level optimization are discussed. In the proposed interface circuit a peak detector circuit operating in the sub-threshold region with power dissipation around 160 nW together with a delay circuit form the control block, which is one of the more important units of the piezoelectric energy harvesting systems. (Abstract shortened by UMI.)

  7. Development of a Position Decoding ASIC for SPECT using Silicon Photomultiplier

    NASA Astrophysics Data System (ADS)

    Cho, M.; Kim, H.; Lim, K. T.; Cho, G.

    2016-01-01

    Single Photon Emission Computed Tomography(SPECT) is a widely used diagnosis modality for detecting metabolic diseases. In general, SPECT system is consisted of a sensor, a pre-amplifier, position decoding circuits(PDC) and a data acquisition(DAQ) system. Due to such complexity, it is quite costly to assemble SPECT system by putting discrete components together. Moreover, using discrete components would make the system rather bulky. In this work, we designed a channel module ASIC for SPECT system. This system was composed of a transimpedance amplifier(TIA), comparators and digital logics. In this particular module, a TIA was selected as a preamplifier because the decay time and the rise time are shorter than that of other preamplifier topologies. In the proposed module, the amplified pulse from the TIA was split into two separate signals and each signal was then fed into two comparators with different reference levels, e.g., a low and high level. Then an XOR gate combined the comparator outputs and the output of XOR gate was sent to the suceeding digital logic. Furthermore, the output of each component in the module is composed of a signal packet. The packet includes the information on the energy, the time and the position of the incident photon. The energy and position information of a detected radiation can be derived from the output of the D-flipflop(DFF) in the module via time-over-threshold(TOT). The timing information was measured using a delayed rising edge from the low-level referenced comparator. There are several advantages in developing the channel module ASIC. First of all, the ASIC has only digital outputs and thus a correction circuit for analog signal distortion can be neglected. In addition, it is possible to cut down the system production cost because the volume of the system can be reduced due to the compactness of ASIC. The benefits of channel module is not only limited to SPECT but also beneficial to many other radiation detecting systems.

  8. Carbon Nanotube Self-Gating Diode and Application in Integrated Circuits.

    PubMed

    Si, Jia; Liu, Lijun; Wang, Fanglin; Zhang, Zhiyong; Peng, Lian-Mao

    2016-07-26

    A nano self-gating diode (SGD) based on nanoscale semiconducting material is proposed, simulated, and realized on semiconducting carbon nanotubes (CNTs) through a doping-free fabrication process. The relationships between the performance and material/structural parameters of the SGD are explored through numerical simulation and verified by experiment results. Based on these results, performance optimization strategy is outlined, and high performance CNT SGDs are fabricated and demonstrated to surpass other published CNT diodes. In particular the CNT SGD exhibits high rectifier factor of up to 1.4 × 10(6) while retains large on-state current. Benefiting from high yield and stability, CNT SGDs are used for constructing logic and analog integrated circuits. Two kinds of basic digital gates (AND and OR) have been realized on chip through using CNT SGDs and on-chip Ti wire resistances, and a full wave rectifier circuit has been demonstrated through using two CNT SGDs. Although demonstrated here using CNT SGDs, this device structure may in principle be implemented using other semiconducting nanomaterials, to provide ideas and building blocks for electronic applications based on nanoscale materials. PMID:27322134

  9. [Acid-Sensing Ion Channels (ASICs) in pain].

    PubMed

    Lingueglia, Eric

    2014-01-01

    The discovery of new drug targets represents a real opportunity for developing fresh strategies against pain. Ion channels are interesting targets because they are directly involved in the detection and the transmission of noxious stimuli by sensory fibres of the peripheral nervous system and by neurons of the spinal cord. Acid-Sensing Ion Channels (ASICs) have emerged as important players in the pain pathway. They are neuronal, voltage-independent depolarizing sodium channels activated by extracellular protons. The ASIC family comprises several subunits that need to associate into homo- or hetero-trimers to form a functional channel. The ASIC1 and ASIC3 isoforms are particularly important in sensory neurons, whereas ASIC1a, alone or in association with ASIC2, is essential in the central nervous system. The potent analgesic effects associated with their inhibition in animals (which can be comparable to those of morphine) and data suggesting a role in human pain illustrate the therapeutic potential of these channels. PMID:24948015

  10. Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

    SciTech Connect

    Khalid, Farah F.; Deptuch, Grzegorz; Shenai, Alpana; Yarema, Raymond J.; /Fermilab

    2010-11-01

    Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.

  11. Monolithic active pixel matrix with binary counters (MAMBO III) ASIC

    SciTech Connect

    Khalid, Farah; Deptuch, Grzegorz; Shenai, Alpana; Yarema, Raymond; /Fermilab

    2010-01-01

    Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.

  12. Improving Design Efficiency for Large-Scale Heterogeneous Circuits

    NASA Astrophysics Data System (ADS)

    Gregerson, Anthony

    Despite increases in logic density, many Big Data applications must still be partitioned across multiple computing devices in order to meet their strict performance requirements. Among the most demanding of these applications is high-energy physics (HEP), which uses complex computing systems consisting of thousands of FPGAs and ASICs to process the sensor data created by experiments at particles accelerators such as the Large Hadron Collider (LHC). Designing such computing systems is challenging due to the scale of the systems, the exceptionally high-throughput and low-latency performance constraints that necessitate application-specific hardware implementations, the requirement that algorithms are efficiently partitioned across many devices, and the possible need to update the implemented algorithms during the lifetime of the system. In this work, we describe our research to develop flexible architectures for implementing such large-scale circuits on FPGAs. In particular, this work is motivated by (but not limited in scope to) high-energy physics algorithms for the Compact Muon Solenoid (CMS) experiment at the LHC. To make efficient use of logic resources in multi-FPGA systems, we introduce Multi-Personality Partitioning, a novel form of the graph partitioning problem, and present partitioning algorithms that can significantly improve resource utilization on heterogeneous devices while also reducing inter-chip connections. To reduce the high communication costs of Big Data applications, we also introduce Information-Aware Partitioning, a partitioning method that analyzes the data content of application-specific circuits, characterizes their entropy, and selects circuit partitions that enable efficient compression of data between chips. We employ our information-aware partitioning method to improve the performance of the hardware validation platform for evaluating new algorithms for the CMS experiment. Together, these research efforts help to improve the efficiency

  13. Heterostructure-based high-speed/high-frequency electronic circuit applications

    NASA Astrophysics Data System (ADS)

    Zampardi, P. J.; Runge, K.; Pierson, R. L.; Higgins, J. A.; Yu, R.; McDermott, B. T.; Pan, N.

    1999-08-01

    With the growth of wireless and lightwave technologies, heterostructure electronic devices are commodity items in the commercial marketplace [Browne J. Power-amplifier MMICs drive commercial circuits. Microwaves & RF, 1998. p. 116-24.]. In particular, HBTs are an attractive device for handset power amplifiers at 900 MHz and 1.9 GHz for CDMA applications [Lum E. GaAs technology rides the wireless wave. Proceedings of the 1997 GaAs IC Symposium, 1997. p. 11-13; "Rockwell Ramps Up". Compound Semiconductor, May/June 1997.]. At higher frequencies, both HBTs and p-HEMTs are expected to dominate the marketplace. For high-speed lightwave circuit applications, heterostructure based products on the market for OC-48 (2.5 Gb/s) and OC-192 (10 Gb/s) are emerging [http://www.nb.rockwell.com/platforms/network_access/nahome.html#5.; http://www.nortel.com/technology/opto/receivers/ptav2.html.]. Chips that operate at 40 Gb/ have been demonstrated in a number of research laboratories [Zampardi PJ, Pierson RL, Runge K, Yu R, Beccue SM, Yu J, Wang KC. hybrid digital/microwave HBTs for >30 Gb/s optical communications. IEDM Technical Digest, 1995. p. 803-6; Swahn T, Lewin T, Mokhtari M, Tenhunen H, Walden R, Stanchina W. 40 Gb/s 3 Volt InP HBT ICs for a fiber optic demonstrator system. Proceedings of the 1996 GaAs IC Symposium, 1996. p. 125-8; Suzuki H, Watanabe K, Ishikawa K, Masuda H, Ouchi K, Tanoue T, Takeyari R. InP/InGaAs HBT ICs for 40 Gbit/s optical transmission systems. Proceedings of the 1997 GaAs IC Symposium, 1997. p. 215-8]. In addition to these two markets, another area where heterostructure devices are having significant impact is for data conversion [Walden RH. Analog-to digital convertor technology comparison. Proceedings of the 1994 GaAs IC Symposium, 1994. p. 217-9; Poulton K, Knudsen K, Corcoran J, Wang KC, Nubling RB, Chang M-CF, Asbeck PM, Huang RT. A 6-b, 4 GSa/s GaAs HBT ADC. IEEE J Solid-State Circuits 1995;30:1109-18; Nary K, Nubling R, Beccue S, Colleran W

  14. Review of hybrid pixel detector readout ASICs for spectroscopic X-ray imaging

    NASA Astrophysics Data System (ADS)

    Ballabriga, R.; Alozy, J.; Campbell, M.; Frojdh, E.; Heijne, E. H. M.; Koenig, T.; Llopart, X.; Marchal, J.; Pennicard, D.; Poikela, T.; Tlustos, L.; Valerio, P.; Wong, W.; Zuber, M.

    2016-01-01

    Semiconductor detector readout chips with pulse processing electronics have made possible spectroscopic X-ray imaging, bringing an improvement in the overall image quality and, in the case of medical imaging, a reduction in the X-ray dose delivered to the patient. In this contribution we review the state of the art in semiconductor-detector readout ASICs for spectroscopic X-ray imaging with emphasis on hybrid pixel detector technology. We discuss how some of the key challenges of the technology (such as dealing with high fluxes, maintaining spectral fidelity, power consumption density) are addressed by the various ASICs. In order to understand the fundamental limits of the technology, the physics of the interaction of radiation with the semiconductor detector and the process of signal induction in the input electrodes of the readout circuit are described. Simulations of the process of signal induction are presented that reveal the importance of making use of the small pixel effect to minimize the impact of the slow motion of holes and hole trapping in the induced signal in high-Z sensor materials. This can contribute to preserve fidelity in the measured spectrum with relatively short values of the shaper peaking time. Simulations also show, on the other hand, the distortion in the energy spectrum due to charge sharing and fluorescence photons when the pixel pitch is decreased. However, using recent measurements from the Medipix3 ASIC, we demonstrate that the spectroscopic information contained in the incoming photon beam can be recovered by the implementation in hardware of an algorithm whereby the signal from a single photon is reconstructed and allocated to the pixel with the largest deposition.

  15. Terahertz imaging technique and application in large scale integrated circuit failure inspection

    NASA Astrophysics Data System (ADS)

    Di, Zhi-gang; Yao, Jian-quan; Jia, Chun-rong; Xu, De-gang; Bing, Pi-bin; Yang, Peng-fei; Zheng, Yi-bo

    2010-11-01

    Terahertz ray, as a new style optic source, usually means the electromagnetic whose frequencies lies in between 0.1THz~10THz, the waveband region of the electromagnetic spectrum lies in the gap between microwaves and infrared ray. With the development of laser techniques, quantum trap techniques and compound semiconductor techniques, many new terahertz techniques have been pioneered, motivated in part by the vast range of possible applications for terahertz imaging, sensing, and spectroscopy. THz imaging technique was introduced, and THz imaging can give us not only the density picture but also the phase information within frequency domain. Consequently, images of suspicious objects such as concealed metallic or metal weapons are much sharper and more readily identified when imaged with THz imaging scanners. On the base of these, the application of THz imaging in nondestructive examination, more concretely in large scale circuit failure inspection was illuminated, and the important techniques of this application were introduced, also future prospects were discussed. With the development of correlative technology of THz, we can draw a conclusion that THz imaging technology will have nice application foreground.

  16. An embedded nonvolatile memory cell with spacer floating gate for power management integrated circuit applications

    NASA Astrophysics Data System (ADS)

    Na, Kee-Yeol; Baek, Ki-Ju; Lee, Gun-Woong; Kim, Yeong-Seuk

    2013-08-01

    This paper describes a simple nonvolatile memory cell with a poly-Si spacer floating gate for power management integrated circuit applications. The proposed memory cell is fabricated using a 0.35 μm double-poly high-voltage CMOS process which includes PIP capacitor, LV (5 V), and HV (20 V) CMOS devices. The floating gates of the proposed cell are buried under a LDD spacer oxide; thus the unit cell can be scaled easily in the channel length direction. In addition, any extra photo masking step is not required for the proposed cell in the applied fabrication process. The proposed cell shows an acceptable threshold voltage window of up to 104 cycles and less than 2% threshold voltage shifts in an 85 °C retention test.

  17. Graphene-based tunable non-foster circuit for VHF applications

    NASA Astrophysics Data System (ADS)

    Tian, Jing; Nagarkoti, Deepak Singh; Rajab, Khalid Z.; Hao, Yang

    2016-06-01

    This paper presents a negative impedance converter (NIC) based on graphene field effect transistors (GFETs) for VHF applications. The NIC is designed following Linvill's open circuit stable (OCS) topology. The DC modelling parameters of GFET are extracted from a device measured by Meric et al. [IEEE Electron Devices Meeting, 23.2.1 (2010)] Estimated parasitics are also taken into account. Simulation results from Keysight Advanced Design System (ADS) show good NIC performance up to 200 MHz and the value of negative capacitance is directly proportional to the capacitive load. In addition, it has been shown that by varying the supply voltage the value of negative capacitance can also be tuned. The NIC stability has been tested up to 2 GHz (10 times the maximum operation frequency) using Nyquist stability criterion to ensure there are no oscillation issues.

  18. Radiation-hardened CMOS integrated circuit development for space nuclear power applications

    NASA Astrophysics Data System (ADS)

    Gover, J. E.; Gregory, B. L.

    Examination of the types of systems required for space nuclear power applications suggests a need for microelectronics technology that can function during and after exposure to radiation levels exceeding 1 x 10 to the 16th neutrons/sq cm and gamma ray doses in excess of 1 x 10 to the 7th rad(Si). Radiation-hardened Complimentary Metal Oxide Silicon and Silicon Nitride Oxide Silicon (SNOS) ICs presently in development at Sandia National Laboratories' Center for Radiation-Hardened Microelectronics satisfy these radiation requirements. Future integrated circuit development will further advance the radiation hardness capabilities while extending the IC technology to 32-bit enhanced microprocessors and 1-Mbyte SNOS EEPROM memories.

  19. DSP filters in FPGAs for image processing applications

    NASA Astrophysics Data System (ADS)

    Taylor, Brad

    1996-10-01

    Real-time video-rate image processing requires orders of magnitude performance beyond the capabilities of general purpose computers. ASICs deliver the required performance, however they have the drawback of fixed functionality. Field programmable gate arrays (FPGAs) are reprogrammable SRAM based ICs capable of real-time image processing. FPGAs deliver the benefits of hardware execution speeds and software programmability. An FPGA program creates a custom data processor, which executes the equivalent of hundreds to thousands of lines of C code on the same clock tick. FPGAs emulate circuits which are normally built as ASICs. Multiple real-time video streams can be processed in Giga Operations' Spectrum Reconfigurable Computing (RC) PlatformTM. The Virtual Bus ArchitectureTM enables the same hardware to be configured into many image processing architectures, including 32-bit pipelines, global busses, rings, and systolic arrays. This allows an efficient mapping of data flows and memory access for many image processing applications and the implementation of many real-time DSP filters, including convolutions, morphological operators, and recoloring and resampling algorithms. FPGAs provide significant price/performance benefits versus ASICs where time to market, cost to market, and technical risk are issues. And FPGA descriptions migrate efficiently and easily into ASICs for downstream cost reduction.

  20. Synchronous and asynchronous multiplexer circuits for medical imaging realized in CMOS 0.18um technology

    NASA Astrophysics Data System (ADS)

    Długosz, R.; Iniewski, K.

    2007-05-01

    Multiplexers are one of the most important elements in readout front-end ASICs for multi-element detectors in medical imaging. The purpose of these ASICs is to detect signals appearing randomly in many channels and to collect the detected data in an ordered fashion (de-randomization) in order to send it to an external ADC. ASIC output stage functionality can be divided into two: pulse detection and multiplexing. The pulse detection block is responsible for detecting maximum values of signals arriving from the shaper, sending a flag signal indicating that the peak signal has been detected and storing the pulse in an analog memory until read by ADC. The multiplexer in turn is responsible for searching for active flags, controlling the channel that has detected the peak signal and performing reset functions after readout. There are several types of multiplexers proposed in this paper, which can be divided into several classes: synchronous, synchronized and asynchronous. Synchronous circuits require availability of the multiphase clock generator, which increases the power dissipation, but simultaneously provide very convenient mechanism that enables unambiguous choice of the active channel. This characteristics leads to 100% effectiveness in data processing and no data loss. Asynchronous multiplexers do not require clock generators and because of that have simpler structure, are faster and more power efficient, especially when data samples occur seldom at the ASIC's inputs. The main problem of the asynchronous solution is when data on two or more inputs occur almost at the same time, shorter than the multiplexer's reaction time. In this situation some data can be lost. In many applications loss of the order of 1% of the data is acceptable, which makes use of asynchronous multiplexers possible. For applications when the lower loss is desirable a new hierarchy mechanism has been introduced. One of proposed solutions is a synchronized binary tree structure, that uses many

  1. Thermocouple-Signal-Conditioning Circuit

    NASA Technical Reports Server (NTRS)

    Simon, Richard A.

    1991-01-01

    Thermocouple-signal-conditioning circuit acting in conjunction with thermocouple, exhibits electrical behavior of voltage in series with resistance. Combination part of input bridge circuit of controller. Circuit configured for either of two specific applications by selection of alternative resistances and supply voltages. Includes alarm circuit detecting open circuit in thermocouple and provides off-scale output to signal malfunctions.

  2. Printed circuit boards as platform for disposable lab-on-a-chip applications

    NASA Astrophysics Data System (ADS)

    Leiterer, Christian; Urban, Matthias; Fritzsche, Wolfgang; Goldys, Ewa; Inglis, David

    2015-12-01

    An increasing demand in performance from electronic devices has resulted in continuous shrinking of electronic components. This shrinkage has demanded that the primary integration platform, the printed circuit board (PCB), follow this same trend. Today, PCB companies offer ~100 micron sized features (depth and width) which mean they are becoming suitable as physical platforms for Lab-on-a-Chip (LOC) and microfluidic applications. Compared to current lithographic based fluidic approaches; PCB technology offers several advantages that are useful for this technology. These include: Being easily designed and changed using free software, robust structures that can often be reused, chip layouts that can be ordered from commercial PCB suppliers at very low cost (1 AUD each in this work), and integration of electrodes at no additional cost. Here we present the application of PCB technology in connection with microfluidics for several biomedical applications. In case of commercialization the costs for each device can be even further decreased to approximately one tenth of its current cost.

  3. Development of arrays of Silicon Drift Detectors and readout ASIC for the SIDDHARTA experiment

    NASA Astrophysics Data System (ADS)

    Quaglia, R.; Schembari, F.; Bellotti, G.; Butt, A. D.; Fiorini, C.; Bombelli, L.; Giacomini, G.; Ficorella, F.; Piemonte, C.; Zorzi, N.

    2016-07-01

    This work deals with the development of new Silicon Drift Detectors (SDDs) and readout electronics for the upgrade of the SIDDHARTA experiment. The detector is based on a SDDs array organized in a 4×2 format with each SDD square shaped with 64 mm2 (8×8) active area. The total active area of the array is therefore 32×16 mm2 while the total area of the detector (including 1 mm border dead area) is 34 × 18mm2. The SIDDHARTA apparatus requires 48 of these modules that are designed and manufactured by Fondazione Bruno Kessler (FBK). The readout electronics is composed by CMOS preamplifiers (CUBEs) and by the new SFERA (SDDs Front-End Readout ASIC) circuit. SFERA is a 16-channels readout ASIC designed in a 0.35 μm CMOS technology, which features in each single readout channel a high order shaping amplifier (9th order Semi-Gaussian complex-conjugate poles) and a high efficiency pile-up rejection logic. The outputs of the channels are connected to an analog multiplexer for the external analog to digital conversion. An on-chip 12-bit SAR ADC is also included. Preliminary measurements of the detectors in the single SDD format are reported. Also measurements of low X-ray energies are reported in order to prove the possible extension to the soft X-ray range.

  4. Onboard calibration circuit for the DAMPE BGO calorimeter front-end electronics

    NASA Astrophysics Data System (ADS)

    Zhang, De-Liang; Feng, Chang-Qing; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Shen, Zhong-Tao; Jiang, Di; Gao, Shan-Shan; Zhang, Yun-Long; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2016-05-01

    DAMPE (DArk Matter Particle Explorer) is a scientific satellite which is mainly aimed at indirectly searching for dark matter in space. One critical sub-detector of the DAMPE payload is the BGO (bismuth germanium oxide) calorimeter, which contains 1848 PMT (photomultiplier tube) dynodes and 16 FEE (Front-End Electronics) boards. VA160 and VATA160, two 32-channel low power ASICs (Application Specific Integrated Circuits), are adopted as the key components on the FEEs to perform charge measurement for the PMT signals. In order to monitor the parameter drift which may be caused by temperature variation, aging, or other environmental factors, an onboard calibration circuit is designed for the VA160 and VATA160 ASICs. It is mainly composed of a 12-bit DAC (Digital to Analog Converter), an operational amplifier and an analog switch. Test results showed that a dynamic range of 0–30 pC with a precision of 5 fC (Root Meam Square, RMS) was achieved, which covers the VA160’s input range. It can be used to compensate for the temperature drift and test the trigger function of the FEEs. The calibration circuit has been implemented for the front-end electronics of the BGO Calorimeter and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite was launched at the end of 2015 and the calibration circuit will operate periodically in space. Supported by Strategic Priority Research Program on Space Science of Chinese Academy of Sciences (XDA04040202-4), and National Basic Research Program (973 Program) of China (2010CB833002) and National Natural Science Foundation of China (11273070)

  5. Fabrication, electrical characterization, and detection application of graphene-sheet-based electrical circuits

    NASA Astrophysics Data System (ADS)

    Peng, Yitian; Lei, Jianping

    2014-11-01

    The distribution of potential, electric field, and gradient of square of electric field was simulated via a finite element method for dielectrophoresis (DEP) assembly. Then reduced graphene oxide sheets (RGOS)- and graphene oxide sheets (GOS)-based electrical circuits were fabricated via DEP assembly. The mechanically exfoliated graphene sheets (MEGS)-based electrical circuit was also fabricated for comparison. The electrical transport properties of three types of graphene-based electrical circuits were measured. The MEGS-based electrical circuit possesses the best electrical conductivity, and the GOS-based electrical circuit has the poorest electrical conductivity among all three circuits. The three types of electrical circuits were applied for the detection of copper ions (Cu2+). The RGOS-based electrical circuit can detect the Cu2+ when the concentration of Cu2+ was as low as 10 nM in solution. The GOS-based electrical circuit can only detect Cu2+ after chemical reduction. The possible mechanism of electron transfer was proposed for the detection. The facile fabrication method and excellent performance imply the RGOS-based electrical circuit has great potential to be applied to metal ion sensors.

  6. Fabrication, electrical characterization, and detection application of graphene-sheet-based electrical circuits

    PubMed Central

    2014-01-01

    The distribution of potential, electric field, and gradient of square of electric field was simulated via a finite element method for dielectrophoresis (DEP) assembly. Then reduced graphene oxide sheets (RGOS)- and graphene oxide sheets (GOS)-based electrical circuits were fabricated via DEP assembly. The mechanically exfoliated graphene sheets (MEGS)-based electrical circuit was also fabricated for comparison. The electrical transport properties of three types of graphene-based electrical circuits were measured. The MEGS-based electrical circuit possesses the best electrical conductivity, and the GOS-based electrical circuit has the poorest electrical conductivity among all three circuits. The three types of electrical circuits were applied for the detection of copper ions (Cu2+). The RGOS-based electrical circuit can detect the Cu2+ when the concentration of Cu2+ was as low as 10 nM in solution. The GOS-based electrical circuit can only detect Cu2+ after chemical reduction. The possible mechanism of electron transfer was proposed for the detection. The facile fabrication method and excellent performance imply the RGOS-based electrical circuit has great potential to be applied to metal ion sensors. PMID:25593547

  7. A readout circuit for wireless passive LC sensors and its application for gastrointestinal monitoring

    NASA Astrophysics Data System (ADS)

    Bao, Kaikai; Chen, Deyong; Shi, Qiang; Liu, Lijuan; Chen, Jian; Li, Jing; Wang, Junbo

    2014-08-01

    A readout circuit is presented for wireless passive LC sensors, where an inductor-capacitor (LC) resonant circuit was combined with a readout coil for resonant frequency detection. The impedance phase of the readout coil shows a ‘dip’ near the sensor’s resonant frequency due to the mutual inductance. Previously, the phase-dip has suffered from limited amplitude in the low-coupling-coefficient condition (especially in the case of implantation), rendering portable detection troublesome. To address this issue, in this study a new differential transduction circuit was proposed where both theoretical analysis and numerical simulations were performed. Compared to conventional transduction circuits (e.g., the I-V circuit and the auto-balancing bridge circuit), the differential circuit was more sensitive to the phase change, enabling more reliable and precise resonant frequency detection. Moreover, the proposed readout circuit was used to detect the gastrointestinal pressure of rabbits with a Ø10 mm × 14 mm LC pressure sensor at an operational distance of up to 60 mm between the LC sensor and the readout circuit. Experimental results recorded a measurement resolution lower than 0.4 kPa and a measurement speed of eight times per second.

  8. Interface-modified random circuit breaker network model applicable to both bipolar and unipolar resistance switching

    NASA Astrophysics Data System (ADS)

    Lee, S. B.; Lee, J. S.; Chang, S. H.; Yoo, H. K.; Kang, B. S.; Kahng, B.; Lee, M.-J.; Kim, C. J.; Noh, T. W.

    2011-01-01

    We observed reversible-type changes between bipolar (BRS) and unipolar resistance switching (URS) in one Pt/SrTiOx/Pt capacitor. To explain both BRS and URS in a unified scheme, we introduce the "interface-modified random circuit breaker network model," in which the bulk medium is represented by a percolating network of circuit breakers. To consider interface effects in BRS, we introduce circuit breakers to investigate resistance states near the interface. This percolation model explains the reversible-type changes in terms of connectivity changes in the circuit breakers and provides insights into many experimental observations of BRS which are under debate by earlier theoretical models.

  9. System-Level Integrated Circuit (SLIC) Technology Development for Phased Array Antenna Applications

    NASA Technical Reports Server (NTRS)

    Windyka, John A.; Zablocki, Ed G.

    1997-01-01

    This report documents the efforts and progress in developing a 'system-level' integrated circuit, or SLIC, for application in advanced phased array antenna systems. The SLIC combines radio-frequency (RF) microelectronics, digital and analog support circuitry, and photonic interfaces into a single micro-hybrid assembly. Together, these technologies provide not only the amplitude and phase control necessary for electronic beam steering in the phased array, but also add thermally-compensated automatic gain control, health and status feedback, bias regulation, and reduced interconnect complexity. All circuitry is integrated into a compact, multilayer structure configured for use as a two-by-four element phased array module, operating at 20 Gigahertz, using a Microwave High-Density Interconnect (MHDI) process. The resultant hardware is constructed without conventional wirebonds, maintains tight inter-element spacing, and leads toward low-cost mass production. The measured performances and development issues associated with both the two-by-four element module and the constituent elements are presented. Additionally, a section of the report describes alternative architectures and applications supported by the SLIC electronics. Test results show excellent yield and performance of RF circuitry and full automatic gain control for multiple, independent channels. Digital control function, while suffering from lower manufacturing yield, also proved successful.

  10. Fully Programmable Ring-Resonator-Based Integrated Photonic Circuit for Phase Coherent Applications

    NASA Astrophysics Data System (ADS)

    Agarwal, Anjali; Toliver, Paul; Menendez, Ronald; Etemad, Shahab; Jackel, Janet; Young, Jeffrey; Banwell, Thomas; Little, B. E.; Chu, S. T.; Chen, Wei; Chen, Wenlu; Hryniewicz, J.; Johnson, F.; Gill, D.; King, O.; Davidson, R.; Donovan, K.; Delfyett, Peter J.

    2006-01-01

    A novel ring-resonator-based integrated photonic chip with ultrafine frequency resolution, providing programmable, stable, and accurate optical-phase control is demonstrated. The ability to manipulate the optical phase of the individual frequency components of a signal is a powerful tool for optical communications, signal processing, and RF photonics applications. As a demonstration of the power of these components, we report their use as programmable spectral-phase encoders (SPEs) and decoders for wavelength-division-multiplexing (WDM)-compatible optical code-division multiple access (OCDMA). Most important for the application here, the high resolution of these ring-resonator circuits makes possible the independent control of the optical phase of the individual tightly spaced frequency lines of a mode-locked laser (MLL). This unique approach allows us to limit the coded signal's spectral bandwidth, thereby allowing for high spectral efficiency (compared to other OCDMA systems) and compatibility with existing WDM systems with a rapidly reconfigurable set of codes. A four-user OCDMA system using polarization multiplexing is shown to operate at data rates of 2.5 Gb/s within a 40-GHz transparent optical window with a bit error rate (BER) better than 10-9 and a spectral efficiency of 25%.