Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

NASA Technical Reports Server (NTRS)

Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

2015-01-01

Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

Thermal Radiometer Signal Processing using Radiation Hard CMOS Application Specific Integrated Circuits for use in Harsh Planetary Environments

NASA Astrophysics Data System (ADS)

Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

2015-10-01

Thermal radiometers such as proposed for the Europa Clipper flyby mission [1] require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-cm2/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

Development of n+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

NASA Astrophysics Data System (ADS)

Unno, Y.; Kamada, S.; Yamamura, K.; Yamamoto, H.; Hanagaki, K.; Hori, R.; Ikegami, Y.; Nakamura, K.; Takubo, Y.; Takashima, R.; Tojo, J.; Kono, T.; Nagai, R.; Saito, S.; Sugibayashi, K.; Hirose, M.; Jinnouchi, O.; Sato, S.; Sawai, H.; Hara, K.; Sato, Kz.; Sato, Kj.; Iwabuchi, S.; Suzuki, J.

2017-01-01

We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n+-in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC.

PubMed

Xinkai Chen; Xiaoyu Zhang; Linwei Zhang; Xiaowen Li; Nan Qi; Hanjun Jiang; Zhihua Wang

2009-02-01

This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm * 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.

Front End Spectroscopy ASIC for Germanium Detectors

NASA Astrophysics Data System (ADS)

Wulf, Eric

the anode and cathode of the device to allow the depth of the interaction within the crystal to be determined. Dr. De Geronimo has developed similar timing circuits for CZT detector ASICs. Furthermore, the timing circuitry of the ASIC is at the very end of the analog section, simplifying and mitigating risks in the redesign. In the first year, we propose to tweak the gain settings and to add timing to the silicon ASIC to match the requirements of a germanium detector. The design specifications of the ASIC will include advice from our collaborators Dr. Boggs from COSI and Dr. Shih from GRIPS. By using a master ASIC designer to integrate his proven front-end and back-end with only minor modifications, we are maximizing the probability of success. NRL has a commercial cross-strip germanium detector with 30 pF of capacitance per strip, including the flex circuit from the detector to the outside of the cryostat. The COSI and GRIPS detectors have a similar capacitance per strip on the outside of their mechanically cooled cryostat. The second year of the program will be devoted to testing the newly fabricated germanium cross-strip ASIC with the NRL germanium detector. At the end of the second year, NASA will have a TRL 5 ASIC for germanium detectors, allowing future missions, including COSI, GRX, and GRIPS, to operate within their thermal and electrical envelopes. At the end of the third year, a detector on COSI will be instrumented with the new ASIC allowing for a TRL 6 demonstration during the following COSI balloon flight.

pMUT+ASIC integrated platform for wide range ultrasonic imaging

NASA Astrophysics Data System (ADS)

Tillak, J.; Saeed, N.; Khazaaleh, S.; Viegas, J.; Yoo, J.

2017-03-01

We propose an integrated platform of Aluminum Nitrate (AlN) based Piezoelectric Micromachined Ultrasonic Transducer (pMUT) phased array with Application Specific Integrated Circuit (ASIC) for medical imaging and industrial diagnosis. The ASIC provides wide driving range for frequencies between 100 kHz and 5 MHz and channelscalable, programmable application adaptive transmitting beamformer. The system supports operation in various media, including gasses, liquids and biological tissue. The scan resolution for 5 MHz operation is 68 μm in air. The beamformer covers a test volume from -30° to +30° with a step of 3° and scan depth of 10 cm. The ASIC system features low noise receiver electronics, power saving transmission circuitry, and high-voltage drive of large capacitance transducer (up to 500 pF). Integrated pMUT phased array consists of 4 channels of single-membrane ultrasonic transducer of 400 nm deflection and 20 pF feed-thru capacitance, which produce 15 Pa pressure at 500 μm distance from the surface of the transducers. The active area of the ASIC is (700×1490) μm2, which includes channel scalable TX, 8-channale low noise RX, digital back end with autonomous beamformer and power management unit. The system is battery powered with 3.3V-5V standard supply, representing a truly portable solution for ultrasonic applications. Given the CMOS-compatible fabrication process for the AlN pMUTs, dense, miniaturized arrays are possible. Furthermore the smooth surface of dielectric AlN renders optical quality MEMS surfaces for integration in miniaturized photonic + ultrasound microsystems.

Small Microprocessor for ASIC or FPGA Implementation

NASA Technical Reports Server (NTRS)

Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

2011-01-01

A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing

NASA Astrophysics Data System (ADS)

De Matteis, M.; De Blasi, M.; Vallicelli, E. A.; Zannoni, M.; Gervasi, M.; Bau, A.; Passerini, A.; Baschirotto, A.

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μ m technology (12 mm2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing.

PubMed

De Matteis, M; De Blasi, M; Vallicelli, E A; Zannoni, M; Gervasi, M; Bau, A; Passerini, A; Baschirotto, A

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μm technology (12 mm 2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

Design and Measurement of a Low-Noise 64-Channels Front-End Readout ASIC for CdZnTe Detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gan, Bo; Wei, Tingcun; Gao, Wu

Cadmium zinc telluride (CdZnTe) detectors, as one of the principal detectors for the next-generation X-ray and γ-ray imagers, have high energy resolution and supporting electrode patterning in the radiation environment at room-temperature. In the present, a number of internationally renowned research institutions and universities are actively using these detector systems to carry out researches of energy spectrum analysis, medical imaging, materials characterization, high-energy physics, nuclear plant monitoring, and astrophysics. As the most important part of the readout system for the CdZnTe detector, the front-end readout application specific integrated circuit (ASIC) would have an important impact on the performances of themore » whole detector system. In order to ensure the small signal to noise ratio (SNR) and sufficient range of the output signal, it is necessary to design a front-end readout ASIC with very low noise and very high dynamic range. In addition, radiation hardness should be considered when the detectors are utilized in the space applications and high energy physics experiments. In this paper, we present measurements and performances of a novel multi-channel radiation-hardness low-noise front-end readout ASIC for CdZnTe detectors. The readout circuits in each channel consist of charge sensitive amplifier, leakage current compensation circuit (LCC), CR-RC shaper, S-K filter, inverse proportional amplifier, peak detect and hold circuit (PDH), discriminator and trigger logic, time sequence control circuit and driving buffer. All of 64 readout channels' outputs enter corresponding inputs of a 64 channel multiplexer. The output of the mux goes directly out of the chip via the output buffer. The 64-channel readout ASIC is implemented using the TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 2.7 mm x 8 mm. At room temperature, the equivalent noise level of a typical channel reaches 66 e{sup -} (rms) at zero farad for

Controller and data acquisition system for SIDECAR ASIC driven HAWAII detectors

NASA Astrophysics Data System (ADS)

Ramaprakash, Anamparambu; Burse, Mahesh; Chordia, Pravin; Chillal, Kalpesh; Kohok, Abhay; Mestry, Vilas; Punnadi, Sujit; Sinha, Sakya

2010-07-01

SIDECAR is an Application Specific Integrated Circuit (ASIC), which can be used for control and data acquisition from near-IR HAWAII detectors offered by Teledyne Imaging Sensors (TIS), USA. The standard interfaces provided by Teledyne are COM API and socket servers running under MS Windows platform. These interfaces communicate to the ASIC (and the detector) through an intermediate card called JWST ASIC Drive Electronics (JADE2). As part of an ongoing programme of several years, for developing astronomical focal plane array (CCDs, CMOS and Hybrid) controllers and data acquisition systems (CDAQs), IUCAA is currently developing the next generation controllers employing Virtex-5 family FPGA devices. We present here the capabilities which are built into these new CDAQs for handling HAWAII detectors. In our system, the computer which hosts the application programme, user interface and device drivers runs on a Linux platform. It communicates through a hot-pluggable USB interface (with an optional optical fibre extender) to the FPGA-based card which replaces the JADE2. The FPGA board in turn, controls the SIDECAR ASIC and through it a HAWAII-2RG detector, both of which are located in a cryogenic test Dewar set up which is liquid nitrogen cooled. The system can acquire data over 1, 4, or 32 readout channels, with or without binning, at different speeds, can define sub-regions for readout, offers various readout schemes like Fowler sampling, up-theramp etc. In this paper, we present the performance results obtained from a prototype system.

A Muscle Fibre Conduction Velocity Tracking ASIC for Local Fatigue Monitoring.

PubMed

Koutsos, Ermis; Cretu, Vlad; Georgiou, Pantelis

2016-12-01

Electromyography analysis can provide information about a muscle's fatigue state by estimating Muscle Fibre Conduction Velocity (MFCV), a measure of the travelling speed of Motor Unit Action Potentials (MUAPs) in muscle tissue. MFCV better represents the physical manifestations of muscle fatigue, compared to the progressive compression of the myoelectic Power Spectral Density, hence it is more suitable for a muscle fatigue tracking system. This paper presents a novel algorithm for the estimation of MFCV using single threshold bit-stream conversion and a dedicated application-specified integrated circuit (ASIC) for its implementation, suitable for a compact, wearable and easy to use muscle fatigue monitor. The presented ASIC is implemented in a commercially available AMS 0.35 [Formula: see text] CMOS technology and utilizes a bit-stream cross-correlator that estimates the conduction velocity of the myoelectric signal in real time. A test group of 20 subjects was used to evaluate the performance of the developed ASIC, achieving good accuracy with an error of only 3.2% compared to Matlab.

Robust Multivariable Optimization and Performance Simulation for ASIC Design

NASA Technical Reports Server (NTRS)

DuMonthier, Jeffrey; Suarez, George

2013-01-01

Application-specific-integrated-circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power, and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem, which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques, which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable, are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way that facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as a framework of software modules, templates, and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation.

Development of slew-rate-limited time-over-threshold (ToT) ASIC for a multi-channel silicon-based ion detector

NASA Astrophysics Data System (ADS)

Uenomachi, M.; Orita, T.; Shimazoe, K.; Takahashi, H.; Ikeda, H.; Tsujita, K.; Sekiba, D.

2018-01-01

High-resolution Elastic Recoil Detection Analysis (HERDA), which consists of a 90o sector magnetic spectrometer and a position-sensitive detector (PSD), is a method of quantitative hydrogen analysis. In order to increase sensitivity, a HERDA system using a multi-channel silicon-based ion detector has been developed. Here, as a parallel and fast readout circuit from a multi-channel silicon-based ion detector, a slew-rate-limited time-over-threshold (ToT) application-specific integrated circuit (ASIC) was designed, and a new slew-rate-limited ToT method is proposed. The designed ASIC has 48 channels and each channel consists of a preamplifier, a slew-rate-limited shaping amplifier, which makes ToT response linear, and a comparator. The measured equivalent noise charges (ENCs) of the preamplifier, the shaper, and the ToT on no detector capacitance were 253±21, 343±46, and 560±56 electrons RMS, respectively. The spectra from a 241Am source measured using a slew-rate-limited ToT ASIC are also reported.

ASIC1A in neurons is critical for fear-related behaviors.

PubMed

Taugher, R J; Lu, Y; Fan, R; Ghobbeh, A; Kreple, C J; Faraci, F M; Wemmie, J A

2017-11-01

Acid-sensing ion channels (ASICs) have been implicated in fear-, addiction- and depression-related behaviors in mice. While these effects have been attributed to ASIC1A in neurons, it has been reported that ASICs may also function in nonneuronal cells. To determine if ASIC1A in neurons is indeed required, we generated neuron-specific knockout (KO) mice with floxed Asic1a alleles disrupted by Cre recombinase driven by the neuron-specific synapsin I promoter (SynAsic1a KO mice). We confirmed that Cre expression occurred in neurons, but not all neurons, and not in nonneuronal cells including astrocytes. Consequent loss of ASIC1A in some but not all neurons was verified by western blotting, immunohistochemistry and electrophysiology. We found ASIC1A was disrupted in fear circuit neurons, and SynAsic1a KO mice exhibited prominent deficits in multiple fear-related behaviors including Pavlovian fear conditioning to cue and context, predator odor-evoked freezing and freezing responses to carbon dioxide inhalation. In contrast, in the nucleus accumbens ASIC1A expression was relatively normal in SynAsic1a KO mice, and consistent with this observation, cocaine conditioned place preference (CPP) was normal. Interestingly, depression-related behavior in the forced swim test, which has been previously linked to ASIC1A in the amygdala, was also normal. Together, these data suggest neurons are an important site of ASIC1A action in fear-related behaviors, whereas other behaviors likely depend on ASIC1A in other neurons or cell types not targeted in SynAsic1a KO mice. These findings highlight the need for further work to discern the roles of ASICs in specific cell types and brain sites. © 2017 John Wiley & Sons Ltd and International Behavioural and Neural Genetics Society.

Analog front-end design of the STS/MUCH-XYTER2—full size prototype ASIC for the CBM experiment

NASA Astrophysics Data System (ADS)

Kleczek, Rafal

2017-01-01

The design of the analog front-end of the STS/MUCH-XYTER2 ASIC, a full-size prototype chip for the Silicon Tracking System (STS, based on double-sided silicon strip sensors) and Muon Chamber (MUCH, based on gas sensors) detectors is presented. The ASIC contains 128 charge processing channels, each built of a charge sensitive amplifier, a polarity selection circuit and two pulse shaping amplifiers forming two parallel signal paths. The first path is used for timing measurement with a fast discriminator. The second path allows low-noise amplitude measurement with a 5-bit continuous-time flash ADC. Different operating conditions and constraints posed by two target detectors' applications require front-end electronics flexibility to meet extended system-wise requirements. The presented circuit implements switchable shaper peaking time, gain switching and trimming, input amplifier pulsed reset circuit, fail-safe measures. The power consumption is scalable (for the STS and the MUCH modes), but limited to 10 mW/channel.

A front end readout electronics ASIC chip for position sensitive solid state detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kravis, S.D.; Tuemer, T.O.; Visser, G.J.

1998-12-31

A mixed signal Application Specific Integrated Circuit (ASIC) chip for front end readout electronics of position sensitive solid state detectors has been manufactured. It is called RENA (Readout Electronics for Nuclear Applications). This chip can be used for both medical and industrial imaging of X-rays and gamma rays. The RENA chip is a monolithic integrated circuit and has 32 channels with low noise high input impedance charge sensitive amplifiers. It works in pulse counting mode with good energy resolution. It also has a self triggering output which is essential for nuclear applications when the incident radiation arrives at random. Different,more » externally selectable, operational modes that includes a sparse readout mode is available to increase data throughput. It also has externally selectable shaping (peaking) times.« less

Digital circuits using universal logic gates

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)

2004-01-01

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

SPIDR, a general-purpose readout system for pixel ASICs

NASA Astrophysics Data System (ADS)

van der Heijden, B.; Visser, J.; van Beuzekom, M.; Boterenbrood, H.; Kulis, S.; Munneke, B.; Schreuder, F.

2017-02-01

The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a "soft core" CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four 10 Gigabit

Integrated circuit cell library

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

2005-01-01

According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

A Prototype PZT Matrix Transducer With Low-Power Integrated Receive ASIC for 3-D Transesophageal Echocardiography.

PubMed

Chen, Chao; Raghunathan, Shreyas B; Yu, Zili; Shabanimotlagh, Maysam; Chen, Zhao; Chang, Zu-yao; Blaak, Sandra; Prins, Christian; Ponte, Jacco; Noothout, Emile; Vos, Hendrik J; Bosch, Johan G; Verweij, Martin D; de Jong, Nico; Pertijs, Michiel A P

2016-01-01

This paper presents the design, fabrication, and experimental evaluation of a prototype lead zirconium titanate (PZT) matrix transducer with an integrated receive ASIC, as a proof of concept for a miniature three-dimensional (3-D) transesophageal echocardiography (TEE) probe. It consists of an array of 9 ×12 piezoelectric elements mounted on the ASIC via an integration scheme that involves direct electrical connections between a bond-pad array on the ASIC and the transducer elements. The ASIC addresses the critical challenge of reducing cable count, and includes front-end amplifiers with adjustable gains and micro-beamformer circuits that locally process and combine echo signals received by the elements of each 3 ×3 subarray. Thus, an order-of-magnitude reduction in the number of receive channels is achieved. Dedicated circuit techniques are employed to meet the strict space and power constraints of TEE probes. The ASIC has been fabricated in a standard 0.18-μm CMOS process and consumes only 0.44 mW/channel. The prototype has been acoustically characterized in a water tank. The ASIC allows the array to be presteered across ±37° while achieving an overall dynamic range of 77 dB. Both the measured characteristics of the individual transducer elements and the performance of the ASIC are in good agreement with expectations, demonstrating the effectiveness of the proposed techniques.

A Framework for Robust Multivariable Optimization of Integrated Circuits in Space Applications

NASA Technical Reports Server (NTRS)

DuMonthier, Jeffrey; Suarez, George

2013-01-01

Application Specific Integrated Circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way which facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as framework of software modules, templates and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation. Templates provide a starting point for both while toolbox functions minimize the code required. Once a test bench has been coded to optimize a particular circuit, it is also used to verify the final design. The combination of test bench and cost function can then serve as a template for similar circuits or be re-used to migrate the design to different processes by re-running it with the

Development of a 32-channel ASIC for an X-ray APD detector onboard the ISS

NASA Astrophysics Data System (ADS)

Arimoto, Makoto; Harita, Shohei; Sugita, Satoshi; Yatsu, Yoichi; Kawai, Nobuyuki; Ikeda, Hirokazu; Tomida, Hiroshi; Isobe, Naoki; Ueno, Shiro; Mihara, Tatehiro; Serino, Motoko; Kohmura, Takayoshi; Sakamoto, Takanori; Yoshida, Atsumasa; Tsunemi, Hiroshi; Hatori, Satoshi; Kume, Kyo; Hasegawa, Takashi

2018-02-01

We report on the design and performance of a mixed-signal application specific integrated circuit (ASIC) dedicated to avalanche photodiodes (APDs) in order to detect hard X-ray emissions in a wide energy band onboard the International Space Station. To realize wide-band detection from 20 keV to 1 MeV, we use Ce:GAGG scintillators, each coupled to an APD, with low-noise front-end electronics capable of achieving a minimum energy detection threshold of 20 keV. The developed ASIC has the ability to read out 32-channel APD signals using 0.35 μm CMOS technology, and an analog amplifier at the input stage is designed to suppress the capacitive noise primarily arising from the large detector capacitance of the APDs. The ASIC achieves a performance of 2099 e- + 1.5 e-/pF at root mean square (RMS) with a wide 300 fC dynamic range. Coupling a reverse-type APD with a Ce:GAGG scintillator, we obtain an energy resolution of 6.7% (FWHM) at 662 keV and a minimum detectable energy of 20 keV at room temperature (20 °C). Furthermore, we examine the radiation tolerance for space applications by using a 90 MeV proton beam, confirming that the ASIC is free of single-event effects and can operate properly without serious degradation in analog and digital processing.

Improved On-Chip Measurement of Delay in an FPGA or ASIC

NASA Technical Reports Server (NTRS)

Chen, Yuan; Burke, Gary; Sheldon, Douglas

2007-01-01

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Burst Mode ASIC-Based Modem

NASA Technical Reports Server (NTRS)

1997-01-01

The NASA Lewis Research Center is sponsoring the Advanced Communication Technology Insertion (ACTION) for Commercial Space Applications program. The goal of the program is to expedite the development of new technology with a clear path towards productization and enhancing the competitiveness of U.S. manufacturers. The industry has made significant investment in developing ASIC-based modem technology for continuous-mode applications and has made investigations into East, reliable acquisition of burst-mode digital communication signals. With rapid advances in analog and digital communications ICs, it is expected that more functions will be integrated onto these parts in the near future. In addition custom ASIC's can also be developed to address the areas not covered by the other IC's. Using the commercial chips and custom ASIC's, lower-cost, compact, reliable, and high-performance modems can be built for demanding satellite communication application. This report outlines a frequency-hop burst modem design based on commercially available chips.

Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

NASA Astrophysics Data System (ADS)

Gao, W.; Gan, B.; Li, X.; Wei, T.; Gao, D.; Hu, Y.

2015-04-01

In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e- at zero farad plus 10 e- per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source 241Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si).

Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

NASA Astrophysics Data System (ADS)

Zeng, Huiming; Wei, Tingcun; Wang, Jia

2017-03-01

A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal-oxide-semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 μm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e-+16.3e-/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

Driver ASIC Environmental Testing and Performance Optimization for SpaceBased Active Mirrors

NASA Astrophysics Data System (ADS)

Mejia Prada, Camilo

Direct imaging of Earth-like planets requires techniques for light suppression, such as coronagraphs or nulling interferometers, in which deformable mirrors (DM) are a principal component. On ground-based systems, DMs are used to correct for turbulence in the Earth’s atmosphere in addition to static aberrations in the optics. For space-based observations, DMs are used to correct for static and quasi- static aberrations in the optical train. State-of-the-art, high-actuator count deformable mirrors suffer from external heavy and bulky electronics in which electrical connections are made through thousands of wires. We are instead developing Application Specific Integrated Circuits (ASICs) capable of direct integration with the DM in a single small package. This integrated ASIC-DM is ideal for space missions, where it offers significant reduction in mass, power and complexity, and performance compatible with high-contrast observations of exoplanets. We have successfully prototyped and tested a 32x32 format Switch-Mode (SM) ASIC which consumes only 2mW static power (total, not per-actuator). A number of constraints were imposed on key parameters of this ASIC design, including sub-picoamp levels of leakage across turned-off switches and from switch-to-substrate, control resolution of 0.04 mV, satisfactory rise/fall times, and a near-zero on-chip crosstalk over a useful range of operating temperatures. This driver ASIC technology is currently at TRL 4. This Supporting Technology proposal will further develop the ASIC technology to TRL 5 by carrying on environmental tests and further optimizing performance, with the end goal of making ASICs suitable for space-based deployment. The effort will be led by JPL, which has considerable expertise with DMs used in highcontrast imaging systems for exoplanet missions and in adaptive optic systems, and in design of DM driver electronics. Microscale, which developed the prototype of the ASICDM, will continue its development. We

SiGe Integrated Circuit Developments for SQUID/TES Readout

NASA Astrophysics Data System (ADS)

Prêle, D.; Voisin, F.; Beillimaz, C.; Chen, S.; Piat, M.; Goldwurm, A.; Laurent, P.

2018-03-01

SiGe integrated circuits dedicated to the readout of superconducting bolometer arrays for astrophysics have been developed since more than 10 years at APC. Whether for Cosmic Microwave Background (CMB) observations with the QUBIC ground-based experiment (Aumont et al. in astro-ph.IM, 2016. arXiv:1609.04372) or for the Hot and Energetic Universe science theme with the X-IFU instrument on-board of the ATHENA space mission (Barret et al. in SPIE 9905, space telescopes & instrumentation 2016: UV to γ Ray, 2016. https://doi.org/10.1117/12.2232432), several kinds of Transition Edge Sensor (TES) (Irwin and Hilton, in ENSS (ed) Cryogenic particle detection, Springer, Berlin, 2005) arrays have been investigated. To readout such superconducting detector arrays, we use time or frequency domain multiplexers (TDM, FDM) (Prêle in JINST 10:C08015, 2016. https://doi.org/10.1088/1748-0221/10/08/C08015) with Superconducting QUantum Interference Devices (SQUID). In addition to the SQUID devices, low-noise biasing and amplification are needed. These last functions can be obtained by using BiCMOS SiGe technology in an Application Specific Integrated Circuit (ASIC). ASIC technology allows integration of highly optimised circuits specifically designed for a unique application. Moreover, we could reach very low-noise and wide band amplification using SiGe bipolar transistor either at room or cryogenic temperatures (Cressler in J Phys IV 04(C6):C6-101, 1994. https://doi.org/10.1051/jp4:1994616). This paper discusses the use of SiGe integrated circuits for SQUID/TES readout and gives an update of the last developments dedicated to the QUBIC telescope and to the X-IFU instrument. Both ASIC called SQmux128 and AwaXe are described showing the interest of such SiGe technology for SQUID multiplexer controls.

Replication of Space-Shuttle Computers in FPGAs and ASICs

NASA Technical Reports Server (NTRS)

Ferguson, Roscoe C.

2008-01-01

A document discusses the replication of the functionality of the onboard space-shuttle general-purpose computers (GPCs) in field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The purpose of the replication effort is to enable utilization of proven space-shuttle flight software and software-development facilities to the extent possible during development of software for flight computers for a new generation of launch vehicles derived from the space shuttles. The replication involves specifying the instruction set of the central processing unit and the input/output processor (IOP) of the space-shuttle GPC in a hardware description language (HDL). The HDL is synthesized to form a "core" processor in an FPGA or, less preferably, in an ASIC. The core processor can be used to create a flight-control card to be inserted into a new avionics computer. The IOP of the GPC as implemented in the core processor could be designed to support data-bus protocols other than that of a multiplexer interface adapter (MIA) used in the space shuttle. Hence, a computer containing the core processor could be tailored to communicate via the space-shuttle GPC bus and/or one or more other buses.

Integrated Cryogenic Electronics Testbed (ICE-T) for Evaluation of Superconductor and Cryo-Semiconductor Integrated Circuits

NASA Astrophysics Data System (ADS)

Dotsenko, V. V.; Sahu, A.; Chonigman, B.; Tang, J.; Lehmann, A. E.; Gupta, V.; Talalevskii, A.; Ruotolo, S.; Sarwana, S.; Webber, R. J.; Gupta, D.

2017-02-01

Research and development of cryogenic application-specific integrated circuits (ASICs), such as high-frequency (tens of GHz) semiconductor and superconductor mixed-signal circuits and large-scale (>10,000 Josephson Junctions) superconductor digital circuits, have long been hindered by the absence of specialized cryogenic test apparatus. During their iterative development phase, most ASICs require many additional input-output lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. We are developing a full suite of modular test apparatus based on cryocoolers that do not consume liquid helium, and support extensive electrical interfaces to standard and custom test equipment. Our design separates the cryogenics from electrical connections, allowing even inexperienced users to conduct testing by simply mounting their ASIC on a removable electrical insert. Thermal connections between the cold stages and the inserts are made with robust thermal links. ICE-T accommodates two independent electrical inserts at the same time. We have designed various inserts, such as universal ones with all 40 or 80 coaxial cables and those with customized wiring and temperature-controlled stages. ICE-T features fast thermal cycling for rapid testing, enables detailed testing over long periods (days to months, if necessary), and even supports automated testing of digital ICs with modular additions.

Design of a video capsule endoscopy system with low-power ASIC for monitoring gastrointestinal tract.

PubMed

Liu, Gang; Yan, Guozheng; Zhu, Bingquan; Lu, Li

2016-11-01

In recent years, wireless capsule endoscopy (WCE) has been a state-of-the-art tool to examine disorders of the human gastrointestinal tract painlessly. However, system miniaturization, enhancement of the image-data transfer rate and power consumption reduction for the capsule are still key challenges. In this paper, a video capsule endoscopy system with a low-power controlling and processing application-specific integrated circuit (ASIC) is designed and fabricated. In the design, these challenges are resolved by employing a microimage sensor, a novel radio frequency transmitter with an on-off keying modulation rate of 20 Mbps, and an ASIC structure that includes a clock management module, a power-efficient image compression module and a power management unit. An ASIC-based prototype capsule, which measures Φ11 mm × 25 mm, has been developed here. Test results show that the designed ASIC consumes much less power than most of the other WCE systems and that its total power consumption per frame is the least. The image compression module can realize high near-lossless compression rate (3.69) and high image quality (46.2 dB). The proposed system supports multi-spectral imaging, including white light imaging and autofluorescence imaging, at a maximum frame rate of 24 fps and with a resolution of 400 × 400. Tests and in vivo trials in pigs have proved the feasibility of the entire system, but further improvements in capsule control and compression performance inside the ASIC are needed in the future.

Data encryption standard ASIC design and development report.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Robertson, Perry J.; Pierson, Lyndon George; Witzke, Edward L.

2003-10-01

This document describes the design, fabrication, and testing of the SNL Data Encryption Standard (DES) ASIC. This device was fabricated in Sandia's Microelectronics Development Laboratory using 0.6 {micro}m CMOS technology. The SNL DES ASIC was modeled using VHDL, then simulated, and synthesized using Synopsys, Inc. software and finally IC layout was performed using Compass Design Automation's CAE tools. IC testing was performed by Sandia's Microelectronic Validation Department using a HP 82000 computer aided test system. The device is a single integrated circuit, pipelined realization of DES encryption and decryption capable of throughputs greater than 6.5 Gb/s. Several enhancements accommodate ATMmore » or IP network operation and performance scaling. This design is the latest step in the evolution of DES modules.« less

The design and development of low- and high-voltage ASICs for space-borne CCD cameras

NASA Astrophysics Data System (ADS)

Waltham, N.; Morrissey, Q.; Clapp, M.; Bell, S.; Jones, L.; Torbet, M.

2017-12-01

The CCD remains the pre-eminent visible and UV wavelength image sensor in space science, Earth and planetary remote sensing. However, the design of space-qualified CCD readout electronics is a significant challenge with requirements for low-volume, low-mass, low-power, high-reliability and tolerance to space radiation. Space-qualified components are frequently unavailable and up-screened commercial components seldom meet project or international space agency requirements. In this paper, we describe an alternative approach of designing and space-qualifying a series of low- and high-voltage mixed-signal application-specific integrated circuits (ASICs), the ongoing development of two low-voltage ASICs with successful flight heritage, and two new high-voltage designs. A challenging sub-system of any CCD camera is the video processing and digitisation electronics. We describe recent developments to improve performance and tolerance to radiation-induced single event latchup of a CCD video processing ASIC originally developed for NASA's Solar Terrestrial Relations Observatory and Solar Dynamics Observatory. We also describe a programme to develop two high-voltage ASICs to address the challenges presented with generating a CCD's bias voltages and drive clocks. A 0.35 μm, 50 V tolerant, CMOS process has been used to combine standard low-voltage 3.3 V transistors with high-voltage 50 V diffused MOSFET transistors that enable output buffers to drive CCD bias drains, gates and clock electrodes directly. We describe a CCD bias voltage generator ASIC that provides 24 independent and programmable 0-32 V outputs. Each channel incorporates a 10-bit digital-to-analogue converter, provides current drive of up to 20 mA into loads of 10 μF, and includes current-limiting and short-circuit protection. An on-chip telemetry system with a 12-bit analogue-to-digital converter enables the outputs and multiple off-chip camera voltages to be monitored. The ASIC can drive one or more CCDs and

Development of a low-noise, 4th-order readout ASIC for CdZnTe detectors in gamma spectrometer applications

NASA Astrophysics Data System (ADS)

Wang, Jia; Su, Lin; Wei, Xiaomin; Zheng, Ran; Hu, Yann

2016-09-01

This paper presents an ASIC readout circuit development, which aims to achieve low noise. In order to compensate the leakage current and improve gain, a dual-stage CSA has been utilized. A 4th-order high-linearity shaper is proposed to obtain a Semi-Gaussian wave and further decrease the noise induced by the leakage current. The ASIC has been designed and fabricated in a standard commercial 2P4M 0.35 μm CMOS process. Die area of one channel is about 1190 μm×147 μm. The input charge range is 1.8 fC. The peaking time can be adjusted from 1 μs to 3 μs. Measured ENC is about 55e- (rms) at input capacitor of 0 F. The gain is 271 mV/fC at the peaking time of 1 μs.

Latest generation of ASICs for photodetector readout

NASA Astrophysics Data System (ADS)

Seguin-Moreau, N.

2013-08-01

The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the "ROC" family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the "ROC" chips.

TOFPET2: a high-performance ASIC for time and amplitude measurements of SiPM signals in time-of-flight applications

NASA Astrophysics Data System (ADS)

Di Francesco, A.; Bugalho, R.; Oliveira, L.; Pacher, L.; Rivetti, A.; Rolo, M.; Silva, J. C.; Silva, R.; Varela, J.

2016-03-01

We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with 320 pF capacitance the circuit has 24 (30) dB SNR, 75(39) ps r.m.s. resolution, and 4(8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.

A wireless capsule system with ASIC for monitoring the physiological signals of the human gastrointestinal tract.

PubMed

Xu, Fei; Yan, Guozheng; Zhao, Kai; Lu, Li; Gao, Jinyang; Liu, Gang

2014-12-01

This paper presents the design of a wireless capsule system for monitoring the physiological signals of the human gastrointestinal (GI) tract. The primary components of the system include a wireless capsule, a portable data recorder, and a workstation. Temperature, pH, and pressure sensors; an RF transceiver; a controlling and processing application specific integrated circuit (ASIC); and batteries were applied in a wireless capsule. Decreasing capsule size, improving sensor precision, and reducing power needs were the primary challenges; these were resolved by employing micro sensors, optimized architecture, and an ASIC design that include power management, clock management, a programmable gain amplifier (PGA), an A/D converter (ADC), and a serial peripheral interface (SPI) communication unit. The ASIC has been fabricated in 0.18- μm CMOS technology with a die area of 5.0 mm × 5.0 mm. The wireless capsule integrating the ASIC controller measures Φ 11 mm × 26 mm. A data recorder and a workstation were developed, and 20 cases of human experiments were conducted in hospitals. Preprocessing in the workstation can significantly improve the quality of the data, and 76 original features were determined by mathematical statistics. Based on the 13 optimal features achieved in the evaluation of the features, the clustering algorithm can identify the patients who lack GI motility with a recognition rate reaching 83.3%.

Cryogenic and radiation hard ASIC design for large format NIR/SWIR detector

NASA Astrophysics Data System (ADS)

Gao, Peng; Dupont, Benoit; Dierickx, Bart; Müller, Eric; Verbruggen, Geert; Gielis, Stijn; Valvekens, Ramses

2014-10-01

An ASIC is developed to control and data quantization for large format NIR/SWIR detector arrays. Both cryogenic and space radiation environment issue are considered during the design. Therefore it can be integrated in the cryogenic chamber, which reduces significantly the vast amount of long wires going in and out the cryogenic chamber, i.e. benefits EMI and noise concerns, as well as the power consumption of cooling system and interfacing circuits. In this paper, we will describe the development of this prototype ASIC for image sensor driving and signal processing as well as the testing in both room and cryogenic temperature.

Localization and Behaviors in Null Mice Suggest that ASIC1 and ASIC2 Modulate Responses to Aversive Stimuli

PubMed Central

Price, Margaret P.; Gong, Huiyu; Parsons, Meredith G.; Kundert, Jacob R.; Reznikov, Leah R.; Bernardinelli, Luisa; Chaloner, Kathryn; Buchanan, Gordon F.; Wemmie, John A.; Richerson, George B.; Cassell, Martin D.; Welsh, Michael J.

2014-01-01

Acid sensing ion channels (ASICs) generate H+-gated Na+ currents that contribute to neuronal function and animal behavior. Like ASIC1, ASIC2 subunits are expressed in the brain and multimerize with ASIC1 to influence acid-evoked currents and facilitate ASIC1 localization to dendritic spines. To better understand how ASIC2 contributes to brain function, we localized the protein and tested the behavioral consequences of ASIC2 gene disruption. For comparison, we also localized ASIC1 and studied ASIC1−/− mice. ASIC2 was prominently expressed in areas of high synaptic density, and with a few exceptions, ASIC1 and ASIC2 localization exhibited substantial overlap. Loss of ASIC1 or ASIC2 decreased freezing behavior in contextual and auditory cue fear conditioning assays, in response to predator odor, and in response to CO2 inhalation. In addition, loss of ASIC1 or ASIC2 increased activity in a forced swim assay. These data suggest that ASIC2, like ASIC1, plays a key role in determining the defensive response to aversive stimuli. They also raise the question of whether gene variations in both ASIC1 and ASIC2 might affect fear and panic in humans. PMID:24256442

Integrated input protection against discharges for Micro Pattern Gas Detectors readout ASICs

NASA Astrophysics Data System (ADS)

Fiutowski, T.; Dąbrowski, W.; Koperny, S.; Wiącek, P.

2017-02-01

Immunity against possible random discharges inside active detector volume of MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for which the breakdown voltages are in the range of a few Volts. The paper presents the design of various input protection structures integrated in the ASIC manufactured in a 350 nm CMOS process and test results using an electrical circuit to mimic discharges in the detectors.

Coarse Grain Reconfigurable ASIC through Multiplexer Based Switches

DTIC Science & Technology

2015-09-15

chip area (0.5 mm2), and from simulation their power consumption is negligible (0.002% from simulation, too small to measure in physical system...performing implementation that is also flexible. REFERENCES [1] I. Kuon and J. Rose, “ Measuring the gap between FPGAs and ASICs,” IEEE Trans...A 3GPP- LTE Example," Solid-State Circuits, IEEE Journal of , vol.47, no.3, pp.757,768, March 2012. [5] Agarwal, A.; Hassanieh, H.; Abari, O

Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors

NASA Astrophysics Data System (ADS)

Bo, Gan; Tingcun, Wei; Wu, Gao; Yongcai, Hu

2016-06-01

In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 × 2.2 mm2. The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows: the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e- at zero farad plus 8.2 e- per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source 241Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si). Project supported by the National Key Scientific Instrument and Equipment Development Project (No. 2011YQ040082), the National Natural Science Foundation of China (Nos. 11475136, 11575144, 61176094), and the Shaanxi Natural Science Foundation of China (No. 2015JM1016).

Triroc: A Multi-Channel SiPM Read-Out ASIC for PET/PET-ToF Application

NASA Astrophysics Data System (ADS)

Ahmad, Salleh; Fleury, Julien; de la Taille, Christophe; Seguin-Moreau, Nathalie; Dulucq, Frederic; Martin-Chassard, Gisele; Callier, Stephane; Thienpont, Damien; Raux, Ludovic

2015-06-01

Triroc is the latest addition to SiPM readout ASICs family developed at Weeroc, a start-up company from the Omega microelectronics group of IN2P3/CNRS. This chip is developed under the framework TRIMAGE European project which is aimed for building a cost effective tri-modal PET/MR/EEG brain scan. To ensure the flexibility and compatibility with any SiPM in the market, the ASIC is designed to be capable of accepting negative and positive polarity input signals. This 64-channel ASIC, is suitable for SiPM readout which requires high accuracy timing and charge measurements. Targeted applications would be PET prototyping with time-of-flight capability. Main features of Triroc includes high dynamic range ADC up to 2500 photoelectrons and TDC fine time binning of 40 ps. Triroc requires very minimal external components which means it is a good contender for compact multichannel PET prototyping. Triroc is designed by using AMS 0.35 μm SiGe technology and it was submitted in March 2014. The detail design of this chip will be presented.

A fast, low power and low noise charge sensitive amplifier ASIC for a UV imaging single photon detector

NASA Astrophysics Data System (ADS)

Seljak, A.; Cumming, H. S.; Varner, G.; Vallerga, J.; Raffanti, R.; Virta, V.

2017-04-01

NASA has funded, through their Strategic Astrophysics Technology (SAT) program, the development of a cross strip (XS) microchannel plate (MCP) detector with the intention to increase its technology readiness level (TRL), enabling prototyping for future NASA missions. One aspect of the development is to convert the large and high powered laboratory Parallel Cross Strip (PXS) readout electronics into application specific integrated circuits (ASICs) to decrease their mass, volume, and power consumption (all limited resources in space) and to make them more robust to the environments of rocket launch and space. The redesign also foresees to increase the overall readout event rate, and decrease the noise contribution of the readout system. This work presents the design and verification of the first stage for the new readout system, the 16 channel charge sensitive amplifier ASIC, called the CSAv3. The single channel amplifier is composed of a charge sensitive amplifier (pre-amplifier), a pole zero cancellation circuit and a shaping amplifier. An additional output stage buffer allows polarity selection of the output analog signal. The operation of the amplifier is programmable via serial bus. It provides an equivalent noise charge (ENC) of around 600 e^- and a baseline gain of 10 mV/fC. The full scale pulse shaped output signal is confined within 100 ns, without long recovery tails, enabling up to 10 MHz periodic event rates without signal pile up. This ASIC was designed and fabricated in 130 nm, TSMC CMOS 1.2 V technology. In addition, we briefly discuss the construction of the readout system and plans for the future work.

ASIC or PIC? Implantable stimulators based on semi-custom CMOS technology or low-power microcontroller architecture.

PubMed

Salmons, S; Gunning, G T; Taylor, I; Grainger, S R; Hitchings, D J; Blackhurst, J; Jarvis, J C

2001-01-01

To gain a better understanding of the effects of chronic stimulation on mammalian muscles we needed to generate patterns of greater variety and complexity than simple constant-frequency or burst patterns. We describe here two approaches to the design of implantable neuromuscular stimulators that can satisfy these requirements. Devices of both types were developed and used in long-term experiments. The first device was based on a semi-custom Application Specific Integrated Circuit (ASIC). This approach has the advantage that the circuit can be completely tested at every stage of development and production, assuring a high degree of reliability. It has the drawback of inflexibility: the patterns are produced by state machines implemented in silicon, so each new set of patterns requires a fresh production run, which is costly and time-consuming. The second device was based on a commercial microcontroller (Microchip PIC16C84). The functionality of this type of circuit is specified in software rather than in silicon hardware, allowing a single device to be programmed for different functions. With the use of features designed to improve fault-tolerance we found this approach to be as reliable as that based on ASICs. The encapsulated devices can easily be accommodated subcutaneously on the flank of a rabbit and a recent version is small enough to implant into the peritoneal cavity of rats. The current devices are programmed with a predetermined set of 12 patterns before assembly; the desired pattern is selected after implantation with an electronic flash gun. The operating current drain is less than 40 microA.

VEGA: A low-power front-end ASIC for large area multi-linear X-ray silicon drift detectors: Design and experimental characterization

NASA Astrophysics Data System (ADS)

Ahangarianabhari, Mahdi; Macera, Daniele; Bertuccio, Giuseppe; Malcovati, Piero; Grassi, Marco

2015-01-01

We present the design and the first experimental characterization of VEGA, an Application Specific Integrated Circuit (ASIC) designed to read out large area monolithic linear Silicon Drift Detectors (SDD's). VEGA consists of an analog and a digital/mixed-signal section to accomplish all the functionalities and specifications required for high resolution X-ray spectroscopy in the energy range between 500 eV and 50 keV. The analog section includes a charge sensitive preamplifier, a shaper with 3-bit digitally selectable shaping times from 1.6 μs to 6.6 μs and a peak stretcher/sample-and-hold stage. The digital/mixed-signal section includes an amplitude discriminator with coarse and fine threshold level setting, a peak discriminator and a logic circuit to fulfill pile-up rejection, signal sampling, trigger generation, channel reset and the preamplifier and discriminators disabling functionalities. A Serial Peripherical Interface (SPI) is integrated in VEGA for loading and storing all configuration parameters in an internal register within few microseconds. The VEGA ASIC has been designed and manufactured in 0.35 μm CMOS mixed-signal technology in single and 32 channel versions with dimensions of 200 μm×500 μm per channel. A minimum intrinsic Equivalent Noise Charge (ENC) of 12 electrons r.m.s. at 3.6 μs peaking time and room temperature is measured and the linearity error is between -0.9% and +0.6% in the whole input energy range. The total power consumption is 481 μW and 420 μW per channel for the single and 32 channels version, respectively. A comparison with other ASICs for X-ray SDD's shows that VEGA has a suitable low noise and offers high functionality as ADC-ready signal processing but at a power consumption that is a factor of four lower than other similar existing ASICs.

Development of a Position Decoding ASIC for SPECT using Silicon Photomultiplier

NASA Astrophysics Data System (ADS)

Cho, M.; Kim, H.; Lim, K. T.; Cho, G.

2016-01-01

Single Photon Emission Computed Tomography(SPECT) is a widely used diagnosis modality for detecting metabolic diseases. In general, SPECT system is consisted of a sensor, a pre-amplifier, position decoding circuits(PDC) and a data acquisition(DAQ) system. Due to such complexity, it is quite costly to assemble SPECT system by putting discrete components together. Moreover, using discrete components would make the system rather bulky. In this work, we designed a channel module ASIC for SPECT system. This system was composed of a transimpedance amplifier(TIA), comparators and digital logics. In this particular module, a TIA was selected as a preamplifier because the decay time and the rise time are shorter than that of other preamplifier topologies. In the proposed module, the amplified pulse from the TIA was split into two separate signals and each signal was then fed into two comparators with different reference levels, e.g., a low and high level. Then an XOR gate combined the comparator outputs and the output of XOR gate was sent to the suceeding digital logic. Furthermore, the output of each component in the module is composed of a signal packet. The packet includes the information on the energy, the time and the position of the incident photon. The energy and position information of a detected radiation can be derived from the output of the D-flipflop(DFF) in the module via time-over-threshold(TOT). The timing information was measured using a delayed rising edge from the low-level referenced comparator. There are several advantages in developing the channel module ASIC. First of all, the ASIC has only digital outputs and thus a correction circuit for analog signal distortion can be neglected. In addition, it is possible to cut down the system production cost because the volume of the system can be reduced due to the compactness of ASIC. The benefits of channel module is not only limited to SPECT but also beneficial to many other radiation detecting systems.

A High-Performance Deformable Mirror with Integrated Driver ASIC for Space Based Active Optics

NASA Astrophysics Data System (ADS)

Shelton, Chris

Direct imaging of exoplanets is key to fully understanding these systems through spectroscopy and astrometry. The primary impediment to direct imaging of exoplanets is the extremely high brightness ratio between the planet and its parent star. Direct imaging requires a technique for contrast suppression, which include coronagraphs, and nulling interferometers. Deformable mirrors (DMs) are essential to both of these techniques. With space missions in mind, Microscale is developing a novel DM with direct integration of DM and its electronic control functions in a single small envelope. The Application Specific Integrated Circuit (ASIC) is key to the shrinking of the electronic control functions to a size compatible with direct integration with the DM. Through a NASA SBIR project, Microscale, with JPL oversight, has successfully demonstrated a unique deformable mirror (DM) driver ASIC prototype based on an ultra-low power switch architecture. Microscale calls this the Switch-Mode ASIC, or SM-ASIC, and has characterized it for a key set of performance parameters, and has tested its operation with a variety of actuator loads, such as piezo stack and unimorph, and over a wide temperature range. These tests show the SM-ASIC's capability of supporting active optics in correcting aberrations of a telescope in space. Microscale has also developed DMs to go with the SM-ASIC driver. The latest DM version produced uses small piezo stack elements in an 8x8 array, bonded to a novel silicon facesheet structure fabricated monolithically into a polished mirror on one side and mechanical linkage posts that connect to the piezoelectric stack actuators on the other. In this Supporting Technology proposal we propose to further develop the ASIC-DM and have assembled a very capable team to do so. It will be led by JPL, which has considerable expertise with DMs used in Adaptive Optics systems, with high-contrast imaging systems for exoplanet missions, and with designing DM driver

A CMOS ASIC Design for SiPM Arrays

PubMed Central

Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K.; Miyaoka, Robert S.; Rudell, Jacques C.

2012-01-01

Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

ASIC3 channels in multimodal sensory perception.

PubMed

Li, Wei-Guang; Xu, Tian-Le

2011-01-19

Acid-sensing ion channels (ASICs), which are members of the sodium-selective cation channels belonging to the epithelial sodium channel/degenerin (ENaC/DEG) family, act as membrane-bound receptors for extracellular protons as well as nonproton ligands. At least five ASIC subunits have been identified in mammalian neurons, which form both homotrimeric and heterotrimeric channels. The highly proton sensitive ASIC3 channels are predominantly distributed in peripheral sensory neurons, correlating with their roles in multimodal sensory perception, including nociception, mechanosensation, and chemosensation. Different from other ASIC subunit composing ion channels, ASIC3 channels can mediate a sustained window current in response to mild extracellular acidosis (pH 7.3-6.7), which often occurs accompanied by many sensory stimuli. Furthermore, recent evidence indicates that the sustained component of ASIC3 currents can be enhanced by nonproton ligands including the endogenous metabolite agmatine. In this review, we first summarize the growing body of evidence for the involvement of ASIC3 channels in multimodal sensory perception and then discuss the potential mechanisms underlying ASIC3 activation and mediation of sensory perception, with a special emphasis on its role in nociception. We conclude that ASIC3 activation and modulation by diverse sensory stimuli represent a new avenue for understanding the role of ASIC3 channels in sensory perception. Furthermore, the emerging implications of ASIC3 channels in multiple sensory dysfunctions including nociception allow the development of new pharmacotherapy.

An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks.

PubMed

Chen, Huan-Yuan; Chen, Chih-Chang; Hwang, Wen-Jyi

2017-09-28

This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting.

An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks

PubMed Central

Chen, Huan-Yuan; Chen, Chih-Chang

2017-01-01

This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting. PMID:28956859

Defense Industrial Base Assessment: U.S. Integrated Circuit Design and Fabrication Capability

DTIC Science & Technology

2009-05-01

in the U.S for the period 2003-2006, with projections to 2011.6 The resulting draft OTE survey was field tested for accuracy and usability with a...custom application specific integrated circuits (ASICs) to field programmable gate arrays (FPGAs). Companies of all sizes can manufacture these IC...able to design one-time Electronically Programmable Gate Arrays (EPGAs) while nine are able to design Field Programmable Gate Arrays (FPGAs). Eight

Proton and non-proton activation of ASIC channels

PubMed Central

Gautschi, Ivan; van Bemmelen, Miguel Xavier; Schild, Laurent

2017-01-01

The Acid-Sensing Ion Channels (ASIC) exhibit a fast desensitizing current when activated by pH values below 7.0. By contrast, non-proton ligands are able to trigger sustained ASIC currents at physiological pHs. To analyze the functional basis of the ASIC desensitizing and sustained currents, we have used ASIC1a and ASIC2a mutants with a cysteine in the pore vestibule for covalent binding of different sulfhydryl reagents. We found that ASIC1a and ASIC2a exhibit two distinct currents, a proton-induced desensitizing current and a sustained current triggered by sulfhydryl reagents. These currents differ in their pH dependency, their sensitivity to the sulfhydryl reagents, their ionic selectivity and their relative magnitude. We propose a model for ASIC1 and ASIC2 activity where the channels can function in two distinct modes, a desensitizing mode and a sustained mode depending on the activating ligands. The pore vestibule of the channel represents a functional site for binding non-proton ligands to activate ASIC1 and ASIC2 at neutral pH and to prevent channel desensitization. PMID:28384246

Role of ASIC1a in Aβ-induced synaptic alterations in the hippocampus.

PubMed

Mango, D; Nisticò, R

2018-05-01

Acid-sensing ion channels (ASICs) are widely expressed in the mammalian central nervous system where they play a key role in synaptic transmission and in specific forms of memory. On the other hand, ASICs can be persistently active under pathological conditions contributing to neuronal damage in ischemic stroke, brain trauma, epilepsy and Parkinson's disease. However, to date no experimental evidence has linked ASICs to Alzheimer's disease (AD). Aim of the present work was to investigate, in CA1 pyramidal neurons, the possible involvement of ASIC1a in the Aβ-mediated effect on metabotropic glutamate (mGlu) receptor dependent transmission. We found that, in slices pretreated with Aβ, the pharmacological blockade of ASIC1a restored the increased intrinsic excitability following group I mGlu receptor activation. This suggests that, under certain conditions, ASIC1a might further contribute to the Aβ-related depolarizing response. We have recently demonstrated that ASIC1a is also involved long-term depression (LTD) induced either by low-frequency stimulation or by application of the group I mGlu receptor agonist DHPG. Here, we have shown that psalmotoxin-1, a selective blocker of ASIC1a, rescued the DHPG-LTD facilitation associated with genetic and non-genetic models of AD. Overall, these results suggest that a functional coupling between ASIC1a and mGlu receptors occurs and might contribute to the synaptic alterations associated with AD. Copyright © 2018 Elsevier Ltd. All rights reserved.

A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

NASA Technical Reports Server (NTRS)

Smith, Edwyn D.

1991-01-01

Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

A comparative study of the time performance between NINO and FlexToT ASICs

NASA Astrophysics Data System (ADS)

Sarasola, I.; Nemallapudi, M. V.; Gundacker, S.; Sánchez, D.; Gascón, D.; Rato, P.; Marín, J.; Auffray, E.

2017-04-01

Universitat de Barcelona (UB) and CIEMAT have designed the FlexToT ASIC for the front-end readout of SiPM-based scintillator detectors. This ASIC is aimed at time of flight (ToF) positron emission tomography (PET) applications. In this work we have evaluated the time performance of the FlexToT v2 ASIC compared to the NINO ASIC, a fast ASIC developped at CERN. NINO electronics give 64 ps sigma for single-photon time resolution (SPTR) and 93 ps FWHM for coincidence time resolution (CTR) with 2 × 2 × 5 mm3 LSO:Ce,Ca crystals and S13360-3050CS SiPMs. Using the same SiPMs and crystals, the FlexToT v2 ASIC yields 91 ps sigma for SPTR and 123 ps FWHM for CTR. Despite worse time performace than NINO, FlexToT v2 features lower power consumption (11 vs. 27 mW/ch) and linear ToT energy measurement.

A 32-channel front-end ASIC for GEM detectors used in beam monitoring applications

NASA Astrophysics Data System (ADS)

Ciciriello, F.; Altieri, P. R.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Lorusso, L.; Marzocca, C.; Matarrese, G.; Ranieri, A.; Stamerra, A.

2017-11-01

A multichannel, mixed-signal, front-end ASIC for GEM detectors, intended for beam monitoring in hadron therapy applications, has been designed and prototyped in a standard 0.35 μm CMOS technology. The analog channels are based on the classic CSA + shaper processing chain, followed by a peak detector which can work as an analog memory, to simplifiy the analog-to-digital conversion of the peak voltage of the output pulse, proportional to the energy of the detected event. The available hardware resources include an 8-bit A/D converter and a standard-cell digital part, which manages the read-out procedure, in sparse or serial mode. The ASIC is self-triggered and transfers energy and address data to the external DAQ via a fast 100 MHz LVDS link. Preliminary characterization results show that the non-linearity error is limited to 5% for a maximum input charge of about 70 fC, the measured ENC is about 1400e- and the time jitter of the trigger signal generated in response to an injected charge of 60 fC is close to 200 ps.

An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras.

PubMed

Bolotnikov, A E; Ackley, K; Camarda, G S; Cherches, C; Cui, Y; De Geronimo, G; Fried, J; Hodges, D; Hossain, A; Lee, W; Mahler, G; Maritato, M; Petryk, M; Roy, U; Salwen, C; Vernon, E; Yang, G; James, R B

2015-07-01

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm(3) detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays' performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

Development of a dedicated readout ASIC for TPC based X-ray polarimeter

NASA Astrophysics Data System (ADS)

Zhang, Hongyan; Deng, Zhi; Li, Hong; Liu, Yinong; Feng, Hua

2016-07-01

X-ray polarimetry with time projection chambers was firstly proposed by JK Black in 2007 and has been greatly developed since then. It measured two dimensional photoelectron tracks with one dimensional strip and the other dimension was estimated by the drift time from the signal waveforms. A readout ASIC, APV25, originally developed for CMS silicon trackers was used and has shown some limitations such as waveform sampling depth. A dedicated ASIC was developed for TPC based X-ray polarimeters in this paper. It integrated 32 channel circuits and each channel consisted of an analog front-end and a waveform sampler based on switched capacitor array. The analog front-end has a charge sensitive preamplifier with a gain of 25 mV/fC, a CR-RC shaper with a peaking time of 25 ns, a baseline holder and a discriminator for self-triggering. The SCA has a buffer latency of 3.2 μs with 64 cells operating at 20 MSPS. The ASIC was fabricated in a 0.18 μm CMOS process. The equivalent noise charge (ENC) of the analog front-end was measured to be 274.8 e+34.6 e/pF. The effective resolution of the SCA was 8.8 bits at sampling rate up to 50 MSPS. The total power consumption was 2.8 mW per channel. The ASIC was also tested with real TPC detectors and two dimensional photoelectron tracks have been successfully acquired. More tests and analysis on the sensitivity to the polarimetry are undergoing and will be presented in this paper.

CWICOM: A Highly Integrated & Innovative CCSDS Image Compression ASIC

NASA Astrophysics Data System (ADS)

Poupat, Jean-Luc; Vitulli, Raffaele

2013-08-01

The space market is more and more demanding in terms of on image compression performances. The earth observation satellites instrument resolution, the agility and the swath are continuously increasing. It multiplies by 10 the volume of picture acquired on one orbit. In parallel, the satellites size and mass are decreasing, requiring innovative electronic technologies reducing size, mass and power consumption. Astrium, leader on the market of the combined solutions for compression and memory for space application, has developed a new image compression ASIC which is presented in this paper. CWICOM is a high performance and innovative image compression ASIC developed by Astrium in the frame of the ESA contract n°22011/08/NLL/LvH. The objective of this ESA contract is to develop a radiation hardened ASIC that implements the CCSDS 122.0-B-1 Standard for Image Data Compression, that has a SpaceWire interface for configuring and controlling the device, and that is compatible with Sentinel-2 interface and with similar Earth Observation missions. CWICOM stands for CCSDS Wavelet Image COMpression ASIC. It is a large dynamic, large image and very high speed image compression ASIC potentially relevant for compression of any 2D image with bi-dimensional data correlation such as Earth observation, scientific data compression… The paper presents some of the main aspects of the CWICOM development, such as the algorithm and specification, the innovative memory organization, the validation approach and the status of the project.

A design of a valid signal selecting and position decoding ASIC for PET using silicon photomultipliers

NASA Astrophysics Data System (ADS)

Cho, M.; Lim, K.-t.; Kim, H.; Yeom, J.-y.; Kim, J.; Lee, C.; Choi, H.; Cho, G.

2017-01-01

In most cases, a PET system has numerous electrical components and channel circuits and thus it would rather be a bulky product. Also, most existing systems receive analog signals from detectors which make them vulnerable to signal distortions. For these reasons, channel reduction techniques are important. In this work, an ASIC for PET module is being proposed. An ASIC chip for 16 PET detector channels, VSSPDC, has been designed and simulated. The main function of the chip is 16-to-1 channel reduction, i.e., finding the position of only the valid signals, signal timing, and magnitudes in all 16 channels at every recorded event. The ASIC comprises four of 4-channel modules and a 2nd 4-to-1 router. A single channel module comprises a transimpedance amplifier for the silicon photomultipliers, dual comparators with high and low level references, and a logic circuitry. While the high level reference was used to test the validity of the signal, the low level reference was used for the timing. The 1-channel module of the ASIC produced an energy pulse by time-over-threshold method and it also produced a time pulse with a fixed delayed time. Since the ASIC chip outputs only a few digital pulses and does not require an external clock, it has an advantage over noise properties. The cadence simulation showed the good performance of the chip as designed.

Seizure Termination by Acidosis Depends on ASIC1a

PubMed Central

Ziemann, Adam E.; Schnizler, Mikael K.; Albert, Gregory W.; Severson, Meryl A.; Howard, Matthew A.; Welsh, Michael J.; Wemmie, John A.

2008-01-01

SUMMARY Most seizures stop spontaneously. However, the molecular mechanisms remain unknown. Earlier observations that seizures reduce brain pH and that acidosis inhibits seizures indicated that acidosis halts epileptic activity. Because acid–sensing ion channel–1a (ASIC1a) shows exquisite sensitivity to extracellular pH and regulates neuron excitability, we hypothesized that acidosis might activate ASIC1a to terminate seizures. Disrupting mouse ASIC1a increased the severity of chemoconvulsant–induced seizures, whereas overexpressing ASIC1a had the opposite effect. ASIC1a did not affect seizure threshold or onset, but shortened seizure duration and prevented progression. CO2 inhalation, long known to lower brain pH and inhibit seizures, also required ASIC1a to interrupt tonic–clonic seizures. Acidosis activated inhibitory interneurons through ASIC1a, suggesting that ASIC1a might limit seizures by increasing inhibitory tone. These findings identify ASIC1a as a key element in seizure termination when brain pH falls. The results suggest a molecular mechanism for how the brain stops seizures and suggest new therapeutic strategies. PMID:18536711

Abnormal cardiac autonomic regulation in mice lacking ASIC3.

PubMed

Cheng, Ching-Feng; Kuo, Terry B J; Chen, Wei-Nan; Lin, Chao-Chieh; Chen, Chih-Cheng

2014-01-01

Integration of sympathetic and parasympathetic outflow is essential in maintaining normal cardiac autonomic function. Recent studies demonstrate that acid-sensing ion channel 3 (ASIC3) is a sensitive acid sensor for cardiac ischemia and prolonged mild acidification can open ASIC3 and evoke a sustained inward current that fires action potentials in cardiac sensory neurons. However, the physiological role of ASIC3 in cardiac autonomic regulation is not known. In this study, we elucidate the role of ASIC3 in cardiac autonomic function using Asic3(-/-) mice. Asic3(-/-) mice showed normal baseline heart rate and lower blood pressure as compared with their wild-type littermates. Heart rate variability analyses revealed imbalanced autonomic regulation, with decreased sympathetic function. Furthermore, Asic3(-/-) mice demonstrated a blunted response to isoproterenol-induced cardiac tachycardia and prolonged duration to recover to baseline heart rate. Moreover, quantitative RT-PCR analysis of gene expression in sensory ganglia and heart revealed that no gene compensation for muscarinic acetylcholines receptors and beta-adrenalin receptors were found in Asic3(-/-) mice. In summary, we unraveled an important role of ASIC3 in regulating cardiac autonomic function, whereby loss of ASIC3 alters the normal physiological response to ischemic stimuli, which reveals new implications for therapy in autonomic nervous system-related cardiovascular diseases.

Design of a Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

NASA Astrophysics Data System (ADS)

Gao, W.; Liu, H.; Gan, B.; Wei, T.; Gao, D.; Hu, Y.

2014-10-01

In this paper, we present the design and preliminary results of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for a PET imaging system whose objective is to achieve the following performances: the spatial resolution of 1 mm3, the detection efficiency of 15% and the time resolution of 1 ns. A cascode amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuits is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. An eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm ×2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy level of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC. The tested result of ENC is 86.5 e- at zero farad plus 9.3 e- per picofarad. The nonlinearity is less than 3%. The crosstalk is less than 2%. The power dissipation is about 3 mW/channel.

Science Enabling ASICs and FEEs for the JUICE and JEO Missions

NASA Technical Reports Server (NTRS)

Paschalidis, Nicholas; Sittler, Ed; Cooper, John; Christian, Eric; Moore, Tom

2011-01-01

A family of science enabling radiation hard Application Specific Integrated Circuits (ASICs), Front End Electronics (FEEs) and Event Processing Systems, with flight heritage on many NASA missions, is presented. These technologies play an important role in the miniaturization of instruments -and spacecraft systems- at the same time increasing performance and reducing power. The technologies target time of flight, position sensing, and energy measurements as well as standard housekeeping and telemetry functions for particle and fields instruments, but find applications in other instrument categories too. More specifically the technologies include: the TOF chip, 1D and 2D Delay Lines with MCP detectors, for high precision fast and low power time of flight and position sensing; the Energy chip for multichannel SSD readout with time over threshold and standard voltage read out for TDC and ADC digitization; Fast multi channel read out chip with commandable thresholds; the TRIO chip for multiplexed ADC and housekeeping etc. It should be mentioned that the ASICs include basic trigger capabilities to enable random event processing in a heavy background of penetrators and UV foreground. Typical instruments include time of flight versus energy and look angle particle analyzers such as: plasma composition, energetic particle, neutral atom imaging as well as fast plasma and deltaE/E ion/electron telescopes. Flight missions include: Cassini/LEMMS, IMAGE/HENA, MESSENGER/EPPS/MLA/X-ray/MLA, STEREO, PLUTO-NH/PEPSSI/LORI, IBEX-Lo, JUNO/JEDI, RBSP/RBSPICE, MMS/HPCA/EPD, SO/SIS. Given the proven capability on heavy radiation missions such as JUNO, MMS and RBSB, as well diverse long duration missions such as MESSENGER, PLUTO and Cassini, it is expected that these technologies will play an important role in the particle and fields (at least) instruments on the upcoming JUICE and JEO missions.

An Electronic-Nose Sensor Node Based on a Polymer-Coated Surface Acoustic Wave Array for Wireless Sensor Network Applications

PubMed Central

Tang, Kea-Tiong; Li, Cheng-Han; Chiu, Shih-Wen

2011-01-01

This study developed an electronic-nose sensor node based on a polymer-coated surface acoustic wave (SAW) sensor array. The sensor node comprised an SAW sensor array, a frequency readout circuit, and an Octopus II wireless module. The sensor array was fabricated on a large K2 128° YX LiNbO3 sensing substrate. On the surface of this substrate, an interdigital transducer (IDT) was produced with a Cr/Au film as its metallic structure. A mixed-mode frequency readout application specific integrated circuit (ASIC) was fabricated using a TSMC 0.18 μm process. The ASIC output was connected to a wireless module to transmit sensor data to a base station for data storage and analysis. This sensor node is applicable for wireless sensor network (WSN) applications. PMID:22163865

An electronic-nose sensor node based on a polymer-coated surface acoustic wave array for wireless sensor network applications.

PubMed

Tang, Kea-Tiong; Li, Cheng-Han; Chiu, Shih-Wen

2011-01-01

This study developed an electronic-nose sensor node based on a polymer-coated surface acoustic wave (SAW) sensor array. The sensor node comprised an SAW sensor array, a frequency readout circuit, and an Octopus II wireless module. The sensor array was fabricated on a large K(2) 128° YX LiNbO3 sensing substrate. On the surface of this substrate, an interdigital transducer (IDT) was produced with a Cr/Au film as its metallic structure. A mixed-mode frequency readout application specific integrated circuit (ASIC) was fabricated using a TSMC 0.18 μm process. The ASIC output was connected to a wireless module to transmit sensor data to a base station for data storage and analysis. This sensor node is applicable for wireless sensor network (WSN) applications.

Acid-sensing ion channels (ASICs) in the taste buds of adult zebrafish.

PubMed

Viña, E; Parisi, V; Cabo, R; Laurà, R; López-Velasco, S; López-Muñiz, A; García-Suárez, O; Germanà, A; Vega, J A

2013-03-01

In detecting chemical properties of food, different molecules and ion channels are involved including members of the acid-sensing ion channels (ASICs) family. Consistently ASICs are present in sensory cells of taste buds of mammals. In the present study the presence of ASICs (ASIC1, ASIC2, ASIC3 and ASIC4) was investigated in the taste buds of adult zebrafish (zASICs) using Western blot and immunohistochemistry. zASIC1 and zASIC3 were regularly absent from taste buds, whereas faint zASIC2 and robust zASIC4 immunoreactivities were detected in sensory cells. Moreover, zASIC2 also immunolabelled nerves supplying taste buds. The present results demonstrate for the first time the presence of zASICs in taste buds of teleosts, with different patterns to that occurring in mammals, probably due to the function of taste buds in aquatic environment and feeding. Nevertheless, the role of zASICs in taste remains to be demonstrated. Copyright © 2013 Elsevier Ireland Ltd. All rights reserved.

Active counter electrode in a-SiC electrochemical metallization memory

NASA Astrophysics Data System (ADS)

Morgan, K. A.; Fan, J.; Huang, R.; Zhong, L.; Gowers, R.; Ou, J. Y.; Jiang, L.; De Groot, C. H.

2017-08-01

Cu/amorphous-SiC (a-SiC) electrochemical metallization memory cells have been fabricated with two different counter electrode (CE) materials, W and Au, in order to investigate the role of CEs in a non-oxide semiconductor switching matrix. In a positive bipolar regime with Cu filaments forming and rupturing, the CE influences the OFF state resistance and minimum current compliance. Nevertheless, a similarity in SET kinetics is seen for both CEs, which differs from previously published SiO2 memories, confirming that CE effects are dependent on the switching layer material or type. Both a-SiC memories are able to switch in the negative bipolar regime, indicating Au and W filaments. This confirms that CEs can play an active role in a non-oxide semiconducting switching matrix, such as a-SiC. By comparing both Au and W CEs, this work shows that W is superior in terms of a higher R OFF/R ON ratio, along with the ability to switch at lower current compliances making it a favourable material for future low energy applications. With its CMOS compatibility, a-SiC/W is an excellent choice for future resistive memory applications.

Onboard calibration circuit for the DAMPE BGO calorimeter front-end electronics

NASA Astrophysics Data System (ADS)

Zhang, De-Liang; Feng, Chang-Qing; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Shen, Zhong-Tao; Jiang, Di; Gao, Shan-Shan; Zhang, Yun-Long; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

2016-05-01

DAMPE (DArk Matter Particle Explorer) is a scientific satellite which is mainly aimed at indirectly searching for dark matter in space. One critical sub-detector of the DAMPE payload is the BGO (bismuth germanium oxide) calorimeter, which contains 1848 PMT (photomultiplier tube) dynodes and 16 FEE (Front-End Electronics) boards. VA160 and VATA160, two 32-channel low power ASICs (Application Specific Integrated Circuits), are adopted as the key components on the FEEs to perform charge measurement for the PMT signals. In order to monitor the parameter drift which may be caused by temperature variation, aging, or other environmental factors, an onboard calibration circuit is designed for the VA160 and VATA160 ASICs. It is mainly composed of a 12-bit DAC (Digital to Analog Converter), an operational amplifier and an analog switch. Test results showed that a dynamic range of 0-30 pC with a precision of 5 fC (Root Meam Square, RMS) was achieved, which covers the VA160’s input range. It can be used to compensate for the temperature drift and test the trigger function of the FEEs. The calibration circuit has been implemented for the front-end electronics of the BGO Calorimeter and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite was launched at the end of 2015 and the calibration circuit will operate periodically in space. Supported by Strategic Priority Research Program on Space Science of Chinese Academy of Sciences (XDA04040202-4), and National Basic Research Program (973 Program) of China (2010CB833002) and National Natural Science Foundation of China (11273070)

ASICs for the Pluto Energetic Particle Spectrometer Science Investigation on NASA's New Horizons mission to Pluto

NASA Astrophysics Data System (ADS)

Paschalidis, Nicholas; McNutt, Ralph

One of the most critical challenges of the Pluto Energetic Particle Spectrometer Science Inves-tigation (PEPSSI) was to meet the science requirements with a total mass and power of ¡1.5 kg and ¡2.5 W, respectively. A key, enabling technology to achieve these goals was the exten-sive use of high-performance, low-power, application-specific integrated circuits (ASICs) for the miniaturization of the 12-channel solid state detector (SSD) readout system, the time-of-flight (TOF) system, and the power supply and housekeeping systems. The PEPSSI instrument is a TOF-versus-energy, compact particle spectrometer that provides measurements of ions and electrons from 20keV to 1MeV in a 160 x 12 solid angle field of view divided into six dual-channel sectors. TOF, constant fraction discriminator (CFD), energy, peak detector, and temperature, remote input/output (TRIO, housekeeping) ASICs were all used synergistically in the instrument enabling the high science performance within the resource constraints. The ASICs were space qualified in accord with military specifications (Class S) for total radiation dose and single-event effects (SEEs), and, most importantly, for a 2000-hour life test to increase the reliability for the long duration of the mission. PEPSSI flies on-board the New Horizons NASA spacecraft to measure pick-up ions from the Pluto's outgassing atmosphere. The space-craft was launched 19 Jan 2006 and presently is en route to Pluto, having passed Jupiter in early 2007. Closest approach to Pluto will occur in mid-July 2015. The instrument has already produced excellent measurements in interplanetary space and during the traversal of Jupiter's magnetotail in 2007.

Circuit for Communication Over Power Lines

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.; Prokop, Normal F.; Greer, Lawrence C., III; Nappier, Jennifer

2011-01-01

Many distributed systems share common sensors and instruments along with a common power line supplying current to the system. A communication technique and circuit has been developed that allows for the simple inclusion of an instrument, sensor, or actuator node within any system containing a common power bus. Wherever power is available, a node can be added, which can then draw power for itself, its associated sensors, and actuators from the power bus all while communicating with other nodes on the power bus. The technique modulates a DC power bus through capacitive coupling using on-off keying (OOK), and receives and demodulates the signal from the DC power bus through the same capacitive coupling. The circuit acts as serial modem for the physical power line communication. The circuit and technique can be made of commercially available components or included in an application specific integrated circuit (ASIC) design, which allows for the circuit to be included in current designs with additional circuitry or embedded into new designs. This device and technique moves computational, sensing, and actuation abilities closer to the source, and allows for the networking of multiple similar nodes to each other and to a central processor. This technique also allows for reconfigurable systems by adding or removing nodes at any time. It can do so using nothing more than the in situ power wiring of the system.

CNFET-based voltage rectifier circuit for biomedical implantable applications

NASA Astrophysics Data System (ADS)

Tu, Yonggen; Qian, Libo; Xia, Yinshui

2017-02-01

Carbon nanotube field effect transistor (CNFET) shows lower threshold voltage and smaller leakage current in comparison to its CMOS counterpart. In this paper, two kinds of CNFET-based rectifiers, full-wave rectifiers and voltage doubler rectifiers are presented for biomedical implantable applications. Based on the standard 32 nm CNFET model, the electrical performance of CNFET rectifiers is analyzed and compared. Simulation results show the voltage conversion efficiency (VCE) and power conversion efficiency (PCE) achieve 70.82% and 72.49% for CNFET full-wave rectifiers and 56.60% and 61.17% for CNFET voltage double rectifiers at typical 1.0 V input voltage excitation, which are higher than that of CMOS design. Moreover, considering the controllable property of CNFET threshold voltage, the effect of various design parameters on the electrical performance is investigated. It is observed that the VCE and PCE of CNFET rectifier increase with increasing CNT diameter and number of tubes. The proposed results would provide some guidelines for design and optimization of CNFET-based rectifier circuits. Project supported by the National Natural Science Foundation of China (Nos. 61131001, 61404077, 61571248), the Science and Technology Fund of Zhejiang Province (No. 2015C31090), the Natural Science Foundation of Ningbo (No. 2014A610147), State Key Laboratory of ASIC & System (No. 2015KF006) and the K. C. Wong Magna Fund in Ningbo University.

Double-differential recording and AGC using microcontrolled variable gain ASIC.

PubMed

Rieger, Robert; Deng, Shin-Liang

2013-01-01

Low-power wearable recording of biopotentials requires acquisition front-ends with high common-mode rejection for interference suppression and adjustable gain to provide an optimum signal range to a cascading analogue-to-digital stage. A microcontroller operated double-differential (DD) recording setup and automatic gain control circuit (AGC) are discussed which reject common-mode interference and provide tunable gain, thus compensating for imbalance and variation in electrode interface impedance. Custom-designed variable gain amplifiers (ASIC) are used as part of the recording setup. The circuit gain and balance is set by the timing of microcontroller generated clock signals. Measured results are presented which confirm that improved common-mode rejection is achieved compared to a single differential amplifier in the presence of input network imbalance. Practical measured examples further validate gain control suitable for biopotential recording and power-line rejection for wearable ECG and EMG recording. The prototype front-end consumes 318 μW including amplifiers and microcontroller.

Multigigabit optical transceivers for high-data rate military applications

NASA Astrophysics Data System (ADS)

Catanzaro, Brian E.; Kuznia, Charlie

2012-01-01

Avionics has experienced an ever increasing demand for processing power and communication bandwidth. Currently deployed avionics systems require gigabit communication using opto-electronic transceivers connected with parallel optical fiber. Ultra Communications has developed a series of transceiver solutions combining ASIC technology with flip-chip bonding and advanced opto-mechanical molded optics. Ultra Communications custom high speed ASIC chips are developed using an SoS (silicon on sapphire) process. These circuits are flip chip bonded with sources (VCSEL arrays) and detectors (PIN diodes) to create an Opto-Electronic Integrated Circuit (OEIC). These have been combined with micro-optics assemblies to create transceivers with interfaces to standard fiber array (MT) cabling technology. We present an overview of the demands for transceivers in military applications and how new generation transceivers leverage both previous generation military optical transceivers as well as commercial high performance computing optical transceivers.

Evidence for the involvement of ASIC3 in sensory mechanotransduction in proprioceptors

PubMed Central

Lin, Shing-Hong; Cheng, Yuan-Ren; Banks, Robert W.; Min, Ming-Yuan; Bewick, Guy S.; Chen, Chih-Cheng

2016-01-01

Acid-sensing ion channel 3 (ASIC3) is involved in acid nociception, but its possible role in neurosensory mechanotransduction is disputed. We report here the generation of Asic3-knockout/eGFPf-knockin mice and subsequent characterization of heterogeneous expression of ASIC3 in the dorsal root ganglion (DRG). ASIC3 is expressed in parvalbumin (Pv+) proprioceptor axons innervating muscle spindles. We further generate a floxed allele of Asic3 (Asic3f/f) and probe the role of ASIC3 in mechanotransduction in neurite-bearing Pv+ DRG neurons through localized elastic matrix movements and electrophysiology. Targeted knockout of Asic3 disrupts spindle afferent sensitivity to dynamic stimuli and impairs mechanotransduction in Pv+ DRG neurons because of substrate deformation-induced neurite stretching, but not to direct neurite indentation. In behavioural tasks, global knockout (Asic3−/−) and Pv-Cre::Asic3f/f mice produce similar deficits in grid and balance beam walking tasks. We conclude that, at least in mouse, ASIC3 is a molecular determinant contributing to dynamic mechanosensitivity in proprioceptors. PMID:27161260

Improving Design Efficiency for Large-Scale Heterogeneous Circuits

NASA Astrophysics Data System (ADS)

Gregerson, Anthony

Despite increases in logic density, many Big Data applications must still be partitioned across multiple computing devices in order to meet their strict performance requirements. Among the most demanding of these applications is high-energy physics (HEP), which uses complex computing systems consisting of thousands of FPGAs and ASICs to process the sensor data created by experiments at particles accelerators such as the Large Hadron Collider (LHC). Designing such computing systems is challenging due to the scale of the systems, the exceptionally high-throughput and low-latency performance constraints that necessitate application-specific hardware implementations, the requirement that algorithms are efficiently partitioned across many devices, and the possible need to update the implemented algorithms during the lifetime of the system. In this work, we describe our research to develop flexible architectures for implementing such large-scale circuits on FPGAs. In particular, this work is motivated by (but not limited in scope to) high-energy physics algorithms for the Compact Muon Solenoid (CMS) experiment at the LHC. To make efficient use of logic resources in multi-FPGA systems, we introduce Multi-Personality Partitioning, a novel form of the graph partitioning problem, and present partitioning algorithms that can significantly improve resource utilization on heterogeneous devices while also reducing inter-chip connections. To reduce the high communication costs of Big Data applications, we also introduce Information-Aware Partitioning, a partitioning method that analyzes the data content of application-specific circuits, characterizes their entropy, and selects circuit partitions that enable efficient compression of data between chips. We employ our information-aware partitioning method to improve the performance of the hardware validation platform for evaluating new algorithms for the CMS experiment. Together, these research efforts help to improve the efficiency

On-chip enzymatic microbiofuel cell-powered integrated circuits.

PubMed

Mark, Andrew G; Suraniti, Emmanuel; Roche, Jérôme; Richter, Harald; Kuhn, Alexander; Mano, Nicolas; Fischer, Peer

2017-05-16

A variety of diagnostic and therapeutic medical technologies rely on long term implantation of an electronic device to monitor or regulate a patient's condition. One proposed approach to powering these devices is to use a biofuel cell to convert the chemical energy from blood nutrients into electrical current to supply the electronics. We present here an enzymatic microbiofuel cell whose electrodes are directly integrated into a digital electronic circuit. Glucose oxidizing and oxygen reducing enzymes are immobilized on microelectrodes of an application specific integrated circuit (ASIC) using redox hydrogels to produce an enzymatic biofuel cell, capable of harvesting electrical power from just a single droplet of 5 mM glucose solution. Optimisation of the fuel cell voltage and power to match the requirements of the electronics allow self-powered operation of the on-board digital circuitry. This study represents a step towards implantable self-powered electronic devices that gather their energy from physiological fluids.

Development of a low-energy charged particle detector with on-anode ASIC for in-situ plasma measurement in the Earth's magnetosphere

NASA Astrophysics Data System (ADS)

Saito, M.; Saito, Y.; Mukai, T.; Asamura, K.

2009-06-01

The future magnetospheric exploration missions (ex. SCOPE: cross Scale COupling in the Plasma universE) aim to obtain electron 3D distribution function with very fast time resolution below 10 ms to investigate the electron dynamics that is regarded as pivotal in understanding the space plasma phenomena such as magnetic reconnection. This can be achieved by developing a new plasma detector system which is fast in signal processing with small size, light weight and low power consumption. The new detector system consists of stacked micro channel plates and a position sensitive multi-anode detector with on-anode analogue ASIC (Application Specific Integrated Circuits). Multi-anode system usually suffers from false signals caused by mainly two effects. One is the effect of the electrostatic crosstalk between the discrete anodes since our new detector consists of many adjacent anodes with small gaps to increase the detection areas. Our experimental results show that there exists electrostatic crosstalk effect of approximately 10% from the adjacent anodes. The effect of 10% electrostatic crosstalk can be effectively avoided by a suitable discrimination level of the signal processing circuit. Non negligible charge cloud size on the anode also causes false counts. Optimized ASIC for in-situ plasma measurement in the Earth's magnetosphere is under development. The initial electron cloud at the MCP output has angular divergence. Furthermore, space charge effects may broaden the size of the charge cloud. We have obtained the charge cloud size both experimentally and theoretically. Our test model detector shows expected performance that is explained by our studies above.

Capturing a failure of an ASIC in-situ, using infrared radiometry and image processing software

NASA Technical Reports Server (NTRS)

Ruiz, Ronald P.

2003-01-01

Failures in electronic devices can sometimes be tricky to locate-especially if they are buried inside radiation-shielded containers designed to work in outer space. Such was the case with a malfunctioning ASIC (Application Specific Integrated Circuit) that was drawing excessive power at a specific temperature during temperature cycle testing. To analyze the failure, infrared radiometry (thermography) was used in combination with image processing software to locate precisely where the power was being dissipated at the moment the failure took place. The IR imaging software was used to make the image of the target and background, appear as unity. As testing proceeded and the failure mode was reached, temperature changes revealed the precise location of the fault. The results gave the design engineers the information they needed to fix the problem. This paper describes the techniques and equipment used to accomplish this failure analysis.

Design and fabrication of an infrared optical pyrometer ASIC as a diagnostic for shock physics experiments

NASA Astrophysics Data System (ADS)

Gordon, Jared

Optical pyrometry is the sensing of thermal radiation emitted from an object using a photoconductive device to convert photons into electrons, and is an important diagnostic tool in shock physics experiments. Data obtained from an optical pyrometer can be used to generate a blackbody curve of the material prior to and after being shocked by a high speed projectile. The sensing element consists of an InGaAs photodiode array, biasing circuitry, and multiple transimpedance amplifiers to boost the weak photocurrent from the noisy dark current into a signal that can eventually be digitized. Once the circuit elements have been defined, more often than not commercial-off-the-shelf (COTS) components are inadequate to satisfy every requirement for the diagnostic, and therefore a custom application specific design has to be considered. This thesis outlines the initial challenges with integrating the photodiode array block with multiple COTS transimpedance amplifiers onto a single chip, and offers a solution to a comparable optical pyrometer that uses the same type of photodiodes in conjunction with a re-designed transimpedance amplifier integrated onto a single chip. The final design includes a thorough analysis of the transimpedance amplifier along with modeling the circuit behavior which entails schematics, simulations, and layout. An alternative circuit is also investigated that incorporates an approach to multiplex the signals from each photodiode onto one data line and not only increases the viable real estate on the chip, but also improves the behavior of the photodiodes as they are subjected to less thermal load. The optical pyrometer application specific integrated circuit (ASIC) for shock physic experiments includes a transimpedance amplifier (TIA) with a 100 kΩ gain operating at bandwidth of 30 MHz, and an input-referred noise RMS current of 50 nA that is capable of driving a 50 Ω load.

Digital circuits for computer applications: A compilation

NASA Technical Reports Server (NTRS)

1972-01-01

The innovations in this updated series of compilations dealing with electronic technology represent a carefully selected collection of digital circuits which have direct application in computer oriented systems. In general, the circuits have been selected as representative items of each section and have been included on their merits of having universal applications in digital computers and digital data processing systems. As such, they should have wide appeal to the professional engineer and scientist who encounter the fundamentals of digital techniques in their daily activities. The circuits are grouped as digital logic circuits, analog to digital converters, and counters and shift registers.

Microwave integrated circuits for space applications

NASA Technical Reports Server (NTRS)

Leonard, Regis F.; Romanofsky, Robert R.

1991-01-01

Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.

Low-power low-noise mixed-mode VLSI ASIC for infinite dynamic range imaging applications

NASA Astrophysics Data System (ADS)

Turchetta, Renato; Hu, Y.; Zinzius, Y.; Colledani, C.; Loge, A.

1998-11-01

Solid state solutions for imaging are mainly represented by CCDs and, more recently, by CMOS imagers. Both devices are based on the integration of the total charge generated by the impinging radiation, with no processing of the single photon information. The dynamic range of these devices is intrinsically limited by the finite value of noise. Here we present the design of an architecture which allows efficient, in-pixel, noise reduction to a practically zero level, thus allowing infinite dynamic range imaging. A detailed calculation of the dynamic range is worked out, showing that noise is efficiently suppressed. This architecture is based on the concept of single-photon counting. In each pixel, we integrate both the front-end, low-noise, low-power analog part and the digital part. The former consists of a charge preamplifier, an active filter for optimal noise bandwidth reduction, a buffer and a threshold comparator, and the latter is simply a counter, which can be programmed to act as a normal shift register for the readout of the counters' contents. Two different ASIC's based on this concept have been designed for different applications. The first one has been optimized for silicon edge-on microstrips detectors, used in a digital mammography R and D project. It is a 32-channel circuit, with a 16-bit binary static counter.It has been optimized for a relatively large detector capacitance of 5 pF. Noise has been measured to be equal to 100 + 7*Cd (pF) electron rms with the digital part, showing no degradation of the noise performances with respect to the design values. The power consumption is 3.8mW/channel for a peaking time of about 1 microsecond(s) . The second circuit is a prototype for pixel imaging. The total active area is about (250 micrometers )**2. The main differences of the electronic architecture with respect to the first prototype are: i) different optimization of the analog front-end part for low-capacitance detectors, ii) in- pixel 4-bit comparator

An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit.

PubMed

Tao Tang; Wang Ling Goh; Lei Yao; Jia Hao Cheong; Yuan Gao

2017-07-01

This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design achieves 90% chip area reduction with enhanced CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-μm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 μA per channel under a supply voltage of 1 V. The input-referred noise of the AFE integrated from 1 Hz to 10k Hz is only 4 μVrms and the CMRR is 110 dB.

Lignan from Thyme Possesses Inhibitory Effect on ASIC3 Channel Current*

PubMed Central

Dubinnyi, Maxim A.; Osmakov, Dmitry I.; Koshelev, Sergey G.; Kozlov, Sergey A.; Andreev, Yaroslav A.; Zakaryan, Naira A.; Dyachenko, Igor A.; Bondarenko, Dmitry A.; Arseniev, Alexander S.; Grishin, Eugene V.

2012-01-01

A novel compound was identified in the acidic extract of Thymus armeniacus collected in the Lake Sevan region of Armenia. This compound, named “sevanol,” to our knowledge is the first low molecular weight natural molecule that has a reversible inhibition effect on both the transient and the sustained current of human ASIC3 channels expressed in Xenopus laevis oocytes. Sevanol completely blocked the transient component (IC50 353 ± 23 μm) and partially (∼45%) inhibited the amplitude of the sustained component (IC50 of 234 ± 53 μm). Other types of acid-sensing ion channel (ASIC) channels were intact to sevanol application, except ASIC1a, which showed more than six times less affinity to it as compared with the inhibitory action on the ASIC3 channel. To elucidate the structure of sevanol, the set of NMR spectra in two solvents (d6-DMSO and D2O) was collected, and the complete chemical structure was confirmed by liquid chromatography-mass spectrometry with electrospray ionization (LC-ESI+-MS) fragmentation. This compound is a new lignan built up of epiphyllic acid and two isocitryl esters in positions 9 and 10. In vivo administration of sevanol (1–10 mg/kg) significantly reversed thermal hyperalgesia induced by complete Freund's adjuvant injection and reduced response to acid in a writhing test. Thus, we assume the probable considerable role of sevanol in known analgesic and anti-inflammatory properties of thyme. PMID:22854960

The GBT-SCA, a radiation tolerant ASIC for detector control and monitoring applications in HEP experiments

NASA Astrophysics Data System (ADS)

Caratelli, A.; Bonacini, S.; Kloukinas, K.; Marchioro, A.; Moreira, P.; De Oliveira, R.; Paillard, C.

2015-03-01

The future upgrades of the LHC experiments will increase the beam luminosity leading to a corresponding growth of the amounts of data to be treated by the data acquisition systems. To address these needs, the GBT (Giga-Bit Transceiver optical link [1,2]) architecture was developed to provide the simultaneous transfer of readout data, timing and trigger signals as well as slow control and monitoring data. The GBT-SCA ASIC, part of the GBT chip-set, has the purpose to distribute control and monitoring signals to the on-detector front-end electronics and perform monitoring operations of detector environmental parameters. In order to meet the requirements of different front-end ASICs used in the experiments, it provides various user-configurable interfaces capable to perform simultaneous operations. It is designed employing radiation tolerant design techniques to ensure robustness against SEUs and TID radiation effects and is implemented in a commercial 130 nm CMOS technology. This work presents the GBT-SCA architecture, the ASIC interfaces, the data transfer protocol, and its integration with the GBT optical link.

Software solution for autonomous observations with H2RG detectors and SIDECAR ASICs for the RATIR camera

NASA Astrophysics Data System (ADS)

Klein, Christopher R.; Kubánek, Petr; Butler, Nathaniel R.; Fox, Ori D.; Kutyrev, Alexander S.; Rapchun, David A.; Bloom, Joshua S.; Farah, Alejandro; Gehrels, Neil; Georgiev, Leonid; González, J. Jesús; Lee, William H.; Lotkin, Gennadiy N.; Moseley, Samuel H.; Prochaska, J. Xavier; Ramirez-Ruiz, Enrico; Richer, Michael G.; Robinson, Frederick D.; Román-Zúñiga, Carlos; Samuel, Mathew V.; Sparr, Leroy M.; Tucker, Corey; Watson, Alan M.

2012-07-01

The Reionization And Transients InfraRed (RATIR) camera has been built for rapid Gamma-Ray Burst (GRB) followup and will provide quasi-simultaneous imaging in ugriZY JH. The optical component uses two 2048 × 2048 pixel Finger Lakes Imaging ProLine detectors, one optimized for the SDSS u, g, and r bands and one optimized for the SDSS i band. The infrared portion incorporates two 2048 × 2048 pixel Teledyne HgCdTe HAWAII-2RG detectors, one with a 1.7-micron cutoff and one with a 2.5-micron cutoff. The infrared detectors are controlled by Teledyne's SIDECAR (System for Image Digitization Enhancement Control And Retrieval) ASICs (Application Specific Integrated Circuits). While other ground-based systems have used the SIDECAR before, this system also utilizes Teledyne's JADE2 (JWST ASIC Drive Electronics) interface card and IDE (Integrated Development Environment). Here we present a summary of the software developed to interface the RATIR detectors with Remote Telescope System, 2nd Version (RTS2) software. RTS2 is an integrated open source package for remote observatory control under the Linux operating system and will autonomously coordinate observatory dome, telescope pointing, detector, filter wheel, focus stage, and dewar vacuum compressor operations. Where necessary we have developed custom interfaces between RTS2 and RATIR hardware, most notably for cryogenic focus stage motor drivers and temperature controllers. All detector and hardware interface software developed for RATIR is freely available and open source as part of the RTS2 distribution.

Programmable Differential Delay Circuit With Fine Delay Adjustment

DOEpatents

DeRyckere, John F.; Jenkins, Philip Nord; Cornett, Frank Nolan

2002-07-09

Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

Spacecraft optical disk recorder memory buffer control

NASA Technical Reports Server (NTRS)

Hodson, Robert F.

1992-01-01

The goal of this project is to develop an Application Specific Integrated Circuit (ASIC) for use in the control electronics of the Spacecraft Optical Disk Recorder (SODR). Specifically, this project is to design an extendable memory buffer controller ASIC for rate matching between a system Input/Output port and the SODR's device interface. The aforementioned goal can be partitioned into the following sub-goals: (1) completion of ASIC design and simulation (on-going via ASEE fellowship); (2) ASIC Fabrication (at ASIC manufacturer); and (3) ASIC Testing (NASA/LaRC, Christopher Newport University).

ASIC3 Channels Integrate Agmatine and Multiple Inflammatory Signals through the Nonproton Ligand Sensing Domain

PubMed Central

2010-01-01

Background Acid-sensing ion channels (ASICs) have long been known to sense extracellular protons and contribute to sensory perception. Peripheral ASIC3 channels represent natural sensors of acidic and inflammatory pain. We recently reported the use of a synthetic compound, 2-guanidine-4-methylquinazoline (GMQ), to identify a novel nonproton sensing domain in the ASIC3 channel, and proposed that, based on its structural similarity with GMQ, the arginine metabolite agmatine (AGM) may be an endogenous nonproton ligand for ASIC3 channels. Results Here, we present further evidence for the physiological correlation between AGM and ASIC3. Among arginine metabolites, only AGM and its analog arcaine (ARC) activated ASIC3 channels at neutral pH in a sustained manner similar to GMQ. In addition to the homomeric ASIC3 channels, AGM also activated heteromeric ASIC3 plus ASIC1b channels, extending its potential physiological relevance. Importantly, the process of activation by AGM was highly sensitive to mild acidosis, hyperosmolarity, arachidonic acid (AA), lactic acid and reduced extracellular Ca2+. AGM-induced ASIC3 channel activation was not through the chelation of extracellular Ca2+ as occurs with increased lactate, but rather through a direct interaction with the newly identified nonproton ligand sensing domain. Finally, AGM cooperated with the multiple inflammatory signals to cause pain-related behaviors in an ASIC3-dependent manner. Conclusions Nonproton ligand sensing domain might represent a novel mechanism for activation or sensitization of ASIC3 channels underlying inflammatory pain-sensing under in vivo conditions. PMID:21143836

The SIRIUS mixed analog-digital ASIC developed for the LOFT LAD and WFM instruments

NASA Astrophysics Data System (ADS)

Cros, A.; Rambaud, D.; Moutaye, E.; Ravera, L.; Barret, D.; Caïs, P.; Clédassou, R.; Bodin, P.; Seyler, J. Y.; Bonzo, A.; Feroci, M.; Labanti, C.; Evangelista, Y.; Favre, Y.

2014-07-01

We report on the development and characterization of the low-noise, low power, mixed analog-digital SIRIUS ASICs for both the LAD and WFM X-ray instruments of LOFT. The ASICs we developed are reading out large area silicon drift detectors (SDD). Stringent requirements in terms of noise (ENC of 17 e- to achieve an energy resolution on the LAD of 200 eV FWHM at 6 keV) and power consumption (650 μW per channel) were basis for the ASICs design. These SIRIUS ASICs are developed to match SDD detectors characteristics: 16 channels ASICs adapted for the LAD (970 microns pitch) and 64 channels for the WFM (145 microns pitch) will be fabricated. The ASICs were developed with the 180nm mixed technology of TSMC.

Towards Evolving Electronic Circuits for Autonomous Space Applications

NASA Technical Reports Server (NTRS)

Lohn, Jason D.; Haith, Gary L.; Colombano, Silvano P.; Stassinopoulos, Dimitris

2000-01-01

The relatively new field of Evolvable Hardware studies how simulated evolution can reconfigure, adapt, and design hardware structures in an automated manner. Space applications, especially those requiring autonomy, are potential beneficiaries of evolvable hardware. For example, robotic drilling from a mobile platform requires high-bandwidth controller circuits that are difficult to design. In this paper, we present automated design techniques based on evolutionary search that could potentially be used in such applications. First, we present a method of automatically generating analog circuit designs using evolutionary search and a circuit construction language. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm, we present experimental results for five design tasks. Second, we investigate the use of coevolution in automated circuit design. We examine fitness evaluation by comparing the effectiveness of four fitness schedules. The results indicate that solution quality is highest with static and co-evolving fitness schedules as compared to the other two dynamic schedules. We discuss these results and offer two possible explanations for the observed behavior: retention of useful information, and alignment of problem difficulty with circuit proficiency.

ASIC-dependent LTP at multiple glutamatergic synapses in amygdala network is required for fear memory

PubMed Central

Chiang, Po-Han; Chien, Ta-Chun; Chen, Chih-Cheng; Yanagawa, Yuchio; Lien, Cheng-Chang

2015-01-01

Genetic variants in the human ortholog of acid-sensing ion channel-1a subunit (ASIC1a) gene are associated with panic disorder and amygdala dysfunction. Both fear learning and activity-induced long-term potentiation (LTP) of cortico-basolateral amygdala (BLA) synapses are impaired in ASIC1a-null mice, suggesting a critical role of ASICs in fear memory formation. In this study, we found that ASICs were differentially expressed within the amygdala neuronal population, and the extent of LTP at various glutamatergic synapses correlated with the level of ASIC expression in postsynaptic neurons. Importantly, selective deletion of ASIC1a in GABAergic cells, including amygdala output neurons, eliminated LTP in these cells and reduced fear learning to the same extent as that found when ASIC1a was selectively abolished in BLA glutamatergic neurons. Thus, fear learning requires ASIC-dependent LTP at multiple amygdala synapses, including both cortico-BLA input synapses and intra-amygdala synapses on output neurons. PMID:25988357

Mongoose ASIC microcontroller programming guide

NASA Astrophysics Data System (ADS)

Smith, Brian S.

1993-09-01

The 'Mongoose' ASIC microcontroller is a radiation-hard implementation of the R3000 microprocessor. This document describes the internals of the microcontroller in a level of detail necessary for someone implementing a software design.

Mongoose ASIC microcontroller programming guide

NASA Technical Reports Server (NTRS)

Smith, Brian S.

1993-01-01

The 'Mongoose' ASIC microcontroller is a radiation-hard implementation of the R3000 microprocessor. This document describes the internals of the microcontroller in a level of detail necessary for someone implementing a software design.

Macro Pixel ASIC (MPA): the readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC

NASA Astrophysics Data System (ADS)

Ceresa, D.; Marchioro, A.; Kloukinas, K.; Kaplon, J.; Bialas, W.; Re, V.; Traversi, G.; Gaioni, L.; Ratti, L.

2014-11-01

The CMS tracker at HL-LHC is required to provide prompt information on particles with high transverse momentum to the central Level 1 trigger. For this purpose, the innermost part of the outer tracker is based on a combination of a pixelated sensor with a short strip sensor, the so-called Pixel-Strip module (PS). The readout of these sensors is carried out by distinct ASICs, the Strip Sensor ASIC (SSA), for the strip layer, and the Macro Pixel ASIC (MPA) for the pixel layer. The processing of the data directly on the front-end module represents a design challenge due to the large data volume (30720 pixels and 1920 strips per module) and the limited power budget. This is the reason why several studies have been carried out to find the best compromise between ASICs performance and power consumption. This paper describes the current status of the MPA ASIC development where the logic for generating prompt information on particles with high transverse momentum is implemented. An overview of the readout method is presented with particular attention on the cluster reduction, position encoding and momentum discrimination logic. Concerning the architectural studies, a software test bench capable of reading physics Monte-Carlo generated events has been developed and used to validate the MPA design and to evaluate the MPA performance. The MPA-Light is scheduled to be submitted for fabrication this year and will include the full analog functions and a part of the digital logic of the final version in order to qualify the chosen VLSI technology for the analog front-end, the module assembly and the low voltage digital supply.

A High-Performance Application Specific Integrated Circuit for Electrical and Neurochemical Traumatic Brain Injury Monitoring.

PubMed

Pagkalos, Ilias; Rogers, Michelle L; Boutelle, Martyn G; Drakakis, Emmanuel M

2018-05-22

This paper presents the first application specific integrated chip (ASIC) for the monitoring of patients who have suffered a Traumatic Brain Injury (TBI). By monitoring the neurophysiological (ECoG) and neurochemical (glucose, lactate and potassium) signals of the injured human brain tissue, it is possible to detect spreading depolarisations, which have been shown to be associated with poor TBI patient outcome. This paper describes the testing of a new 7.5 mm 2 ASIC fabricated in the commercially available AMS 0.35 μm CMOS technology. The ASIC has been designed to meet the demands of processing the injured brain tissue's ECoG signals, recorded by means of depth or brain surface electrodes, and neurochemical signals, recorded using microdialysis coupled to microfluidics-based electrochemical biosensors. The potentiostats use switchedcapacitor charge integration to record currents with 100 fA resolution, and allow automatic gain changing to track the falling sensitivity of a biosensor. This work supports the idea of a "behind the ear" wireless microplatform modality, which could enable the monitoring of currently non-monitored mobile TBI patients for the onset of secondary brain injury. ©2018 The Authors. Published by Wiley-VCH Verlag GmbH & Co. KGaA.

In situ hybridization evidence for the coexistence of ASIC and TRPV1 within rat single sensory neurons.

PubMed

Ugawa, Shinya; Ueda, Takashi; Yamamura, Hisao; Shimada, Shoichi

2005-05-20

The activation of nociceptors by protons plays a crucial role in the initiation and maintenance of acidosis-linked pain. Acid-sensing ion channel (ASIC) and transient receptor potential/vanilloid receptor subtype-1 (TRPV1) encode proton-activated cation channels expressed by nociceptors and the opening of these channels results in nociceptor excitation. Histological relations among ASIC clones and the colocalization of each ASIC subunit and TRPV1 within single sensory neurons were examined on serial sections of rat dorsal root ganglia (DRG) using in situ hybridization histochemistry. ASIC1a transcripts were expressed in 20-25% of the DRG neurons, and most of the neurons had small (<30 microm)-diameter cell bodies. ASIC1b transcripts and ASIC3 transcripts were expressed in approximately 10% and 30-35% of the DRG neurons, respectively, and the greater part of each population was located in small-to-medium (30-50 microm)-diameter cells. The ASIC1a transcripts and ASIC1b transcripts were basically localized in the distinct populations of the DRG neurons, while approximately 20% of the ASIC1a-positive neurons and approximately 10% of the ASIC1b-positive neurons expressed ASIC3 transcripts. TRPV1 transcripts were expressed in 35-40% of the DRG neurons, and most of the TRPV1-positive neurons had small-diameter cell bodies. Intense expression signals for ASIC1a transcripts were detected in 40-45% of the TRPV1-positive neurons. Neurons expressing both ASIC1b and TRPV1 transcripts were barely detected in the DRG. Approximately 30% of the TRPV1-positive neurons expressed ASIC3 transcripts, and the double-labeled neurons were comprised of both small-diameter and medium-diameter cells. Approximately 13% of the TRPV1-positive neurons expressed both ASIC1a and ASIC3 transcripts.

20 CFR 405.515 - Application of circuit court law.

Code of Federal Regulations, 2010 CFR

2010-04-01

... 20 Employees' Benefits 2 2010-04-01 2010-04-01 false Application of circuit court law. 405.515 Section 405.515 Employees' Benefits SOCIAL SECURITY ADMINISTRATION ADMINISTRATIVE REVIEW PROCESS FOR ADJUDICATING INITIAL DISABILITY CLAIMS Judicial Review § 405.515 Application of circuit court law. We will...

Note: A 102 dB dynamic-range charge-sampling readout for ionizing particle/radiation detectors based on an application-specific integrated circuit (ASIC)

NASA Astrophysics Data System (ADS)

Pullia, A.; Zocca, F.; Capra, S.

2018-02-01

An original technique for the measurement of charge signals from ionizing particle/radiation detectors has been implemented in an application-specific integrated circuit form. The device performs linear measurements of the charge both within and beyond its output voltage swing. The device features an unprecedented spectroscopic dynamic range of 102 dB and is suitable for high-resolution ion and X-γ ray spectroscopy. We believe that this approach may change a widespread paradigm according to which no high-resolution spectroscopy is possible when working close to or beyond the limit of the preamplifier's output voltage swing.

Note: A 102 dB dynamic-range charge-sampling readout for ionizing particle/radiation detectors based on an application-specific integrated circuit (ASIC).

PubMed

Pullia, A; Zocca, F; Capra, S

2018-02-01

An original technique for the measurement of charge signals from ionizing particle/radiation detectors has been implemented in an application-specific integrated circuit form. The device performs linear measurements of the charge both within and beyond its output voltage swing. The device features an unprecedented spectroscopic dynamic range of 102 dB and is suitable for high-resolution ion and X-γ ray spectroscopy. We believe that this approach may change a widespread paradigm according to which no high-resolution spectroscopy is possible when working close to or beyond the limit of the preamplifier's output voltage swing.

Integrated circuit for SAW and MEMS sensors

NASA Astrophysics Data System (ADS)

Fischer, Wolf-Joachim; Koenig, Peter; Ploetner, Matthias; Hermann, Rudiger; Stab, Helmut

2001-11-01

The sensor processor circuit has been developed for hand-held devices used in industrial and environmental applications, such as on-line process monitoring. Thereby devices with SAW sensors or MEMS resonators will benefit from this processor especially. Up to 8 sensors can be connected to the circuit as multisensors or sensor arrays. Two sensor processors SP1 and SP2 for different applications are presented in this paper. The SP-1 chip has a PCMCIA interface which can be used for the program and data transfer. SAW sensors which are working in the frequency range from 80 MHz to 160 MHz can be connected to the processor directly. It is possible to use the new SP-2 chip fabricated in a 0.5(mu) CMOS process for SAW devices with a maximum frequency of 600 MHz. An on-chip analog-digital-converter (ADC) and 6 PWM modules support the development of high-miniaturized intelligent sensor systems We have developed a multi-SAW sensor system with this ASIC that manages the requirements on control as well as signal generation and storage and provides an interface to the PC and electronic devices on the board. Its low power consumption and its PCMCIA plug fulfil the requirements of small size and mobility. For this application sensors have been developed to detect hazardous gases in ambient air. Sensors with differently modified copper-phthalocyanine films are capable of detecting NO2 and O3, whereas those with a hyperbranched polyester film respond to NH3.

TOFPET 2: A high-performance circuit for PET time-of-flight

NASA Astrophysics Data System (ADS)

Di Francesco, Agostino; Bugalho, Ricardo; Oliveira, Luis; Rivetti, Angelo; Rolo, Manuel; Silva, Jose C.; Varela, Joao

2016-07-01

We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with (320 pF) capacitance the circuit has 24 (30) dB SNR, 75 (39) ps r.m.s. resolution, and 4 (8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.

Integrated low power digital gyro control electronics

NASA Technical Reports Server (NTRS)

M'Closkey, Robert (Inventor); Grayver, Eugene (Inventor); Challoner, A. Dorian (Inventor); Hayworth, Ken J. (Inventor)

2005-01-01

Embodiments of the invention generally encompass a digital, application specific integrated circuit (ASIC) has been designed to perform excitation of a selected mode within a vibratory rate gyroscope, damping, or force-rebalance, of other modes within the sensor, and signal demodulation of the in-phase and quadrature components of the signal containing the angular rate information. The ASIC filters dedicated to each channel may be individually programmed to accommodate different rate sensor designs/technology or variations within the same class of sensors. The ASIC architecture employs a low-power design, making the ASIC, particularly suitable for use in power-sensitive applications.

The latency validation of the optical link for the ATLAS Liquid Argon Calorimeter Phase-I trigger upgrade

NASA Astrophysics Data System (ADS)

Deng, B.; Xiao, L.; Zhao, X.; Baker, E.; Gong, D.; Guo, D.; He, H.; Hou, S.; Liu, C.; Liu, T.; Sun, Q.; Thomas, J.; Wang, J.; Xiang, A. C.; Yang, D.; Ye, J.; Zhou, W.

2018-05-01

Two optical data link data transmission Application Specific Integrated Circuits (ASICs), the baseline and its backup, have been designed for the ATLAS Liquid Argon (LAr) Calorimeter Phase-I trigger upgrade. The latency of each ASIC and that of its corresponding receiver implemented in a back-end Field-Programmable Gate Array (FPGA) are critical specifications. In this paper, we present the latency measurements and simulation of two ASICs. The measurement results indicate that both ASICs achieve their design goals and meet the latency specifications. The consistency between the simulation and measurements validates the ASIC latency characterization.

Enhanced maximal exercise capacity, vasodilation to electrical muscle contraction, and hind limb vascular density in ASIC1a null mice.

PubMed

Drummond, Heather A; Xiang, Lusha; Chade, Alejandro R; Hester, Robert

2017-08-01

Acid-sensing ion channel (ASIC) proteins form extracellular proton-gated, cation-selective channels in neurons and vascular smooth muscle cells and are proposed to act as extracellular proton sensors. However, their importance to vascular responses under conditions associated with extracellular acidosis, such as strenuous exercise, is unclear. Therefore, the purpose of this study was to determine if one ASIC protein, ASIC1a, contributes to extracellular proton-gated vascular responses and exercise tolerance. To determine if ASIC1a contributes to exercise tolerance, we determined peak oxygen (O 2 ) uptake in conscious ASIC1a -/- mice during exhaustive treadmill running. Loss of ASIC1a was associated with a greater peak running speed (60 ± 2 vs. 53 ± 3 m·min -1 , P  = 0.049) and peak oxygen (O 2 ) uptake during exhaustive treadmill running (9563 ± 120 vs. 8836 ± 276 mL·kg -1 ·h -1 , n  = 6-7, P  = 0.0082). There were no differences in absolute or relative lean body mass, as determined by EchoMRI. To determine if ASIC1a contributes to vascular responses during muscle contraction, we measured femoral vascular conductance (FVC) during a stepwise electrical stimulation (0.5-5.0 Hz at 3 V for 60 sec) of the left major hind limb muscles. FVC increased to a greater extent in ASIC1a -/- versus ASIC1a +/+ mice (0.44 ± 0.03 vs. 0.30 ± 0.04 mL·min -1 ·100 g hind limb mass -1 · mmHg -1 , n  = 5 each, P  = 0.0009). Vasodilation following local application of external protons in the spinotrapezius muscle increased the duration, but not the magnitude, of the vasodilatory response in ASIC1a -/- mice. Finally, we examined hind limb vascular density using micro-CT and found increased density of 0-80  μ m vessels ( P  <   0.05). Our findings suggest an increased vascular density and an enhanced vasodilatory response to local protons, to a lesser degree, may contribute to the enhanced vascular conductance and increased peak exercise capacity

Fabrication Security and Trust of Domain-Specific ASIC Processors

DTIC Science & Technology

2016-10-30

embedded in the design. For example , an ASIC processor potentially has a 10-1,000X performance advantage over its FPGA and GPP counterparts, but...paper by summarizing our lessons learned from this project and suggests a few research directions. II. DOMAIN-SPECIFIC ASIC PROCESSORS As Figure 1 has...sponsored by the Assistant Secretary of Defense for Research & Engineering under Air Force Contract #FA8721-05-C-0002. Opinions, interpretations

Extracellular Spermine Exacerbates Ischemic Neuronal Injury through Sensitization of ASIC1a Channels to Extracellular Acidosis

PubMed Central

Duan, Bo; Wang, Yi-Zhi; Yang, Tao; Chu, Xiang-Ping; Yu, Ye; Huang, Yu; Cao, Hui; Hansen, Jillian; Simon, Roger P.; Zhu, Michael X.; Xiong, Zhi-Gang; Xu, Tian-Le

2011-01-01

Ischemic brain injury is a major problem associated with stroke. It has been increasingly recognized that acid-sensing ion channels (ASICs) contribute significantly to ischemic neuronal damage, but the underlying mechanism has remained elusive. Here, we show that extracellular spermine, one of the endogenous polyamines, exacerbates ischemic neuronal injury through sensitization of ASIC1a channels to extracellular acidosis. Pharmacological blockade of ASIC1a or deletion of the ASIC1 gene greatly reduces the enhancing effect of spermine in ischemic neuronal damage both in cultures of dissociated neurons and in a mouse model of focal ischemia. Mechanistically, spermine profoundly reduces desensitization of ASIC1a by slowing down desensitization in the open state, shifting steady-state desensitization to more acidic pH, and accelerating recovery between repeated periods of acid stimulation. Spermine-mediated potentiation of ASIC1a activity is occluded by PcTX1 (psalmotoxin 1), a specific ASIC1a inhibitor binding to its extracellular domain. Functionally, the enhanced channel activity is accompanied by increased acid-induced neuronal membrane depolarization and cytoplasmic Ca2+ overload, which may partially explain the exacerbated neuronal damage caused by spermine. More importantly, blocking endogenous spermine synthesis significantly attenuates ischemic brain injury mediated by ASIC1a but not that by NMDA receptors. Thus, extracellular spermine contributes significantly to ischemic neuronal injury through enhancing ASIC1a activity. Our data suggest new neuroprotective strategies for stroke patients via inhibition of polyamine synthesis and subsequent spermine–ASIC interaction. PMID:21307247

Implementation of a Synchronized Oscillator Circuit for Fast Sensing and Labeling of Image Objects

PubMed Central

Kowalski, Jacek; Strzelecki, Michal; Kim, Hyongsuk

2011-01-01

We present an application-specific integrated circuit (ASIC) CMOS chip that implements a synchronized oscillator cellular neural network with a matrix size of 32 × 32 for object sensing and labeling in binary images. Networks of synchronized oscillators are a recently developed tool for image segmentation and analysis. Its parallel network operation is based on a “temporary correlation” theory that attempts to describe scene recognition as if performed by the human brain. The synchronized oscillations of neuron groups attract a person’s attention if he or she is focused on a coherent stimulus (image object). For more than one perceived stimulus, these synchronized patterns switch in time between different neuron groups, thus forming temporal maps that code several features of the analyzed scene. In this paper, a new oscillator circuit based on a mathematical model is proposed, and the network architecture and chip functional blocks are presented and discussed. The proposed chip is implemented in AMIS 0.35 μm C035M-D 5M/1P technology. An application of the proposed network chip for the segmentation of insulin-producing pancreatic islets in magnetic resonance liver images is presented. PMID:22163803

An Energy Efficient ECG Signal Processor Detecting Cardiovascular Diseases on Smartphone.

PubMed

Jain, Sanjeev Kumar; Bhaumik, Basabi

2017-04-01

A novel disease diagnostic algorithm for ECG signal processing based on forward search is implemented in Application Specific Integrated Circuit (ASIC) for cardiovascular disease diagnosis on smartphone. An ASIC is fabricated using 130-nm CMOS low leakage process technology. The area of our PQRST ASIC is 1.21 mm 2 . The energy dissipation of PQRST ASIC is 96 pJ with a supply voltage of 0.9 V. The outputs from the ASIC are fed to an Android application that generates diagnostic report and can be sent to a cardiologist via email. The ASIC and Android application are verified for the detection of bundle branch block, hypertrophy, arrhythmia and myocardial infarction using Physionet PTB diagnostic ECG database. The failed detection rate is 0.69%, 0.69%, 0.34% and 1.72% for bundle branch block, hypertrophy, arrhythmia and myocardial infarction respectively. The AV block is detected in all the three patients in the Physionet St. Petersburg arrhythmia database. Our proposed ASIC together with our Android application is the most suitable for an energy efficient wearable cardiovascular disease detection system.

Investigation of noise insensitive electronic circuits for automotive applications with particular regard to MOS circuits

NASA Astrophysics Data System (ADS)

Gorille, I.

1980-11-01

The application of MOS switching circuits of high complexity in essential automobile systems, such as ignition and injection, was investigated. A bipolar circuit technology, current hogging logic (CHL), was compared to MOS technologies for its competitiveness. The functional requirements of digital automotive systems can only be met by technologies allowing large packing densities and medium speeds. The properties of n-MOS and CMOS are promising whereas the electrical power needed by p-MOS circuits is in general prohibitively large.

JPIC-Rad-Hard JPEG2000 Image Compression ASIC

NASA Astrophysics Data System (ADS)

Zervas, Nikos; Ginosar, Ran; Broyde, Amitai; Alon, Dov

2010-08-01

JPIC is a rad-hard high-performance image compression ASIC for the aerospace market. JPIC implements tier 1 of the ISO/IEC 15444-1 JPEG2000 (a.k.a. J2K) image compression standard [1] as well as the post compression rate-distortion algorithm, which is part of tier 2 coding. A modular architecture enables employing a single JPIC or multiple coordinated JPIC units. JPIC is designed to support wide data sources of imager in optical, panchromatic and multi-spectral space and airborne sensors. JPIC has been developed as a collaboration of Alma Technologies S.A. (Greece), MBT/IAI Ltd (Israel) and Ramon Chips Ltd (Israel). MBT IAI defined the system architecture requirements and interfaces, The JPEG2K-E IP core from Alma implements the compression algorithm [2]. Ramon Chips adds SERDES interfaces and host interfaces and integrates the ASIC. MBT has demonstrated the full chip on an FPGA board and created system boards employing multiple JPIC units. The ASIC implementation, based on Ramon Chips' 180nm CMOS RadSafe[TM] RH cell library enables superior radiation hardness.

High performance protection circuit for power electronics applications

NASA Astrophysics Data System (ADS)

Tudoran, Cristian D.; Dǎdârlat, Dorin N.; Toşa, Nicoleta; Mişan, Ioan

2015-12-01

In this paper we present a high performance protection circuit designed for the power electronics applications where the load currents can increase rapidly and exceed the maximum allowed values, like in the case of high frequency induction heating inverters or high frequency plasma generators. The protection circuit is based on a microcontroller and can be adapted for use on single-phase or three-phase power systems. Its versatility comes from the fact that the circuit can communicate with the protected system, having the role of a "sensor" or it can interrupt the power supply for protection, in this case functioning as an external, independent protection circuit.

BAE Systems Radiation Hardened SpaceWire ASIC and Roadmap

NASA Technical Reports Server (NTRS)

Berger, Richard; Milliser, Myrna; Kapcio, Paul; Stanley, Dan; Moser, David; Koehler, Jennifer; Rakow, Glenn; Schnurr, Richard

2006-01-01

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS, technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASlC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a 4-port SpaceWire router with two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, -and a memory controller for additional external memory use. The SpaceWire ASlC is planned for use on both the Geostationary Operational Environmental Satellites (GOES)-R and the Lunar Reconnaissance Orbiter (LRO). Engineering parts have already been delivered to both programs. This paper discusses the SpaceWire protocol and those elements of it that have been built into the current SpaceWire reusable core. There are features within the core that go beyond the current standard that can be enabled or disabled by the user and these will be described. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be discussed. Optional configurations within user systems will be shown. The physical imp!ementation of the design will be described and test results from the hardware will be discussed. Finally, the BAE Systems roadmap for SpaceWire developments will be discussed, including some products already in design as well as longer term plans.

A miniature on-chip multi-functional ECG signal processor with 30 µW ultra-low power consumption.

PubMed

Liu, Xin; Zheng, Yuan Jin; Phyu, Myint Wai; Zhao, Bin; Je, Minkyu; Yuan, Xiao Jun

2010-01-01

In this paper, a miniature low-power Electrocardiogram (ECG) signal processing application specific integrated circuit (ASIC) chip is proposed. This chip provides multiple critical functions for ECG analysis using a systematic wavelet transform algorithm and a novel SRAM-based ASIC architecture, while achieves low cost and high performance. Using 0.18 µm CMOS technology and 1 V power supply, this ASIC chip consumes only 29 µW and occupies an area of 3 mm(2). This on-chip ECG processor is highly suitable for reliable real-time cardiac status monitoring applications.

KLauS: an ASIC for silicon photomultiplier readout and its application in a setup for production testing of scintillating tiles

NASA Astrophysics Data System (ADS)

Briggl, K.; Dorn, M.; Hagdorn, R.; Harion, T.; Schultz-Coulon, H. C.; Shen, W.

2014-02-01

KLauS is an ASIC produced in the AMS 0.35 μm SiGe process to read out the charge signals from silicon photomultipliers. Developed as an analog front-end for future calorimeters with high granularity as pursued by the AHCAL concept in the CALICE collaboration, the ASIC is designed to measure the charge signal of the sensors in a large dynamic range and with low electronic noise contributions. In order to tune the operation voltage of each sensor individually, an 8-bit DAC to tune the voltage at the input terminal within a range of 2V is implemented. Using an integrated fast comparator with low jitter, the time information can be measured with sub-nanosecond resolution. The low power consumption of the ASIC can be further decreased using power gating techniques. Future versions of KLauS are under development and will incorporate an ADC with a resolution of up to 12-bits and blocks for digital data transmission. The chip is used in a setup for mass testing and characterization of scintillator tiles for the AHCAL test beam program.

High performance protection circuit for power electronics applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tudoran, Cristian D., E-mail: cristian.tudoran@itim-cj.ro; Dădârlat, Dorin N.; Toşa, Nicoleta

2015-12-23

In this paper we present a high performance protection circuit designed for the power electronics applications where the load currents can increase rapidly and exceed the maximum allowed values, like in the case of high frequency induction heating inverters or high frequency plasma generators. The protection circuit is based on a microcontroller and can be adapted for use on single-phase or three-phase power systems. Its versatility comes from the fact that the circuit can communicate with the protected system, having the role of a “sensor” or it can interrupt the power supply for protection, in this case functioning as anmore » external, independent protection circuit.« less

The role of periodontal ASIC3 in orofacial pain induced by experimental tooth movement in rats.

PubMed

Gao, Meiya; Long, Hu; Ma, Wenqiang; Liao, Lina; Yang, Xin; Zhou, Yang; Shan, Di; Huang, Renhuan; Jian, Fan; Wang, Yan; Lai, Wenli

2016-12-01

This study aimed to clarify the roles of Acid-sensing ion channel 3 (ASIC3) in orofacial pain following experimental tooth movement. Sixty male Sprague-Dawley rats were divided into the experimental group (40g, n = 30) and the sham group (0g, n = 30). Closed coil springs were ligated between maxillary incisor and molars to achieve experimental tooth movement. Rat grimace scale (RGS) scores were assessed at 0, 1, 3, 5, 7, and 14 days after the placement of the springs. ASIC3 immunostaining was performed and the expression levels of ASIC3 were measured through integrated optical density/area in Image-Pro Plus 6.0. Moreover, 18 rats were divided into APETx2 group (n = 6), amiloride group (n = 6), and vehicle group (n = 6), and RGS scores were obtained compared among them to verify the roles of ASIC3 in orofacial pain following tooth movement. ASIC3 expression levels became significantly higher in the experimental group than in sham group on 1, 3, and 5 days and became similar on 7 and 14 days. Pain levels (RGS scores) increased in both groups and were significantly higher in the experimental group on 1, 3, 5, and 7 days and were similar on 14 days. Periodontal ASIC3 expression levels were correlated with orofacial pain levels following experimental tooth movement. Periodontal administrations of ASIC3 antagonists (APETx2 and amiloride) could alleviate pain. This study needs to be better evidenced by RNA interference of ASIC3 in periodontal tissues in rats following experimental tooth movement. Moreover, we hope further studies would concentrate on the pain perception of ASIC3 knockout (ASIC3 -/- ) mice. Our results suggest that periodontal ASIC3 plays an important role in orofacial pain induced by experimental tooth movement. © The Author 2015. Published by Oxford University Press on behalf of the European Orthodontic Society. All rights reserved. For permissions, please email: journals.permissions@oup.com.

Human ASIC3 channel dynamically adapts its activity to sense the extracellular pH in both acidic and alkaline directions.

PubMed

Delaunay, Anne; Gasull, Xavier; Salinas, Miguel; Noël, Jacques; Friend, Valérie; Lingueglia, Eric; Deval, Emmanuel

2012-08-07

In rodent sensory neurons, acid-sensing ion channel 3 (ASIC3) has recently emerged as a particularly important sensor of nonadaptive pain associated with tissue acidosis. However, little is known about the human ASIC3 channel, which includes three splice variants differing in their C-terminal domain (hASIC3a, hASIC3b, and hASIC3c). hASIC3a transcripts represent the main mRNAs expressed in both peripheral and central neuronal tissues (dorsal root ganglia [DRG], spinal cord, and brain), where a small proportion of hASIC3c transcripts is also detected. We show that hASIC3 channels (hASIC3a, hASIC3b, or hASIC3c) are able to directly sense extracellular pH changes not only during acidification (up to pH 5.0), but also during alkalization (up to pH 8.0), an original and inducible property yet unknown. When the external pH decreases, hASIC3 display a transient acid mode with brief activation that is relevant to the classical ASIC currents, as previously described. On the other hand, an external pH increase activates a sustained alkaline mode leading to a constitutive activity at resting pH. Both modes are inhibited by the APETx2 toxin, an ASIC3-type channel inhibitor. The alkaline sensitivity of hASIC3 is an intrinsic property of the channel, which is supported by the extracellular loop and involves two arginines (R68 and R83) only present in the human clone. hASIC3 is thus able to sense the extracellular pH in both directions and therefore to dynamically adapt its activity between pH 5.0 and 8.0, a property likely to participate in the fine tuning of neuronal membrane potential and to neuron sensitization in various pH environments.

High-Speed Integrated Circuits for Military Applications.

DTIC Science & Technology

1979-11-01

1.5 pm circuits at the present time. " Market economics do not justify these circuits in the time frame of the VHSI program." See also Ref. 9. 7 per...on microprocessors currently in production, but the huge commercial market that is thought to exist for these devices when they can at last be...Subsection I, below). The single-chip microprocessor dominates the commercial market and those military applications for which their through- put is

LEC GaAs for integrated circuit applications

NASA Technical Reports Server (NTRS)

Kirkpatrick, C. G.; Chen, R. T.; Homes, D. E.; Asbeck, P. M.; Elliott, K. R.; Fairman, R. D.; Oliver, J. D.

1984-01-01

Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.

A Low-Power ASIC Signal Processor for a Vestibular Prosthesis.

PubMed

Töreyin, Hakan; Bhatti, Pamela T

2016-06-01

A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm (2) and consumes 1.24 mW when supplied with ± 1.6 V.

Differential regulation of ASICs and TRPV1 by zinc in rat bronchopulmonary sensory neurons.

PubMed

Vysotskaya, Zhanna V; Moss, Charles R; Gu, Qihai

2014-12-01

Zinc has been known to act as a signaling molecule that regulates a variety of neuronal functions. In this study, we aimed to study the effect of zinc on two populations of acid-sensitive ion channels, acid-sensing ion channels (ASICs), and transient receptor potential vanilloid receptor-1 (TRPV1), in vagal bronchopulmonary sensory neurons. Rat vagal sensory neurons innervating lungs and airways were retrogradely labeled with a fluorescent tracer. Whole-cell perforated patch-clamp recordings were carried out in primarily cultured bronchopulmonary sensory neurons. The acid-evoked ASIC and TRPV1 currents were measured and compared between before and after the zinc pretreatment. ASIC currents were induced by a pH drop from 7.4 to 6.8 or 6.5 in the presence of capsazepine (10 µM), a specific TRPV1 antagonist. Pretreatment with zinc (50 or 300 µM, 2 min) displayed different effects on the two distinct phenotypes of ASIC currents: a marked potentiation on ASIC channels with fast kinetics of activation and inactivation or no significant effect on ASIC currents with slow activation and inactivation. On the other hand, pretreatment with zinc significantly inhibited the acid (pH 5.5 or 5.3)-induced TRPV1 currents. The inhibition was abolished by intracellular chelation of zinc by TPEN (25 µM), indicating that intracellular accumulation of zinc was likely required for its inhibitory effect on TRPV1 channels. Our study showed that zinc differentially regulates the activities of ASICs and TRPV1 channels in rat vagal bronchopulmonary sensory neurons.

The Panda Strip Asic: Pasta

NASA Astrophysics Data System (ADS)

Lai, A.

2018-01-01

PASTA is the 64 channel front-end chip, designed in a 110 nm CMOS technology to read out the strip sensors of the Micro Vertex Detector (MVD) of the PANDA experiment. This chip provides high resolution timestamp and deposited charge information by means of the time-over-threshold technique. Its working principle is based on a predecessor, the TOFPET ASIC, that was designed for medical applications. A general restructuring of the architecture was needed, in order to meet the specific requirements imposed by the physics programme of PANDA, especially in terms of radiation tolerance, spatial constraints, and readout in absence of a first level hardware trigger. The first revision of PASTA is currently under evaluation at the Forschungszentrum Jülich, where a data acquisition system dedicated to the MVD prototypes has been developed. This paper describes the main aspect of the chip design, gives an overview of the data acquisition system used for the verification, and shows the first results regarding the performance of PASTA.

SVGA and XGA active matrix microdisplays for head-mounted applications

NASA Astrophysics Data System (ADS)

Alvelda, Phillip; Bolotski, Michael; Brown, Imani L.

2000-03-01

The MicroDisplay Corporation's liquid crystal on silicon (LCOS) display devices are based on the union of several technologies with the extreme integration capability of conventionally fabricated CMOS substrates. The fast liquid crystal operation modes and new scalable high-performance pixel addressing architectures presented in this paper enable substantially improved color, contrast, and brightness while still satisfying the optical, packaging, and power requirements of portable applications. The entire suite of MicroDisplay's technologies was devised to create a line of mixed-signal application-specific integrated circuits (ASICs) in single-chip display systems. Mixed-signal circuits can integrate computing, memory, and communication circuitry on the same substrate as the display drivers and pixel array for a multifunctional complete system-on-a-chip. System-on-a-chip benefits also include reduced head supported weight requirements through the elimination of off-chip drive electronics.

A Low-Power ASIC Signal Processor for a Vestibular Prosthesis

PubMed Central

Töreyin, Hakan; Bhatti, Pamela T.

2017-01-01

A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm2 and consumes 1.24 mW when supplied with ± 1.6 V. PMID:26800546

An infrastructure for accurate characterization of single-event transients in digital circuits.

PubMed

Savulimedu Veeravalli, Varadan; Polzer, Thomas; Schmid, Ulrich; Steininger, Andreas; Hofbauer, Michael; Schweiger, Kurt; Dietrich, Horst; Schneider-Hornstein, Kerstin; Zimmermann, Horst; Voss, Kay-Obbe; Merk, Bruno; Hajek, Michael

2013-11-01

We present the architecture and a detailed pre-fabrication analysis of a digital measurement ASIC facilitating long-term irradiation experiments of basic asynchronous circuits, which also demonstrates the suitability of the general approach for obtaining accurate radiation failure models developed in our FATAL project. Our ASIC design combines radiation targets like Muller C-elements and elastic pipelines as well as standard combinational gates and flip-flops with an elaborate on-chip measurement infrastructure. Major architectural challenges result from the fact that the latter must operate reliably under the same radiation conditions the target circuits are exposed to, without wasting precious die area for a rad-hard design. A measurement architecture based on multiple non-rad-hard counters is used, which we show to be resilient against double faults, as well as many triple and even higher-multiplicity faults. The design evaluation is done by means of comprehensive fault injection experiments, which are based on detailed Spice models of the target circuits in conjunction with a standard double-exponential current injection model for single-event transients (SET). To be as accurate as possible, the parameters of this current model have been aligned with results obtained from 3D device simulation models, which have in turn been validated and calibrated using micro-beam radiation experiments at the GSI in Darmstadt, Germany. For the latter, target circuits instrumented with high-speed sense amplifiers have been used for analog SET recording. Together with a probabilistic analysis of the sustainable particle flow rates, based on a detailed area analysis and experimental cross-section data, we can conclude that the proposed architecture will indeed sustain significant target hit rates, without exceeding the resilience bound of the measurement infrastructure.

New Generation Power System for Space Applications

NASA Technical Reports Server (NTRS)

Jones, Loren; Carr, Greg; Deligiannis, Frank; Lam, Barbara; Nelson, Ron; Pantaleon, Jose; Ruiz, Ian; Treicler, John; Wester, Gene; Sauers, Jim;

Knockdown of acid-sensing ion channel 1a (ASIC1a) suppresses disease phenotype in SCA1 mouse model.

PubMed

Vig, Parminder J S; Hearst, Scoty M; Shao, Qingmei; Lopez, Maripar E

2014-08-01

The mutated ataxin-1 protein in spinocerebellar ataxia 1 (SCA1) targets Purkinje cells (PCs) of the cerebellum and causes progressive ataxia due to loss of PCs and neurons of the brainstem. The exact mechanism of this cellular loss is still not clear. Currently, there are no treatments for SCA1; however, understanding of the mechanisms that regulate SCA1 pathology is essential for devising new therapies for SCA1 patients. We previously established a connection between the loss of intracellular calcium-buffering and calcium-signalling proteins with initiation of neurodegeneration in SCA1 transgenic (Tg) mice. Recently, acid-sensing ion channel 1a (ASIC1a) have been implicated in calcium-mediated toxicity in many brain disorders. Here, we report generating SCA1 Tg mice in the ASIC1a knockout (KO) background and demonstrate that the deletion of ASIC1a gene expression causes suppression of the SCA1 disease phenotype. Loss of the ASIC1a channel in SCA1/ASIC1a KO mice resulted in the improvement of motor deficit and decreased PC degeneration. Interestingly, the expression of the ASIC1 variant, ASIC1b, was upregulated in the cerebellum of both SCA1/ASIC1a KO and ASIC1a KO animals as compared to the wild-type (WT) and SCA1 Tg mice. Further, these SCA1/ASIC1a KO mice exhibited translocation of PC calcium-binding protein calbindin-D28k from the nucleus to the cytosol in young animals, which otherwise have both cytosolic and nuclear localization. Furthermore, in addition to higher expression of calcium-buffering protein parvalbumin, PCs of the older SCA1/ASIC1a KO mice showed a decrease in morphologic abnormalities as compared to the age-matched SCA1 animals. Our data suggest that ASIC1a may be a mediator of SCA1 pathogenesis and targeting ASIC1a could be a novel approach to treat SCA1.

Intelligent subsystem interface for modular hardware system

NASA Technical Reports Server (NTRS)

Caffrey, Robert T. (Inventor); Krening, Douglas N. (Inventor); Lannan, Gregory B. (Inventor); Schneiderwind, Michael J. (Inventor); Schneiderwind, Robert A. (Inventor)

2000-01-01

A single chip application specific integrated circuit (ASIC) which provides a flexible, modular interface between a subsystem and a standard system bus. The ASIC includes a microcontroller/microprocessor, a serial interface for connection to the bus, and a variety of communications interface devices available for coupling to the subsystem. A three-bus architecture, utilizing arbitration, provides connectivity within the ASIC and between the ASIC and the subsystem. The communication interface devices include UART (serial), parallel, analog, and external device interface utilizing bus connections paired with device select signals. A low power (sleep) mode is provided as is a processor disable option.

VLSI technology for smaller, cheaper, faster return link systems

NASA Technical Reports Server (NTRS)

Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John

1994-01-01

Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.

ASIC1a Deficient Mice Show Unaltered Neurodegeneration in the Subacute MPTP Model of Parkinson Disease.

PubMed

Komnig, Daniel; Imgrund, Silke; Reich, Arno; Gründer, Stefan; Falkenburger, Björn H

2016-01-01

Inflammation contributes to the death of dopaminergic neurons in Parkinson disease and can be accompanied by acidification of extracellular pH, which may activate acid-sensing ion channels (ASIC). Accordingly, amiloride, a non-selective inhibitor of ASIC, was protective in an acute 1-methyl-4-phenyl-1,2,3,6-tetrahydropyridine (MPTP) mouse model of Parkinson disease. To complement these findings we determined MPTP toxicity in mice deficient for ASIC1a, the most common ASIC isoform in neurons. MPTP was applied i.p. in doses of 30 mg per kg on five consecutive days. We determined the number of dopaminergic neurons in the substantia nigra, assayed by stereological counting 14 days after the last MPTP injection, the number of Nissl positive neurons in the substantia nigra, and the concentration of catecholamines in the striatum. There was no difference between ASIC1a-deficient mice and wildtype controls. We are therefore not able to confirm that ASIC1a are involved in MPTP toxicity. The difference might relate to the subacute MPTP model we used, which more closely resembles the pathogenesis of Parkinson disease, or to further targets of amiloride.

Mobile Learning Based Worked Example in Electric Circuit (WEIEC) Application to Improve the High School Students' Electric Circuits Interpretation Ability

ERIC Educational Resources Information Center

Yadiannur, Mitra; Supahar

2017-01-01

This research aims to determine the feasibility and effectivity of mobile learning based Worked Example in Electric Circuits (WEIEC) application in improving the high school students' electric circuits interpretation ability on Direct Current Circuits materials. The research method used was a combination of Four-D Models and ADDIE model. The…

Osthole, a herbal compound, alleviates nucleus pulposus-evoked nociceptive responses through the suppression of overexpression of acid-sensing ion channel 3 (ASIC3) in rat dorsal root ganglion

PubMed Central

He, Qiu-Lan; Chen, Yuling; Qin, Jian; Mo, Sui-Lin; Wei, Ming; Zhang, Jin-Jun; Li, Mei-Na; Zou, Xue-Nong; Zhou, Shu-Feng; Chen, Xiao-Wu; Sun, Lai-Bao

2012-01-01

Summary Background Osthole (Ost), a natural coumarin derivative, has been shown to inhibit many pro-inflammatory mediators and block voltage-gated Na+ channels. During inflammation, acidosis is an important pain inducer which activates nociceptors by gating depolarizing cationic channels, such as acid-sensing ion channel 3 (ASIC3). The aim of this study was to examine the effects of Ost on nucleus pulposus-evoked nociceptive responses and ASIC3 over-expression in the rat dorsal root ganglion, and to investigate the possible mechanism. Material/Methods Radicular pain was generated with application of nucleus pulposus (NP) to nerve root. Mechanical allodynia was evaluated using von Frey filaments with logarithmically incremental rigidity to calculate the 50% probability thresholds for mechanical paw withdrawal. ASIC3 protein expression in dorsal root ganglions (DRGs) was assessed with Western blot and immunohistochemistry. Membrane potential (MP) shift of DRG neurons induced by ASIC3-sensitive acid (pH6.5) was determined by DiBAC4 (3) fluorescence intensity (F.I.). Results The NP-evoked mechanical hyperalgesia model showed allodynia for 3 weeks, and ASIC3 expression was up-regulated in DRG neurons, reaching peak on Day 7. Epidural administration of Ost induced a remarkable and prolonged antinociceptive effect, accompanied by an inhibition of over-expressed ASIC3 protein and of abnormal shift of MP. Amiloride (Ami), an antagonist of ASIC3, strengthened the antinociceptive effect of Ost. Conclusions Up-regulation of ASIC3 expression may be associated with NP-evoked mechanical hyperalgesia. A single epidural injection of Ost decreased ASIC3 expression in DGR neurons and the pain in the NP-evoked mechanical hyperalgesia model. Osthole may be of great benefit for preventing chronic pain status often seen in lumbar disc herniation (LDH). PMID:22648244

Design and characterization of the ePix10k: a high dynamic range integrating pixel ASIC for LCLS detectors

NASA Astrophysics Data System (ADS)

Caragiulo, P.; Dragone, A.; Markovic, B.; Herbst, R.; Nishimura, K.; Reese, B.; Herrmann, S.; Hart, P.; Blaj, G.; Segal, J.; Tomada, A.; Hasi, J.; Carini, G.; Kenney, C.; Haller, G.

2015-05-01

ePix10k is a variant of a novel class of integrating pixel ASICs architectures optimized for the processing of signals in second generation LINAC Coherent Light Source (LCLS) X-Ray cameras. The ASIC is optimized for high dynamic range application requiring high spatial resolution and fast frame rates. ePix ASICs are based on a common platform composed of a random access analog matrix of pixel with global shutter, fast parallel column readout, and dedicated sigma-delta analog to digital converters per column. The ePix10k variant has 100um×100um pixels arranged in a 176×192 matrix, a resolution of 140e- r.m.s. and a signal range of 3.5pC (10k photons at 8keV). In its final version it will be able to sustain a frame rate of 2kHz. A first prototype has been fabricated and characterized. Performance in terms of noise, linearity, uniformity, cross-talk, together with preliminary measurements with bump bonded sensors are reported here.

[Flexible print circuit technology application in biomedical engineering].

PubMed

Jiang, Lihua; Cao, Yi; Zheng, Xiaolin

2013-06-01

Flexible print circuit (FPC) technology has been widely applied in variety of electric circuits with high precision due to its advantages, such as low-cost, high specific fabrication ability, and good flexibility, etc. Recently, this technology has also been used in biomedical engineering, especially in the development of microfluidic chip and microelectrode array. The high specific fabrication can help making microelectrode and other micro-structure equipment. And good flexibility allows the micro devices based on FPC technique to be easily packaged with other parts. In addition, it also reduces the damage of microelectrodes to the tissue. In this paper, the application of FPC technology in biomedical engineering is introduced. Moreover, the important parameters of FPC technique and the development trend of prosperous applications is also discussed.

Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

NASA Astrophysics Data System (ADS)

Gao, W.; Liu, H.; Gan, B.; Hu, Y.

2014-05-01

In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e- to 180,000e-, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e- at zero farad plus 5.4 e- per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

Performance of an optical encoder based on a nondiffractive beam implemented with a specific photodetection integrated circuit and a diffractive optical element.

PubMed

Quintián, Fernando Perez; Calarco, Nicolás; Lutenberg, Ariel; Lipovetzky, José

2015-09-01

In this paper, we study the incremental signal produced by an optical encoder based on a nondiffractive beam (NDB). The NDB is generated by means of a diffractive optical element (DOE). The detection system is composed by an application specific integrated circuit (ASIC) sensor. The sensor consists of an array of eight concentric annular photodiodes, each one provided with a programmable gain amplifier. In this way, the system is able to synthesize a nonuniform detectivity. The contrast, amplitude, and harmonic content of the sinusoidal output signal are analyzed. The influence of the cross talk among the annular photodiodes is placed in evidence through the dependence of the signal contrast on the wavelength.

MUSIC: An 8 channel readout ASIC for SiPM arrays

NASA Astrophysics Data System (ADS)

Gómez, Sergio; Gascón, David; Fernández, Gerard; Sanuy, Andreu; Mauricio, Joan; Graciani, Ricardo; Sanchez, David

2016-04-01

This paper presents an 8 channel ASIC for SiPM anode readout based on a novel low input impedance current conveyor (under patent1). This Multiple Use SiPM Integrated Circuit (MUSIC) has been designed to serve several purposes, including, for instance, the readout of SiPM arrays for some of the Cherenkov Telescope Array (CTA) cameras. The current division scheme at the very front end part of the circuit splits the input current into differently scaled copies which are connected to independent current mirrors. The circuit contains a tunable pole zero cancellation of the SiPM recovery time constant to deal with sensors from different manufacturers. Decay times up to 100 ns are supported covering most of the available SiPM devices in the market. MUSIC offers three main features: (1) differential output of the sum of the individual input channels; (2) 8 individual single ended analog outputs and; (3) 8 individual binary outputs. The digital outputs encode the amount of collected charge in the duration of the digital signal using a time over threshold technique. For each individual channel, the user must select the analog or digital output. Each functionality, the signal sum and the 8 A/D outputs, include a selectable dual-gain configuration. Moreover, the signal sum implements dual-gain output providing a 15 bit dynamic range. Full die simulation results of the MUSIC designed using AMS 0.35 µm SiGe technology are presented: total die size of 9 mm2, 500 MHz bandwidth for channel sum and 150 MHz bandwidth for A/D channels, low input impedance (≍32 Ω), single photon output pulse width at half maximum (FWHM) between 5 and 10 ns and with a power consumption of ≍ 30 mW/ch plus ≍ 200 mW for the 8 ch sum. Encapsulated prototype samples of the MUSIC are expected by March 2016.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Britton, C.L.; Jagadish, U.; Bryan, W.L.

An Integrated Circuit (IC) readout chip with four channels arranged so as to receive input charge from the corners of the chip was designed for use with 5- to 7-mm pixel detectors. This Application Specific IC (ASIC) can be used for cold neutron imaging, for study of structural order in materials using cold neutron scattering or for particle physics experiments. The ASIC is fabricated in a 0.5-{micro}m n-well AMI process. The design of the ASIC and the test measurements made is reported. Noise measurements are also reported.

New APETx-like peptides from sea anemone Heteractis crispa modulate ASIC1a channels.

PubMed

Kalina, Rimma; Gladkikh, Irina; Dmitrenok, Pavel; Chernikov, Oleg; Koshelev, Sergey; Kvetkina, Aleksandra; Kozlov, Sergey; Kozlovskaya, Emma; Monastyrnaya, Margarita

2018-06-01

Sea anemones are an abundant source of various biologically active peptides. The hydrophobic 20% ethanol fraction of tropical sea anemone Heteractis crispa was shown to contain at least 159 peptide compounds including neurotoxins, proteinase and α-amylase inhibitors, as well as modulators of acid-sensing ion channels (ASICs). The three new peptides, π-AnmTX Hcr 1b-2, -3, and -4 (41 aa) (short names Hcr 1b-2, -3, -4), identified by a combination of reversed-phase liquid chromatography and mass spectrometry were found to belong to the class 1b sea anemone neurotoxins. The amino acid sequences of these peptides were determined by Edman degradation and tandem mass spectrometry. The percent of identity of Hcr 1b-2, -3, and -4 with well-known ASIC3 inhibitors Hcr 1b-1 from H. crispa and APETx2 from Anthopleura elegantissima is 95-78% and 46-49%, respectively. Electrophysiological experiments on homomeric ASIC channels expressed in Xenopus laevis oocytes establish that these peptides are the first inhibitors of ASIC1a derived from sea anemone venom. The major peptide, Hcr 1b-2, inhibited both rASIC1a (IC 50 4.8 ± 0.3 μM; nH 0.92 ± 0.05) and rASIC3 (IC 50 15.9 ± 1.1 μM; nH 1.0 ± 0.05). The maximum inhibition at saturating peptide concentrations reached 64% and 81%, respectively. In the model of acid-induced muscle pain Hcr 1b-2 was also shown to exhibit an antihyperalgesic effect, significantly reducing of the pain threshold of experimental animals. Copyright © 2018 Elsevier Inc. All rights reserved.

Multi-element germanium detectors for synchrotron applications

NASA Astrophysics Data System (ADS)

Rumaiz, A. K.; Kuczewski, A. J.; Mead, J.; Vernon, E.; Pinelli, D.; Dooryhee, E.; Ghose, S.; Caswell, T.; Siddons, D. P.; Miceli, A.; Baldwin, J.; Almer, J.; Okasinski, J.; Quaranta, O.; Woods, R.; Krings, T.; Stock, S.

2018-04-01

We have developed a series of monolithic multi-element germanium detectors, based on sensor arrays produced by the Forschungzentrum Julich, and on Application-specific integrated circuits (ASICs) developed at Brookhaven. Devices have been made with element counts ranging from 64 to 384. These detectors are being used at NSLS-II and APS for a range of diffraction experiments, both monochromatic and energy-dispersive. Compact and powerful readout systems have been developed, based on the new generation of FPGA system-on-chip devices, which provide closely coupled multi-core processors embedded in large gate arrays. We will discuss the technical details of the systems, and present some of the results from them.

VHDL Modeling and Simulation of a Digital Image Synthesizer for Countering ISAR

DTIC Science & Technology

2003-06-01

This thesis discusses VHDL modeling and simulation of a full custom Application Specific Integrated Circuit (ASIC) for a Digital Image Synthesizer...necessary for a given application . With such a digital method, it is possible for a small ship to appear as large as an aircraft carrier or any high...INTRODUCTION TO DIGITAL IMAGE SYNTHESIZER (DIS) A. BACKGROUND The Digital Image Synthesizer (DIS) is an Application Specific Integrated Circuit

Memory-Based Structured Application Specific Integrated Circuit (ASIC) Study

DTIC Science & Technology

2008-10-01

memory interface, arbiter/ schedulers for rescheduling the memory requests according to some schedule policy, and memory channels for communicating...between the power-savings and the wakeup overhead with respect to both wakeup power and wakeup delay. For example, dream mode can save 50% more static...power than sleep mode, but at the expense of twice the wake delay and three times the wakeup energy. The user can specify power-gating modes for various components.

Genetic variation in the ASIC3 gene influences blood pressure levels in Taiwanese.

PubMed

Ko, Yu-Lin; Hsu, Lung-An; Wu, Semon; Teng, Ming-Sheng; Chang, Hsien-Hsun; Chen, Chih-Cheng; Cheng, Ching-Feng

2008-11-01

The acid-sensing ion channel 3 (ASIC3) is a ligand-gated cation channel activated by extracellular protons, and is associated with an exercise-induced pressor reflex and possibly autonomic imbalance. To test the statistical association between genetic polymorphisms of the ASIC3 gene and blood pressure (BP) variations in Taiwanese, 551 unrelated individuals (286 men and 265 women) were recruited from a routine health examination. The participants had no prior history of cardiovascular disease or medication use for hypertension. Six ASIC3 gene polymorphisms were genotyped; three were polymorphic, and only the rs2288646 polymorphism was associated with variations in BP among participants. Significantly higher systolic, diastolic, and mean BP were observed in participants carrying the rs2288646-A allele (P=0.034, 0.023, and 0.010, respectively). Significantly higher frequencies of the rs2288646-A-containing genotype were observed in normotensive, prehypertensive, and hypertensive subgroups (P for trend=0.026); and in those with higher systolic and diastolic BPs (P for trend=0.005 and P for trend=0.002, respectively). The association between the rs2288646-A allele and BP persisted even after adjustment for age, sex, BMI, and other metabolic factors. When a second independent group of 403 individuals was combined with the first group of 551 (n=954), a significantly higher frequency of the rs2288646-A-containing genotype was observed in participants with hypertension (9.7 vs. 4.0%, P=0.003). Our data showed an independent association between an ASIC3 genetic polymorphism and BP variations in Taiwanese. These results suggest that the ASIC3 may be involved in BP regulation.

Development of cryogenic CMOS Readout ASICs for the Point-Contact HPGe Detectors for Dark Matter Search and Neutrino Experiments

NASA Astrophysics Data System (ADS)

Deng, Zhi; He, Li; Liu, Feng; Liu, Yinong; Xue, Tao; Li, Yulan; Yue, Qian

2017-05-01

The paper presents the developments of two cryogenic readout ASICs for the point-contact HPGe detectors for dark matter search and neutrino experiments. Extremely low noise readout electronics were demanded and the capability of working at cryogenic temperatures may bring great advantages. The first ASIC was a monolithic CMOS charge sensitive preamplifier with its noise optimized for ∼1 pF input capacitance. The second ASIC was a waveform recorder based on switched capacitor array. These two ASICs were fabricated in CMOS 350 nm and 180 nm processes respectively. The prototype chips were tested and showed promising results. Both ASICs worked well at low temperature. The preamplifier had achieved ENC of 10.3 electrons with 0.7 pF input capacitance and the SCA chip could run at 9 bit effective resolution and 25 MSPS sampling rate.

Resveratrol attenuates bone cancer pain through regulating the expression levels of ASIC3 and activating cell autophagy.

PubMed

Zhu, Haili; Ding, Jieqiong; Wu, Ji; Liu, Tingting; Liang, Jing; Tang, Qiong; Jiao, Ming

2017-11-01

Bone cancer pain (BCP) is one of the most common pains in patients with malignant cancers. The mechanism underlying BCP is largely unknown. Our previous studies and the increasing evidence both have shown that acid-sensing ion channels 3 (ASIC3) is an important protein in the pathological pain state in some pain models. We hypothesized that the expression change of ASIC3 might be one of the factors related to BCP. In this study, we established the BCP model through intrathecally injecting rat mammary gland carcinoma cells (MRMT-1) into the left tibia of Sprague-Dawley female rats, and found that the BCP rats showed bone destruction, increased mechanical pain sensitivities and up-regulated ASIC3 protein expression levels in L4-L6 dorsal root ganglion. Then, resveratrol, which was intraperitoneally injected into the BCP rats on post-operative Day 21, dose-dependently increased the paw withdrawal threshold of BCP rats, reversed the pain behavior, and had an antinociceptive effect on BCP rats. In ASIC3-transfected SH-SY5Y cells, the ASIC3 protein expression levels were regulated by resveratrol in a dose- and time-dependent manner. Meanwhile, resveratrol also had an antinociceptive effect in ASIC3-mediated pain rat model. Furthermore, resveratrol also enhanced the phosphorylation of AMPK, SIRT1, and LC3-II levels in ASIC3-transfected SH-SY5Y cells, indicating that resveratrol could activate the AMPK-SIRT1-autophagy signal pathway in ASIC3-transfected SH-SY5Y cells. In BCP rats, SIRT1 and LC3-II were also down-regulated. These findings provide new evidence for the use of resveratrol as a therapeutic treatment during BCP states. © The Author 2017. Published by Oxford University Press on behalf of the Institute of Biochemistry and Cell Biology, Shanghai Institutes for Biological Sciences, Chinese Academy of Sciences. All rights reserved. For permissions, please e-mail: journals.permissions@oup.com.

Development of a flight qualified 100 x 100 mm MCP UV detector using advanced cross strip anodes and associated ASIC electronics

NASA Astrophysics Data System (ADS)

Vallerga, John; McPhate, Jason; Tremsin, Anton; Siegmund, Oswald; Raffanti, Rick; Cumming, Harley; Seljak, Andrej; Virta, Vihtori; Varner, Gary

2016-07-01

Photon counting microchannel plate (MCP) imagers have been the detector of choice for most UV astronomical missions over the last three decades (e.g. EUVE, FUSE, COS on Hubble etc.) and been mentioned for instruments on future large telescopes in space such as LUVOIR14. Using cross strip anodes, improvements in the MCP laboratory readout technology have resulted in better spatial resolution (x10), temporal resolution (x 1000) and output event rate (x100), all the while operating at lower gain (x10) resulting in lower high voltage requirements and longer MCP lifetimes. A crossed strip anode MCP readout starts with a set of orthogonal conducting strips (e.g. 80 x 80), typically spaced at a 635 micron pitch onto which charge clouds from MCP amplified events land. Each strip has its own charge sensitive amplifier that is sampled continuously by a dedicated analog to digital converter (ADC). All of the ADC digital output lines are fed into a field programmable gate array (FGPA) which can detect charge events landing on the strips, measure the peak amplitudes of those charge events and calculate their spatial centroid along with their time of arrival (X,Y,T) and pass this information to a downstream computer. Laboratory versions of these electronics have demonstrated < 20 microns FWHM spatial resolution, count rates on the order of 2 MHz, and temporal resolution of 1ns. In 2012 our group at U.C. Berkeley, along with our partners at the U. Hawaii, received a NASA Strategic Astrophysics Technology (SAT) grant to raise the TRL of a cross strip detector from 4 to 6 by replacing most of the 19" rack mounted, high powered electronics with application specific integrated circuits (ASICs) which will lower the power, mass, and volume requirements of the detector electronics. We were also tasked to design and fabricate a "standard" 50mm square active area MCP detector incorporating these electronics that can be environmentally qualified for flight (temperature, vacuum, vibration

ASICs Approach for the Implementation of a Symmetric Triangular Fuzzy Coprocessor and Its Application to Adaptive Filtering

NASA Technical Reports Server (NTRS)

Starks, Scott; Abdel-Hafeez, Saleh; Usevitch, Bryan

1997-01-01

This paper discusses the implementation of a fuzzy logic system using an ASICs design approach. The approach is based upon combining the inherent advantages of symmetric triangular membership functions and fuzzy singleton sets to obtain a novel structure for fuzzy logic system application development. The resulting structure utilizes a fuzzy static RAM to store the rule-base and the end-points of the triangular membership functions. This provides advantages over other approaches in which all sampled values of membership functions for all universes must be stored. The fuzzy coprocessor structure implements the fuzzification and defuzzification processes through a two-stage parallel pipeline architecture which is capable of executing complex fuzzy computations in less than 0.55us with an accuracy of more than 95%, thus making it suitable for a wide range of applications. Using the approach presented in this paper, a fuzzy logic rule-base can be directly downloaded via a host processor to an onchip rule-base memory with a size of 64 words. The fuzzy coprocessor's design supports up to 49 rules for seven fuzzy membership functions associated with each of the chip's two input variables. This feature allows designers to create fuzzy logic systems without the need for additional on-board memory. Finally, the paper reports on simulation studies that were conducted for several adaptive filter applications using the least mean squared adaptive algorithm for adjusting the knowledge rule-base.

Inspecting Engineering Samples

NASA Image and Video Library

2017-12-08

Goddard's Ritsko Wins 2011 SAVE Award The winner of the 2011 SAVE Award is Matthew Ritsko, a Goddard financial manager. His tool lending library would track and enable sharing of expensive space-flight tools and hardware after projects no longer need them. This set of images represents the types of tools used at NASA. To read more go to: www.nasa.gov/topics/people/features/ritsko-save.html Dr. Doug Rabin (Code 671) and PI La Vida Cooper (Code 564) inspect engineering samples of the HAS-2 imager which will be tested and readout using a custom ASIC with a 16-bit ADC (analog to digital converter) and CDS (correlated double sampling) circuit designed by the Code 564 ASIC group as a part of an FY10 IRAD. The purpose of the IRAD was to develop and high resolution digitizer for Heliophysics applications such as imaging. Future goals for the collaboration include characterization testing and eventually a sounding rocket flight of the integrated system. *ASIC= Application Specific Integrated Circuit NASA/GSFC/Chris Gunn

The function and regulation of acid‐sensing ion channels (ASICs) and the epithelial Na+ channel (ENaC): IUPHAR Review 19

PubMed Central

Boscardin, Emilie; Alijevic, Omar; Hummler, Edith

2016-01-01

Acid‐sensing ion channels (ASICs) and the epithelial Na+ channel (ENaC) are both members of the ENaC/degenerin family of amiloride‐sensitive Na+ channels. ASICs act as proton sensors in the nervous system where they contribute, besides other roles, to fear behaviour, learning and pain sensation. ENaC mediates Na+ reabsorption across epithelia of the distal kidney and colon and of the airways. ENaC is a clinically used drug target in the context of hypertension and cystic fibrosis, while ASIC is an interesting potential target. Following a brief introduction, here we will review selected aspects of ASIC and ENaC function. We discuss the origin and nature of pH changes in the brain and the involvement of ASICs in synaptic signalling. We expose how in the peripheral nervous system, ASICs cover together with other ion channels a wide pH range as proton sensors. We introduce the mechanisms of aldosterone‐dependent ENaC regulation and the evidence for an aldosterone‐independent control of ENaC activity, such as regulation by dietary K+. We then provide an overview of the regulation of ENaC by proteases, a topic of increasing interest over the past few years. In spite of the profound differences in the physiological and pathological roles of ASICs and ENaC, these channels share many basic functional and structural properties. It is likely that further research will identify physiological contexts in which ASICs and ENaC have similar or overlapping roles. PMID:27278329

Coxsackievirus and adenovirus receptor (CAR) mediates trafficking of acid sensing ion channel 3 (ASIC3) via PSD-95.

PubMed

Excoffon, Katherine J D A; Kolawole, Abimbola O; Kusama, Nobuyoshi; Gansemer, Nicholas D; Sharma, Priyanka; Hruska-Hageman, Alesia M; Petroff, Elena; Benson, Christopher J

2012-08-17

We have previously shown that the Coxsackievirus and adenovirus receptor (CAR) can interact with post-synaptic density 95 (PSD-95) and localize PSD-95 to cell-cell junctions. We have also shown that activity of the acid sensing ion channel (ASIC3), a H(+)-gated cation channel that plays a role in mechanosensation and pain signaling, is negatively modulated by PSD-95 through a PDZ-based interaction. We asked whether CAR and ASIC3 simultaneously interact with PSD-95, and if so, whether co-expression of these proteins alters their cellular distribution and localization. Results indicate that CAR and ASIC3 co-immunoprecipitate only when co-expressed with PSD-95. CAR also brings both PSD-95 and ASIC3 to the junctions of heterologous cells. Moreover, CAR rescues PSD-95-mediated inhibition of ASIC3 currents. These data suggest that, in addition to activity as a viral receptor and adhesion molecule, CAR can play a role in trafficking proteins, including ion channels, in a PDZ-based scaffolding complex. Copyright © 2012 Elsevier Inc. All rights reserved.

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array—Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

PubMed Central

Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-01-01

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array—application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384. PMID:28672813

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

PubMed

Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-06-24

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

NASA Astrophysics Data System (ADS)

Gupta, Neha; Parihar, Priyanka; Neema, Vaibhav

2018-04-01

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells. If we want to reduce the overall power in the memory system, we have to work on the input circuitry of memory architecture i.e. row and column decoder. In this research work, low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed. In this work, the comparison of cluster DECODER, body bias DECODER, source bias DECODER, and source coupling DECODER are designed and analyzed for memory array application. Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool. Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92% and static energy by 99.92% at a supply voltage of 1.2 V. The proposed circuit also improves dynamic power dissipation by 5.69%, dynamic PDP/EDP 65.03% and delay 57.25% at 1.2 V supply voltage.

Performance study of SKIROC2/A ASIC for ILD Si-W ECAL

NASA Astrophysics Data System (ADS)

Suehara, T.; Sekiya, I.; Callier, S.; Balagura, V.; Boudry, V.; Brient, J.-C.; de la Taille, C.; Kawagoe, K.; Irles, A.; Magniette, F.; Nanni, J.; Pöschl, R.; Yoshioka, T.

2018-03-01

The ILD Si-W ECAL is a sampling calorimeter with tungsten absorber and highly segmented silicon layers for the International Large Detector (ILD), one of the two detector concepts for the International Linear Collider. SKIROC2 is an ASIC for the ILD Si-W ECAL. To investigate the issues found in prototype detectors, we prepared dedicated ASIC evaluation boards with either BGA sockets or directly soldered SKIROC2. We report a performance study with the evaluation boards, including signal-to-noise ratio and TDC performance with comparing SKIROC2 and an updated version, SKIROC2A.

Knockout of the ASIC2 channel in mice does not impair cutaneous mechanosensation, visceral mechanonociception and hearing

PubMed Central

Roza, Carolina; Puel, Jean-Luc; Kress, Michaela; Baron, Anne; Diochot, Sylvie; Lazdunski, Michel; Waldmann, Rainer

2004-01-01

Mechanosensitive cation channels are thought to be crucial for different aspects of mechanoperception, such as hearing and touch sensation. In the nematode C. elegans, the degenerins MEC-4 and MEC-10 are involved in mechanosensation and were proposed to form mechanosensitive cation channels. Mammalian degenerin homologues, the H+-gated ASIC channels, are expressed in sensory neurones and are therefore interesting candidates for mammalian mechanosensors. We investigated the effect of an ASIC2 gene knockout in mice on hearing and on cutaneous mechanosensation and visceral mechanonociception. However, our data do not support a role of ASIC2 in those facets of mechanoperception. PMID:15169849

High temperature superconducting thin film microwave circuits: Fabrication, characterization, and applications

NASA Technical Reports Server (NTRS)

Bhasin, K. B.; Warner, J. D.; Romanofsky, R. R.; Heinen, V. O.; Chorey, C. M.

1990-01-01

Epitaxial YBa2Cu3O7 films were grown on several microwave substrates. Surface resistance and penetration depth measurements were performed to determine the quality of these films. Here the properties of these films on key microwave substrates are described. The fabrication and characterization of a microwave ring resonator circuit to determine transmission line losses are presented. Lower losses than those observed in gold resonator circuits were observed at temperatures lower than critical transition temperature. Based on these results, potential applications of microwave superconducting circuits such as filters, resonators, oscillators, phase shifters, and antenna elements in space communication systems are identified.

High temperature superconducting thin film microwave circuits - Fabrication, characterization, and applications

NASA Technical Reports Server (NTRS)

Bhasin, K. B.; Warner, J. D.; Romanofsky, R. R.; Heinen, V. O.; Chorey, C. M.

1990-01-01

Epitaxial YBa2Cu3O7 films were grown on several microwave substrates. Surface resistance and penetration depth measurements were performed to determine the quality of these films. Here, the properties of these films on key microwave substrates are described. The fabrication and characterization of a microwave ring resonator circuit to determine transmission line losses are presented. Lower losses than those observed in gold resonator circuits were observed at temperatures lower than critical transition temperature. Based on these results, potential applications of microwave superconducting circuits such as filters, resonators, oscillators, phase shifters, and antenna elements in space communication systems are identified.

Energy dispersive CdTe and CdZnTe detectors for spectral clinical CT and NDT applications

NASA Astrophysics Data System (ADS)

Barber, W. C.; Wessel, J. C.; Nygard, E.; Iwanczyk, J. S.

2015-06-01

We are developing room temperature compound semiconductor detectors for applications in energy-resolved high-flux single x-ray photon-counting spectral computed tomography (CT), including functional imaging with nanoparticle contrast agents for medical applications and non-destructive testing (NDT) for security applications. Energy-resolved photon-counting can provide reduced patient dose through optimal energy weighting for a particular imaging task in CT, functional contrast enhancement through spectroscopic imaging of metal nanoparticles in CT, and compositional analysis through multiple basis function material decomposition in CT and NDT. These applications produce high input count rates from an x-ray generator delivered to the detector. Therefore, in order to achieve energy-resolved single photon counting in these applications, a high output count rate (OCR) for an energy-dispersive detector must be achieved at the required spatial resolution and across the required dynamic range for the application. The required performance in terms of the OCR, spatial resolution, and dynamic range must be obtained with sufficient field of view (FOV) for the application thus requiring the tiling of pixel arrays and scanning techniques. Room temperature cadmium telluride (CdTe) and cadmium zinc telluride (CdZnTe) compound semiconductors, operating as direct conversion x-ray sensors, can provide the required speed when connected to application specific integrated circuits (ASICs) operating at fast peaking times with multiple fixed thresholds per pixel provided the sensors are designed for rapid signal formation across the x-ray energy ranges of the application at the required energy and spatial resolutions, and at a sufficiently high detective quantum efficiency (DQE). We have developed high-flux energy-resolved photon-counting x-ray imaging array sensors using pixellated CdTe and CdZnTe semiconductors optimized for clinical CT and security NDT. We have also fabricated high

Energy dispersive CdTe and CdZnTe detectors for spectral clinical CT and NDT applications

PubMed Central

Barber, W. C.; Wessel, J. C.; Nygard, E.; Iwanczyk, J. S.

2014-01-01

We are developing room temperature compound semiconductor detectors for applications in energy-resolved high-flux single x-ray photon-counting spectral computed tomography (CT), including functional imaging with nanoparticle contrast agents for medical applications and non destructive testing (NDT) for security applications. Energy-resolved photon-counting can provide reduced patient dose through optimal energy weighting for a particular imaging task in CT, functional contrast enhancement through spectroscopic imaging of metal nanoparticles in CT, and compositional analysis through multiple basis function material decomposition in CT and NDT. These applications produce high input count rates from an x-ray generator delivered to the detector. Therefore, in order to achieve energy-resolved single photon counting in these applications, a high output count rate (OCR) for an energy-dispersive detector must be achieved at the required spatial resolution and across the required dynamic range for the application. The required performance in terms of the OCR, spatial resolution, and dynamic range must be obtained with sufficient field of view (FOV) for the application thus requiring the tiling of pixel arrays and scanning techniques. Room temperature cadmium telluride (CdTe) and cadmium zinc telluride (CdZnTe) compound semiconductors, operating as direct conversion x-ray sensors, can provide the required speed when connected to application specific integrated circuits (ASICs) operating at fast peaking times with multiple fixed thresholds per pixel provided the sensors are designed for rapid signal formation across the x-ray energy ranges of the application at the required energy and spatial resolutions, and at a sufficiently high detective quantum efficiency (DQE). We have developed high-flux energy-resolved photon-counting x-ray imaging array sensors using pixellated CdTe and CdZnTe semiconductors optimized for clinical CT and security NDT. We have also fabricated high

Energy dispersive CdTe and CdZnTe detectors for spectral clinical CT and NDT applications.

PubMed

Barber, W C; Wessel, J C; Nygard, E; Iwanczyk, J S

2015-06-01

We are developing room temperature compound semiconductor detectors for applications in energy-resolved high-flux single x-ray photon-counting spectral computed tomography (CT), including functional imaging with nanoparticle contrast agents for medical applications and non destructive testing (NDT) for security applications. Energy-resolved photon-counting can provide reduced patient dose through optimal energy weighting for a particular imaging task in CT, functional contrast enhancement through spectroscopic imaging of metal nanoparticles in CT, and compositional analysis through multiple basis function material decomposition in CT and NDT. These applications produce high input count rates from an x-ray generator delivered to the detector. Therefore, in order to achieve energy-resolved single photon counting in these applications, a high output count rate (OCR) for an energy-dispersive detector must be achieved at the required spatial resolution and across the required dynamic range for the application. The required performance in terms of the OCR, spatial resolution, and dynamic range must be obtained with sufficient field of view (FOV) for the application thus requiring the tiling of pixel arrays and scanning techniques. Room temperature cadmium telluride (CdTe) and cadmium zinc telluride (CdZnTe) compound semiconductors, operating as direct conversion x-ray sensors, can provide the required speed when connected to application specific integrated circuits (ASICs) operating at fast peaking times with multiple fixed thresholds per pixel provided the sensors are designed for rapid signal formation across the x-ray energy ranges of the application at the required energy and spatial resolutions, and at a sufficiently high detective quantum efficiency (DQE). We have developed high-flux energy-resolved photon-counting x-ray imaging array sensors using pixellated CdTe and CdZnTe semiconductors optimized for clinical CT and security NDT. We have also fabricated high

Evidence that activation of ASIC1a by acidosis increases osteoclast migration and adhesion by modulating integrin/Pyk2/Src signaling pathway.

PubMed

Li, X; Ye, J-X; Xu, M-H; Zhao, M-D; Yuan, F-L

2017-07-01

Activated acid-sensing ion channel 1a (ASIC1a) is involved in acid-induced osteoclastogenesis by regulating activation of the transcription factor NFATc1. These results indicated that ASIC1a activation by extracellular acid may cause osteoclast migration and adhesion through Ca 2+ -dependent integrin/Pyk2/Src signaling pathway. Osteoclast adhesion and migration are responsible for osteoporotic bone loss. Acidic conditions promote osteoclastogenesis. ASIC1a in osteoclasts is associated with acid-induced osteoclastogenesis through modulating transcription factor NFATc1 activation. However, the influence and the detailed mechanism of ASIC1a in regulating osteoclast adhesion and migration, in response to extracellular acid, are not well characterized. In this study, knockdown of ASIC1a was achieved in bone marrow macrophage cells using small interfering RNA (siRNA). The adhesion and migration abilities of osteoclast precursors and osteoclasts were determined by adhesion and migration assays, in vitro. Bone resorption was performed to measure osteoclast function. Cytoskeletal changes were assessed by F-actin ring formation. αvβ3 integrin expression in osteoclasts was measured by flow cytometry. Western blotting and co-immunoprecipitation were performed to measure alterations in integrin/Pyk2/Src signaling pathway. Our results showed that blockade of ASIC1a using ASIC1a-siRNA inhibited acid-induced osteoclast precursor migration and adhesion, as well as osteoclast adhesion and bone resorption; we also demonstrated that inhibition of ASIC1a decreased the cell surface αvβ3 integrin and β3 protein expression. Moreover, blocking of ASIC1a inhibited acidosis-induced actin ring formation and reduced Pyk2 and Src phosphorylation in osteoclasts and also inhibited the acid-induced association of the αvβ3 integrin/Src/Pyk2. Together, these results highlight a key functional role of ASIC1a/αvβ3 integrin/Pyk2/Src signaling pathway in migration and adhesion of osteoclasts.

CLARO: an ASIC for high rate single photon counting with multi-anode photomultipliers

NASA Astrophysics Data System (ADS)

Baszczyk, M.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Dorosz, P.; Fiorini, M.; Gotti, C.; Kucewicz, W.; Malaguti, R.; Pessina, G.

2017-08-01

The CLARO is a radiation-hard 8-channel ASIC designed for single photon counting with multi-anode photomultiplier tubes. Each channel outputs a digital pulse when the input signal from the photomultiplier crosses a configurable threshold. The fast return to baseline, typically within 25 ns, and below 50 ns in all conditions, allows to count up to 107 hits/s on each channel, with a power consumption of about 1 mW per channel. The ASIC presented here is a much improved version of the first 4-channel prototype. The threshold can be precisely set in a wide range, between 30 ke- (5 fC) and 16 Me- (2.6 pC). The noise of the amplifier with a 10 pF input capacitance is 3.5 ke- (0.6 fC) RMS. All settings are stored in a 128-bit configuration and status register, protected against soft errors with triple modular redundancy. The paper describes the design of the ASIC at transistor-level, and demonstrates its performance on the test bench.

Macromodels of digital integrated circuits for program packages of circuit engineering design

NASA Astrophysics Data System (ADS)

Petrenko, A. I.; Sliusar, P. B.; Timchenko, A. P.

1984-04-01

Various aspects of the generation of macromodels of digital integrated circuits are examined, and their effective application in program packages of circuit engineering design is considered. Three levels of macromodels are identified, and the application of such models to the simulation of circuit outputs is discussed.

High Rate Digital Demodulator ASIC

NASA Technical Reports Server (NTRS)

Ghuman, Parminder; Sheikh, Salman; Koubek, Steve; Hoy, Scott; Gray, Andrew

1998-01-01

The architecture of High Rate (600 Mega-bits per second) Digital Demodulator (HRDD) ASIC capable of demodulating BPSK and QPSK modulated data is presented in this paper. The advantages of all-digital processing include increased flexibility and reliability with reduced reproduction costs. Conventional serial digital processing would require high processing rates necessitating a hardware implementation in other than CMOS technology such as Gallium Arsenide (GaAs) which has high cost and power requirements. It is more desirable to use CMOS technology with its lower power requirements and higher gate density. However, digital demodulation of high data rates in CMOS requires parallel algorithms to process the sampled data at a rate lower than the data rate. The parallel processing algorithms described here were developed jointly by NASA's Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL). The resulting all-digital receiver has the capability to demodulate BPSK, QPSK, OQPSK, and DQPSK at data rates in excess of 300 Mega-bits per second (Mbps) per channel. This paper will provide an overview of the parallel architecture and features of the HRDR ASIC. In addition, this paper will provide an over-view of the implementation of the hardware architectures used to create flexibility over conventional high rate analog or hybrid receivers. This flexibility includes a wide range of data rates, modulation schemes, and operating environments. In conclusion it will be shown how this high rate digital demodulator can be used with an off-the-shelf A/D and a flexible analog front end, both of which are numerically computer controlled, to produce a very flexible, low cost high rate digital receiver.

Vehicle-based vision sensors for intelligent highway systems

NASA Astrophysics Data System (ADS)

Masaki, Ichiro

1989-09-01

This paper describes a vision system, based on ASIC (Application Specific Integrated Circuit) approach, for vehicle guidance on highways. After reviewing related work in the fields of intelligent vehicles, stereo vision, and ASIC-based approaches, the paper focuses on a stereo vision system for intelligent cruise control. The system measures the distance to the vehicle in front using trinocular triangulation. An application specific processor architecture was developed to offer low mass-production cost, real-time operation, low power consumption, and small physical size. The system was installed in the trunk of a car and evaluated successfully on highways.

Cryogenic and radiation-hard asic for interfacing large format NIR/SWIR detector arrays

NASA Astrophysics Data System (ADS)

Gao, Peng; Dupont, Benoit; Dierickx, Bart; Müller, Eric; Verbruggen, Geert; Gielis, Stijn; Valvekens, Ramses

2017-11-01

For scientific and earth observation space missions, weight and power consumption is usually a critical factor. In order to obtain better vehicle integration, efficiency and controllability for large format NIR/SWIR detector arrays, a prototype ASIC is designed. It performs multiple detector array interfacing, power regulation and data acquisition operations inside the cryogenic chambers. Both operation commands and imaging data are communicated via the SpaceWire interface which will significantly reduce the number of wire goes in and out the cryogenic chamber. This "ASIC" prototype is realized in 0.18um CMOS technology and is designed for radiation hardness.

Handheld ultrasound array imaging device

NASA Astrophysics Data System (ADS)

Hwang, Juin-Jet; Quistgaard, Jens

1999-06-01

A handheld ultrasound imaging device, one that weighs less than five pounds, has been developed for diagnosing trauma in the combat battlefield as well as a variety of commercial mobile diagnostic applications. This handheld device consists of four component ASICs, each is designed using the state of the art microelectronics technologies. These ASICs are integrated with a convex array transducer to allow high quality imaging of soft tissues and blood flow in real time. The device is designed to be battery driven or ac powered with built-in image storage and cineloop playback capability. Design methodologies of a handheld device are fundamentally different to those of a cart-based system. As system architecture, signal and image processing algorithm as well as image control circuit and software in this device is deigned suitably for large-scale integration, the image performance of this device is designed to be adequate to the intent applications. To elongate the battery life, low power design rules and power management circuits are incorporated in the design of each component ASIC. The performance of the prototype device is currently being evaluated for various applications such as a primary image screening tool, fetal imaging in Obstetrics, foreign object detection and wound assessment for emergency care, etc.

Multi-element germanium detectors for synchrotron applications

DOE PAGES

Rumaiz, A. K.; Kuczewski, A. J.; Mead, J.; ...

2018-04-27

In this paper, we have developed a series of monolithic multi-element germanium detectors, based on sensor arrays produced by the Forschungzentrum Julich, and on Application-specific integrated circuits (ASICs) developed at Brookhaven. Devices have been made with element counts ranging from 64 to 384. These detectors are being used at NSLS-II and APS for a range of diffraction experiments, both monochromatic and energy-dispersive. Compact and powerful readout systems have been developed, based on the new generation of FPGA system-on-chip devices, which provide closely coupled multi-core processors embedded in large gate arrays. Finally, we will discuss the technical details of the systems,more » and present some of the results from them.« less

Multi-element germanium detectors for synchrotron applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rumaiz, A. K.; Kuczewski, A. J.; Mead, J.

In this paper, we have developed a series of monolithic multi-element germanium detectors, based on sensor arrays produced by the Forschungzentrum Julich, and on Application-specific integrated circuits (ASICs) developed at Brookhaven. Devices have been made with element counts ranging from 64 to 384. These detectors are being used at NSLS-II and APS for a range of diffraction experiments, both monochromatic and energy-dispersive. Compact and powerful readout systems have been developed, based on the new generation of FPGA system-on-chip devices, which provide closely coupled multi-core processors embedded in large gate arrays. Finally, we will discuss the technical details of the systems,more » and present some of the results from them.« less

System-Level Integrated Circuit (SLIC) development for phased array antenna applications

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Raquet, C. A.

1991-01-01

A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

System-level integrated circuit (SLIC) development for phased array antenna applications

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Raquet, C. A.

1991-01-01

A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

Implementation of the Timepix ASIC in the Scalable Readout System

NASA Astrophysics Data System (ADS)

Lupberger, M.; Desch, K.; Kaminski, J.

2016-09-01

We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

Characterization of the ePix100 prototype: a front-end ASIC for second-generation LCLS integrating hybrid pixel detectors

NASA Astrophysics Data System (ADS)

Caragiulo, P.; Dragone, A.; Markovic, B.; Herbst, R.; Nishimura, K.; Reese, B.; Herrmann, S.; Hart, P.; Blaj, G.; Segal, J.; Tomada, A.; Hasi, J.; Carini, G.; Kenney, C.; Haller, G.

2014-09-01

ePix100 is the first variant of a novel class of integrating pixel ASICs architectures optimized for the processing of signals in second generation LINAC Coherent Light Source (LCLS) X-Ray cameras. ePix100 is optimized for ultra-low noise application requiring high spatial resolution. ePix ASICs are based on a common platform composed of a random access analog matrix of pixel with global shutter, fast parallel column readout, and dedicated sigma-delta analog to digital converters per column. The ePix100 variant has 50μmx50μm pixels arranged in a 352x384 matrix, a resolution of 50e- r.m.s. and a signal range of 35fC (100 photons at 8keV). In its final version it will be able to sustain a frame rate of 1kHz. A first prototype has been fabricated and characterized and the measurement results are reported here.

Design and application of cotranscriptional non-enzymatic RNA circuits and signal transducers

PubMed Central

Bhadra, Sanchita; Ellington, Andrew D.

2014-01-01

Nucleic acid circuits are finding increasing real-life applications in diagnostics and synthetic biology. Although DNA has been the main operator in most nucleic acid circuits, transcriptionally produced RNA circuits could provide powerful alternatives for reagent production and their use in cells. Towards these goals, we have implemented a particular nucleic acid circuit, catalytic hairpin assembly, using RNA for both information storage and processing. Our results demonstrated that the design principles developed for DNA circuits could be readily translated to engineering RNA circuits that operated with similar kinetics and sensitivities of detection. Not only could purified RNA hairpins perform amplification reactions but RNA hairpins transcribed in vitro also mediated amplification, even without purification. Moreover, we could read the results of the non-enzymatic amplification reactions using a fluorescent RNA aptamer ‘Spinach’ that was engineered to undergo sequence-specific conformational changes. These advances were applied to the end-point and real-time detection of the isothermal strand displacement amplification reaction that produces single-stranded DNAs as part of its amplification cycle. We were also able to readily engineer gate structures with RNA similar to those that have previously formed the basis of DNA circuit computations. Taken together, these results validate an entirely new chemistry for the implementation of nucleic acid circuits. PMID:24493736

Millimeter-wave and optoelectronic applications of heterostructure integrated circuits

NASA Technical Reports Server (NTRS)

Pavlidis, Dimitris

1991-01-01

The properties are reviewed of heterostructure devices for microwave-monolithic-integrated circuits (MMICs) and optoelectronic integrated circuits (OICs). Specific devices examined include lattice-matched and pseudomorphic InAlAs/InGaAs high-electron mobility transistors (HEMTs), mixer/multiplier diodes, and heterojunction bipolar transistors (HBTs) developed with a number of materials. MMICs are reviewed that can be employed for amplification, mixing, and signal generation, and receiver/transmitter applications are set forth for OICs based on GaAs and InP heterostructure designs. HEMTs, HBTs, and junction-FETs can be utilized in combination with PIN, MSM, and laser diodes to develop novel communication systems based on technologies that combine microwave and photonic capabilities.

Millimeter-wave and optoelectronic applications of heterostructure integrated circuits

NASA Astrophysics Data System (ADS)

Pavlidis, Dimitris

1991-02-01

The properties are reviewed of heterostructure devices for microwave-monolithic-integrated circuits (MMICs) and optoelectronic integrated circuits (OICs). Specific devices examined include lattice-matched and pseudomorphic InAlAs/InGaAs high-electron mobility transistors (HEMTs), mixer/multiplier diodes, and heterojunction bipolar transistors (HBTs) developed with a number of materials. MMICs are reviewed that can be employed for amplification, mixing, and signal generation, and receiver/transmitter applications are set forth for OICs based on GaAs and InP heterostructure designs. HEMTs, HBTs, and junction-FETs can be utilized in combination with PIN, MSM, and laser diodes to develop novel communication systems based on technologies that combine microwave and photonic capabilities.

Micromachined piezoresistive inclinometer with oscillator-based integrated interface circuit and temperature readout

NASA Astrophysics Data System (ADS)

Dalola, Simone; Ferrari, Vittorio; Marioli, Daniele

2012-03-01

In this paper a dual-chip system for inclination measurement is presented. It consists of a MEMS (microelectromechanical system) piezoresistive accelerometer manufactured in silicon bulk micromachining and a CMOS (complementary metal oxide semiconductor) ASIC (application specific integrated circuit) interface designed for resistive-bridge sensors. The sensor is composed of a seismic mass symmetrically suspended by means of four flexure beams that integrate two piezoresistors each to detect the applied static acceleration, which is related to inclination with respect to the gravity vector. The ASIC interface is based on a relaxation oscillator where the frequency and the duty cycle of a rectangular-wave output signal are related to the fractional bridge imbalance and the overall bridge resistance of the sensor, respectively. The latter is a function of temperature; therefore the sensing element itself can be advantageously used to derive information for its own thermal compensation. DC current excitation of the sensor makes the configuration unaffected by wire resistances and parasitic capacitances. Therefore, a modular system results where the sensor can be placed remotely from the electronics without suffering accuracy degradation. The inclination measurement system has been characterized as a function of the applied inclination angle at different temperatures. At room temperature, the experimental sensitivity of the system results in about 148 Hz/g, which corresponds to an angular sensitivity around zero inclination angle of about 2.58 Hz deg-1. This is in agreement with finite element method simulations. The measured output fluctuations at constant temperature determine an equivalent resolution of about 0.1° at midrange. In the temperature range of 25-65 °C the system sensitivity decreases by about 10%, which is less than the variation due to the microsensor alone thanks to thermal compensation provided by the current excitation of the bridge and the positive

α-Dendrotoxin inhibits the ASIC current in dorsal root ganglion neurons from rat.

PubMed

Báez, Adriana; Salceda, Emilio; Fló, Martín; Graña, Martín; Fernández, Cecilia; Vega, Rosario; Soto, Enrique

2015-10-08

Dendrotoxins are a group of peptide toxins purified from the venom of several mamba snakes. α-Dendrotoxin (α-DTx, from the Eastern green mamba Dendroaspis angusticeps) is a well-known blocker of voltage-gated K(+) channels and specifically of K(v)1.1, K(v)1.2 and K(v)1.6. In this work we show that α-DTx inhibited the ASIC currents in DRG neurons (IC50=0.8 μM) when continuously perfused during 25 s (including a 5 s pulse to pH 6.1), but not when co-applied with the pH drop. Additionally, we show that α-DTx abolished a transient component of the outward current that, in some experiments, appeared immediately after the end of the acid pulse. Our data indicate that α-DTx inhibits ASICs in the high nM range while some Kv are inhibited in the low nM range. The α-DTx selectivity and its potential interaction with ASICs should be taken in consideration when DTx is used in the high nM range. Copyright © 2015 Elsevier Ireland Ltd. All rights reserved.

PAR-2 activation enhances weak acid-induced ATP release through TRPV1 and ASIC sensitization in human esophageal epithelial cells.

PubMed

Wu, Liping; Oshima, Tadayuki; Shan, Jing; Sei, Hiroo; Tomita, Toshihiko; Ohda, Yoshio; Fukui, Hirokazu; Watari, Jiro; Miwa, Hiroto

2015-10-15

Esophageal visceral hypersensitivity has been proposed to be the pathogenesis of heartburn sensation in nonerosive reflux disease. Protease-activated receptor-2 (PAR-2) is expressed in human esophageal epithelial cells and is believed to play a role in inflammation and sensation. PAR-2 activation may modulate these responses through adenosine triphosphate (ATP) release, which is involved in transduction of sensation and pain. The transient receptor potential vanilloid receptor 1 (TRPV1) and acid-sensing ion channels (ASICs) are both acid-sensitive nociceptors. However, the interaction among these molecules and the mechanisms of heartburn sensation are still not clear. We therefore examined whether ATP release in human esophageal epithelial cells in response to acid is modulated by TRPV1 and ASICs and whether PAR-2 activation influences the sensitivity of TRPV1 and ASICs. Weak acid (pH 5) stimulated the release of ATP from primary human esophageal epithelial cells (HEECs). This effect was significantly reduced after pretreatment with 5-iodoresiniferatoxin (IRTX), a TRPV1-specific antagonist, or with amiloride, a nonselective ASIC blocker. TRPV1 and ASIC3 small interfering RNA (siRNA) transfection also decreased weak acid-induced ATP release. Pretreatment of HEECs with trypsin, tryptase, or a PAR-2 agonist enhanced weak acid-induced ATP release. Trypsin treatment led to the phosphorylation of TRPV1. Acid-induced ATP release enhancement by trypsin was partially blocked by IRTX, amiloride, or a PAR-2 antagonist. Conversely, acid-induced ATP release was augmented by PAR-2 activation through TRPV1 and ASICs. These findings suggested that the pathophysiology of heartburn sensation or esophageal hypersensitivity may be associated with the activation of PAR-2, TRPV1, and ASICs. Copyright © 2015 the American Physiological Society.

Hardware and software status of QCDOC

NASA Astrophysics Data System (ADS)

Boyle, P. A.; Chen, D.; Christ, N. H.; Clark, M.; Cohen, S. D.; Cristian, C.; Dong, Z.; Gara, A.; Joó, B.; Jung, C.; Kim, C.; Levkova, L.; Liao, X.; Liu, G.; Mawhinney, R. D.; Ohta, S.; Petrov, K.; Wettig, T.; Yamaguchi, A.

2004-03-01

QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation.

Development of 4-Sides Buttable CdTe-ASIC Hybrid Module for X-ray Flat Panel Detector

NASA Astrophysics Data System (ADS)

Tamaki, Mitsuru; Mito, Yoshio; Shuto, Yasuhiro; Kiyuna, Tatsuya; Yamamoto, Masaya; Sagae, Kenichi; Kina, Tooru; Koizumi, Tatsuhiro; Ohno, Ryoichi

2009-08-01

A 4-sides buttable CdTe-ASIC hybrid module suitable for use in an X-ray flat panel detector (FPD) has been developed by applying through silicon via (TSV) technology to the readout ASIC. The ASIC has 128 times 256 channels of charge integration type readout circuitry and an area of 12.9 mm times 25.7 mm. The CdTe sensor of 1 mm thickness, having the same area and pixel of 100 mum pitch, was fabricated from the Cl-doped CdTe single crystal grown by traveling heater method (THM). Then the CdTe pixel sensor was hybridized with the ASIC using the bump-bonding technology. The basic performance of this 4-sides buttable module was evaluated by taking X-ray images, and it was compared with that of a commercially available indirect type CsI(Tl) FPD. A prototype CdTe FPD was made by assembling 9 pieces of the 4-sides buttable modules into 3 times 3 arrays in which the neighboring modules were mounted on the interface board. The FPD covers an active area of 77 mm times 39 mm. The results showed the great potential of this 4-sides buttable module for the new real time X-ray FPD with high spatial resolution.

Readout ASICs and Electronics for the 144-channel HAPDs for the Aerogel RICH at Belle II

NASA Astrophysics Data System (ADS)

Nishida, S.; Adachi, I.; Ikeda, H.; Hara, K.; Iijima, T.; Iwata, S.; Korpar, S.; Križan, P.; Kuroda, E.; Pestotnik, R.; Seljak, A.; Sumiyoshi, T.; Takagaki, H.

The particle identification (PID) device in the endcap of the Belle detector will be upgraded to a ring imaging Cherenkov counter (RICH) using aerogel as a radiator at the Belle II experiment. We develop the electronics to read out the 70,000 channels of hit information from the 144-channel hybrid avalanche photodetectors (HAPD), of the aerogel RICH detector. A readout ASIC is developed to digitize the HAPD signals, and was used in a beam test with the prototype detector. The performance and plan of the ASIC is reported in this study. We have also designed the readout electronics for the aerogel RICH, which consist of front-end boards with the ASICs merger boards to collect data from the front-end boards. A front-end board that fits in the actual available space for the aerogel RICH electronics was produced.

Chemical synthesis, 3D structure, and ASIC binding site of the toxin mambalgin-2.

PubMed

Schroeder, Christina I; Rash, Lachlan D; Vila-Farrés, Xavier; Rosengren, K Johan; Mobli, Mehdi; King, Glenn F; Alewood, Paul F; Craik, David J; Durek, Thomas

2014-01-20

Mambalgins are a novel class of snake venom components that exert potent analgesic effects mediated through the inhibition of acid-sensing ion channels (ASICs). The 57-residue polypeptide mambalgin-2 (Ma-2) was synthesized by using a combination of solid-phase peptide synthesis and native chemical ligation. The structure of the synthetic toxin, determined using homonuclear NMR, revealed an unusual three-finger toxin fold reminiscent of functionally unrelated snake toxins. Electrophysiological analysis of Ma-2 on wild-type and mutant ASIC1a receptors allowed us to identify α-helix 5, which borders on the functionally critical acidic pocket of the channel, as a major part of the Ma-2 binding site. This region is also crucial for the interaction of ASIC1a with the spider toxin PcTx1, thus suggesting that the binding sites for these toxins substantially overlap. This work lays the foundation for structure-activity relationship (SAR) studies and further development of this promising analgesic peptide. Copyright © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Test systems of the STS-XYTER2 ASIC: from wafer-level to in-system verification

NASA Astrophysics Data System (ADS)

Kasinski, Krzysztof; Zubrzycka, Weronika

2016-09-01

The STS/MUCH-XYTER2 ASIC is a full-size prototype chip for the Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the new fixed-target experiment Compressed Baryonic Matter (CBM) at FAIR-center, Darmstadt, Germany. The STS assembly includes more than 14000 ASICs. The complicated, time-consuming, multi-step assembly process of the detector building blocks and tight quality assurance requirements impose several intermediate testing to be performed for verifying crucial assembly steps (e.g. custom microcable tab-bonding before wire-bonding to the PCB) and - if necessary - identifying channels or modules for rework. The chip supports the multi-level testing with different probing / contact methods (wafer probe-card, pogo-probes, in-system tests). A huge number of ASICs to be tested restricts the number and kind of tests possible to be performed within a reasonable time. The proposed architectures of test stand equipment and a brief summary of methodologies are presented in this paper.

Highly-Integrated CMOS Interface Circuits for SiPM-Based PET Imaging Systems.

PubMed

Dey, Samrat; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

2012-01-01

Recent developments in the area of Positron Emission Tomography (PET) detectors using Silicon Photomultipliers (SiPMs) have demonstrated the feasibility of higher resolution PET scanners due to a significant reduction in the detector form factor. The increased detector density requires a proportionally larger number of channels to interface the SiPM array with the backend digital signal processing necessary for eventual image reconstruction. This work presents a CMOS ASIC design for signal reducing readout electronics in support of an 8×8 silicon photomultiplier array. The row/column/diagonal summation circuit significantly reduces the number of required channels, reducing the cost of subsequent digitizing electronics. Current amplifiers are used with a single input from each SiPM cathode. This approach helps to reduce the detector loading, while generating all the necessary row, column and diagonal addressing information. In addition, the single current amplifier used in our Pulse-Positioning architecture facilitates the extraction of pulse timing information. Other components under design at present include a current-mode comparator which enables threshold detection for dark noise current reduction, a transimpedance amplifier and a variable output impedance I/O driver which adapts to a wide range of loading conditions between the ASIC and lines with the off-chip Analog-to-Digital Converters (ADCs).

Highly-Integrated CMOS Interface Circuits for SiPM-Based PET Imaging Systems

PubMed Central

Dey, Samrat; Lewellen, Thomas K.; Miyaoka, Robert S.; Rudell, Jacques C.

2013-01-01

Recent developments in the area of Positron Emission Tomography (PET) detectors using Silicon Photomultipliers (SiPMs) have demonstrated the feasibility of higher resolution PET scanners due to a significant reduction in the detector form factor. The increased detector density requires a proportionally larger number of channels to interface the SiPM array with the backend digital signal processing necessary for eventual image reconstruction. This work presents a CMOS ASIC design for signal reducing readout electronics in support of an 8×8 silicon photomultiplier array. The row/column/diagonal summation circuit significantly reduces the number of required channels, reducing the cost of subsequent digitizing electronics. Current amplifiers are used with a single input from each SiPM cathode. This approach helps to reduce the detector loading, while generating all the necessary row, column and diagonal addressing information. In addition, the single current amplifier used in our Pulse-Positioning architecture facilitates the extraction of pulse timing information. Other components under design at present include a current-mode comparator which enables threshold detection for dark noise current reduction, a transimpedance amplifier and a variable output impedance I/O driver which adapts to a wide range of loading conditions between the ASIC and lines with the off-chip Analog-to-Digital Converters (ADCs). PMID:24301987

An ASIC memory buffer controller for a high speed disk system

NASA Technical Reports Server (NTRS)

Hodson, Robert F.; Campbell, Steve

1993-01-01

The need for large capacity, high speed mass memory storage devices has become increasingly evident at NASA during the past decade. High performance mass storage systems are crucial to present and future NASA systems. Spaceborne data storage system requirements have grown in response to the increasing amounts of data generated and processed by orbiting scientific experiments. Predictions indicate increases in the volume of data by orders of magnitude during the next decade. Current predictions are for storage capacities on the order of terabits (Tb), with data rates exceeding one gigabit per second (Gbps). As part of the design effort for a state of the art mass storage system, NASA Langley has designed a 144 CMOS ASIC to support high speed data transfers. This paper discusses the system architecture, ASIC design and some of the lessons learned in the development process.

Application-specific coarse-grained reconfigurable array: architecture and design methodology

NASA Astrophysics Data System (ADS)

Zhou, Li; Liu, Dongpei; Zhang, Jianfeng; Liu, Hengzhu

2015-06-01

Coarse-grained reconfigurable arrays (CGRAs) have shown potential for application in embedded systems in recent years. Numerous reconfigurable processing elements (PEs) in CGRAs provide flexibility while maintaining high performance by exploring different levels of parallelism. However, a difference remains between the CGRA and the application-specific integrated circuit (ASIC). Some application domains, such as software-defined radios (SDRs), require flexibility with performance demand increases. More effective CGRA architectures are expected to be developed. Customisation of a CGRA according to its application can improve performance and efficiency. This study proposes an application-specific CGRA architecture template composed of generic PEs (GPEs) and special PEs (SPEs). The hardware of the SPE can be customised to accelerate specific computational patterns. An automatic design methodology that includes pattern identification and application-specific function unit generation is also presented. A mapping algorithm based on ant colony optimisation is provided. Experimental results on the SDR target domain show that compared with other ordinary and application-specific reconfigurable architectures, the CGRA generated by the proposed method performs more efficiently for given applications.

An Analysis of Heavy-Ion Single Event Effects for a Variety of Finite State-Machine Mitigation Strategies

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; Label, Kenneth A.; Kim, Hak; Phan, Anthony; Seidleck, Christina

2014-01-01

Finite state-machines (FSMs) are used to control operational flow in application specific integrated circuits (ASICs) and field programmable gate array (FPGA) devices. Because of their ease of interpretation, FSMs simplify the design and verification process and consequently are significant components in a synchronous design.

Micro-miniature radio frequency transmitter for communication and tracking applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Crutcher, R.I.; Emery, M.S.; Falter, K.G.

1996-12-31

A micro-miniature radio frequency (rf) transmitter has been developed and demonstrated by the Oak Ridge National Laboratory. The objective of the rf transmitter development was to maximize the transmission distance while drastically shrinking the overall transmitter size, including antenna. Based on analysis and testing, an application-specific integrated circuit (ASIC) with a 16-GHz gallium arsenide (GaAs) oscillator and integrated on-chip antenna was designed and fabricated using microwave monolithic integrated circuit (MMIC) technology. Details of the development and the results of various field tests will be discussed. The rf transmitter is applicable to covert surveillance and tracking scenarios due to its smallmore » size of 2.2 x 2.2 mm, including the antenna. Additionally, the 16-GHz frequency is well above the operational range of consumer-grade radio scanners, providing a degree of protection from unauthorized interception. Variations of the transmitter design have been demonstrated for tracking and tagging beacons, transmission of digital data, and transmission of real-time analog video from a surveillance camera. Preliminary laboratory measurements indicate adaptability to direct-sequence spread-spectrum transmission, providing a low probability of intercept and/or detection. Concepts related to law enforcement applications will be presented.« less

Thermocouple-Signal-Conditioning Circuit

NASA Technical Reports Server (NTRS)

Simon, Richard A.

1991-01-01

Thermocouple-signal-conditioning circuit acting in conjunction with thermocouple, exhibits electrical behavior of voltage in series with resistance. Combination part of input bridge circuit of controller. Circuit configured for either of two specific applications by selection of alternative resistances and supply voltages. Includes alarm circuit detecting open circuit in thermocouple and provides off-scale output to signal malfunctions.

Low power signal processing electronics for wearable medical devices.

PubMed

Casson, Alexander J; Rodriguez-Villegas, Esther

2010-01-01

Custom designed microchips, known as Application Specific Integrated Circuits (ASICs), offer the lowest possible power consumption electronics. However, this comes at the cost of a longer, more complex and more costly design process compared to one using generic, off-the-shelf components. Nevertheless, their use is essential in future truly wearable medical devices that must operate for long periods of time from physically small, energy limited batteries. This presentation will demonstrate the state-of-the-art in ASIC technology for providing online signal processing for use in these wearable medical devices.

JPRS Report: Science & Technology - Europe.

DTIC Science & Technology

1992-12-21

in the aero- nautical industry—through the use of hybrids, ASICs [application-specific integrated circuits ], etc. "The system will also have an... Module ], the cylinder-shaped pressurized cabin that can be firmly attached to the international space station), which is to be launched in 1999...34] [Excerpt] Two hundred scientists and $1 billion to design the chip of the future, an integrated circuit (IC) giving microcomputers power

Multi-petascale highly efficient parallel supercomputer

DOEpatents

Asaad, Sameh; Bellofatto, Ralph E.; Blocksome, Michael A.; Blumrich, Matthias A.; Boyle, Peter; Brunheroto, Jose R.; Chen, Dong; Cher, Chen -Yong; Chiu, George L.; Christ, Norman; Coteus, Paul W.; Davis, Kristan D.; Dozsa, Gabor J.; Eichenberger, Alexandre E.; Eisley, Noel A.; Ellavsky, Matthew R.; Evans, Kahn C.; Fleischer, Bruce M.; Fox, Thomas W.; Gara, Alan; Giampapa, Mark E.; Gooding, Thomas M.; Gschwind, Michael K.; Gunnels, John A.; Hall, Shawn A.; Haring, Rudolf A.; Heidelberger, Philip; Inglett, Todd A.; Knudson, Brant L.; Kopcsay, Gerard V.; Kumar, Sameer; Mamidala, Amith R.; Marcella, James A.; Megerian, Mark G.; Miller, Douglas R.; Miller, Samuel J.; Muff, Adam J.; Mundy, Michael B.; O'Brien, John K.; O'Brien, Kathryn M.; Ohmacht, Martin; Parker, Jeffrey J.; Poole, Ruth J.; Ratterman, Joseph D.; Salapura, Valentina; Satterfield, David L.; Senger, Robert M.; Smith, Brian; Steinmacher-Burow, Burkhard; Stockdell, William M.; Stunkel, Craig B.; Sugavanam, Krishnan; Sugawara, Yutaka; Takken, Todd E.; Trager, Barry M.; Van Oosten, James L.; Wait, Charles D.; Walkup, Robert E.; Watson, Alfred T.; Wisniewski, Robert W.; Wu, Peng

2015-07-14

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

NASA Technical Reports Server (NTRS)

Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

2014-01-01

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

IMOTEPAD: A mixed-signal 64-channel front-end ASIC for small-animal PET imaging

NASA Astrophysics Data System (ADS)

Fang, Xiaochao; Ollivier-Henry, Nicolas; Gao, Wu; Hu-Guo, Christine; Colledani, Claude; Humbert, Bernard; Brasse, David; Hu, Yann

2011-04-01

This paper presents the design and characteristics of a mixed-signal 64-channel front-end readout ASIC called IMOTEPAD dedicated to multi-channel plate (MCP) photodetector coupled to LYSO scintillating crystals for small-animal PET imaging. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. As a result, both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. This dedicated ASIC IMOTEPAD comprises two parts: the analog part IMOTEPA and the digital part IMOTEPD. The IMOTEPA is dedicated to energy measurement. And the timing information is digitized by the IMOTEPD in which the key principal element is a time-to-digital converter (TDC) based on a delay-locked loop (DLL) with 32 delay cells. The chip is designed and fabricated in 0.35 μm CMOS process. The measurements show that for the analog part IMOTEPA, the energy gain is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The SNR is 39 dB and the RMS noise is 300 μV. The nonlinearity is less than 3%. The crosstalk is less than 0.2%. For the IMOTEPD, the bin size of the TDC is 625 ps with a reference clock of 50 MHz. The RMS jitter of the DLL is less than 42 ps. The DNL of the TDC is equal to about 0.17 LSB and the INL is equal to 0.31 LSB. The power dissipation of each channel is less than 16.8 mW. The design of the ASIC, especially for TDC and the measurement results of the IMOTEPAD will be presented and discussed in this paper.

Methods of fabricating applique circuits

DOEpatents

Dimos, Duane B.; Garino, Terry J.

1999-09-14

Applique circuits suitable for advanced packaging applications are introduced. These structures are particularly suited for the simple integration of large amounts (many nanoFarads) of capacitance into conventional integrated circuit and multichip packaging technology. In operation, applique circuits are bonded to the integrated circuit or other appropriate structure at the point where the capacitance is required, thereby minimizing the effects of parasitic coupling. An immediate application is to problems of noise reduction and control in modern high-frequency circuitry.

Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

NASA Astrophysics Data System (ADS)

Lee, M. J.; Brown, D. N.; Chang, J. K.; Ding, D.; Gnani, D.; Grace, C. R.; Jones, J. A.; Kolomensky, Y. G.; von der Lippe, H.; Mcvittie, P. J.; Stettler, M. W.; Walder, J.-P.

2015-06-01

We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Carlson, Thomas J.; Myjak, Mitchell J.

At the request of the U.S. Army Corps of Engineers, Portland District, researchers from Pacific Northwest National Laboratory investigated the use of an application-specific integrated circuit (ASIC) to reduce the weight and volume of Juvenile Salmon Acoustic Telemetry System (JSATS) transmitters while retaining current functionality. Review of the design of current JSATS transmitters identified components that could be replaced by an ASIC while retaining the function of the current transmitter and offering opportunities to extend function if desired. ASIC design alternatives were identified that could meet transmitter weight and volume targets of 200 mg and 100 mm3. If alternatives tomore » the cylindrical batteries used in current JSATS transmitters can be identified, it could be possible to implant ASIC-based JSATS transmitters by injection rather than surgery. Using criteria for the size of fish suitable for surgical implantation of current JSATS transmitters, it was concluded that fish as small as 70 mm in length could be implanted with an ASIC-based transmitter, particularly if implantation by injection became feasible.« less

RF-DC converter for HF RFID sensing applications powered by a near-field loop antenna

NASA Astrophysics Data System (ADS)

Colella, R.; Pasca, M.; Catarinucci, L.; Tarricone, L.; D'Amico, S.

2016-07-01

In this paper, an RF-DC converter operating at 13.56 MHz (HF radio frequency identification (RFID) frequency band) is presented. Its architecture provides RF to load isolation, reducing the losses due to the reverse saturation current and improving the sensitivity. Fed by a loop antenna, the RF-DC converter is made by a Dickson's RF-DC rectifier and an additional Pelliconi's charge pump driven by a fully integrated 50 kHz ring oscillator realized using an application-specific integrated circuit (ASIC). The input RF signal from the reader is converted to DC supply voltage and stored on a 1 μF capacitor. Mathematical model of the converter is developed and verified through measurements. Silicon prototypes of the ASIC have been realized in 350 nm complementary metal-oxide semiconductor technology. Measurements have been done on 10 different samples showing an output voltage in the range of 0.5 V-3.11 V in correspondence of an RF input signal power in the range of -19 dBm-0 dBm. These output voltage levels are suitable to power HF RFID sensing platforms and sensor nodes of body sensor networks.

Printed stretchable circuit on soft elastic substrate for wearable application

NASA Astrophysics Data System (ADS)

Yuan, Wei; Wu, Xinzhou; Gu, Weibing; Lin, Jian; Cui, Zheng

2018-01-01

In this paper, a flexible and stretchable circuit has been fabricated by the printing method based on Ag NWs/PDMS composite. The randomly oriented Ag NWs were buried in PDMS to form a conductive and stretchable electrode. Stable conductivity was achieved with a large range of tensile strain (0-50%) after the initial stretching/releasing cycle. The stable electrical response is due to the buckling of the Ag NWs/PDMS composite layer. Furthermore, printed stretchable circuits integrated with commercial ICs have been demonstrated for wearable applications. Project supported by the National Program on Key Basic Research Project (No. 2015CB351901), the Strategic Priority Research Program of the Chinese Academy of Sciences (No. XDA09020201), and the National Science Foundation of China (Nos. 51603227, 51603228).

Neural CMOS-integrated circuit and its application to data classification.

PubMed

Göknar, Izzet Cem; Yildiz, Merih; Minaei, Shahram; Deniz, Engin

2012-05-01

Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

Design and Application of a Circuit for Measuring Frequency and Duty Cycle of Stimulated Bioelectrical Signal

NASA Astrophysics Data System (ADS)

Tang, Li-Ming; Chang, Ben-Kang; Liu, Tie-Bing; Wu, Min; Ling, Gang

2002-12-01

To design a new type of circuit for measuring frequency & duty cycle of stimulated bioelectrical signal for the project of 'the map of neuron-threshold in human brain and its clinical application'. This circuit was designed according to the character of stimulated bioelectrical signals. It was tested and improved and then used in the neuron -threshold stimulator. The circuit was found to be very accurate for measuring frequency and the error for measuring duty cycle was below 0.2%. This circuit is well-designed, simple, easy to use, and can be applied in many systems.

Large Scale Integrated Circuits for Military Applications.

DTIC Science & Technology

1977-05-01

economic incentive for riarrowing this gap is examined, y (U)^wo"categories of cost are analyzed: the direct life cycle cost of the integrated circuit...dependence of these costs on the physical charac- teristics of the integrated circuits is discussed. (U) The economic and physical characteristics of... economic incentive for narrowing this gap is examined. Two categories of cost are analyzed: the direct life cycle cost of the integrated circuit

An integrated signal conditioner for high-frequency inductive position sensors

NASA Astrophysics Data System (ADS)

Rahal, Mohamad; Demosthenous, Andreas

2010-01-01

This paper describes the design, implementation and evaluation of a signal conditioner application-specific integrated circuit (ASIC) for high-frequency inductive non-contact position sensors. These sensors employ a radio frequency technology based on an antenna planar arrangement and a resonant target, have a high inherent resolution (0.1% of antenna length) and can measure target position over a wide distance range (<0.1 mm to >10 m). However, due to the relatively high-frequency excitation (1 MHz typically) and to the specific layouts of these sensors, there is unwanted capacitive coupling between the transmitter and receiver coils; this type of distortion reduces linearity and resolution. The ASIC, which is the first generation of its kind for this type of sensor, employs a differential mixer topology which suppresses the capacitive coupling offsets. The system architecture and circuit details are presented. The ASIC was fabricated in a 0.6 µm high-voltage CMOS technology occupying an area of 8 mm2. It dissipates about 30 mA from a 24 V power supply. The ASIC was tested with a high-frequency inductive position sensor (with an antenna length of 10.8 cm). The measured input-referred offset due to transmitter crosstalk is on average about 22 µV over a wide phase difference variation (-99° to +117°) between the transmitter and demodulating signals.

Performance of CATIROC: ASIC for smart readout of large photomultiplier arrays

NASA Astrophysics Data System (ADS)

Blin, S.; Callier, S.; Conforti Di Lorenzo, S.; Dulucq, F.; De La Taille, C.; Martin-Chassard, G.; Seguin-Moreau, N.

2017-03-01

CATIROC (Charge And Time Integrated Read Out Chip) is a complete read-out chip manufactured in AustriaMicroSystem (AMS) SiGe 0.35 μm technology, designed to read arrays of 16 photomultipliers (PMTs). It is an upgraded version of PARISROC2 [1] designed in 2010 in the context of the PMm2 (square meter PhotoMultiplier) project [2]. CATIROC is a SoC (System on Chip) that processes analog signals up to the digitization and sparsification to reduce the cost and cable number. The ASIC is composed of 16 independent channels that work in triggerless mode, auto-triggering on the single photo-electron. It provides a charge measurement up to 400 photoelectrons (70 pC) on two scales of 10 bits and a timing information with an accuracy of 200 ps rms. The ASIC was sent for fabrication in February 2015 and then received in September 2015. It is a good candidate for two Chinese projects (LHAASO and JUNO). The architecture and the measurements will be detailed in the paper.

Single Event Effects Test Results for Advanced Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory R.; Swift, Gary M.

2006-01-01

Reconfigurable Field Programmable Gate Arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turnApplication Specific Integrated Circuit (ASIC) from Altera were subjected to single-event testing using heavy ions. Both Altera devices (Stratix II and HardCopy II) exhibited a low latchup threshold (below an LET of 3 MeV-cm2/mg) and thus are not recommended for applications in the space radiation environment. The flash-based Actel ProASIC Plus device did not exhibit latchup to an effective LET of 75 MeV-cm2/mg at room temperature. In addition, these tests did not show flash cell charge loss (upset) or retention damage. Upset characterization of the design-level flip-flops yielded an LET threshold below 10 MeV-cm2/mg and a high LET cross section of about lxlO-6 cm2/bit for storing ones and about lxl0-7 cm2/bit for storing zeros . Thus, the ProASIC device may be suitable for critical flight applications with appropriate triple modular redundancy mitigation techniques.

40 CFR 413.80 - Applicability: Description of the printed circuit board subcategory.

Code of Federal Regulations, 2010 CFR

2010-07-01

... 40 Protection of Environment 28 2010-07-01 2010-07-01 true Applicability: Description of the printed circuit board subcategory. 413.80 Section 413.80 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) EFFLUENT GUIDELINES AND STANDARDS ELECTROPLATING POINT SOURCE CATEGORY Printed...

Integral Battery Power Limiting Circuit for Intrinsically Safe Applications

NASA Technical Reports Server (NTRS)

Burns, Bradley M.; Blalock, Norman N.

2010-01-01

A circuit topology has been designed to guarantee the output of intrinsically safe power for the operation of electrical devices in a hazardous environment. This design uses a MOSFET (metal oxide semiconductor field-effect transistor) as a switch to connect and disconnect power to a load. A test current is provided through a separate path to the load for monitoring by a comparator against a preset threshold level. The circuit is configured so that the test current will detect a fault in the load and open the switch before the main current can respond. The main current passes through the switch and then an inductor. When a fault occurs in the load, the current through the inductor cannot change immediately, but the voltage drops immediately to safe levels. The comparator detects this drop and opens the switch before the current in the inductor has a chance to respond. This circuit protects both the current and voltage from exceeding safe levels. Typically, this type of protection is accomplished by a fuse or a circuit breaker, but in order for a fuse or a circuit breaker to blow or trip, the current must exceed the safe levels momentarily, which may be just enough time to ignite anything in a hazardous environment. To prevent this from happening, a fuse is typically current-limited by the addition of the resistor to keep the current within safe levels while the fuse reacts. The use of a resistor is acceptable for non-battery applications where the wasted energy and voltage drop across the resistor can be tolerated. The use of the switch and inductor minimizes the wasted energy. For example, a circuit runs from a 3.6-V battery that must be current-limited to 200 mA. If the circuit normally draws 10 mA, then an 18-ohm resistor would drop 180 mV during normal operation, while a typical switch (0.02 ohm) and inductor (0.97 ohm) would only drop 9.9 mV. From a power standpoint, the current-limiting resistor protection circuit wastes about 18 times more power than the

Dedicated multichannel readout ASIC coupled with single crystal diamond for dosimeter application

NASA Astrophysics Data System (ADS)

Fabbri, A.; Falco, M. D.; De Notaristefani, F.; Galasso, M.; Marinelli, M.; Orsolini Cencelli, V.; Tortora, L.; Verona, C.; Verona Rinati, G.

2013-02-01

This paper reports on the tests of a low-noise, multi-channel readout integrated circuit used as a readout electronic front-end for a diamond multi-pixel dosimeter. The system is developed for dose distribution measurement in radiotherapy applications. The first 10-channel prototype chip was designed and fabricated in a 0.18 um CMOS process. Every channel includes a charge integrator with a 10 pF capacitor and a double slope A/D converter. The diamond multi-pixel detector, based on CVD synthetic single crystal diamond Schottky diodes, is made by a 3 × 3 sensor matrix. The overall device has been tested under irradiation with 6 MeV radio therapeutic photon beams at the Policlinico ``Tor Vergata'' (PTV) hospital. Measurements show a 20 fA RMS leakage current from the front-end input stage and a negligible dark current from the diamond detector, a stable temporal response and a good linear behaviour as a function of both dose and dose rate. These characteristics were common to each tested channel.

Design of a Multi-Channel Low-Noise Readout ASIC for CdZnTe-Based X-Ray and γ-Ray Spectrum Analyzer

NASA Astrophysics Data System (ADS)

Gan, B.; Wei, T.; Gao, W.; Zheng, R.; Hu, Y.

2015-10-01

In this paper, we report on the recent development of a 32-channel low-noise front-end readout ASIC for cadmium zinc telluride (CdZnTe) X-ray and γ-ray detectors. Each readout channel includes a charge sensitive amplifier, a CR-RC shaping amplifier and an analog output buffer. The readout ASIC is implemented using TSMC 0.35 - μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 mm ×4.8 mm. At room temperature, the equivalent noise level of a typical channel reaches 133 e- (rms) with the input parasitic capacitance of 0 pF for the average power consumption of 2.8 mW per channel. The linearity error is less than ±2% and the input energy dynamic range of the readout ASIC is from 10 keV to 1 MeV. The crosstalk between the channels is less than 0.4%. By connecting the readout ASIC to a CdZnTe detector, we obtained a γ-ray spectrum, the energy resolution is 1.8% at the 662-keV line of 137Cs source.

GATING CIRCUITS

DOEpatents

Merrill, L.C.

1958-10-14

Control circuits for vacuum tubes are described, and a binary counter having an improved trigger circuit is reported. The salient feature of the binary counter is the application of the input signal to the cathode of each of two vacuum tubes through separate capacitors and the connection of each cathode to ground through separate diodes. The control of the binary counter is achieved in this manner without special pulse shaping of the input signal. A further advantage of the circuit is the simplicity and minimum nuruber of components required, making its use particularly desirable in computer machines.

Flexible Circuits

NASA Technical Reports Server (NTRS)

1986-01-01

Adflex Solutions, Inc.'s flexible circuits may be molded to the shape of a chassis for bulk reduction. Particularly valuable when circuitry must be moved. They are produced by combining a plastic film, a metallic conductor and an adhesive. One adhesive, LARC-TPI, developed by the Langley Research Center, is a thermoplastic polyimide resin used to produce laminates by Rogers Corporation. It can be processed at a lower temperature, has good moisture resistance and excellent adherence. It is used to bond film to copper foil conductor materials in flexible circuits. The circuits have both aerospace and commercial applications.

Electronic circuits for communications systems: A compilation

NASA Technical Reports Server (NTRS)

1972-01-01

The compilation of electronic circuits for communications systems is divided into thirteen basic categories, each representing an area of circuit design and application. The compilation items are moderately complex and, as such, would appeal to the applications engineer. However, the rationale for the selection criteria was tailored so that the circuits would reflect fundamental design principles and applications, with an additional requirement for simplicity whenever possible.

DOE Office of Scientific and Technical Information (OSTI.GOV)

De Geronimo, G.; Fried, J.; Rehak, P.

We present an application-specific integrated circuit (ASIC) for high-resolution x-ray spectrometers (XRS). The ASIC reads out signals from pixelated silicon drift detectors (SDDs). The pixel does not have an integrated field effect transistor (FET); rather, readout is accomplished by wire-bonding the anodes to the inputs of the ASIC. The ASIC dissipates 32 mW, and offers 16 channels of low-noise charge amplification, high-order shaping with baseline stabilization, discrimination, a novel pile-up rejector, and peak detection with an analog memory. The readout is sparse and based on custom low-power tristatable low-voltage differential signaling (LPT-LVDS). A unit of 64 SDD pixels, read outmore » by four ASICs, covers an area of 12.8 cm{sup 2} and dissipates with the sensor biased about 15 mW/cm{sup 2}. As a tile-based system, the 64-pixel units cover a large detection area. Our preliminary measurements at -44 C show a FWHM of 145 eV at the 5.9 keV peak of a {sup 55}Fe source, and less than 80 eV on a test-pulse line at 200 eV.« less

Spacecraft optical disk recorder memory buffer control

NASA Technical Reports Server (NTRS)

Hodson, Robert F.

1993-01-01

This paper discusses the research completed under the NASA-ASEE summer faculty fellowship program. The project involves development of an Application Specific Integrated Circuit (ASIC) to be used as a Memory Buffer Controller (MBC) in the Spacecraft Optical Disk System (SODR). The SODR system has demanding capacity and data rate specifications requiring specialized electronics to meet processing demands. The system is being designed to support Gigabit transfer rates with Terabit storage capability. The complete SODR system is designed to exceed the capability of all existing mass storage systems today. The ASIC development for SODR consist of developing a 144 pin CMOS device to perform format conversion and data buffering. The final simulations of the MBC were completed during this summer's NASA-ASEE fellowship along with design preparations for fabrication to be performed by an ASIC manufacturer.

Heterostructure-based high-speed/high-frequency electronic circuit applications

NASA Astrophysics Data System (ADS)

Zampardi, P. J.; Runge, K.; Pierson, R. L.; Higgins, J. A.; Yu, R.; McDermott, B. T.; Pan, N.

1999-08-01

With the growth of wireless and lightwave technologies, heterostructure electronic devices are commodity items in the commercial marketplace [Browne J. Power-amplifier MMICs drive commercial circuits. Microwaves & RF, 1998. p. 116-24.]. In particular, HBTs are an attractive device for handset power amplifiers at 900 MHz and 1.9 GHz for CDMA applications [Lum E. GaAs technology rides the wireless wave. Proceedings of the 1997 GaAs IC Symposium, 1997. p. 11-13; "Rockwell Ramps Up". Compound Semiconductor, May/June 1997.]. At higher frequencies, both HBTs and p-HEMTs are expected to dominate the marketplace. For high-speed lightwave circuit applications, heterostructure based products on the market for OC-48 (2.5 Gb/s) and OC-192 (10 Gb/s) are emerging [http://www.nb.rockwell.com/platforms/network_access/nahome.html#5.; http://www.nortel.com/technology/opto/receivers/ptav2.html.]. Chips that operate at 40 Gb/ have been demonstrated in a number of research laboratories [Zampardi PJ, Pierson RL, Runge K, Yu R, Beccue SM, Yu J, Wang KC. hybrid digital/microwave HBTs for >30 Gb/s optical communications. IEDM Technical Digest, 1995. p. 803-6; Swahn T, Lewin T, Mokhtari M, Tenhunen H, Walden R, Stanchina W. 40 Gb/s 3 Volt InP HBT ICs for a fiber optic demonstrator system. Proceedings of the 1996 GaAs IC Symposium, 1996. p. 125-8; Suzuki H, Watanabe K, Ishikawa K, Masuda H, Ouchi K, Tanoue T, Takeyari R. InP/InGaAs HBT ICs for 40 Gbit/s optical transmission systems. Proceedings of the 1997 GaAs IC Symposium, 1997. p. 215-8]. In addition to these two markets, another area where heterostructure devices are having significant impact is for data conversion [Walden RH. Analog-to digital convertor technology comparison. Proceedings of the 1994 GaAs IC Symposium, 1994. p. 217-9; Poulton K, Knudsen K, Corcoran J, Wang KC, Nubling RB, Chang M-CF, Asbeck PM, Huang RT. A 6-b, 4 GSa/s GaAs HBT ADC. IEEE J Solid-State Circuits 1995;30:1109-18; Nary K, Nubling R, Beccue S, Colleran W

Superconducting quantum circuits theory and application

NASA Astrophysics Data System (ADS)

Deng, Xiuhao

Superconducting quantum circuit models are widely used to understand superconducting devices. This thesis consists of four studies wherein the superconducting quantum circuit is used to illustrate challenges related to quantum information encoding and processing, quantum simulation, quantum signal detection and amplification. The existence of scalar Aharanov-Bohm phase has been a controversial topic for decades. Scalar AB phase, defined as time integral of electric potential, gives rises to an extra phase factor in wavefunction. We proposed a superconducting quantum Faraday cage to detect temporal interference effect as a consequence of scalar AB phase. Using the superconducting quantum circuit model, the physical system is solved and resulting AB effect is predicted. Further discussion in this chapter shows that treating the experimental apparatus quantum mechanically, spatial scalar AB effect, proposed by Aharanov-Bohm, can't be observed. Either a decoherent interference apparatus is used to observe spatial scalar AB effect, or a quantum Faraday cage is used to observe temporal scalar AB effect. The second study involves protecting a quantum system from losing coherence, which is crucial to any practical quantum computation scheme. We present a theory to encode any qubit, especially superconducting qubits, into a universal quantum degeneracy point (UQDP) where low frequency noise is suppressed significantly. Numerical simulations for superconducting charge qubit using experimental parameters show that its coherence time is prolong by two orders of magnitude using our universal degeneracy point approach. With this improvement, a set of universal quantum gates can be performed at high fidelity without losing too much quantum coherence. Starting in 2004, the use of circuit QED has enabled the manipulation of superconducting qubits with photons. We applied quantum optical approach to model coupled resonators and obtained a four-wave mixing toolbox to operate photons

Possibilities for mixed mode chip manufacturing in EUROPRACTICE

NASA Astrophysics Data System (ADS)

Das, C.

1997-02-01

EUROPRACTICE is an EC initiative under the ESPRIT programme which aims to stimulate the wider exploitation of state-of-the-art microelectronics technologies by European industry and to enhance European industrial competitiveness in the global market-place. Through EUROPRACTICE, the EC has created a range of Basic Services that offer users a cost-effective and flexible means of accessing three main microelectronics-based technologies: Application Specific Integrated Circuit (ASICs), Multi-Chip Modules (MCMs) and Microsystems. EUROPRACTICE Basic Services reduce the cost and risk for companies wishing to begin using these technologies. EUROPRACTICE offers a fully supported, low cost route for companies to design and fabricate ASICs for their individual applications. Low cost is achieved by consolidating designs from many users onto a single semiconductor wafer (MPW: Multi Project Wafer). The EUROPRACTICE IC Manufacturing Service (ICMS) offers a broad range of fabrication technologies including CMOS, BiCMOS and GaAs. The Service extends from enabling users to produce prototype ASICs for testing and evaluation, through to low-volume production runs.

Protective Socket For Integrated Circuits

NASA Technical Reports Server (NTRS)

Wilkinson, Chris; Henegar, Greg

1988-01-01

Socket for intergrated circuits (IC's) protects from excessive voltages and currents or from application of voltages and currents in wrong sequence during insertion or removal. Contains built-in switch that opens as IC removed, disconnecting leads from signals and power. Also protects other components on circuit board from transients produced by insertion and removal of IC. Makes unnecessary to turn off power to entire circuit board so other circuits on board continue to function.

The test of VLSI circuits

NASA Astrophysics Data System (ADS)

Baviere, Ph.

Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

A Thermally Powered ISFET Array for On-Body pH Measurement.

PubMed

Douthwaite, Matthew; Koutsos, Ermis; Yates, David C; Mitcheson, Paul D; Georgiou, Pantelis

2017-12-01

Recent advances in electronics and electrochemical sensors have led to an emerging class of next generation wearables, detecting analytes in biofluids such as perspiration. Most of these devices utilize ion-selective electrodes (ISEs) as a detection method; however, ion-sensitive field-effect transistors (ISFETs) offer a solution with improved integration and a low power consumption. This work presents a wearable, thermoelectrically powered system composed of an application-specific integrated circuit (ASIC), two commercial power management integrated circuits and a network of commercial thermoelectric generators (TEGs). The ASIC is fabricated in 0.35 m CMOS and contains an ISFET array designed to read pH as a current, a processing module which averages the signal to reduce noise and encodes it into a frequency, and a transmitter. The output frequency has a measured sensitivity of 6 to 8 kHz/pH for a pH range of 7-5. It is shown that the sensing array and processing module has a power consumption 6 W and, therefore, can be entirely powered by body heat using a TEG. Array averaging is shown to reduce noise at these low power levels to 104 V (input referred integrated noise), reducing the minimum detectable limit of the ASIC to 0.008 pH units. The work forms the foundation and proves the feasibility of battery-less, on-body electrochemical for perspiration analysis in sports science and healthcare applications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Heffner, M.; Riot, V.; Fabris, L.

Medium to large channel count detectors are usually faced with a few unattractive options for data acquisition (DAQ). Small to medium sized TPC experiments, for example, can be too small to justify the high expense and long development time of application specific integrated circuit (ASIC) development. In some cases an experiment can piggy-back on a larger experiment and the associated ASIC development, but this puts the time line of development out of the hands of the smaller experiment. Another option is to run perhaps thousands of cables to rack mounted equipment, which is clearly undesirable. The development of commercial high-speedmore » high-density FPGAs and ADCs combined with the small discrete components and robotic assembly open a new option that scales to tens of thousands of channels and is only slightly larger than ASICs using off-the-shelf components.« less

A Compact, Flexible, High Channel Count DAQ Built From Off-the-Shelf Components

DOE PAGES

Heffner, M.; Riot, V.; Fabris, L.

2013-06-01

Medium to large channel count detectors are usually faced with a few unattractive options for data acquisition (DAQ). Small to medium sized TPC experiments, for example, can be too small to justify the high expense and long development time of application specific integrated circuit (ASIC) development. In some cases an experiment can piggy-back on a larger experiment and the associated ASIC development, but this puts the time line of development out of the hands of the smaller experiment. Another option is to run perhaps thousands of cables to rack mounted equipment, which is clearly undesirable. The development of commercial high-speedmore » high-density FPGAs and ADCs combined with the small discrete components and robotic assembly open a new option that scales to tens of thousands of channels and is only slightly larger than ASICs using off-the-shelf components.« less

Protection circuits for very high frequency ultrasound systems.

PubMed

Choi, Hojong; Shung, K Kirk

2014-04-01

The purpose of protection circuits in ultrasound applications is to block noise signals from the transmitter from reaching the transducer and also to prevent unwanted high voltage signals from reaching the receiver. The protection circuit using a resistor and diode pair is widely used due to its simple architecture, however, it may not be suitable for very high frequency (VHF) ultrasound transducer applications (>100 MHz) because of its limited bandwidth. Therefore, a protection circuit using MOSFET devices with unique structure is proposed in this paper. The performance of the designed protection circuit was compared with that of other traditional protection schemes. The performance characteristics measured were the insertion loss (IL), total harmonic distortion (THD) and transient response time (TRT). The new protection scheme offers the lowest IL (-1.0 dB), THD (-69.8 dB) and TRT (78 ns) at 120 MHz. The pulse-echo response using a 120 MHz LiNbO3 transducer with each protection circuit was measured to validate the feasibility of the protection circuits in VHF ultrasound applications. The sensitivity and bandwidth of the transducer using the new protection circuit improved by 252.1 and 50.9 %, respectively with respect to the protection circuit using a resistor and diode pair. These results demonstrated that the new protection circuit design minimizes the IL, THD and TRT for VHF ultrasound transducer applications.

Protection Circuits for Very High Frequency Ultrasound Systems

PubMed Central

Shung, K. Kirk

2014-01-01

The purpose of protection circuits in ultrasound applications is to block noise signals from the transmitter from reaching the transducer and also to prevent unwanted high voltage signals from reaching the receiver. The protection circuit using a resistor and diode pair is widely used due to its simple architecture, however, it may not be suitable for very high frequency (VHF) ultrasound transducer applications (>100 MHz) because of its limited bandwidth. Therefore, a protection circuit using MOSFET devices with unique structure is proposed in this paper. The performance of the designed protection circuit was compared with that of other traditional protection schemes. The performance characteristics measured were the insertion loss (IL), total harmonic distortion (THD) and transient response time (TRT). The new protection scheme offers the lowest IL (−1.0 dB), THD (−69.8 dB) and TRT (78 ns) at 120 MHz. The pulse-echo response using a 120 MHz LiNbO3 transducer with each protection circuit was measured to validate the feasibility of the protection circuits in VHF ultrasound applications. The sensitivity and bandwidth of the transducer using the new protection circuit improved by 252.1 and 50.9 %, respectively with respect to the protection circuit using a resistor and diode pair. These results demonstrated that the new protection circuit design minimizes the IL, THD and TRT for VHF ultrasound transducer applications. PMID:24682684

Circuit-level simulation of transistor lasers and its application to modelling of microwave photonic links

NASA Astrophysics Data System (ADS)

Iezekiel, Stavros; Christou, Andreas

2015-03-01

Equivalent circuit models of a transistor laser are used to investigate the suitability of this relatively new device for analog microwave photonic links. The three-terminal nature of the device enables transistor-based circuit design techniques to be applied to optoelectronic transmitter design. To this end, we investigate the application of balanced microwave amplifier topologies in order to enable low-noise links to be realized with reduced intermodulation distortion and improved RF impedance matching compared to conventional microwave photonic links.

A low power biomedical signal processor ASIC based on hardware software codesign.

PubMed

Nie, Z D; Wang, L; Chen, W G; Zhang, T; Zhang, Y T

2009-01-01

A low power biomedical digital signal processor ASIC based on hardware and software codesign methodology was presented in this paper. The codesign methodology was used to achieve higher system performance and design flexibility. The hardware implementation included a low power 32bit RISC CPU ARM7TDMI, a low power AHB-compatible bus, and a scalable digital co-processor that was optimized for low power Fast Fourier Transform (FFT) calculations. The co-processor could be scaled for 8-point, 16-point and 32-point FFTs, taking approximate 50, 100 and 150 clock circles, respectively. The complete design was intensively simulated using ARM DSM model and was emulated by ARM Versatile platform, before conducted to silicon. The multi-million-gate ASIC was fabricated using SMIC 0.18 microm mixed-signal CMOS 1P6M technology. The die area measures 5,000 microm x 2,350 microm. The power consumption was approximately 3.6 mW at 1.8 V power supply and 1 MHz clock rate. The power consumption for FFT calculations was less than 1.5 % comparing with the conventional embedded software-based solution.

Single event effect hardness for the front-end ASICs in the DAMPE satellite BGO calorimeter

NASA Astrophysics Data System (ADS)

Gao, Shan-Shan; Jiang, Di; Feng, Chang-Qing; Xi, Kai; Liu, Shu-Bin; An, Qi

2016-01-01

The Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray studies with a primary scientific goal of indirect detection of dark matter particles. As a crucial sub-detector, the BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effects (SEEs) become threats to reliability. In order to evaluate SEE sensitivities of these chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration registers and the optimized sequential design for the data acquisition process, 52 VA160 chips and 32 VATA160 chips have been applied in the flight model of the BGO calorimeter with radiation hardness assurance. Supported by Strategic Priority Research Program on Space Science of the Chinese Academy of Sciences (XDA04040202-4) and Fundamental Research Funds for the Central Universities (WK2030040048)

A tripolar current-steering stimulator ASIC for field shaping in deep brain stimulation.

PubMed

Valente, Virgilio; Demosthenous, Andreas; Bayford, Richard

2012-06-01

A significant problem with clinical deep brain stimulation (DBS) is the high variability of its efficacy and the frequency of side effects, related to the spreading of current beyond the anatomical target area. This is the result of the lack of control that current DBS systems offer on the shaping of the electric potential distribution around the electrode. This paper presents a stimulator ASIC with a tripolar current-steering output stage, aiming at achieving more selectivity and field shaping than current DBS systems. The ASIC was fabricated in a 0.35-μ m CMOS technology occupying a core area of 0.71 mm(2). It consists of three current sourcing/sinking channels. It is capable of generating square and exponential-decay biphasic current pulses with five different time constants up to 28 ms and delivering up to 1.85 mA of cathodic current, in steps of 4 μA, from a 12 V power supply. Field shaping was validated by mapping the potential distribution when injecting current pulses through a multicontact DBS electrode in saline.

MuTRiG: a mixed signal Silicon Photomultiplier readout ASIC with high timing resolution and gigabit data link

NASA Astrophysics Data System (ADS)

Chen, H.; Briggl, K.; Eckert, P.; Harion, T.; Munwes, Y.; Shen, W.; Stankova, V.; Schultz-Coulon, H. C.

2017-01-01

MuTRiG is a mixed signal Silicon Photomultiplier readout ASIC designed in UMC 180 nm CMOS technology for precise timing and high event rate applications in high energy physics experiments and medical imaging. It is dedicated to the readout of the scintillating fiber detector and the scintillating tile detector of the Mu3e experiment. The MuTRiG chip extends the excellent timing performance of the STiCv3 chip with a fast digital readout for high rate applications. The high timing performance of the fully differential SiPM readout channels and 50 ps time binning TDCs are complemented by an upgraded digital readout logic and a 1.28 Gbps LVDS serial data link. The design of the chip and the characterization results of the analog front-end, TDC and the LVDS data link are presented.

Electronic Circuit Analysis Language (ECAL)

NASA Astrophysics Data System (ADS)

Chenghang, C.

1983-03-01

The computer aided design technique is an important development in computer applications and it is an important component of computer science. The special language for electronic circuit analysis is the foundation of computer aided design or computer aided circuit analysis (abbreviated as CACD and CACA) of simulated circuits. Electronic circuit analysis language (ECAL) is a comparatively simple and easy to use circuit analysis special language which uses the FORTRAN language to carry out the explanatory executions. It is capable of conducting dc analysis, ac analysis, and transient analysis of a circuit. Futhermore, the results of the dc analysis can be used directly as the initial conditions for the ac and transient analyses.

Carbon Nanotube Self-Gating Diode and Application in Integrated Circuits.

PubMed

Si, Jia; Liu, Lijun; Wang, Fanglin; Zhang, Zhiyong; Peng, Lian-Mao

2016-07-26

A nano self-gating diode (SGD) based on nanoscale semiconducting material is proposed, simulated, and realized on semiconducting carbon nanotubes (CNTs) through a doping-free fabrication process. The relationships between the performance and material/structural parameters of the SGD are explored through numerical simulation and verified by experiment results. Based on these results, performance optimization strategy is outlined, and high performance CNT SGDs are fabricated and demonstrated to surpass other published CNT diodes. In particular the CNT SGD exhibits high rectifier factor of up to 1.4 × 10(6) while retains large on-state current. Benefiting from high yield and stability, CNT SGDs are used for constructing logic and analog integrated circuits. Two kinds of basic digital gates (AND and OR) have been realized on chip through using CNT SGDs and on-chip Ti wire resistances, and a full wave rectifier circuit has been demonstrated through using two CNT SGDs. Although demonstrated here using CNT SGDs, this device structure may in principle be implemented using other semiconducting nanomaterials, to provide ideas and building blocks for electronic applications based on nanoscale materials.

Electronic control circuits: A compilation

NASA Technical Reports Server (NTRS)

1973-01-01

A compilation of technical R and D information on circuits and modular subassemblies is presented as a part of a technology utilization program. Fundamental design principles and applications are given. Electronic control circuits discussed include: anti-noise circuit; ground protection device for bioinstrumentation; temperature compensation for operational amplifiers; hybrid gatling capacitor; automatic signal range control; integrated clock-switching control; and precision voltage tolerance detector.

Tool for Crimping Flexible Circuit Leads

NASA Technical Reports Server (NTRS)

Hulse, Aaron; Diftler, Myron A.

2009-01-01

A hand tool has been developed for crimping leads in flexible tails that are parts of some electronic circuits -- especially some sensor circuits. The tool is used to cut the tails to desired lengths and attach solder tabs to the leads. For tailoring small numbers of circuits for special applications, this hand tool is a less expensive alternative to a commercially available automated crimping tool. The crimping tool consists of an off-the-shelf hand crimping tool plus a specialized crimping insert designed specifically for the intended application.

Analog integrated circuits design for processing physiological signals.

PubMed

Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

2010-01-01

Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

A CMOS Neural Interface for a Multichannel Vestibular Prosthesis

PubMed Central

Hageman, Kristin N.; Kalayjian, Zaven K.; Tejada, Francisco; Chiang, Bryce; Rahman, Mehdi A.; Fridman, Gene Y.; Dai, Chenkai; Pouliquen, Philippe O.; Georgiou, Julio; Della Santina, Charles C.; Andreou, Andreas G.

2015-01-01

We present a high-voltage CMOS neural-interface chip for a multichannel vestibular prosthesis (MVP) that measures head motion and modulates vestibular nerve activity to restore vision- and posture-stabilizing reflexes. This application specific integrated circuit neural interface (ASIC-NI) chip was designed to work with a commercially available microcontroller, which controls the ASIC-NI via a fast parallel interface to deliver biphasic stimulation pulses with 9-bit programmable current amplitude via 16 stimulation channels. The chip was fabricated in the ONSemi C5 0.5 micron, high-voltage CMOS process and can accommodate compliance voltages up to 12 V, stimulating vestibular nerve branches using biphasic current pulses up to 1.45 ± 0.06 mA with durations as short as 10 µs/phase. The ASIC-NI includes a dedicated digital-to-analog converter for each channel, enabling it to perform complex multipolar stimulation. The ASIC-NI replaces discrete components that cover nearly half of the 2nd generation MVP (MVP2) printed circuit board, reducing the MVP system size by 48% and power consumption by 17%. Physiological tests of the ASIC-based MVP system (MVP2A) in a rhesus monkey produced reflexive eye movement responses to prosthetic stimulation similar to those observed when using the MVP2. Sinusoidal modulation of stimulus pulse rate from 68–130 pulses per second at frequencies from 0.1 to 5 Hz elicited appropriately-directed slow phase eye velocities ranging in amplitude from 1.9–16.7°/s for the MVP2 and 2.0–14.2°/s for the MVP2A. The eye velocities evoked by MVP2 and MVP2A showed no significant difference (t-test, p = 0.034), suggesting that the MVP2A achieves performance at least as good as the larger MVP2. PMID:25974945

Catalytic nucleic acids (DNAzymes) as functional units for logic gates and computing circuits: from basic principles to practical applications.

PubMed

Orbach, Ron; Willner, Bilha; Willner, Itamar

2015-03-11

This feature article addresses the implementation of catalytic nucleic acids as functional units for the construction of logic gates and computing circuits, and discusses the future applications of these systems. The assembly of computational modules composed of DNAzymes has led to the operation of a universal set of logic gates, to field programmable logic gates and computing circuits, to the development of multiplexers/demultiplexers, and to full-adder systems. Also, DNAzyme cascades operating as logic gates and computing circuits were demonstrated. DNAzyme logic systems find important practical applications. These include the use of DNAzyme-based systems for sensing and multiplexed analyses, for the development of controlled release and drug delivery systems, for regulating intracellular biosynthetic pathways, and for the programmed synthesis and operation of cascades.

Practical applications of digital integrated circuits. Part 2: Minimization techniques, code conversion, flip-flops, and asynchronous circuits

NASA Technical Reports Server (NTRS)

1972-01-01

Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be pointed out that the logic theory contained herein applies to all hardware. Binary numbers, simplification of logic circuits, code conversion circuits, basic flip-flop theory, details about series 54/7400, and asynchronous circuits are discussed.

Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

PubMed

Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2016-05-09

Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications

PubMed Central

Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2016-01-01

Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V−1 sec−1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity. PMID:27157914

Effects of high-energy particle showers on the embedded front-end electronics of an electromagnetic calorimeter for a future lepton collider

NASA Astrophysics Data System (ADS)

Adloff, C.; Francis, K.; Repond, J.; Smith, J.; Trojand, D.; Xia, L.; Baldolemar, E.; Li, J.; Park, S. T.; Sosebee, M.; White, A. P.; Yu, J.; Mikami, Y.; Watson, N. K.; Mavromanolakis, G.; Thomson, M. A.; Ward, D. R.; Yan, W.; Benchekroun, D.; Hoummada, A.; Khoulaki, Y.; Benyamna, M.; Cârloganu, C.; Fehr, F.; Gay, P.; Manen, S.; Royer, L.; Blazey, G. C.; Dyshkant, A.; Zutshi, V.; Hostachy, J.-Y.; Morin, L.; Cornett, U.; David, D.; Fabbri, R.; Falley, G.; Gadow, K.; Garutti, E.; Göttlicher, P.; Günter, C.; Karstensen, S.; Krivan, F.; Lucaci-Timoce, A.-I.; Lu, S.; Lutz, B.; Marchesini, I.; Meyer, N.; Morozov, S.; Morgunov, V.; Reinecke, M.; Sefkow, F.; Smirnov, P.; Terwort, M.; Vargas-Trevino, A.; Wattimena, N.; Wendt, O.; Feege, N.; Haller, J.; Richter, S.; Samson, J.; Eckert, P.; Kaplan, A.; Schultz-Coulon, H.-Ch.; Shen, W.; Stamen, R.; Tadday, A.; Bilki, B.; Norbeck, E.; Onel, Y.; Kawagoe, K.; Uozumi, S.; Dauncey, P. D.; Magnan, A.-M.; Bartsch, V.; Salvatore, F.; Laktineh, I.; Calvo Alamillo, E.; Fouz, M.-C.; Puerta-Pelayo, J.; Frey, A.; Kiesling, C.; Simon, F.; Bonis, J.; Bouquet, B.; Callier, S.; Cornebise, P.; Doublet, Ph.; Dulucq, F.; Faucci Giannelli, M.; Fleury, J.; Li, H.; Martin-Chassard, G.; Richard, F.; de La Taille, Ch.; Pöschl, R.; Raux, L.; Seguin-Moreau, N.; Wicek, F.; Anduze, M.; Boudry, V.; Brient, J.-C.; Jeans, D.; Mora de Freitas, P.; Musat, G.; Reinhard, M.; Ruan, M.; Videau, H.; Marcisovsky, M.; Sicho, P.; Vrba, V.; Zalesak, J.; Belhorma, B.; Ghazlane, H.; Calice Collaboration

2011-10-01

Application Specific Integrated Circuits, ASICs, similar to those envisaged for the readout electronics of the central calorimeters of detectors for a future lepton collider have been exposed to high-energy electromagnetic showers. A salient feature of these calorimeters is that the readout electronics will be embedded into the calorimeter layers. In this article it is shown that interactions of shower particles in the volume of the readout electronics do not alter the noise pattern of the ASICs. No signal at or above the MIP level has been observed during the exposure. The upper limit at the 95% confidence level on the frequency of fake signals is smaller than 1×10-5 for a noise threshold of about 60% of a MIP. For ASICs with similar design to those which were tested, it can thus be largely excluded that the embedding of the electronics into the calorimeter layers compromises the performance of the calorimeters.

Sensor readout detector circuit

DOEpatents

Chu, Dahlon D.; Thelen, Jr., Donald C.

1998-01-01

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems.

Sensor readout detector circuit

DOEpatents

Chu, D.D.; Thelen, D.C. Jr.

1998-08-11

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems. 6 figs.

SEMICONDUCTOR INTEGRATED CIRCUITS: A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth

NASA Astrophysics Data System (ADS)

Tao, Tong; Baoyong, Chi; Ziqiang, Wang; Ying, Zhang; Hanjun, Jiang; Zhihua, Wang

2010-05-01

A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth in 0.35 μm CMOS is presented. The circuit consists of two variable gain amplifiers (VGA) in cascade and a Gm-C elliptic low-pass filter (LPF). The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications. In order to achieve the optimum power consumption, the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application. Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN, 8.9 mW for WCDMA and only 6.5 mW for Bluetooth, all with a 3 V power supply. The analog baseband circuit could provide -10 to +40 dB variable gain, third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth, fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA, and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN, respectively.

Management of Microcircuit Obsolescence in a Pre-Production ACAT-ID Missile Program

DTIC Science & Technology

2002-12-01

and Engineering Center ASIC Application Specific Integrated Circuit AVCOM Avionics Component Obsolescence Management BRU Battery Replaceable Unit...then just a paper qualification, e.g. Board or Battery Replaceable Unit ( BRU ) testing. 5 After-market Package The Die is Available and Can Be...Encapsulated Microcircuits (PEM), speed change, failure rate) 8 Emulation Manufacture or re-engineering of a FFF Replacement 9 CCA or BRU Redesign Board

Single software platform used for high speed data transfer implementation in a 65k pixel camera working in single photon counting mode

NASA Astrophysics Data System (ADS)

Maj, P.; Kasiński, K.; Gryboś, P.; Szczygieł, R.; Kozioł, A.

2015-12-01

Integrated circuits designed for specific applications generally use non-standard communication methods. Hybrid pixel detector readout electronics produces a huge amount of data as a result of number of frames per seconds. The data needs to be transmitted to a higher level system without limiting the ASIC's capabilities. Nowadays, the Camera Link interface is still one of the fastest communication methods, allowing transmission speeds up to 800 MB/s. In order to communicate between a higher level system and the ASIC with a dedicated protocol, an FPGA with dedicated code is required. The configuration data is received from the PC and written to the ASIC. At the same time, the same FPGA should be able to transmit the data from the ASIC to the PC at the very high speed. The camera should be an embedded system enabling autonomous operation and self-monitoring. In the presented solution, at least three different hardware platforms are used—FPGA, microprocessor with real-time operating system and the PC with end-user software. We present the use of a single software platform for high speed data transfer from 65k pixel camera to the personal computer.

DOE Office of Scientific and Technical Information (OSTI.GOV)

DE GERONIMO,G.; CHEN, W.; FRIED, J.

We present an application specific integrated circuit (ASIC) for high-resolution x-ray spectrometers. The ASIC is designed to read out signals from a pixelated silicon drift detector (SDD). Each hexagonal pixel has an area of 15 mmz and an anode capacitance of less than 100 fF. There is no integrated Field Effect transistor (FET) in the pixel, rather, the readout is done by wirebonding the anodes to the inputs of the ASIC. The ASIC provides 14 channels of low-noise charge amplification, high-order shaping with baseline stabilization, and peak detection with analog memory. The readout is sparse and based on low voltagemore » differential signaling. An interposer provides all the interconnections required to bias and operate the system. The channel dissipates 1.6 mW. The complete 14-pixel unit covers an area of 210 mm{sup 2}, dissipates 12 mW cm{sup -2}, and can be tiled to cover an arbitrarily large detection area. We measured a preliminary resolution of 172 eV at -35 C on the 6 keV peak of a {sup 55}Fe source.« less

The use of hybrid integrated circuit techniques in biotelemetry applications

NASA Technical Reports Server (NTRS)

Fryer, T. B.

1977-01-01

A review is presented of some features of hybrid integrated circuits that make their use advantageous in miniature biotelemetry applications. The various techniques for fabricating resistors, capacitors and interconnections by both thin film and thick film technology are discussed. The use of chip capacitors, resistors, and especially standard IC chips on substrates with fired-on interconnection patterns is emphasized. The review is designed primarily to acquaint biotelemetry users and designers with an overview of this fabrication technique so that they can better communicate their needs with an understanding of its limitations and advantages to facilities specializing in hybrid construction.

Design of pressure-driven microfluidic networks using electric circuit analogy.

PubMed

Oh, Kwang W; Lee, Kangsun; Ahn, Byungwook; Furlani, Edward P

2012-02-07

This article reviews the application of electric circuit methods for the analysis of pressure-driven microfluidic networks with an emphasis on concentration- and flow-dependent systems. The application of circuit methods to microfluidics is based on the analogous behaviour of hydraulic and electric circuits with correlations of pressure to voltage, volumetric flow rate to current, and hydraulic to electric resistance. Circuit analysis enables rapid predictions of pressure-driven laminar flow in microchannels and is very useful for designing complex microfluidic networks in advance of fabrication. This article provides a comprehensive overview of the physics of pressure-driven laminar flow, the formal analogy between electric and hydraulic circuits, applications of circuit theory to microfluidic network-based devices, recent development and applications of concentration- and flow-dependent microfluidic networks, and promising future applications. The lab-on-a-chip (LOC) and microfluidics community will gain insightful ideas and practical design strategies for developing unique microfluidic network-based devices to address a broad range of biological, chemical, pharmaceutical, and other scientific and technical challenges.

Integrated coherent matter wave circuits

DOE PAGES

Ryu, C.; Boshier, M. G.

2015-09-21

An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through theirmore » electric polarizability. Moreover, the source of coherent matter waves is a Bose–Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry.« less

Fractal Electronic Circuits Assembled From Nanoclusters

NASA Astrophysics Data System (ADS)

Fairbanks, M. S.; McCarthy, D.; Taylor, R. P.; Brown, S. A.

2009-07-01

Many patterns in nature can be described using fractal geometry. The effect of this fractal character is an array of properties that can include high internal connectivity, high dispersivity, and enhanced surface area to volume ratios. These properties are often desirable in applications and, consequently, fractal geometry is increasingly employed in technologies ranging from antenna to storm barriers. In this paper, we explore the application of fractal geometry to electrical circuits, inspired by the pervasive fractal structure of neurons in the brain. We show that, under appropriate growth conditions, nanoclusters of Sb form into islands on atomically flat substrates via a process close to diffusion-limited aggregation (DLA), establishing fractal islands that will form the basis of our fractal circuits. We perform fractal analysis of the islands to determine the spatial scaling properties (characterized by the fractal dimension, D) of the proposed circuits and demonstrate how varying growth conditions can affect D. We discuss fabrication approaches for establishing electrical contact to the fractal islands. Finally, we present fractal circuit simulations, which show that the fractal character of the circuit translates into novel, non-linear conduction properties determined by the circuit's D value.

Negative Difference Resistance and Its Application to Construct Boolean Logic Circuits

NASA Astrophysics Data System (ADS)

Nikodem, Maciej; Bawiec, Marek A.; Surmacz, Tomasz R.

Electronic circuits based on nanodevices and quantum effect are the future of logic circuits design. Today's technology allows constructing resonant tunneling diodes, quantum cellular automata and nanowires/nanoribbons that are the elementary components of threshold gates. However, synthesizing a threshold circuit for an arbitrary logic function is still a challenging task where no efficient algorithms exist. This paper focuses on Generalised Threshold Gates (GTG), giving the overview of threshold circuit synthesis methods and presenting an algorithm that considerably simplifies the task in case of GTG circuits.

A One Chip Hardened Solution for High Speed SpaceWire System Implementations. Session: Components

NASA Technical Reports Server (NTRS)

Marshall, Joseph R.; Berger, Richard W.; Rakow, Glenn P.

2007-01-01

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASIC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a router with 4 SpaceWire ports and two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, and a memory controller for additional external memory use. The SpaceWire cores are also reused in other ASICs under development. The SpaceWire ASIC is planned for use on the Geostationary Operational Environmental Satellites (GOES)-R, the Lunar Reconnaissance Orbiter (LRO) and other missions. Engineering and flight parts have been delivered to programs and users. This paper reviews the SpaceWire protocol and those elements of it that have been built into the current and next SpaceWire reusable cores and features within the core that go beyond the current standard and can be enabled or disabled by the user. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be reviewed and highlighted. Optional configurations within user systems and test boards will be shown. The physical implementation of the design will be described and test results from the hardware will be discussed. Application of this ASIC and other ASICs containing the SpaceWire cores and embedded microcontroller to Plug and Play and reconfigurable implementations will be described. Finally, the BAE Systems roadmap for SpaceWire developments will be updated, including some products already in design as well as longer term plans.

Multi-petascale highly efficient parallel supercomputer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Asaad, Sameh; Bellofatto, Ralph E.; Blocksome, Michael A.

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time andmore » supports DMA functionality allowing for parallel processing message-passing.« less

Role of peripheral sigma-1 receptors in ischaemic pain: Potential interactions with ASIC and P2X receptors.

PubMed

Kwon, S G; Roh, D H; Yoon, S Y; Choi, S R; Choi, H S; Moon, J Y; Kang, S Y; Kim, H W; Han, H J; Beitz, A J; Oh, S B; Lee, J H

2016-04-01

The role of peripheral sigma-1 receptors (Sig-1Rs) in normal nociception and in pathologically induced pain conditions has not been thoroughly investigated. Since there is mounting evidence that Sig-1Rs modulate ischaemia-induced pathological conditions, we investigated the role of Sig-1Rs in ischaemia-induced mechanical allodynia (MA) and addressed their possible interaction with acid-sensing ion channels (ASICs) and P2X receptors at the ischaemic site. We used a rodent model of hindlimb thrombus-induced ischaemic pain (TIIP) to investigate their role. Western blot was performed to observe changes in Sig-1R expression in peripheral nervous tissues. MA was measured after intraplantar (i.pl.) injections of antagonists for the Sig-1, ASIC and P2X receptors in TIIP rats or agonists of each receptor in naïve rats. Sig-1R expression significantly increased in skin, sciatic nerve and dorsal root ganglia at 3 days post-TIIP surgery. I.pl. injections of the Sig-1R antagonist, BD-1047 on post-operative days 0-3 significantly attenuated the development of MA during the induction phase, but had no effect on MA when given during the maintenance phase (days 3-6 post-surgery). BD-1047 synergistically increased amiloride (an ASICs blocker)- and TNP-ATP (a P2X antagonist)-induced analgesic effects in TIIP rats. In naïve rats, i.pl. injection of Sig-1R agonist PRE-084 alone did not produce MA; but it did induce MA when co-administered with either an acidic pH solution or a sub-effective dose of αβmeATP. Peripheral Sig-1Rs contribute to the induction of ischaemia-induced MA via facilitation of ASICs and P2X receptors. Thus, peripheral Sig-1Rs represent a novel therapeutic target for the treatment of ischaemic pain. © 2015 European Pain Federation - EFIC®

Biosignal integrated circuit with simultaneous acquisition of ECG and PPG for wearable healthcare applications.

PubMed

Kim, Hyungseup; Park, Yunjong; Ko, Youngwoon; Mun, Yeongjin; Lee, Sangmin; Ko, Hyoungho

2018-01-01

Wearable healthcare systems require measurements from electrocardiograms (ECGs) and photoplethysmograms (PPGs), and the blood pressure of the user. The pulse transit time (PTT) can be calculated by measuring the ECG and PPG simultaneously. Continuous-time blood pressure without using an air cuff can be estimated by using the PTT. This paper presents a biosignal acquisition integrated circuit (IC) that can simultaneously measure the ECG and PPG for wearable healthcare applications. Included in this biosignal acquisition circuit are a voltage mode instrumentation amplifier (IA) for ECG acquisition and a current mode transimpedance amplifier for PPG acquisition. The analog outputs from the ECG and PPG channels are muxed and converted to digital signals using 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The proposed IC is fabricated by using a standard 0.18 μm CMOS process with an active area of 14.44 mm2. The total current consumption for the multichannel IC is 327 μA with a 3.3 V supply. The measured input referred noise of ECG readout channel is 1.3 μVRMS with a bandwidth of 0.5 Hz to 100 Hz. And the measured input referred current noise of the PPG readout channel is 0.122 nA/√Hz with a bandwidth of 0.5 Hz to 100 Hz. The proposed IC, which is implemented using various circuit techniques, can measure ECG and PPG signals simultaneously to calculate the PTT for wearable healthcare applications.

A nickel-cadmium battery reconditioning circuit

NASA Technical Reports Server (NTRS)

Lanier, R.

1977-01-01

The circuit presented is simple and small enough to be included in a typical battery charge/power control assembly, yet provides the advantage of a complete ground-type battery reconditioning discharge. Test results on the circuit when used to recondition two 24 cell, 20 A-h nickel-cadmium batteries are given. These results show that a battery reconditioned with this circuit returns to greater than 90 percent of its original capacity (greater than nameplate capacity) and follows a typical new battery degradation curve even after over 20,000 simulated orbital cycles for a 4 year period. Applications of the circuit are considered along with recommendations relative to its use. Its application in low voltage (22 to 36 Vdc) power systems and in high voltage (100 to 150 Vdc) power systems is discussed. The implications are that the high voltage systems have a greater need for battery reconditioning than their low voltage counterparts, and that using these circuit techniques, the expected life of a battery in low Earth orbit can be up to 5 years.

ASIC-based architecture for the real-time computation of 2D convolution with large kernel size

NASA Astrophysics Data System (ADS)

Shao, Rui; Zhong, Sheng; Yan, Luxin

2015-12-01

Bidimensional convolution is a low-level processing algorithm of interest in many areas, but its high computational cost constrains the size of the kernels, especially in real-time embedded systems. This paper presents a hardware architecture for the ASIC-based implementation of 2-D convolution with medium-large kernels. Aiming to improve the efficiency of storage resources on-chip, reducing off-chip bandwidth of these two issues, proposed construction of a data cache reuse. Multi-block SPRAM to cross cached images and the on-chip ping-pong operation takes full advantage of the data convolution calculation reuse, design a new ASIC data scheduling scheme and overall architecture. Experimental results show that the structure can achieve 40× 32 size of template real-time convolution operations, and improve the utilization of on-chip memory bandwidth and on-chip memory resources, the experimental results show that the structure satisfies the conditions to maximize data throughput output , reducing the need for off-chip memory bandwidth.

A novel CMOS transducer for giant magnetoresistance sensors.

PubMed

Luong, Van Su; Lu, Chih-Cheng; Yang, Jing-Wen; Jeng, Jen-Tzong

2017-02-01

In this work, an ASIC (application specific integrated circuits) transducer circuit for field modulated giant magnetoresistance (GMR) sensors was designed and fabricated using a 0.18-μm CMOS process. The transducer circuits consist of a frequency divider, a digital phase shifter, an instrument amplifier, and an analog mixer. These comprise a mix of analog and digital circuit techniques. The compact chip size of 1.5 mm × 1.5 mm for both analog and digital parts was achieved using the TSMC18 1P6M (1-polysilicon 6-metal) process design kit, and the characteristics of the system were simulated using an HSpice simulator. The output of the transducer circuit is the result of the first harmonic detection, which resolves the modulated field using a phase sensitive detection (PSD) technique and is proportional to the measured magnetic field. When the dual-bridge GMR sensor is driven by the transducer circuit with a current of 10 mA at 10 kHz, the observed sensitivity of the field sensor is 10.2 mV/V/Oe and the nonlinearity error was 3% in the linear range of ±1 Oe. The performance of the system was also verified by rotating the sensor system horizontally in earth's magnetic field and recording the sinusoidal output with respect to the azimuth angle, which exhibits an error of less than ±0.04 Oe. These results prove that the ASIC transducer is suitable for driving the AC field modulated GMR sensors applied to geomagnetic measurement.

A SUBSATELLITE AREA-OF-VIEW CIRCUIT.

DTIC Science & Technology

A subsatellite circle circuit is included in the NRL experimental satellite position prediction and display equipment ( SPAD ). The circuit paints, on...center is defined by the subsatellite position, and the SPAD prediction computer uses the satellite look-cone angle (say, that of a cloud-cover camera) and...modification the circle circuit used for SPAD is applicable to any cathode-ray tube display having either electrostatic or magnetic deflection

ISFET-based sensor signal processor chip design for environment monitoring applications

NASA Astrophysics Data System (ADS)

Chung, Wen-Yaw; Yang, Chung-Huang; Wang, Ming-Ga

2004-12-01

In recent years Ion-Sensitive Field Effect Transistor (ISFET) based transducers create valuable applications in physiological data acquisition and environment monitoring. This paper presents a mixed-mode ASIC design for potentiometric ISFET-based bio-chemical sensor applications including H+ sensing and hand-held pH meter. For battery power consideration, the proposed system consists of low voltage (3V) analog front-end readout circuits and digital processor has been developed and fabricated in a 0.5mm double-poly double-metal CMOS technology. To assure that the correct pH value can be measured, the two-point calibration circuitry based on the response of standard pH4 and pH7 buffer solution has been implemented by using algorithmic state machine hardware algorithms. The measurement accuracy of the chip is 10 bits and the measured range between pH 2 to pH 12 compared to ideal values is within the accuracy of 0.1pH. For homeland environmental applications, the system provide rapid, easy to use, and cost-effective on-site testing on the quality of water, such as drinking water, ground water and river water. The processor has a potential usage in battery-operated and portable devices in environmental monitoring applications compared to commercial hand-held pH meter.

Optical printed circuit board (O-PCB) and VLSI photonic integrated circuits: visions, challenges, and progresses

NASA Astrophysics Data System (ADS)

Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Noh, H. S.; Kim, K. H.; Song, S. H.

2006-09-01

A collective overview and review is presented on the original work conducted on the theory, design, fabrication, and in-tegration of micro/nano-scale optical wires and photonic devices for applications in a newly-conceived photonic systems called "optical printed circuit board" (O-PCBs) and "VLSI photonic integrated circuits" (VLSI-PIC). These are aimed for compact, high-speed, multi-functional, intelligent, light-weight, low-energy and environmentally friendly, low-cost, and high-volume applications to complement or surpass the capabilities of electrical PCBs (E-PCBs) and/or VLSI electronic integrated circuit (VLSI-IC) systems. These consist of 2-dimensional or 3-dimensional planar arrays of micro/nano-optical wires and circuits to perform the functions of all-optical sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards or substrates. The integrated optical devices include micro/nano-scale waveguides, lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices, made of polymer, silicon and other semiconductor materials. For VLSI photonic integration, photonic crystals and plasmonic structures have been used. Scientific and technological issues concerning the processes of miniaturization, interconnection and integration of these systems as applicable to board-to-board, chip-to-chip, and intra-chip integration, are discussed along with applications for future computers, telecommunications, and sensor-systems. Visions and challenges toward these goals are also discussed.

Silicon Carbide Integrated Circuit Chip

NASA Image and Video Library

2015-02-17

A multilevel interconnect silicon carbide integrated circuit chip with co-fired ceramic package and circuit board recently developed at the NASA GRC Smart Sensors and Electronics Systems Branch for high temperature applications. High temperature silicon carbide electronics and compatible packaging technologies are elements of instrumentation for aerospace engine control and long term inner-solar planet explorations.

SFERA: An Integrated Circuit for the Readout of X and gamma -Ray Detectors

NASA Astrophysics Data System (ADS)

Schembari, Filippo; Quaglia, Riccardo; Bellotti, Giovanni; Fiorini, Carlo

2016-06-01

In this work we present SFERA, a low-noise fully-programmable 16 channel readout ASIC designed for both Xand y-ray spectroscopy and imaging applications. The chip is designed to process signals coming from solid-state detectors and CMOS preamplifiers. The design has been guided by the use of Silicon Drift Detectors (SDDs) and CUBE charge sensitive amplifiers (CSAs), although we consider the ASIC sufficiently versatile to be used with other types of detectors. Five different gains are implemented, namely 2800 e-, 4400 e-, 10000 e-, 14000 e- and 20000 e-, considering the input connected to a 25 fF feedback capacitance CMOS preamplifier. Filter peaking times (tP) are also programmable among 0.5, 1, 2, 3, 4 and 6 μs. Each readout channel is the cascade of a 9th order semi-Gaussian shaping-amplifier (SA) and a peak detector (PKS), followed by a dedicated pile-up rejection (PUR) digital logic. Three data multiplexing strategies are implemented: the so-called polling X, intended for high-rate X-ray applications, the polling y, for scintillation light detection and the sparse, for signals derandomization. The spectroscopic characterization has shown an energy resolution of 122.1 eV FWHM on the Mn-Ku line of an 55Fe X-ray source using a 10 mm2 SDD cooled at -35 °C at 4 μs filter peaking time. The measured resolution is 130 eV at the peaking time of 500 ns. At 1 Mcps input count rate and 500 ns peaking time, we have measured 42% of processed events at the output of the ASIC after the PUR selection. Output data can be digitized on-chip by means of an embedded 12-bit successive-approximation ADC. The effective resolution of the data converter is 10.75-bit when operated at 4.5 MS/s. The chosen technology is the AMS 0.35 μm CMOS and the chip area occupancy is 5 × 5 mm2.

Traveling-Wave Tube Cold-Test Circuit Optimization Using CST MICROWAVE STUDIO

NASA Technical Reports Server (NTRS)

Chevalier, Christine T.; Kory, Carol L.; Wilson, Jeffrey D.; Wintucky, Edwin G.; Dayton, James A., Jr.

2003-01-01

The internal optimizer of CST MICROWAVE STUDIO (MWS) was used along with an application-specific Visual Basic for Applications (VBA) script to develop a method to optimize traveling-wave tube (TWT) cold-test circuit performance. The optimization procedure allows simultaneous optimization of circuit specifications including on-axis interaction impedance, bandwidth or geometric limitations. The application of Microwave Studio to TWT cold-test circuit optimization is described.

Scalable, efficient ASICS for the square kilometre array: From A/D conversion to central correlation

NASA Astrophysics Data System (ADS)

Schmatz, M. L.; Jongerius, R.; Dittmann, G.; Anghel, A.; Engbersen, T.; van Lunteren, J.; Buchmann, P.

2014-05-01

The Square Kilometre Array (SKA) is a future radio telescope, currently being designed by the worldwide radio-astronomy community. During the first of two construction phases, more than 250,000 antennas will be deployed, clustered in aperture-array stations. The antennas will generate 2.5 Pb/s of data, which needs to be processed in real time. For the processing stages from A/D conversion to central correlation, we propose an ASIC solution using only three chip architectures. The architecture is scalable - additional chips support additional antennas or beams - and versatile - it can relocate its receiver band within a range of a few MHz up to 4GHz. This flexibility makes it applicable to both SKA phases 1 and 2. The proposed chips implement an antenna and station processor for 289 antennas with a power consumption on the order of 600W and a correlator, including corner turn, for 911 stations on the order of 90 kW.

ChromAIX2: A large area, high count-rate energy-resolving photon counting ASIC for a Spectral CT Prototype

NASA Astrophysics Data System (ADS)

Steadman, Roger; Herrmann, Christoph; Livne, Amir

2017-08-01

Spectral CT based on energy-resolving photon counting detectors is expected to deliver additional diagnostic value at a lower dose than current state-of-the-art CT [1]. The capability of simultaneously providing a number of spectrally distinct measurements not only allows distinguishing between photo-electric and Compton interactions but also discriminating contrast agents that exhibit a K-edge discontinuity in the absorption spectrum, referred to as K-edge Imaging [2]. Such detectors are based on direct converting sensors (e.g. CdTe or CdZnTe) and high-rate photon counting electronics. To support the development of Spectral CT and show the feasibility of obtaining rates exceeding 10 Mcps/pixel (Poissonian observed count-rate), the ChromAIX ASIC has been previously reported showing 13.5 Mcps/pixel (150 Mcps/mm2 incident) [3]. The ChromAIX has been improved to offer the possibility of a large area coverage detector, and increased overall performance. The new ASIC is called ChromAIX2, and delivers count-rates exceeding 15 Mcps/pixel with an rms-noise performance of approximately 260 e-. It has an isotropic pixel pitch of 500 μm in an array of 22×32 pixels and is tile-able on three of its sides. The pixel topology consists of a two stage amplifier (CSA and Shaper) and a number of test features allowing to thoroughly characterize the ASIC without a sensor. A total of 5 independent thresholds are also available within each pixel, allowing to acquire 5 spectrally distinct measurements simultaneously. The ASIC also incorporates a baseline restorer to eliminate excess currents induced by the sensor (e.g. dark current and low frequency drifts) which would otherwise cause an energy estimation error. In this paper we report on the inherent electrical performance of the ChromAXI2 as well as measurements obtained with CZT (CdZnTe)/CdTe sensors and X-rays and radioactive sources.

Microfluidic Serial Dilution Circuit

PubMed Central

Paegel, Brian M.; Grover, William H.; Skelley, Alison M.; Mathies, Richard A.; Joyce, Gerald F.

2008-01-01

In vitro evolution of RNA molecules requires a method for executing many consecutive serial dilutions. To solve this problem, a microfluidic circuit has been fabricated in a three-layer glass-PDMS-glass device. The 400-nL serial dilution circuit contains five integrated membrane valves: three two-way valves arranged in a loop to drive cyclic mixing of the diluent and carryover, and two bus valves to control fluidic access to the circuit through input and output channels. By varying the valve placement in the circuit, carryover fractions from 0.04 to 0.2 were obtained. Each dilution process, which is comprised of a diluent flush cycle followed by a mixing cycle, is carried out with no pipeting, and a sample volume of 400 nL is sufficient for conducting an arbitrary number of serial dilutions. Mixing is precisely controlled by changing the cyclic pumping rate, with a minimum mixing time of 22 s. This microfluidic circuit is generally applicable for integrating automated serial dilution and sample preparation in almost any microfluidic architecture. PMID:17073422

Simple circuit for pacing hearts of experimental animals.

PubMed

Freeman, G L; Colston, J T

1992-06-01

In this paper we describe a simple pacing circuit which can be used to drive the heart over a wide range of rates. The circuit is an astable multivibrator, based on an LM555 integrated circuit. It is powered by a 9-V battery and is small enough for use in rabbits. The circuit is easily constructed and inexpensive, making it attractive for numerous applications in cardiovascular research.

Electronic circuits: A compilation. [for electronic equipment in telecommunication

NASA Technical Reports Server (NTRS)

1976-01-01

A compilation containing articles on newly developed electronic circuits and systems is presented. It is divided into two sections: (1) section 1 on circuits and techniques of particular interest in communications technology, and (2) section 2 on circuits designed for a variety of specific applications. The latest patent information available is also given. Circuit diagrams are shown.

Ultra-Reliable Digital Avionics (URDA) processor

NASA Astrophysics Data System (ADS)

Branstetter, Reagan; Ruszczyk, William; Miville, Frank

1994-10-01

Texas Instruments Incorporated (TI) developed the URDA processor design under contract with the U.S. Air Force Wright Laboratory and the U.S. Army Night Vision and Electro-Sensors Directorate. TI's approach couples advanced packaging solutions with advanced integrated circuit (IC) technology to provide a high-performance (200 MIPS/800 MFLOPS) modular avionics processor module for a wide range of avionics applications. TI's processor design integrates two Ada-programmable, URDA basic processor modules (BPM's) with a JIAWG-compatible PiBus and TMBus on a single F-22 common integrated processor-compatible form-factor SEM-E avionics card. A separate, high-speed (25-MWord/second 32-bit word) input/output bus is provided for sensor data. Each BPM provides a peak throughput of 100 MIPS scalar concurrent with 400-MFLOPS vector processing in a removable multichip module (MCM) mounted to a liquid-flowthrough (LFT) core and interfacing to a processor interface module printed wiring board (PWB). Commercial RISC technology coupled with TI's advanced bipolar complementary metal oxide semiconductor (BiCMOS) application specific integrated circuit (ASIC) and silicon-on-silicon packaging technologies are used to achieve the high performance in a miniaturized package. A Mips R4000-family reduced instruction set computer (RISC) processor and a TI 100-MHz BiCMOS vector coprocessor (VCP) ASIC provide, respectively, the 100 MIPS of a scalar processor throughput and 400 MFLOPS of vector processing throughput for each BPM. The TI Aladdim ASIC chipset was developed on the TI Aladdin Program under contract with the U.S. Army Communications and Electronics Command and was sponsored by the Advanced Research Projects Agency with technical direction from the U.S. Army Night Vision and Electro-Sensors Directorate.

Triple inverter pierce oscillator circuit suitable for CMOS

DOEpatents

Wessendorf,; Kurt, O [Albuquerque, NM

2007-02-27

An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

Four-terminal circuit element with photonic core

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sampayan, Stephen

A four-terminal circuit element is described that includes a photonic core inside of the circuit element that uses a wide bandgap semiconductor material that exhibits photoconductivity and allows current flow through the material in response to the light that is incident on the wide bandgap material. The four-terminal circuit element can be configured based on various hardware structures using a single piece or multiple pieces or layers of a wide bandgap semiconductor material to achieve various designed electrical properties such as high switching voltages by using the photoconductive feature beyond the breakdown voltages of semiconductor devices or circuits operated basedmore » on electrical bias or control designs. The photonic core aspect of the four-terminal circuit element provides unique features that enable versatile circuit applications to either replace the semiconductor transistor-based circuit elements or semiconductor diode-based circuit elements.« less

Noise isolation system for high-speed circuits

DOEpatents

McNeilly, D.R.

1983-12-29

A noise isolation circuit is provided that consists of a dual function bypass which confines high-speed switching noise to the component or circuit which generates it and isolates the component or circuit from high-frequency noise transients which may be present on the ground and power supply busses. A local circuit ground is provided which is coupled to the system ground by sufficient impedance to force the dissipation of the noise signal in the local circuit or component generating the noise. The dual function bypass network couples high-frequency noise signals generated in the local component or circuit through a capacitor to the local ground while isolating the component or circuit from noise signals which may be present on the power supply busses or system ground. The network is an effective noise isolating system and is applicable to both high-speed analog and digital circuits.

Noise isolation system for high-speed circuits

DOEpatents

McNeilly, David R.

1986-01-01

A noise isolation circuit is provided that consists of a dual function bypass which confines high-speed switching noise to the component or circuit which generates it and isolates the component or circuit from high-frequency noise transients which may be present on the ground and power supply busses. A local circuit ground is provided which is coupled to the system ground by sufficient impedance to force the dissipation of the noise signal in the local circuit or component generating the noise. The dual function bypass network couples high-frequency noise signals generated in the local component or circuit through a capacitor to the local ground while isolating the component or circuit from noise signals which may be present on the power supply busses or system ground. The network is an effective noise isolating system and is applicable to both high-speed analog and digital circuits.

Micropower circuits for bidirectional wireless telemetry in neural recording applications.

PubMed

Neihart, Nathan M; Harrison, Reid R

2005-11-01

State-of-the art neural recording systems require electronics allowing for transcutaneous, bidirectional data transfer. As these circuits will be implanted near the brain, they must be small and low power. We have developed micropower integrated circuits for recovering clock and data signals over a transcutaneous power link. The data recovery circuit produces a digital data signal from an ac power waveform that has been amplitude modulated. We have also developed an FM transmitter with the lowest power dissipation reported for biosignal telemetry. The FM transmitter consists of a low-noise biopotential amplifier and a voltage controlled oscillator used to transmit amplified neural signals at a frequency near 433 MHz. All circuits were fabricated in a standard 0.5-microm CMOS VLSI process. The resulting chip is powered through a wireless inductive link. The power consumption of the clock and data recovery circuits is measured to be 129 microW; the power consumption of the transmitter is measured to be 465 microW when using an external surface mount inductor. Using a parasitic antenna less than 2 mm long, a received power level was measured to be -59.73 dBm at a distance of one meter.

MULTI-ELECTRODE TUBE PULSE MEMORY CIRCUIT

DOEpatents

Gundlach, J.C.; Reeves, J.B.

1958-05-20

Control circuits are described for pulse memory devices for scalers and the like, and more particularly to a driving or energizing circuit for a polycathode gaseous discharge tube having an elongated anode and a successive series of cathodes spaced opposite the anode along its length. The circuit is so arranged as to utilize an arc discharge between the anode and a cathode to count a series of pulses. Upon application of an input pulse the discharge is made to occur between the anode and the next successive cathode, and an output pulse is produced when a particular subsequent cathode is reached. The circuit means for transfering the discharge by altering the anode potential and potential of the cathodes and interconnecting the cathodes constitutes the novel aspects of the invention. A low response time and reduced number of circuit components are the practical advantages of the described circuit.

Detector Control and Data Acquisition for the Wide-Field Infrared Survey Telescope (WFIRST) with a Custom ASIC

NASA Technical Reports Server (NTRS)

Smith, Brian S.; Loose, Markus; Alkire, Greg; Joshi, Atul; Kelly, Daniel; Siskind, Eric; Rossetti, Dino; Mah, Jonathan; Cheng, Edward; Miko, Laddawan;

Low-power wireless micromanometer system for acute and chronic bladder-pressure monitoring.

PubMed

Majerus, Steve J A; Fletter, Paul C; Damaser, Margot S; Garverick, Steven L

2011-03-01

This letter describes the design, fabrication, and testing of a wireless bladder-pressure-sensing system for chronic, point-of-care applications, such as urodynamics or closed-loop neuromodulation. The system consists of a miniature implantable device and an external RF receiver and wireless battery charger. The implant is small enough to be cystoscopically implanted within the bladder wall, where it is securely held and shielded from the urine stream. The implant consists of a custom application-specific integrated circuit (ASIC), a pressure transducer, a rechargeable battery, and wireless telemetry and recharging antennas. The ASIC includes instrumentation, wireless transmission, and power-management circuitry, and on an average draws less than 9 μA from the 3.6-V battery. The battery charge can be wirelessly replenished with daily 6-h recharge periods that can occur during the periods of sleep. Acute in vivo evaluation of the pressure-sensing system in canine models has demonstrated that the system can accurately capture lumen pressure from a submucosal implant location.

Radiation-Hardened Solid-State Drive

NASA Technical Reports Server (NTRS)

Sheldon, Douglas J.

2010-01-01

A method is provided for a radiationhardened (rad-hard) solid-state drive for space mission memory applications by combining rad-hard and commercial off-the-shelf (COTS) non-volatile memories (NVMs) into a hybrid architecture. The architecture is controlled by a rad-hard ASIC (application specific integrated circuit) or a FPGA (field programmable gate array). Specific error handling and data management protocols are developed for use in a rad-hard environment. The rad-hard memories are smaller in overall memory density, but are used to control and manage radiation-induced errors in the main, and much larger density, non-rad-hard COTS memory devices. Small amounts of rad-hard memory are used as error buffers and temporary caches for radiation-induced errors in the large COTS memories. The rad-hard ASIC/FPGA implements a variety of error-handling protocols to manage these radiation-induced errors. The large COTS memory is triplicated for protection, and CRC-based counters are calculated for sub-areas in each COTS NVM array. These counters are stored in the rad-hard non-volatile memory. Through monitoring, rewriting, regeneration, triplication, and long-term storage, radiation-induced errors in the large NV memory are managed. The rad-hard ASIC/FPGA also interfaces with the external computer buses.

Error Mitigation for Short-Depth Quantum Circuits

NASA Astrophysics Data System (ADS)

Temme, Kristan; Bravyi, Sergey; Gambetta, Jay M.

2017-11-01

Two schemes are presented that mitigate the effect of errors and decoherence in short-depth quantum circuits. The size of the circuits for which these techniques can be applied is limited by the rate at which the errors in the computation are introduced. Near-term applications of early quantum devices, such as quantum simulations, rely on accurate estimates of expectation values to become relevant. Decoherence and gate errors lead to wrong estimates of the expectation values of observables used to evaluate the noisy circuit. The two schemes we discuss are deliberately simple and do not require additional qubit resources, so to be as practically relevant in current experiments as possible. The first method, extrapolation to the zero noise limit, subsequently cancels powers of the noise perturbations by an application of Richardson's deferred approach to the limit. The second method cancels errors by resampling randomized circuits according to a quasiprobability distribution.

Hermetic Packages For Millimeter-Wave Circuits

NASA Technical Reports Server (NTRS)

Herman, Martin I.; Lee, Karen A.; Lowry, Lynn E.; Carpenter, Alain; Wamhof, Paul

1994-01-01

Advanced hermetic packages developed to house electronic circuits operating at frequencies from 1 to 100 gigahertz and beyond. Signals coupled into and out of packages electromagnetically. Provides circuit packages small, lightweight, rugged, and inexpensive in mass production. Packages embedded in planar microstrip and coplanar waveguide circuits, in waveguide-to-planar and planar-to-waveguide circuitry, in waveguide-to-waveguide circuitry, between radiating (antenna) elements, and between planar transmission lines and radiating elements. Other applications in automotive, communication, radar, remote sensing, and biomedical electronic systems foreseen.

Challenges Regarding IP Core Functional Reliability

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; LaBel, Kenneth A.

2017-01-01

For many years, intellectual property (IP) cores have been incorporated into field programmable gate array (FPGA) and application specific integrated circuit (ASIC) design flows. However, the usage of large complex IP cores were limited within products that required a high level of reliability. This is no longer the case. IP core insertion has become mainstream including their use in highly reliable products. Due to limited visibility and control, challenges exist when using IP cores and subsequently compromise product reliability. We discuss challenges and suggest potential solutions to critical application IP insertion.

Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits

NASA Technical Reports Server (NTRS)

1975-01-01

Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

Extremely Bendable, High-Performance Integrated Circuits Using Semiconducting Carbon Nanotube Networks for Digital, Analog, and Radio-Frequency Applications

DTIC Science & Technology

2012-02-07

circuits on mechanically flexible substrates for digital, analog and radio frequency applications. The asobtained thin-film transistors ( TFTs ) exhibit... flexible substrates for digital, analog and radio frequency applications. The as- obtained thin-film transistors ( TFTs ) exhibit highly uniform device...LCD) and organic light- emitting diode ( OLED ) displays lack the transparency and flexibility and are thus unsuitable for flexible electronic

Document analysis with neural net circuits

NASA Technical Reports Server (NTRS)

Graf, Hans Peter

1994-01-01

Document analysis is one of the main applications of machine vision today and offers great opportunities for neural net circuits. Despite more and more data processing with computers, the number of paper documents is still increasing rapidly. A fast translation of data from paper into electronic format is needed almost everywhere, and when done manually, this is a time consuming process. Markets range from small scanners for personal use to high-volume document analysis systems, such as address readers for the postal service or check processing systems for banks. A major concern with present systems is the accuracy of the automatic interpretation. Today's algorithms fail miserably when noise is present, when print quality is poor, or when the layout is complex. A common approach to circumvent these problems is to restrict the variations of the documents handled by a system. In our laboratory, we had the best luck with circuits implementing basic functions, such as convolutions, that can be used in many different algorithms. To illustrate the flexibility of this approach, three applications of the NET32K circuit are described in this short viewgraph presentation: locating address blocks, cleaning document images by removing noise, and locating areas of interest in personal checks to improve image compression. Several of the ideas realized in this circuit that were inspired by neural nets, such as analog computation with a low resolution, resulted in a chip that is well suited for real-world document analysis applications and that compares favorably with alternative, 'conventional' circuits.

Architecture of a general purpose embedded Slow-Control Adapter ASIC for future high-energy physics experiments

NASA Astrophysics Data System (ADS)

Gabrielli, Alessandro; Loddo, Flavio; Ranieri, Antonio; De Robertis, Giuseppe

2008-10-01

This work is aimed at defining the architecture of a new digital ASIC, namely Slow-Control Adapter (SCA), which will be designed in a commercial 130-nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics in future high-energy physics experiments. The GBT link provides a transparent transport layer between the SCA and control electronics in the counting room. The proposed SCA supports a variety of common bus protocols to interface with end-user general-purpose electronics. Between the GBT and the SCA a standard 100 Mb/s IEEE-802.3 compatible protocol will be implemented. This standard protocol allows off-line tests of the prototypes using commercial components that support the same standard. The project is justified because embedded applications in modern large HEP experiments require particular care to assure the lowest possible power consumption, still offering the highest reliability demanded by very large particle detectors.

Assessment of SOI Devices and Circuits at Extreme Temperatures

NASA Technical Reports Server (NTRS)

Elbuluk, Malik; Hammoud, Ahmad; Patterson, Richard L.

2007-01-01

Electronics designed for use in future NASA space exploration missions are expected to encounter extreme temperatures and wide thermal swings. Such missions include planetary surface exploration, bases, rovers, landers, orbiters, and satellites. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of mission. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical devices, circuits, and systems suitable for applications in deep space exploration missions and aerospace environment. Silicon-On-Insulator (SOI) technology has been under active consideration in the electronics industry for many years due to the advantages that it can provide in integrated circuit (IC) chips and computer processors. Faster switching, less power, radiationtolerance, reduced leakage, and high temp-erature capability are some of the benefits that are offered by using SOI-based devices. A few SOI circuits are available commercially. However, there is a noticeable interest in SOI technology for different applications. Very little data, however, exist on the performance of such circuits under cryogenic temperatures. In this work, the performance of SOI integrated circuits, evaluated under low temperature and thermal cycling, are reported. In particular, three examples of SOI circuits that have been tested for operation at low at temperatures are given. These circuits are SOI operational amplifiers, timers and power MOSFET drivers. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these circuits for use in space exploration missions at cryogenic temperatures. The findings are useful to mission planners and circuit designers so that proper selection of electronic parts can be made, and risk assessment can be established for such circuits for use in space missions.

Programmable dispersion on a photonic integrated circuit for classical and quantum applications.

PubMed

Notaros, Jelena; Mower, Jacob; Heuck, Mikkel; Lupo, Cosmo; Harris, Nicholas C; Steinbrecher, Gregory R; Bunandar, Darius; Baehr-Jones, Tom; Hochberg, Michael; Lloyd, Seth; Englund, Dirk

2017-09-04

We demonstrate a large-scale tunable-coupling ring resonator array, suitable for high-dimensional classical and quantum transforms, in a CMOS-compatible silicon photonics platform. The device consists of a waveguide coupled to 15 ring-based dispersive elements with programmable linewidths and resonance frequencies. The ability to control both quality factor and frequency of each ring provides an unprecedented 30 degrees of freedom in dispersion control on a single spatial channel. This programmable dispersion control system has a range of applications, including mode-locked lasers, quantum key distribution, and photon-pair generation. We also propose a novel application enabled by this circuit - high-speed quantum communications using temporal-mode-based quantum data locking - and discuss the utility of the system for performing the high-dimensional unitary optical transformations necessary for a quantum data locking demonstration.

Enabling complex genetic circuits to respond to extrinsic environmental signals.

PubMed

Hoynes-O'Connor, Allison; Shopera, Tatenda; Hinman, Kristina; Creamer, John Philip; Moon, Tae Seok

2017-07-01

Genetic circuits have the potential to improve a broad range of metabolic engineering processes and address a variety of medical and environmental challenges. However, in order to engineer genetic circuits that can meet the needs of these real-world applications, genetic sensors that respond to relevant extrinsic and intrinsic signals must be implemented in complex genetic circuits. In this work, we construct the first AND and NAND gates that respond to temperature and pH, two signals that have relevance in a variety of real-world applications. A previously identified pH-responsive promoter and a temperature-responsive promoter were extracted from the E. coli genome, characterized, and modified to suit the needs of the genetic circuits. These promoters were combined with components of the type III secretion system in Salmonella typhimurium and used to construct a set of AND gates with up to 23-fold change. Next, an antisense RNA was integrated into the circuit architecture to invert the logic of the AND gate and generate a set of NAND gates with up to 1168-fold change. These circuits provide the first demonstration of complex pH- and temperature-responsive genetic circuits, and lay the groundwork for the use of similar circuits in real-world applications. Biotechnol. Bioeng. 2017;114: 1626-1631. © 2017 Wiley Periodicals, Inc. © 2017 Wiley Periodicals, Inc.

Silicon millimetre-wave integrated-circuit (SIMMWIC) SPST switch

NASA Astrophysics Data System (ADS)

Stabile, P. J.; Rosen, A.

1984-10-01

The first silicon millimetre-wave integrated circuit (SIMMWIC) has been successfully fabricated. This circuit is a monolithic SPST switch with a 3 dB bandwidth of 20 percent and a minimum isolation of 21.6 dB across the band (centre frequency is 36.75 GHz). This monolithic circuit is a low-cost reproducible building block for all millimetre-wave control applications.

Overload protection circuit for output driver

DOEpatents

Stewart, Roger G.

1982-05-11

A protection circuit for preventing excessive power dissipation in an output transistor whose conduction path is connected between a power terminal and an output terminal. The protection circuit includes means for sensing the application of a turn on signal to the output transistor and the voltage at the output terminal. When the turn on signal is maintained for a period of time greater than a given period without the voltage at the output terminal reaching a predetermined value, the protection circuit decreases the turn on signal to, and the current conduction through, the output transistor.

On equivalent resistance of electrical circuits

NASA Astrophysics Data System (ADS)

Kagan, Mikhail

2015-01-01

While the standard (introductory physics) way of computing the equivalent resistance of nontrivial electrical circuits is based on Kirchhoff's rules, there is a mathematically and conceptually simpler approach, called the method of nodal potentials, whose basic variables are the values of the electric potential at the circuit's nodes. In this paper, we review the method of nodal potentials and illustrate it using the Wheatstone bridge as an example. We then derive a closed-form expression for the equivalent resistance of a generic circuit, which we apply to a few sample circuits. The result unveils a curious interplay between electrical circuits, matrix algebra, and graph theory and its applications to computer science. The paper is written at a level accessible by undergraduate students who are familiar with matrix arithmetic. Additional proofs and technical details are provided in appendices.

Neuromorphic Silicon Neuron Circuits

PubMed Central

Indiveri, Giacomo; Linares-Barranco, Bernabé; Hamilton, Tara Julia; van Schaik, André; Etienne-Cummings, Ralph; Delbruck, Tobi; Liu, Shih-Chii; Dudek, Piotr; Häfliger, Philipp; Renaud, Sylvie; Schemmel, Johannes; Cauwenberghs, Gert; Arthur, John; Hynna, Kai; Folowosele, Fopefolu; Saighi, Sylvain; Serrano-Gotarredona, Teresa; Wijekoon, Jayawan; Wang, Yingxue; Boahen, Kwabena

2011-01-01

Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips. PMID:21747754

A Survey of Memristive Threshold Logic Circuits.

PubMed

Maan, Akshay Kumar; Jayadevi, Deepthi Anirudhan; James, Alex Pappachen

2017-08-01

In this paper, we review different memristive threshold logic (MTL) circuits that are inspired from the synaptic action of the flow of neurotransmitters in the biological brain. The brainlike generalization ability and the area minimization of these threshold logic circuits aim toward crossing Moore's law boundaries at device, circuits, and systems levels. Fast switching memory, signal processing, control systems, programmable logic, image processing, reconfigurable computing, and pattern recognition are identified as some of the potential applications of MTL systems. The physical realization of nanoscale devices with memristive behavior from materials, such as TiO 2 , ferroelectrics, silicon, and polymers, has accelerated research effort in these application areas, inspiring the scientific community to pursue the design of high-speed, low-cost, low-power, and high-density neuromorphic architectures.

Cost optimization in low volume VLSI circuits

NASA Technical Reports Server (NTRS)

Cook, K. B., Jr.; Kerns, D. V., Jr.

1982-01-01

The relationship of integrated circuit (IC) cost to electronic system cost is developed using models for integrated circuit cost which are based on design/fabrication approach. Emphasis is on understanding the relationship between cost and volume for custom circuits suitable for NASA applications. In this report, reliability is a major consideration in the models developed. Results are given for several typical IC designs using off the shelf, full custom, and semicustom IC's with single and double level metallization.

Self-consistent radiation-based simulation of electric arcs: II. Application to gas circuit breakers

NASA Astrophysics Data System (ADS)

Iordanidis, A. A.; Franck, C. M.

2008-07-01

An accurate and robust method for radiative heat transfer simulation for arc applications was presented in the previous paper (part I). In this paper a self-consistent mathematical model based on computational fluid dynamics and a rigorous radiative heat transfer model is described. The model is applied to simulate switching arcs in high voltage gas circuit breakers. The accuracy of the model is proven by comparison with experimental data for all arc modes. The ablation-controlled arc model is used to simulate high current PTFE arcs burning in cylindrical tubes. Model accuracy for the lower current arcs is evaluated using experimental data on the axially blown SF6 arc in steady state and arc resistance measurements close to current zero. The complete switching process with the arc going through all three phases is also simulated and compared with the experimental data from an industrial circuit breaker switching test.

Inverter Circuits Using ZnO Nanoparticle Based Thin-Film Transistors for Flexible Electronic Applications

PubMed Central

Vidor, Fábio F.; Meyers, Thorsten; Hilleringmann, Ulrich

2016-01-01

Innovative systems exploring the flexibility and the transparency of modern semiconducting materials are being widely researched by the scientific community and by several companies. For a low-cost production and large surface area applications, thin-film transistors (TFTs) are the key elements driving the system currents. In order to maintain a cost efficient integration process, solution based materials are used as they show an outstanding tradeoff between cost and system complexity. In this paper, we discuss the integration process of ZnO nanoparticle TFTs using a high-k resin as gate dielectric. The performance in dependence on the transistor structure has been investigated, and inverted staggered setups depict an improved performance over the coplanar device increasing both the field-effect mobility and the ION/IOFF ratio. Aiming at the evaluation of the TFT characteristics for digital circuit applications, inverter circuits using a load TFT in the pull-up network and an active TFT in the pull-down network were integrated. The inverters show reasonable switching characteristics and V/V gains. Conjointly, the influence of the geometry ratio and the supply voltage on the devices have been analyzed. Moreover, as all integration steps are suitable to polymeric templates, the fabrication process is fully compatible to flexible substrates. PMID:28335282

Inverter Circuits Using ZnO Nanoparticle Based Thin-Film Transistors for Flexible Electronic Applications.

PubMed

Vidor, Fábio F; Meyers, Thorsten; Hilleringmann, Ulrich

2016-08-23

Innovative systems exploring the flexibility and the transparency of modern semiconducting materials are being widely researched by the scientific community and by several companies. For a low-cost production and large surface area applications, thin-film transistors (TFTs) are the key elements driving the system currents. In order to maintain a cost efficient integration process, solution based materials are used as they show an outstanding tradeoff between cost and system complexity. In this paper, we discuss the integration process of ZnO nanoparticle TFTs using a high- k resin as gate dielectric. The performance in dependence on the transistor structure has been investigated, and inverted staggered setups depict an improved performance over the coplanar device increasing both the field-effect mobility and the I ON / I OFF ratio. Aiming at the evaluation of the TFT characteristics for digital circuit applications, inverter circuits using a load TFT in the pull-up network and an active TFT in the pull-down network were integrated. The inverters show reasonable switching characteristics and V / V gains. Conjointly, the influence of the geometry ratio and the supply voltage on the devices have been analyzed. Moreover, as all integration steps are suitable to polymeric templates, the fabrication process is fully compatible to flexible substrates.

Teaching RLC Parallel Circuits in High-School Physics Class

ERIC Educational Resources Information Center

Simon, Alpár

2015-01-01

This paper will try to give an alternative treatment of the subject "parallel RLC circuits" and "resonance in parallel RLC circuits" from the Physics curricula for the XIth grade from Romanian high-schools, with an emphasis on practical type circuits and their possible applications, and intends to be an aid for both Physics…

Quantum-circuit refrigerator

NASA Astrophysics Data System (ADS)

Tan, Kuan Yen; Partanen, Matti; Lake, Russell E.; Govenius, Joonas; Masuda, Shumpei; Möttönen, Mikko

2017-05-01

Quantum technology promises revolutionizing applications in information processing, communications, sensing and modelling. However, efficient on-demand cooling of the functional quantum degrees of freedom remains challenging in many solid-state implementations, such as superconducting circuits. Here we demonstrate direct cooling of a superconducting resonator mode using voltage-controllable electron tunnelling in a nanoscale refrigerator. This result is revealed by a decreased electron temperature at a resonator-coupled probe resistor, even for an elevated electron temperature at the refrigerator. Our conclusions are verified by control experiments and by a good quantitative agreement between theory and experimental observations at various operation voltages and bath temperatures. In the future, we aim to remove spurious dissipation introduced by our refrigerator and to decrease the operational temperature. Such an ideal quantum-circuit refrigerator has potential applications in the initialization of quantum electric devices. In the superconducting quantum computer, for example, fast and accurate reset of the quantum memory is needed.

An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system.

PubMed

Fang, Wai-Chi; Huang, Kuan-Ju; Chou, Chia-Ching; Chang, Jui-Chung; Cauwenberghs, Gert; Jung, Tzyy-Ping

2014-01-01

This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.

Measuring User Similarity Using Electric Circuit Analysis: Application to Collaborative Filtering

PubMed Central

Yang, Joonhyuk; Kim, Jinwook; Kim, Wonjoon; Kim, Young Hwan

2012-01-01

We propose a new technique of measuring user similarity in collaborative filtering using electric circuit analysis. Electric circuit analysis is used to measure the potential differences between nodes on an electric circuit. In this paper, by applying this method to transaction networks comprising users and items, i.e., user–item matrix, and by using the full information about the relationship structure of users in the perspective of item adoption, we overcome the limitations of one-to-one similarity calculation approach, such as the Pearson correlation, Tanimoto coefficient, and Hamming distance, in collaborative filtering. We found that electric circuit analysis can be successfully incorporated into recommender systems and has the potential to significantly enhance predictability, especially when combined with user-based collaborative filtering. We also propose four types of hybrid algorithms that combine the Pearson correlation method and electric circuit analysis. One of the algorithms exceeds the performance of the traditional collaborative filtering by 37.5% at most. This work opens new opportunities for interdisciplinary research between physics and computer science and the development of new recommendation systems PMID:23145095

Measuring user similarity using electric circuit analysis: application to collaborative filtering.

PubMed

Yang, Joonhyuk; Kim, Jinwook; Kim, Wonjoon; Kim, Young Hwan

2012-01-01

We propose a new technique of measuring user similarity in collaborative filtering using electric circuit analysis. Electric circuit analysis is used to measure the potential differences between nodes on an electric circuit. In this paper, by applying this method to transaction networks comprising users and items, i.e., user-item matrix, and by using the full information about the relationship structure of users in the perspective of item adoption, we overcome the limitations of one-to-one similarity calculation approach, such as the Pearson correlation, Tanimoto coefficient, and Hamming distance, in collaborative filtering. We found that electric circuit analysis can be successfully incorporated into recommender systems and has the potential to significantly enhance predictability, especially when combined with user-based collaborative filtering. We also propose four types of hybrid algorithms that combine the Pearson correlation method and electric circuit analysis. One of the algorithms exceeds the performance of the traditional collaborative filtering by 37.5% at most. This work opens new opportunities for interdisciplinary research between physics and computer science and the development of new recommendation systems.

Energy and Timing Measurement with Time-Based Detector Readout for PET Applications: Principle and Validation with Discrete Circuit Components

PubMed Central

Sun, Xishan; Lan, Allan K.; Bircher, Chad; Deng, Zhi; Liu, Yinong; Shao, Yiping

2011-01-01

A new signal processing method for PET application has been developed, with discrete circuit components to measure energy and timing of a gamma interaction based solely on digital timing processing without using an amplitude-to-digital convertor (ADC) or a constant fraction discriminator (CFD). A single channel discrete component time-based readout (TBR) circuit was implemented in a PC board. Initial circuit functionality and performance evaluations have been conducted. Accuracy and linearity of signal amplitude measurement were excellent, as measured with test pulses. The measured timing accuracy from test pulses reached to less than 300 ps, a value limited mainly by the timing jitter of the prototype electronics circuit. Both suitable energy and coincidence timing resolutions (~18% and ~1.0 ns) have been achieved with 3 × 3 × 20 mm3 LYSO scintillator and photomultiplier tube-based detectors. With its relatively simple circuit and low cost, TBR is expected to be a suitable front-end signal readout electronics for compact PET or other radiation detectors requiring the reading of a large number of detector channels and demanding high performance for energy and timing measurement. PMID:21743761

An equivalent circuit model of supercapacitors for applications in wireless sensor networks

NASA Astrophysics Data System (ADS)

Yang, Hengzhao; Zhang, Ying

2011-04-01

Energy harvesting technologies have been extensively researched to develop long-lived wireless sensor networks. To better utilize the harvested energy, various energy storage systems are proposed. A simple circuit model is developed to describe supercapacitor behavior, which uses two resistor-capacitor branches with different time constants to characterize the charging and redistribution processes, and a variable leakage resistance (VLR) to characterize the self-discharge process. The voltage and temperature dependence of the VLR values is also discussed. Results show that the VLR model is more accurate than the energy recursive equation (ERE) models for short term wireless sensor network applications.

Sour Ageusia in Two Individuals Implicates Ion Channels of the ASIC and PKD Families in Human Sour Taste Perception at the Anterior Tongue

PubMed Central

Huque, Taufiqul; Cowart, Beverly J.; Dankulich-Nagrudny, Luba; Pribitkin, Edmund A.; Bayley, Douglas L.; Spielman, Andrew I.; Feldman, Roy S.; Mackler, Scott A.; Brand, Joseph G.

2009-01-01

Background The perception of sour taste in humans is incompletely understood at the receptor cell level. We report here on two patients with an acquired sour ageusia. Each patient was unresponsive to sour stimuli, but both showed normal responses to bitter, sweet, and salty stimuli. Methods and Findings Lingual fungiform papillae, containing taste cells, were obtained by biopsy from the two patients, and from three sour-normal individuals, and analyzed by RT-PCR. The following transcripts were undetectable in the patients, even after 50 cycles of amplification, but readily detectable in the sour-normal subjects: acid sensing ion channels (ASICs) 1a, 1β, 2a, 2b, and 3; and polycystic kidney disease (PKD) channels PKD1L3 and PKD2L1. Patients and sour-normals expressed the taste-related phospholipase C-β2, the δ-subunit of epithelial sodium channel (ENaC) and the bitter receptor T2R14, as well as β-actin. Genomic analysis of one patient, using buccal tissue, did not show absence of the genes for ASIC1a and PKD2L1. Immunohistochemistry of fungiform papillae from sour-normal subjects revealed labeling of taste bud cells by antibodies to ASICs 1a and 1β, PKD2L1, phospholipase C-β2, and δ-ENaC. An antibody to PKD1L3 labeled tissue outside taste bud cells. Conclusions These data suggest a role for ASICs and PKDs in human sour perception. This is the first report of sour ageusia in humans, and the very existence of such individuals (“natural knockouts”) suggests a cell lineage for sour that is independent of the other taste modalities. PMID:19812697

Characteristics of Radio-Frequency Circuits Utilizing Ferroelectric Capacitors

NASA Technical Reports Server (NTRS)

Eskridge, Michael; Gui, Xiao; MacLeod, Todd; Ho, Fat D.

2011-01-01

Ferroelectric capacitors, most commonly used in memory circuits and variable components, were studied in simple analog radio-frequency circuits such as the RLC resonator and Colpitts oscillator. The goal was to characterize the RF circuits in terms of frequency of oscillation, gain, etc, using ferroelectric capacitors. Frequencies of oscillation of both circuits were measured and studied a more accurate resonant frequency can be obtained using the ferroelectric capacitors. Many experiments were conducted and data collected. A model to simulate the experimental results will be developed. Discrepancies in gain and frequency in these RF circuits when conventional capacitors are replaced with ferroelectric ones were studied. These results will enable circuit designers to anticipate the effects of using ferroelectric components in their radio- frequency applications.

A 64ch readout module for PPD/MPPC/SiPM using EASIROC ASIC

NASA Astrophysics Data System (ADS)

Nakamura, Isamu; Ishijima, N.; Hanagaki, K.; Yoshimura, K.; Nakai, Y.; Ueno, K.

2015-07-01

A readout module for PPD/MPPC/GAPD/SiPM is developed using EASIROC ASIC. The module can handle 64 PPDs and has on-board bias power supply, ADC for energy measurement, 1 ns TDC on FPGA as well as 64ch Logic output for external trigger. Controls and data transfer are through SiTCP technology implemented in FPGA. The module has NIM format for convenience, but can be operated without crate with 5 V AC/DC converter. Basic performance of production module was tested and the results are presented in the poster.

Principles of Genetic Circuit Design

PubMed Central

Brophy, Jennifer A.N.; Voigt, Christopher A.

2014-01-01

Cells are able to navigate environments, communicate, and build complex patterns by initiating gene expression in response to specific signals. Engineers need to harness this capability to program cells to perform tasks or build chemicals and materials that match the complexity seen in nature. This review describes new tools that aid the construction of genetic circuits. We show how circuit dynamics can be influenced by the choice of regulators and changed with expression “tuning knobs.” We collate the failure modes encountered when assembling circuits, quantify their impact on performance, and review mitigation efforts. Finally, we discuss the constraints that arise from operating within a living cell. Collectively, better tools, well-characterized parts, and a comprehensive understanding of how to compose circuits are leading to a breakthrough in the ability to program living cells for advanced applications, from living therapeutics to the atomic manufacturing of functional materials. PMID:24781324

Ultrascalable petaflop parallel supercomputer

DOEpatents

Blumrich, Matthias A [Ridgefield, CT; Chen, Dong [Croton On Hudson, NY; Chiu, George [Cross River, NY; Cipolla, Thomas M [Katonah, NY; Coteus, Paul W [Yorktown Heights, NY; Gara, Alan G [Mount Kisco, NY; Giampapa, Mark E [Irvington, NY; Hall, Shawn [Pleasantville, NY; Haring, Rudolf A [Cortlandt Manor, NY; Heidelberger, Philip [Cortlandt Manor, NY; Kopcsay, Gerard V [Yorktown Heights, NY; Ohmacht, Martin [Yorktown Heights, NY; Salapura, Valentina [Chappaqua, NY; Sugavanam, Krishnan [Mahopac, NY; Takken, Todd [Brewster, NY

2010-07-20

A massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. The use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.

Design of the Wind Tunnel Model Communication Controller Board. Degree awarded by Christopher Newport Univ. on Dec. 1998

NASA Technical Reports Server (NTRS)

Wilson, William C.

1999-01-01

The NASA Langley Research Center's Wind Tunnel Reinvestment project plans to shrink the existing data acquisition electronics to fit inside a wind tunnel model. Space limitations within a model necessitate a distributed system of Application Specific Integrated Circuits (ASICs) rather than a centralized system based on PC boards. This thesis will focus on the design of the prototype of the communication Controller board. A portion of the communication Controller board is to be used as the basis of an ASIC design. The communication Controller board will communicate between the internal model modules and the external data acquisition computer. This board is based around an Field Programmable Gate Array (FPGA), to allow for reconfigurability. In addition to the FPGA, this board contains buffer Random Access Memory (RAM), configuration memory (EEPROM), drivers for the communications ports, and passive components.

Development of Formulations for a-SiC and Manganese CMP and Post-CMP Cleaning of Cobalt

NASA Astrophysics Data System (ADS)

Lagudu, Uma Rames Krishna

We have investigated the chemical mechanical polishing (CMP) of amorphous SiC (a-SiC) and Mn and Post CMP cleaning of cobalt for various device applications. During the manufacture of copper interconnects using the damascene process the polishing of copper is followed by the polishing of the barrier material (Co, Mn, Ru and their alloys) and its post CMP cleaning. This is followed by the a-SiC hard mask CMP. Silicon carbide thin films, though of widespread use in microelectronic engineering, are difficult to process by CMP because of their hardness and chemical inertness. The earlier part of the SiC work discusses the development of slurries based on silica abrasives that resulted in high a-SiC removal rates (RRs). The ionic strength of the silica dispersion was found to play a significant role in enhancing material removal rate, while also providing very good post-polish surface-smoothness. For example, the addition of 50 mM potassium nitrate to a pH 8 aqueous slurry consisting of 10 wt % of silica abrasives and 1.47 M hydrogen peroxide increased the RR from about 150 nm/h to about 2100 nm/h. The role of ionic strength in obtaining such high RRs was investigated using surface zeta-potentials measurements and X-ray photoelectron spectroscopy (XPS). Evidently, hydrogen peroxide promoted the oxidation of Si and C to form weakly adhered species that were subsequently removed by the abrasive action of the silica particles. The effect of potassium nitrate in increasing material removal is attributed to the reduction in the electrostatic repulsion between the abrasive particles and the SiC surface because of screening of surface charges by the added electrolyte. We also show that transition metal compounds when used as additives to silica dispersions enhance a-SiC removal rates (RRs). Silica slurries containing potassium permanganate gave RRs as high as 2000 nm/h at pH 4. Addition of copper sulfate to this slurry further enhanced the RRs to ˜3500 nm/h at pH 6

Foldable graphene electronic circuits based on paper substrates.

PubMed

Hyun, Woo Jin; Park, O Ok; Chin, Byung Doo

2013-09-14

Graphene electronic circuits are prepared on paper substrates by using graphene nanoplates and applied to foldable paper-based electronics. The graphene circuits show a small change in conductance under various folding angles and maintain an electronic path on paper substrates after repetition of folding and unfolding. Foldable paper-based applications with graphene circuits exhibit excellent folding stability. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Circuits Protect Against Incorrect Power Connections

NASA Technical Reports Server (NTRS)

Delombard, Richard

1992-01-01

Simple circuits prevent application of incorrectly polarized or excessive voltages. Connected temporarily or permanently at power-connecting terminals. Devised to protect electrical and electronic equipment installed in spacecraft and subjected to variety of tests in different facilities prior to installation. Basic concept of protective circuits also applied easily to many kinds of electrical and electronic equipment that must be protected against incorrect power connections.

BOREHOLE FLOWMETERS: FIELD APPLICATION AND DATA ANALYSIS

EPA Science Inventory

This paper reviews application of borehole flowmeters in granular and fractured rocks. asic data obtained in the field are the ambient flow log and the pumping-induced flow log. hese basic logs may then be used to calculate other quantities of interest. he paper describes the app...

Enzyme-based logic gates and circuits-analytical applications and interfacing with electronics.

PubMed

Katz, Evgeny; Poghossian, Arshak; Schöning, Michael J

2017-01-01

The paper is an overview of enzyme-based logic gates and their short circuits, with specific examples of Boolean AND and OR gates, and concatenated logic gates composed of multi-step enzyme-biocatalyzed reactions. Noise formation in the biocatalytic reactions and its decrease by adding a "filter" system, converting convex to sigmoid response function, are discussed. Despite the fact that the enzyme-based logic gates are primarily considered as components of future biomolecular computing systems, their biosensing applications are promising for immediate practical use. Analytical use of the enzyme logic systems in biomedical and forensic applications is discussed and exemplified with the logic analysis of biomarkers of various injuries, e.g., liver injury, and with analysis of biomarkers characteristic of different ethnicity found in blood samples on a crime scene. Interfacing of enzyme logic systems with modified electrodes and semiconductor devices is discussed, giving particular attention to the interfaces functionalized with signal-responsive materials. Future perspectives in the design of the biomolecular logic systems and their applications are discussed in the conclusion. Graphical Abstract Various applications and signal-transduction methods are reviewed for enzyme-based logic systems.

Programmable Low-Voltage Circuit Breaker and Tester

NASA Technical Reports Server (NTRS)

Greenfield, Terry

2008-01-01

An instrumentation system that would comprise a remotely controllable and programmable low-voltage circuit breaker plus several electric-circuit-testing subsystems has been conceived, originally for use aboard a spacecraft during all phases of operation from pre-launch testing through launch, ascent, orbit, descent, and landing. The system could also be adapted to similar use aboard aircraft. In comparison with remotely controllable circuit breakers heretofore commercially available, this system would be smaller, less massive, and capable of performing more functions, as needed for aerospace applications.

Single Event Effects Test Results for the Actel ProASIC Plus and Altera Stratix-II Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory R.; Swift, Gary M.

2006-01-01

This work describes radiation testing of Actel's ProASIC Plus and Altera's Stratix-II FPGAs. The Actel Device Under Test (DUT) was a ProASIC Plus APA300-PQ208 nonvolatile, field reprogrammable device which is based on a 0.22micron flash-based LVCMOS technology. Limited investigation has taken place into flash based FPGA technologies, therefore this test served as a preliminary reference point for various SEE behaviors. The Altera DUT was a Stratix-II EP2S60F1020C4. Single Event Upset (SEU) and Single Event Latchup (SEL) were the focus of these studies. For the Actel, a latchup test was done at an effective LET of 75.0 MeV-sq cm/mg at room temperature, and no latchup was detected when irradiated to a total fluence of 1 x 10(exp 7) particles/sq cm. The Altera part was shown to latchup at room temperature.

γEpithelial Na(+) Channel (γENaC) and the Acid-Sensing Ion Channel 1 (ASIC1) expression in the urothelium of patients with neurogenic detrusor overactivity.

PubMed

Traini, Chiara; Del Popolo, Giulio; Lazzeri, Massimo; Mazzaferro, Katia; Nelli, Federico; Calosi, Laura; Vannucchi, Maria Giuliana

2015-11-01

To investigate the expression of two types of cation channels, γEpithelial Na(+) Channel (γENaC) and the Acid-Sensing Ion Channel 1 (ASIC1), in the urothelium of controls and in patients affected by neurogenic detrusor overactivity (NDO). In parallel, urodynamic parameters were collected and correlated to the immunohistochemical results. Four controls and 12 patients with a clinical diagnosis of NDO and suprasacral spinal cord lesion underwent urodynamic measurements and cystoscopy. Cold-cup biopsies were frozen and processed for immunohistochemistry and Western Blot. Spearman's correlation coefficient between morphological and urodynamic data was applied. One-way anova followed by Newman-Keuls multiple comparison post hoc test was applied for Western Blot results. In the controls, γENaC and ASIC1 were expressed in the urothelium with differences in their cell distribution and intensity. In patients with NDO, both markers showed consistent changes either in cell distribution and labelling intensity compared with the controls. A significant correlation between a higher intensity of γENaC expression in the urothelium of patients with NDO and lower values of bladder compliance was detected. The present findings show important changes in the expression of γENaC and ASIC1 in NDO human urothelium. Notably, while the changes in γENaC might impair the mechanosensory function of the urothelium, the increase of ASIC1 might represent an attempt to compensate for the excess in local sensitivity. © 2014 The Authors BJU International © 2014 BJU International Published by John Wiley & Sons Ltd.

Commutation circuit for an HVDC circuit breaker

DOEpatents

Premerlani, William J.

1981-01-01

A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.

Commutation circuit for an HVDC circuit breaker

DOEpatents

Premerlani, W.J.

1981-11-10

A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components. 13 figs.

Creating single-copy genetic circuits

PubMed Central

Lee, Jeong Wook; Gyorgy, Andras; Cameron, D. Ewen; Pyenson, Nora; Choi, Kyeong Rok; Way, Jeffrey C.; Silver, Pamela A.; Del Vecchio, Domitilla; Collins, James J.

2017-01-01

SUMMARY Synthetic biology is increasingly used to develop sophisticated living devices for basic and applied research. Many of these genetic devices are engineered using multi-copy plasmids, but as the field progresses from proof-of-principle demonstrations to practical applications, it is important to develop single-copy synthetic modules that minimize consumption of cellular resources and can be stably maintained as genomic integrants. Here we use empirical design, mathematical modeling and iterative construction and testing to build single-copy, bistable toggle switches with improved performance and reduced metabolic load that can be stably integrated into the host genome. Deterministic and stochastic models led us to focus on basal transcription to optimize circuit performance and helped to explain the resulting circuit robustness across a large range of component expression levels. The design parameters developed here provide important guidance for future efforts to convert functional multi-copy gene circuits into optimized single-copy circuits for practical, real-world use. PMID:27425413

Cancellation Circuit for Transmit-Receive Isolation

DTIC Science & Technology

2010-09-01

non -ideal hardware, and the performance of the circuit is limited. One of the major problems is the leakage from the circulator. The leakage disrupts...cancellation circuit was investigated by a series of simulations using Agilent ADS (Agilent Advanced Design System), and hardware tests were conducted to...developed in the WDDPA application, allowing coherent processing of the data from all elements. There are limitations encountered due to non -ideal

Printed Graphene Derivative Circuits as Passive Electrical Filters

PubMed Central

Sinar, Dogan

2018-01-01

The objective of this study is to inkjet print resistor-capacitor (RC) low pass electrical filters, using a novel water-based cellulose graphene ink, and compare the voltage-frequency and transient behavior to equivalent circuits constructed from discrete passive components. The synthesized non-toxic graphene-carboxymethyl cellulose (G-CMC) ink is deposited on mechanically flexible polyimide substrates using a customized printer that dispenses functionalized aqueous solutions. The design of the printed first-order and second-order low-pass RC filters incorporate resistive traces and interdigitated capacitors. Low pass filter characteristics, such as time constant, cut-off frequency and roll-off rate, are determined for comparative analysis. Experiments demonstrate that for low frequency applications (<100 kHz) the printed graphene derivative circuits performed as well as the circuits constructed from discrete resistors and capacitors for both low pass filter and RC integrator applications. The impact of mechanical stress due to bending on the electrical performance of the flexible printed circuits is also investigated. PMID:29473890

Printed Graphene Derivative Circuits as Passive Electrical Filters.

PubMed

Sinar, Dogan; Knopf, George K

2018-02-23

The objective of this study is to inkjet print resistor-capacitor ( RC ) low pass electrical filters, using a novel water-based cellulose graphene ink, and compare the voltage-frequency and transient behavior to equivalent circuits constructed from discrete passive components. The synthesized non-toxic graphene-carboxymethyl cellulose (G-CMC) ink is deposited on mechanically flexible polyimide substrates using a customized printer that dispenses functionalized aqueous solutions. The design of the printed first-order and second-order low-pass RC filters incorporate resistive traces and interdigitated capacitors. Low pass filter characteristics, such as time constant, cut-off frequency and roll-off rate, are determined for comparative analysis. Experiments demonstrate that for low frequency applications (<100 kHz) the printed graphene derivative circuits performed as well as the circuits constructed from discrete resistors and capacitors for both low pass filter and RC integrator applications. The impact of mechanical stress due to bending on the electrical performance of the flexible printed circuits is also investigated.

Selection of wires and circuit protective devices for STS Orbiter vehicle payload electrical circuits

NASA Technical Reports Server (NTRS)

Gaston, Darilyn M.

1991-01-01

Electrical designers of Orbiter payloads face the challenge of determining proper circuit protection/wire size parameters to satisfy Orbiter engineering and safety requirements. This document is the result of a program undertaken to review test data from all available aerospace sources and perform additional testing to eliminate extrapolation errors. The resulting compilation of data was used to develop guidelines for the selection of wire sizes and circuit protection ratings. The purpose is to provide guidance to the engineering to ensure a design which meets Orbiter standards and which should be applicable to any aerospace design.

Fast, Low-Power, Hysteretic Level-Detector Circuit

NASA Technical Reports Server (NTRS)

Arditti, Mordechai

1993-01-01

Circuit for detection of preset levels of voltage or current intended to replace standard fast voltage comparator. Hysteretic analog/digital level detector operates at unusually low power with little sacrifice of speed. Comprises low-power analog circuit and complementary metal oxide/semiconductor (CMOS) digital circuit connected in overall closed feedback loop to decrease rise and fall times, provide hysteresis, and trip-level control. Contains multiple subloops combining linear and digital feedback. Levels of sensed signals and hysteresis level easily adjusted by selection of components to suit specific application.

Microwave integrated circuit for Josephson voltage standards

NASA Technical Reports Server (NTRS)

Holdeman, L. B.; Toots, J.; Chang, C. C. (Inventor)

1980-01-01

A microwave integrated circuit comprised of one or more Josephson junctions and short sections of microstrip or stripline transmission line is fabricated from thin layers of superconducting metal on a dielectric substrate. The short sections of transmission are combined to form the elements of the circuit and particularly, two microwave resonators. The Josephson junctions are located between the resonators and the impedance of the Josephson junctions forms part of the circuitry that couples the two resonators. The microwave integrated circuit has an application in Josephson voltage standards. In this application, the device is asymmetrically driven at a selected frequency (approximately equal to the resonance frequency of the resonators), and a d.c. bias is applied to the junction. By observing the current voltage characteristic of the junction, a precise voltage, proportional to the frequency of the microwave drive signal, is obtained.

Logic circuits from zero forcing.

PubMed

Burgarth, Daniel; Giovannetti, Vittorio; Hogben, Leslie; Severini, Simone; Young, Michael

We design logic circuits based on the notion of zero forcing on graphs; each gate of the circuits is a gadget in which zero forcing is performed. We show that such circuits can evaluate every monotone Boolean function. By using two vertices to encode each logical bit, we obtain universal computation. We also highlight a phenomenon of "back forcing" as a property of each function. Such a phenomenon occurs in a circuit when the input of gates which have been already used at a given time step is further modified by a computation actually performed at a later stage. Finally, we show that zero forcing can be also used to implement reversible computation. The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity. Moreover, in the light of applications of zero forcing in quantum mechanics, the link with Boolean functions may suggest a new directions in quantum control theory and in the study of engineered quantum spin systems. It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.

180-GHz Interferometric Imager

NASA Technical Reports Server (NTRS)

Kangaslahti, Pekka P.; Lim, Boon H.; O'Dwyer, Ian J.; Soria, Mary M.; Owen, Heather R.; Gaier, Todd C.; Lambrigtsen, Bjorn, H.; Tanner, Alan B.; Ruf, Christopher

2011-01-01

A 180-GHz interferometric imager uses compact receiver modules, combined high- and low-gain antennas, and ASIC (application specific integrated circuit) correlator technology, enabling continuous, all-weather observations of water vapor with 25-km resolution and 0.3-K noise in 15 minutes of observation for numerical weather forecasting and tropical storm prediction. The GeoSTAR-II prototype instrument is broken down into four major subsystems: the compact, low-noise receivers; sub-array modules; IF signal distribution; and the digitizer/correlator. Instead of the single row of antennas adopted in GeoSTAR, this version has four rows of antennas on a coarser grid. This dramatically improves the sensitivity in the desired field of view. The GeoSTAR-II instrument is a 48-element, synthetic, thinned aperture radiometer operating at 165-183 GHz. The instrument has compact receivers integrated into tiles of 16 elements in a 4x4 arrangement. These tiles become the building block of larger arrays. The tiles contain signal distribution for bias controls, IF signal, and local oscillator signals. The IF signals are digitized and correlated using an ASIC correlator to minimize power consumption. Previous synthetic aperture imagers have used comparatively large multichip modules, whereas this approach uses chip-scale modules mounted on circuit boards, which are in turn mounted on the distribution manifolds. This minimizes the number of connectors and reduces system mass. The use of ASIC technology in the digitizers and correlators leads to a power reduction close to an order of magnitude.

SVGA and XGA LCOS microdisplays for HMD applications

NASA Astrophysics Data System (ADS)

Bolotski, Michael; Alvelda, Phillip

1999-07-01

MicroDisplay liquid crystal on silicon (LCOS) display devices are based on a combination of technologies combined with the extreme integration capability of conventionally fabricated CMOS substrates. Two recent SVGA (800 X 600) pixel resolution designs were demonstrated based on 10 micron and 12.5-micron pixel pitch architectures. The resulting microdisplays measure approximately 10 mm and 12 mm in diagonal respectively. Further, an XGA (1024 X 768) resolution display fabricated with a 12.5-micron pixel pitch with a 16-mm diagonal was also demonstrated. Both the larger SVGA and the XGA design were based on the same 12.5-micron pixel-pitch design, demonstrating a quickly scalable design architecture for rapid prototyping life-cycles. All three microdisplay designs described above function in grayscale and high-performance Field-Sequential-Color (FSC) operating modes. The fast liquid crystal operating modes and new scalable high- performance pixel addressing architectures presented in this paper enable substantially improved color, contrast, and brightness while still satisfying the optical, packaging, and power requirements of portable commercial and defense applications including ultra-portable helmet, eyeglass, and heat-mounted systems. The entire suite of The MicroDisplay Corporation's technologies was devised to create a line of mixed-signal application-specific integrated circuits (ASIC) in single-chip display systems. Mixed-signal circuits can integrate computing, memory, and communication circuitry on the same substrate as the display drivers and pixel array for a multifunctional complete system-on-a-chip. For helmet and head-mounted displays this can include capabilities such as the incorporation of customized symbology and information storage directly on the display substrate. System-on-a-chip benefits also include reduced head supported weight requirements through the elimination of off-chip drive electronics.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vernon, E.; De Geronimo, G.; Ackley, K.

We report on the development of an application specific integrated circuit (ASIC) for 3D position sensitive detectors (3D PSD). The ASIC is designed to operate with pixelated wide bandgap sensors like Cadmium-Zinc-Telluride (CZT), Mercuric Iodide (Hgl2) and Thallium Bromide (TIBr). It measures the amplitudes and timings associated with an ionizing event on 128 anodes, the anode grid, and the cathode. Each channel provides low-noise charge amplification, high-order shaping with peaking time adjustable from 250 ns to 12 {micro}s, gain adjustable to 20 mV/fC or 120 mV/fC (for a dynamic range of 3.2 MeV and 530 keV in CZT), amplitude discriminationmore » with 5-bit trimming, and positive and negative peak and timing detections. The readout can be full or sparse, based on a flag and single- or multi-cycle token passing. All channels, triggered channels only, or triggered with neighbors can be read out thus increasing the rate capability of the system to more than 10 kcps. The ASIC dissipates 330 mW which corresponds to about 2.5 mW per channel.« less

ELECTRONIC PHASE CONTROL CIRCUIT

DOEpatents

Salisbury, J.D.; Klein, W.W.; Hansen, C.F.

1959-04-21

An electronic circuit is described for controlling the phase of radio frequency energy applied to a multicavity linear accelerator. In one application of the circuit two cavities are excited from a single radio frequency source, with one cavity directly coupled to the source and the other cavity coupled through a delay line of special construction. A phase detector provides a bipolar d-c output signal proportional to the difference in phase between the voltage in the two cavities. This d-c signal controls a bias supply which provides a d-c output for varying the capacitnce of voltage sensitive capacitors in the delay line. The over-all operation of the circuit is completely electronic, overcoming the time response limitations of the electromechanical control systems, and the relative phase relationship of the radio frequency voltages in the two caviiies is continuously controlled to effect particle acceleration.

Configurable test bed design for nanosats to qualify commercial and customized integrated circuits

NASA Astrophysics Data System (ADS)

Guareschi, W.; Azambuja, J.; Kastensmidt, F.; Reis, R.; Durao, O.; Schuch, N.; Dessbesel, G.

The use of small satellites has increased substantially in recent years due to the reduced cost of their development and launch, as well to the flexibility offered by commercial components. The test bed is a platform that allows components to be evaluated and tested in space. It is a flexible platform, which can be adjusted to a wide quantity of components and interfaces. This work proposes the design and implementation of a test bed suitable for test and evaluation of commercial circuits used in nanosatellites. The development of such a platform allows developers to reduce the efforts in the integration of components and therefore speed up the overall system development time. The proposed test bed is a configurable platform implemented using a Field Programmable Gate Array (FPGA) that controls the communication protocols and connections to the devices under test. The Flash-based ProASIC3E FPGA from Microsemi is used as a control system. This adaptive system enables the control of new payloads and softcores for test and validation in space. Thus, the integration can be easily performed through configuration parameters. It is intended for modularity. Each component connected to the test bed can have a specific interface programmed using a hardware description language (HDL). The data of each component is stored in embedded memories. Each component has its own memory space. The size of the allocated memory can be also configured. The data transfer priority can be set and packaging can be added to the logic, when needed. Communication with peripheral devices and with the Onboard Computer (OBC) is done through the pre-implemented protocols, such as I2C (Inter-Integrated Circuit), SPI (Serial Peripheral Interface) and external memory control. In loco primary tests demonstrated the control system's functionality. The commercial ProASIC3E FPGA family is not space-flight qualified, but tests have been made under Total Ionizing Dose (TID) showing its robustness up to 25 kr

Radiation Hardened Structured ASIC Platform with Compensation of Delay for Temperature and Voltage Variations for Multiple Redundant Temporal Voting Latch Technology

NASA Technical Reports Server (NTRS)

Ardalan, Sasan (Inventor)

2018-01-01

The invention relates to devices and methods of maintaining the current starved delay at a constant value across variations in voltage and temperature to increase the speed of operation of the sequential logic in the radiation hardened ASIC design.

CHEETAH: circuit-switched high-speed end-to-end transport architecture

NASA Astrophysics Data System (ADS)

Veeraraghavan, Malathi; Zheng, Xuan; Lee, Hyuk; Gardner, M.; Feng, Wuchun

2003-10-01

Leveraging the dominance of Ethernet in LANs and SONET/SDH in MANs and WANs, we propose a service called CHEETAH (Circuit-switched High-speed End-to-End Transport ArcHitecture). The service concept is to provide end hosts with high-speed, end-to-end circuit connectivity on a call-by-call shared basis, where a "circuit" consists of Ethernet segments at the ends that are mapped into Ethernet-over-SONET long-distance circuits. This paper focuses on the file-transfer application for such circuits. For this application, the CHEETAH service is proposed as an add-on to the primary Internet access service already in place for enterprise hosts. This allows an end host that is sending a file to first attempt setting up an end-to-end Ethernet/EoS circuit, and if rejected, fall back to the TCP/IP path. If the circuit setup is successful, the end host will enjoy a much shorter file-transfer delay than on the TCP/IP path. To determine the conditions under which an end host with access to the CHEETAH service should attempt circuit setup, we analyze mean file-transfer delays as a function of call blocking probability in the circuit-switched network, probability of packet loss in the IP network, round-trip times, link rates, and so on.

The use of low resistivity substrates for optimal noise reduction, ground referencing, and current conduction in mixed signal ASICs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zimmerman, T.

1997-12-01

This paper is distilled from a talk given at the 3rd International Meeting on Front End Electronics in Taos, N.M. on Nov. 7,1997. It is based on experience gained by designing and testing the SVX3 128 channel silicon strip detector readout chip. The SVX3 chip organization is shown in Fig. 1. The Front End section consists of an integrator and analog pipeline designed at Fermilab, and the Back End section is an ADC plus sparsification and readout logic designed at LBL. SVX3 is a deadtimeless readout chip, which means that the front end is acquiring low level analog signals whilemore » the back end is digitizing and reading out digital signals. It is thus a true mixed signal chip, and demands close attention to avoid disastrous coupling from the digital to the analog sections. SVX3 is designed in a bulk CMOS process (i.e., the circuits sit in a silicon substrate). In such a process, the substrate becomes a potential coupling path. This paper discusses the effect of the substrate resistivity on coupling, and also goes into a more general discussion of grounding and referencing in mixed signal designs and how low resistivity substrates can be used to advantage. Finally, an alternative power supply current conduction method for ASICs is presented as an additional advantage which can be obtained with low resistivity substrates. 1 ref., 13 figs., 1 tab.« less

Active shunt capacitance cancelling oscillator circuit

DOEpatents

Wessendorf, Kurt O.

2003-09-23

An oscillator circuit is disclosed which can be used to produce oscillation using a piezoelectric crystal, with a frequency of oscillation being largely independent of any shunt capacitance associated with the crystal (i.e. due to electrodes on the surfaces of the crystal and due to packaging and wiring for the crystal). The oscillator circuit is based on a tuned gain stage which operates the crystal at a frequency, f, near a series resonance frequency, f.sub.S. The oscillator circuit further includes a compensation circuit that supplies all the ac current flow through the shunt resistance associated with the crystal so that this ac current need not be supplied by the tuned gain stage. The compensation circuit uses a current mirror to provide the ac current flow based on the current flow through a reference capacitor that is equivalent to the shunt capacitance associated with the crystal. The oscillator circuit has applications for driving piezoelectric crystals for sensing of viscous, fluid or solid media by detecting a change in the frequency of oscillation of the crystal and a resonator loss which occur from contact of an exposed surface of the crystal by the viscous, fluid or solid media.

30 CFR 75.800 - High-voltage circuits; circuit breakers.

Code of Federal Regulations, 2010 CFR

2010-07-01

... shall be equipped with devices to provide protection against under-voltage grounded phase, short circuit... 30 Mineral Resources 1 2010-07-01 2010-07-01 false High-voltage circuits; circuit breakers. 75.800... § 75.800 High-voltage circuits; circuit breakers. [Statutory Provisions] High-voltage circuits entering...

Antagonists to TRPV1, ASICs and P2X have a potential role to prevent the triggering of regional bone metabolic disorder and pain-like behavior in tail-suspended mice.

PubMed

Hanaka, Megumi; Iba, Kousuke; Dohke, Takayuki; Kanaya, Kumiko; Okazaki, Shunichiro; Yamashita, Toshihiko

2018-05-01

Our recent studies demonstrated that regional bone loss in the unloaded hind limbs of tail-suspended mice triggered pain-like behaviors due to the acidic environment in the bone induced by osteoclast activation. The aims of the present study were to examine whether TRPV1, ASIC and P2X (known as nociceptors) are expressed in bone, and whether the antagonists to those receptors affect the expression of osteoblast and osteoclast regulators, and prevent the triggering of not only pain-like behaviors but also high bone turnover conditions in tail-suspension model mice. The hind limb-unloaded mice were subjected to tail suspension with the hind limbs elevated for 14days. The effects of the TRPV1, ASIC3, P2X2/3 antagonists on pain-like behaviors as assessed by the von Frey test, paw flick test and spontaneous pain scale; the expressions of TRPV1, ASICs, and P2X2 in the bone; and the effects of those antagonists on osteoblast and osteoclast regulators were examined. In addition, we evaluated the preventive effect of continuous treatment with a TRPV1 antagonist on the trigger for pain-like behavior and bone loss in tail-suspended mice. Pain-like behaviors were significantly improved by the treatment with TRPV1, ASIC, P2X antagonists; TRPV1, ASICs and P2X were expressed in the bone tissues; and the antagonists to these receptors down-regulated the expression of osteoblast and osteoclast regulators in tail-suspended mice. In addition, continuous treatment with a TRPV1 antagonist during tail-suspension prevented the induction of pain-like behaviors and regional bone loss in the unloaded hind limbs. We, therefore, believe that those receptor antagonists have a potential role in preventing the triggering of skeletal pain with associated regional bone metabolic disorder. Copyright © 2018 Elsevier Inc. All rights reserved.

Smart sensors development based on a distributed bus for microsystems applications

NASA Astrophysics Data System (ADS)

Ferrer, Carles; Lorente, Bibiana

2003-04-01

Our main objective in this work has been to develop a comunication system applicable between sensors and actuators and the data processing circuitry inside the microsystem in order to develop a flexible and modular architecture. This communication system is based on the use of a dedicated sensor bus composed by only two wires (a bidirectional data line and a clock line for sincronization). The basic philosophy of this development has been to create an IP model with VHDL for the bus driver that can be added to the sensor or the actuator to create an smart device that could be easily plugged with the other componets of the microsystem architecture. This methodology can be applied to a high integrated microsystem based on an extensively use of microelectronics technologies (ASICs, SoCs & MCMs). The reduced number of wires is an extraordinary advatage because produce a minimal interconnection between all the components and as a consequence the size of the microinstrument becomes smaller. The second aspect that we have considered in this development has been to reach a communication protocol that permits to built-up a very simple but robust bus driver interface that minimize the circuit overhead. This interconnection system has been applied to biomedical and aerospatial microsystems applications.

Low-Power, 8-Channel EEG Recorder and Seizure Detector ASIC for a Subdermal Implantable System.

PubMed

Do Valle, Bruno G; Cash, Sydney S; Sodini, Charles G

2016-12-01

EEG remains the mainstay test for the diagnosis and treatment of patients with epilepsy. Unfortunately, ambulatory EEG systems are far from ideal for patients who have infrequent seizures. These systems only last up to 3 days and if a seizure is not captured during the recordings, a definite diagnosis of the patient's condition cannot be given. This work aims to address this need by proposing a subdermal implantable, eight-channel EEG recorder and seizure detector that has two modes of operation: diagnosis and seizure counting. In the diagnosis mode, EEG is continuously recorded until a number of seizures are recorded. In the seizure counting mode, the system uses a low-power algorithm to track the number of seizures a patient has, providing doctors with a reliable count to help determine medication efficacy or other clinical endpoint. An ASIC that implements the EEG recording and seizure detection algorithm was designed and fabricated in a 0.18 μm CMOS process. The ASIC includes eight EEG channels and is designed to minimize the system's power and size. The result is a power-efficient analog front end that requires 2.75 μW per channel in diagnosis mode and 0.84 μW per channel in seizure counting mode. Both modes have an input referred noise of approximately 1.1 μVrms.

Flexible organic transistors and circuits with extreme bending stability

NASA Astrophysics Data System (ADS)

Sekitani, Tsuyoshi; Zschieschang, Ute; Klauk, Hagen; Someya, Takao

2010-12-01

Flexible electronic circuits are an essential prerequisite for the development of rollable displays, conformable sensors, biodegradable electronics and other applications with unconventional form factors. The smallest radius into which a circuit can be bent is typically several millimetres, limited by strain-induced damage to the active circuit elements. Bending-induced damage can be avoided by placing the circuit elements on rigid islands connected by stretchable wires, but the presence of rigid areas within the substrate plane limits the bending radius. Here we demonstrate organic transistors and complementary circuits that continue to operate without degradation while being folded into a radius of 100μm. This enormous flexibility and bending stability is enabled by a very thin plastic substrate (12.5μm), an atomically smooth planarization coating and a hybrid encapsulation stack that places the transistors in the neutral strain position. We demonstrate a potential application as a catheter with a sheet of transistors and sensors wrapped around it that enables the spatially resolved measurement of physical or chemical properties inside long, narrow tubes.

Circuit compliance compensation in lung protective ventilation.

PubMed

Masselli, Grazia Maria Pia; Silvestri, Sergio; Sciuto, Salvatore Andrea; Cappa, Paolo

2006-01-01

Lung protective ventilation utilizes low tidal volumes to ventilate patients with severe lung pathologies. The compensation of breathing circuit effects, i.e. those induced by compressible volume of the circuit, results particularly critical in the calculation of the actual tidal volume delivered to patient's respiratory system which in turns is responsible of the level of permissive hypercapnia. The present work analyzes the applicability of the equation for circuit compressible volume compensation in the case of pressure and volume controlled lung protective ventilation. Experimental tests conducted in-vitro show that the actual tidal volume can be reliably estimated if the compliance of the breathing circuit is measured with the same parameters and ventilation technique that will be utilized in lung protective ventilation. Differences between volume and pressure controlled ventilation are also quantitatively assessed showing that pressure controlled ventilation allows a more reliable compensation of breathing circuit compressible volume.

Measuring circuit

DOEpatents

Sun, Shan C.; Chaprnka, Anthony G.

1977-01-11

An automatic gain control circuit functions to adjust the magnitude of an input signal supplied to a measuring circuit to a level within the dynamic range of the measuring circuit while a log-ratio circuit adjusts the magnitude of the output signal from the measuring circuit to the level of the input signal and optimizes the signal-to-noise ratio performance of the measuring circuit.

A programmable heater control circuit for spacecraft

NASA Technical Reports Server (NTRS)

Nguyen, D. D.; Owen, J. W.; Smith, D. A.; Lewter, W. J.

1994-01-01

Spacecraft thermal control is accomplished for many components through use of multilayer insulation systems, electrical heaters, and radiator systems. The heaters are commanded to maintain component temperatures within design specifications. The programmable heater control circuit (PHCC) was designed to obtain an effective and efficient means of spacecraft thermal control. The hybrid circuit provides use of control instrumentation as temperature data, available to the spacecraft central data system, reprogramming capability of the local microprocessor during the spacecraft's mission, and the elimination of significant spacecraft wiring. The hybrid integrated circuit has a temperature sensing and conditioning circuit, a microprocessor, and a heater power and control circuit. The device is miniature and housed in a volume which allows physical integration with the component to be controlled. Applications might include alternate battery-powered logic-circuit configurations. A prototype unit with appropriate physical and functional interfaces was procured for testing. The physical functionality and the feasibility of fabrication of the hybrid integrated circuit were successfully verified. The remaining work to develop a flight-qualified device includes fabrication and testing of a Mil-certified part. An option for completing the PHCC flight qualification testing is to enter into a joint venture with industry.

Modular thought in the circuit analysis

NASA Astrophysics Data System (ADS)

Wang, Feng

2018-04-01

Applied to solve the problem of modular thought, provides a whole for simplification's method, the complex problems have become of, and the study of circuit is similar to the above problems: the complex connection between components, make the whole circuit topic solution seems to be more complex, and actually components the connection between the have rules to follow, this article mainly tells the story of study on the application of the circuit modular thought. First of all, this paper introduces the definition of two-terminal network and the concept of two-terminal network equivalent conversion, then summarizes the common source resistance hybrid network modular approach, containing controlled source network modular processing method, lists the common module, typical examples analysis.

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

PubMed Central

Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

2016-01-01

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively. PMID:27792131

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose.

PubMed

Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

2016-10-25

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal-oxide-semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm². The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

Performance of circuit switching in the Internet

NASA Astrophysics Data System (ADS)

Molinero-Fernández, Pablo; McKeown, Nick

2003-04-01

We study the performance of an Internet that uses circuit switching (CS) instead of, or in addition to, packet switching (PS). On the face of it, this would seem a pointless exercise; the Internet is packet switched, and it was deliberately built that way to enable the efficiencies afforded by statistical multiplexing and the robustness of fast rerouting around failures. But link utilization is low particularly at the core of the Internet, which makes statistical multiplexing less important than it once was. Moreover, circuit switches today are capable of rapid reconfiguration around failures. There is also renewed interest in CS because of the ease of building very-high-capacity optical circuit switches. Although several proposals have suggested ways in which CS may be introduced into the Internet, the research presented here is based on Transmission Control Protocol (TCP) switching, in which a new circuit is created for each application flow. Here we explore the performance of a network that uses TCP switching, with particular emphasis on the response time experienced by users. We use simple M/GI/1 and M/GI/N queues to model application flows in both packet-switched and circuit-switched networks, as well as ns-2 simulations. We conclude that because of high-bandwidth long-lived flows, it does not make sense to use CS in shared-access or local area networks. But our results suggest that in the core of the network, where high capacity is needed most, and where peak flow rate is limited by the access link, there is little or no difference in performance between CS and PS. Given that circuit switches can be built to be much faster than packet switches, this suggests that a circuit-switched core warrants further investigation.

Addressable-Matrix Integrated-Circuit Test Structure

NASA Technical Reports Server (NTRS)

Sayah, Hoshyar R.; Buehler, Martin G.

1991-01-01

Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.

No-warp potted circuits

NASA Technical Reports Server (NTRS)

Robinson, W. W.

1979-01-01

Sponge inserts compensate for potting-compound expansion and relieve thermal stresses on circuit boards. Technique quality of production runs on PC boards intended for applications in environments less severe than those for aerospace equipment. Pads reduce weight of modules because they weigh far less than potting compound they displace.

Temporal Planning for Compilation of Quantum Approximate Optimization Algorithm Circuits

NASA Technical Reports Server (NTRS)

Venturelli, Davide; Do, Minh Binh; Rieffel, Eleanor Gilbert; Frank, Jeremy David

2017-01-01

We investigate the application of temporal planners to the problem of compiling quantum circuits to newly emerging quantum hardware. While our approach is general, we focus our initial experiments on Quantum Approximate Optimization Algorithm (QAOA) circuits that have few ordering constraints and allow highly parallel plans. We report on experiments using several temporal planners to compile circuits of various sizes to a realistic hardware. This early empirical evaluation suggests that temporal planning is a viable approach to quantum circuit compilation.

30 CFR 77.800 - High-voltage circuits; circuit breakers.

Code of Federal Regulations, 2010 CFR

2010-07-01

... devices to provide protection against under voltage, grounded phase, short circuit and overcurrent. High... 30 Mineral Resources 1 2010-07-01 2010-07-01 false High-voltage circuits; circuit breakers. 77.800... COAL MINES Surface High-Voltage Distribution § 77.800 High-voltage circuits; circuit breakers. High...

GAS PHOTOTUBE CIRCUIT

DOEpatents

Richardson, J.H.

1958-03-01

This patent pertains to electronic circuits for measuring the intensity of light and is especially concerned with measurement between preset light thresholds. Such a circuit has application in connection with devices for reading-out information stored on punch cards or tapes where the cards and tapes are translucent. By the novel arrangement of this invention thc sensitivity of a gas phototube is maintained at a low value when the light intensity is below a first threshold level. If the light level rises above the first threshold level, the tube is rendered highly sensitive and an output signal will vary in proportion to the light intensity change. When the light level decreases below a second threshold level, the gas phototube is automatically rendered highly insensitive. Each of these threshold points is adjustable.

Project Circuits in a Basic Electric Circuits Course

ERIC Educational Resources Information Center

Becker, James P.; Plumb, Carolyn; Revia, Richard A.

2014-01-01

The use of project circuits (a photoplethysmograph circuit and a simple audio amplifier), introduced in a sophomore-level electric circuits course utilizing active learning and inquiry-based methods, is described. The development of the project circuits was initiated to promote enhanced engagement and deeper understanding of course content among…

Electronic circuits

NASA Technical Reports Server (NTRS)

1976-01-01

Twenty-nine circuits and circuit techniques developed for communications and instrumentation technology are described. Topics include pulse-code modulation, phase-locked loops, data coding, data recording, detection circuits, logic circuits, oscillators, and amplifiers.

Biomedically relevant circuit-design strategies in mammalian synthetic biology

PubMed Central

Bacchus, William; Aubel, Dominique; Fussenegger, Martin

2013-01-01

The development and progress in synthetic biology has been remarkable. Although still in its infancy, synthetic biology has achieved much during the past decade. Improvements in genetic circuit design have increased the potential for clinical applicability of synthetic biology research. What began as simple transcriptional gene switches has rapidly developed into a variety of complex regulatory circuits based on the transcriptional, translational and post-translational regulation. Instead of compounds with potential pharmacologic side effects, the inducer molecules now used are metabolites of the human body and even members of native cell signaling pathways. In this review, we address recent progress in mammalian synthetic biology circuit design and focus on how novel designs push synthetic biology toward clinical implementation. Groundbreaking research on the implementation of optogenetics and intercellular communications is addressed, as particularly optogenetics provides unprecedented opportunities for clinical application. Along with an increase in synthetic network complexity, multicellular systems are now being used to provide a platform for next-generation circuit design. PMID:24061539

Design and implementation of a simple acousto optic dual control circuit

NASA Astrophysics Data System (ADS)

Li, Biqing; Li, Zhao

2017-04-01

This page proposed a simple light control circuit which designed by using power supply circuit, sonic circuits, electric circuit and delay circuit four parts. The main chip for CD4011, have inside of the four and to complete the sonic or circuit, electric, delay logic circuit. During the day, no matter how much a pedestrian voice, is ever shine light bulb. Dark night, circuit in a body to make the microphone as long as testing noise, and will automatically be bright for pedestrians lighting, several minutes after the automatic and put out, effective energy saving. Applicable scope and the working principle of the circuit principle diagram and given device parameters selection, power saving effect is obvious, at the same time greatly reduce the maintenance quantity, saving money, use effect is good.

Graphene Oxide/Poly(3-hexylthiophene) Nanocomposite Thin-Film Phototransistor for Logic Circuit Applications

NASA Astrophysics Data System (ADS)

Mansouri, S.; Coskun, B.; El Mir, L.; Al-Sehemi, Abdullah G.; Al-Ghamdi, Ahmed; Yakuphanoglu, F.

2018-04-01

Graphene is a sheet-structured material that lacks a forbidden band, being a good candidate for use in radiofrequency applications. We have elaborated graphene-oxide-doped poly(3-hexylthiophene) nanocomposite to increase the interlayer distance and thereby open a large bandgap for use in the field of logic circuits. Graphene oxide/poly(3-hexylthiophene) (GO/P3HT) nanocomposite thin-film transistors (TFTs) were fabricated on silicon oxide substrate by spin coating method. The current-voltage ( I- V) characteristics of TFTs with various P3HT compositions were studied in the dark and under light illumination. The photocurrent, charge carrier mobility, subthreshold voltage, density of interface states, density of occupied states, and I ON/ I OFF ratio of the devices strongly depended on the P3HT weight ratio in the composite. The effects of white-light illumination on the electrical parameters of the transistors were investigated. The results indicated that GO/P3HT nanocomposite thin-film transistors have high potential for use in radiofrequency applications, and their feasibility for use in digital applications has been demonstrated.

Implantable neurotechnologies: bidirectional neural interfaces--applications and VLSI circuit implementations.

PubMed

Greenwald, Elliot; Masters, Matthew R; Thakor, Nitish V

2016-01-01

A bidirectional neural interface is a device that transfers information into and out of the nervous system. This class of devices has potential to improve treatment and therapy in several patient populations. Progress in very large-scale integration has advanced the design of complex integrated circuits. System-on-chip devices are capable of recording neural electrical activity and altering natural activity with electrical stimulation. Often, these devices include wireless powering and telemetry functions. This review presents the state of the art of bidirectional circuits as applied to neuroprosthetic, neurorepair, and neurotherapeutic systems.

DC isolation and protection system and circuit

NASA Technical Reports Server (NTRS)

Wagner, Charles A. (Inventor); Kellogg, Gary V. (Inventor)

1991-01-01

A precision analog electronic circuit that is capable of sending accurate signals to an external device that has hostile electric characteristics, including the presence of very large common mode voltages. The circuit is also capable of surviving applications of normal mode overvoltages of up to 120 VAC/VDC for unlimited periods of time without damage or degradation. First, the circuit isolates the DC signal output from the computer. Means are then provided for amplifying the isolated DC signal. Further means are provided for stabilizing and protecting the isolating and amplifying means, and the isolated and amplified DC signal which is output to the external device, against overvoltages and overcurrents.

Negative inductance circuits for metamaterial bandwidth enhancement

NASA Astrophysics Data System (ADS)

Avignon-Meseldzija, Emilie; Lepetit, Thomas; Ferreira, Pietro Maris; Boust, Fabrice

2017-12-01

Passive metamaterials have yet to be translated into applications on a large scale due in large part to their limited bandwidth. To overcome this limitation many authors have suggested coupling metamaterials to non-Foster circuits. However, up to now, the number of convincing demonstrations based on non-Foster metamaterials has been very limited. This paper intends to clarify why progress has been so slow, i.e., the fundamental difficulty in making a truly broadband and efficient non-Foster metamaterial. To this end, we consider two families of metamaterials, namely Artificial Magnetic Media and Artificial Magnetic Conductors. In both cases, it turns out that bandwidth enhancement requires negative inductance with almost zero resistance. To estimate bandwidth enhancement with actual non-Foster circuits, we consider two classes of such circuits, namely Linvill and gyrator. The issue of stability being critical, both metamaterial families are studied with equivalent circuits that include advanced models of these non-Foster circuits. Conclusions are different for Artificial Magnetic Media coupled to Linvill circuits and Artificial Magnetic Conductors coupled to gyrator circuits. In the first case, requirements for bandwidth enhancement and stability are very hard to meet simultaneously whereas, in the second case, an adjustment of the transistor gain does significantly increase bandwidth.

High-performance electronics for time-of-flight PET systems

NASA Astrophysics Data System (ADS)

Choong, W.-S.; Peng, Q.; Vu, C. Q.; Turko, B. T.; Moses, W. W.

2013-01-01

We have designed and built a high-performance readout electronics system for time-of-flight positron emission tomography (TOF PET) cameras. The electronics architecture is based on the electronics for a commercial whole-body PET camera (Siemens/CPS Cardinal electronics), modified to improve the timing performance. The fundamental contributions in the electronics that can limit the timing resolution include the constant fraction discriminator (CFD), which converts the analog electrical signal from the photo-detector to a digital signal whose leading edge is time-correlated with the input signal, and the time-to-digital converter (TDC), which provides a time stamp for the CFD output. Coincident events are identified by digitally comparing the values of the time stamps. In the Cardinal electronics, the front-end processing electronics are performed by an Analog subsection board, which has two application-specific integrated circuits (ASICs), each servicing a PET block detector module. The ASIC has a built-in CFD and TDC. We found that a significant degradation in the timing resolution comes from the ASIC's CFD and TDC. Therefore, we have designed and built an improved Analog subsection board that replaces the ASIC's CFD and TDC with a high-performance CFD (made with discrete components) and TDC (using the CERN high-performance TDC ASIC). The improved Analog subsection board is used in a custom single-ring LSO-based TOF PET camera. The electronics system achieves a timing resolution of 60 ps FWHM. Prototype TOF detector modules are read out with the electronics system and give coincidence timing resolutions of 259 ps FWHM and 156 ps FWHM for detector modules coupled to LSO and LaBr3 crystals respectively.

High-performance electronics for time-of-flight PET systems.

PubMed

Choong, W-S; Peng, Q; Vu, C Q; Turko, B T; Moses, W W

2013-01-01

We have designed and built a high-performance readout electronics system for time-of-flight positron emission tomography (TOF PET) cameras. The electronics architecture is based on the electronics for a commercial whole-body PET camera (Siemens/CPS Cardinal electronics), modified to improve the timing performance. The fundamental contributions in the electronics that can limit the timing resolution include the constant fraction discriminator (CFD), which converts the analog electrical signal from the photo-detector to a digital signal whose leading edge is time-correlated with the input signal, and the time-to-digital converter (TDC), which provides a time stamp for the CFD output. Coincident events are identified by digitally comparing the values of the time stamps. In the Cardinal electronics, the front-end processing electronics are performed by an Analog subsection board, which has two application-specific integrated circuits (ASICs), each servicing a PET block detector module. The ASIC has a built-in CFD and TDC. We found that a significant degradation in the timing resolution comes from the ASIC's CFD and TDC. Therefore, we have designed and built an improved Analog subsection board that replaces the ASIC's CFD and TDC with a high-performance CFD (made with discrete components) and TDC (using the CERN high-performance TDC ASIC). The improved Analog subsection board is used in a custom single-ring LSO-based TOF PET camera. The electronics system achieves a timing resolution of 60 ps FWHM. Prototype TOF detector modules are read out with the electronics system and give coincidence timing resolutions of 259 ps FWHM and 156 ps FWHM for detector modules coupled to LSO and LaBr 3 crystals respectively.

Simulation Approach for Timing Analysis of Genetic Logic Circuits.

PubMed

Baig, Hasan; Madsen, Jan

2017-07-21

Constructing genetic logic circuits is an application of synthetic biology in which parts of the DNA of a living cell are engineered to perform a dedicated Boolean function triggered by an appropriate concentration of certain proteins or by different genetic components. These logic circuits work in a manner similar to electronic logic circuits, but they are much more stochastic and hence much harder to characterize. In this article, we introduce an approach to analyze the threshold value and timing of genetic logic circuits. We show how this approach can be used to analyze the timing behavior of single and cascaded genetic logic circuits. We further analyze the timing sensitivity of circuits by varying the degradation rates and concentrations. Our approach can be used not only to characterize the timing behavior but also to analyze the timing constraints of cascaded genetic logic circuits, a capability that we believe will be important for design automation in synthetic biology.

Double layers and circuits in astrophysics

NASA Technical Reports Server (NTRS)

Alfven, Hannes

1986-01-01

As the rate of energy release in a double layer with voltage delta V is P approx I delta V, a double layer must be treated as a part of a circuit which delivers the current I. As neither double layer nor circuit can be derived from magnetofluid models of a plasma, such models are useless for treating energy transfer by means of double layers. They must be replaced by particle models and circuit theory. A simple circuit is suggested which is applied to the energizing of auroral particles, to solar flares, and to intergalactic double radio sources. Application to the heliospheric current systems leads to the prediction of two double layers on the Sun's axis which may give radiations detectable from Earth. Double layers in space should be classified as a new type of celestial object (one example is the double radio sources). It is tentatively suggested in X-ray and Gamma-ray bursts may be due to exploding double layers (although annihilation is an alternative energy source). A study of how a number of the most used textbooks in astrophysics treat important concepts like double layers, critical velocity, pinch effects and circuits is made.

Signal Digitizer and Cross-Correlation Application Specific Integrated Circuit

NASA Technical Reports Server (NTRS)

Baranauskas, Gytis (Inventor); Lim, Boon H. (Inventor); Baranauskas, Dalius (Inventor); Zelenin, Denis (Inventor); Kangaslahti, Pekka (Inventor); Tanner, Alan B. (Inventor)

2017-01-01

According to one embodiment, a cross-correlator comprises a plurality of analog front ends (AFEs), a cross-correlation circuit and a data serializer. Each of the AFEs comprises a variable gain amplifier (VGA) and a corresponding analog-to-digital converter (ADC) in which the VGA receives and modifies a unique analog signal associates with a measured analog radio frequency (RF) signal and the ADC produces digital data associated with the modified analog signal. Communicatively coupled to the AFEs, the cross-correlation circuit performs a cross-correlation operation on the digital data produced from different measured analog RF signals. The data serializer is communicatively coupled to the summing and cross-correlating matrix and continuously outputs a prescribed amount of the correlated digital data.

A closed-loop compressive-sensing-based neural recording system.

PubMed

Zhang, Jie; Mitra, Srinjoy; Suo, Yuanming; Cheng, Andrew; Xiong, Tao; Michon, Frederic; Welkenhuysen, Marleen; Kloosterman, Fabian; Chin, Peter S; Hsiao, Steven; Tran, Trac D; Yazicioglu, Firat; Etienne-Cummings, Ralph

2015-06-01

This paper describes a low power closed-loop compressive sensing (CS) based neural recording system. This system provides an efficient method to reduce data transmission bandwidth for implantable neural recording devices. By doing so, this technique reduces a majority of system power consumption which is dissipated at data readout interface. The design of the system is scalable and is a viable option for large scale integration of electrodes or recording sites onto a single device. The entire system consists of an application-specific integrated circuit (ASIC) with 4 recording readout channels with CS circuits, a real time off-chip CS recovery block and a recovery quality evaluation block that provides a closed feedback to adaptively adjust compression rate. Since CS performance is strongly signal dependent, the ASIC has been tested in vivo and with standard public neural databases. Implemented using efficient digital circuit, this system is able to achieve >10 times data compression on the entire neural spike band (500-6KHz) while consuming only 0.83uW (0.53 V voltage supply) additional digital power per electrode. When only the spikes are desired, the system is able to further compress the detected spikes by around 16 times. Unlike other similar systems, the characteristic spikes and inter-spike data can both be recovered which guarantes a >95% spike classification success rate. The compression circuit occupied 0.11mm(2)/electrode in a 180nm CMOS process. The complete signal processing circuit consumes <16uW/electrode. Power and area efficiency demonstrated by the system make it an ideal candidate for integration into large recording arrays containing thousands of electrode. Closed-loop recording and reconstruction performance evaluation further improves the robustness of the compression method, thus making the system more practical for long term recording.

The development of the miniaturized waveform receiver with the function measuring Antenna Impedance in space plasmas

NASA Astrophysics Data System (ADS)

Ishii, H.; Kojima, H.; Fukuhara, H.; Okada, S.; Yamakawa, H.

2012-04-01

Plasma wave is one of the most essential physical quantities in the solar terrestrial physics. The role of plasma wave receiver onboard satellites is to detect plasma waves in space with a good signal to noise ratio. There are two types of plasma wave receivers, the sweep frequency analyzer and the waveform capture. While the sweep frequency analyzer provides plasma wave spectra, the waveform capture obtains waveforms with phase information that is significant in studying nonlinear phenomena. Antenna sensors to observe electric fields of the plasma waves show different features in plasmas from in vacuum. The antenna impedances have specific characteristics in the frequency domain because of the dispersion of plasmas. These antenna impedances are expressed with complex number. We need to know not only the antenna impedances but also the transfer functions of plasma wave receiver's circuits in order to calibrate observed waveforms precisely. The impedances of the electric field antennas are affected by a state of surrounding plasmas. Since satellites run through various regions with different plasma parameters, we precisely should measure the antenna impedances onboard spacecraft. On the contrary, we can obtain the plasma density and by measuring the antenna impedances. Several formulas of the antenna impedance measurement system were proposed. A synchronous detection method is used on the BepiColombo Mercury Magnetospheric Orbiter (MMO), which will be launched in 2014. The digital data are stored in the onboard memory. They are read out and converted to the analog waveforms by D/A converter. They are fed into the input of the preamplifiers of antenna sensors through a resistor. We can calculate a transfer function of the circuit by applying the synchronous detection method to the output waveform from waveform receivers and digital data as a signal source. The size of this system is same as an A5 board. In recent years, Application Specific Integrated Circuit (ASIC

Neuro-Prosthetic Implants With Adjustable Electrode Arrays

NASA Technical Reports Server (NTRS)

Whitacre, Jay; DelCastillo, Linda Y.; Mojarradi, Mohammad; Johnson, Travis; West, William; Andersen, Richard

2006-01-01

Brushlike arrays of electrodes packaged with application-specific integrated circuits (ASICs) are undergoing development for use as electronic implants especially as neuro-prosthetic devices that might be implanted in brains to detect weak electrical signals generated by neurons. These implants partly resemble the ones reported in Integrated Electrode Arrays for Neuro-Prosthetic Implants (NPO-21198), NASA Tech Briefs, Vol. 27, No. 2 (February 2003), page 48. The basic idea underlying both the present and previously reported implants is that the electrodes would pick up signals from neurons and the ASICs would amplify and otherwise preprocess the signals for monitoring by external equipment. The figure presents a simplified and partly schematic view of an implant according to the present concept. Whereas the electrodes in an implant according to the previously reported concept would be microscopic wires, the electrodes according to the present concept are in the form of microscopic needles. An even more important difference would be that, unlike the previously reported concept, the present concept calls for the inclusion of microelectromechanical actuators for adjusting the depth of penetration of the electrodes into brain tissue. The prototype implant now under construction includes an array of 100 electrodes and corresponding array of electrode contact pads formed on opposite faces of a plate fabricated by techniques that are established in the art of microelectromechanical systems (MEMS). A mixed-signal ASIC under construction at the time of reporting the information for this article will include 100 analog amplifier channels (one amplifier per electrode). On one face of the mixed-signal ASIC there will be a solder-bump/micro-pad array that will have the same pitch as that of the electrode array, and that will be used to make the electrical and mechanical connections between the electrode array and the ASIC. Once the electrode array and the ASIC are soldered

Design of remote laser-induced fluorescence system's acquisition circuit

NASA Astrophysics Data System (ADS)

Wang, Guoqing; Lou, Yue; Wang, Ran; Yan, Debao; Li, Xin; Zhao, Xin; Chen, Dong; Zhao, Qi

2017-10-01

Laser-induced fluorescence system(LIfS) has been found its significant application in identifying one kind of substance from another by its properties even it's thimbleful, and becomes useful in plenty of fields. Many superior works have reported LIfS' theoretical analysis , designs and uses. However, the usual LIPS is always constructed in labs to detect matter quite closely, for the system using low-power laser as excitation source and charge coupled device (CCD) as detector. Promoting the detectivity of LIfS is of much concern to spread its application. Here, we take a high-energy narrow-pulse laser instead of commonly used continuous wave laser to operate sample, thus we can get strong fluorescent. Besides, photomultiplier (PMT) with high sensitivity is adopted in our system to detect extremely weak fluorescence after a long flight time from the sample to the detector. Another advantage in our system, as the fluorescence collected into spectroscopy, multiple wavelengths of light can be converted to the corresponding electrical signals with the linear array multichannel PMT. Therefore, at the cost of high-powered incentive and high-sensitive detector, a remote LIFS is get. In order to run this system, it is of importance to turn light signal to digital signal which can be processed by computer. The pulse width of fluorescence is deeply associated with excitation laser, at the nanosecond(ns) level, which has a high demand for acquisition circuit. We design an acquisition circuit including, I/V conversion circuit, amplifying circuit and peak-holding circuit. The simulation of circuit shows that peak-holding circuit can be one effective approach to reducing difficulty of acquisition circuit.

Interface and protocol development for STS read-out ASIC in the CBM experiment at FAIR

NASA Astrophysics Data System (ADS)

Kasinski, Krzysztof; Zabolotny, Wojciech; Szczygiel, Robert

2014-11-01

This paper presents a proposal of a protocol for communication between the read-out integrated circuit for the STS (Silicon Tracking System) and the Data Processing Board (DPB) at CBM (Compressed Baryonic Matter) experiment at FAIR, GSI (Helmholtzzentrum fuer Schwerionenforschung GmbH) in Germany. The application background, objectives and proposed solution is presented.

Application of telecom planar lightwave circuits for homeland security sensing

NASA Astrophysics Data System (ADS)

Veldhuis, Gert J.; Elders, Job; van Weerden, Harm; Amersfoort, Martin

2004-03-01

Over the past decade, a massive effort has been made in the development of planar lightwave circuits (PLCs) for application in optical telecommunications. Major advances have been made, on both the technological and functional performance front. Highly sophisticated software tools that are used to tailor designs to required functional performance support these developments. In addition extensive know-how in the field of packaging, testing, and failure mode and effects analysis (FMEA) has been built up in the struggle for meeting the stringent Telcordia requirements that apply to telecom products. As an example, silica-on-silicon is now a mature technology available at several industrial foundries around the world, where, on the performance front, the arrayed-waveguide grating (AWG) has evolved into an off-the-shelf product. The field of optical chemical-biological (CB) sensors for homeland security application can greatly benefit from the advances as described above. In this paper we discuss the currently available technologies, device concepts, and modeling tools that have emerged from the telecommunications arena and that can effectively be applied to the field of homeland security. Using this profound telecom knowledge base, standard telecom components can readily be tailored for detecting CB agents. Designs for telecom components aim at complete isolation from the environment to exclude impact of environmental parameters on optical performance. For sensing applications, the optical path must be exposed to the measurand, in this area additional development is required beyond what has already been achieved in telecom development. We have tackled this problem, and are now in a position to apply standard telecom components for CB sensing. As an example, the application of an AWG as a refractometer is demonstrated, and its performance evaluated.

35 GHz integrated circuit rectifying antenna with 33 percent efficiency

NASA Technical Reports Server (NTRS)

Yoo, T.-W.; Chang, K.

1991-01-01

A 35 GHz integrated circuit rectifying antenna (rectenna) has been developed using a microstrip dipole antenna and beam-lead mixer diode. Greater than 33 percent conversion efficiency has been achieved. The circuit should have applications in microwave/millimeter-wave power transmission and detection.

Responses of glomus cells to hypoxia and acidosis are uncoupled, reciprocal and linked to ASIC3 expression: selectivity of chemosensory transduction

PubMed Central

Lu, Yongjun; Whiteis, Carol A; Sluka, Kathleen A; Chapleau, Mark W; Abboud, François M

2013-01-01

Carotid body glomus cells are the primary sites of chemotransduction of hypoxaemia and acidosis in peripheral arterial chemoreceptors. They exhibit pronounced morphological heterogeneity. A quantitative assessment of their functional capacity to differentiate between these two major chemical signals has remained undefined. We tested the hypothesis that there is a differential sensory transduction of hypoxia and acidosis at the level of glomus cells. We measured cytoplasmic Ca2+ concentration in individual glomus cells, isolated in clusters from rat carotid bodies, in response to hypoxia ( mmHg) and to acidosis at pH 6.8. More than two-thirds (68%) were sensitive to both hypoxia and acidosis, 19% were exclusively sensitive to hypoxia and 13% exclusively sensitive to acidosis. Those sensitive to both revealed significant preferential sensitivity to either hypoxia or to acidosis. This uncoupling and reciprocity was recapitulated in a mouse model by altering the expression of the acid-sensing ion channel 3 (ASIC3) which we had identified earlier in glomus cells. Increased expression of ASIC3 in transgenic mice increased pH sensitivity while reducing cyanide sensitivity. Conversely, deletion of ASIC3 in the knockout mouse reduced pH sensitivity while the relative sensitivity to cyanide or to hypoxia was increased. In this work, we quantify functional differences among glomus cells and show reciprocal sensitivity to acidosis and hypoxia in most glomus cells. We speculate that this selective chemotransduction of glomus cells by either stimulus may result in the activation of different afferents that are preferentially more sensitive to either hypoxia or acidosis, and thus may evoke different and more specific autonomic adjustments to either stimulus. PMID:23165770

Compensated gain control circuit for buck regulator command charge circuit

DOEpatents

Barrett, David M.

1996-01-01

A buck regulator command charge circuit includes a compensated-gain control signal for compensating for changes in the component values in order to achieve optimal voltage regulation. The compensated-gain control circuit includes an automatic-gain control circuit for generating a variable-gain control signal. The automatic-gain control circuit is formed of a precision rectifier circuit, a filter network, an error amplifier, and an integrator circuit.

Thermally-induced voltage alteration for integrated circuit analysis

DOEpatents

Cole, Jr., Edward I.

2000-01-01

A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

Compensated gain control circuit for buck regulator command charge circuit

DOEpatents

Barrett, D.M.

1996-11-05

A buck regulator command charge circuit includes a compensated-gain control signal for compensating for changes in the component values in order to achieve optimal voltage regulation. The compensated-gain control circuit includes an automatic-gain control circuit for generating a variable-gain control signal. The automatic-gain control circuit is formed of a precision rectifier circuit, a filter network, an error amplifier, and an integrator circuit. 5 figs.

Video data compression using artificial neural network differential vector quantization

NASA Technical Reports Server (NTRS)

Krishnamurthy, Ashok K.; Bibyk, Steven B.; Ahalt, Stanley C.

1991-01-01

An artificial neural network vector quantizer is developed for use in data compression applications such as Digital Video. Differential Vector Quantization is used to preserve edge features, and a new adaptive algorithm, known as Frequency-Sensitive Competitive Learning, is used to develop the vector quantizer codebook. To develop real time performance, a custom Very Large Scale Integration Application Specific Integrated Circuit (VLSI ASIC) is being developed to realize the associative memory functions needed in the vector quantization algorithm. By using vector quantization, the need for Huffman coding can be eliminated, resulting in superior performance against channel bit errors than methods that use variable length codes.

MiniDSS: a low-power and high-precision miniaturized digital sun sensor

NASA Astrophysics Data System (ADS)

de Boer, B. M.; Durkut, M.; Laan, E.; Hakkesteegt, H.; Theuwissen, A.; Xie, N.; Leijtens, J. L.; Urquijo, E.; Bruins, P.

2017-11-01

A high-precision and low-power miniaturized digital sun sensor has been developed at TNO. The single-chip sun sensor comprises an application specific integrated circuit (ASIC) on which an active pixel sensor (APS), read-out and processing circuitry as well as communication circuitry are combined. The design was optimized for low recurrent cost. The sensor is albedo insensitive and the prototype combines an accuracy in the order of 0.03° with a mass of just 72 g and a power consumption of only 65 mW.

Advanced testing of the DEPFET minimatrix particle detector

NASA Astrophysics Data System (ADS)

Andricek, L.; Kodyš, P.; Koffmane, C.; Ninkovic, J.; Oswald, C.; Richter, R.; Ritter, A.; Rummel, S.; Scheirich, J.; Wassatsch, A.

2012-01-01

The DEPFET (DEPleted Field Effect Transistor) is an active pixel particle detector with a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) integrated in each pixel, providing first amplification stage of readout electronics. Excellent signal over noise performance is gained this way. The DEPFET sensor will be used as a vertex detector in the Belle II experiment at SuperKEKB, electron-positron collider in Japan. The vertex detector will be composed of two layers of pixel detectors (DEPFET) and four layers of strip detectors. The DEPFET sensor requires switching and current readout circuits for its operation. These circuits have been designed as ASICs (Application Specific Integrated Circuits) in several different versions, but they provide insufficient flexibility for precise detector testing. Therefore, a test system with a flexible control cycle range and minimal noise has been designed for testing and characterizing of small detector prototypes (Minimatrices). Sensors with different design layouts and thicknesses are produced in order to evaluate and select the one with the best performance for the Belle II application. Description of the test system as well as measurement results are presented.

Connecting Time and Frequency in the RC Circuit

NASA Astrophysics Data System (ADS)

Moya, A. A.

2017-04-01

Charging and discharging processes of a capacitor through a resistor, as well as the concept of impedance in alternating current circuits, are topics covered in introductory physics courses. The experimental study of the charge and discharge of a capacitor through a resistor is a well-established lab exercise that is used to introduce concepts such as exponential increase or decrease and time constant. Determining the time constant of the RC circuit has important practical applications because, for example, it can be used to measure unknown values of resistance or capacitance. The transient experiment can be done by using a voltmeter and stopwatch, signal generator and oscilloscope, or even low-cost data acquisition systems such as Arduino. An equivalent topic when studying alternating current circuits arises from the characterization of the impedance of the series or parallel combination of the capacitor and the resistor as a function of frequency. Determining the time constant of the RC circuit by means of impedance measurements for different frequencies is a known experimental technique that can be done using not only LCR meters but also basic instrumentation in the physics lab such as a signal generator, frequency counter, and multimeter. However, lab exercises dealing with RC circuits in alternating current usually focus on their use as filters, and the potential applications in the field of the electrical characterization of material systems are ignored. In this work, we describe a simple exercise showing how the time constant of the RC circuit can easily be determined in the introductory physics lab by means of impedance measurements as a function of frequency. This exercise allows students to learn experimental techniques that find application to characterize the time constants of the charge transport processes in material systems. Moreover, comparison of the time constants obtained from transient and frequency analysis allows us to relate the time and

Synthetic Analog and Digital Circuits for Cellular Computation and Memory

PubMed Central

Purcell, Oliver; Lu, Timothy K.

2014-01-01

Biological computation is a major area of focus in synthetic biology because it has the potential to enable a wide range of applications. Synthetic biologists have applied engineering concepts to biological systems in order to construct progressively more complex gene circuits capable of processing information in living cells. Here, we review the current state of computational genetic circuits and describe artificial gene circuits that perform digital and analog computation. We then discuss recent progress in designing gene circuits that exhibit memory, and how memory and computation have been integrated to yield more complex systems that can both process and record information. Finally, we suggest new directions for engineering biological circuits capable of computation. PMID:24794536

An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras

DOE PAGES

Bolotnikov, A. E.; Ackley, K.; Camarda, G. S.; ...

2015-07-28

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe (CZT) detectors coupled to a front-end readout ASIC for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6x6x15 mm 3 detectors grouped into 3x3 sub-arrays of 2x2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readoutmore » electronics. The further enhancement of the arrays’ performance and reduction of their cost are made possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.« less

A novel interface circuit for triboelectric nanogenerator

NASA Astrophysics Data System (ADS)

Yu, Wuqi; Ma, Jiahao; Zhang, Zhaohua; Ren, Tianling

2017-10-01

For most triboelectric nanogenerators (TENGs), the electric output should be a short AC pulse, which has the common characteristic of high voltage but low current. Thus it is necessary to convert the AC to DC and store the electric energy before driving conventional electronics. The traditional AC voltage regulator circuit which commonly consists of transformer, rectifier bridge, filter capacitor, and voltage regulator diode is not suitable for the TENG because the transformer’s consumption of power is appreciable if the TENG output is small. This article describes an innovative design of an interface circuit for a triboelectric nanogenerator that is transformerless and easily integrated. The circuit consists of large-capacity electrolytic capacitors that can realize to intermittently charge lithium-ion batteries and the control section contains the charging chip, the rectifying circuit, a comparator chip and switch chip. More important, the whole interface circuit is completely self-powered and self-controlled. Meanwhile, the chip is widely used in the circuit, so it is convenient to integrate into PCB. In short, this work presents a novel interface circuit for TENGs and makes progress to the practical application and industrialization of nanogenerators. Project supported by the National Natural Science Foundation of China (No. 61434001) and the ‘Thousands Talents’ Program for Pioneer Researchers and Its Innovation Team, China.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Flory, John Andrew; Padilla, Denise D.; Gauthier, John H.

Upcoming weapon programs require an aggressive increase in Application Specific Integrated Circuit (ASIC) production at Sandia National Laboratories (SNL). SNL has developed unique modeling and optimization tools that have been instrumental in improving ASIC production productivity and efficiency, identifying optimal operational and tactical execution plans under resource constraints, and providing confidence in successful mission execution. With ten products and unprecedented levels of demand, a single set of shared resources, highly variable processes, and the need for external supplier task synchronization, scheduling is an integral part of successful manufacturing. The scheduler uses an iterative multi-objective genetic algorithm and a multi-dimensional performancemore » evaluator. Schedule feasibility is assessed using a discrete event simulation (DES) that incorporates operational uncertainty, variability, and resource availability. The tools provide rapid scenario assessments and responses to variances in the operational environment, and have been used to inform major equipment investments and workforce planning decisions in multiple SNL facilities.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bolotnikov, A. E., E-mail: bolotnik@bnl.gov; Ackley, K.; Camarda, G. S.

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm{sup 3} detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We presentmore » the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays’ performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.« less

Multiplexed, High Density Electrophysiology with Nanofabricated Neural Probes

PubMed Central

Du, Jiangang; Blanche, Timothy J.; Harrison, Reid R.; Lester, Henry A.; Masmanidis, Sotiris C.

2011-01-01

Extracellular electrode arrays can reveal the neuronal network correlates of behavior with single-cell, single-spike, and sub-millisecond resolution. However, implantable electrodes are inherently invasive, and efforts to scale up the number and density of recording sites must compromise on device size in order to connect the electrodes. Here, we report on silicon-based neural probes employing nanofabricated, high-density electrical leads. Furthermore, we address the challenge of reading out multichannel data with an application-specific integrated circuit (ASIC) performing signal amplification, band-pass filtering, and multiplexing functions. We demonstrate high spatial resolution extracellular measurements with a fully integrated, low noise 64-channel system weighing just 330 mg. The on-chip multiplexers make possible recordings with substantially fewer external wires than the number of input channels. By combining nanofabricated probes with ASICs we have implemented a system for performing large-scale, high-density electrophysiology in small, freely behaving animals that is both minimally invasive and highly scalable. PMID:22022568

Design of the PET-MR system for head imaging of the DREAM Project

NASA Astrophysics Data System (ADS)

González, A. J.; Conde, P.; Hernández, L.; Herrero, V.; Moliner, L.; Monzó, J. M.; Orero, A.; Peiró, A.; Rodríguez-Álvarez, M. J.; Ros, A.; Sánchez, F.; Soriano, A.; Vidal, L. F.; Benlloch, J. M.

2013-02-01

In this paper we describe the overall design of a PET-MR system for head imaging within the framework of the DREAM Project as well as the first detector module tests. The PET system design consists of 4 rings of 16 detector modules each and it is expected to be integrated in a head dedicated radio frequency coil of an MR scanner. The PET modules are based on monolithic LYSO crystals coupled by means of optical devices to an array of 256 Silicon Photomultipliers. These types of crystals allow to preserve the scintillation light distribution and, thus, to recover the exact photon impact position with the proper characterization of such a distribution. Every module contains 4 Application Specific Integrated Circuits (ASICs) which return detailed information of several light statistical momenta. The preliminary tests carried out on this design and controlled by means of ASICs have shown promising results towards the suitability of hybrid PET-MR systems.

A time-based front-end ASIC for the silicon micro strip sensors of the bar PANDA Micro Vertex Detector

NASA Astrophysics Data System (ADS)

Di Pietro, V.; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Zambanini, A.

2016-03-01

The bar PANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA (bar PANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels.

Simulation environment based on the Universal Verification Methodology

NASA Astrophysics Data System (ADS)

Fiergolski, A.

2017-01-01

Universal Verification Methodology (UVM) is a standardized approach of verifying integrated circuit designs, targeting a Coverage-Driven Verification (CDV). It combines automatic test generation, self-checking testbenches, and coverage metrics to indicate progress in the design verification. The flow of the CDV differs from the traditional directed-testing approach. With the CDV, a testbench developer, by setting the verification goals, starts with an structured plan. Those goals are targeted further by a developed testbench, which generates legal stimuli and sends them to a device under test (DUT). The progress is measured by coverage monitors added to the simulation environment. In this way, the non-exercised functionality can be identified. Moreover, the additional scoreboards indicate undesired DUT behaviour. Such verification environments were developed for three recent ASIC and FPGA projects which have successfully implemented the new work-flow: (1) the CLICpix2 65 nm CMOS hybrid pixel readout ASIC design; (2) the C3PD 180 nm HV-CMOS active sensor ASIC design; (3) the FPGA-based DAQ system of the CLICpix chip. This paper, based on the experience from the above projects, introduces briefly UVM and presents a set of tips and advices applicable at different stages of the verification process-cycle.

Distributed Motor Controller (DMC) for Operation in Extreme Environments

NASA Technical Reports Server (NTRS)

McKinney, Colin M.; Yager, Jeremy A.; Mojarradi, Mohammad M.; Some, Rafi; Sirota, Allen; Kopf, Ted; Stern, Ryan; Hunter, Don

2012-01-01

This paper presents an extreme environment capable Distributed Motor Controller (DMC) module suitable for operation with a distributed architecture of future spacecraft systems. This motor controller is designed to be a bus-based electronics module capable of operating a single Brushless DC motor in extreme space environments: temperature (-120 C to +85 C required, -180 C to +100 C stretch goal); radiation (>;20K required, >;100KRad stretch goal); >;360 cycles of operation. Achieving this objective will result in a scalable modular configuration for motor control with enhanced reliability that will greatly lower cost during the design, fabrication and ATLO phases of future missions. Within the heart of the DMC lies a pair of cold-capable Application Specific Integrated Circuits (ASICs) and a Field Programmable Gate Array (FPGA) that enable its miniaturization and operation in extreme environments. The ASICs are fabricated in the IBM 0.5 micron Silicon Germanium (SiGe) BiCMOS process and are comprised of Analog circuitry to provide telemetry information, sensor interface, and health and status of DMC. The FPGA contains logic to provide motor control, status monitoring and spacecraft interface. The testing and characterization of these ASICs have yielded excellent functionality in cold temperatures (-135 C). The DMC module has demonstrated successful operation of a motor at temperature.

A 4×8-Gbps VCSEL array driver ASIC and integration with a custom array transmitter module for the LHC front-end transmission

DOE Office of Scientific and Technical Information (OSTI.GOV)

Guo, Di; Liu, Chonghan; Chen, Jinghong

This paper describes the design, fabrication and experiment results of a 4×8-Gbps Vertical-Cavity Surface-Emitting Laser (VCSEL) array driver ASIC with the adjustable active-shunt peaking technique and the novel balanced output structure under the Silicon-on-Sapphire (SOS) process, and a custom array optical transmitter module, featuring a compact size of 10 mm×15 mm×5.3 mm. Both the array driver ASIC and the module have been fully tested after integration as a complete parallel transmitter. Optical eye diagram of each channel passes the eye mask at 8 Gbps/ch with adjacent channel working simultaneously with a power consumption of 150 mW/ch. As a result, themore » optical transmission of Bit-Error Rate (BER) less than 10E-12 is achieved at an aggregated data rate of 4×8-Gbps.« less

A 4×8-Gbps VCSEL array driver ASIC and integration with a custom array transmitter module for the LHC front-end transmission

DOE PAGES

Guo, Di; Liu, Chonghan; Chen, Jinghong; ...

2016-03-21

This paper describes the design, fabrication and experiment results of a 4×8-Gbps Vertical-Cavity Surface-Emitting Laser (VCSEL) array driver ASIC with the adjustable active-shunt peaking technique and the novel balanced output structure under the Silicon-on-Sapphire (SOS) process, and a custom array optical transmitter module, featuring a compact size of 10 mm×15 mm×5.3 mm. Both the array driver ASIC and the module have been fully tested after integration as a complete parallel transmitter. Optical eye diagram of each channel passes the eye mask at 8 Gbps/ch with adjacent channel working simultaneously with a power consumption of 150 mW/ch. As a result, themore » optical transmission of Bit-Error Rate (BER) less than 10E-12 is achieved at an aggregated data rate of 4×8-Gbps.« less

Microwave photonics with superconducting quantum circuits

NASA Astrophysics Data System (ADS)

Gu, Xiu; Kockum, Anton Frisk; Miranowicz, Adam; Liu, Yu-xi; Nori, Franco

2017-11-01

In the past 20 years, impressive progress has been made both experimentally and theoretically in superconducting quantum circuits, which provide a platform for manipulating microwave photons. This emerging field of superconducting quantum microwave circuits has been driven by many new interesting phenomena in microwave photonics and quantum information processing. For instance, the interaction between superconducting quantum circuits and single microwave photons can reach the regimes of strong, ultra-strong, and even deep-strong coupling. Many higher-order effects, unusual and less familiar in traditional cavity quantum electrodynamics with natural atoms, have been experimentally observed, e.g., giant Kerr effects, multi-photon processes, and single-atom induced bistability of microwave photons. These developments may lead to improved understanding of the counterintuitive properties of quantum mechanics, and speed up applications ranging from microwave photonics to superconducting quantum information processing. In this article, we review experimental and theoretical progress in microwave photonics with superconducting quantum circuits. We hope that this global review can provide a useful roadmap for this rapidly developing field.

Digitally Programmable Analogue Circuits for Sensor Conditioning Systems

PubMed Central

Zatorre, Guillermo; Medrano, Nicolás; Sanz, María Teresa; Aldea, Concepción; Calvo, Belén; Celma, Santiago

2009-01-01

This work presents two current-mode integrated circuits designed for sensor signal preprocessing in embedded systems. The proposed circuits have been designed to provide good signal transfer and fulfill their function, while minimizing the load effects due to building complex conditioning architectures. The processing architecture based on the proposed building blocks can be reconfigured through digital programmability. Thus, sensor useful range can be expanded, changes in the sensor operation can be compensated for and furthermore, undesirable effects such as device mismatching and undesired physical magnitudes sensor sensibilities are reduced. The circuits were integrated using a 0.35 μm standard CMOS process. Experimental measurements, load effects and a study of two different tuning strategies are presented. From these results, system performance is tested in an application which entails extending the linear range of a magneto-resistive sensor. Circuit area, average power consumption and programmability features allow these circuits to be included in embedded sensing systems as a part of the analogue conditioning components. PMID:22412331

Microwave GaAs Integrated Circuits On Quartz Substrates

NASA Technical Reports Server (NTRS)

Siegel, Peter H.; Mehdi, Imran; Wilson, Barbara

1994-01-01

Integrated circuits for use in detecting electromagnetic radiation at millimeter and submillimeter wavelengths constructed by bonding GaAs-based integrated circuits onto quartz-substrate-based stripline circuits. Approach offers combined advantages of high-speed semiconductor active devices made only on epitaxially deposited GaAs substrates with low-dielectric-loss, mechanically rugged quartz substrates. Other potential applications include integration of antenna elements with active devices, using carrier substrates other than quartz to meet particular requirements using lifted-off GaAs layer in membrane configuration with quartz substrate supporting edges only, and using lift-off technique to fabricate ultrathin discrete devices diced separately and inserted into predefined larger circuits. In different device concept, quartz substrate utilized as transparent support for GaAs devices excited from back side by optical radiation.

Unidirectional invisibility induced by parity-time symmetric circuit

NASA Astrophysics Data System (ADS)

Lv, Bo; Fu, Jiahui; Wu, Bian; Li, Rujiang; Zeng, Qingsheng; Yin, Xinhua; Wu, Qun; Gao, Lei; Chen, Wan; Wang, Zhefei; Liang, Zhiming; Li, Ao; Ma, Ruyu

2017-01-01

Parity-time (PT) symmetric structures present the unidirectional invisibility at the spontaneous PT-symmetry breaking point. In this paper, we propose a PT-symmetric circuit consisting of a resistor and a microwave tunnel diode (TD) which represent the attenuation and amplification, respectively. Based on the scattering matrix method, the circuit can exhibit an ideal unidirectional performance at the spontaneous PT-symmetry breaking point by tuning the transmission lines between the lumped elements. Additionally, the resistance of the reactance component can alter the bandwidth of the unidirectional invisibility flexibly. Furthermore, the electromagnetic simulation for the proposed circuit validates the unidirectional invisibility and the synchronization with the input energy well. Our work not only provides an unidirectional invisible circuit based on PT-symmetry, but also proposes a potential solution for the extremely selective filter or cloaking applications.

Multiplier less high-speed squaring circuit for binary numbers

NASA Astrophysics Data System (ADS)

Sethi, Kabiraj; Panda, Rutuparna

2015-03-01

The squaring operation is important in many applications in signal processing, cryptography etc. In general, squaring circuits reported in the literature use fast multipliers. A novel idea of a squaring circuit without using multipliers is proposed in this paper. Ancient Indian method used for squaring decimal numbers is extended here for binary numbers. The key to our success is that no multiplier is used. Instead, one squaring circuit is used. The hardware architecture of the proposed squaring circuit is presented. The design is coded in VHDL and synthesised and simulated in Xilinx ISE Design Suite 10.1 (Xilinx Inc., San Jose, CA, USA). It is implemented in Xilinx Vertex 4vls15sf363-12 device (Xilinx Inc.). The results in terms of time delay and area is compared with both modified Booth's algorithm and squaring circuit using Vedic multipliers. Our proposed squaring circuit seems to have better performance in terms of both speed and area.

Photonic Integrated Circuit (PIC) Device Structures: Background, Fabrication Ecosystem, Relevance to Space Systems Applications, and Discussion of Related Radiation Effects

NASA Technical Reports Server (NTRS)

Alt, Shannon

2016-01-01

Electronic integrated circuits are considered one of the most significant technological advances of the 20th century, with demonstrated impact in their ability to incorporate successively higher numbers transistors and construct electronic devices onto a single CMOS chip. Photonic integrated circuits (PICs) exist as the optical analog to integrated circuits; however, in place of transistors, PICs consist of numerous scaled optical components, including such "building-block" structures as waveguides, MMIs, lasers, and optical ring resonators. The ability to construct electronic and photonic components on a single microsystems platform offers transformative potential for the development of technologies in fields including communications, biomedical device development, autonomous navigation, and chemical and atmospheric sensing. Developing on-chip systems that provide new avenues for integration and replacement of bulk optical and electro-optic components also reduces size, weight, power and cost (SWaP-C) limitations, which are important in the selection of instrumentation for specific flight projects. The number of applications currently emerging for complex photonics systems-particularly in data communications-warrants additional investigations when considering reliability for space systems development. This Body of Knowledge document seeks to provide an overview of existing integrated photonics architectures; the current state of design, development, and fabrication ecosystems in the United States and Europe; and potential space applications, with emphasis given to associated radiation effects and reliability.

Magnetomicrofluidics Circuits for Organizing Bioparticle Arrays

NASA Astrophysics Data System (ADS)

Abedini-Nassab, Roozbeh

Single-cell analysis (SCA) tools have important applications in the analysis of phenotypic heterogeneity, which is difficult or impossible to analyze in bulk cell culture or patient samples. SCA tools thus have a myriad of applications ranging from better credentialing of drug therapies to the analysis of rare latent cells harboring HIV infection or in Cancer. However, existing SCA systems usually lack the required combination of programmability, flexibility, and scalability necessary to enable the study of cell behaviors and cell-cell interactions at the scales sufficient to analyze extremely rare events. To advance the field, I have developed a novel, programmable, and massively-parallel SCA tool which is based on the principles of computer circuits. By integrating these magnetic circuits with microfluidics channels, I developed a platform that can organize a large number of single particles into an array in a controlled manner. My magnetophoretic circuits use passive elements constructed in patterned magnetic thin films to move cells along programmed tracks with an external rotating magnetic field. Cell motion along these tracks is analogous to the motion of charges in an electrical conductor, following a rule similar to Ohm's law. I have also developed asymmetric conductors, similar to electrical diodes, and storage sites for cells that behave similarly to electrical capacitors. I have also developed magnetophoretic circuits which use an overlaid pattern of microwires to switch single cells between different tracks. This switching mechanism, analogous to the operation of electronic transistors, is achieved by establishing a semiconducting gap in the magnetic pattern which can be changed from an insulating state to a conducting state by application of electrical current to an overlaid electrode. I performed an extensive study on the operation of transistors to optimize their geometry and minimize the required gate currents. By combining these elements into

Ultralow-power organic complementary circuits.

PubMed

Klauk, Hagen; Zschieschang, Ute; Pflaum, Jens; Halik, Marcus

2007-02-15

The prospect of using low-temperature processable organic semiconductors to implement transistors, circuits, displays and sensors on arbitrary substrates, such as glass or plastics, offers enormous potential for a wide range of electronic products. Of particular interest are portable devices that can be powered by small batteries or by near-field radio-frequency coupling. The main problem with existing approaches is the large power consumption of conventional organic circuits, which makes battery-powered applications problematic, if not impossible. Here we demonstrate an organic circuit with very low power consumption that uses a self-assembled monolayer gate dielectric and two different air-stable molecular semiconductors (pentacene and hexadecafluorocopperphthalocyanine, F16CuPc). The monolayer dielectric is grown on patterned metal gates at room temperature and is optimized to provide a large gate capacitance and low gate leakage currents. By combining low-voltage p-channel and n-channel organic thin-film transistors in a complementary circuit design, the static currents are reduced to below 100 pA per logic gate. We have fabricated complementary inverters, NAND gates, and ring oscillators that operate with supply voltages between 1.5 and 3 V and have a static power consumption of less than 1 nW per logic gate. These organic circuits are thus well suited for battery-powered systems such as portable display devices and large-surface sensor networks as well as for radio-frequency identification tags with extended operating range.

Flip-flop resolving time test circuit

NASA Technical Reports Server (NTRS)

Rosenberger, F.; Chaney, T. J.

1982-01-01

Integrated circuit (IC) flip-flop resolving time parameters are measured by wafer probing, without need of dicing or bonding, throught the incorporation of test structures on an IC together with the flip-flop to be measured. Several delays that are fabricated as part of the test circuit, including a voltage-controlled delay with a resolution of a few picosecs, are calibrated as part of the test procedure by integrating them into, and out of, the delay path of a ring oscillator. Each of the delay values is calculated by subtracting the period of the ring oscillator with the delay omitted from the period with the delay included. The delay measurement technique is sufficiently general for other applications. The technique is illustrated for the case of the flip-flop parameters of a 5-micron feature size NMOS circuit.

Dynamics, Analysis and Implementation of a Multiscroll Memristor-Based Chaotic Circuit

NASA Astrophysics Data System (ADS)

Alombah, N. Henry; Fotsin, Hilaire; Ngouonkadi, E. B. Megam; Nguazon, Tekou

This article introduces a novel four-dimensional autonomous multiscroll chaotic circuit which is derived from the actual simplest memristor-based chaotic circuit. A fourth circuit element — another inductor — is introduced to generate the complex behavior observed. A systematic study of the chaotic behavior is performed with the help of some nonlinear tools such as Lyapunov exponents, phase portraits, and bifurcation diagrams. Multiple scroll attractors are observed in Matlab, Pspice environments and also experimentally. We also observe the phenomenon of antimonotonicity, periodic and chaotic bubbles, multiple periodic-doubling bifurcations, Hopf bifurcations, crises and the phenomenon of intermittency. The chaotic dynamics of this circuit is realized by laboratory experiments, Pspice simulations, numerical and analytical investigations. It is observed that the results from the three environments agree to a great extent. This topology is likely convenient to be used to intentionally generate chaos in memristor-based chaotic circuit applications, given the fact that multiscroll chaotic systems have found important applications as broadband signal generators, pseudorandom number generators for communication engineering and also in biometric authentication.

Design and implementation of GaAs HBT circuits with ACME

NASA Technical Reports Server (NTRS)

Hutchings, Brad L.; Carter, Tony M.

1993-01-01

GaAs HBT circuits offer high performance (5-20 GHz) and radiation hardness (500 Mrad) that is attractive for space applications. ACME is a CAD tool specifically developed for HBT circuits. ACME implements a novel physical schematic-capture design technique where designers simultaneously view the structure and physical organization of a circuit. ACME's design interface is similar to schematic capture; however, unlike conventional schematic capture, designers can directly control the physical placement of both function and interconnect at the schematic level. In addition, ACME provides design-time parasitic extraction, complex wire models, and extensions to Multi-Chip Modules (MCM's). A GaAs HBT gate-array and semi-custom circuits have been developed with ACME; several circuits have been fabricated and found to be fully functional .

Algorithms and architecture for multiprocessor based circuit simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deutsch, J.T.

Accurate electrical simulation is critical to the design of high performance integrated circuits. Logic simulators can verify function and give first-order timing information. Switch level simulators are more effective at dealing with charge sharing than standard logic simulators, but cannot provide accurate timing information or discover DC problems. Delay estimation techniques and cell level simulation can be used in constrained design methods, but must be tuned for each application, and circuit simulation must still be used to generate the cell models. None of these methods has the guaranteed accuracy that many circuit designers desire, and none can provide detailed waveformmore » information. Detailed electrical-level simulation can predict circuit performance if devices and parasitics are modeled accurately. However, the computational requirements of conventional circuit simulators make it impractical to simulate current large circuits. In this dissertation, the implementation of Iterated Timing Analysis (ITA), a relaxation-based technique for accurate circuit simulation, on a special-purpose multiprocessor is presented. The ITA method is an SOR-Newton, relaxation-based method which uses event-driven analysis and selective trace to exploit the temporal sparsity of the electrical network. Because event-driven selective trace techniques are employed, this algorithm lends itself to implementation on a data-driven computer.« less

ADDER CIRCUIT

DOEpatents

Jacobsohn, D.H.; Merrill, L.C.

1959-01-20

An improved parallel addition unit is described which is especially adapted for use in electronic digital computers and characterized by propagation of the carry signal through each of a plurality of denominationally ordered stages within a minimum time interval. In its broadest aspects, the invention incorporates a fast multistage parallel digital adder including a plurality of adder circuits, carry-propagation circuit means in all but the most significant digit stage, means for conditioning each carry-propagation circuit during the time period in which information is placed into the adder circuits, and means coupling carry-generation portions of thc adder circuit to the carry propagating means.

Error-rate prediction for programmable circuits: methodology, tools and studied cases

NASA Astrophysics Data System (ADS)

Velazco, Raoul

2013-05-01

This work presents an approach to predict the error rates due to Single Event Upsets (SEU) occurring in programmable circuits as a consequence of the impact or energetic particles present in the environment the circuits operate. For a chosen application, the error-rate is predicted by combining the results obtained from radiation ground testing and the results of fault injection campaigns performed off-beam during which huge numbers of SEUs are injected during the execution of the studied application. The goal of this strategy is to obtain accurate results about different applications' error rates, without using particle accelerator facilities, thus significantly reducing the cost of the sensitivity evaluation. As a case study, this methodology was applied a complex processor, the Power PC 7448 executing a program issued from a real space application and a crypto-processor application implemented in an SRAM-based FPGA and accepted to be embedded in the payload of a scientific satellite of NASA. The accuracy of predicted error rates was confirmed by comparing, for the same circuit and application, predictions with measures issued from radiation ground testing performed at the cyclotron Cyclone cyclotron of HIF (Heavy Ion Facility) of Louvain-la-Neuve (Belgium).

Characterization of Novel Thin-Films and Structures for Integrated Circuit and Photovoltaic Applications

NASA Astrophysics Data System (ADS)

Zhao, Zhao

Thin films have been widely used in various applications. This research focuses on the characterization of novel thin films in the integrated circuits and photovoltaic techniques. The ion implanted layer in silicon can be treated as ion implanted thin film, which plays an essential role in the integrated circuits fabrication. Novel rapid annealing methods, i.e. microwave annealing and laser annealing, are conducted to activate ion dopants and repair the damages, and then are compared with the conventional rapid thermal annealing (RTA). In terms of As+ and P+ implanted Si, the electrical and structural characterization confirms that the microwave and laser annealing can achieve more efficient dopant activation and recrystallization than conventional RTA. The efficient dopant activation in microwave annealing is attributed to ion hopping under microwave field, while the liquid phase growth in laser annealing provides its efficient dopant activation. The characterization of dopants diffusion shows no visible diffusion after microwave annealing, some extent of end range of diffusion after RTA, and significant dopant diffusion after laser annealing. For photovoltaic applications, an indium-free novel three-layer thin-film structure (transparent composited electrode (TCE)) is demonstrated as a promising transparent conductive electrode for solar cells. The characterization of TCE mainly focuses on its optical and electrical properties. Transfer matrix method for optical transmittance calculation is validated and proved to be a desirable method for predicting transmittance of TCE containing continuous metal layer, and can estimate the trend of transmittance as the layer thickness changes. TiO2/Ag/TiO2 (TAgT) electrode for organic solar cells (OSCs) is then designed using numerical simulation and shows much higher Haacke figure of merit than indium tin oxide (ITO). In addition, TAgT based OSC shows better performance than ITO based OSC when compatible hole transfer layer

Color Coding of Circuit Quantities in Introductory Circuit Analysis Instruction

ERIC Educational Resources Information Center

Reisslein, Jana; Johnson, Amy M.; Reisslein, Martin

2015-01-01

Learning the analysis of electrical circuits represented by circuit diagrams is often challenging for novice students. An open research question in electrical circuit analysis instruction is whether color coding of the mathematical symbols (variables) that denote electrical quantities can improve circuit analysis learning. The present study…

Design of an improved RCD buffer circuit for full bridge circuit

NASA Astrophysics Data System (ADS)

Yang, Wenyan; Wei, Xueye; Du, Yongbo; Hu, Liang; Zhang, Liwei; Zhang, Ou

2017-05-01

In the full bridge inverter circuit, when the switch tube suddenly opened or closed, the inductor current changes rapidly. Due to the existence of parasitic inductance of the main circuit. Therefore, the surge voltage between drain and source of the switch tube can be generated, which will have an impact on the switch and the output voltage. In order to ab sorb the surge voltage. An improve RCD buffer circuit is proposed in the paper. The peak energy will be absorbed through the buffer capacitor of the circuit. The part energy feedback to the power supply, another part release through the resistor in the form of heat, and the circuit can absorb the voltage spikes. This paper analyzes the process of the improved RCD snubber circuit, According to the specific parameters of the main circuit, a reasonable formula for calculating the resistance capacitance is given. A simulation model will be modulated in Multisim, which compared the waveform of tube voltage and the output waveform of the circuit without snubber circuit with the improved RCD snubber circuit. By comparing and analyzing, it is proved that the improved buffer circuit can absorb surge voltage. Finally, experiments are demonstrated to validate that the correctness of the RC formula and the improved RCD snubber circuit.

Nucleic acids for the rational design of reaction circuits.

PubMed

Padirac, Adrien; Fujii, Teruo; Rondelez, Yannick

2013-08-01

Nucleic acid-based circuits are rationally designed in vitro assemblies that can perform complex preencoded programs. They can be used to mimic in silico computations. Recent works emphasized the modularity and robustness of these circuits, which allow their scaling-up. Another new development has led to dynamic, time-responsive systems that can display emergent behaviors like oscillations. These are closely related to biological architectures and provide an in vitro model of in vivo information processing. Nucleic acid circuits have already been used to handle various processes for technological or biotechnological purposes. Future applications of these chemical smart systems will benefit from the rapidly growing ability to design, construct, and model nucleic acid circuits of increasing size. Copyright © 2012 Elsevier Ltd. All rights reserved.

A silicon technology for millimeter-wave monolithic circuits

NASA Astrophysics Data System (ADS)

Stabile, P. J.; Rosen, A.

1984-12-01

A silicon millimeter-wave integrated-circuit (SIMMWIC) technology that includes high-energy ion implantation and pulsed-laser annealing, secondary ion mass spectrometry (SIMS) profile diagnostics, and novel wafer thinning has been developed. This technology has been applied to a SIMMWIC single-pole single-throw (SPST) switch and to IMPATT and p-i-n diode fabrication schemes. Thus, the SIMMWIC technology is a proven base for monolithic millimeter-wave sources and control circuit applications.

Tolerance of the High Energy X-ray Imaging Technology ASIC to potentially destructive radiation processes in Earth-orbit-equivalent environments

NASA Astrophysics Data System (ADS)

Ryan, D. F.; Baumgartner, W. H.; Wilson, M.; Benmoussa, A.; Campola, M.; Christe, S. D.; Gissot, S.; Jones, L.; Newport, J.; Prydderch, M.; Richards, S.; Seller, P.; Shih, A. Y.; Thomas, S.

2018-02-01

The High Energy X-ray Imaging Technology (HEXITEC) ASIC is designed on a 0.35 μm CMOS process to read out CdTe or CZT detectors and hence provide fine-pixellated spectroscopic imaging in the range 2-200 keV. In this paper, we examine the tolerance of HEXITEC to both potentially destructive cumulative and single event radiation effects. Bare ASICs are irradiated with X-rays up to a total ionising dose (TID) of 1 Mrad (SiO2) and bombarded with heavy ions with linear energy transfer (LET) up to 88.3 MeV mg-1 cm-2. HEXITEC is shown to operate reliably below a TID of 150 krad, have immunity to fatal single event latchup (SEL) and have high tolerance to non-fatal SEL up to LETs of at least 88.3 MeV mg-1 cm-2. The results are compared to predictions of TID and SELs for various Earth-orbits and aluminium shielding thicknesses. It is found that HEXITEC's radiation tolerance to both potentially destructive cumulative and single event effects is sufficient to reliably operate in these environments with moderate shielding.

Using Spare Logic Resources To Create Dynamic Test Points

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor

2011-01-01

A technique has been devised to enable creation of a dynamic set of test points in an embedded digital electronic system. As a result, electronics contained in an application specific circuit [e.g., gate array, field programmable gate array (FPGA)] can be internally probed, even when contained in a closed housing during all phases of test. In the present technique, the test points are not fixed and limited to a small number; the number of test points can vastly exceed the number of buffers or pins, resulting in a compact footprint. Test points are selected by means of spare logic resources within the ASIC(s) and/or FPGA(s). A register is programmed with a command, which is used to select the signals that are sent off-chip and out of the housing for monitoring by test engineers and external test equipment. The register can be commanded by any suitable means: for example, it could be commanded through a command port that would normally be used in the operation of the system. In the original application of the technique, commanding of the register is performed via a MIL-STD-1553B communication subsystem.

Architecture design of the multi-functional wavelet-based ECG microprocessor for realtime detection of abnormal cardiac events.

PubMed

Cheng, Li-Fang; Chen, Tung-Chien; Chen, Liang-Gee

2012-01-01

Most of the abnormal cardiac events such as myocardial ischemia, acute myocardial infarction (AMI) and fatal arrhythmia can be diagnosed through continuous electrocardiogram (ECG) analysis. According to recent clinical research, early detection and alarming of such cardiac events can reduce the time delay to the hospital, and the clinical outcomes of these individuals can be greatly improved. Therefore, it would be helpful if there is a long-term ECG monitoring system with the ability to identify abnormal cardiac events and provide realtime warning for the users. The combination of the wireless body area sensor network (BASN) and the on-sensor ECG processor is a possible solution for this application. In this paper, we aim to design and implement a digital signal processor that is suitable for continuous ECG monitoring and alarming based on the continuous wavelet transform (CWT) through the proposed architectures--using both programmable RISC processor and application specific integrated circuits (ASIC) for performance optimization. According to the implementation results, the power consumption of the proposed processor integrated with an ASIC for CWT computation is only 79.4 mW. Compared with the single-RISC processor, about 91.6% of the power reduction is achieved.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, W.; Yin, J.; Li, C.

This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by amore » FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e{sup -} to 100000 e{sup -}, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)« less

SpaceWire Driver Software for Special DSPs

NASA Technical Reports Server (NTRS)

Clark, Douglas; Lux, James; Nishimoto, Kouji; Lang, Minh

2003-01-01

A computer program provides a high-level C-language interface to electronics circuitry that controls a SpaceWire interface in a system based on a space qualified version of the ADSP-21020 digital signal processor (DSP). SpaceWire is a spacecraft-oriented standard for packet-switching data-communication networks that comprise nodes connected through bidirectional digital serial links that utilize low-voltage differential signaling (LVDS). The software is tailored to the SMCS-332 application-specific integrated circuit (ASIC) (also available as the TSS901E), which provides three highspeed (150 Mbps) serial point-to-point links compliant with the proposed Institute of Electrical and Electronics Engineers (IEEE) Standard 1355.2 and equivalent European Space Agency (ESA) Standard ECSS-E-50-12. In the specific application of this software, the SpaceWire ASIC was combined with the DSP processor, memory, and control logic in a Multi-Chip Module DSP (MCM-DSP). The software is a collection of low-level driver routines that provide a simple message-passing application programming interface (API) for software running on the DSP. Routines are provided for interrupt-driven access to the two styles of interface provided by the SMCS: (1) the "word at a time" conventional host interface (HOCI); and (2) a higher performance "dual port memory" style interface (COMI).

Building robust functionality in synthetic circuits using engineered feedback regulation.

PubMed

Chen, Susan; Harrigan, Patrick; Heineike, Benjamin; Stewart-Ornstein, Jacob; El-Samad, Hana

2013-08-01

The ability to engineer novel functionality within cells, to quantitatively control cellular circuits, and to manipulate the behaviors of populations, has many important applications in biotechnology and biomedicine. These applications are only beginning to be explored. In this review, we advocate the use of feedback control as an essential strategy for the engineering of robust homeostatic control of biological circuits and cellular populations. We also describe recent works where feedback control, implemented in silico or with biological components, was successfully employed for this purpose. Copyright © 2013 Elsevier Ltd. All rights reserved.

Design methodology: edgeless 3D ASICs with complex in-pixel processing for pixel detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fahim Farah, Fahim Farah; Deptuch, Grzegorz W.; Hoff, James R.

The design methodology for the development of 3D integrated edgeless pixel detectors with in-pixel processing using Electronic Design Automation (EDA) tools is presented. A large area 3 tier 3D detector with one sensor layer and two ASIC layers containing one analog and one digital tier, is built for x-ray photon time of arrival measurement and imaging. A full custom analog pixel is 65μm x 65μm. It is connected to a sensor pixel of the same size on one side, and on the other side it has approximately 40 connections to the digital pixel. A 32 x 32 edgeless array withoutmore » any peripheral functional blocks constitutes a sub-chip. The sub-chip is an indivisible unit, which is further arranged in a 6 x 6 array to create the entire 1.248cm x 1.248cm ASIC. Each chip has 720 bump-bond I/O connections, on the back of the digital tier to the ceramic PCB. All the analog tier power and biasing is conveyed through the digital tier from the PCB. The assembly has no peripheral functional blocks, and hence the active area extends to the edge of the detector. This was achieved by using a few flavors of almost identical analog pixels (minimal variation in layout) to allow for peripheral biasing blocks to be placed within pixels. The 1024 pixels within a digital sub-chip array have a variety of full custom, semi-custom and automated timing driven functional blocks placed together. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout. The methodology uses the Cadence design platform, however it is not limited to this tool.« less

Design methodology: edgeless 3D ASICs with complex in-pixel processing for pixel detectors

NASA Astrophysics Data System (ADS)

Fahim, Farah; Deptuch, Grzegorz W.; Hoff, James R.; Mohseni, Hooman

2015-08-01

The design methodology for the development of 3D integrated edgeless pixel detectors with in-pixel processing using Electronic Design Automation (EDA) tools is presented. A large area 3 tier 3D detector with one sensor layer and two ASIC layers containing one analog and one digital tier, is built for x-ray photon time of arrival measurement and imaging. A full custom analog pixel is 65μm x 65μm. It is connected to a sensor pixel of the same size on one side, and on the other side it has approximately 40 connections to the digital pixel. A 32 x 32 edgeless array without any peripheral functional blocks constitutes a sub-chip. The sub-chip is an indivisible unit, which is further arranged in a 6 x 6 array to create the entire 1.248cm x 1.248cm ASIC. Each chip has 720 bump-bond I/O connections, on the back of the digital tier to the ceramic PCB. All the analog tier power and biasing is conveyed through the digital tier from the PCB. The assembly has no peripheral functional blocks, and hence the active area extends to the edge of the detector. This was achieved by using a few flavors of almost identical analog pixels (minimal variation in layout) to allow for peripheral biasing blocks to be placed within pixels. The 1024 pixels within a digital sub-chip array have a variety of full custom, semi-custom and automated timing driven functional blocks placed together. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout. The methodology uses the Cadence design platform, however it is not limited to this tool.

Optimized structural designs for stretchable silicon integrated circuits.

PubMed

Kim, Dae-Hyeong; Liu, Zhuangjian; Kim, Yun-Soung; Wu, Jian; Song, Jizhou; Kim, Hoon-Sik; Huang, Yonggang; Hwang, Keh-Chih; Zhang, Yongwei; Rogers, John A

2009-12-01

Materials and design strategies for stretchable silicon integrated circuits that use non-coplanar mesh layouts and elastomeric substrates are presented. Detailed experimental and theoretical studies reveal many of the key underlying aspects of these systems. The results shpw, as an example, optimized mechanics and materials for circuits that exhibit maximum principal strains less than 0.2% even for applied strains of up to approximately 90%. Simple circuits, including complementary metal-oxide-semiconductor inverters and n-type metal-oxide-semiconductor differential amplifiers, validate these designs. The results suggest practical routes to high-performance electronics with linear elastic responses to large strain deformations, suitable for diverse applications that are not readily addressed with conventional wafer-based technologies.

Modular electron transfer circuits for synthetic biology

PubMed Central

Agapakis, Christina M

2010-01-01

Electron transfer is central to a wide range of essential metabolic pathways, from photosynthesis to fermentation. The evolutionary diversity and conservation of proteins that transfer electrons makes these pathways a valuable platform for engineered metabolic circuits in synthetic biology. Rational engineering of electron transfer pathways containing hydrogenases has the potential to lead to industrial scale production of hydrogen as an alternative source of clean fuel and experimental assays for understanding the complex interactions of multiple electron transfer proteins in vivo. We designed and implemented a synthetic hydrogen metabolism circuit in Escherichia coli that creates an electron transfer pathway both orthogonal to and integrated within existing metabolism. The design of such modular electron transfer circuits allows for facile characterization of in vivo system parameters with applications toward further engineering for alternative energy production. PMID:21468209

Lithium Circuit Test Section Design and Fabrication

NASA Technical Reports Server (NTRS)

Godfroy, Thomas; Garber, Anne

2006-01-01

The Early Flight Fission - Test Facilities (EFF-TF) team has designed and built an actively pumped lithium flow circuit. Modifications were made to a circuit originally designed for NaK to enable the use of lithium that included application specific instrumentation and hardware. Component scale freeze/thaw tests were conducted to both gain experience with handling and behavior of lithium in solid and liquid form and to supply anchor data for a Generalized Fluid System Simulation Program (GFSSP) model that was modified to include the physics for freeze/thaw transitions. Void formation was investigated. The basic circuit components include: reactor segment, lithium to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. This paper will discuss the overall system design and build and the component testing findings.

Lithium Circuit Test Section Design and Fabrication

NASA Astrophysics Data System (ADS)

Godfroy, Thomas; Garber, Anne; Martin, James

2006-01-01

The Early Flight Fission - Test Facilities (EFF-TF) team has designed and built an actively pumped lithium flow circuit. Modifications were made to a circuit originally designed for NaK to enable the use of lithium that included application specific instrumentation and hardware. Component scale freeze/thaw tests were conducted to both gain experience with handling and behavior of lithium in solid and liquid form and to supply anchor data for a Generalized Fluid System Simulation Program (GFSSP) model that was modified to include the physics for freeze/thaw transitions. Void formation was investigated. The basic circuit components include: reactor segment, lithium to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. This paper discusses the overall system design and build and the component testing findings.

Silicon-On-Insulator (SOI) Devices and Mixed-Signal Circuits for Extreme Temperature Applications

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad; Elbuluk, Malik

2008-01-01

Electronic systems in planetary exploration missions and in aerospace applications are expected to encounter extreme temperatures and wide thermal swings in their operational environments. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of the missions. Electronic parts based on silicon-on-insulator (SOI) technology are known, based on device structure, to provide faster switching, consume less power, and offer better radiation-tolerance compared to their silicon counterparts. They also exhibit reduced current leakage and are often tailored for high temperature operation. However, little is known about their performance at low temperature. The performance of several SOI devices and mixed-signal circuits was determined under extreme temperatures, cold-restart, and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these devices for use in space exploration missions under extreme temperatures. The experimental results obtained on selected SOI devices are presented and discussed in this paper.

Semicustom integrated circuits and the standard transistor array radix (STAR)

NASA Technical Reports Server (NTRS)

Edge, T. M.

1977-01-01