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Sample records for circuit test generation

  1. Delay test generation for synchronous sequential circuits

    NASA Astrophysics Data System (ADS)

    Devadas, Srinivas

    1989-05-01

    We address the problem of generating tests for delay faults in non-scan synchronous sequential circuits. Delay test generation for sequential circuits is a considerably more difficult problem than delay testing of combinational circuits and has received much less attention. In this paper, we present a method for generating test sequences to detect delay faults in sequential circuits using the stuck-at fault sequential test generator STALLION. The method is complete in that it will generate a delay test sequence for a targeted fault given sufficient CPU time, if such a sequence exists. We term faults for which no delay test sequence exists, under out test methodology, sequentially delay redundant. We describe means of eliminating sequential delay redundancies in logic circuits. We present a partial-scan methodology for enhancing the testability of difficult-to-test of untestable sequential circuits, wherein a small number of flip-flops are selected and made controllable/observable. The selection process guarantees the elimination of all sequential delay redundancies. We show that an intimate relationship exists between state assignment and delay testability of a sequential machine. We describe a state assignment algorithm for the synthesis of sequential machines with maximal delay fault testability. Preliminary experimental results using the test generation, partial-scan and synthesis algorithm are presented.

  2. Generating circuit tests by exploiting designed behavior

    NASA Astrophysics Data System (ADS)

    Shirley, Mark H.

    1988-12-01

    Generating tests for sequential devices is one of the hardest problems in designing and manufacturing digital circuits. This task is difficult primarily because internal components are accessible only indirectly, forcing a test generator to use the surrounding components collectively as a probe for detecting faults. This in turn forces the test generator to reason about complex interactions between the behaviors of these surrounding components. Current automated solutions are becoming ineffective as designs grow larger and more complex. Yet, despite the complexity, human experts remain remarkably successful, in part, because they use knowledge from many sources and use a variety of reasoning techniques. This thesis exploits several kinds of expert knowledge about circuits and test generation not used by the current algorithms. First, many test generation problems can be solved efficiently using operation relations, a novel representation of circuit behavior that connects internal component operations with directly executable circuit operations. Operation relations can be computed efficiently for sequential circuits that provide few operations at their interfaces by searching traces of simulated circuit behavior. Second, experts write test programs rather than test vectors because programs are a more readable and compact representation for tests than vectors are. Test programs can be constructed automatically by merging test program fragments using expert supplied goal-refined rules and domain independent planning techniques from artificial intelligence.

  3. Test generation for highly sequential circuits

    NASA Astrophysics Data System (ADS)

    Ghosh, Abhijit; Devadas, Srinivas; Newton, A. Richard

    1989-08-01

    We address the problem of generating test sequences for stuck-at faults in non-scan synchronous sequential circuits. We present a novel test procedure that exploits both the structure of the combinational logic in the circuit as well as the sequential behavior of the circuit. In contrast to previous approaches, we decompose the problem of sequential test generation into three subproblems of combinational test generation, fault-free state justification and fault-free state differentiation. We describe fast algorithms for state justification and state differentiation using the ON-sets and OFF-sets of flip-flop inputs and primary outputs. The decomposition of the testing problems into three subproblems rather than the traditional two, performing the justification and differentiation steps on the fault free rather than the faulty machine and the use of efficient techniques for cube intersection results in significant performance improvements over previous approaches.

  4. Test signal generation for analog circuits

    NASA Astrophysics Data System (ADS)

    Burdiek, B.; Mathis, W.

    2003-05-01

    In this paper a new test signal generation approach for general analog circuits based on the variational calculus and modern control theory methods is presented. The computed transient test signals also called test stimuli are optimal with respect to the detection of a given fault set by means of a predefined merit functional representing a fault detection criterion. The test signal generation problem of finding optimal test stimuli detecting all faults form the fault set is formulated as an optimal control problem. The solution of the optimal control problem representing the test stimuli is computed using an optimization procedure. The optimization procedure is based on the necessary conditions for optimality like the maximum principle of Pontryagin and adjoint circuit equations.

  5. A hierarchical approach to test generation for CMOS VLSI circuits

    NASA Astrophysics Data System (ADS)

    Weening, Edward Christiaan

    A hierarchical approach to the automatic test pattern generation for large digital VLSI circuits, fabricated in CMOS technology, is developed and implemented. The use of information on the circuit's hierarchy, which is readily available from most modern CAD (Computer Aided Design) systems, speeds up the test generation process considerably and enhances the quality of the tests generated. The hierarchical test generation tool can also be integrated in future CAD systems making test generation and testability enhancement during circuit design feasible. The hierarchical approach is described at the switch, functional, and behavioral level. A test pattern generation algorithm at the switch level is presented. Test generation and fault simulation algorithms both using OBDD (Ordered Binary Decision Diagram) functional descriptions of the circuit modules are presented. A test plan generation method at the behavioral level is presented. Practical results show that the hierarchical approach to test generation is more efficient than a conventional, non-hierarchical approach, especially for switch level faults. The results also show that the use of Design For Testability (DFT) circuitry is supported at the behavioral level.

  6. Capacitive charge generation apparatus and method for testing circuits

    DOEpatents

    Cole, Jr., Edward I.; Peterson, Kenneth A.; Barton, Daniel L.

    1998-01-01

    An electron beam apparatus and method for testing a circuit. The electron beam apparatus comprises an electron beam incident on an outer surface of an insulating layer overlying one or more electrical conductors of the circuit for generating a time varying or alternating current electrical potential on the surface; and a measurement unit connected to the circuit for measuring an electrical signal capacitively coupled to the electrical conductors to identify and map a conduction state of each of the electrical conductors, with or without an electrical bias signal being applied to the circuit. The electron beam apparatus can further include a secondary electron detector for forming a secondary electron image for registration with a map of the conduction state of the electrical conductors. The apparatus and method are useful for failure analysis or qualification testing to determine the presence of any open-circuits or short-circuits, and to verify the continuity or integrity of electrical conductors buried below an insulating layer thickness of 1-100 .mu.m or more without damaging or breaking down the insulating layer. The types of electrical circuits that can be tested include integrated circuits, multi-chip modules, printed circuit boards and flexible printed circuits.

  7. Capacitive charge generation apparatus and method for testing circuits

    DOEpatents

    Cole, E.I. Jr.; Peterson, K.A.; Barton, D.L.

    1998-07-14

    An electron beam apparatus and method for testing a circuit are disclosed. The electron beam apparatus comprises an electron beam incident on an outer surface of an insulating layer overlying one or more electrical conductors of the circuit for generating a time varying or alternating current electrical potential on the surface; and a measurement unit connected to the circuit for measuring an electrical signal capacitively coupled to the electrical conductors to identify and map a conduction state of each of the electrical conductors, with or without an electrical bias signal being applied to the circuit. The electron beam apparatus can further include a secondary electron detector for forming a secondary electron image for registration with a map of the conduction state of the electrical conductors. The apparatus and method are useful for failure analysis or qualification testing to determine the presence of any open-circuits or short-circuits, and to verify the continuity or integrity of electrical conductors buried below an insulating layer thickness of 1-100 {micro}m or more without damaging or breaking down the insulating layer. The types of electrical circuits that can be tested include integrated circuits, multi-chip modules, printed circuit boards and flexible printed circuits. 7 figs.

  8. A Single Input Change Test Pattern Generator for Sequential Circuits

    NASA Astrophysics Data System (ADS)

    Liang, Feng; Lei, Shaochong; Shao, Zhibiao

    An optimized Built-In Self-Test technology is proposed in this paper. A simplified algebraic model is developed to represent the configurations of single input change circuits. A novel single input change sequence generation technique is designed. It consists of a modified scan shift register, a seed storage array and a series of XOR gates. This circuitry can automatically generate single input change sequences of more unique vectors. Experimental results based on the ISCAS-89 benchmark show that the proposed method can achieve high stuck-at fault coverage with low switching activity during test applications.

  9. Functional test generation for digital circuits described with a declarative language: LUSTRE

    NASA Astrophysics Data System (ADS)

    Almahrous, Mazen

    1990-08-01

    A functional approach to the test generation problem starting from a high level description is proposed. The circuit tested is modeled, using the LUSTRE high level data flow description language. The different LUSTRE primitives are translated to a SATAN format graph in order to evaluate the testability of the circuit and to generate test sequences. Another method of testing the complex circuits comprising an operative part and a control part is defined. It consists of checking experiments for the control part observed through the operative part. It was applied to the automata generated from a LUSTRE description of the circuit.

  10. Integrated circuit test-port architecture and method and apparatus of test-port generation

    DOEpatents

    Teifel, John

    2016-04-12

    A method and apparatus are provided for generating RTL code for a test-port interface of an integrated circuit. In an embodiment, a test-port table is provided as input data. A computer automatically parses the test-port table into data structures and analyzes it to determine input, output, local, and output-enable port names. The computer generates address-detect and test-enable logic constructed from combinational functions. The computer generates one-hot multiplexer logic for at least some of the output ports. The one-hot multiplexer logic for each port is generated so as to enable the port to toggle between data signals and test signals. The computer then completes the generation of the RTL code.

  11. Automatic test pattern generation for logic circuits using the Boolean tree

    SciTech Connect

    Jeong Taegwon.

    1991-01-01

    The goal of this study was to develop an algorithm that can generate test patterns for combinational circuits and sequential logic circuits automatically. The new proposed algorithm generates a test pattern by using a special tree called a modified Boolean tree. In this algorithm, the construction of a modified Boolean tree is the most time-consuming step. Following the construction of a modified Boolean tree, a test pattern can be found by simply assigning a logic value 1 for even primary inputs and a logic value 0 for odd primary inputs of the constructed modified Boolean tree. The algorithm is applied to several benchmark circuits. The results showed the following: (1) for combinational circuits, the algorithm can generate test patterns 10-15% faster than the FAN algorithm, which is known as one of the most efficient algorithms to-date; (2) for sequential circuits, the algorithm shows more fault coverage than the nine valued algorithm.

  12. Test Generation Algorithm for Fault Detection of Analog Circuits Based on Extreme Learning Machine

    PubMed Central

    Zhou, Jingyu; Tian, Shulin; Yang, Chenglin; Ren, Xuelong

    2014-01-01

    This paper proposes a novel test generation algorithm based on extreme learning machine (ELM), and such algorithm is cost-effective and low-risk for analog device under test (DUT). This method uses test patterns derived from the test generation algorithm to stimulate DUT, and then samples output responses of the DUT for fault classification and detection. The novel ELM-based test generation algorithm proposed in this paper contains mainly three aspects of innovation. Firstly, this algorithm saves time efficiently by classifying response space with ELM. Secondly, this algorithm can avoid reduced test precision efficiently in case of reduction of the number of impulse-response samples. Thirdly, a new process of test signal generator and a test structure in test generation algorithm are presented, and both of them are very simple. Finally, the abovementioned improvement and functioning are confirmed in experiments. PMID:25610458

  13. Test generation algorithm for fault detection of analog circuits based on extreme learning machine.

    PubMed

    Zhou, Jingyu; Tian, Shulin; Yang, Chenglin; Ren, Xuelong

    2014-01-01

    This paper proposes a novel test generation algorithm based on extreme learning machine (ELM), and such algorithm is cost-effective and low-risk for analog device under test (DUT). This method uses test patterns derived from the test generation algorithm to stimulate DUT, and then samples output responses of the DUT for fault classification and detection. The novel ELM-based test generation algorithm proposed in this paper contains mainly three aspects of innovation. Firstly, this algorithm saves time efficiently by classifying response space with ELM. Secondly, this algorithm can avoid reduced test precision efficiently in case of reduction of the number of impulse-response samples. Thirdly, a new process of test signal generator and a test structure in test generation algorithm are presented, and both of them are very simple. Finally, the abovementioned improvement and functioning are confirmed in experiments. PMID:25610458

  14. Photoconductive circuit element pulse generator

    DOEpatents

    Rauscher, Christen

    1989-01-01

    A pulse generator for characterizing semiconductor devices at millimeter wavelength frequencies where a photoconductive circuit element (PCE) is biased by a direct current voltage source and produces short electrical pulses when excited into conductance by short laser light pulses. The electrical pulses are electronically conditioned to improve the frequency related amplitude characteristics of the pulses which thereafter propagate along a transmission line to a device under test.

  15. Integrated circuit reliability testing

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G. (Inventor); Sayah, Hoshyar R. (Inventor)

    1990-01-01

    A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.

  16. Integrated circuit reliability testing

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G. (Inventor); Sayah, Hoshyar R. (Inventor)

    1988-01-01

    A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.

  17. Designing Test Chips for Custom Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Griswold, T. W.; Pina, C. A.; Timoc, C. C.

    1985-01-01

    Collection of design and testing procedures partly automates development of built-in test chips for CMOS integrated circuits. Testchip methodology intended especially for users of custom integratedcircuit wafers. Test-Chip Designs and Testing Procedures (including datareduction procedures) generated automatically by computer from programed design and testing rules and from information supplied by user.

  18. Chain Of Test Contacts For Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Lieneweg, Udo

    1989-01-01

    Test structure forms chain of "cross" contacts fabricated together with large-scale integrated circuits. If necessary, number of such chains incorporated at suitable locations in integrated-circuit wafer for determination of fabrication yield of contacts. In new structure, resistances of individual contacts determined: In addition to making it possible to identify local defects, enables generation of statistical distributions of contact resistances for prediction of "parametric" contact yield of fabrication process.

  19. Integrated-Circuit Pseudorandom-Number Generator

    NASA Technical Reports Server (NTRS)

    Steelman, James E.; Beasley, Jeff; Aragon, Michael; Ramirez, Francisco; Summers, Kenneth L.; Knoebel, Arthur

    1992-01-01

    Integrated circuit produces 8-bit pseudorandom numbers from specified probability distribution, at rate of 10 MHz. Use of Boolean logic, circuit implements pseudorandom-number-generating algorithm. Circuit includes eight 12-bit pseudorandom-number generators, outputs are uniformly distributed. 8-bit pseudorandom numbers satisfying specified nonuniform probability distribution are generated by processing uniformly distributed outputs of eight 12-bit pseudorandom-number generators through "pipeline" of D flip-flops, comparators, and memories implementing conditional probabilities on zeros and ones.

  20. Automatic Parametric Testing Of Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Jennings, Glenn A.; Pina, Cesar A.

    1989-01-01

    Computer program for parametric testing saves time and effort in research and development of integrated circuits. Software system automatically assembles various types of test structures and lays them out on silicon chip, generates sequency of test instructions, and interprets test data. Employs self-programming software; needs minimum of human intervention. Adapted to needs of different laboratories and readily accommodates new test structures. Program codes designed to be adaptable to most computers and test equipment now in use. Written in high-level languages to enhance transportability.

  1. Electronic test and calibration circuits, a compilation

    NASA Technical Reports Server (NTRS)

    1972-01-01

    A wide variety of simple test calibration circuits are compiled for the engineer and laboratory technician. The majority of circuits were found inexpensive to assemble. Testing electronic devices and components, instrument and system test, calibration and reference circuits, and simple test procedures are presented.

  2. Submicrosecond Power-Switching Test Circuit

    NASA Technical Reports Server (NTRS)

    Folk, Eric N.

    2006-01-01

    A circuit that changes an electrical load in a switching time shorter than 0.3 microsecond has been devised. This circuit can be used in testing the regulation characteristics of power-supply circuits . especially switching power-converter circuits that are supposed to be able to provide acceptably high degrees of regulation in response to rapid load transients. The combination of this power-switching circuit and a known passive constant load could be an attractive alternative to a typical commercially available load-bank circuit that can be made to operate in nominal constant-voltage, constant-current, and constant-resistance modes. The switching provided by a typical commercial load-bank circuit in the constant-resistance mode is not fast enough for testing of regulation in response to load transients. Moreover, some test engineers do not trust the test results obtained when using commercial load-bank circuits because the dynamic responses of those circuits are, variously, partly unknown and/or excessively complex. In contrast, the combination of this circuit and a passive constant load offers both rapid switching and known (or at least better known) load dynamics. The power-switching circuit (see figure) includes a signal-input section, a wide-hysteresis Schmitt trigger that prevents false triggering in the event of switch-contact bounce, a dual-bipolar-transistor power stage that drives the gate of a metal oxide semiconductor field-effect transistor (MOSFET), and the MOSFET, which is the output device that performs the switching of the load. The MOSFET in the specific version of the circuit shown in the figure is rated to stand off a potential of 100 V in the "off" state and to pass a current of 20 A in the "on" state. The switching time of this circuit (the characteristic time of rise or fall of the potential at the drain of the MOSFET) is .300 ns. The circuit can accept any of three control inputs . which one depending on the test that one seeks to perform: a

  3. Conductive surge testing of circuits and systems

    NASA Technical Reports Server (NTRS)

    Richman, P.

    1980-01-01

    Techniques are given for conductive surge testing of powered electronic equipment. The correct definitions of common and normal mode are presented. Testing requires not only spike-surge generators with a suitable range of open-circuit voltage and short-circuit current waveshapes, but also appropriate means, termed couplers, for connecting test surges to the equipment under test. Key among coupler design considerations is minimization of fail positives resulting from reduction in delivered surge energy due to the coupler. Back-filters and the lines on which they are necessary, are considered as well as ground-fault and ground potential rise. A method for monitoring delivered and resulting surge waves is mentioned.

  4. BLOCKING OSCILLATOR DOUBLE PULSE GENERATOR CIRCUIT

    DOEpatents

    Haase, J.A.

    1961-01-24

    A double-pulse generator, particuiarly a double-pulse generator comprising a blocking oscillator utilizing a feedback circuit to provide means for producing a second pulse within the recovery time of the blocking oscillator, is described. The invention utilized a passive network which permits adjustment of the spacing between the original pulses derived from the blocking oscillator and further utilizes the original pulses to trigger a circuit from which other pulses are initiated. These other pulses are delayed and then applied to the input of the blocking oscillator, with the result that the output from the oscillator circuit contains twice the number of pulses originally initiated by the blocking oscillator itself.

  5. Intersecting Circuits Generate Precisely Patterned Retinal Waves

    PubMed Central

    Akrouh, Alejandro; Kerschensteiner, Daniel

    2013-01-01

    SUMMARY The developing retina generates spontaneous glutamatergic (stage III) waves of activity that sequentially recruit neighboring ganglion cells with opposite light responses (ON and OFF RGCs). This activity pattern is thought to help establish parallel ON and OFF pathways in downstream visual areas. The circuits that produce stage III waves and desynchronize ON and OFF RGC firing remain obscure. Using dual patch clamp recordings, we find that ON and OFF RGCs receive sequential excitatory input from ON and OFF cone bipolar cells (CBCs), respectively. This input sequence is generated by crossover circuits, in which ON CBCs control glutamate release from OFF CBCs via diffusely stratified inhibitory amacrine cells. In addition, neighboring ON CBCs communicate directly and indirectly through lateral glutamatergic transmission and gap junctions, both of which are required for wave initiation and propagation. Thus, intersecting lateral excitatory and vertical inhibitory circuits give rise to precisely patterned stage III retinal waves. PMID:23830830

  6. 30 CFR 56.6407 - Circuit testing.

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Circuit testing. 56.6407 Section 56.6407... Blasting § 56.6407 Circuit testing. A blasting galvanometer or other instrument designed for testing... series or the resistance of multiple balanced series to be connected in parallel prior to...

  7. 30 CFR 56.6407 - Circuit testing.

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... 30 Mineral Resources 1 2013-07-01 2013-07-01 false Circuit testing. 56.6407 Section 56.6407... Blasting § 56.6407 Circuit testing. A blasting galvanometer or other instrument designed for testing... series or the resistance of multiple balanced series to be connected in parallel prior to...

  8. 30 CFR 56.6407 - Circuit testing.

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ... 30 Mineral Resources 1 2011-07-01 2011-07-01 false Circuit testing. 56.6407 Section 56.6407... Blasting § 56.6407 Circuit testing. A blasting galvanometer or other instrument designed for testing... series or the resistance of multiple balanced series to be connected in parallel prior to...

  9. 30 CFR 56.6407 - Circuit testing.

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... 30 Mineral Resources 1 2014-07-01 2014-07-01 false Circuit testing. 56.6407 Section 56.6407... Blasting § 56.6407 Circuit testing. A blasting galvanometer or other instrument designed for testing... series or the resistance of multiple balanced series to be connected in parallel prior to...

  10. A power semiconductor test circuit with reduced power requirements

    NASA Technical Reports Server (NTRS)

    Been, J. F.

    1970-01-01

    Switching circuit utilizing silicon controlled rectifier reduces input power requirements normally associated with testing power semiconductors in an operational type mode. Circuit alleviates problems of inaccessibility, lack of large amounts of power, physical size of power resistors, wiring, and heat generation.

  11. 30 CFR 57.6407 - Circuit testing.

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ... 30 Mineral Resources 1 2011-07-01 2011-07-01 false Circuit testing. 57.6407 Section 57.6407... Blasting-Surface and Underground § 57.6407 Circuit testing. A blasting galvanometer or other instrument... parallel prior to their connection to the blasting line; (3) Continuity of blasting lines prior to...

  12. 30 CFR 57.6407 - Circuit testing.

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... 30 Mineral Resources 1 2013-07-01 2013-07-01 false Circuit testing. 57.6407 Section 57.6407... Blasting-Surface and Underground § 57.6407 Circuit testing. A blasting galvanometer or other instrument... parallel prior to their connection to the blasting line; (3) Continuity of blasting lines prior to...

  13. 30 CFR 57.6407 - Circuit testing.

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Circuit testing. 57.6407 Section 57.6407... Blasting-Surface and Underground § 57.6407 Circuit testing. A blasting galvanometer or other instrument... parallel prior to their connection to the blasting line; (3) Continuity of blasting lines prior to...

  14. 30 CFR 56.6407 - Circuit testing.

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... 30 Mineral Resources 1 2012-07-01 2012-07-01 false Circuit testing. 56.6407 Section 56.6407 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION, DEPARTMENT OF LABOR METAL AND NONMETAL MINE SAFETY AND HEALTH SAFETY AND HEALTH STANDARDS-SURFACE METAL AND NONMETAL MINES Explosives Electric Blasting § 56.6407 Circuit testing. A...

  15. 30 CFR 57.6407 - Circuit testing.

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... 30 Mineral Resources 1 2014-07-01 2014-07-01 false Circuit testing. 57.6407 Section 57.6407... Blasting-Surface and Underground § 57.6407 Circuit testing. A blasting galvanometer or other instrument... parallel prior to their connection to the blasting line; (3) Continuity of blasting lines prior to...

  16. Memristive Sisyphus circuit for clock signal generation.

    PubMed

    Pershin, Yuriy V; Shevchenko, Sergey N; Nori, Franco

    2016-01-01

    Frequency generators are widely used in electronics. Here, we report the design and experimental realization of a memristive frequency generator employing a unique combination of only digital logic gates, a single-supply voltage and a realistic thresholdtype memristive device. In our circuit, the oscillator frequency and duty cycle are defined by the switching characteristics of the memristive device and external resistors. We demonstrate the circuit operation both experimentally, using a memristor emulator, and theoretically, using a model memristive device with threshold. Importantly, nanoscale realizations of memristive devices offer small-size alternatives to conventional quartz-based oscillators. In addition, the suggested approach can be used for mimicking some cyclic (Sisyphus) processes in nature, such as "dripping ants" or drops from leaky faucets. PMID:27199243

  17. Memristive Sisyphus circuit for clock signal generation

    NASA Astrophysics Data System (ADS)

    Pershin, Yuriy V.; Shevchenko, Sergey N.; Nori, Franco

    2016-05-01

    Frequency generators are widely used in electronics. Here, we report the design and experimental realization of a memristive frequency generator employing a unique combination of only digital logic gates, a single-supply voltage and a realistic thresholdtype memristive device. In our circuit, the oscillator frequency and duty cycle are defined by the switching characteristics of the memristive device and external resistors. We demonstrate the circuit operation both experimentally, using a memristor emulator, and theoretically, using a model memristive device with threshold. Importantly, nanoscale realizations of memristive devices offer small-size alternatives to conventional quartz-based oscillators. In addition, the suggested approach can be used for mimicking some cyclic (Sisyphus) processes in nature, such as “dripping ants” or drops from leaky faucets.

  18. Memristive Sisyphus circuit for clock signal generation

    PubMed Central

    Pershin, Yuriy V.; Shevchenko, Sergey N.; Nori, Franco

    2016-01-01

    Frequency generators are widely used in electronics. Here, we report the design and experimental realization of a memristive frequency generator employing a unique combination of only digital logic gates, a single-supply voltage and a realistic thresholdtype memristive device. In our circuit, the oscillator frequency and duty cycle are defined by the switching characteristics of the memristive device and external resistors. We demonstrate the circuit operation both experimentally, using a memristor emulator, and theoretically, using a model memristive device with threshold. Importantly, nanoscale realizations of memristive devices offer small-size alternatives to conventional quartz-based oscillators. In addition, the suggested approach can be used for mimicking some cyclic (Sisyphus) processes in nature, such as “dripping ants” or drops from leaky faucets. PMID:27199243

  19. Periodic binary sequence generators: VLSI circuits considerations

    NASA Technical Reports Server (NTRS)

    Perlman, M.

    1984-01-01

    Feedback shift registers are efficient periodic binary sequence generators. Polynomials of degree r over a Galois field characteristic 2(GF(2)) characterize the behavior of shift registers with linear logic feedback. The algorithmic determination of the trinomial of lowest degree, when it exists, that contains a given irreducible polynomial over GF(2) as a factor is presented. This corresponds to embedding the behavior of an r-stage shift register with linear logic feedback into that of an n-stage shift register with a single two-input modulo 2 summer (i.e., Exclusive-OR gate) in its feedback. This leads to Very Large Scale Integrated (VLSI) circuit architecture of maximal regularity (i.e., identical cells) with intercell communications serialized to a maximal degree.

  20. Lithium Circuit Test Section Design and Fabrication

    NASA Technical Reports Server (NTRS)

    Godfroy, Thomas; Garber, Anne

    2006-01-01

    The Early Flight Fission - Test Facilities (EFF-TF) team has designed and built an actively pumped lithium flow circuit. Modifications were made to a circuit originally designed for NaK to enable the use of lithium that included application specific instrumentation and hardware. Component scale freeze/thaw tests were conducted to both gain experience with handling and behavior of lithium in solid and liquid form and to supply anchor data for a Generalized Fluid System Simulation Program (GFSSP) model that was modified to include the physics for freeze/thaw transitions. Void formation was investigated. The basic circuit components include: reactor segment, lithium to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. This paper will discuss the overall system design and build and the component testing findings.

  1. Lithium Circuit Test Section Design and Fabrication

    NASA Astrophysics Data System (ADS)

    Godfroy, Thomas; Garber, Anne; Martin, James

    2006-01-01

    The Early Flight Fission - Test Facilities (EFF-TF) team has designed and built an actively pumped lithium flow circuit. Modifications were made to a circuit originally designed for NaK to enable the use of lithium that included application specific instrumentation and hardware. Component scale freeze/thaw tests were conducted to both gain experience with handling and behavior of lithium in solid and liquid form and to supply anchor data for a Generalized Fluid System Simulation Program (GFSSP) model that was modified to include the physics for freeze/thaw transitions. Void formation was investigated. The basic circuit components include: reactor segment, lithium to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. This paper discusses the overall system design and build and the component testing findings.

  2. Lithium Circuit Test Section Design and Fabrication

    SciTech Connect

    Godfroy, Thomas; Garber, Anne; Martin, James

    2006-01-20

    The Early Flight Fission -- Test Facilities (EFF-TF) team has designed and built an actively pumped lithium flow circuit. Modifications were made to a circuit originally designed for NaK to enable the use of lithium that included application specific instrumentation and hardware. Component scale freeze/thaw tests were conducted to both gain experience with handling and behavior of lithium in solid and liquid form and to supply anchor data for a Generalized Fluid System Simulation Program (GFSSP) model that was modified to include the physics for freeze/thaw transitions. Void formation was investigated. The basic circuit components include: reactor segment, lithium to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. This paper discusses the overall system design and build and the component testing findings.

  3. Flip-flop resolving time test circuit

    NASA Technical Reports Server (NTRS)

    Rosenberger, F.; Chaney, T. J.

    1982-01-01

    Integrated circuit (IC) flip-flop resolving time parameters are measured by wafer probing, without need of dicing or bonding, throught the incorporation of test structures on an IC together with the flip-flop to be measured. Several delays that are fabricated as part of the test circuit, including a voltage-controlled delay with a resolution of a few picosecs, are calibrated as part of the test procedure by integrating them into, and out of, the delay path of a ring oscillator. Each of the delay values is calculated by subtracting the period of the ring oscillator with the delay omitted from the period with the delay included. The delay measurement technique is sufficiently general for other applications. The technique is illustrated for the case of the flip-flop parameters of a 5-micron feature size NMOS circuit.

  4. Test Structures For Bumpy Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.; Sayah, Hoshyar R.

    1989-01-01

    Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

  5. Automatic generation of signal processing integrated circuits

    SciTech Connect

    Pope, S.P.

    1985-01-01

    A system for the automated design of signal processing integrated circuits is described in this thesis. The system is based on a library of circuit cells, and a software package that can configure the cells into complete integrated circuits. The architecture of the cell library is optimized for low and medium bandwidth digital signal processing applications. Circuits designed with the system use a multiprocessor architecture. Input to the system is a design file written in a specialized programming language. Software emulation from the design file is used to verify performance. A two-pass silicon compiler is used to translate the design file into a mask-level description of an integrated circuit. A major goal of the project is to make the system useable by those with little or no formal training in integrated circuits. A second goal is to reduce the time and cost associated with performing an integrated circuit design, while still producing designs which are reasonably efficient in their use of the technology. Development of the system was guided by basic research on appropriate architectures and circuit constructs for signal processors. As part of this research an integrated circuit was designed which performs speech analysis and synthesis. This vocoder circuit is intended for use in low-bit-rate digital speech transmission systems.

  6. 30 CFR 57.6407 - Circuit testing.

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... 30 Mineral Resources 1 2012-07-01 2012-07-01 false Circuit testing. 57.6407 Section 57.6407 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION, DEPARTMENT OF LABOR METAL AND NONMETAL MINE SAFETY AND HEALTH SAFETY AND HEALTH STANDARDS-UNDERGROUND METAL AND NONMETAL MINES Explosives Electric Blasting-Surface and Underground § 57.6407...

  7. Testing of the anemometer circuit: Data report

    NASA Technical Reports Server (NTRS)

    Moen, Michael J.

    1992-01-01

    The following text discusses results from the electronic step testing and the beginning of velocity step testing in the shock tube. It should be kept in mind that frequency response is always measured as the time from the beginning of the event to the minimum (positive inflection) of the 'bucket' that immediately follows the response. This report is not a complete account of the results from square wave testing. Some data is still in the process of being analyzed and efforts are being made to fit the data to both Freymuth's third order theory and modelled responses from SPICE circuit simulation software.

  8. Integral testing of relays and circuit breakers

    SciTech Connect

    Bandyopadhyay, K.K.

    1993-12-31

    Among all equipment types considered for seismic qualification, relays have been most extensively studied through testing due to a wide variation of their designs and seismic capacities. A temporary electrical discontinuity or ``chatter`` is the common concern for relays. A chatter duration of 2 milliseconds is typically used as an acceptance criterion to determine the seismic capability of a relay. Many electrical devices, on the other hand, receiving input signals from relays can safely tolerate a chatter level much greater than 2 ms. In Phase I of a test program, Brookhaven National Laboratory performed testing of many relay models using the 2-ms chatter criterion. In Phase II of the program, the factors influencing the relay chatter criterion, and impacts of relay chatter on medium and low voltage circuit breakers and lockout relays were investigated. This paper briefly describes the Phase II tests and presents the important observations.

  9. FRONTAL VIEW OF #3 GENERATOR, 6600 VOLT OIL CIRCUIT BREAKER, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    FRONTAL VIEW OF #3 GENERATOR, 6600 VOLT OIL CIRCUIT BREAKER, LOCATED BEHIND SLATE SWITCHBOARD. PHOTO BY JET LOWE, HAER, 1995. - Elwha River Hydroelectric System, Elwha Hydroelectric Dam & Plant, Port Angeles, Clallam County, WA

  10. Entangled Coherent States Generation in two Superconducting LC Circuits

    SciTech Connect

    Chen Meiyu; Zhang Weimin

    2008-11-07

    We proposed a novel pure electronic (solid state) device consisting of two superconducting LC circuits coupled to a superconducting flux qubit. The entangled coherent states of the two LC modes is generated through the measurement of the flux qubit states. The interaction of the flux qubit and two LC circuits is controlled by the external microwave control lines. The geometrical structure of the LC circuits is adjustable and makes a strong coupling between them achievable. This entangled coherent state generator can be realized by using the conventional microelectronic fabrication techniques which increases the feasibility of the experiment.

  11. Synthesizing genetic sequential logic circuit with clock pulse generator

    PubMed Central

    2014-01-01

    Background Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. Results This paper presents a genetic sequential logic circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic counter circuit based on the topology of the digital sequential logic circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic circuits which plays a key role in the sequential logic circuit with specific operational frequency. Conclusions A cascaded genetic logic circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic circuits, genetic sequential logic circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal. PMID:24884665

  12. Creative Test Generators

    ERIC Educational Resources Information Center

    Vickers, F. D.

    1973-01-01

    A brief description of a test generating program which generates questions concerning the Fortran programming language in a random but guided fashion and without resorting to an item bank.'' (Author/AK)

  13. Starter/generator testing

    NASA Astrophysics Data System (ADS)

    Anon

    1994-10-01

    Sundstrand Aerospace and GE Aircraft Engines have studied the switched reluctance machine for use as an integral starter/generator for future aircraft engines. They have conducted an initial, low-power testing of the starter/generator, which is based on power inverters using IGBT-technology semiconductors, to verify its feasibility in the externally mounted version of the integral starter/generator. This preliminary testing of the 250-kW starter/generator reveals favorable results.

  14. Fastrac Gas Generator Testing

    NASA Technical Reports Server (NTRS)

    Nesman, Tomas E.; Dennis, Jay

    2001-01-01

    A rocket engine gas generator component development test was recently conducted at the Marshall Space Flight Center. This gas generator is intended to power a rocket engine turbopump by the combustion of Lox and RP-1. The testing demonstrated design requirements for start sequence, wall compatibility, performance, and stable combustion. During testing the gas generator injector was modified to improve distribution of outer wall coolant and the igniter boss was modified to investigate the use of a pyrotechnic igniter. Expected chamber pressure oscillations at longitudinal acoustic mode were measured for three different chamber lengths tested. High amplitude discrete oscillations resulted in the chamber-alone configurations when chamber acoustic modes coupled with feed-system acoustics modes. For the full gas generator configuration, which included a turbine inlet manifold, high amplitude oscillations occurred only at off-design very low power levels. This testing led to a successful gas generator design for the Fastrac 60,000 lb thrust engine.

  15. Fastrac Gas Generator Testing

    NASA Technical Reports Server (NTRS)

    Nesman, Tomas E.; Dennis, Jay

    1999-01-01

    A rocket engine gas generator component development test was recently conducted at the Marshall Space Flight Center. This gas generator was intended to power a rocket engine turbopump by the combustion of Lox and RP-1. The testing demonstrated design requirements for start sequence, wall compatibility, performance, and stable combustion. During testing the gas generator injector was modified to improve distribution of outer wall coolant and the igniter boss was modified to investigate the use of a pyrotechnic igniter, Expected chamber pressure oscillations at longitudinal acoustic modes were measured for three different chamber lengths tested. High amplitude discrete oscillations occurred in the chamber-alone configurations when chamber acoustic modes coupled with feed-system acoustics modes. For the full gas generator configuration, which included the turbine inlet manifold simulator, high amplitude oscillations occurred only at off-design very low power levels. This testing led to a successful gas generator design for the Fastrac 60,000 lb thrust engine.

  16. Development of a circuit breaker for large generators. Final report

    SciTech Connect

    Garzon, R.D.; Wu, J.L.

    1982-01-01

    This report deals with the evaluation of design concepts for the development of Circuit Breakers for large generators and attempts to define a rating structure for a generator circuit breaker. It includes studies on the influence of the system upon the performance of the circuit breaker. This study covers: The harmonic content in the fault current, the absence of current zeros, the influence of the dynamics of the generator shaft upon the current, and the magnitude and characteristics of the inherent transient recovery voltage produced by the system. Design requirements such as storage volumes, operating pressures and size of nozzle's orifice are identified for SF/sub 6/ synchronous and non synchronous interrupters of the axial flow type. The concept of a current limiting generator circuit breaker is introduced and two variations of a current limiting element are evaluated. One of the concepts uses liquid metal (NaK 78) as the current limiting element, and the other considers the use of a frangible conductor. The preliminary results obtained with an experimental model of a NaK device shows that a magnetic pinching effect reduces the time required for the initiation of the liquid metal vaporization which determines the onset of current limitation and shows that the NaK device appears to offer promise for the development of a current limiting generator breaker.

  17. Reduced circuit implementation of encoder and syndrome generator

    SciTech Connect

    Trager, Barry M; Winograd, Shmuel

    2014-05-27

    An error correction method and system includes an Encoder and Syndrome-generator that operate in parallel to reduce the amount of circuitry used to compute check symbols and syndromes for error correcting codes. The system and method computes the contributions to the syndromes and check symbols 1 bit at a time instead of 1 symbol at a time. As a result, the even syndromes can be computed as powers of the odd syndromes. Further, the system assigns symbol addresses so that there are, for an example GF(2.sup.8) which has 72 symbols, three (3) blocks of addresses which differ by a cube root of unity to allow the data symbols to be combined for reducing size and complexity of odd syndrome circuits. Further, the implementation circuit for generating check symbols is derived from syndrome circuit using the inverse of the part of the syndrome matrix for check locations.

  18. Test results for SEU and SEL immune memory circuits

    NASA Technical Reports Server (NTRS)

    Wiseman, D.; Canaris, J.; Whitaker, S.; Gambles, J.; Arave, K.; Arave, L.

    1993-01-01

    Test results for three SEU logic/circuit hardened CMOS memory circuits verify upset and latch-up immunity for two configurations to be in excess of 120 MeV cm(exp 2)/mg using a commercial, non-radiation hardened CMOS process. Test chips from three separate fabrication runs in two different process were evaluated.

  19. Calorimeter Preamplifier Hybrid Circuit Test Jig

    SciTech Connect

    Abraham, B.M.; /Fermilab

    1999-04-19

    There are two ways in which the testing may be initiated, remotely or locally. If the remote operation is desired, an external TTL level signal must be provided to the test jig with the remotellocal switch on the side of the test jig switched to remote. A logic high will initiate the test. A logic low will terminate the test. In the event that an external signal is connected to the test jig while local operation occurs, the local control takes precedence over remote control. Once a DVT has been locked in the ZIF socket and the DIP switches are selected, the Push-to-Test button may be depressed. Momentarily depressing the button will initiate a test with a minimum 400 ms duration. At the same time a PBCLOCK and PBLATCH pulses will be initiated and the power rails +12V, +8V, and -6V will be ramped to full voltage. The time at which the power rails reach the full voltage is about 13 ms and it is synchronized with bypass capacitors placed on COMP input of U20 and U22 and on the output of U23 voltage regulators. The voltage rails are supplied to a {+-}10% window comparator. A red LED indicates the rail is below or above 10% of the design value. A green LED indicates the rail is within acceptable limits. For DDT with a 5 pF and 10 pF feed back capacitor, the +12V and +8V rails are current-regulated to 19rnA and 22 rnA respectively and the -6V rail is short-circuit protected within the regulator. For DUT with a 22 pF feed back capacitor the current regulation is the same as above except that the +8V rail is current regulated to 43 rnA. The power rails are supplied to the DUT via a 10 {Omega} resistor. The voltage drop across this resistor is sensed by a differential amplifier AD620 and amplified by a gain of 10. An external BNC connection is provided from this point to allow for current measurements by the vendor. The current value for each rail is calculated by measuring the voltage value at this point and divided by (10*10{Omega}). The next stage inverts and amplifies

  20. Electrical short circuit and current overload tests on aircraft wiring

    NASA Technical Reports Server (NTRS)

    Cahill, Patricia

    1995-01-01

    The findings of electrical short circuit and current overload tests performed on commercial aircraft wiring are presented. A series of bench-scale tests were conducted to evaluate circuit breaker response to overcurrent and to determine if the wire showed any visible signs of thermal degradation due to overcurrent. Three types of wire used in commercial aircraft were evaluated: MIL-W-22759/34 (150 C rated), MIL-W-81381/12 (200 C rated), and BMS 1360 (260 C rated). A second series of tests evaluated circuit breaker response to short circuits and ticking faults. These tests were also meant to determine if the three test wires behaved differently under these conditions and if a short circuit or ticking fault could start a fire. It is concluded that circuit breakers provided reliable overcurrent protection. Circuit breakers may not protect wire from ticking faults but can protect wire from direct shorts. These tests indicated that the appearance of a wire subjected to a current that totally degrades the insulation looks identical to a wire subjected to a fire; however the 'fire exposed' conductor was more brittle than the conductor degraded by overcurrent. Preliminary testing indicates that direct short circuits are not likely to start a fire. Preliminary testing indicated that direct short circuits do not erode insulation and conductor to the extent that ticking faults did. Circuit breakers may not safeguard against the ignition of flammable materials by ticking faults. The flammability of materials near ticking faults is far more important than the rating of the wire insulation material.

  1. Short Circuit Current Contribution for Different Wind Turbine Generator Types

    SciTech Connect

    Muljadi, E.; Samaan, Nader A.; Gevorgian, Vahan; Li, Jun; Pasupulati, Subbaiah

    2010-09-28

    An important aspect of wind power plant (WPP) impact studies is to evaluate the short circuit (SC) current contribution of the plant into the transmission network under different fault conditions. This task can be challenging to protection engineers due to the topology differences between different types of wind turbine generators (WTGs) and the conventional generating units. This paper represents simulation results for short circuit current contribution for different types of WTGs obtained through transient analysis using generic WTG models. The obtained waveforms are analyzed to explain the behavior, such as peak values and rate of decay, of the WTG. The effect of fault types and location, and the effect of the control algorithms of power converters on SC current contribution are investigated. It is shown that the response of the WPP to faults will vary based on the type of the installed WTGs. While in Type 1 and Type 2 WTGs, short circuit current will be determined by the physical characteristics of the induction generator, the contribu-tion of Type 3 and Type 4 WTG will be mostly characterized by the power converters control algorithms which are usually considered proprietary information by the wind turbine manufacturers.

  2. Test and inspection for process control of monolithic circuits

    NASA Technical Reports Server (NTRS)

    Spangenberg, E.

    1967-01-01

    Report details the test and inspection procedures for the mass production of high reliability integrated circuits. It covers configuration control, basic fundamentals of quality control, control charts, wafer process evaluation, general process evaluation, evaluation score system, and diffusion evaluation.

  3. Addressable-Matrix Integrated-Circuit Test Structure

    NASA Technical Reports Server (NTRS)

    Sayah, Hoshyar R.; Buehler, Martin G.

    1991-01-01

    Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.

  4. Documentation of Stainless Steel Lithium Circuit Test Section Design

    NASA Technical Reports Server (NTRS)

    Godfroy, T. J.; Martin, J. J.; Stewart, E. T.; Rhys, N. O.

    2010-01-01

    The Early Flight Fission-Test Facilities (EFF-TF) team was tasked by Naval Reactors Prime Contract Team (NRPCT) to design, fabricate, and test an actively pumped lithium (Li) flow circuit. This Li circuit takes advantage of work in progress at the EFF TF on a stainless steel sodium/potassium (NaK) circuit. The effort involved modifying the original stainless steel NaK circuit such that it could be operated with Li in place of NaK. This new design considered freeze/thaw issues and required the addition of an expansion tank and expansion/extrusion volumes in the circuit plumbing. Instrumentation has been specified for Li and circuit heaters have been placed throughout the design to ensure adequate operational temperatures and no uncontrolled freezing of the Li. All major components have been designed and fabricated prior to circuit redesign for Li and were not modified. Basic circuit components include: reactor segment, Li to gas heat exchanger, electromagnetic liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. The reactor segment, based on a Los Alamos National Laboratory 100-kW design study with 120 fuel pins, is the only prototypic component in the circuit. However, due to earlier funding constraints, a 37-pin partial-array of the core, including the central three rings of fuel pins (pin and flow path dimensions are the same as those in the full design), was selected for fabrication and test. This Technical Publication summarizes the design and integration of the pumped liquid metal Li flow circuit as of May 1, 2005.

  5. Documentation of Stainless Steel Lithium Circuit Test Section Design. Suppl

    NASA Technical Reports Server (NTRS)

    Godfroy, Thomas J. (Compiler); Martin, James J.

    2010-01-01

    The Early Flight Fission-Test Facilities (EFF-TF) team was tasked by Naval Reactors Prime Contract Team (NRPCT) to design, fabricate, and test an actively pumped lithium (Li) flow circuit. This Li circuit takes advantage of work in progress at the EFF TF on a stainless steel sodium/potassium (NaK) circuit. The effort involved modifying the original stainless steel NaK circuit such that it could be operated with Li in place of NaK. This new design considered freeze/thaw issues and required the addition of an expansion tank and expansion/extrusion volumes in the circuit plumbing. Instrumentation has been specified for Li and circuit heaters have been placed throughout the design to ensure adequate operational temperatures and no uncontrolled freezing of the Li. All major components have been designed and fabricated prior to circuit redesign for Li and were not modified. Basic circuit components include: reactor segment, Li to gas heat exchanger, electromagnetic liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. The reactor segment, based on a Los Alamos National Laboratory 100-kW design study with 120 fuel pins, is the only prototypic component in the circuit. However, due to earlier funding constraints, a 37-pin partial-array of the core, including the central three rings of fuel pins (pin and flow path dimensions are the same as those in the full design), was selected for fabrication and test. This Technical Publication summarizes the design and integration of the pumped liquid metal Li flow circuit as of May 1, 2005. This supplement contains drawings, analysis, and calculations

  6. Fiber-optic testing system having a detection circuit

    NASA Astrophysics Data System (ADS)

    Needham, Francis L.

    1992-05-01

    A system for testing a fiber-optic component with infrared radiation is provided. The testing system has a source of infrared radiation, an optic coupler, a detecting circuit, and an analog tape recorder. The optic coupler directs the infrared radiation onto the fiber-optic component. The detection circuit is electrically connected to the tape recorder. The detection circuit has an amplifier, a potentiometer connected in parallel to the amplifier, and a photoelectric transducer connected in series to the amplifier. These components are mounted on a non-conductive board. A power source supplies voltage and is connected to the amplifier. The circuit operates by having the photoelectric transducer sense the infrared radiation emitted from the tested fiber-optic component and convert the radiation into an electrical signal. The amplifier then amplifies the electrical signal to the voltage necessary for driving the tape recorder.

  7. Fiber-optical testing system having a detection circuit

    NASA Astrophysics Data System (ADS)

    Needham, Francis L.

    1994-01-01

    A system for testing a fiber-optic component with infrared radiation is provided. The testing system has a source of infrared radiation, an optic coupler, a detecting circuit, and an analog tape recorder. The optic coupler directs the infrared radiation onto the fiber-optic component. The detection circuit is electrically connected to the tape recorder. The detection circuit has an amplifier, a potentiometer connected in parallel to the amplifier, and a photoelectric transducer connected in series to the amplifier. These components are mounted on a non-conductive board. A power source supplies voltage and is connected to the amplifier. The circuit operates by having the photoelectric transducer sense the infrared radiation emitted from the tested fiber-optic component and convert the radiation into an electrical signal. The amplifier then amplifies the electrical signal to the voltage necessary for driving the tape recorder.

  8. Elements configuration of the open lead test circuit

    NASA Astrophysics Data System (ADS)

    Fukuzaki, Yumi; Ono, Akira

    2016-07-01

    In the field of electronics, small electronic devices are widely utilized because they are easy to carry. The devices have various functions by user's request. Therefore, the lead's pitch or the ball's pitch have been narrowed and high-density printed circuit board has been used in the devices. Use of the ICs which have narrow lead pitch makes normal connection difficult. When logic circuits in the devices are fabricated with the state-of-the-art technology, some faults have occurred more frequently. It can be divided into types of open faults and short faults. We have proposed a new test method using a test circuit in the past. This paper propose elements configuration of the test circuit.

  9. Research on reliability test circuit of pneumatic pressure regulator

    NASA Astrophysics Data System (ADS)

    Ma, Jungong; Wang, Haitao; Oneyama, Naotake; Senoo, Mitsuru; Zhang, Huping

    2006-11-01

    In order to evaluate ISO/CD19973-4, some items had been tested, such as step response, valve opening, feasible opening frequency, air consumption, piping influence, cycle response and so on. The results show that Valve opening varies sensitively to the size of piping, solenoid valve and test chamber. The valve of regulator opens to some extent, closes immediately, and never reaches the full opening. If these circuit specifications are defined concretely and observed strictly, it is not impossible to obtain a certain required opening ratio and air consumption is very large. On the side, the compared tests based on the Japanese JIS test circuit having been carried out, the results show that, regardless of test circuit specifications, the valve of regulator always repeats full closing and full opening. The relief valve of the regulator operates too. At the same operating frequency, air consumption is one digit less than the one in ISO/CD 19973-4 circuit. In the end, improved JIS circuit was put forward as a reliability circuit of pneumatic pressure regulator.

  10. Generating Effective Models and Parameters for RNA Genetic Circuits.

    PubMed

    Hu, Chelsea Y; Varner, Jeffrey D; Lucks, Julius B

    2015-08-21

    RNA genetic circuitry is emerging as a powerful tool to control gene expression. However, little work has been done to create a theoretical foundation for RNA circuit design. A prerequisite to this is a quantitative modeling framework that accurately describes the dynamics of RNA circuits. In this work, we develop an ordinary differential equation model of transcriptional RNA genetic circuitry, using an RNA cascade as a test case. We show that parameter sensitivity analysis can be used to design a set of four simple experiments that can be performed in parallel using rapid cell-free transcription-translation (TX-TL) reactions to determine the 13 parameters of the model. The resulting model accurately recapitulates the dynamic behavior of the cascade, and can be easily extended to predict the function of new cascade variants that utilize new elements with limited additional characterization experiments. Interestingly, we show that inconsistencies between model predictions and experiments led to the model-guided discovery of a previously unknown maturation step required for RNA regulator function. We also determine circuit parameters in two different batches of TX-TL, and show that batch-to-batch variation can be attributed to differences in parameters that are directly related to the concentrations of core gene expression machinery. We anticipate the RNA circuit models developed here will inform the creation of computer aided genetic circuit design tools that can incorporate the growing number of RNA regulators, and that the parametrization method will find use in determining functional parameters of a broad array of natural and synthetic regulatory systems. PMID:26046393

  11. Circuit design considerations for regulating energy generated by dielectric elastomer generators

    NASA Astrophysics Data System (ADS)

    Lo, Ho Cheong; Mckay, Thomas; O'Brien, Benjamin M.; Calius, Emilio; Anderson, Iain

    2011-04-01

    Dielectric Elastomer Generator(s) (DEG) have many unique properties that give them advantages over conventional electromagnetic generators. These include the ability to effectively generate power from slow and irregular motions, low cost, relatively large energy density, and a soft and flexible nature. For DEG to generate usable electrical energy circuits for charging (or priming) the stretched DEG and regulating the generated energy when relaxed are required. Most prior art has focused on the priming challenge, and there is currently very little work into developing circuits that address design issues for extracting the electrical energy and converting it into a usable form such as low DC voltages (~10 V) for small batteries or AC mains voltage (~100 V). This paper provides a brief introduction to the problems of regulating the energy generated by DEG. A buck converter and a charge pump are common DC-DC step-down circuits and are used as case studies to explore the design issues inherent in converting the high voltage energy into a form suitable for charging a battery. Buck converters are efficient and reliable but also heavy and bulky, making them suitable for large scale power generation. The smaller and simpler charge pump, though a less effective energy harvester, is better for small and discrete power generation. Future development in miniature DE fabrication is expected to reduce the high operational voltages, simplifying the design of these circuits.

  12. RF Testing Of Microwave Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Romanofsky, R. R.; Ponchak, G. E.; Shalkhauser, K. A.; Bhasin, K. B.

    1988-01-01

    Fixtures and techniques are undergoing development. Four test fixtures and two advanced techniques developed in continuing efforts to improve RF characterization of MMIC's. Finline/waveguide test fixture developed to test submodules of 30-GHz monolithic receiver. Universal commercially-manufactured coaxial test fixture modified to enable characterization of various microwave solid-state devices in frequency range of 26.5 to 40 GHz. Probe/waveguide fixture is compact, simple, and designed for non destructive testing of large number of MMIC's. Nondestructive-testing fixture includes cosine-tapered ridge, to match impedance wavequide to microstrip. Advanced technique is microwave-wafer probing. Second advanced technique is electro-optical sampling.

  13. Extended life testing evaluation of complementary MOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Brosnan, T. E.

    1972-01-01

    The purpose of the extended life testing evaluation of complementary MOS integrated circuits was twofold: (1) To ascertain the long life capability of complementary MOS devices. (2) To assess the objectivity and reliability of various accelerated life test methods as an indication or prediction tool. In addition, the determination of a suitable life test sequence for these devices was of importance. Conclusions reached based on the parts tested and the test results obtained was that the devices were not acceptable.

  14. A circuit model for the explosive-driven plate generator

    NASA Astrophysics Data System (ADS)

    Caird, R. S.; Erickson, D. J.; Fowler, C. M.; Freeman, B. L.; Goforth, J. H.

    Explosive-driven generators are modelled as lumped parameter circuit elements in order to estimate performance in applications and to optimize the design of experiments. The plate generator is essentially a parallel or tilted plate transmission line in which the current-carrying flat plate conductors are driven by plane wave explosive systems. A simple model for the time-varying inductance of this system was developed. First, an analytic expression is used to predict the plate motion. Then, the inductance is expressed as a function of plate separation to give the computational model. Time-dependent flux losses are accounted for by an increasing waste inductance. Model predictions are compared with the available shot data.

  15. Representation of Type 4 wind turbine generator for steady state short-circuit calculations

    NASA Astrophysics Data System (ADS)

    Kamara, Wouleye

    commercial distribution system analysis program, to perform short-circuit calculations in multiphase complex unbalanced systems. Detailed study of the behavior of Type 4 wind turbine generator using electromagnetic type programs like EMTP-RV has assessed that the proposed model closely reproduces the real behavior of the wind turbine generator under steady-state fault conditions. The proposed model is then implemented in CYME 7.0 and validated for different fault scenarios using the Fortis Alberta 25 kV distribution system as benchmark. The fault contribution obtained from the proposed model is compared against the one obtained from the previous model implemented in CYME 7.0. The validation test cases show that the proposed model estimates the fault contribution of the wind turbine generator with better precision than the former models. Besides, the performance and robustness of the short-circuit algorithm developed allow handling unbalanced networks with inverter interfaced wind turbine generators as it is based on the MANA formulation.

  16. Equivalent diagram of a solar cell, based on short-circuit and open-circuit tests

    NASA Astrophysics Data System (ADS)

    Slonim, Michael A.; Tslaf, Avraam L.

    1987-12-01

    A novel equivalent diagram of a solar cell is developed. A solar cell array is represented by a voltage source E and two internal resistances r(sc) and r(oc) which are determined from short-cirucit and open-circuit tests. E is constant and does not depend on irradiation; r(sc) is constant for given irradiation; r(oc) is constant for given irradiation under the open-circuit condition but changes its value with varying load. An example is presented for calculation of the parameters in the equivalent diagram using the experimental output characteristic of a cell. An analysis is made of the trend in parameters of modern solar cells for the developed diagram. The diagram allows the use of ordinary calculation and design techniques for the analysis of circuits with solar cells.

  17. MIRAGE read-in integrated circuit testing results

    NASA Astrophysics Data System (ADS)

    Hoelter, Theodore R.; Henry, Blake A.; Graff, John H.; Aziz, Naseem Y.

    1999-07-01

    This paper describes the test results for the MIRAGE read- in-integrated-circuit (RIIC) designed by Indigo Systems Corporation. This RIIC, when mated with suspended membrane, micro-machined resistive elements, forms a highly advanced emitter array. This emitter array is used by Indigo and Santa Barbara Infrared Incorporated in a jointly developed product for infrared scene generation, called MIRAGE. The MIRAGE RIIC is a 512 X 512 pixel design which incorporates a number of features that extend the state of the art for emitter array RIIC devices. These innovations include an all-digital interface for scene data, snapshot image updates (all pixels show the new frame simultaneously), frame rates up to 200 Hz, operating modes that control the device output, power consumption, and diagnostic configuration. Tests measuring operating speed, RIIC functionality and D/A converter performance were completed. At 2.1 X 2.3 cm, this die is also the largest nonstitched device ever made by Indigo's foundry, American Microsystems Incorporated. As with any IC design, die yield is a critical factor that typically scales with the size and complexity. Die yield, and a statistical breakdown of the failures observed will be discussed.

  18. Ring Counter Based ATPG for Low Transition Test Pattern Generation

    PubMed Central

    Begam, V. M. Thoulath; Baulkani, S.

    2015-01-01

    In test mode test patterns are applied in random fashion to the circuit under circuit. This increases switching transition between the consecutive test patterns and thereby increases dynamic power dissipation. The proposed ring counter based ATPG reduces vertical switching transitions by inserting test vectors only between the less correlative test patterns. This paper presents the RC-ATPG with an external circuit. The external circuit consists of XOR gates, full adders, and multiplexers. First the total number of transitions between the consecutive test patterns is determined. If it is more, then the external circuit generates and inserts test vectors in between the two test patterns. Test vector insertion increases the correlation between the test patterns and reduces dynamic power dissipation. The results prove that the test patterns generated by the proposed ATPG have fewer transitions than the conventional ATPG. Experimental results based on ISCAS'85 and ISCAS'89 benchmark circuits show 38.5% reduction in the average power and 50% reduction in the peak power attained during testing with a small size decoding logic. PMID:26075295

  19. A Testing System for Diagnosing Misconceptions in DC Electric Circuits.

    ERIC Educational Resources Information Center

    Chang, Kuo-En; Liu, Sei-Hua; Chen, Sei-Wang

    1998-01-01

    Outlines a test-based diagnosis system for misconceptions in DC electric circuits and its three parts: problem library, problem selector and diagnoser. Discusses misconception discrimination and diagnosis theories, and reports the system supports satisfactory diagnosis. Includes an analysis of nine student misconceptions about electrical circuits…

  20. Combined Self-Test of Analog Portion and ADCs in Integrated Mixed-Signal Circuits

    NASA Astrophysics Data System (ADS)

    Hu, Geng; Wang, Hong; Yang, Shiyuan

    Testing is a critical stage in integrated circuits production in order to guarantee reliability. The complexity and high integration level of mixed-signal ICs has put forward new challenges to circuit testing. This paper describes an oscillation-based combined self-test strategy for the analog portion and analog-to-digital converters (ADCs) in integrated mixed-signal circuits. In test mode, the analog portion under test is reconfigured into an oscillator, generating periodic signals as the test stimulus of ADC. By analyzing the A/D conversion results, a histogram test of ADC can be performed, and the oscillation frequency as well as amplitude can be checked, and in this way the oscillation test of the analog portion is realized simultaneously. For an analog benchmark circuit combined with an ADC, triangle oscillation and sinusoid oscillation schemes are both given to test their faults. Experimental results show that fault coverage of the analog portion is 92.2% and 94.3% in the two schemes respectively, and faults in the ADC can also be tested.

  1. Radiation Testing and Evaluation Issues for Modern Integrated Circuits

    NASA Technical Reports Server (NTRS)

    LaBel, Kenneth A.; Cohn, Lew M.

    2005-01-01

    Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

  2. Laser system for testing radiation imaging detector circuits

    NASA Astrophysics Data System (ADS)

    Zubrzycka, Weronika; Kasinski, Krzysztof

    2015-09-01

    Performance and functionality of radiation imaging detector circuits in charge and position measurement systems need to meet tight requirements. It is therefore necessary to thoroughly test sensors as well as read-out electronics. The major disadvantages of using radioactive sources or particle beams for testing are high financial expenses and limited accessibility. As an alternative short pulses of well-focused laser beam are often used for preliminary tests. There are number of laser-based devices available on the market, but very often their applicability in this field is limited. This paper describes concept, design and validation of laser system for testing silicon sensor based radiation imaging detector circuits. The emphasis is put on keeping overall costs low while achieving all required goals: mobility, flexible parameters, remote control and possibility of carrying out automated tests. The main part of the developed device is an optical pick-up unit (OPU) used in optical disc drives. The hardware includes FPGA-controlled circuits for laser positioning in 2 dimensions (horizontal and vertical), precision timing (frequency and number) and amplitude (diode current) of short ns-scale (3.2 ns) light pulses. The system is controlled via USB interface by a dedicated LabVIEW-based application enabling full manual or semi-automated test procedures.

  3. Experiences in the use of evolutionary techniques for testing digital circuits

    NASA Astrophysics Data System (ADS)

    Corno, Fulvio; Rebaudengo, Maurizio; Sonza Reorda, Matteo

    1998-10-01

    The generation of test patterns for sequential circuits is one of the most challenging problems arising in the field of Computer-Aided Design for VLSI circuits. In the past decade, Genetic Algorithms have been deeply investigated as a possible approach: several algorithms have been described, and significant improvements have been proposed with respect to their original versions. As a result, GA-based test pattern generators can now effectively compete with other methods, such as topological or symbolic ones. This paper discusses the advantages and disadvantages of GA-based approaches and describes GATTO, a state-of-the-art GA-based test pattern generator. Other algorithms belonging to the same category are outlined as well. The paper puts GATTO and other GA-based tools in perspective, and shows that Evolutionary computation techniques can successfully compete with more traditional approaches, or be integrated with them.

  4. Providing Reliability of Physical Systems: Fully Delay Testable Logical Circuit Design with Compact Representation of all PDF Test Pairs

    NASA Astrophysics Data System (ADS)

    Matrosova, A. Yu.; Mitrofanov, E. V.; Akhynova, D. I.

    2016-01-01

    Functional reliability is one of the important properties of physical systems provided by reliability of system components, in particular, control logical components. The new approach to fully delay testable circuit design oriented to cut overheads and lengths of circuit paths has been developed. Compact representation of all PDF test pairs is reduced to keeping the corresponding generative vector pairs. The number of generative vector pairs does not exceed the doubled number of internal ROBDD nodes originating from the circuit, while the number of the circuit paths can exponentially depend on the number of these internal nodes. The algorithm of involving the PDF test pair from the proper generative vector pair is suggested. This procedure does not require essential calculations. The algorithm of deriving the generative vector pair has a polynomial complexity.

  5. Relay test program. Series 2 tests: Integral testing of relays and circuit breakers

    SciTech Connect

    Bandyopadhyay, K.K.; Kunkel, C.; Shteyngart, S.

    1994-02-01

    This report presents the results of a relay test program conducted by Brookhaven National Laboratory (BNL) under the sponsorship of the US Nuclear Regulatory Commission (NRC). The program is a continuation of an earlier test program the results of which were published in NUREG/CR-4867. The current program was carried out in two phases: electrical testing and vibration testing. The objective was primarily to focus on the electrical discontinuity or continuity of relays and circuit breaker tripping mechanisms subjected to electrical pulses and vibration loads. The electrical testing was conducted by KEMA-Powertest Company and the vibration testing was performed at Wyle Laboratories, Huntsville, Alabama. This report discusses the test procedures, presents the test data, includes an analysis of the data and provides recommendations regarding reliable relay testing.

  6. Function electrical stimulation signals generator circuits for the central nerve and the sciatic nerve.

    PubMed

    Wenyuan, Li; Zhenyu, Zhang; Zhi-Gong, Wang

    2005-01-01

    Circuits for the signal generation of the FES (functional electrical stimulation) of the central nerve and the sciatic nerve have been designed. The circuits were implemented by using discrete devices. The FES circuits consist of two or three operational amplifiers. The bandwidths of the circuits are more than 10 kHz and their gains are variable from 20 dB to 60 dB. To a load of several kilo-ohms, according to the microelectrode with the nerve, the circuit for stimulating central nerve can provide a current signal, and the signal value is more than 1mA. The circuit for stimulating sciatic nerve can provide a stimulating voltage signal of more than 10 Vs. The loads of the circuits are microelectrodes contacted with nerves. The circuits can be used with two kinds of microelectrodes: cuff microelectrodes which for stimulating sciatic nerve and shaft microelectrodes which for stimulating central nerve. PMID:17281443

  7. Circuit design for nuclear radiation test of CMOS multiplier chips

    SciTech Connect

    Lim, T.S.; Martin, R.L.; Hughes, H.L.

    1986-09-01

    This paper describes the design of a microprocessor-based electronic circuit to be used in testing the effects of nuclear radiation on a CMOS 8 x 8 multiplier chip. Knowledge of such effects is important for military and space applications of integrated circuits. The multiplier chip undergoing testing is attached to a DUT (device under test) board which is enclosed in a metal container. The container is then lowered to the cobalt 60 radiation source located at the bottom of a 15-ft-deep pool. The gamma-ray radiation test setup is schematically shown. The in-source test board containing the multiplier chip is attached to an 8085-based, single-board microcomputer (SDK-85) by a 30-ft multiconductor cable. Doses of gamma-ray radiation from cobalt 60 are applied in steps at increasing quantities until the multiplier chip, which is tested between doses, begins to malfunction. An 8085 assembly language program is used for functional test of the multiplier. The leakage current and the propagation delay time are also measured between doses.

  8. Combinatorial Generation of Test Suites

    NASA Technical Reports Server (NTRS)

    Dvorak, Daniel L.; Barrett, Anthony C.

    2009-01-01

    Testgen is a computer program that generates suites of input and configuration vectors for testing other software or software/hardware systems. As systems become ever more complex, often, there is not enough time to test systems against all possible combinations of inputs and configurations, so test engineers need to be selective in formulating test plans. Testgen helps to satisfy this need: In response to a test-suite-requirement-specification model, it generates a minimal set of test vectors that satisfies all the requirements.

  9. Universal nondestructive mm-wave integrated circuit test fixture

    NASA Technical Reports Server (NTRS)

    Romanofsky, Robert R. (Inventor); Shalkhauser, Kurt A. (Inventor)

    1990-01-01

    Monolithic microwave integrated circuit (MMIC) test includes a bias module having spring-loaded contacts which electrically engage pads on a chip carrier disposed in a recess of a base member. RF energy is applied to and passed from the chip carrier by chamfered edges of ridges in the waveguide passages of housings which are removably attached to the base member. Thru, Delay, and Short calibration standards having dimensions identical to those of the chip carrier assure accuracy and reliability of the test. The MMIC chip fits in an opening in the chip carrier with the boundaries of the MMIC lying on movable reference planes thereby establishing accuracy and flexibility.

  10. Capabilities and Testing of the Fission Surface Power Primary Test Circuit (FSP-PTC)

    NASA Technical Reports Server (NTRS)

    Garber, Anne E.

    2007-01-01

    An actively pumped alkali metal flow circuit, designed and fabricated at the NASA Marshall Space Flight Center, is currently undergoing testing in the Early Flight Fission Test Facility (EFF-TF). Sodium potassium (NaK), which was used in the SNAP-10A fission reactor, was selected as the primary coolant. Basic circuit components include: simulated reactor core, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, liquid metal flowmeter, load/drain reservoir, expansion reservoir, test section, and instrumentation. Operation of the circuit is based around a 37-pin partial-array core (pin and flow path dimensions are the same as those in a full core), designed to operate at 33 kWt. NaK flow rates of greater than 1 kg/sec may be achieved, depending upon the power applied to the EM pump. The heat exchanger provides for the removal of thermal energy from the circuit, simulating the presence of an energy conversion system. The presence of the test section increases the versatility of the circuit. A second liquid metal pump, an energy conversion system, and highly instrumented thermal simulators are all being considered for inclusion within the test section. This paper summarizes the capabilities and ongoing testing of the Fission Surface Power Primary Test Circuit (FSP-PTC).

  11. Apparatus and method for defect testing of integrated circuits

    DOEpatents

    Cole, Jr., Edward I.; Soden, Jerry M.

    2000-01-01

    An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

  12. Apparatus and method for defect testing of integrated circuits

    SciTech Connect

    Cole, E.I. Jr.; Soden, J.M.

    2000-02-29

    An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V(DD), to an IC under test and measures a transient voltage component, V(DDT), signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V(DDT) signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V(DDT) signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

  13. Series and parallel arc-fault circuit interrupter tests.

    SciTech Connect

    Johnson, Jay; Fresquez, Armando J.; Gudgel, Bob; Meares, Andrew

    2013-07-01

    While the 2011 National Electrical Code%C2%AE (NEC) only requires series arc-fault protection, some arc-fault circuit interrupter (AFCI) manufacturers are designing products to detect and mitigate both series and parallel arc-faults. Sandia National Laboratories (SNL) has extensively investigated the electrical differences of series and parallel arc-faults and has offered possible classification and mitigation solutions. As part of this effort, Sandia National Laboratories has collaborated with MidNite Solar to create and test a 24-string combiner box with an AFCI which detects, differentiates, and de-energizes series and parallel arc-faults. In the case of the MidNite AFCI prototype, series arc-faults are mitigated by opening the PV strings, whereas parallel arc-faults are mitigated by shorting the array. A range of different experimental series and parallel arc-fault tests with the MidNite combiner box were performed at the Distributed Energy Technologies Laboratory (DETL) at SNL in Albuquerque, NM. In all the tests, the prototype de-energized the arc-faults in the time period required by the arc-fault circuit interrupt testing standard, UL 1699B. The experimental tests confirm series and parallel arc-faults can be successfully mitigated with a combiner box-integrated solution.

  14. A Digital Coreless Maximum Power Point Tracking Circuit for Thermoelectric Generators

    NASA Astrophysics Data System (ADS)

    Kim, Shiho; Cho, Sungkyu; Kim, Namjae; Baatar, Nyambayar; Kwon, Jangwoo

    2011-05-01

    This paper describes a maximum power point tracking (MPPT) circuit for thermoelectric generators (TEG) without a digital controller unit. The proposed method uses an analog tracking circuit that samples the half point of the open-circuit voltage without a digital signal processor (DSP) or microcontroller unit for calculating the peak power point using iterative methods. The simulation results revealed that the MPPT circuit, which employs a boost-cascaded-with-buck converter, handled rapid variation of temperature and abrupt changes of load current; this method enables stable operation with high power transfer efficiency. The proposed MPPT technique is a useful analog MPPT solution for thermoelectric generators.

  15. 49 CFR 236.577 - Test, acknowledgement, and cut-in circuits.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Test, acknowledgement, and cut-in circuits. 236.577 Section 236.577 Transportation Other Regulations Relating to Transportation (Continued) FEDERAL..., acknowledgement, and cut-in circuits. Test, acknowledgement, and cut-in circuits shall be tested at least...

  16. 49 CFR 236.577 - Test, acknowledgement, and cut-in circuits.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 49 Transportation 4 2011-10-01 2011-10-01 false Test, acknowledgement, and cut-in circuits. 236.577 Section 236.577 Transportation Other Regulations Relating to Transportation (Continued) FEDERAL..., acknowledgement, and cut-in circuits. Test, acknowledgement, and cut-in circuits shall be tested at least...

  17. 42 CFR 84.93 - Gas flow test; open-circuit apparatus.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 42 Public Health 1 2010-10-01 2010-10-01 false Gas flow test; open-circuit apparatus. 84.93...-Contained Breathing Apparatus § 84.93 Gas flow test; open-circuit apparatus. (a) A static-flow test will be performed on all open-circuit apparatus. (b) The flow from the apparatus shall be greater than 200...

  18. 42 CFR 84.93 - Gas flow test; open-circuit apparatus.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 42 Public Health 1 2011-10-01 2011-10-01 false Gas flow test; open-circuit apparatus. 84.93...-Contained Breathing Apparatus § 84.93 Gas flow test; open-circuit apparatus. (a) A static-flow test will be performed on all open-circuit apparatus. (b) The flow from the apparatus shall be greater than 200...

  19. Microwave generators simplify swept tests

    NASA Astrophysics Data System (ADS)

    Foster, C. E.; Hagins, M. R.

    1986-01-01

    The utilization of the swept-frequency capability makes it possible to conduct any number of microwave tests. It is pointed out that today's microwave sweepers make such tests simple and straightforward. A filter test involving a high-pass filter with a cutoff frequency of 14.0 GHz is discussed, taking into account the use of a microwave sweeper operating in the range from 12 to 18 GHz. Attention is also given to swept-frequency amplifier testing, antenna swept-gain testing, and microwave antenna testing. With a sweep generator, it is simple to assemble a setup for testing amplifier small-signal gain, flatness, and rolloff.

  20. Analysis of Non-Standard Lightning Impulse Voltage for Actual Substation and Generation Circuit

    NASA Astrophysics Data System (ADS)

    Okabe, Shigemitsu; Koutou, Masanori; Yuasa, Sadayuki; Suzuki, Toshiyuki; Rokunohe, Toshiaki; Yamagiwa, Tokio

    Evaluation of lightning surge waveforms that actually enter into substations is important when investigating the test voltage of electric power equipment. The standard lightning impulse waveform (1.2/50μs) is used for factory tests. However, the actual lightning surge waveforms in actual substations are complex waveforms in which various different oscillations are superimposed. Investigation of insulation characteristics of equipment against the complex waveforms and the standard one has significant importance. We analyzed these waveforms entering actual substations with respect to the insulation characteristics of gas insulated switchigear (GIS). From the results, we defined four types of non-standard lightning impulse waveforms. Then non-standard lightning impulse voltage is generated by an equipment circuit which is consisted of an impulse generator (IG), R, L and C is analyzed with EMTP. Voltage time characteristics were evaluated from the obtained impulse voltages.

  1. Generation of nearly hemispherical and high gain azimuthally symmetric patterns with printed circuit antennas

    NASA Astrophysics Data System (ADS)

    Yang, Hung Yu; Alexopoulos, Nicolaos G.

    1987-08-01

    Patttern shaping techniques are discussed for printed circuit antennas such as microstrip dipoles and slot elements. Crossed printed circuit dipoles or a combination of a printed circuit dipole and a slot are employed. It is demonstrated that with the proper choice of substrate or substrate-superstrate parameters it is possible to generate: (1) nearly hemispherical patterns, (2) high-gain azimuthally symmetric patterns, and (3) nearly sec theta patterns.

  2. Testing interconnected VLSI circuits in the Big Viterbi Decoder

    NASA Technical Reports Server (NTRS)

    Onyszchuk, I. M.

    1991-01-01

    The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

  3. 42 CFR 84.96 - Service time test; closed-circuit apparatus.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 42 Public Health 1 2011-10-01 2011-10-01 false Service time test; closed-circuit apparatus. 84.96...-Contained Breathing Apparatus § 84.96 Service time test; closed-circuit apparatus. (a) The closed-circuit apparatus will be classified according to the length of time it supplies adequate breathing gas to...

  4. 42 CFR 84.95 - Service time test; open-circuit apparatus.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 42 Public Health 1 2011-10-01 2011-10-01 false Service time test; open-circuit apparatus. 84.95...-Contained Breathing Apparatus § 84.95 Service time test; open-circuit apparatus. (a) Service time will be measured with a breathing machine as described in § 84.88. (b) The open-circuit apparatus will...

  5. 42 CFR 84.96 - Service time test; closed-circuit apparatus.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 42 Public Health 1 2010-10-01 2010-10-01 false Service time test; closed-circuit apparatus. 84.96...-Contained Breathing Apparatus § 84.96 Service time test; closed-circuit apparatus. (a) The closed-circuit apparatus will be classified according to the length of time it supplies adequate breathing gas to...

  6. 42 CFR 84.95 - Service time test; open-circuit apparatus.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 42 Public Health 1 2010-10-01 2010-10-01 false Service time test; open-circuit apparatus. 84.95...-Contained Breathing Apparatus § 84.95 Service time test; open-circuit apparatus. (a) Service time will be measured with a breathing machine as described in § 84.88. (b) The open-circuit apparatus will...

  7. Soft-error generation due to heavy-ion tracks in bipolar integrated circuits

    NASA Technical Reports Server (NTRS)

    Zoutendyk, J. A.

    1984-01-01

    Both bipolar and MOS integrated circuits have been empirically demonstrated to be susceptible to single-particle soft-error generation, commonly referred to as single-event upset (SEU), which is manifested in a bit-flip in a latch-circuit construction. Here, the intrinsic characteristics of SEU in bipolar (static) RAM's are demonstrated through results obtained from the modeling of this effect using computer circuit-simulation techniques. It is shown that as the dimensions of the devices decrease, the critical charge required to cause SEU decreases in proportion to the device cross-section. The overall results of the simulations are applicable to most integrated circuit designs.

  8. 37. SAR2, SHOWING OIL CIRCUIT BREAKERS (ABOVE) AND GENERATOR FIELD ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    37. SAR-2, SHOWING OIL CIRCUIT BREAKERS (ABOVE) AND GENERATOR FIELD COIL CONTROL RHEOSTATS (BELOW). SCE negative no. 10331, November 1, 1923. Photograph by G. Haven Bishop. - Santa Ana River Hydroelectric System, SAR-2 Powerhouse, Redlands, San Bernardino County, CA

  9. Test Generator for MATLAB Simulations

    NASA Technical Reports Server (NTRS)

    Henry, Joel

    2011-01-01

    MATLAB Automated Test Tool, version 3.0 (MATT 3.0) is a software package that provides automated tools that reduce the time needed for extensive testing of simulation models that have been constructed in the MATLAB programming language by use of the Simulink and Real-Time Workshop programs. MATT 3.0 runs on top of the MATLAB engine application-program interface to communicate with the Simulink engine. MATT 3.0 automatically generates source code from the models, generates custom input data for testing both the models and the source code, and generates graphs and other presentations that facilitate comparison of the outputs of the models and the source code for the same input data. Context-sensitive and fully searchable help is provided in HyperText Markup Language (HTML) format.

  10. Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools

    NASA Astrophysics Data System (ADS)

    Higami, Yoshinobu; Saluja, Kewal K.; Takahashi, Hiroshi; Kobayashi, Shin-Ya; Takamatsu, Yuzo

    This paper presents methods for detecting transistor short faults using logic level fault simulation and test generation. The paper considers two types of transistor level faults, namely strong shorts and weak shorts, which were introduced in our previous research. These faults are defined based on the values of outputs of faulty gates. The proposed fault simulation and test generation are performed using gate-level tools designed to deal with stuck-at faults, and no transistor-level tools are required. In the test generation process, a circuit is modified by inserting inverters, and a stuck-at test generator is used. The modification of a circuit does not mean a design-for-testability technique, as the modified circuit is used only during the test generation process. Further, generated test patterns are compacted by fault simulation. Also, since the weak short model involves uncertainty in its behavior, we define fault coverage and fault efficiency in three different way, namely, optimistic, pessimistic and probabilistic and assess them. Finally, experimental results for ISCAS benchmark circuits are used to demonstrate the effectiveness of the proposed methods.

  11. Note: Picosecond impulse generator driven by cascaded step recovery diode pulse shaping circuit.

    PubMed

    Choi, Gil Wong; Choi, Jin Joo; Han, Seung Hoon

    2011-01-01

    In this paper, a picosecond impulse generator using step recovery diodes (SRDs) is presented. In order to reduce the pulse width of an impulse generator, we employed a cascaded SRD pulse-shaping circuit. A short impulse generation is confirmed in numerical simulation of a time-transient circuit simulator. Measurements show that the measured pulse width of the cascaded SRD impulse generator is 250 ps at 10% of the peak amplitude, which is improved by 85 ps compared with a conventional SRD impulse generator. PMID:21280869

  12. Note: Picosecond impulse generator driven by cascaded step recovery diode pulse shaping circuit

    NASA Astrophysics Data System (ADS)

    Wong Choi, Gil; Joo Choi, Jin; Hoon Han, Seung

    2011-01-01

    In this paper, a picosecond impulse generator using step recovery diodes (SRDs) is presented. In order to reduce the pulse width of an impulse generator, we employed a cascaded SRD pulse-shaping circuit. A short impulse generation is confirmed in numerical simulation of a time-transient circuit simulator. Measurements show that the measured pulse width of the cascaded SRD impulse generator is 250 ps at 10% of the peak amplitude, which is improved by 85 ps compared with a conventional SRD impulse generator.

  13. A test technique for measuring lightning-induced voltages on aircraft electrical circuits

    NASA Technical Reports Server (NTRS)

    Walko, L. C.

    1974-01-01

    The development of a test technique used for the measurement of lightning-induced voltages in the electrical circuits of a complete aircraft is described. The resultant technique utilizes a portable device known as a transient analyzer capable of generating unidirectional current impulses similar to lightning current surges, but at a lower current level. A linear relationship between the magnitude of lightning current and the magnitude of induced voltage permitted the scaling up of measured induced values to full threat levels. The test technique was found to be practical when used on a complete aircraft.

  14. Design and testing of integrated circuits for reactor protection channels

    SciTech Connect

    Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.; Rana, I.

    1995-06-01

    Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. Purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing.

  15. New downhole steam generator tested

    SciTech Connect

    Bleakley, W.B.

    1981-07-01

    Completion of 2 field tests of a new-model down-hole steam generator paves the way for further evaluation and development of a system destined to increase California's heavy oil production. Current air pollution restrictions there prevent installation of conventional steam generators in several areas of interest to oil operators. The current series of tests, conducted by Chemical Oil Recovery Co. (CORCO) of Bakersfield, California, follows an earlier prototype operation conducted by Sandia National Laboratories in conjunction with the US Department of Energy. The CORCO tests were conducted on the surface with the generator's output going into Tenneco Oil Exploration and Production Co.'s overland-Riokern Well No. 80, located in the Kern River field 4 miles north of Bakersfield. The first test was concluded with just under 1000 bbl of steam injected, less than planned due to a higher-than-expected injection pressure. The unit operated at less than 25% capacity because of the air compressor limitation. Compressor output was only 285 psi, not enough to inject the desired volumes into the reservoir. Test data shows that injection amounted to 150 bpd of 90 to 95% quality steam at 225-psi wellhead pressure. After injection, the well was shut in for 3 days to allow soaking, then put on production. Initial production was 40 bopd at 175 F.

  16. Research of 100 MHz ultra-low-jitter clock generating circuit

    SciTech Connect

    Qiu, Duyu; Tan, Feng; Tian, Shulin; Zeng, Hao; Ye, Peng

    2015-04-15

    Jitter which quantifies the quality of a clock is an important specification. It is of great significance for an electronic system. To obtain a good signal-to-noise ratio for sampling systems, there must be clocks with low jitter performances. By using the relationship between jitter and phase noise, the 100 MHz clock generating circuit with ultra-low jitter and phase noise characteristics are studied in this paper. Bipolar junction transistor with low noise figure and low corner frequency should be selected. Inductance and capacitance in the feedback circuit are obviously the main contributions to the jitter. Impacts of the loaded quality factor (Q{sub L}) of the circuit on the jitter are analyzed, and the explicit expression for the jitter based on circuit components is derived as well. The simulation and experiment results are proved to show that the jitter and phase noise characteristics can be improved by increasing Q{sub L} of the circuit.

  17. Apparatus for and method of testing an electrical ground fault circuit interrupt device

    DOEpatents

    Andrews, Lowell B.

    1998-01-01

    An apparatus for testing a ground fault circuit interrupt device includes a processor, an input device connected to the processor for receiving input from an operator, a storage media connected to the processor for storing test data, an output device connected to the processor for outputting information corresponding to the test data to the operator, and a calibrated variable load circuit connected between the processor and the ground fault circuit interrupt device. The ground fault circuit interrupt device is configured to trip a corresponding circuit breaker. The processor is configured to receive signals from the calibrated variable load circuit and to process the signals to determine a trip threshold current and/or a trip time. A method of testing the ground fault circuit interrupt device includes a first step of providing an identification for the ground fault circuit interrupt device. Test data is then recorded in accordance with the identification. By comparing test data from an initial test with test data from a subsequent test, a trend of performance for the ground fault circuit interrupt device is determined.

  18. Apparatus for and method of testing an electrical ground fault circuit interrupt device

    DOEpatents

    Andrews, L.B.

    1998-08-18

    An apparatus for testing a ground fault circuit interrupt device includes a processor, an input device connected to the processor for receiving input from an operator, a storage media connected to the processor for storing test data, an output device connected to the processor for outputting information corresponding to the test data to the operator, and a calibrated variable load circuit connected between the processor and the ground fault circuit interrupt device. The ground fault circuit interrupt device is configured to trip a corresponding circuit breaker. The processor is configured to receive signals from the calibrated variable load circuit and to process the signals to determine a trip threshold current and/or a trip time. A method of testing the ground fault circuit interrupt device includes a first step of providing an identification for the ground fault circuit interrupt device. Test data is then recorded in accordance with the identification. By comparing test data from an initial test with test data from a subsequent test, a trend of performance for the ground fault circuit interrupt device is determined. 17 figs.

  19. The Generation Effect: Activating Broad Neural Circuits During Memory Encoding

    PubMed Central

    Rosner, Zachary A.; Elman, Jeremy A.; Shimamura, Arthur P.

    2012-01-01

    The generation effect is a robust memory phenomenon in which actively producing material during encoding acts to improve later memory performance. In an fMRI analysis, we explored the neural basis of this effect. During encoding, participants generated synonyms from word-fragment cues (e.g. GARBAGE-W_ST_) or read other synonym pairs (e.g. GARBAGE-WASTE). Compared to simply reading target words, generating target words significantly improved later recognition memory performance. During encoding, this benefit was associated with a broad neural network that involved both prefrontal (inferior frontal gyrus, middle frontal gyrus) and posterior cortex (inferior temporal gyrus, lateral occipital cortex, parahippocampal gyrus, ventral posterior parietal cortex). These findings define the prefrontal-posterior cortical dynamics associated with the mnemonic benefits underlying the generation effect. PMID:23079490

  20. 42 CFR 84.93 - Gas flow test; open-circuit apparatus.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 42 Public Health 1 2014-10-01 2014-10-01 false Gas flow test; open-circuit apparatus. 84.93...-Contained Breathing Apparatus § 84.93 Gas flow test; open-circuit apparatus. (a) A static-flow test will be...) water-column height when full container pressure is applied. (c) Where pressure demand apparatus...

  1. 42 CFR 84.93 - Gas flow test; open-circuit apparatus.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... 42 Public Health 1 2013-10-01 2013-10-01 false Gas flow test; open-circuit apparatus. 84.93...-Contained Breathing Apparatus § 84.93 Gas flow test; open-circuit apparatus. (a) A static-flow test will be...) water-column height when full container pressure is applied. (c) Where pressure demand apparatus...

  2. 42 CFR 84.93 - Gas flow test; open-circuit apparatus.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 42 Public Health 1 2012-10-01 2012-10-01 false Gas flow test; open-circuit apparatus. 84.93...-Contained Breathing Apparatus § 84.93 Gas flow test; open-circuit apparatus. (a) A static-flow test will be...) water-column height when full container pressure is applied. (c) Where pressure demand apparatus...

  3. Modifications and Modelling of the Fission Surface Power Primary Test Circuit (FSP-PTC)

    NASA Technical Reports Server (NTRS)

    Garber, Ann E.

    2008-01-01

    An actively pumped alkali metal flow circuit, designed and fabricated at the NASA Marshall Space Flight Center, underwent a range of tests at MSFC in early 2007. During this period, system transient responses and the performance of the liquid metal pump were evaluated. In May of 2007, the circuit was drained and cleaned to prepare for multiple modifications: the addition of larger upper and lower reservoirs, the installation of an annular linear induction pump (ALIP), and the inclusion of the Single Flow Cell Test Apparatus (SFCTA) in the test section. Performance of the ALIP, provided by Idaho National Laboratory (INL), will be evaluated when testing resumes. The SFCTA, which will be tested simultaneously, will provide data on alkali metal flow behavior through the simulated core channels and assist in the development of a second generation thermal simulator. Additionally, data from the first round of testing has been used to refine the working system model, developed using the Generalized Fluid System Simulation Program (GFSSP). This paper covers the modifications of the FSP-PTC and the updated GFSSP system model.

  4. Downhole steam generator: field tests

    SciTech Connect

    Eson, R.L.

    1982-01-01

    Excessive air pollution and heat losses up to 32% in the surface lines and out the stacks of conventional generators are reasons why conventional steam generation is efficient. These problems are addressed and overcome through the use of a direct-fired down-hole steam generator (DSG). By performing the combustion process at high pressure, and then adding water, a mixture of carbon dioxide, nitrogen, and steam is discharged directly into the heavy oil reservoir. This study documents a series of field tests of a direct-fired DSG showing its ability to produce and inject high quality steam into heavy oil reservoirs without the need for expensive stack scrubbers to remove sulfur dioxide (SO/sub 2/), as well as sophisticated nitrogen oxides (NO/sub x/) control techniques. Results from the 6-in. diameter, 6-ft long, 7.1-mmBtu/hr DSG showed that corrosion can be controlled and production can be improved dramatically in actual field tests in California heavy oil reservoirs.

  5. Traveling-Wave Tube Cold-Test Circuit Optimization Using CST MICROWAVE STUDIO

    NASA Technical Reports Server (NTRS)

    Chevalier, Christine T.; Kory, Carol L.; Wilson, Jeffrey D.; Wintucky, Edwin G.; Dayton, James A., Jr.

    2003-01-01

    The internal optimizer of CST MICROWAVE STUDIO (MWS) was used along with an application-specific Visual Basic for Applications (VBA) script to develop a method to optimize traveling-wave tube (TWT) cold-test circuit performance. The optimization procedure allows simultaneous optimization of circuit specifications including on-axis interaction impedance, bandwidth or geometric limitations. The application of Microwave Studio to TWT cold-test circuit optimization is described.

  6. Optimal testing input sets for reduced diagnosis time of nuclear power plant digital electronic circuits

    SciTech Connect

    Kim, D.S.; Seong, P.H. . Dept. of Nuclear Engineering)

    1994-02-01

    This paper describes the optimal testing input sets required for the fault diagnosis of the nuclear power plant digital electronic circuits. With the complicated systems such as very large scale integration (VLSI), nuclear power plant (NPP), and aircraft, testing is the major factor of the maintenance of the system. Particularly, diagnosis time grows quickly with the complexity of the component. In this research, for reduce diagnosis time the authors derived the optimal testing sets that are the minimal testing sets required for detecting the failure and for locating of the failed component. For reduced diagnosis time, the technique presented by Hayes fits best for the approach to testing sets generation among many conventional methods. However, this method has the following disadvantages: (a) it considers only the simple network (b) it concerns only whether the system is in failed state or not and does not provide the way to locate the failed component. Therefore the authors have derived the optimal testing input sets that resolve these problems by Hayes while preserving its advantages. When they applied the optimal testing sets to the automatic fault diagnosis system (AFDS) which incorporates the advanced fault diagnosis method of artificial intelligence technique, they found that the fault diagnosis using the optimal testing sets makes testing the digital electronic circuits much faster than that using exhaustive testing input sets; when they applied them to test the Universal (UV) Card which is a nuclear power plant digital input/output solid state protection system card, they reduced the testing time up to about 100 times.

  7. Emulation of high-frequency substrate noise generation in CMOS digital circuits

    NASA Astrophysics Data System (ADS)

    Shimazaki, Shunsuke; Taga, Shota; Makita, Tetsuya; Azuma, Naoya; Miura, Noriyuki; Nagata, Makoto

    2014-01-01

    A noise emulator is based on the capacitor charging modeling and generates power and substrate noises expected in a CMOS digital integrated circuit. An off-chip near-magnetic-field sensor indirectly characterizes the distribution of clock timing and the adjustability of skews within on-chip digital circuits. An on-chip noise monitor captures power and substrate noise waveforms and evaluates noise frequency components in a wide frequency bandwidth. A 65 nm CMOS prototype demonstrated power and substrate noise generation in a variety of operating scenarios of digital integrated circuits. Power noise generation emulated at 125 MHz exhibits the enhancements of high-order harmonic components after deskewing at a timing resolution of 37.8 ps, as is specifically seen in more than 10 dB enlargement of the substrate noise component at 2.1 GHz.

  8. Neural circuits underlying the generation of theta oscillations.

    PubMed

    Pignatelli, Michele; Beyeler, Anna; Leinekugel, Xavier

    2012-01-01

    Theta oscillations represent the neural network configuration underlying active awake behavior and paradoxical sleep. This major EEG pattern has been extensively studied, from physiological to anatomical levels, for more than half a century. Nevertheless the cellular and network mechanisms accountable for the theta generation are still not fully understood. This review synthesizes the current knowledge on the circuitry involved in the generation of theta oscillations, from the hippocampus to extra hippocampal structures such as septal complex, entorhinal cortex and pedunculopontine tegmentum, a main trigger of theta state through direct and indirect projections to the septal complex. We conclude with a short overview of the perspectives offered by technical advances for deciphering more precisely the different neural components underlying the emergence of theta oscillations. PMID:21964249

  9. An oscillatory neuronal circuit generating a locomotory rhythm.

    PubMed Central

    Friesen,, W O; Poon, M; Stent, G S

    1976-01-01

    A quartet of interconnected interneurons whose periodic activity appears to generate the traveling body wave of the swimming leech has been identified on each side of segmental ganglia of the ventral nerve cord of Hirudo medicinalis. Theoretical analysis and electronic analog models of the identified intra- and interganglionic synaptic connections of the segmentally iterated interneurons showed that they form an oscillatory network with cycle period and intra-and intersegmental phase relations appropriate for the swimming movement. Images PMID:1068483

  10. 42 CFR 84.95 - Service time test; open-circuit apparatus.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... classified according to the length of time it supplies air or oxygen to the breathing machine. (c) The... 42 Public Health 1 2012-10-01 2012-10-01 false Service time test; open-circuit apparatus. 84.95...-Contained Breathing Apparatus § 84.95 Service time test; open-circuit apparatus. (a) Service time will...

  11. 42 CFR 84.95 - Service time test; open-circuit apparatus.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... classified according to the length of time it supplies air or oxygen to the breathing machine. (c) The... 42 Public Health 1 2013-10-01 2013-10-01 false Service time test; open-circuit apparatus. 84.95...-Contained Breathing Apparatus § 84.95 Service time test; open-circuit apparatus. (a) Service time will...

  12. 42 CFR 84.94 - Gas flow test; closed-circuit apparatus.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 42 Public Health 1 2011-10-01 2011-10-01 false Gas flow test; closed-circuit apparatus. 84.94...-Contained Breathing Apparatus § 84.94 Gas flow test; closed-circuit apparatus. (a) Where oxygen is supplied... rated service time of the apparatus. (b) Where constant flow is used in conjunction with demand...

  13. 47 CFR 80.867 - Ship station tools, instruction books, circuit diagrams and testing equipment.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 47 Telecommunication 5 2011-10-01 2011-10-01 false Ship station tools, instruction books, circuit... Requirements for Cargo Vessels Not Subject to Subpart W § 80.867 Ship station tools, instruction books, circuit diagrams and testing equipment. (a) Each ship station must be provided with such tools, testing...

  14. A complete hardening method for the generation of fault tolerant circuits

    NASA Astrophysics Data System (ADS)

    Portela-Garcia, Marta; Garcia-Valderas, Mario; Lopez-Ongil, Celia; Entrena, Luis

    2005-06-01

    Fault Tolerance has become an important requirement for integrated circuits, not only in safety critical applications like aerospace circuits, but also for applications working at the earth surface. Since the appearance of nanometer technologies, the sensitiveness of integrated circuits to radiation has increased notably, making the occurrence of soft errors much more frequent. Therefore, hardened circuits are currently required in many applications where fault tolerance was not a requirement in the very near past. In this paper, tools and methods for the whole hardening process of a circuit are presented: tools for the automatic insertion of fault tolerant structures in a circuit description and methods for the evaluation of fault tolerance achieved. These methods allow the evaluation of fault tolerance by means of emulation in platform FPGAs, which offer a much faster way to perform evaluation than simulation based techniques. Different circuits are used to test the proposed tool for inserting fault tolerant structures. Fault tolerance evaluation is performed using the proposed fault emulation methods, before and after applying hardening process, showing the fault tolerance improvement. The proposed techniques for evaluation have been compared, in terms of evaluation time, with previously proposed solutions and with simulation based solutions, showing improvements of several orders of magnitude.

  15. Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

    NASA Technical Reports Server (NTRS)

    Buehler, M. G. (Inventor)

    1985-01-01

    An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

  16. Performance testing of thermoelectric generators at JPL

    NASA Technical Reports Server (NTRS)

    Rouklove, P.; Truscello, V.

    1974-01-01

    Results of life tests of thermoelectric generators ranging in output power from 800 microwatts to 170 watts. Emphasis is placed on the results obtained from tests of three advanced prototypes - a high-performance generator, a transit-type generator, and a ring converter. In addition, the results of life tests of a number of generators representing Nimbus, Pioneer, and Viking technology are presented.

  17. Investigation of DC hybrid circuit breaker based on high-speed switch and arc generator.

    PubMed

    Wu, Yifei; Rong, Mingzhe; Wu, Yi; Yang, Fei; Li, Mei; Zhong, Jianying; Han, Guohui; Niu, Chunping; Hu, Yang

    2015-02-01

    A new design of DC hybrid circuit breaker based on high-speed switch (HSS) and arc generator (AG), which can drastically profit from low heat loss in normal state and fast current breaking under fault state, is presented and analyzed in this paper. AG is designed according to the magnetic pinch effect of liquid metal. By utilizing the arc voltage generated across AG, the fault current is rapidly commutated from HSS into parallel connected branch. As a consequence, the arcless open of HSS is achieved. The post-arc conducting resume time (Δ tc) of AG and the commutation original voltage (Uc), two key factors in the commutation process, are investigated experimentally. Particularly, influences of the liquid metal channel diameter (Φ) of AG, fault current rate of rise (di/dt) and Uc on Δ tc are focused on. Furthermore, a suitable Uc is determined during the current commutation process, aiming at the reliable arcless open of HSS and short breaking time. Finally, the fault current breaking test is carried out for the current peak value of 11.8 kA, and the validity of the design is confirmed by the experimental results. PMID:25725867

  18. Investigation of DC hybrid circuit breaker based on high-speed switch and arc generator

    NASA Astrophysics Data System (ADS)

    Wu, Yifei; Rong, Mingzhe; Wu, Yi; Yang, Fei; Li, Mei; Zhong, Jianying; Han, Guohui; Niu, Chunping; Hu, Yang

    2015-02-01

    A new design of DC hybrid circuit breaker based on high-speed switch (HSS) and arc generator (AG), which can drastically profit from low heat loss in normal state and fast current breaking under fault state, is presented and analyzed in this paper. AG is designed according to the magnetic pinch effect of liquid metal. By utilizing the arc voltage generated across AG, the fault current is rapidly commutated from HSS into parallel connected branch. As a consequence, the arcless open of HSS is achieved. The post-arc conducting resume time (Δ tc) of AG and the commutation original voltage (Uc), two key factors in the commutation process, are investigated experimentally. Particularly, influences of the liquid metal channel diameter (Φ) of AG, fault current rate of rise (di/dt) and Uc on Δ tc are focused on. Furthermore, a suitable Uc is determined during the current commutation process, aiming at the reliable arcless open of HSS and short breaking time. Finally, the fault current breaking test is carried out for the current peak value of 11.8 kA, and the validity of the design is confirmed by the experimental results.

  19. Testing of printed circuit board solder joints by optical correlation

    NASA Technical Reports Server (NTRS)

    Espy, P. N.

    1975-01-01

    An optical correlation technique for the nondestructive evaluation of printed circuit board solder joints was evaluated. Reliable indications of induced stress levels in solder joint lead wires are achievable. Definite relations between the inherent strength of a solder joint, with its associated ability to survive stress, are demonstrable.

  20. Development and Simulation of Increased Generation on a Secondary Circuit of a Microgrid

    NASA Astrophysics Data System (ADS)

    Reyes, Karina

    As fossil fuels are depleted and their environmental impacts remain, other sources of energy must be considered to generate power. Renewable sources, for example, are emerging to play a major role in this regard. In parallel, electric vehicle (EV) charging is evolving as a major load demand. To meet reliability and resiliency goals demanded by the electricity market, interest in microgrids are growing as a distributed energy resource (DER). In this thesis, the effects of intermittent renewable power generation and random EV charging on secondary microgrid circuits are analyzed in the presence of a controllable battery in order to characterize and better understand the dynamics associated with intermittent power production and random load demands in the context of the microgrid paradigm. For two reasons, a secondary circuit on the University of California, Irvine (UCI) Microgrid serves as the case study. First, the secondary circuit (UC-9) is heavily loaded and an integral component of a highly characterized and metered microgrid. Second, a unique "next-generation" distributed energy resource has been deployed at the end of the circuit that integrates photovoltaic power generation, battery storage, and EV charging. In order to analyze this system and evaluate the impact of the DER on the secondary circuit, a model was developed to provide a real-time load flow analysis. The research develops a power management system applicable to similarly integrated systems. The model is verified by metered data obtained from a network of high resolution electric meters and estimated load data for the buildings that have unknown demand. An increase in voltage is observed when the amount of photovoltaic power generation is increased. To mitigate this effect, a constant power factor is set. Should the real power change dramatically, the reactive power is changed to mitigate voltage fluctuations.

  1. A versatile waveform generator for testing neuroelectric signal processors.

    PubMed

    Kohn, A F

    1989-08-01

    A multi-channel waveform generator was designed for testing neuroelectric signal processors. Smooth transient signals that resemble action potentials or evoked potentials are generated by a second order switched capacitor filter excited by brief rectangular pulses. The choice of an integrated circuit switched capacitor filter simplified the design by circumventing some of the disadvantages of conventional active filters. The waveform generator is versatile, with several signal parameters being independently adjustable from front panel controls: duration, waveshape, latency, amplitude and signal-to-noise ratio. The generator has been used for testing evoked potential acquisition and processing systems, for evaluating the effects of analog filters on evoked potentials and for testing systems designed to detect and classify trains of multi-unit action potentials. PMID:2770339

  2. Test Writing Made Simple: Generate Tests and Worksheets Electronically.

    ERIC Educational Resources Information Center

    Lodish, Erica

    1986-01-01

    Describes capabilities of test and worksheet generator software; discusses features to consider when evaluating the software for purchase; and presents reviews of eight test and worksheet generators: P.D.Q., Testmaster, Easy Quiz Maker, EA Mathematics Worksheet Generator, Mathematics Worksheet Generator, Earth Science Test Maker, Individualized…

  3. Variable cooling circuit for thermoelectric generator and engine and method of control

    DOEpatents

    Prior, Gregory P

    2012-10-30

    An apparatus is provided that includes an engine, an exhaust system, and a thermoelectric generator (TEG) operatively connected to the exhaust system and configured to allow exhaust gas flow therethrough. A first radiator is operatively connected to the engine. An openable and closable engine valve is configured to open to permit coolant to circulate through the engine and the first radiator when coolant temperature is greater than a predetermined minimum coolant temperature. A first and a second valve are controllable to route cooling fluid from the TEG to the engine through coolant passages under a first set of operating conditions to establish a first cooling circuit, and from the TEG to a second radiator through at least some other coolant passages under a second set of operating conditions to establish a second cooling circuit. A method of controlling a cooling circuit is also provided.

  4. Note: Complementary metal-oxide-semiconductor high voltage pulse generation circuits

    NASA Astrophysics Data System (ADS)

    Sun, Jiwei; Wang, Pingshan

    2013-10-01

    We present two types of on-chip pulse generation circuits. The first is based on CMOS pulse-forming-lines (PFLs). It includes a four-stage charge pump, a four-stacked-MOSFET switch and a 5 mm long PFL. The circuit is implemented in a 0.13 μm CMOS process. Pulses of ˜1.8 V amplitude with ˜135 ps duration on a 50 Ω load are obtained. The obtained voltage is higher than 1.6 V, the rated operating voltage of the process. The second is a high-voltage Marx generator which also uses stacked MOSFETs as high voltage switches. The output voltage is 11.68 V, which is higher than the highest breakdown voltage (˜10 V) of the CMOS process. These results significantly extend high-voltage pulse generation capabilities of CMOS technologies.

  5. Note: Complementary metal-oxide-semiconductor high voltage pulse generation circuits.

    PubMed

    Sun, Jiwei; Wang, Pingshan

    2013-10-01

    We present two types of on-chip pulse generation circuits. The first is based on CMOS pulse-forming-lines (PFLs). It includes a four-stage charge pump, a four-stacked-MOSFET switch and a 5 mm long PFL. The circuit is implemented in a 0.13 μm CMOS process. Pulses of ~1.8 V amplitude with ~135 ps duration on a 50 Ω load are obtained. The obtained voltage is higher than 1.6 V, the rated operating voltage of the process. The second is a high-voltage Marx generator which also uses stacked MOSFETs as high voltage switches. The output voltage is 11.68 V, which is higher than the highest breakdown voltage (~10 V) of the CMOS process. These results significantly extend high-voltage pulse generation capabilities of CMOS technologies. PMID:24182184

  6. Automated Test-Form Generation

    ERIC Educational Resources Information Center

    van der Linden, Wim J.; Diao, Qi

    2011-01-01

    In automated test assembly (ATA), the methodology of mixed-integer programming is used to select test items from an item bank to meet the specifications for a desired test form and optimize its measurement accuracy. The same methodology can be used to automate the formatting of the set of selected items into the actual test form. Three different…

  7. Initial Testing of the Stainless Steel NaK-Cooled Circuit (SNaKC)

    NASA Technical Reports Server (NTRS)

    Garber, Anne; Godfroy, Thomas

    2007-01-01

    An actively pumped alkali metal flow circuit, designed and fabricated at the NASA Marshall Space Flight Center, is currently undergoing testing in the Early Flight Fission Test Facility (EFF-TF). Sodium potassium (NaK) was selected as the primary coolant. Basic circuit components include: simulated reactor core, NaK to gas heat exchanger, electromagnetic liquid metal pump, liquid metal flowmeter, load/drain reservoir, expansion reservoir, test section, and instrumentation. Operation of the circuit is based around the 37-pin partial-array core (pin and flow path dimensions are the same as those in a full core), designed to operate at 33 kWt. This presentation addresses the construction, fill and initial testing of the Stainless Steel NaK-Cooled Circuit (SNaKC).

  8. Design and test of clock distribution circuits for the Macro Pixel ASIC

    NASA Astrophysics Data System (ADS)

    Gaioni, L.; De Canio, F.; Manghisoni, M.; Ratti, L.; Re, V.; Traversi, G.

    2016-07-01

    Clock distribution circuits account for a significant fraction of the power dissipation of the Macro Pixel ASIC (MPA), designed for the pixel layer readout of the so-called Pixel-Strip module in the innermost part of the CMS tracker at the High Luminosity LHC. A test chip including low power clock distribution circuits of the MPA has been designed in a 65 nm CMOS technology and thoroughly tested. This work summarizes the experimental results relevant to the prototype chip, focusing particularly on the power and speed performance and compares such results with those coming from circuit simulations.

  9. Generator acceptance test and inspection report

    SciTech Connect

    Johns, B.R.

    1997-07-24

    This Acceptance Test Report(ATR) is the completed testing and inspection of the new portable generator. The testing and inspection is to verify that the generator provided by the vendor meets the requirements of specification WHC-S-0252, Revision 2. Attached is various other documentation to support the inspection and testing.

  10. Off-Line Testing for Bridge Faults in CMOS Domino Logic Circuits

    NASA Technical Reports Server (NTRS)

    Bennett, K.; Lala, P. K.; Busaba, F.

    1997-01-01

    Bridge faults, especially in CMOS circuits, have unique characteristics which make them difficult to detect during testing. This paper presents a technique for detecting bridge faults which have an effect on the output of CMOS Domino logic circuits. The faults are modeled at the transistor level and this technique is based on analyzing the off-set of the function during off-line testing.

  11. Feedback from network states generates variability in a probabilistic olfactory circuit

    PubMed Central

    Gordus, Andrew; Pokala, Navin; Levy, Sagi; Flavell, Steven W.; Bargmann, Cornelia I

    2016-01-01

    Summary Variability is a prominent feature of behavior, and an active element of certain behavioral strategies. To understand how neuronal circuits control variability, we examined the propagation of sensory information in a chemotaxis circuit of Caenorhabditis elegans where discrete sensory inputs can drive a probabilistic behavioral response. Olfactory neurons respond to odor stimuli with rapid and reliable changes in activity, but downstream AIB interneurons respond with a probabilistic delay. The interneuron response to odor depends on the collective activity of multiple neurons – AIB, RIM, and AVA -- when the odor stimulus arrives. Certain activity states of the network correlate with reliable responses to odor stimuli. Artificially generating these activity states by modifying neuronal activity increases the reliability of odor responses in interneurons and the reliability of the behavioral response to odor. The integration of sensory information with network state may represent a general mechanism for generating variability in behavior. PMID:25772698

  12. A miniature microcontroller curve tracing circuit for space flight testing transistors

    NASA Astrophysics Data System (ADS)

    Prokop, N.; Greer, L.; Krasowski, M.; Flatico, J.; Spina, D.

    2015-02-01

    This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results.

  13. Method of boundary testing of the electric circuits and its application for calculating electric tolerances. [electric equipment tests

    NASA Technical Reports Server (NTRS)

    Redkina, N. P.

    1974-01-01

    Boundary testing of electric circuits includes preliminary and limiting tests. Preliminary tests permit determination of the critical parameters causing the greatest deviation of the output parameter of the system. The boundary tests offer the possibility of determining the limits of the fitness of the system with simultaneous variation of its critical parameters.

  14. Architectures and Design for Next-Generation Hybrid Circuit/Packet Networks

    NASA Astrophysics Data System (ADS)

    Vadrevu, Sree Krishna Chaitanya

    Internet traffic is increasing rapidly at an annual growth rate of 35% with aggregate traffic exceeding several Exabyte's per month. The traffic is also becoming heterogeneous in bandwidth and quality-of-service (QoS) requirements with growing popularity of cloud computing, video-on-demand (VoD), e-science, etc. Hybrid circuit/packet networks which can jointly support circuit and packet services along with the adoption of high-bit-rate transmission systems form an attractive solution to address the traffic growth. 10 Gbps and 40 Gbps transmission systems are widely deployed in telecom backbone networks such as Comcast, AT&T, etc., and network operators are considering migration to 100 Gbps and beyond. This dissertation proposes robust architectures, capacity migration strategies, and novel service frameworks for next-generation hybrid circuit/packet architectures. In this dissertation, we study two types of hybrid circuit/packet networks: a) IP-over-WDM networks, in which the packet (IP) network is overlaid on top of the circuit (optical WDM) network and b) Hybrid networks in which the circuit and packet networks are deployed side by side such as US DoE's ESnet. We investigate techniques to dynamically migrate capacity between the circuit and packet sections by exploiting traffic variations over a day, and our methods show that significant bandwidth savings can be obtained with improved reliability of services. Specifically, we investigate how idle backup circuit capacity can be used to support packet services in IP-over-WDM networks, and similarly, excess capacity in packet network to support circuit services in ESnet. Control schemes that enable our mechanisms are also discussed. In IP-over-WDM networks, with upcoming 100 Gbps and beyond, dedicated protection will induce significant under-utilization of backup resources. We investigate design strategies to loan idle circuit backup capacity to support IP/packet services. However, failure of backup circuits will

  15. Method for characterizing the upset response of CMOS circuits using alpha-particle sensitive test circuits

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G. (Inventor); Blaes, Brent R. (Inventor); Nixon, Robert H. (Inventor); Soli, George A. (Inventor)

    1995-01-01

    A method for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. A technique utilizing test structures to quickly and inexpensively characterize the SEU sensitivity of standard cell latches intended for use in a space environment. This bench-level approach utilizes alpha particles to induce upsets in a low LET sensitive 4-k bit test SRAM. This SRAM consists of cells that employ an offset voltage to adjust their upset sensitivity and an enlarged sensitive drain junction to enhance the cell's upset rate.

  16. A Novel Picosecond Pulse Generation Circuit Based on SRD and NLTL

    PubMed Central

    Zhou, Jianming; Lu, Qiuyuan; Liu, Fan; Li, Yinqiao

    2016-01-01

    Because of the importance of ultra-wideband (UWB) radar in various applications, short pulse generation in UWB systems has attracted a lot of attention in recent years. In order to shorten the pulse, nonlinear transmission line (NLTL) is imported, which expands the application of step recovery diode (SRD) for pulse generation. Detailed analysis and equations for this SRD and NLTL-based pulse generation are provided and verified by simulation and experimental results. Factors that could cause pulse waveform distortions are also analyzed. The generator circuit presented in this paper generates 130ps and 3.3V pulse, which can be used in UWB radar systems that require sub-nanosecond pulses. PMID:26919290

  17. A Novel Picosecond Pulse Generation Circuit Based on SRD and NLTL.

    PubMed

    Zhou, Jianming; Lu, Qiuyuan; Liu, Fan; Li, Yinqiao

    2016-01-01

    Because of the importance of ultra-wideband (UWB) radar in various applications, short pulse generation in UWB systems has attracted a lot of attention in recent years. In order to shorten the pulse, nonlinear transmission line (NLTL) is imported, which expands the application of step recovery diode (SRD) for pulse generation. Detailed analysis and equations for this SRD and NLTL-based pulse generation are provided and verified by simulation and experimental results. Factors that could cause pulse waveform distortions are also analyzed. The generator circuit presented in this paper generates 130ps and 3.3V pulse, which can be used in UWB radar systems that require sub-nanosecond pulses. PMID:26919290

  18. Development of a Novel Test Method for On-Demand Internal Short Circuit in a Li-Ion Cell (Presentation)

    SciTech Connect

    Keyser, M.; Long, D.; Jung, Y. S.; Pesaran, A.; Darcy, E.; McCarthy, B.; Patrick, L.; Kruger, C.

    2011-01-01

    This presentation describes a cell-level test method that simulates an emergent internal short circuit, produces consistent and reproducible test results, can establish the locations and temperatures/power/SOC conditions where an internal short circuit will result in thermal runaway, and provides relevant data to validate internal short circuit models.

  19. Electronic load for testing power generating devices

    NASA Technical Reports Server (NTRS)

    Friedman, E. B.; Stepfer, G.

    1968-01-01

    Instrument tests various electric power generating devices by connecting the devices to the input of the load and comparing their outputs with a reference voltage. The load automatically adjusts until voltage output of the power generating device matches the reference.

  20. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  1. Design and testing of an active quenching circuit for an avalanche photodiode photon detector

    NASA Technical Reports Server (NTRS)

    Arbel, D.; Schwartz, J. A.

    1991-01-01

    The photon-detection capabilities of avalanche photodiodes (APDs) operating above their theoretical breakdown voltages are described, with particular attention given to the needs and methods of quenching an avalanche once breakdown has occurred. A brief background on the motives of and previous work with this mode of operation is presented. Finally, a description of the design and testing of an active quenching circuit is given. Although the active quenching circuit did not perform as expected, knowledge was gained as to the signal amplitudes necessary for quenching and the need for a better model for the above-breakdown circuit characteristics of the Geiger-mode APD.

  2. Molten-Caustic-Leaching (MCL or Gravimelt) System Integration Project. Topical report for test circuit operation

    SciTech Connect

    Not Available

    1990-11-01

    This is a report of the results obtained from the operation of an integrated test circuit for the Molten-Caustic-Leaching (MCL or Gravimelt) process for the desulfurization and demineralization of coal. The objectives of operational testing of the 20 pounds of coal per hour integrated MCL test circuit are: (1) to demonstrate the technical capability of the process for producing a demineralized and desulfurized coal that meets New Source Performance Standards (NSPS); (2) to determine the range of effective process operation; (3) to test process conditions aimed at significantly lower costs; and (4) to deliver product coal.

  3. Thermal verification testing of commercial printed-circuit boards for spaceflight

    NASA Technical Reports Server (NTRS)

    Foster, William M., II

    1992-01-01

    A method developed to verify commercial printed-circuit boards for a Shuttle orbital flight is discussed. The test sequence is based on early fault detection, desire to test the final assembly, and integration with other verification testing. A component thermal screening test is performed first to force flaws in design, workmanship, parts, processes, and materials into observable failures. Temperature definition and vibration tests are performed next. Final assembly testing is performed to simulate the Shuttle flight. An abbreviated thermal screening test is performed as a check after the vibration test, and then a complete thermal operational test is performed. The final assembly test finishes up with a burn-in of 100 h of trouble-free operation. Verification is successful when all components and final assemblies have passed each test. This method was very successful in verifying that commercial printed-circuit boards will survive in the Shuttle environment.

  4. Modifications to the Fission Surface Power Primary Test Circuit (FSP-PTC)

    NASA Technical Reports Server (NTRS)

    Garber, Anne E.

    2008-01-01

    An actively pumped alkali metal flow circuit, designed and fabricated at the NASA Marshall Space Flight Center, underwent a range of tests at MSFC in early 2007. During this period, system transient responses and the performance of the liquid metal pump were evaluated. In May of 2007, the circuit was drained and cleaned to prepare for multiple modifications: the addition of larger upper and lower reservoirs, the installation of an annular linear induction pump (ALIP), and the inclusion of a closeable orifice in the test section. Modifications are now complete and testing has resumed. Performance of the ALIp, provided by Idaho National Laboratory (INL), is the subject of the first round ofexperimentation. This paper provides a summary of the tests conducted on the original circuit, details the physical changes that have since been made to it, and describes the current test program.

  5. Generation of a macroscopic entangled coherent state using quantum memories in circuit QED

    PubMed Central

    Liu, Tong; Su, Qi-Ping; Xiong, Shao-Jie; Liu, Jin-Ming; Yang, Chui-Ping; Nori, Franco

    2016-01-01

    W-type entangled states can be used as quantum channels for, e.g., quantum teleportation, quantum dense coding, and quantum key distribution. In this work, we propose a way to generate a macroscopic W-type entangled coherent state using quantum memories in circuit QED. The memories considered here are nitrogen-vacancy center ensembles (NVEs), each located in a different cavity. This proposal does not require initially preparing each NVE in a coherent state instead of a ground state, which should significantly reduce its experimental difficulty. For most of the operation time, each cavity remains in a vacuum state, thus decoherence caused by the cavity decay and the unwanted inter-cavity crosstalk are greatly suppressed. Moreover, only one external-cavity coupler qubit is needed, which simplifies the circuit. PMID:27562055

  6. Generation of a macroscopic entangled coherent state using quantum memories in circuit QED.

    PubMed

    Liu, Tong; Su, Qi-Ping; Xiong, Shao-Jie; Liu, Jin-Ming; Yang, Chui-Ping; Nori, Franco

    2016-01-01

    W-type entangled states can be used as quantum channels for, e.g., quantum teleportation, quantum dense coding, and quantum key distribution. In this work, we propose a way to generate a macroscopic W-type entangled coherent state using quantum memories in circuit QED. The memories considered here are nitrogen-vacancy center ensembles (NVEs), each located in a different cavity. This proposal does not require initially preparing each NVE in a coherent state instead of a ground state, which should significantly reduce its experimental difficulty. For most of the operation time, each cavity remains in a vacuum state, thus decoherence caused by the cavity decay and the unwanted inter-cavity crosstalk are greatly suppressed. Moreover, only one external-cavity coupler qubit is needed, which simplifies the circuit. PMID:27562055

  7. F-1 Engine Gas Generator Testing

    NASA Video Gallery

    The gas generator from an F-1 engine is test-fired at the Marshall Space Flight Center in Huntsville, Ala., on Jan. 24, 2013. Data from the 30 second test will be used in the development of advance...

  8. Analysis of Distribution Circuits with High Penetrations of Photo-Voltaic Generation and Progressive Steps to Enable Higher Penetrations

    NASA Astrophysics Data System (ADS)

    Payne, Joshua Daniel

    Concern for anthropogenic climate change has instigated an increase in renewable generation capacity, including photo-voltaic (PV) power generation in distribution circuits. Distribution circuits with relatively high penetrations of PV generation (High-Pen PV) exist today, but how much more generation can distribution systems handle? This research aims to approach this question by 1) analyzing and quantifying High-Pen PV limitations on the primary circuits of distribution systems and 2) propose and analyze progressive steps to enable higher penetrations of PV on distribution circuits. Utilizing connectivity and load demand measurements provided by Pacific Gas & Electric (PG&E), time-resolved three-phase balanced feeder models of a commercial and a residential circuit featuring High-Pen PV were developed and calibrated to the point of the sub-station. Once calibrated, the circuit performance was simulated with varying PV penetrations and spatial distributions for typical seasonal high and seasonal low load demand days. Circuit scenarios with the Generation Center located downstream of the Load Center and with high impedance distribution line in-between lead to high voltage conditions. High-Pen PV interacting with the sub-station Load Drop Compensation (LDC) resulted an increased number of equipment operations and low voltage conditions on the circuit. As PV penetration increased, sub-station power factor and line loss decreased until reverse power flow became dominant. These were observed characteristics of High-Pen PV circuits. To overcome the limitations stated above, practical steps, such as line re-conductoring, and progressive control and operation changes were introduced. The progressive changes included using a Voltage Rise Siting (VRS) score for planning and LDC Current Compensation control to enable higher penetrations of PV. It was shown that limitations of High-Pen PV on the primary side of distribution circuits may be overcome via these practical and

  9. Assembly and Thermal Hydraulic Test of a Stainless Steel Sodium-Potassium Circuit

    NASA Technical Reports Server (NTRS)

    Garber, A.; Godfroy, T.; Webster, K.

    2007-01-01

    Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the NASA Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system was originally built for use with lithium, but due to a shift in focus, it was redesigned for use with a eutectic mixture of sodium potassium (NaK). Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This paper summarizes the first fill and checkout testing of the Stainless Steel NaK-Cooled Circuit (SNaKC).

  10. 4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

    NASA Technical Reports Server (NTRS)

    Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

    2015-01-01

    Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

  11. Life test of a nickel cadmium battery with a protection/reconditioning circuit

    NASA Technical Reports Server (NTRS)

    Lanier, J. R., Jr.; Bush, J. R., Jr.

    1981-01-01

    Results are discussed for a Ni-Cd battery test over a period of 8 years, 2 months and 44,213 simulated low Earth orbits. The battery cells were protected against overdischarge and reversal at discharge rates up to 25 amperes (1.25C) by a battery protection and reconditioning circuit. The circuit performed flawlessly during the test, and proved its value, both as a battery reconditioner and a cell protection device. Battery cell failures are also discussed. The test demonstrated the viability of using Ni-Cd batteries at depth-of-discharge up to 25 percent for over 5 years in a low Earth orbit.

  12. Revised evaluation of steam generator testing alternatives

    SciTech Connect

    1981-01-01

    A scoping evaluation was made of various facility alternatives for test of LMFBR prototype steam generators and models. Recommendations are given for modifications to EBR-II and SCTI (Sodium Components Test Installation) for prototype SG testing, and for few-tube model testing. (DLC)

  13. Development of a Three-Tier Test to Assess Misconceptions about Simple Electric Circuits

    ERIC Educational Resources Information Center

    Pesman, Haki; Eryilmaz, Ali

    2010-01-01

    The authors aimed to propose a valid and reliable diagnostic instrument by developing a three-tier test on simple electric circuits. Based on findings from the interviews, open-ended questions, and the related literature, the test was developed and administered to 124 high school students. In addition to some qualitative techniques for…

  14. Mechanisms of Left-Right Coordination in Mammalian Locomotor Pattern Generation Circuits: A Mathematical Modeling View

    PubMed Central

    Talpalar, Adolfo E.; Rybak, Ilya A.

    2015-01-01

    The locomotor gait in limbed animals is defined by the left-right leg coordination and locomotor speed. Coordination between left and right neural activities in the spinal cord controlling left and right legs is provided by commissural interneurons (CINs). Several CIN types have been genetically identified, including the excitatory V3 and excitatory and inhibitory V0 types. Recent studies demonstrated that genetic elimination of all V0 CINs caused switching from a normal left-right alternating activity to a left-right synchronized “hopping” pattern. Furthermore, ablation of only the inhibitory V0 CINs (V0D subtype) resulted in a lack of left-right alternation at low locomotor frequencies and retaining this alternation at high frequencies, whereas selective ablation of the excitatory V0 neurons (V0V subtype) maintained the left–right alternation at low frequencies and switched to a hopping pattern at high frequencies. To analyze these findings, we developed a simplified mathematical model of neural circuits consisting of four pacemaker neurons representing left and right, flexor and extensor rhythm-generating centers interacting via commissural pathways representing V3, V0D, and V0V CINs. The locomotor frequency was controlled by a parameter defining the excitation of neurons and commissural pathways mimicking the effects of N-methyl-D-aspartate on locomotor frequency in isolated rodent spinal cord preparations. The model demonstrated a typical left-right alternating pattern under control conditions, switching to a hopping activity at any frequency after removing both V0 connections, a synchronized pattern at low frequencies with alternation at high frequencies after removing only V0D connections, and an alternating pattern at low frequencies with hopping at high frequencies after removing only V0V connections. We used bifurcation theory and fast-slow decomposition methods to analyze network behavior in the above regimes and transitions between them. The model

  15. Mechanisms of left-right coordination in mammalian locomotor pattern generation circuits: a mathematical modeling view.

    PubMed

    Molkov, Yaroslav I; Bacak, Bartholomew J; Talpalar, Adolfo E; Rybak, Ilya A

    2015-05-01

    The locomotor gait in limbed animals is defined by the left-right leg coordination and locomotor speed. Coordination between left and right neural activities in the spinal cord controlling left and right legs is provided by commissural interneurons (CINs). Several CIN types have been genetically identified, including the excitatory V3 and excitatory and inhibitory V0 types. Recent studies demonstrated that genetic elimination of all V0 CINs caused switching from a normal left-right alternating activity to a left-right synchronized "hopping" pattern. Furthermore, ablation of only the inhibitory V0 CINs (V0D subtype) resulted in a lack of left-right alternation at low locomotor frequencies and retaining this alternation at high frequencies, whereas selective ablation of the excitatory V0 neurons (V0V subtype) maintained the left-right alternation at low frequencies and switched to a hopping pattern at high frequencies. To analyze these findings, we developed a simplified mathematical model of neural circuits consisting of four pacemaker neurons representing left and right, flexor and extensor rhythm-generating centers interacting via commissural pathways representing V3, V0D, and V0V CINs. The locomotor frequency was controlled by a parameter defining the excitation of neurons and commissural pathways mimicking the effects of N-methyl-D-aspartate on locomotor frequency in isolated rodent spinal cord preparations. The model demonstrated a typical left-right alternating pattern under control conditions, switching to a hopping activity at any frequency after removing both V0 connections, a synchronized pattern at low frequencies with alternation at high frequencies after removing only V0D connections, and an alternating pattern at low frequencies with hopping at high frequencies after removing only V0V connections. We used bifurcation theory and fast-slow decomposition methods to analyze network behavior in the above regimes and transitions between them. The model

  16. 42 CFR 84.97 - Test for carbon dioxide in inspired gas; open- and closed-circuit apparatus; maximum allowable...

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 42 Public Health 1 2010-10-01 2010-10-01 false Test for carbon dioxide in inspired gas; open- and... carbon dioxide in inspired gas; open- and closed-circuit apparatus; maximum allowable limits. (a) Open-circuit apparatus. (1) The concentration of carbon dioxide in inspired gas in open-circuit apparatus...

  17. 42 CFR 84.97 - Test for carbon dioxide in inspired gas; open- and closed-circuit apparatus; maximum allowable...

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... 42 Public Health 1 2013-10-01 2013-10-01 false Test for carbon dioxide in inspired gas; open- and... carbon dioxide in inspired gas; open- and closed-circuit apparatus; maximum allowable limits. (a) Open-circuit apparatus. (1) The concentration of carbon dioxide in inspired gas in open-circuit apparatus...

  18. 42 CFR 84.97 - Test for carbon dioxide in inspired gas; open- and closed-circuit apparatus; maximum allowable...

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 42 Public Health 1 2012-10-01 2012-10-01 false Test for carbon dioxide in inspired gas; open- and... carbon dioxide in inspired gas; open- and closed-circuit apparatus; maximum allowable limits. (a) Open-circuit apparatus. (1) The concentration of carbon dioxide in inspired gas in open-circuit apparatus...

  19. 42 CFR 84.97 - Test for carbon dioxide in inspired gas; open- and closed-circuit apparatus; maximum allowable...

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 42 Public Health 1 2011-10-01 2011-10-01 false Test for carbon dioxide in inspired gas; open- and... carbon dioxide in inspired gas; open- and closed-circuit apparatus; maximum allowable limits. (a) Open-circuit apparatus. (1) The concentration of carbon dioxide in inspired gas in open-circuit apparatus...

  20. 42 CFR 84.97 - Test for carbon dioxide in inspired gas; open- and closed-circuit apparatus; maximum allowable...

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 42 Public Health 1 2014-10-01 2014-10-01 false Test for carbon dioxide in inspired gas; open- and... carbon dioxide in inspired gas; open- and closed-circuit apparatus; maximum allowable limits. (a) Open-circuit apparatus. (1) The concentration of carbon dioxide in inspired gas in open-circuit apparatus...

  1. Description and test results of a variable speed, constant frequency generating system

    NASA Technical Reports Server (NTRS)

    Brady, F. J.

    1985-01-01

    The variable-speed, constant frequency generating system developed for the Mod-0 wind turbine is presented. This report describes the system as it existed at the conclusion of the project. The cycloconverter control circuit is described including the addition of field-oriented control. The laboratory test and actual wind turbine test results are included.

  2. Generating Test Templates via Automated Theorem Proving

    NASA Technical Reports Server (NTRS)

    Kancherla, Mani Prasad

    1997-01-01

    Testing can be used during the software development process to maintain fidelity between evolving specifications, program designs, and code implementations. We use a form of specification-based testing that employs the use of an automated theorem prover to generate test templates. A similar approach was developed using a model checker on state-intensive systems. This method applies to systems with functional rather than state-based behaviors. This approach allows for the use of incomplete specifications to aid in generation of tests for potential failure cases. We illustrate the technique on the cannonical triangle testing problem and discuss its use on analysis of a spacecraft scheduling system.

  3. Integration of MHD load models with circuit representations the Z generator.

    SciTech Connect

    Jennings, Christopher A.; Ampleford, David J.; Jones, Brent Manley; McBride, Ryan D.; Bailey, James E.; Jones, Michael C.; Gomez, Matthew Robert.; Cuneo, Michael Edward; Nakhleh, Charles; Stygar, William A.; Savage, Mark Edward; Wagoner, Timothy C.; Moore, James K.

    2013-03-01

    MHD models of imploding loads fielded on the Z accelerator are typically driven by reduced or simplified circuit representations of the generator. The performance of many of the imploding loads is critically dependent on the current and power delivered to them, so may be strongly influenced by the generators response to their implosion. Current losses diagnosed in the transmission lines approaching the load are further known to limit the energy delivery, while exhibiting some load dependence. Through comparing the convolute performance of a wide variety of short pulse Z loads we parameterize a convolute loss resistance applicable between different experiments. We incorporate this, and other current loss terms into a transmission line representation of the Z vacuum section. We then apply this model to study the current delivery to a wide variety of wire array and MagLif style liner loads.

  4. Mobile testing complex based on an explosive magnetic generator

    NASA Astrophysics Data System (ADS)

    Shurupov, A. V.; Kozlov, A. V.; Gusev, A. N.; Shurupova, N. P.; Zavalova, V. E.; Chulkov, A. N.; Bazelyan, E. M.

    2015-01-01

    A mobile testing complex prototype on the basis of an explosive magnetic generator (MTC EMG) is developed to simulate a lightning current pulse. The main element of this complex is a current pulse generator comprising a EMG with a pulse transformer for energy release into the load. The electric chain of the MTC EMG is theoretically analyzed taking into consideration energy losses in active resistances in the primary circuit of the transformer and the inductive-resistive nature of the load, which resulted in the minimization of energy losses in the primary circuit depending on the electric chain parameters. It was found that, if the energy losses are minimized, the efficiency of transferring the EMG energy into the load exceeds 50%. As a result of the field tests of the MTC EMG, its basic characteristics were determined and the waveforms of the current pulses and voltages in the load were obtained. It is shown that the results of the mathematical simulation of current pulses in the load are in good agreement with the experimental data.

  5. Thermal verification testing of commercial printed-circuit boards for spaceflight

    NASA Technical Reports Server (NTRS)

    Foster, William M., II

    1991-01-01

    A method is discussed developed to verify commercial printed-circuit boards for a shuttle orbital flight. The Space Acceleration Measurement System Project used this method first with great success. The test sequence is based on early fault detection, desire to test the final assembly, and integration with other verification testing. A component thermal screening test is performed first to force flaws in design, workmanship, parts, processes, and materials into observable failures. Then temperature definition tests are performed that consist of infrared scanning, thermal vacuum testing, and preliminary thermal operational testing. Only the engineering unit is used for temperature definition testing, but the preliminary thermal operational testing is performed on the flight unit after the temperature range has been defined. In the sequence of testing, vibration testing is performed next, but most vibration failures cannot be detected without subsequent temperature cycling. Finally, final assembly testing is performed to simulate the shuttle flight. An abbreviated thermal screening test is performed as a check after the vibration test, and then a complete thermal operational test is performed. The final assembly test finishes up with a burn-in of 100 hours of trouble-free operation. Verification is successful when all components and final assemblies have passed each test satisfactory. This method was very successful in verifying that commercial printed-circuit boards will survive in the shuttle environment.

  6. Assessing the SEU resistance of CMOS latches using alpha-particle sensitive test circuits

    NASA Technical Reports Server (NTRS)

    Buehler, M.; Blaes, B.; Nixon, R.

    1990-01-01

    The importance of Cosmic Rays on the performance of integrated circuits (IC's) in a space environment is evident in the upset rate of the Tracking and Data Relay Satellite (TDRS) launched in Apr. 1983. This satellite experiences a single-event-upset (SEU) per day which must be corrected from the ground. Such experience caused a redesign of the Galileo spacecraft with SEU resistant IC's. The solution to the SEU problem continues to be important as the complexity of spacecraft grows, the feature size of IC's decreases, and as space systems are designed with circuits fabricated at non-radiation hardened foundries. This paper describes an approach for verifying the susceptibility of CMOS latches to heavy-ion induced state changes. The approach utilizes alpha particles to induce the upsets in test circuits. These test circuits are standard cells that have offset voltages which sensitize the circuits to upsets. These results are then used to calculate the upsetability at operating voltages. In this study results are presented for the alpha particle upset of a six-transistor static random access memory (SRAM) cell. Then a methodology is described for the analysis of a standard-cell inverter latch.

  7. Testing of Diode-Clamping in an Inductive Pulsed Plasma Thruster Circuit

    NASA Technical Reports Server (NTRS)

    Toftul, Alexandra; Polzin, Kurt A.; Martin, Adam K.; Hudgins, Jerry L.

    2014-01-01

    Testing of a 5.5 kV silicon (Si) diode and 5.8 kV prototype silicon carbide (SiC) diode in an inductive pulsed plasma thruster (IPPT) circuit was performed to obtain a comparison of the resulting circuit recapture efficiency,eta(sub r), defined as the percentage of the initial charge energy remaining on the capacitor bank after the diode interrupts the current. The diode was placed in a pulsed circuit in series with a silicon controlled rectifier (SCR) switch, and the voltages across different components and current waveforms were collected over a range of capacitor charge voltages. Reverse recovery parameters, including turn-off time and peak reverse recovery current, were measured and capacitor voltage waveforms were used to determine the recapture efficiency for each case. The Si fast recovery diode in the circuit was shown to yield a recapture efficiency of up to 20% for the conditions tested, while the SiC diode further increased recapture efficiency to nearly 30%. The data presented show that fast recovery diodes operate on a timescale that permits them to clamp the discharge quickly after the first half cycle, supporting the idea that diode-clamping in IPPT circuit reduces energy dissipation that occurs after the first half cycle

  8. Self-Testing Quantum Random Number Generator

    NASA Astrophysics Data System (ADS)

    Lunghi, Tommaso; Brask, Jonatan Bohr; Lim, Charles Ci Wen; Lavigne, Quentin; Bowles, Joseph; Martin, Anthony; Zbinden, Hugo; Brunner, Nicolas

    2015-04-01

    The generation of random numbers is a task of paramount importance in modern science. A central problem for both classical and quantum randomness generation is to estimate the entropy of the data generated by a given device. Here we present a protocol for self-testing quantum random number generation, in which the user can monitor the entropy in real time. Based on a few general assumptions, our protocol guarantees continuous generation of high quality randomness, without the need for a detailed characterization of the devices. Using a fully optical setup, we implement our protocol and illustrate its self-testing capacity. Our work thus provides a practical approach to quantum randomness generation in a scenario of trusted but error-prone devices.

  9. Self-testing quantum random number generator.

    PubMed

    Lunghi, Tommaso; Brask, Jonatan Bohr; Lim, Charles Ci Wen; Lavigne, Quentin; Bowles, Joseph; Martin, Anthony; Zbinden, Hugo; Brunner, Nicolas

    2015-04-17

    The generation of random numbers is a task of paramount importance in modern science. A central problem for both classical and quantum randomness generation is to estimate the entropy of the data generated by a given device. Here we present a protocol for self-testing quantum random number generation, in which the user can monitor the entropy in real time. Based on a few general assumptions, our protocol guarantees continuous generation of high quality randomness, without the need for a detailed characterization of the devices. Using a fully optical setup, we implement our protocol and illustrate its self-testing capacity. Our work thus provides a practical approach to quantum randomness generation in a scenario of trusted but error-prone devices. PMID:25933297

  10. 42 CFR 84.95 - Service time test; open-circuit apparatus.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 42 Public Health 1 2014-10-01 2014-10-01 false Service time test; open-circuit apparatus. 84.95 Section 84.95 Public Health PUBLIC HEALTH SERVICE, DEPARTMENT OF HEALTH AND HUMAN SERVICES OCCUPATIONAL SAFETY AND HEALTH RESEARCH AND RELATED ACTIVITIES APPROVAL OF RESPIRATORY PROTECTIVE DEVICES Self-Contained Breathing Apparatus § 84.95 Service...

  11. 42 CFR 84.94 - Gas flow test; closed-circuit apparatus.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 42 Public Health 1 2010-10-01 2010-10-01 false Gas flow test; closed-circuit apparatus. 84.94 Section 84.94 Public Health PUBLIC HEALTH SERVICE, DEPARTMENT OF HEALTH AND HUMAN SERVICES OCCUPATIONAL SAFETY AND HEALTH RESEARCH AND RELATED ACTIVITIES APPROVAL OF RESPIRATORY PROTECTIVE DEVICES Self-Contained Breathing Apparatus § 84.94 Gas flow...

  12. New reconstruction method for x-ray testing of multilayer printed circuit board

    NASA Astrophysics Data System (ADS)

    Yang, Min; Wang, Gao; Liu, Yongzhan

    2010-05-01

    For multilayer printed circuit board (PCB) and large-scale integrated circuit (LIC) chips, nondestructive testing of the inner structure and welding defects is very important for circuit diagram reverse design and manufacturing quality control. The traditional nondestructive testing of this kind of plate-like object is digital radiography (DR), which can provide only images with overlapped information, so it is difficult to get a full and accurate circuit image of every layer and the position of the defects using the DR method. At the same time, traditional computed tomography scanning methods are also unable to resolve this problem. A new reconstruction method is proposed for the nondestructive testing of plate-like objects. With this method, x rays irradiate the surface of the reconstructed object at an oblique angle, and a series of projection images are obtained while the object is rotating. Then, through a relevant preprocessing method on the projections and a special reconstructing algorithm, cross sections of the scanning region are finally obtained slice by slice. The experimental results prove that this method satisfactorily addresses the challenges of nondestructive testing of plate-like objects such as PCB or LIC.

  13. The thermoelectric generator test program at JPL.

    NASA Technical Reports Server (NTRS)

    Stapfer, G.; Rouklove, P.

    1972-01-01

    Discussion of the test results and analysis performed on data obtained from eight thermoelectric generators exhibiting a total combined operating time of about 21 years. Three (3) SNAP-19 type generators are discussed. Generator SN-20, the engineering model of the units presently operating on the Nimbus S/C, has been in operation for over 4 years and has shown drastic degradation after losing the internal cover gas. Generator SN-21, with more than four years of operating time, is operated in an air environment. The performance of this generator appears predictable and stable. For the last 2 years of operation generator degradation has been negligible. Generator SN-31, which utilizes the TAGS material for the P thermoelectric leg, is similar in design to the units to be used on the Pioneer S/C and has operated for over two years in an all-argon atmosphere.

  14. Using Test Generating Software for Assessment

    NASA Astrophysics Data System (ADS)

    Singh Aurora, Tarlok

    2007-04-01

    Assessment is an important part of teaching and learning. Designing suitable tests and quizzes for assessment is a time consuming task. With faculty's much commitment at work, sometimes it is not easy to find enough time to design a good test before the test day. Searching for and modifying older tests can take considerable amount of time. There is a need to develop a customized test bank that one could use to generate a quiz or test quickly before class time or before a test. A number of commercial software is available for e-learning that has this capability. Some of these are - Test Generator, Examview, Test Pro Developer etc. Application of Examview software in developing a test bank for physics will be presented. A physics test bank, with applications in other disciplines, can be gradually built over time and used to create a test or quiz quickly. Multiple scrambled versions of a single test (and answer sheets) can be created to discourage cheating in a large class setting. The presentation will show how to build a test bank.

  15. Development of a stereo-symmetrical nanosecond pulsed power generator composed of modularized avalanche transistor Marx circuits

    NASA Astrophysics Data System (ADS)

    Li, Jiang-Tao; Zhong, Xu; Cao, Hui; Zhao, Zheng; Xue, Jing; Li, Tao; Li, Zheng; Wang, Ya-Nan

    2015-09-01

    Avalanche transistors have been widely studied and used in nanosecond high voltage pulse generations. However, output power improvement is always limited by the low thermal capacities of avalanche transistors, especially under high repetitive working frequency. Parallel stacked transistors can effectively improve the output current but the controlling of trigger and output synchronism has always been a hard and complex work. In this paper, a novel stereo-symmetrical nanosecond pulsed power generator with high reliability was developed. By analyzing and testing the special performances of the combined Marx circuits, numbers of meaningful conclusions on the pulse amplitude, pulse back edge, and output impedance were drawn. The combining synchronism of the generator was confirmed excellent and lower conducting current through the transistors was realized. Experimental results showed that, on a 50 Ω resistive load, pulses with 1.5-5.2 kV amplitude and 5.3-14.0 ns width could be flexibly generated by adjusting the number of combined modules, the supply voltage, and the module type.

  16. Development of a stereo-symmetrical nanosecond pulsed power generator composed of modularized avalanche transistor Marx circuits.

    PubMed

    Li, Jiang-Tao; Zhong, Xu; Cao, Hui; Zhao, Zheng; Xue, Jing; Li, Tao; Li, Zheng; Wang, Ya-Nan

    2015-09-01

    Avalanche transistors have been widely studied and used in nanosecond high voltage pulse generations. However, output power improvement is always limited by the low thermal capacities of avalanche transistors, especially under high repetitive working frequency. Parallel stacked transistors can effectively improve the output current but the controlling of trigger and output synchronism has always been a hard and complex work. In this paper, a novel stereo-symmetrical nanosecond pulsed power generator with high reliability was developed. By analyzing and testing the special performances of the combined Marx circuits, numbers of meaningful conclusions on the pulse amplitude, pulse back edge, and output impedance were drawn. The combining synchronism of the generator was confirmed excellent and lower conducting current through the transistors was realized. Experimental results showed that, on a 50 Ω resistive load, pulses with 1.5-5.2 kV amplitude and 5.3-14.0 ns width could be flexibly generated by adjusting the number of combined modules, the supply voltage, and the module type. PMID:26429438

  17. Molten-Caustic-Leaching (Gravimelt) System Integration Project, Phase 2. Topical report for test circuit operation

    SciTech Connect

    Not Available

    1993-02-01

    The objective of the task (Task 6) covered in this document was to operate the refurbished/modified test circuit of the Gravimeh Process in a continuous integrated manner to obtain the engineering and operational data necessary to assess the technical performance and reliability of the circuit. This data is critical to the development of this technology as a feasible means of producing premium clean burning fuels that meet New Source Performance Standards (NSPS). Significant refurbishments and design modifications had been made to the facility (in particular to the vacuum filtration and evaporation units) during Tasks 1 and 2, followed by off-line testing (Task 3). Two weeks of continuous around-the-clock operation of the refurbished/modified MCL test circuit were performed. During the second week of testing, all sections of the plant were operated in an integrated fashion for an extended period of time, including a substantial number of hours of on-stream time for the vacuum filters and the caustic evaporation unit. A new process configuration was tested in which centrate from the acid wash train (without acid addition) was used as the water makeup for the water wash train, thus-eliminating the one remaining process waste water stream. A 9-inch centrifuge was tested at various solids loadings and at flow rates up to 400 lbs/hr of coal feed to obtain a twenty-fold scaleup factor over the MCL integrated test facility centrifuge performance data.

  18. A miniature microcontroller curve tracing circuit for space flight testing transistors.

    PubMed

    Prokop, N; Greer, L; Krasowski, M; Flatico, J; Spina, D

    2015-02-01

    This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results. PMID:25725870

  19. MYSID TWO-GENERATION TEST GUIDELINE

    EPA Science Inventory

    McKenney, Charles L., Jr. In press. Mysid Two-Generation Test Guideline. OECD Expert Group on Invertebrate Testing for Endocrine Disruptors, Organisation for Economic Co-operation and Development, Paris, France. 17 p. (ERL,GB 1215).

    This guideline describes a two-generati...

  20. Testing and Troubleshooting Automatically Generated Source Code

    NASA Technical Reports Server (NTRS)

    Henry, Joel

    1998-01-01

    Tools allowing engineers to model the real-time behavior of systems that control many types of NASA systems have become widespread. These tools automatically generate source code that is compiled, linked, then downloaded into computers controlling everything from wind tunnels to space flight systems. These tools save hundreds of hours of software development time and allow engineers with thorough application area knowledge but little software development experience to generate software to control the systems they use daily. These systems are verified and validated by simulating the real-time models, and by other techniques that focus on the model or the hardware. The automatically generated source code is typically not subjected to rigorous testing using conventional software testing techniques. Given the criticality and safety issues surrounding these systems, the application of conventional and new software testing and troubleshooting techniques to the automatically generated will improve the reliability of the resulting systems.

  1. Alcohol LOX Steam Generator Test Experience

    NASA Astrophysics Data System (ADS)

    Schaefer, K.; Dommers, M.

    2004-10-01

    At the DLR test centre in Lampoldshausen there is a long experience in the development of rocket steam generators as a main subsystem for the altitude simulation. The rocket steam generators make it possible to supply the required quantities of steam at short notice with reduced investment and operating costs. The rocket steam generators are based on the combustion of liquid oxygen (LOX) and ethyl alcohol (ALC). The paper deals with the experience of the development of the steam generators and the operation at the altitude simulation P1.0 for satellite propulsion and P4.2 for altitude simulation of AESTUS upper stage engine.

  2. Recent Updates to the Fission Surface Power Primary Test Circuit (FSP-PTC)

    NASA Technical Reports Server (NTRS)

    Garber, Anne E.

    2008-01-01

    An actively pumped alkali metal flow circuit, designed and fabricated at the NASA Marshall Space Flight Center, underwent a range of tests at MSFC in early 2007. During this period, system transient responses and the performance of the liquid metal pump were evaluated. In May of 2007, the circuit was drained and cleaned to prepare for multiple modifications: the addition of larger upper and lower reservoirs, the installation of an annular linear induction pump (ALIP), and the inclusion of a closeable orifice in the test section. Modifications are now complete and testing has resumed. Performance of the ALIP, provided by Idaho National Laboratory (1NL), is the subject of the first round of experimentation. This presentation details the physical changes made to the FSP-PTC and the current test program.

  3. Modifications and Modeling of the Fission Surface Power Primary Test Circuit (FSP-PTC)

    NASA Technical Reports Server (NTRS)

    Garber, Anne E.

    2008-01-01

    An actively pumped alkali metal flow circuit, designed and fabricated at the NASA Marshall Space Flight Center, underwent a range of tests at MSFC in early 2007. During this period, system transient responses and the performance of the liquid metal pump were evaluated. In May of2007, the circuit was drained and cleaned to prepare for multiple modifications: the addition of larger upper and lower reservoirs, the installation of an annular linear induction pump (ALIP), and the inclusion of a closeable orifice in the test section. Performance of the ALIP, provided by Idaho National Laboratory (INL), will be evaluated when testing resumes. Data from the first round of testing has been used to refine the working system model, developed using the Generalized Fluid System Simulation Program (GFSSP). This paper covers the modifications of the FSP-PTC and the updated GFSSP system model.

  4. Formal methods for test case generation

    NASA Technical Reports Server (NTRS)

    Rushby, John (Inventor); De Moura, Leonardo Mendonga (Inventor); Hamon, Gregoire (Inventor)

    2011-01-01

    The invention relates to the use of model checkers to generate efficient test sets for hardware and software systems. The method provides for extending existing tests to reach new coverage targets; searching *to* some or all of the uncovered targets in parallel; searching in parallel *from* some or all of the states reached in previous tests; and slicing the model relative to the current set of coverage targets. The invention provides efficient test case generation and test set formation. Deep regions of the state space can be reached within allotted time and memory. The approach has been applied to use of the model checkers of SRI's SAL system and to model-based designs developed in Stateflow. Stateflow models achieving complete state and transition coverage in a single test case are reported.

  5. Controllable high-fidelity quantum state transfer and entanglement generation in circuit QED

    PubMed Central

    Xu, Peng; Yang, Xu-Chen; Mei, Feng; Xue, Zheng-Yuan

    2016-01-01

    We propose a scheme to realize controllable quantum state transfer and entanglement generation among transmon qubits in the typical circuit QED setup based on adiabatic passage. Through designing the time-dependent driven pulses applied on the transmon qubits, we find that fast quantum sate transfer can be achieved between arbitrary two qubits and quantum entanglement among the qubits also can also be engineered. Furthermore, we numerically analyzed the influence of the decoherence on our scheme with the current experimental accessible systematical parameters. The result shows that our scheme is very robust against both the cavity decay and qubit relaxation, the fidelities of the state transfer and entanglement preparation process could be very high. In addition, our scheme is also shown to be insensitive to the inhomogeneous of qubit-resonator coupling strengths. PMID:26804326

  6. Accurate Cold-Test Model of Helical TWT Slow-Wave Circuits

    NASA Technical Reports Server (NTRS)

    Kory, Carol L.; Dayton, James A., Jr.

    1997-01-01

    Recently, a method has been established to accurately calculate cold-test data for helical slow-wave structures using the three-dimensional electromagnetic computer code, MAFIA. Cold-test parameters have been calculated for several helical traveling-wave tube (TWT) slow-wave circuits possessing various support rod configurations, and results are presented here showing excellent agreement with experiment. The helical models include tape thickness, dielectric support shapes and material properties consistent with the actual circuits. The cold-test data from this helical model can be used as input into large-signal helical TWT interaction codes making it possible, for the first time, to design a complete TWT via computer simulation.

  7. Accurate Cold-Test Model of Helical TWT Slow-Wave Circuits

    NASA Technical Reports Server (NTRS)

    Kory, Carol L.; Dayton, J. A., Jr.

    1998-01-01

    Recently, a method has been established to accurately calculate cold-test data for helical slow-wave structures using the three-dimensional (3-D) electromagnetic computer code, MAFIA. Cold-test parameters have been calculated for several helical traveling-wave tube (TWT) slow-wave circuits possessing various support rod configurations, and results are presented here showing excellent agreement with experiment. The helical models include tape thickness, dielectric support shapes and material properties consistent with the actual circuits. The cold-test data from this helical model can be used as input into large-signal helical TWT interaction codes making it possible, for the first time, to design a complete TWT via computer simulation.

  8. Accurate Cold-Test Model of Helical TWT Slow-Wave Circuits

    NASA Technical Reports Server (NTRS)

    Kory, Carol L.; Dayton, James A., Jr.

    1998-01-01

    Recently, a method has been established to accurately calculate cold-test data for helical slow-wave structures using the three-dimensional (3-D) electromagnetic computer code, MAxwell's equations by the Finite Integration Algorithm (MAFIA). Cold-test parameters have been calculated for several helical traveLing-wave tube (TWT) slow-wave circuits possessing various support rod configurations, and results are presented here showing excellent agreement with experiment. The helical models include tape thickness, dielectric support shapes and material properties consistent with the actual circuits. The cold-test data from this helical model can be used as input into large-signal helical TWT interaction codes making It possible, for the first time, to design complete TWT via computer simulation.

  9. Design of parity generator and checker circuit using electro-optic effect of Mach-Zehnder interferometers

    NASA Astrophysics Data System (ADS)

    Kumar, Santosh; Chanderkanta; Amphawan, Angela

    2016-04-01

    Parity is an extra bit which is used to add in digital information to detect error at the receiver end. It can be even and odd parity. In case of even parity, the number of one's will be even included the parity and reverse in the case of odd parity. The circuit which is used to generate the parity at the transmitter side, called the parity generator and the circuit which is used to detect the parity at receiver side is called as parity checker. In this paper, an even and odd parity generator and checker circuits are designed using electro-optic effect inside lithium niobate based Mach-Zehnder Interferometers (MZIs). The MZIs structures collectively show powerful capability in switching an input optical signal to a desired output port from a collection of output ports. The paper constitutes a mathematical description of the proposed device and thereafter simulation using MATLAB. The study is verified using beam propagation method (BPM).

  10. Test structures for propagation delay measurements on high-speed integrated circuits

    NASA Technical Reports Server (NTRS)

    Long, S. I.

    1984-01-01

    The accuracy of high-speed wafer-level measurements on digital IC's is limited by the probe interface. This limitation strongly encourages the use of built-in on-chip test hardware to reduce the number of critical off-chip high-speed interfaces. A novel synchronous propagation delay test structure is described which will provide accurate parametric data under typical automatic test conditions. Built-in test features added to complex combinational circuits are shown which are useful for delay measurement and which reduce the total number of high-speed I/O connections while still providing acceptable fault coverage in many cases.

  11. Downhole steam generator subject of Sandia tests

    SciTech Connect

    Not Available

    1981-05-01

    The first field test of a down-hole steam generator developed to inject hot steam directly into deeply buried heavy oil reservoirs began in mid-April near Long Beach, CA. The 23-ft-long, 6-in.-diameter generator, developed by Sandia National Laboratories, will produce up to 800 cu ft of 500 F steam a minute (1.2 MW thermal) at the bottom of a 2500-ft well. Goals of the test are to demonstrate the feasibility of operating the generator at realistic depths and to determine its overall performance and environmental impact. Development of the generator is part of the US Department of Energy's Project Deep Steam to identify techniques for recovering heavy oil from deeply buried (greater than 2500 ft) reservoirs.

  12. ADDER CIRCUIT

    DOEpatents

    Jacobsohn, D.H.; Merrill, L.C.

    1959-01-20

    An improved parallel addition unit is described which is especially adapted for use in electronic digital computers and characterized by propagation of the carry signal through each of a plurality of denominationally ordered stages within a minimum time interval. In its broadest aspects, the invention incorporates a fast multistage parallel digital adder including a plurality of adder circuits, carry-propagation circuit means in all but the most significant digit stage, means for conditioning each carry-propagation circuit during the time period in which information is placed into the adder circuits, and means coupling carry-generation portions of thc adder circuit to the carry propagating means.

  13. Surface Degradation of Ag/W Circuit Breaker Contacts During Standardized UL Testing

    NASA Astrophysics Data System (ADS)

    Yu, Haibo; Sun, Yu; Kesim, M. Tumerkan; Harmon, Jason; Potter, Jonathan; Alpay, S. Pamir; Aindow, Mark

    2015-09-01

    The near-surface microstructure of Ag/W contacts from 120 V, 30 A commercial circuit breakers in the as-manufactured condition and after standardized UL overload/temperature-rise, endurance, and short-circuit testing have been investigated using a combination of x-ray diffraction, scanning electron microscopy, energy-dispersive x-ray spectroscopy, focused ion beam milling, and transmission electron microscopy. The as-manufactured contacts comprised three constituents: sintered Ag/W composite particles with fine-grained Ag and coarse-grained W, coarse-grained pockets of Ag infiltrate, and a nano-crystalline surface Ag layer. There are also WO3 and Ag2O phases at the surface. After UL overload/temperature-rise testing, there is Ag loss giving a porous W-rich layer at the contact surface. In addition to binary oxides, we observe the formation of Ag2WO4. After UL endurance testing, material is swept across the surface by the breaker action giving a W-rich eroded porous surface on one side and a build-up of mixed oxides on the other. After UL short-circuit testing, a W crust forms due to melting and re-solidification of W and vaporization of Ag, and mid-plane cracks form due to the severe thermal gradients. There is a strong correlation between the observed microstructural features and the contact resistance measurements obtained from these samples.

  14. Torque calculation of the asynchronous motor in short-circuit test

    SciTech Connect

    Demski, W.; Szymanski, G.

    1998-09-01

    The paper presents the application of the calculation method of electromagnetic torque for asynchronous motor in short-circuit test. The {rvec A}, {rvec A}-V formulation with a complex notation for time harmonic systems in the finite difference method is used to solve the nonlinear three dimensional problem. The volume Maxwell stress tensor is used for force and torque calculation. The numerical results are compared with measurement.

  15. Computer-Based Arithmetic Test Generation

    ERIC Educational Resources Information Center

    Trocchi, Robert F.

    1973-01-01

    The computer can be a welcome partner in the instructional process, but only if there is man-machine interaction. Man should not compromise system design because of available hardware; the computer must fit the system design for the result to represent an acceptable solution to instructional technology. The Arithmetic Test Generator system fits…

  16. Next Generation Drivetrain Development and Test Program

    SciTech Connect

    Keller, Jonathan; Erdman, Bill; Blodgett, Doug; Halse, Chris; Grider, Dave

    2015-11-03

    This presentation was given at the Wind Energy IQ conference in Bremen, Germany, November 30 through December 2, 2105. It focused on the next-generation drivetrain architecture and drivetrain technology development and testing (including gearbox and inverter software and medium-voltage inverter modules.

  17. Temperature distortion generator for turboshaft engine testing

    NASA Technical Reports Server (NTRS)

    Klann, G. A.; Barth, R. L.; Biesiadny, T. J.

    1984-01-01

    The procedures and unique hardware used to conduct an experimental investigation into the response of a small-turboshaft-engine compression system to various hot gas ingestion patterns are presented. The temperature distortion generator described herein uses gaseous hydrogen to create both steady-state and time-variant, or transient, temperature distortion at the engine inlet. The range of transient temperature ramps produced by the distortion generator during the engine tests was from less than 111 deg K/sec (200 deg R/sec) to above 611 deg K/sec (1100 deg R/sec); instantaneous temperatures to 422 deg K (760 deg R) above ambient were generated. The distortion generator was used to document the maximum inlet temperatures and temperature rise rates that the compression system could tolerate before the onset of stall for various circumferential distortions as well as the compressor system response during stall.

  18. Dual stator winding variable speed asynchronous generator: magnetic equivalent circuit with saturation, FEM analysis and experiments

    NASA Astrophysics Data System (ADS)

    Tutelea, L. N.; Muntean, N.; Deaconu, S. I.; Cunţan, C. D.

    2016-02-01

    The authors carried out a theoretical and experimental study of dual stator winding squirrel cage asynchronous generator (DSWA) behaviour in the presence of saturation regime (non-sinusoidal) due to the variable speed operation. The main aims are the determination of the relations of calculating the equivalent parameters of the machine windings, FEM validation of parameters and characteristics with free FEMM 4.2 computing software and the practice experimental tests for verifying them. Issue is limited to three phase range of double stator winding cage-asynchronous generator of small sized powers, the most currently used in the small adjustable speed wind or hydro power plants. The tests were carried out using three-phase asynchronous generator having rated power of 6 [kVA].

  19. Super NiCd Open-Circuit Storage and Low Earth Orbit (LEO) Life Test Evaluation

    NASA Technical Reports Server (NTRS)

    Baer, Jean Marie; Hwang, Warren C.; Ang, Valerie J.; Hayden, Jeff; Rao, Gopalakrishna; Day, John H. (Technical Monitor)

    2002-01-01

    This presentation discusses Air Force tests performed on super NiCd cells to measure their performance under conditions simulating Low Earth Orbit (LEO) conditions. Super NiCd cells offer potential advantages over existing NiCd cell designs including advanced cell design with improved separator material and electrode making processes, but handling and storage requires active charging. These tests conclude that the super NiCd cells support generic Air Force qualifications for conventional LEO missions (up to five years duration) and that handling and storage may not actually require active charging as previously assumed. Topics covered include: Test Plan, Initial Characterization Tests, Open-Circuit Storage Tests, and post storage capacities.

  20. Infrared Thermography as Applied to Thermal Testing of Power Systems Circuit Boards.

    NASA Astrophysics Data System (ADS)

    Miles, Jonathan James

    All operational electronic equipment dissipates some amount of energy in the form of infrared radiation. Faulty electronic components on a printed circuit board can be categorized as hard (functional) or soft (latent functional). Hard faults are those which are detected during a conventional manufacturing electronic test process. Soft failures, in contrast, are those which are undetectable through conventional testing, but which manifest themselves after a product has been placed into service. Such field defective modules ultimately result in operational failure and subsequently enter a manufacturer's costly repair process. While thermal imaging systems are being used increasingly in the electronic equipment industry as a product-testing tool, applications have primarily been limited to product design or repair processes, with minimal use in a volume manufacturing environment. Use of thermal imaging systems in such an environment has mostly been limited to low-volume products or random screening of high-volume products. Thermal measurements taken in a manufacturing environment are often taken manually, thus defeating their capability of rapid data acquisition and constraining their full potential in a high-volume manufacturing process. Integration of a thermal measurement system with automated testing equipment is essential for optimal use of expensive infrared measurement tools in a high-volume manufacturing environment. However, such a marriage presents problems with respect to both existing manufacturing test processes and infrared measurement techniques. Methods are presented in this dissertation to test automatically for latent faults, those which elude detection during conventional electronic testing, on printed circuit boards. These methods are intended for implementation in a volume manufacturing environment and involve the application of infrared imaging tools. Successful incorporation of infrared testing into existing test processes requires that: PASS

  1. Generation of copper rich metallic phases from waste printed circuit boards

    SciTech Connect

    Cayumil, R.; Khanna, R.; Ikram-Ul-Haq, M.; Rajarao, R.; Hill, A.; Sahajwalla, V.

    2014-10-15

    Highlights: • Recycling and material recovery from waste printed circuit boards is very complex. • Thermoset polymers, ceramics and metals are present simultaneously in waste PCBs. • Heat treatment of PCBs was carried out at 1150 °C under inert conditions. • Various metallic phases could be segregated out as copper based metallic droplets. • Carbon and ceramics residues can be further recycled in a range of applications. - Abstract: The rapid consumption and obsolescence of electronics have resulted in e-waste being one of the fastest growing waste streams worldwide. Printed circuit boards (PCBs) are among the most complex e-waste, containing significant quantities of hazardous and toxic materials leading to high levels of pollution if landfilled or processed inappropriately. However, PCBs are also an important resource of metals including copper, tin, lead and precious metals; their recycling is appealing especially as the concentration of these metals in PCBs is considerably higher than in their ores. This article is focused on a novel approach to recover copper rich phases from waste PCBs. Crushed PCBs were heat treated at 1150 °C under argon gas flowing at 1 L/min into a horizontal tube furnace. Samples were placed into an alumina crucible and positioned in the cold zone of the furnace for 5 min to avoid thermal shock, and then pushed into the hot zone, with specimens exposed to high temperatures for 10 and 20 min. After treatment, residues were pulled back to the cold zone and kept there for 5 min to avoid thermal cracking and re-oxidation. This process resulted in the generation of a metallic phase in the form of droplets and a carbonaceous residue. The metallic phase was formed of copper-rich red droplets and tin-rich white droplets along with the presence of several precious metals. The carbonaceous residue was found to consist of slag and ∼30% carbon. The process conditions led to the segregation of hazardous lead and tin clusters in the

  2. A computer test bench for checking and adjusting the automatic regulators of generator excitation systems

    SciTech Connect

    Dovganyuk, I. Ya.; Labunets, I. A.; Plotnikova, T. V.; Sokur, P. V.

    2008-05-15

    A computer test bench for testing and debugging natural samples of the automatic excitation regulation systems of generators, the protection units and the power part of the excitation system is described. The bench includes a personal computer with specialized input-output circuit boards for analog and digital signals, and enables the time and cost involved in developing and checking control systems to be reduced considerably. The program employed operates in real time and enables the automatic excitation regulators of synchronous generators and generators with longitudinal-transverse excitation in a specific power system to be adjusted.

  3. Design and test of a capacitance detection circuit based on a transimpedance amplifier

    NASA Astrophysics Data System (ADS)

    Linfeng, Mu; Wendong, Zhang; Changde, He; Rui, Zhang; Jinlong, Song; Chenyang, Xue

    2015-07-01

    This paper presents a transimpedance amplifier (TIA) capacitance detection circuit aimed at detecting micro-capacitance, which is caused by ultrasonic stimulation applied to the capacitive micro-machined ultrasonic transducer (CMUT). In the capacitance interface, a TIA is adopted to amplify the received signal with a center frequency of 400 kHz, and finally detect ultrasound pressure. The circuit has a strong anti-stray property and this paper also studies the calculation of compensation capacity in detail. To ensure high resolution, noise analysis is conducted. After optimization, the detected minimum ultrasound pressure is 2.1 Pa, which is two orders of magnitude higher than the former. The test results showed that the circuit was sensitive to changes in ultrasound pressure and the distance between the CMUT and stumbling block, which also successfully demonstrates the functionality of the developed TIA of the analog-front-end receiver. Project supported by the National Natural Science Foundation of China (No. 61127008) and the Subsidized Program of the National High Technology Research and Development Program of China (No. 2011AA040404).

  4. Development and Analysis of Cold Trap for Use in Fission Surface Power-Primary Test Circuit

    NASA Technical Reports Server (NTRS)

    Wolfe, T. M.; Dervan, C. A.; Pearson, J. B.; Godfroy, T. J.

    2012-01-01

    The design and analysis of a cold trap proposed for use in the purification of circulated eutectic sodium potassium (NaK-78) loops is presented. The cold trap is designed to be incorporated into the Fission Surface Power-Primary Test Circuit (FSP-PTC), which incorporates a pumped NaK loop to simulate in-space nuclear reactor-based technology using non-nuclear test methodology as developed by the Early Flight Fission-Test Facility. The FSP-PTC provides a test circuit for the development of fission surface power technology. This system operates at temperatures that would be similar to those found in a reactor (500-800 K). By dropping the operating temperature of a specified percentage of NaK flow through a bypass containing a forced circulation cold trap, the NaK purity level can be increased by precipitating oxides from the NaK and capturing them within the cold trap. This would prevent recirculation of these oxides back through the system, which may help prevent corrosion.

  5. Design and test of a robust multi-channel programmable sensor interface circuit for use in extreme environments

    SciTech Connect

    Van Cutsem, K.; De Cock, W.; Tavernier, S.

    2011-07-01

    This article describes the design of a sensor interface circuit for the amplification of voltages and currents. The created PCB was tested at high temperatures and under gamma irradiation. Two different operational amplifiers were compared. (authors)

  6. Thermal hydraulic performance testing of printed circuit heat exchangers in a high-temperature helium test facility

    SciTech Connect

    Sai K. Mylavarapu; Xiaodong Sun; Richard E. Glosup; Richard N. Christensen; Michael W. Patterson

    2014-04-01

    In high-temperature gas-cooled reactors, such as a very high temperature reactor (VHTR), an intermediate heat exchanger (IHX) is required to efficiently transfer the core thermal output to a secondary fluid for electricity generation with an indirect power cycle and/or process heat applications. Currently, there is no proven high-temperature (750–800 °C or higher) compact heat exchanger technology for high-temperature reactor design concepts. In this study, printed circuit heat exchanger (PCHE), a potential IHX concept for high-temperature applications, has been investigated for their heat transfer and pressure drop characteristics under high operating temperatures and pressures. Two PCHEs, each having 10 hot and 10 cold plates with 12 channels (semicircular cross-section) in each plate are fabricated using Alloy 617 plates and tested for their performance in a high-temperature helium test facility (HTHF). The PCHE inlet temperature and pressure were varied from 85 to 390 °C/1.0–2.7 MPa for the cold side and 208–790 °C/1.0–2.7 MPa for the hot side, respectively, while the mass flow rate of helium was varied from 15 to 49 kg/h. This range of mass flow rates corresponds to PCHE channel Reynolds numbers of 950 to 4100 for the cold side and 900 to 3900 for the hot side (corresponding to the laminar and laminar-to-turbulent transition flow regimes). The obtained experimental data have been analyzed for the pressure drop and heat transfer characteristics of the heat transfer surface of the PCHEs and compared with the available models and correlations in the literature. In addition, a numerical treatment of hydrodynamically developing and hydrodynamically fully-developed laminar flow through a semicircular duct is presented. Relations developed for determining the hydrodynamic entrance length in a semicircular duct and the friction factor (or pressure drop) in the hydrodynamic entry length region for laminar flow through a semicircular duct are given. Various

  7. Custom pulse generator for RPC testing

    NASA Astrophysics Data System (ADS)

    Gil, A.; Castro, E.; Díaz, J.; Fonte, P.; Garzón, J. A.; Montes, N.; Zapata, M.

    2009-05-01

    We present a pulse generator able to generate pulses statistically similar to the ones produced by RPC cells. The device generates up to four arrays of fast and narrow random-like pulses. Polarity, maximum amplitudes, widths and pulse rate in each channel may be modified independently in order to simulate different RPC setups and environments. This portable and cost-effective pulse generator is a versatile instrument for testing FE-Electronics and different real detector features related with the signal propagation inside the detector. It has been developed in the framework of the ESTRELA project of the HADES experiment at GSI. ESTRELA (Electrically Shielded Timing RPC Ensemble for Low Angles) is part of the upgrade of the HADES experiment at GSI with the aim of constructing an RPC-based time-of-flight wall that will cover around 8 m 2 in order to cope with the high particle multiplicities expected for heavy nuclei collision systems such as Au+Au.

  8. Spike timing-dependent serotonergic neuromodulation of synaptic strength intrinsic to a central pattern generator circuit.

    PubMed

    Sakurai, Akira; Katz, Paul S

    2003-11-26

    Neuromodulation is often thought to have a static, gain-setting function in neural circuits. Here we report a counter example: the neuromodulatory effect of a serotonergic neuron is dependent on the interval between its spikes and those of the neuron being modulated. The serotonergic dorsal swim interneurons (DSIs) are members of the escape swim central pattern generator (CPG) in the mollusk Tritonia diomedea. DSI spike trains heterosynaptically enhanced synaptic potentials evoked by another CPG neuron, ventral swim interneuron B (VSI-B), when VSI-B action potentials occurred within 10 sec of a DSI spike train; however, if VSI-B was stimulated 20-120 sec after DSI, then the amplitude of VSI-B synaptic potentials decreased. Consistent with this, VSI-B-evoked synaptic currents exhibited a temporally biphasic and bidirectional change in amplitude after DSI stimulation. Both the DSI-evoked enhancement and decrement were occluded by serotonin and blocked by the serotonin receptor antagonist methysergide, suggesting that both phases are mediated by serotonin. In most preparations, however, bath-applied serotonin caused only a sustained enhancement of VSI-B synaptic strength. The heterosynaptic modulation interacted with short-term homosynaptic plasticity: DSI-evoked depression was offset by VSI-B homosynaptic facilitation. This caused a complicated temporal pattern of neuromodulation when DSI and VSI-B were stimulated to fire in alternating bursts to mimic the natural motor pattern: DSI strongly enhanced summated VSI-B synaptic potentials and suppressed single synaptic potentials after the cessation of the artificial motor pattern. Thus, spike timing-dependent serotonergic neuromodulatory actions can impart temporal information that may be relevant to the operation of the CPG. PMID:14645466

  9. BETA: Behavioral testability analyzer and its application to high-level test generation and synthesis for testability. Ph.D. Thesis

    NASA Technical Reports Server (NTRS)

    Chen, Chung-Hsing

    1992-01-01

    In this thesis, a behavioral-level testability analysis approach is presented. This approach is based on analyzing the circuit behavioral description (similar to a C program) to estimate its testability by identifying controllable and observable circuit nodes. This information can be used by a test generator to gain better access to internal circuit nodes and to reduce its search space. The results of the testability analyzer can also be used to select test points or partial scan flip-flops in the early design phase. Based on selection criteria, a novel Synthesis for Testability approach call Test Statement Insertion (TSI) is proposed, which modifies the circuit behavioral description directly. Test Statement Insertion can also be used to modify circuit structural description to improve its testability. As a result, Synthesis for Testability methodology can be combined with an existing behavioral synthesis tool to produce more testable circuits.

  10. 49 CFR 229.114 - Steam generator inspections and tests.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... 49 Transportation 4 2013-10-01 2013-10-01 false Steam generator inspections and tests. 229.114... Generators § 229.114 Steam generator inspections and tests. (a) Periodic steam generator inspection. Except as provided in § 229.33, each steam generator shall be inspected and tested in accordance...

  11. 49 CFR 229.114 - Steam generator inspections and tests.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 49 Transportation 4 2014-10-01 2014-10-01 false Steam generator inspections and tests. 229.114... Generators § 229.114 Steam generator inspections and tests. (a) Periodic steam generator inspection. Except as provided in § 229.33, each steam generator shall be inspected and tested in accordance...

  12. 49 CFR 229.114 - Steam generator inspections and tests.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 49 Transportation 4 2012-10-01 2012-10-01 false Steam generator inspections and tests. 229.114... Generators § 229.114 Steam generator inspections and tests. (a) Periodic steam generator inspection. Except as provided in § 229.33, each steam generator shall be inspected and tested in accordance...

  13. Configurable test bed design for nanosats to qualify commercial and customized integrated circuits

    NASA Astrophysics Data System (ADS)

    Guareschi, W.; Azambuja, J.; Kastensmidt, F.; Reis, R.; Durao, O.; Schuch, N.; Dessbesel, G.

    The use of small satellites has increased substantially in recent years due to the reduced cost of their development and launch, as well to the flexibility offered by commercial components. The test bed is a platform that allows components to be evaluated and tested in space. It is a flexible platform, which can be adjusted to a wide quantity of components and interfaces. This work proposes the design and implementation of a test bed suitable for test and evaluation of commercial circuits used in nanosatellites. The development of such a platform allows developers to reduce the efforts in the integration of components and therefore speed up the overall system development time. The proposed test bed is a configurable platform implemented using a Field Programmable Gate Array (FPGA) that controls the communication protocols and connections to the devices under test. The Flash-based ProASIC3E FPGA from Microsemi is used as a control system. This adaptive system enables the control of new payloads and softcores for test and validation in space. Thus, the integration can be easily performed through configuration parameters. It is intended for modularity. Each component connected to the test bed can have a specific interface programmed using a hardware description language (HDL). The data of each component is stored in embedded memories. Each component has its own memory space. The size of the allocated memory can be also configured. The data transfer priority can be set and packaging can be added to the logic, when needed. Communication with peripheral devices and with the Onboard Computer (OBC) is done through the pre-implemented protocols, such as I2C (Inter-Integrated Circuit), SPI (Serial Peripheral Interface) and external memory control. In loco primary tests demonstrated the control system's functionality. The commercial ProASIC3E FPGA family is not space-flight qualified, but tests have been made under Total Ionizing Dose (TID) showing its robustness up to 25 kr

  14. Wein bridge oscillator circuit

    NASA Technical Reports Server (NTRS)

    Lipoma, P. C.

    1971-01-01

    Circuit with minimum number of components provides stable outputs of 2 to 8 volts at frequencies of .001 to 100 kHz. Oscillator exhibits low power consumption, portability, simplicity, and drive capability, it has application as loudspeaker tester and audible alarm, as well as in laboratory and test generators.

  15. Optimal Test Design with Rule-Based Item Generation

    ERIC Educational Resources Information Center

    Geerlings, Hanneke; van der Linden, Wim J.; Glas, Cees A. W.

    2013-01-01

    Optimal test-design methods are applied to rule-based item generation. Three different cases of automated test design are presented: (a) test assembly from a pool of pregenerated, calibrated items; (b) test generation on the fly from a pool of calibrated item families; and (c) test generation on the fly directly from calibrated features defining…

  16. Development, testing, and demonstration of an optimal fine coal cleaning circuit

    SciTech Connect

    Mishra, M.; Placha, M.; Bethell, P.

    1995-11-01

    The overall objective of this project is to improve the efficiency of fine coal cleaning. The project will be completed in two phases: bench-scale testing and demonstration of four advanced flotation cells and; in-plant proof-of-concept (POC) pilot plant testing of two flotation cells individually and in two-stage combinations. The goal is to ascertain if a two-stage circuit can result in reduced capital and operating costs while achieving improved separation efficiency. The plant selected for this project, Cyprus Emerald Coal Preparation plant, cleans 1200 tph of raw coal. The plant produces approximately 4 million tonnes of clean coal per year at an average as received energy content of 30.2 MJ/Kg (13,000 Btu/lb).

  17. Magnetic Circuit Model of PM Motor-Generator to Predict Radial Forces

    NASA Technical Reports Server (NTRS)

    McLallin, Kerry (Technical Monitor); Kascak, Peter E.; Dever, Timothy P.; Jansen, Ralph H.

    2004-01-01

    A magnetic circuit model is developed for a PM motor for flywheel applications. A sample motor is designed and modeled. Motor configuration and selection of materials is discussed, and the choice of winding configuration is described. A magnetic circuit model is described, which includes the stator back iron, rotor yoke, permanent magnets, air gaps and the stator teeth. Iterative solution of this model yields flux linkages, back EMF, torque, power, and radial force at the rotor caused by eccentricity. Calculated radial forces are then used to determine motor negative stiffness.

  18. Generation of copper rich metallic phases from waste printed circuit boards.

    PubMed

    Cayumil, R; Khanna, R; Ikram-Ul-Haq, M; Rajarao, R; Hill, A; Sahajwalla, V

    2014-10-01

    The rapid consumption and obsolescence of electronics have resulted in e-waste being one of the fastest growing waste streams worldwide. Printed circuit boards (PCBs) are among the most complex e-waste, containing significant quantities of hazardous and toxic materials leading to high levels of pollution if landfilled or processed inappropriately. However, PCBs are also an important resource of metals including copper, tin, lead and precious metals; their recycling is appealing especially as the concentration of these metals in PCBs is considerably higher than in their ores. This article is focused on a novel approach to recover copper rich phases from waste PCBs. Crushed PCBs were heat treated at 1150°C under argon gas flowing at 1L/min into a horizontal tube furnace. Samples were placed into an alumina crucible and positioned in the cold zone of the furnace for 5 min to avoid thermal shock, and then pushed into the hot zone, with specimens exposed to high temperatures for 10 and 20 min. After treatment, residues were pulled back to the cold zone and kept there for 5 min to avoid thermal cracking and re-oxidation. This process resulted in the generation of a metallic phase in the form of droplets and a carbonaceous residue. The metallic phase was formed of copper-rich red droplets and tin-rich white droplets along with the presence of several precious metals. The carbonaceous residue was found to consist of slag and ∼30% carbon. The process conditions led to the segregation of hazardous lead and tin clusters in the metallic phase. The heat treatment temperature was chosen to be above the melting point of copper; molten copper helped to concentrate metallic constituents and their separation from the carbonaceous residue and the slag. Inert atmosphere prevented the re-oxidation of metals and the loss of carbon in the gaseous fraction. Recycling e-waste is expected to lead to enhanced metal recovery, conserving natural resources and providing an environmentally

  19. Electron and optical beam testing of integrated circuits using CIVA, LIVA, and LECIVA

    SciTech Connect

    Cole, E.I. Jr.

    1995-09-01

    Charge-Induced Voltage Alteration (CIVA), Light-Induced Voltage Alteration, (LIVA), and Low Energy CIVA (LECIVA) are three new failure analysis imaging techniques developed to quickly localize defects on ICs. All three techniques utilize the voltage fluctuations of a constant current power supply as an electron or photon beam is scanned across an IC. CIVA and LECIVA yield rapid localization of open interconnections on ICs. LIVA allows quick localization of open-circuited and damaged semiconductor junctions. LIVA can also be used to image transistor logic states and can be performed from the backside of ICs with an infrared laser source. The physics of signal generation for each technique and examples of their use in failure analysis are described.

  20. Validation Testing of Hydrogen Generation Technology

    SciTech Connect

    Smith, Barton; Toops, Todd J

    2007-12-01

    This report describes the results of testing performed by ORNL for Photech Energies, Inc. The objective of the testing was to evaluate the efficacy of Photech's hydrogen generation reactor technology, which produces gaseous hydrogen through electrolysis. Photech provided several prototypes of their proprietary reactor for testing and the ancillary equipment, such as power supplies and electrolyte solutions, required for proper operation of the reactors. ORNL measured the production of hydrogen gas (volumetric flow of hydrogen at atmospheric pressure) as a function of input power and analyzed the composition of the output stream to determine the purity of the hydrogen content. ORNL attempted measurements on two basic versions of the prototype reactors-one version had a clear plastic outer cylinder, while another version had a stainless steel outer cylinder-but was only able to complete measurements on reactors in the plastic version. The problem observed in the stainless steel reactors was that in these reactors most of the hydrogen was produced near the anodes along with oxygen and the mixed gases made it impossible to determine the amount of hydrogen produced. In the plastic reactors the production of hydrogen gas increased monotonically with input power, and the flow rates increased faster at low input powers than they did at higher input powers. The maximum flow rate from the cathode port measured during the tests was 0.85 LPM at an input power of about 1100 W, an electrolyte concentration of 20%. The composition of the flow from the cathode port was primarily hydrogen and water vapor, with some oxygen and trace amounts of carbon dioxide. An operational mode that occurs briefly during certain operating conditions, and is characterized by flashes of light and violent bubbling near the cathode, might be attributable to the combustion of hydrogen and oxygen in the electrolyte solution.

  1. Testing and Qualifying Linear Integrated Circuits for Radiation Degradation in Space

    NASA Technical Reports Server (NTRS)

    Johnston, Allan H.; Rax, Bernard G.

    2006-01-01

    This paper discusses mechanisms and circuit-related factors that affect the degradation of linear integrated circuits from radiation in space. For some circuits there is sufficient degradation to affect performance at total dose levels below 4 krad(Si) because the circuit design techniques require higher gain for the pnp transistors that are the most sensitive to radiation. Qualification methods are recommended that include displacement damage as well as ionization damage.

  2. Analysis and comparison of real-time sine-wave generation for PWM circuits. [Pulse Width Modulation

    SciTech Connect

    Mirkazemi-Moud, M.; Green, T.C.; Williams, B.W. . Dept. of Computing and Electrical Engineering)

    1993-01-01

    The paper presented four methods for hardware and software generation in real time of sine waves suitable for PWM circuits. The sine waves are derived from a truncated modified cosine Taylor series, wt([pi]-wt) function, a digitally filtered trapezoid, and a second-order differential equation. Triple injection is incorporated by the addition of a defined magnitude triangular waveform of three times the fundamental frequency. Each sine wave generating technique is implemented, as applicable, in a programmable logic cell array and/or in microprocessor-based software. In each case, the output spectra and total harmonic distortion are compared with computer-simulated results.

  3. In-plant testing of a novel coal cleaning circuit using advanced technologies, Quarterly report, March 1 - May 31, 1996

    SciTech Connect

    Honaker, R.Q.; Reed, S.; Mohanty, M.K.

    1996-12-31

    Research conducted at Southern Illinois University at Carbondale over the past two years has identified highly efficient methods for treating fine coal (i.e., -28 mesh). In this study, a circuit comprised of the three advanced fine coal cleaning technologies is being tested in an operating preparation plant to evaluate circuit performance and to compare the performance with the current technologies used to treat -16 mesh fine coal. The circuit integrated a Floatex hydrosizer, a Falcon concentrator and a Jameson froth flotation cell. The Floatex hydrosizer is being used as a primary cleaner for the nominally -16 mesh Illinois No. 5 fine coal circuit feed. The overflow of the Floatex is screened at 48 mesh using a Sizetec vibratory screen to produce a clean coal product from the screen overflow. The screen overflow is further treated by the Falcon and Jameson Cell. During this reporting period, tests were initiated on the fine coal circuit installed at the Kerr-McGee Galatia preparation plant. The circuit was found to reduce both the ash content and the pyritic sulfur content. Additional in-plant circuitry tests are ongoing.

  4. 47 CFR 80.867 - Ship station tools, instruction books, circuit diagrams and testing equipment.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 47 Telecommunication 5 2014-10-01 2014-10-01 false Ship station tools, instruction books, circuit... Requirements for Cargo Vessels Not Subject to Subpart W § 80.867 Ship station tools, instruction books, circuit..., instruction books and circuit diagrams to enable the radiotelephone installation to be maintained in...

  5. 47 CFR 80.867 - Ship station tools, instruction books, circuit diagrams and testing equipment.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... 47 Telecommunication 5 2013-10-01 2013-10-01 false Ship station tools, instruction books, circuit... Requirements for Cargo Vessels Not Subject to Subpart W § 80.867 Ship station tools, instruction books, circuit..., instruction books and circuit diagrams to enable the radiotelephone installation to be maintained in...

  6. 47 CFR 80.867 - Ship station tools, instruction books, circuit diagrams and testing equipment.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 47 Telecommunication 5 2012-10-01 2012-10-01 false Ship station tools, instruction books, circuit... Requirements for Cargo Vessels Not Subject to Subpart W § 80.867 Ship station tools, instruction books, circuit..., instruction books and circuit diagrams to enable the radiotelephone installation to be maintained in...

  7. 47 CFR 80.867 - Ship station tools, instruction books, circuit diagrams and testing equipment.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 47 Telecommunication 5 2010-10-01 2010-10-01 false Ship station tools, instruction books, circuit... Requirements for Cargo Vessels Not Subject to Subpart W § 80.867 Ship station tools, instruction books, circuit..., instruction books and circuit diagrams to enable the radiotelephone installation to be maintained in...

  8. A rule-based software test data generator

    NASA Technical Reports Server (NTRS)

    Deason, William H.; Brown, David B.; Chang, Kai-Hsiung; Cross, James H., II

    1991-01-01

    Rule-based software test data generation is proposed as an alternative to either path/predicate analysis or random data generation. A prototype rule-based test data generator for Ada programs is constructed and compared to a random test data generator. Four Ada procedures are used in the comparison. Approximately 2000 rule-based test cases and 100,000 randomly generated test cases are automatically generated and executed. The success of the two methods is compared using standard coverage metrics. Simple statistical tests showing that even the primitive rule-based test data generation prototype is significantly better than random data generation are performed. This result demonstrates that rule-based test data generation is feasible and shows great promise in assisting test engineers, especially when the rule base is developed further.

  9. Design and testing of an all-digital readout integrated circuit for infrared focal plane arrays

    NASA Astrophysics Data System (ADS)

    Kelly, Michael; Berger, Robert; Colonero, Curtis; Gregg, Mark; Model, Joshua; Mooney, Daniel; Ringdahl, Eric

    2005-08-01

    The digital focal plane array (DFPA) project demonstrates the enabling technologies necessary to build readout integrated circuits for very large infrared focal plane arrays (IR FPAs). Large and fast FPAs are needed for a new class of spectrally diverse sensors. Because of the requirement for high-resolution (low noise) sampling, and because of the sample rate needed for rapid acquisition of high-resolution spectra, it is highly desirable to perform analog-to-digital (A/D) conversion right at the pixel level. A dedicated A/D converter located under every pixel in a one-million-plus element array, and all-digital readout integrated circuits will enable multi- and hyper-spectral imaging systems with unprecedented spatial and spectral resolution and wide area coverage. DFPAs provide similar benefits to standard IR imaging systems as well. We have addressed the key enabling technologies for realizing the DFPA architecture in this work. Our effort concentrated on demonstrating a 60-micron footprint, 14-bit A/D converter and 2.5 Gbps, 16:1 digital multiplexer, the most basic components of the sensor. The silicon test chip was fabricated in a 0.18-micron CMOS process, and was designed to operate with HgxCd1-xTe detectors at cryogenic temperatures. Two A/D designs, one using static logic and one using dynamic logic, were built and tested for performance and power dissipation. Structures for evaluating the bit-error-rate of the multiplexer on-chip and through a differential output driver were implemented for a complete performance assessment. A unique IC probe card with fixtures to mount into an evacuated, closed-cycle helium dewar were also designed for testing up to 2.5 Gbps at temperatures as low as 50 K.

  10. Off-line, built-in test techniques for VLSI circuits

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Sievers, M. W.

    1982-01-01

    It is shown that the use of redundant on-chip circuitry improves the testability of an entire VLSI circuit. In the study described here, five techniques applied to a two-bit ripple carry adder are compared. The techniques considered are self-oscillation, self-comparison, partition, scan path, and built-in logic block observer. It is noted that both classical stuck-at faults and nonclassical faults, such as bridging faults (shorts), stuck-on x faults where x may be 0, 1, or vary between the two, and parasitic flip-flop faults occur in IC structures. To simplify the analysis of the testing techniques, however, a stuck-at fault model is assumed.