CD-ROM Hardware Configurations: Selection and Design.

ERIC Educational Resources Information Center

Jaffe, Lee David; Watkins, Steven G.

1992-01-01

Presents selection and design considerations to help libraries make informed decisions about hardware configurations of CD-ROM systems. Highlights include CD-ROM configurations, including single drive workstations, daisychains, and jukeboxes; network configurations, including remote access; microcomputer features; CD-ROM drive selection; and…

Shuttle mission simulator hardware conceptual design report

NASA Technical Reports Server (NTRS)

Burke, J. F.

1973-01-01

The detailed shuttle mission simulator hardware requirements are discussed. The conceptual design methods, or existing technology, whereby those requirements will be fulfilled are described. Information of a general nature on the total design problem plus specific details on how these requirements are to be satisfied are reported. The configuration of the simulator is described and the capabilities for various types of training are identified.

Design Tools for Reconfigurable Hardware in Orbit (RHinO)

NASA Technical Reports Server (NTRS)

French, Mathew; Graham, Paul; Wirthlin, Michael; Larchev, Gregory; Bellows, Peter; Schott, Brian

2004-01-01

The Reconfigurable Hardware in Orbit (RHinO) project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. These tools leverage an established FPGA design environment and focus primarily on space effects mitigation and power optimization. The project is creating software to automatically test and evaluate the single-event-upsets (SEUs) sensitivities of an FPGA design and insert mitigation techniques. Extensions into the tool suite will also allow evolvable algorithm techniques to reconfigure around single-event-latchup (SEL) events. In the power domain, tools are being created for dynamic power visualiization and optimization. Thus, this technology seeks to enable the use of Reconfigurable Hardware in Orbit, via an integrated design tool-suite aiming to reduce risk, cost, and design time of multimission reconfigurable space processors using SRAM-based FPGAs.

Energy Efficient Engine combustor test hardware detailed design report

NASA Technical Reports Server (NTRS)

Burrus, D. L.; Chahrour, C. A.; Foltz, H. L.; Sabla, P. E.; Seto, S. P.; Taylor, J. R.

1984-01-01

The Energy Efficient Engine (E3) Combustor Development effort was conducted as part of the overall NASA/GE E3 Program. This effort included the selection of an advanced double-annular combustion system design. The primary intent was to evolve a design which meets the stringent emissions and life goals of the E3 as well as all of the usual performance requirements of combustion systems for modern turbofan engines. Numerous detailed design studies were conducted to define the features of the combustion system design. Development test hardware was fabricated, and an extensive testing effort was undertaken to evaluate the combustion system subcomponents in order to verify and refine the design. Technology derived from this development effort will be incorporated into the engine combustion system hardware design. This advanced engine combustion system will then be evaluated in component testing to verify the design intent. What is evolving from this development effort is an advanced combustion system capable of satisfying all of the combustion system design objectives and requirements of the E3. Fuel nozzle, diffuser, starting, and emissions design studies are discussed.

Hardware architecture design of image restoration based on time-frequency domain computation

NASA Astrophysics Data System (ADS)

Wen, Bo; Zhang, Jing; Jiao, Zipeng

2013-10-01

The image restoration algorithms based on time-frequency domain computation is high maturity and applied widely in engineering. To solve the high-speed implementation of these algorithms, the TFDC hardware architecture is proposed. Firstly, the main module is designed, by analyzing the common processing and numerical calculation. Then, to improve the commonality, the iteration control module is planed for iterative algorithms. In addition, to reduce the computational cost and memory requirements, the necessary optimizations are suggested for the time-consuming module, which include two-dimensional FFT/IFFT and the plural calculation. Eventually, the TFDC hardware architecture is adopted for hardware design of real-time image restoration system. The result proves that, the TFDC hardware architecture and its optimizations can be applied to image restoration algorithms based on TFDC, with good algorithm commonality, hardware realizability and high efficiency.

X-15 Hardware Design Challenges

NASA Technical Reports Server (NTRS)

Storms, Harrison A., Jr.

1991-01-01

Historical events in the development of the X-15 hardware design are presented. Some of the topics covered include: (1) drivers that led to the development of the X-15; (2) X-15 space research objectives; (3) original performance targets; (4) the X-15 typical mission; (5) X-15 dimensions and weight; (5) the propulsion system; (6) X-15 development milestones; (7) engineering and manufacturing challenges; (8) the X-15 structure; (9) ballistic flight control; (10) landing gear; (11) nose gear; and (12) an X-15 program recap.

Mechanically verified hardware implementing an 8-bit parallel IO Byzantine agreement processor

NASA Technical Reports Server (NTRS)

Moore, J. Strother

1992-01-01

Consider a network of four processors that use the Oral Messages (Byzantine Generals) Algorithm of Pease, Shostak, and Lamport to achieve agreement in the presence of faults. Bevier and Young have published a functional description of a single processor that, when interconnected appropriately with three identical others, implements this network under the assumption that the four processors step in synchrony. By formalizing the original Pease, et al work, Bevier and Young mechanically proved that such a network achieves fault tolerance. We develop, formalize, and discuss a hardware design that has been mechanically proven to implement their processor. In particular, we formally define mapping functions from the abstract state space of the Bevier-Young processor to a concrete state space of a hardware module and state a theorem that expresses the claim that the hardware correctly implements the processor. We briefly discuss the Brock-Hunt Formal Hardware Description Language which permits designs both to be proved correct with the Boyer-Moore theorem prover and to be expressed in a commercially supported hardware description language for additional electrical analysis and layout. We briefly describe our implementation.

Hardware Design Improvements to the Major Constituent Analyzer

NASA Technical Reports Server (NTRS)

Combs, Scott; Schwietert, Daniel; Anaya, Marcial; DeWolf, Shannon; Merrill, Dave; Gardner, Ben D.; Thoresen, Souzan; Granahan, John; Belcher, Paul; Matty, Chris

2011-01-01

The Major Constituent Analyzer (MCA) onboard the International Space Station (ISS) is designed to monitor the major constituents of the ISS's internal atmosphere. This mass spectrometer based system is an integral part of the Environmental Control and Life Support System (ECLSS) and is a primary tool for the management of ISS atmosphere composition. As a part of NASA Change Request CR10773A, several alterations to the hardware have been made to accommodate improved MCA logistics. First, the ORU 08 verification gas assembly has been modified to allow the verification gas cylinder to be installed on orbit. The verification gas is an essential MCA consumable that requires periodic replenishment. Designing the cylinder for subassembly transport reduces the size and weight of the maintained item for launch. The redesign of the ORU 08 assembly includes a redesigned housing, cylinder mounting apparatus, and pneumatic connection. The second hardware change is a redesigned wiring harness for the ORU 02 analyzer. The ORU 02 electrical connector interface was damaged in a previous on-orbit installation, and this necessitated the development of a temporary fix while a more permanent solution was developed. The new wiring harness design includes flexible cable as well as indexing fasteners and guide-pins, and provides better accessibility during the on-orbit maintenance operation. This presentation will describe the hardware improvements being implemented for MCA as well as the expected improvement to logistics and maintenance.

Parameterized hardware description as object oriented hardware model implementation

NASA Astrophysics Data System (ADS)

Drabik, Pawel K.

2010-09-01

The paper introduces novel model for design, visualization and management of complex, highly adaptive hardware systems. The model settles component oriented environment for both hardware modules and software application. It is developed on parameterized hardware description research. Establishment of stable link between hardware and software, as a purpose of designed and realized work, is presented. Novel programming framework model for the environment, named Graphic-Functional-Components is presented. The purpose of the paper is to present object oriented hardware modeling with mentioned features. Possible model implementation in FPGA chips and its management by object oriented software in Java is described.

Energy efficient engine low-pressure compressor component test hardware detailed design report

NASA Technical Reports Server (NTRS)

Michael, C. J.; Halle, J. E.

1981-01-01

The aerodynamic and mechanical design description of the low pressure compressor component of the Energy Efficient Engine were used. The component was designed to meet the requirements of the Flight Propulsion System while maintaining a low cost approach in providing a low pressure compressor design for the Integrated Core/Low Spool test required in the Energy Efficient Engine Program. The resulting low pressure compressor component design meets or exceeds all design goals with the exception of surge margin. In addition, the expense of hardware fabrication for the Integrated Core/Low Spool test has been minimized through the use of existing minor part hardware.

Design and development of data acquisition system based on WeChat hardware

NASA Astrophysics Data System (ADS)

Wang, Zhitao; Ding, Lei

2018-06-01

Data acquisition system based on WeChat hardware provides methods for popularization and practicality of data acquisition. The whole system is based on WeChat hardware platform, where the hardware part is developed on DA14580 development board and the software part is based on Alibaba Cloud. We designed service module, logic processing module, data processing module and database module. The communication between hardware and software uses AirSync Protocal. We tested this system by collecting temperature and humidity data, and the result shows that the system can aquisite the temperature and humidity in real time according to settings.

HSCT Sector Combustor Hardware Modifications for Improved Combustor Design

NASA Technical Reports Server (NTRS)

Greenfield, Stuart C.; Heberling, Paul V.; Moertle, George E.

2005-01-01

An alternative to the stepped-dome design for the lean premixed prevaporized (LPP) combustor has been developed. The new design uses the same premixer types as the stepped-dome design: integrated mixer flameholder (IMFH) tubes and a cyclone swirler pilot. The IMFH fuel system has been taken to a new level of development. Although the IMFH fuel system design developed in this Task is not intended to be engine-like hardware, it does have certain characteristics of engine hardware, including separate fuel circuits for each of the fuel stages. The four main stage fuel circuits are integrated into a single system which can be withdrawn from the combustor as a unit. Additionally, two new types of liner cooling have been designed. The resulting lean blowout data was found to correlate well with the Lefebvre parameter. As expected, CO and unburned hydrocarbons emissions were shown to have an approximately linear relationship, even though some scatter was present in the data, and the CO versus flame temperature data showed the typical cupped shape. Finally, the NOx emissions data was shown to agree well with a previously developed correlation based on emissions data from Configuration 3 tests performed at GEAE. The design variations of the cyclone swirler pilot that were investigated in this study did not significantly change the NOx emissions from the baseline design (GEAE Configuration 3) at supersonic cruise conditions.

Hardware description languages

NASA Technical Reports Server (NTRS)

Tucker, Jerry H.

1994-01-01

Hardware description languages are special purpose programming languages. They are primarily used to specify the behavior of digital systems and are rapidly replacing traditional digital system design techniques. This is because they allow the designer to concentrate on how the system should operate rather than on implementation details. Hardware description languages allow a digital system to be described with a wide range of abstraction, and they support top down design techniques. A key feature of any hardware description language environment is its ability to simulate the modeled system. The two most important hardware description languages are Verilog and VHDL. Verilog has been the dominant language for the design of application specific integrated circuits (ASIC's). However, VHDL is rapidly gaining in popularity.

Automated culture system experiments hardware: developing test results and design solutions.

PubMed

Freddi, M; Covini, M; Tenconi, C; Ricci, C; Caprioli, M; Cotronei, V

2002-07-01

The experiment proposed by Prof. Ricci University of Milan is funded by ASI with Laben as industrial Prime Contractor. ACS-EH (Automated Culture System-Experiment Hardware) will support the multigenerational experiment on weightlessness with rotifers and nematodes within four Experiment Containers (ECs) located inside the European Modular Cultivation System (EMCS) facility..Actually the Phase B is in progress and a concept design solution has been defined. The most challenging aspects for the design of such hardware are, from biological point of view the provision of an environment which permits animal's survival and to maintain desiccated generations separated and from the technical point of view, the miniaturisation of the hardware itself due to the reduce EC provided volume (160mmx60mmx60mm). The miniaturisation will allow a better use of the available EMCS Facility resources (e.g. volume. power etc.) and to fulfil the experiment requirements. ACS-EH, will be ready to fly in the year 2005 on boar the ISS.

A novel visual hardware behavioral language

NASA Technical Reports Server (NTRS)

Li, Xueqin; Cheng, H. D.

1992-01-01

Most hardware behavioral languages just use texts to describe the behavior of the desired hardware design. This is inconvenient for VLSI designers who enjoy using the schematic approach. The proposed visual hardware behavioral language has the ability to graphically express design information using visual parallel models (blocks), visual sequential models (processes) and visual data flow graphs (which consist of primitive operational icons, control icons, and Data and Synchro links). Thus, the proposed visual hardware behavioral language can not only specify hardware concurrent and sequential functionality, but can also visually expose parallelism, sequentiality, and disjointness (mutually exclusive operations) for the hardware designers. That would make the hardware designers capture the design ideas easily and explicitly using this visual hardware behavioral language.

Hardware Design of the Energy Efficient Fall Detection Device

NASA Astrophysics Data System (ADS)

Skorodumovs, A.; Avots, E.; Hofmanis, J.; Korāts, G.

2016-04-01

Health issues for elderly people may lead to different injuries obtained during simple activities of daily living. Potentially the most dangerous are unintentional falls that may be critical or even lethal to some patients due to the heavy injury risk. In the project "Wireless Sensor Systems in Telecare Application for Elderly People", we have developed a robust fall detection algorithm for a wearable wireless sensor. To optimise the algorithm for hardware performance and test it in field, we have designed an accelerometer based wireless fall detector. Our main considerations were: a) functionality - so that the algorithm can be applied to the chosen hardware, and b) power efficiency - so that it can run for a very long time. We have picked and tested the parts, built a prototype, optimised the firmware for lowest consumption, tested the performance and measured the consumption parameters. In this paper, we discuss our design choices and present the results of our work.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

NASA Astrophysics Data System (ADS)

Barr, David R. W.; Dudek, Piotr

2009-12-01

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

New Single Piece Blast Hardware design

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ulrich, Andri; Steinzig, Michael Louis; Aragon, Daniel Adrian

W, Q and PF engineers and machinists designed and fabricated, on the new Mazak i300, the first Single Piece Blast Hardware (unclassified design shown) reducing fabrication and inspection time by over 50%. The first DU Single Piece is completed and will be used for Hydro Test 3680. Past hydro tests used a twopiece assembly due to a lack of equipment capable of machining the complex saddle shape in a single piece. The i300 provides turning and milling 5-axis machining on one machine. The milling head on the i300 can machine past 90 relative to the spindle axis. This makes itmore » possible to machine the complex saddle surface on a single piece. Going to a single piece eliminates tolerance problems, such as tilting and eccentricity, that typically occurred when assembling the two pieces together« less

Hardware Testing and System Evaluation: Procedures to Evaluate Commodity Hardware for Production Clusters

DOE Office of Scientific and Technical Information (OSTI.GOV)

Goebel, J

2004-02-27

Without stable hardware any program will fail. The frustration and expense of supporting bad hardware can drain an organization, delay progress, and frustrate everyone involved. At Stanford Linear Accelerator Center (SLAC), we have created a testing method that helps our group, SLAC Computer Services (SCS), weed out potentially bad hardware and purchase the best hardware at the best possible cost. Commodity hardware changes often, so new evaluations happen periodically each time we purchase systems and minor re-evaluations happen for revised systems for our clusters, about twice a year. This general framework helps SCS perform correct, efficient evaluations. This article outlinesmore » SCS's computer testing methods and our system acceptance criteria. We expanded the basic ideas to other evaluations such as storage, and we think the methods outlined in this article has helped us choose hardware that is much more stable and supportable than our previous purchases. We have found that commodity hardware ranges in quality, so systematic method and tools for hardware evaluation were necessary. This article is based on one instance of a hardware purchase, but the guidelines apply to the general problem of purchasing commodity computer systems for production computational work.« less

Intrinsic Hardware Evolution for the Design and Reconfiguration of Analog Speed Controllers for a DC Motor

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; Ferguson, Michael I.

2003-01-01

Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a second generation Field Programmable Transistor Array (FPTA2). The performance of an evolved controller is compared to that of a conventional proportional-integral (PI) controller. It is shown that hardware evolution is able to create a compact design that provides good performance, while using considerably less functional electronic components than the conventional design. Additionally, the use of hardware evolution to provide fault tolerance by reconfiguring the design is explored. Experimental results are presented showing that significant recovery of capability can be made in the face of damaging induced faults.

Theorem Proving in Intel Hardware Design

NASA Technical Reports Server (NTRS)

O'Leary, John

2009-01-01

For the past decade, a framework combining model checking (symbolic trajectory evaluation) and higher-order logic theorem proving has been in production use at Intel. Our tools and methodology have been used to formally verify execution cluster functionality (including floating-point operations) for a number of Intel products, including the Pentium(Registered TradeMark)4 and Core(TradeMark)i7 processors. Hardware verification in 2009 is much more challenging than it was in 1999 - today s CPU chip designs contain many processor cores and significant firmware content. This talk will attempt to distill the lessons learned over the past ten years, discuss how they apply to today s problems, outline some future directions.

Accelerating a MPEG-4 video decoder through custom software/hardware co-design

NASA Astrophysics Data System (ADS)

Díaz, Jorge L.; Barreto, Dacil; García, Luz; Marrero, Gustavo; Carballo, Pedro P.; Núñez, Antonio

2007-05-01

In this paper we present a novel methodology to accelerate an MPEG-4 video decoder using software/hardware co-design for wireless DAB/DMB networks. Software support includes the services provided by the embedded kernel μC/OS-II, and the application tasks mapped to software. Hardware support includes several custom co-processors and a communication architecture with bridges to the main system bus and with a dual port SRAM. Synchronization among tasks is achieved at two levels, by a hardware protocol and by kernel level scheduling services. Our reference application is an MPEG-4 video decoder composed of several software functions and written using a special C++ library named CASSE. Profiling and space exploration techniques were used previously over the Advanced Simple Profile (ASP) MPEG-4 decoder to determinate the best HW/SW partition developed here. This research is part of the ARTEMI project and its main goal is the establishment of methodologies for the design of real-time complex digital systems using Programmable Logic Devices with embedded microprocessors as target technology and the design of multimedia systems for broadcasting networks as reference application.

Test Hardware Design for Flight-Like Operation of Advanced Stirling Convertors

NASA Technical Reports Server (NTRS)

Oriti, Salvatore M.

2012-01-01

NASA Glenn Research Center (GRC) has been supporting development of the Advanced Stirling Radioisotope Generator (ASRG) since 2006. A key element of the ASRG project is providing life, reliability, and performance testing of the Advanced Stirling Convertor (ASC). For this purpose, the Thermal Energy Conversion branch at GRC has been conducting extended operation of a multitude of free-piston Stirling convertors. The goal of this effort is to generate long-term performance data (tens of thousands of hours) simultaneously on multiple units to build a life and reliability database. The test hardware for operation of these convertors was designed to permit in-air investigative testing, such as performance mapping over a range of environmental conditions. With this, there was no requirement to accurately emulate the flight hardware. For the upcoming ASC-E3 units, the decision has been made to assemble the convertors into a flight-like configuration. This means the convertors will be arranged in the dual-opposed configuration in a housing that represents the fit, form, and thermal function of the ASRG. The goal of this effort is to enable system level tests that could not be performed with the traditional test hardware at GRC. This offers the opportunity to perform these system-level tests much earlier in the ASRG flight development, as they would normally not be performed until fabrication of the qualification unit. This paper discusses the requirements, process, and results of this flight-like hardware design activity.

Functional design specification for Stowage List And Hardware Tracking System (SLAHTS). [space shuttles

NASA Technical Reports Server (NTRS)

Keltner, D. J.

1975-01-01

This functional design specification defines the total systems approach to meeting the requirements stated in the Detailed Requirements Document for Stowage List and Hardware Tracking System for the space shuttle program. The stowage list and hardware tracking system is identified at the system and subsystem level with each subsystem defined as a function of the total system.

Hardware

NASA Technical Reports Server (NTRS)

1999-01-01

The full complement of EDOMP investigations called for a broad spectrum of flight hardware ranging from commercial items, modified for spaceflight, to custom designed hardware made to meet the unique requirements of testing in the space environment. In addition, baseline data collection before and after spaceflight required numerous items of ground-based hardware. Two basic categories of ground-based hardware were used in EDOMP testing before and after flight: (1) hardware used for medical baseline testing and analysis, and (2) flight-like hardware used both for astronaut training and medical testing. To ensure post-landing data collection, hardware was required at both the Kennedy Space Center (KSC) and the Dryden Flight Research Center (DFRC) landing sites. Items that were very large or sensitive to the rigors of shipping were housed permanently at the landing site test facilities. Therefore, multiple sets of hardware were required to adequately support the prime and backup landing sites plus the Johnson Space Center (JSC) laboratories. Development of flight hardware was a major element of the EDOMP. The challenges included obtaining or developing equipment that met the following criteria: (1) compact (small size and light weight), (2) battery-operated or requiring minimal spacecraft power, (3) sturdy enough to survive the rigors of spaceflight, (4) quiet enough to pass acoustics limitations, (5) shielded and filtered adequately to assure electromagnetic compatibility with spacecraft systems, (6) user-friendly in a microgravity environment, and (7) accurate and efficient operation to meet medical investigative requirements.

Optimized design of embedded DSP system hardware supporting complex algorithms

NASA Astrophysics Data System (ADS)

Li, Yanhua; Wang, Xiangjun; Zhou, Xinling

2003-09-01

The paper presents an optimized design method for a flexible and economical embedded DSP system that can implement complex processing algorithms as biometric recognition, real-time image processing, etc. It consists of a floating-point DSP, 512 Kbytes data RAM, 1 Mbytes FLASH program memory, a CPLD for achieving flexible logic control of input channel and a RS-485 transceiver for local network communication. Because of employing a high performance-price ratio DSP TMS320C6712 and a large FLASH in the design, this system permits loading and performing complex algorithms with little algorithm optimization and code reduction. The CPLD provides flexible logic control for the whole DSP board, especially in input channel, and allows convenient interface between different sensors and DSP system. The transceiver circuit can transfer data between DSP and host computer. In the paper, some key technologies are also introduced which make the whole system work efficiently. Because of the characters referred above, the hardware is a perfect flat for multi-channel data collection, image processing, and other signal processing with high performance and adaptability. The application section of this paper presents how this hardware is adapted for the biometric identification system with high identification precision. The result reveals that this hardware is easy to interface with a CMOS imager and is capable of carrying out complex biometric identification algorithms, which require real-time process.

The role of hardware in learning engineering fundamentals: An empirical study of engineering design and product analysis activity

NASA Astrophysics Data System (ADS)

Brereton, Margot Felicity

A series of short engineering exercises and design projects was created to help students learn to apply abstract knowledge to physical experiences with hardware. The exercises involved designing machines from kits of materials and dissecting and analyzing familiar household products. Students worked in teams. During the activities students brought their knowledge of engineering fundamentals to bear. Videotape analysis was used to identify and characterize the ways in which hardware contributed to learning fundamental concepts. Structural and qualitative analyses of videotaped activities were undertaken. Structural analysis involved counting the references to theory and hardware and the extent of interleaving of references in activity. The analysis found that there was much more discussion linking fundamental concepts to hardware in some activities than in others. The analysis showed that the interleaving of references to theory and hardware in activity is observable and quantifiable. Qualitative analysis was used to investigate the dialog linking concepts and hardware. Students were found to advance their designs and their understanding of engineering fundamentals through a negotiation process in which they pitted abstract concepts against hardware behavior. Through this process students sorted out theoretical assumptions and causal relations. In addition they discovered design assumptions, functional connections and physical embodiments of abstract concepts in hardware, developing a repertoire of familiar hardware components and machines. Hardware was found to be integral to learning, affecting the course of inquiry and the dynamics of group interaction. Several case studies are presented to illustrate the processes at work. The research illustrates the importance of working across the boundary between abstractions and experiences with hardware in order to learn engineering and physical sciences. The research findings are: (a) the negotiation process by which

Ripple FPN reduced algorithm based on temporal high-pass filter and hardware implementation

NASA Astrophysics Data System (ADS)

Li, Yiyang; Li, Shuo; Zhang, Zhipeng; Jin, Weiqi; Wu, Lei; Jin, Minglei

2016-11-01

Cooled infrared detector arrays always suffer from undesired Ripple Fixed-Pattern Noise (FPN) when observe the scene of sky. The Ripple Fixed-Pattern Noise seriously affect the imaging quality of thermal imager, especially for small target detection and tracking. It is hard to eliminate the FPN by the Calibration based techniques and the current scene-based nonuniformity algorithms. In this paper, we present a modified space low-pass and temporal high-pass nonuniformity correction algorithm using adaptive time domain threshold (THP&GM). The threshold is designed to significantly reduce ghosting artifacts. We test the algorithm on real infrared in comparison to several previously published methods. This algorithm not only can effectively correct common FPN such as Stripe, but also has obviously advantage compared with the current methods in terms of detail protection and convergence speed, especially for Ripple FPN correction. Furthermore, we display our architecture with a prototype built on a Xilinx Virtex-5 XC5VLX50T field-programmable gate array (FPGA). The hardware implementation of the algorithm based on FPGA has two advantages: (1) low resources consumption, and (2) small hardware delay (less than 20 lines). The hardware has been successfully applied in actual system.

Lab at Home: Hardware Kits for a Digital Design Lab

ERIC Educational Resources Information Center

Oliver, J. P.; Haim, F.

2009-01-01

An innovative laboratory methodology for an introductory digital design course is presented. Instead of having traditional lab experiences, where students have to come to school classrooms, a "lab at home" concept is proposed. Students perform real experiments in their own homes, using hardware kits specially developed for this purpose. They…

Parallel transmission RF pulse design for eddy current correction at ultra high field.

PubMed

Zheng, Hai; Zhao, Tiejun; Qian, Yongxian; Ibrahim, Tamer; Boada, Fernando

2012-08-01

Multidimensional spatially selective RF pulses have been used in MRI applications such as B₁ and B₀ inhomogeneities mitigation. However, the long pulse duration has limited their practical applications. Recently, theoretical and experimental studies have shown that parallel transmission can effectively shorten pulse duration without sacrificing the quality of the excitation pattern. Nonetheless, parallel transmission with accelerated pulses can be severely impeded by hardware and/or system imperfections. One of such imperfections is the effect of the eddy current field. In this paper, we first show the effects of the eddy current field on the excitation pattern and then report an RF pulse the design method to correct eddy current fields caused by the RF coil and the gradient system. Experimental results on a 7 T human eight-channel parallel transmit system show substantial improvements on excitation patterns with the use of eddy current correction. Moreover, the proposed model-based correction method not only demonstrates comparable excitation patterns as the trajectory measurement method, but also significantly improves time efficiency. Copyright © 2012. Published by Elsevier Inc.

SensoTube: A Scalable Hardware Design Architecture for Wireless Sensors and Actuators Networks Nodes in the Agricultural Domain

PubMed Central

Piromalis, Dimitrios; Arvanitis, Konstantinos

2016-01-01

Wireless Sensor and Actuators Networks (WSANs) constitute one of the most challenging technologies with tremendous socio-economic impact for the next decade. Functionally and energy optimized hardware systems and development tools maybe is the most critical facet of this technology for the achievement of such prospects. Especially, in the area of agriculture, where the hostile operating environment comes to add to the general technological and technical issues, reliable and robust WSAN systems are mandatory. This paper focuses on the hardware design architectures of the WSANs for real-world agricultural applications. It presents the available alternatives in hardware design and identifies their difficulties and problems for real-life implementations. The paper introduces SensoTube, a new WSAN hardware architecture, which is proposed as a solution to the various existing design constraints of WSANs. The establishment of the proposed architecture is based, firstly on an abstraction approach in the functional requirements context, and secondly, on the standardization of the subsystems connectivity, in order to allow for an open, expandable, flexible, reconfigurable, energy optimized, reliable and robust hardware system. The SensoTube implementation reference model together with its encapsulation design and installation are analyzed and presented in details. Furthermore, as a proof of concept, certain use cases have been studied in order to demonstrate the benefits of migrating existing designs based on the available open-source hardware platforms to SensoTube architecture. PMID:27527180

SensoTube: A Scalable Hardware Design Architecture for Wireless Sensors and Actuators Networks Nodes in the Agricultural Domain.

PubMed

Piromalis, Dimitrios; Arvanitis, Konstantinos

2016-08-04

Wireless Sensor and Actuators Networks (WSANs) constitute one of the most challenging technologies with tremendous socio-economic impact for the next decade. Functionally and energy optimized hardware systems and development tools maybe is the most critical facet of this technology for the achievement of such prospects. Especially, in the area of agriculture, where the hostile operating environment comes to add to the general technological and technical issues, reliable and robust WSAN systems are mandatory. This paper focuses on the hardware design architectures of the WSANs for real-world agricultural applications. It presents the available alternatives in hardware design and identifies their difficulties and problems for real-life implementations. The paper introduces SensoTube, a new WSAN hardware architecture, which is proposed as a solution to the various existing design constraints of WSANs. The establishment of the proposed architecture is based, firstly on an abstraction approach in the functional requirements context, and secondly, on the standardization of the subsystems connectivity, in order to allow for an open, expandable, flexible, reconfigurable, energy optimized, reliable and robust hardware system. The SensoTube implementation reference model together with its encapsulation design and installation are analyzed and presented in details. Furthermore, as a proof of concept, certain use cases have been studied in order to demonstrate the benefits of migrating existing designs based on the available open-source hardware platforms to SensoTube architecture.

Hardware accelerator design for tracking in smart camera

NASA Astrophysics Data System (ADS)

Singh, Sanjay; Dunga, Srinivasa Murali; Saini, Ravi; Mandal, A. S.; Shekhar, Chandra; Vohra, Anil

2011-10-01

Smart Cameras are important components in video analysis. For video analysis, smart cameras needs to detect interesting moving objects, track such objects from frame to frame, and perform analysis of object track in real time. Therefore, the use of real-time tracking is prominent in smart cameras. The software implementation of tracking algorithm on a general purpose processor (like PowerPC) could achieve low frame rate far from real-time requirements. This paper presents the SIMD approach based hardware accelerator designed for real-time tracking of objects in a scene. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA. Resulted frame rate is 30 frames per second for 250x200 resolution video in gray scale.

Open-source hardware for medical devices.

PubMed

Niezen, Gerrit; Eslambolchilar, Parisa; Thimbleby, Harold

2016-04-01

Open-source hardware is hardware whose design is made publicly available so anyone can study, modify, distribute, make and sell the design or the hardware based on that design. Some open-source hardware projects can potentially be used as active medical devices. The open-source approach offers a unique combination of advantages, including reducing costs and faster innovation. This article compares 10 of open-source healthcare projects in terms of how easy it is to obtain the required components and build the device.

Dedicated hardware processor and corresponding system-on-chip design for real-time laser speckle imaging.

PubMed

Jiang, Chao; Zhang, Hongyan; Wang, Jia; Wang, Yaru; He, Heng; Liu, Rui; Zhou, Fangyuan; Deng, Jialiang; Li, Pengcheng; Luo, Qingming

2011-11-01

Laser speckle imaging (LSI) is a noninvasive and full-field optical imaging technique which produces two-dimensional blood flow maps of tissues from the raw laser speckle images captured by a CCD camera without scanning. We present a hardware-friendly algorithm for the real-time processing of laser speckle imaging. The algorithm is developed and optimized specifically for LSI processing in the field programmable gate array (FPGA). Based on this algorithm, we designed a dedicated hardware processor for real-time LSI in FPGA. The pipeline processing scheme and parallel computing architecture are introduced into the design of this LSI hardware processor. When the LSI hardware processor is implemented in the FPGA running at the maximum frequency of 130 MHz, up to 85 raw images with the resolution of 640×480 pixels can be processed per second. Meanwhile, we also present a system on chip (SOC) solution for LSI processing by integrating the CCD controller, memory controller, LSI hardware processor, and LCD display controller into a single FPGA chip. This SOC solution also can be used to produce an application specific integrated circuit for LSI processing.

Towards composition of verified hardware devices

NASA Technical Reports Server (NTRS)

Schubert, E. Thomas; Levitt, K.; Cohen, G. C.

1991-01-01

Computers are being used where no affordable level of testing is adequate. Safety and life critical systems must find a replacement for exhaustive testing to guarantee their correctness. Through a mathematical proof, hardware verification research has focused on device verification and has largely ignored system composition verification. To address these deficiencies, we examine how the current hardware verification methodology can be extended to verify complete systems.

Commercial Aircraft Maintenance Experience Relating to Engine External Hardware

NASA Technical Reports Server (NTRS)

Soditus, Sharon M.

2006-01-01

Airlines are extremely sensitive to the amount of dollars spent on maintaining the external engine hardware in the field. Analysis reveals that many problems revolve around a central issue, reliability. Fuel and oil leakage due to seal failure and electrical fault messages due to wire harness failures play a major role in aircraft delays and cancellations (D&C's) and scheduled maintenance. Correcting these items on the line requires a large investment of engineering resources and manpower after the fact. The smartest and most cost effective philosophy is to build the best hardware the first time. The only way to do that is to completely understand and model the operating environment, study the field experience of similar designs and to perform extensive testing.

Open-source hardware for medical devices

PubMed Central

2016-01-01

Open-source hardware is hardware whose design is made publicly available so anyone can study, modify, distribute, make and sell the design or the hardware based on that design. Some open-source hardware projects can potentially be used as active medical devices. The open-source approach offers a unique combination of advantages, including reducing costs and faster innovation. This article compares 10 of open-source healthcare projects in terms of how easy it is to obtain the required components and build the device. PMID:27158528

AirSTAR Hardware and Software Design for Beyond Visual Range Flight Research

NASA Technical Reports Server (NTRS)

Laughter, Sean; Cox, David

2016-01-01

The National Aeronautics and Space Administration (NASA) Airborne Subscale Transport Aircraft Research (AirSTAR) Unmanned Aerial System (UAS) is a facility developed to study the flight dynamics of vehicles in emergency conditions, in support of aviation safety research. The system was upgraded to have its operational range significantly expanded, going beyond the line of sight of a ground-based pilot. A redesign of the airborne flight hardware was undertaken, as well as significant changes to the software base, in order to provide appropriate autonomous behavior in response to a number of potential failures and hazards. Ground hardware and system monitors were also upgraded to include redundant communication links, including ADS-B based position displays and an independent flight termination system. The design included both custom and commercially available avionics, combined to allow flexibility in flight experiment design while still benefiting from tested configurations in reversionary flight modes. A similar hierarchy was employed in the software architecture, to allow research codes to be tested, with a fallback to more thoroughly validated flight controls. As a remotely piloted facility, ground systems were also developed to ensure the flight modes and system state were communicated to ground operations personnel in real-time. Presented in this paper is a general overview of the concept of operations for beyond visual range flight, and a detailed review of the airborne hardware and software design. This discussion is held in the context of the safety and procedural requirements that drove many of the design decisions for the AirSTAR UAS Beyond Visual Range capability.

When "Less is More": The Optimal Design of Language Laboratory Hardware.

ERIC Educational Resources Information Center

Kershaw, Gary; Boyd, Gary

1980-01-01

The results of a process of designing, building, and "de-bugging" two replacement language laboratory hardware systems at Concordia University (Montreal) are described. Because commercially available systems did not meet specifications within budgetary constraints, the systems were built by the university technical department. The systems replaced…

Study of the adaptability of existing hardware designs to a Pioneer Saturn/Uranus probe

NASA Technical Reports Server (NTRS)

1973-01-01

The basic concept of designing a scientific entry probe for the expected range of environments at Saturn or Uranus and making the probe compatible with the interface constraints of the Pioneer spacecraft was investigated for launches in the early 1980's. It was found that the amount of hardware commonality between that used in the Pioneer Venus program and that for the Saturn/Uranus probe was approximately 85%. It is recommended that additional development studies be conducted to improve the hardware definitions of the probe design for the following: heat shield, battery, nose cap jettisoning, and thermal control insulation.

Motion compensation in digital subtraction angiography using graphics hardware.

PubMed

Deuerling-Zheng, Yu; Lell, Michael; Galant, Adam; Hornegger, Joachim

2006-07-01

An inherent disadvantage of digital subtraction angiography (DSA) is its sensitivity to patient motion which causes artifacts in the subtraction images. These artifacts could often reduce the diagnostic value of this technique. Automated, fast and accurate motion compensation is therefore required. To cope with this requirement, we first examine a method explicitly designed to detect local motions in DSA. Then, we implement a motion compensation algorithm by means of block matching on modern graphics hardware. Both methods search for maximal local similarity by evaluating a histogram-based measure. In this context, we are the first who have mapped an optimizing search strategy on graphics hardware while paralleling block matching. Moreover, we provide an innovative method for creating histograms on graphics hardware with vertex texturing and frame buffer blending. It turns out that both methods can effectively correct the artifacts in most case, as the hardware implementation of block matching performs much faster: the displacements of two 1024 x 1024 images can be calculated at 3 frames/s with integer precision or 2 frames/s with sub-pixel precision. Preliminary clinical evaluation indicates that the computation with integer precision could already be sufficient.

IDEAS and App Development Internship in Hardware and Software Design

NASA Technical Reports Server (NTRS)

Alrayes, Rabab D.

2016-01-01

In this report, I will discuss the tasks and projects I have completed while working as an electrical engineering intern during the spring semester of 2016 at NASA Kennedy Space Center. In the field of software development, I completed tasks for the G-O Caching Mobile App and the Asbestos Management Information System (AMIS) Web App. The G-O Caching Mobile App was written in HTML, CSS, and JavaScript on the Cordova framework, while the AMIS Web App is written in HTML, CSS, JavaScript, and C# on the AngularJS framework. My goals and objectives on these two projects were to produce an app with an eye-catching and intuitive User Interface (UI), which will attract more employees to participate; to produce a fully-tested, fully functional app which supports workforce engagement and exploration; to produce a fully-tested, fully functional web app that assists technicians working in asbestos management. I also worked in hardware development on the Integrated Display and Environmental Awareness System (IDEAS) wearable technology project. My tasks on this project were focused in PCB design and camera integration. My goals and objectives for this project were to successfully integrate fully functioning custom hardware extenders on the wearable technology headset to minimize the size of hardware on the smart glasses headset for maximum user comfort; to successfully integrate fully functioning camera onto the headset. By the end of this semester, I was able to successfully develop four extender boards to minimize hardware on the headset, and assisted in integrating a fully-functioning camera into the system.

Hardware Evolution of Closed-Loop Controller Designs

NASA Technical Reports Server (NTRS)

Gwaltney, David; Ferguson, Ian

2002-01-01

Poster presentation will outline on-going efforts at NASA, MSFC to employ various Evolvable Hardware experimental platforms in the evolution of digital and analog circuitry for application to automatic control. Included will be information concerning the application of commercially available hardware and software along with the use of the JPL developed FPTA2 integrated circuit and supporting JPL developed software. Results to date will be presented.

Efficient architecture for spike sorting in reconfigurable hardware.

PubMed

Hwang, Wen-Jyi; Lee, Wei-Hao; Lin, Shiow-Jyu; Lai, Sheng-Ying

2013-11-01

This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.

Hardware synthesis from DDL description. [simulating a digital system for computerized design of large scale integrated circuits

NASA Technical Reports Server (NTRS)

Shiva, S. G.; Shah, A. M.

1980-01-01

The details of digital systems can be conveniently input into the design automation system by means of hardware description language (HDL). The computer aided design and test (CADAT) system at NASA MSFC is used for the LSI design. The digital design language (DDL) was selected as HDL for the CADAT System. DDL translator output can be used for the hardware implementation of the digital design. Problems of selecting the standard cells from the CADAT standard cell library to realize the logic implied by the DDL description of the system are addressed.

Health Maintenance System (HMS) Hardware Research, Design, and Collaboration

NASA Technical Reports Server (NTRS)

Gonzalez, Stefanie M.

2010-01-01

The Space Life Sciences division (SLSD) concentrates on optimizing a crew member's health. Developments are translated into innovative engineering solutions, research growth, and community awareness. This internship incorporates all those areas by targeting various projects. The main project focuses on integrating clinical and biomedical engineering principles to design, develop, and test new medical kits scheduled for launch in the Spring of 2011. Additionally, items will be tagged with Radio Frequency Interference Devices (RFID) to keep track of the inventory. The tags will then be tested to optimize Radio Frequency feed and feed placement. Research growth will occur with ground based experiments designed to measure calcium encrusted deposits in the International Space Station (ISS). The tests will assess the urine calcium levels with Portable Clinical Blood Analyzer (PCBA) technology. If effective then a model for urine calcium will be developed and expanded to microgravity environments. To support collaboration amongst the subdivisions of SLSD the architecture of the Crew Healthcare Systems (CHeCS) SharePoint site has been redesigned for maximum efficiency. Community collaboration has also been established with the University of Southern California, Dept. of Aeronautical Engineering and the Food and Drug Administration (FDA). Hardware disbursements will transpire within these communities to support planetary surface exploration and to serve as an educational tool demonstrating how ground based medicine influenced the technological development of space hardware.

Design and control of compliant tensegrity robots through simulation and hardware validation

PubMed Central

Caluwaerts, Ken; Despraz, Jérémie; Işçen, Atıl; Sabelhaus, Andrew P.; Bruce, Jonathan; Schrauwen, Benjamin; SunSpiral, Vytas

2014-01-01

To better understand the role of tensegrity structures in biological systems and their application to robotics, the Dynamic Tensegrity Robotics Lab at NASA Ames Research Center, Moffett Field, CA, USA, has developed and validated two software environments for the analysis, simulation and design of tensegrity robots. These tools, along with new control methodologies and the modular hardware components developed to validate them, are presented as a system for the design of actuated tensegrity structures. As evidenced from their appearance in many biological systems, tensegrity (‘tensile–integrity’) structures have unique physical properties that make them ideal for interaction with uncertain environments. Yet, these characteristics make design and control of bioinspired tensegrity robots extremely challenging. This work presents the progress our tools have made in tackling the design and control challenges of spherical tensegrity structures. We focus on this shape since it lends itself to rolling locomotion. The results of our analyses include multiple novel control approaches for mobility and terrain interaction of spherical tensegrity structures that have been tested in simulation. A hardware prototype of a spherical six-bar tensegrity, the Reservoir Compliant Tensegrity Robot, is used to empirically validate the accuracy of simulation. PMID:24990292

Design and Control of Compliant Tensegrity Robots Through Simulation and Hardware Validation

NASA Technical Reports Server (NTRS)

Caluwaerts, Ken; Despraz, Jeremie; Iscen, Atil; Sabelhaus, Andrew P.; Bruce, Jonathan; Schrauwen, Benjamin; Sunspiral, Vytas

2014-01-01

To better understand the role of tensegrity structures in biological systems and their application to robotics, the Dynamic Tensegrity Robotics Lab at NASA Ames Research Center has developed and validated two different software environments for the analysis, simulation, and design of tensegrity robots. These tools, along with new control methodologies and the modular hardware components developed to validate them, are presented as a system for the design of actuated tensegrity structures. As evidenced from their appearance in many biological systems, tensegrity ("tensile-integrity") structures have unique physical properties which make them ideal for interaction with uncertain environments. Yet these characteristics, such as variable structural compliance, and global multi-path load distribution through the tension network, make design and control of bio-inspired tensegrity robots extremely challenging. This work presents the progress in using these two tools in tackling the design and control challenges. The results of this analysis includes multiple novel control approaches for mobility and terrain interaction of spherical tensegrity structures. The current hardware prototype of a six-bar tensegrity, code-named ReCTeR, is presented in the context of this validation.

Process of videotape making: presentation design, software, and hardware

NASA Astrophysics Data System (ADS)

Dickinson, Robert R.; Brady, Dan R.; Bennison, Tim; Burns, Thomas; Pines, Sheldon

1991-06-01

The use of technical video tape presentations for communicating abstractions of complex data is now becoming commonplace. While the use of video tapes in the day-to-day work of scientists and engineers is still in its infancy, their use as applications oriented conferences is now growing rapidly. Despite these advancements, there is still very little that is written down about the process of making technical videotapes. For printed media, different presentation styles are well known for categories such as results reports, executive summary reports, and technical papers and articles. In this paper, the authors present ideas on the topic of technical videotape presentation design in a format that is worth referring to. They have started to document the ways in which the experience of media specialist, teaching professionals, and character animators can be applied to scientific animation. Software and hardware considerations are also discussed. For this portion, distinctions are drawn between the software and hardware required for computer animation (frame at a time) productions, and live recorded interaction with a computer graphics display.

Interim Service ISDN Satellite (ISIS) hardware experiment design for advanced ISDN satellite design and experiments

NASA Technical Reports Server (NTRS)

Pepin, Gerard R.

1992-01-01

The Interim Service Integrated Services Digital Network (ISDN) Satellite (ISIS) Hardware Experiment Design for Advanced Satellite Designs describes the design of the ISDN Satellite Terminal Adapter (ISTA) capable of translating ISDN protocol traffic into time division multiple access (TDMA) signals for use by a communications satellite. The ISTA connects the Type 1 Network Termination (NT1) via the U-interface on the line termination side of the CPE to the V.35 interface for satellite uplink. The same ISTA converts in the opposite direction the V.35 to U-interface data with a simple switch setting.

Test Hardware Design for Flightlike Operation of Advanced Stirling Convertors (ASC-E3)

NASA Technical Reports Server (NTRS)

Oriti, Salvatore M.

2012-01-01

NASA Glenn Research Center (GRC) has been supporting development of the Advanced Stirling Radioisotope Generator (ASRG) since 2006. A key element of the ASRG project is providing life, reliability, and performance testing of the Advanced Stirling Convertor (ASC). For this purpose, the Thermal Energy Conversion branch at GRC has been conducting extended operation of a multitude of free-piston Stirling convertors. The goal of this effort is to generate long-term performance data (tens of thousands of hours) simultaneously on multiple units to build a life and reliability database. The test hardware for operation of these convertors was designed to permit in-air investigative testing, such as performance mapping over a range of environmental conditions. With this, there was no requirement to accurately emulate the flight hardware. For the upcoming ASC-E3 units, the decision has been made to assemble the convertors into a flight-like configuration. This means the convertors will be arranged in the dual-opposed configuration in a housing that represents the fit, form, and thermal function of the ASRG. The goal of this effort is to enable system level tests that could not be performed with the traditional test hardware at GRC. This offers the opportunity to perform these system-level tests much earlier in the ASRG flight development, as they would normally not be performed until fabrication of the qualification unit. This paper discusses the requirements, process, and results of this flight-like hardware design activity.

Magnesium Alloys for Space Hardware Design

NASA Technical Reports Server (NTRS)

Aroh, Joseph

2017-01-01

There have been advances in magnesium alloy development that NASA has not taken into consideration for space hardware because of a lack of test data. Magnesium alloys offer excellent weight reduction, specific strength, and deep space radiation mitigation. Traditionally, magnesium has been perceived as having too poor of a flammability resistance and corrosion resistance to be used for flight. Recent developments in magnesium alloying has led to the formation of two alloys, WE43 and Elektron 21, which are self-extinguishing and significantly less flammable because of their composition. Likewise, an anodizing process called Tagnite was formulated to deter any concern with galvanic and saltwater corrosion. The Materials Science Branch at Kennedy Space Center is currently researching these new alloys and treatments to better understand how they behave in the harsh environment of space. Successful completion of the proposed testing should result in a more thorough understanding of modern aerospace materials and processes, and possibly the permission to use magnesium alloys in future NASA designs.

Modular hardware synthesis using an HDL. [Hardware Description Language

NASA Technical Reports Server (NTRS)

Covington, J. A.; Shiva, S. G.

1981-01-01

Although hardware description languages (HDL) are becoming more and more necessary to automated design systems, their application is complicated due to the difficulty in translating the HDL description into an implementable format, nonfamiliarity of hardware designers with high-level language programming, nonuniform design methodologies and the time and costs involved in transfering HDL design software. Digital design language (DDL) suffers from all of the above problems and in addition can only by synthesized on a complete system and not on its subparts, making it unsuitable for synthesis using standard modules or prefabricated chips such as those required in LSI or VLSI circuits. The present paper presents a method by which the DDL translator can be made to generate modular equations that will allow the system to be synthesized as an interconnection of lower-level modules. The method involves the introduction of a new language construct called a Module which provides for the separate translation of all equations bounded by it.

Real-time distortion correction for visual inspection systems based on FPGA

NASA Astrophysics Data System (ADS)

Liang, Danhua; Zhang, Zhaoxia; Chen, Xiaodong; Yu, Daoyin

2008-03-01

Visual inspection is a kind of new technology based on the research of computer vision, which focuses on the measurement of the object's geometry and location. It can be widely used in online measurement, and other real-time measurement process. Because of the defects of the traditional visual inspection, a new visual detection mode -all-digital intelligent acquisition and transmission is presented. The image processing, including filtering, image compression, binarization, edge detection and distortion correction, can be completed in the programmable devices -FPGA. As the wide-field angle lens is adopted in the system, the output images have serious distortion. Limited by the calculating speed of computer, software can only correct the distortion of static images but not the distortion of dynamic images. To reach the real-time need, we design a distortion correction system based on FPGA. The method of hardware distortion correction is that the spatial correction data are calculated first under software circumstance, then converted into the address of hardware storage and stored in the hardware look-up table, through which data can be read out to correct gray level. The major benefit using FPGA is that the same circuit can be used for other circularly symmetric wide-angle lenses without being modified.

Design and control of compliant tensegrity robots through simulation and hardware validation.

PubMed

Caluwaerts, Ken; Despraz, Jérémie; Işçen, Atıl; Sabelhaus, Andrew P; Bruce, Jonathan; Schrauwen, Benjamin; SunSpiral, Vytas

2014-09-06

To better understand the role of tensegrity structures in biological systems and their application to robotics, the Dynamic Tensegrity Robotics Lab at NASA Ames Research Center, Moffett Field, CA, USA, has developed and validated two software environments for the analysis, simulation and design of tensegrity robots. These tools, along with new control methodologies and the modular hardware components developed to validate them, are presented as a system for the design of actuated tensegrity structures. As evidenced from their appearance in many biological systems, tensegrity ('tensile-integrity') structures have unique physical properties that make them ideal for interaction with uncertain environments. Yet, these characteristics make design and control of bioinspired tensegrity robots extremely challenging. This work presents the progress our tools have made in tackling the design and control challenges of spherical tensegrity structures. We focus on this shape since it lends itself to rolling locomotion. The results of our analyses include multiple novel control approaches for mobility and terrain interaction of spherical tensegrity structures that have been tested in simulation. A hardware prototype of a spherical six-bar tensegrity, the Reservoir Compliant Tensegrity Robot, is used to empirically validate the accuracy of simulation. © 2014 The Author(s) Published by the Royal Society. All rights reserved.

A preferential design approach for energy-efficient and robust implantable neural signal processing hardware.

PubMed

Narasimhan, Seetharam; Chiel, Hillel J; Bhunia, Swarup

2009-01-01

For implantable neural interface applications, it is important to compress data and analyze spike patterns across multiple channels in real time. Such a computational task for online neural data processing requires an innovative circuit-architecture level design approach for low-power, robust and area-efficient hardware implementation. Conventional microprocessor or Digital Signal Processing (DSP) chips would dissipate too much power and are too large in size for an implantable system. In this paper, we propose a novel hardware design approach, referred to as "Preferential Design" that exploits the nature of the neural signal processing algorithm to achieve a low-voltage, robust and area-efficient implementation using nanoscale process technology. The basic idea is to isolate the critical components with respect to system performance and design them more conservatively compared to the noncritical ones. This allows aggressive voltage scaling for low power operation while ensuring robustness and area efficiency. We have applied the proposed approach to a neural signal processing algorithm using the Discrete Wavelet Transform (DWT) and observed significant improvement in power and robustness over conventional design.

Satellite Communication Hardware Emulation System (SCHES)

NASA Technical Reports Server (NTRS)

Kaplan, Ted

1993-01-01

Satellite Communication Hardware Emulator System (SCHES) is a powerful simulator that emulates the hardware used in TDRSS links. SCHES is a true bit-by-bit simulator that models communications hardware accurately enough to be used as a verification mechanism for actual hardware tests on user spacecraft. As a credit to its modular design, SCHES is easily configurable to model any user satellite communication link, though some development may be required to tailor existing software to user specific hardware.

Modeling and Compensation Design for a Power Hardware-in-the-Loop Simulation of an AC Distribution System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ainsworth, Nathan; Hariri, Ali; Prabakar, Kumaraguru

Power hardware-in-the-loop (PHIL) simulation, where actual hardware under text is coupled with a real-time digital model in closed loop, is a powerful tool for analyzing new methods of control for emerging distributed power systems. However, without careful design and compensation of the interface between the simulated and actual systems, PHIL simulations may exhibit instability and modeling inaccuracies. This paper addresses issues that arise in the PHIL simulation of a hardware battery inverter interfaced with a simulated distribution feeder. Both the stability and accuracy issues are modeled and characterized, and a methodology for design of PHIL interface compensation to ensure stabilitymore » and accuracy is presented. The stability and accuracy of the resulting compensated PHIL simulation is then shown by experiment.« less

Door Hardware and Installations; Carpentry: 901894.

ERIC Educational Resources Information Center

Dade County Public Schools, Miami, FL.

The curriculum guide outlines a course designed to provide instruction in the selection, preparation, and installation of hardware for door assemblies. The course is divided into five blocks of instruction (introduction to doors and hardware, door hardware, exterior doors and jambs, interior doors and jambs, and a quinmester post-test) totaling…

AFOSR BRI: Co-Design of Hardware/Software for Predicting MAV Aerodynamics

DTIC Science & Technology

2016-09-27

DOCUMENTATION PAGE Form ApprovedOMB No. 0704-0188 1. REPORT DATE (DD-MM-YYYY) 2. REPORT TYPE 4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER 6. AUTHOR(S) 7...703-588-8494 AFOSR BRI While Moore’s Law theoretically doubles processor performance every 24 months, much of the realizable performance remains...past efforts to develop such CFD codes on accelerated processors showed limited success, our hardware/software co-design approach created malleable

Preliminary design of flight hardware for two-phase fluid research

NASA Technical Reports Server (NTRS)

Hustvedt, D. C.; Oonk, R. L.

1982-01-01

This study defined the preliminary designs of flight software for the Space Shuttle Orbiter for three two-phase fluid research experiments: (1) liquid reorientation - to study the motion of liquid in tanks subjected to small accelerations; (2) pool boiling - to study low-gravity boiling from horizontal cylinders; and (3) flow boiling - to study low-gravity forced flow boiling heat transfer and flow phenomena in a heated horizontal tube. The study consisted of eight major tasks: reassessment of the existing experiment designs, assessment of the Spacelab facility approach, assessment of the individual carry-on approach, selection of the preferred approach, preliminary design of flight hardware, safety analysis, preparation of a development plan, estimates of detailed design, fabrication and ground testing costs. The most cost effective design approach for the experiments is individual carry-ons in the Orbiter middeck. The experiments were designed to fit into one or two middeck lockers. Development schedules for the detailed design, fabrication and ground testing ranged from 15 1/2 to 18 months. Minimum costs (in 1981 dollars) ranged from $463K for the liquid reorientation experiment to $998K for the pool boiling experiment.

Formal hardware verification of digital circuits

NASA Technical Reports Server (NTRS)

Joyce, J.; Seger, C.-J.

1991-01-01

The use of formal methods to verify the correctness of digital circuits is less constrained by the growing complexity of digital circuits than conventional methods based on exhaustive simulation. This paper briefly outlines three main approaches to formal hardware verification: symbolic simulation, state machine analysis, and theorem-proving.

Modeling and Compensation Design for a Power Hardware-in-the-Loop Simulation of an AC Distribution System: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Prabakar, Kumaraguru; Ainsworth, Nathan; Pratt, Annabelle

Power hardware-in-the-loop (PHIL) simulation, where actual hardware under text is coupled with a real-time digital model in closed loop, is a powerful tool for analyzing new methods of control for emerging distributed power systems. However, without careful design and compensation of the interface between the simulated and actual systems, PHIL simulations may exhibit instability and modeling inaccuracies. This paper addresses issues that arise in the PHIL simulation of a hardware battery inverter interfaced with a simulated distribution feeder. Both the stability and accuracy issues are modeled and characterized, and a methodology for design of PHIL interface compensation to ensure stabilitymore » and accuracy is presented. The stability and accuracy of the resulting compensated PHIL simulation is then shown by experiment.« less

Design and test hardware for a solar array switching unit

NASA Technical Reports Server (NTRS)

Patil, A. R.; Cho, B. H.; Sable, D.; Lee, F. C.

1992-01-01

This paper describes the control of a pulse width modulated (PWM) type sequential shunt switching unit (SSU) for spacecraft applications. It is found that the solar cell output capacitance has a significant impact on SSU design. Shorting of this cell capacitance by the PWM switch causes input current surges. These surges are minimized by the use of a series filter inductor. The system with a filter is analyzed for ripple and the control to output-voltage transfer function. Stable closed loop design considerations are discussed. The results are supported by modeling and measurements of loop gain and of closed-loop bus impedance on test hardware for NASA's 120 V Earth Observation System (EOS). The analysis and modeling are also applicable to NASA's 160 V Space Station power system.

Modular implementation of a digital hardware design automation system

NASA Astrophysics Data System (ADS)

Masud, M.

An automation system based on AHPL (A Hardware Programming Language) was developed. The project may be divided into three distinct phases: (1) Upgrading of AHPL to make it more universally applicable; (2) Implementation of a compiler for the language; and (3) illustration of how the compiler may be used to support several phases of design activities. Several new features were added to AHPL. These include: application-dependent parameters, mutliple clocks, asynchronous results, functional registers and primitive functions. The new language, called Universal AHPL, has been defined rigorously. The compiler design is modular. The parsing is done by an automatic parser generated from the SLR(1)BNF grammar of the language. The compiler produces two data bases from the AHPL description of a circuit. The first one is a tabular representation of the circuit, and the second one is a detailed interconnection linked list. The two data bases provide a means to interface the compiler to application-dependent CAD systems.

Safe to Fly: Certifying COTS Hardware for Spaceflight

NASA Technical Reports Server (NTRS)

Fichuk, Jessica L.

2011-01-01

Providing hardware for the astronauts to use on board the Space Shuttle or International Space Station (ISS) involves a certification process that entails evaluating hardware safety, weighing risks, providing mitigation, and verifying requirements. Upon completion of this certification process, the hardware is deemed safe to fly. This process from start to finish can be completed as quickly as 1 week or can take several years in length depending on the complexity of the hardware and whether the item is a unique custom design. One area of cost and schedule savings that NASA implements is buying Commercial Off the Shelf (COTS) hardware and certifying it for human spaceflight as safe to fly. By utilizing commercial hardware, NASA saves time not having to develop, design and build the hardware from scratch, as well as a timesaving in the certification process. By utilizing COTS hardware, the current detailed certification process can be simplified which results in schedule savings. Cost savings is another important benefit of flying COTS hardware. Procuring COTS hardware for space use can be more economical than custom building the hardware. This paper will investigate the cost savings associated with certifying COTS hardware to NASA s standards rather than performing a custom build.

The DISCUS Hardware System,

DTIC Science & Technology

1982-07-01

blocks. DISCUS has no form of hardware synchronisation between the processors. The only synchronisation is at an operating system level. ;ach processor is... operations in global store so that semaphoring on global objects can be done correctly. Write Protect is used by the operating system for read-only...the appropriate operating system program. String Handling primitives . The Z8000 has a rich set of string primitives . However as we saw before if a

Object oriented design (OOD) in real-time hardware-in-the-loop (HWIL) simulations

NASA Astrophysics Data System (ADS)

Morris, Joe; Richard, Henri; Lowman, Alan; Youngren, Rob

2006-05-01

Using Object Oriented Design (OOD) concepts in AMRDEC's Hardware-in-the Loop (HWIL) real-time simulations allows the user to interchange parts of the simulation to meet test requirements. A large-scale three-spectral band simulator connected via a high speed reflective memory ring for time-critical data transfers to PC controllers connected by non real-time Ethernet protocols is used to separate software objects from logical entities close to their respective controlled hardware. Each standalone object does its own dynamic initialization, real-time processing, and end of run processing; therefore it can be easily maintained and updated. A Resource Allocation Program (RAP) is also utilized along with a device table to allocate, organize, and document the communication protocol between the software and hardware components. A GUI display program lists all allocations and deallocations of HWIL memory and hardware resources. This interactive program is also used to clean up defunct allocations of dead processes. Three examples are presented using the OOD and RAP concepts. The first is the control of an ACUTRONICS built three-axis flight table using the same control for calibration and real-time functions. The second is the transportability of a six-degree-of-freedom (6-DOF) simulation from an Onyx residence to a Linux-PC. The third is the replacement of the 6-DOF simulation with a replay program to drive the facility with archived run data for demonstration or analysis purposes.

Employing ISRU Models to Improve Hardware Design

NASA Technical Reports Server (NTRS)

Linne, Diane L.

2010-01-01

An analytical model for hydrogen reduction of regolith was used to investigate the effects of several key variables on the energy and mass performance of reactors for a lunar in-situ resource utilization oxygen production plant. Reactor geometry, reaction time, number of reactors, heat recuperation, heat loss, and operating pressure were all studied to guide hardware designers who are developing future prototype reactors. The effects of heat recuperation where the incoming regolith is pre-heated by the hot spent regolith before transfer was also investigated for the first time. In general, longer reaction times per batch provide a lower overall energy, but also result in larger and heavier reactors. Three reactors with long heat-up times results in similar energy requirements as a two-reactor system with all other parameters the same. Three reactors with heat recuperation results in energy reductions of 20 to 40 percent compared to a three-reactor system with no heat recuperation. Increasing operating pressure can provide similar energy reductions as heat recuperation for the same reaction times.

Skylab SO71/SO72 circadian periodicity experiment. [experimental design and checkout of hardware

NASA Technical Reports Server (NTRS)

Fairchild, M. K.; Hartmann, R. A.

1973-01-01

The circadian rhythm hardware activities from 1965 through 1973 are considered. A brief history of the programs leading to the development of the combined Skylab SO71/SO72 Circadian Periodicity Experiment (CPE) is given. SO71 is the Skylab experiment number designating the pocket mouse circadian experiment, and SO72 designates the vinegar gnat circadian experiment. Final design modifications and checkout of the CPE, integration testing with the Apollo service module CSM 117 and the launch preparation and support tasks at Kennedy Space Center are reported.

Radiation Mitigation and Power Optimization Design Tools for Reconfigurable Hardware in Orbit

NASA Technical Reports Server (NTRS)

French, Matthew; Graham, Paul; Wirthlin, Michael; Wang, Li; Larchev, Gregory

2005-01-01

The Reconfigurable Hardware in Orbit (RHinO)project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. In the second year of the project, design tools that leverage an established FPGA design environment have been created to visualize and analyze an FPGA circuit for radiation weaknesses and power inefficiencies. For radiation, a single event Upset (SEU) emulator, persistence analysis tool, and a half-latch removal tool for Xilinx/Virtex-II devices have been created. Research is underway on a persistence mitigation tool and multiple bit upsets (MBU) studies. For power, synthesis level dynamic power visualization and analysis tools have been completed. Power optimization tools are under development and preliminary test results are positive.

Event and Pulse Node Hardware Design for Nuclear Fusion Experiments

NASA Astrophysics Data System (ADS)

Fortunato, J. C.; Batista, A.; Sousa, J.; Fernandes, H.; Varandas, C. A. F.

2008-04-01

This article presents an event and pulse node hardware module (EPN) developed for use in control and data acquisition (CODAC) in current and upcoming long discharges nuclear fusion experiments. Its purpose is to allow real time event management and trigger distribution. The use of a mixture of digital signal processing and field programmable gate arrays, with fiber optic channels for event broadcast between CODAC nodes, and short length paths between the EPN and CODAC hardware, allows an effective and low latency communication path. This hardware will be integrated in the ISTTOK CODAC to allow long AC plasma discharges.

Automatic Digital Hardware Synthesis

DTIC Science & Technology

1990-09-01

VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate array (FPGAI using...process of translating VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate...allows the engineer to use VHDL to create and validate a design, and then to implement it in a gate array. The development of software o translate VHDL

The design and hardware implementation of a low-power real-time seizure detection algorithm

NASA Astrophysics Data System (ADS)

Raghunathan, Shriram; Gupta, Sumeet K.; Ward, Matthew P.; Worth, Robert M.; Roy, Kaushik; Irazoqui, Pedro P.

2009-10-01

Epilepsy affects more than 1% of the world's population. Responsive neurostimulation is emerging as an alternative therapy for the 30% of the epileptic patient population that does not benefit from pharmacological treatment. Efficient seizure detection algorithms will enable closed-loop epilepsy prostheses by stimulating the epileptogenic focus within an early onset window. Critically, this is expected to reduce neuronal desensitization over time and lead to longer-term device efficacy. This work presents a novel event-based seizure detection algorithm along with a low-power digital circuit implementation. Hippocampal depth-electrode recordings from six kainate-treated rats are used to validate the algorithm and hardware performance in this preliminary study. The design process illustrates crucial trade-offs in translating mathematical models into hardware implementations and validates statistical optimizations made with empirical data analyses on results obtained using a real-time functioning hardware prototype. Using quantitatively predicted thresholds from the depth-electrode recordings, the auto-updating algorithm performs with an average sensitivity and selectivity of 95.3 ± 0.02% and 88.9 ± 0.01% (mean ± SEα = 0.05), respectively, on untrained data with a detection delay of 8.5 s [5.97, 11.04] from electrographic onset. The hardware implementation is shown feasible using CMOS circuits consuming under 350 nW of power from a 250 mV supply voltage from simulations on the MIT 180 nm SOI process.

Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system

NASA Astrophysics Data System (ADS)

Ammendola, R.; Biagioni, A.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Rossetti, D.; Simula, F.; Tosoratto, L.; Vicini, P.

2015-12-01

In the attempt to develop an interconnection architecture optimized for hybrid HPC systems dedicated to scientific computing, we designed APEnet+, a point-to-point, low-latency and high-performance network controller supporting 6 fully bidirectional off-board links over a 3D torus topology. The first release of APEnet+ (named V4) was a board based on a 40 nm Altera FPGA, integrating 6 channels at 34 Gbps of raw bandwidth per direction and a PCIe Gen2 x8 host interface. It has been the first-of-its-kind device to implement an RDMA protocol to directly read/write data from/to Fermi and Kepler NVIDIA GPUs using NVIDIA peer-to-peer and GPUDirect RDMA protocols, obtaining real zero-copy GPU-to-GPU transfers over the network. The latest generation of APEnet+ systems (now named V5) implements a PCIe Gen3 x8 host interface on a 28 nm Altera Stratix V FPGA, with multi-standard fast transceivers (up to 14.4 Gbps) and an increased amount of configurable internal resources and hardware IP cores to support main interconnection standard protocols. Herein we present the APEnet+ V5 architecture, the status of its hardware and its system software design. Both its Linux Device Driver and the low-level libraries have been redeveloped to support the PCIe Gen3 protocol, introducing optimizations and solutions based on hardware/software co-design.

Design and implementation of encrypted and decrypted file system based on USBKey and hardware code

NASA Astrophysics Data System (ADS)

Wu, Kehe; Zhang, Yakun; Cui, Wenchao; Jiang, Ting

2017-05-01

To protect the privacy of sensitive data, an encrypted and decrypted file system based on USBKey and hardware code is designed and implemented in this paper. This system uses USBKey and hardware code to authenticate a user. We use random key to encrypt file with symmetric encryption algorithm and USBKey to encrypt random key with asymmetric encryption algorithm. At the same time, we use the MD5 algorithm to calculate the hash of file to verify its integrity. Experiment results show that large files can be encrypted and decrypted in a very short time. The system has high efficiency and ensures the security of documents.

NASA HUNCH Hardware

NASA Technical Reports Server (NTRS)

Hall, Nancy R.; Wagner, James; Phelps, Amanda

2014-01-01

What is NASA HUNCH? High School Students United with NASA to Create Hardware-HUNCH is an instructional partnership between NASA and educational institutions. This partnership benefits both NASA and students. NASA receives cost-effective hardware and soft goods, while students receive real-world hands-on experiences. The 2014-2015 was the 12th year of the HUNCH Program. NASA Glenn Research Center joined the program that already included the NASA Johnson Space Flight Center, Marshall Space Flight Center, Langley Research Center and Goddard Space Flight Center. The program included 76 schools in 24 states and NASA Glenn worked with the following five schools in the HUNCH Build to Print Hardware Program: Medina Career Center, Medina, OH; Cattaraugus Allegheny-BOCES, Olean, NY; Orleans Niagara-BOCES, Medina, NY; Apollo Career Center, Lima, OH; Romeo Engineering and Tech Center, Washington, MI. The schools built various parts of an International Space Station (ISS) middeck stowage locker and learned about manufacturing process and how best to build these components to NASA specifications. For the 2015-2016 school year the schools will be part of a larger group of schools building flight hardware consisting of 20 ISS middeck stowage lockers for the ISS Program. The HUNCH Program consists of: Build to Print Hardware; Build to Print Soft Goods; Design and Prototyping; Culinary Challenge; Implementation: Web Page and Video Production.

Hardware accelerator design for change detection in smart camera

NASA Astrophysics Data System (ADS)

Singh, Sanjay; Dunga, Srinivasa Murali; Saini, Ravi; Mandal, A. S.; Shekhar, Chandra; Chaudhury, Santanu; Vohra, Anil

2011-10-01

Smart Cameras are important components in Human Computer Interaction. In any remote surveillance scenario, smart cameras have to take intelligent decisions to select frames of significant changes to minimize communication and processing overhead. Among many of the algorithms for change detection, one based on clustering based scheme was proposed for smart camera systems. However, such an algorithm could achieve low frame rate far from real-time requirements on a general purpose processors (like PowerPC) available on FPGAs. This paper proposes the hardware accelerator capable of detecting real time changes in a scene, which uses clustering based change detection scheme. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA board. Resulted frame rate is 30 frames per second for QVGA resolution in gray scale.

VLSI realization of learning vector quantization with hardware/software co-design for different applications

NASA Astrophysics Data System (ADS)

An, Fengwei; Akazawa, Toshinobu; Yamasaki, Shogo; Chen, Lei; Jürgen Mattausch, Hans

2015-04-01

This paper reports a VLSI realization of learning vector quantization (LVQ) with high flexibility for different applications. It is based on a hardware/software (HW/SW) co-design concept for on-chip learning and recognition and designed as a SoC in 180 nm CMOS. The time consuming nearest Euclidean distance search in the LVQ algorithm’s competition layer is efficiently implemented as a pipeline with parallel p-word input. Since neuron number in the competition layer, weight values, input and output number are scalable, the requirements of many different applications can be satisfied without hardware changes. Classification of a d-dimensional input vector is completed in n × \\lceil d/p \\rceil + R clock cycles, where R is the pipeline depth, and n is the number of reference feature vectors (FVs). Adjustment of stored reference FVs during learning is done by the embedded 32-bit RISC CPU, because this operation is not time critical. The high flexibility is verified by the application of human detection with different numbers for the dimensionality of the FVs.

A CLIPS based personal computer hardware diagnostic system

NASA Technical Reports Server (NTRS)

Whitson, George M.

1991-01-01

Often the person designated to repair personal computers has little or no knowledge of how to repair a computer. Described here is a simple expert system to aid these inexperienced repair people. The first component of the system leads the repair person through a number of simple system checks such as making sure that all cables are tight and that the dip switches are set correctly. The second component of the system assists the repair person in evaluating error codes generated by the computer. The final component of the system applies a large knowledge base to attempt to identify the component of the personal computer that is malfunctioning. We have implemented and tested our design with a full system to diagnose problems for an IBM compatible system based on the 8088 chip. In our tests, the inexperienced repair people found the system very useful in diagnosing hardware problems.

A hardware-algorithm co-design approach to optimize seizure detection algorithms for implantable applications.

PubMed

Raghunathan, Shriram; Gupta, Sumeet K; Markandeya, Himanshu S; Roy, Kaushik; Irazoqui, Pedro P

2010-10-30

Implantable neural prostheses that deliver focal electrical stimulation upon demand are rapidly emerging as an alternate therapy for roughly a third of the epileptic patient population that is medically refractory. Seizure detection algorithms enable feedback mechanisms to provide focally and temporally specific intervention. Real-time feasibility and computational complexity often limit most reported detection algorithms to implementations using computers for bedside monitoring or external devices communicating with the implanted electrodes. A comparison of algorithms based on detection efficacy does not present a complete picture of the feasibility of the algorithm with limited computational power, as is the case with most battery-powered applications. We present a two-dimensional design optimization approach that takes into account both detection efficacy and hardware cost in evaluating algorithms for their feasibility in an implantable application. Detection features are first compared for their ability to detect electrographic seizures from micro-electrode data recorded from kainate-treated rats. Circuit models are then used to estimate the dynamic and leakage power consumption of the compared features. A score is assigned based on detection efficacy and the hardware cost for each of the features, then plotted on a two-dimensional design space. An optimal combination of compared features is used to construct an algorithm that provides maximal detection efficacy per unit hardware cost. The methods presented in this paper would facilitate the development of a common platform to benchmark seizure detection algorithms for comparison and feasibility analysis in the next generation of implantable neuroprosthetic devices to treat epilepsy. Copyright © 2010 Elsevier B.V. All rights reserved.

Computer hardware description languages - A tutorial

NASA Technical Reports Server (NTRS)

Shiva, S. G.

1979-01-01

The paper introduces hardware description languages (HDL) as useful tools for hardware design and documentation. The capabilities and limitations of HDLs are discussed along with the guidelines needed in selecting an appropriate HDL. The directions for future work are provided and attention is given to the implementation of HDLs in microcomputers.

Programming time-multiplexed reconfigurable hardware using a scalable neuromorphic compiler.

PubMed

Minkovich, Kirill; Srinivasa, Narayan; Cruz-Albrecht, Jose M; Cho, Youngkwan; Nogin, Aleksey

2012-06-01

Scalability and connectivity are two key challenges in designing neuromorphic hardware that can match biological levels. In this paper, we describe a neuromorphic system architecture design that addresses an approach to meet these challenges using traditional complementary metal-oxide-semiconductor (CMOS) hardware. A key requirement in realizing such neural architectures in hardware is the ability to automatically configure the hardware to emulate any neural architecture or model. The focus for this paper is to describe the details of such a programmable front-end. This programmable front-end is composed of a neuromorphic compiler and a digital memory, and is designed based on the concept of synaptic time-multiplexing (STM). The neuromorphic compiler automatically translates any given neural architecture to hardware switch states and these states are stored in digital memory to enable desired neural architectures. STM enables our proposed architecture to address scalability and connectivity using traditional CMOS hardware. We describe the details of the proposed design and the programmable front-end, and provide examples to illustrate its capabilities. We also provide perspectives for future extensions and potential applications.

Applying a Genetic Algorithm to Reconfigurable Hardware

NASA Technical Reports Server (NTRS)

Wells, B. Earl; Weir, John; Trevino, Luis; Patrick, Clint; Steincamp, Jim

2004-01-01

This paper investigates the feasibility of applying genetic algorithms to solve optimization problems that are implemented entirely in reconfgurable hardware. The paper highlights the pe$ormance/design space trade-offs that must be understood to effectively implement a standard genetic algorithm within a modem Field Programmable Gate Array, FPGA, reconfgurable hardware environment and presents a case-study where this stochastic search technique is applied to standard test-case problems taken from the technical literature. In this research, the targeted FPGA-based platform and high-level design environment was the Starbridge Hypercomputing platform, which incorporates multiple Xilinx Virtex II FPGAs, and the Viva TM graphical hardware description language.

Design-for-Hardware-Trust Techniques, Detection Strategies and Metrics for Hardware Trojans

DTIC Science & Technology

2015-12-14

down  both  rising  and  falling  transitions.  For  Trojan   detection ,   one   fault ,   slow-­‐to-­‐rise  or   slow-­‐to...in Jan. 2016. Through the course of this project we developed novel hardware Trojan detection techniques based on clock sweeping. The technique takes...algorithms to detect minor changes due to Trojan and compared them with those changes made by process variations. This technique was implemented on

Thermal Hardware for the Thermal Analyst

NASA Technical Reports Server (NTRS)

Steinfeld, David

2015-01-01

The presentation will be given at the 26th Annual Thermal Fluids Analysis Workshop (TFAWS 2015) hosted by the Goddard Space Flight Center (GSFC) Thermal Engineering Branch (Code 545). NCTS 21070-1. Most Thermal analysts do not have a good background into the hardware which thermally controls the spacecraft they design. SINDA and Thermal Desktop models are nice, but knowing how this applies to the actual thermal hardware (heaters, thermostats, thermistors, MLI blanketing, optical coatings, etc...) is just as important. The course will delve into the thermal hardware and their application techniques on actual spacecraft. Knowledge of how thermal hardware is used and applied will make a thermal analyst a better engineer.

Development of Hardware-in-the-Loop Simulation Based on Gazebo and Pixhawk for Unmanned Aerial Vehicles

NASA Astrophysics Data System (ADS)

Nguyen, Khoa Dang; Ha, Cheolkeun

2018-04-01

Hardware-in-the-loop simulation (HILS) is well known as an effective approach in the design of unmanned aerial vehicles (UAV) systems, enabling engineers to test the control algorithm on a hardware board with a UAV model on the software. Performance of HILS is determined by performances of the control algorithm, the developed model, and the signal transfer between the hardware and software. The result of HILS is degraded if any signal could not be transferred to the correct destination. Therefore, this paper aims to develop a middleware software to secure communications in HILS system for testing the operation of a quad-rotor UAV. In our HILS, the Gazebo software is used to generate a nonlinear six-degrees-of-freedom (6DOF) model, sensor model, and 3D visualization for the quad-rotor UAV. Meanwhile, the flight control algorithm is designed and implemented on the Pixhawk hardware. New middleware software, referred to as the control application software (CAS), is proposed to ensure the connection and data transfer between Gazebo and Pixhawk using the multithread structure in Qt Creator. The CAS provides a graphical user interface (GUI), allowing the user to monitor the status of packet transfer, and perform the flight control commands and the real-time tuning parameters for the quad-rotor UAV. Numerical implementations have been performed to prove the effectiveness of the middleware software CAS suggested in this paper.

Space Station Freedom biomedical monitoring and countermeasures: Biomedical facility hardware catalog

NASA Technical Reports Server (NTRS)

1990-01-01

This hardware catalog covers that hardware proposed under the Biomedical Monitoring and Countermeasures Development Program supported by the Johnson Space Center. The hardware items are listed separately by item, and are in alphabetical order. Each hardware item specification consists of four pages. The first page describes background information with an illustration, definition and a history/design status. The second page identifies the general specifications, performance, rack interface requirements, problems, issues, concerns, physical description, and functional description. The level of hardware design reliability is also identified under the maintainability and reliability category. The third page specifies the mechanical design guidelines and assumptions. Described are the material types and weights, modules, and construction methods. Also described is an estimation of percentage of construction which utilizes a particular method, and the percentage of required new mechanical design is documented. The fourth page analyzes the electronics, the scope of design effort, and the software requirements. Electronics are described by percentages of component types and new design. The design effort, as well as, the software requirements are identified and categorized.

Hardware development process for Human Research facility applications

NASA Astrophysics Data System (ADS)

Bauer, Liz

2000-01-01

The simple goal of the Human Research Facility (HRF) is to conduct human research experiments on the International Space Station (ISS) astronauts during long-duration missions. This is accomplished by providing integration and operation of the necessary hardware and software capabilities. A typical hardware development flow consists of five stages: functional inputs and requirements definition, market research, design life cycle through hardware delivery, crew training, and mission support. The purpose of this presentation is to guide the audience through the early hardware development process: requirement definition through selecting a development path. Specific HRF equipment is used to illustrate the hardware development paths. .

Combined Cycle Engine Large-Scale Inlet for Mode Transition Experiments: System Identification Rack Hardware Design

NASA Technical Reports Server (NTRS)

Thomas, Randy; Stueber, Thomas J.

2013-01-01

The System Identification (SysID) Rack is a real-time hardware-in-the-loop data acquisition (DAQ) and control instrument rack that was designed and built to support inlet testing in the NASA Glenn Research Center 10- by 10-Foot Supersonic Wind Tunnel. This instrument rack is used to support experiments on the Combined-Cycle Engine Large-Scale Inlet for Mode Transition Experiment (CCE? LIMX). The CCE?LIMX is a testbed for an integrated dual flow-path inlet configuration with the two flow paths in an over-and-under arrangement such that the high-speed flow path is located below the lowspeed flow path. The CCE?LIMX includes multiple actuators that are designed to redirect airflow from one flow path to the other; this action is referred to as "inlet mode transition." Multiple phases of experiments have been planned to support research that investigates inlet mode transition: inlet characterization (Phase-1) and system identification (Phase-2). The SysID Rack hardware design met the following requirements to support Phase-1 and Phase-2 experiments: safely and effectively move multiple actuators individually or synchronously; sample and save effector control and position sensor feedback signals; automate control of actuator positioning based on a mode transition schedule; sample and save pressure sensor signals; and perform DAQ and control processes operating at 2.5 KHz. This document describes the hardware components used to build the SysID Rack including their function, specifications, and system interface. Furthermore, provided in this document are a SysID Rack effectors signal list (signal flow); system identification experiment setup; illustrations indicating a typical SysID Rack experiment; and a SysID Rack performance overview for Phase-1 and Phase-2 experiments. The SysID Rack described in this document was a useful tool to meet the project objectives.

Optimal proximity correction: application for flash memory design

NASA Astrophysics Data System (ADS)

Chen, Y. O.; Huang, D. L.; Sung, K. T.; Chiang, J. J.; Yu, M.; Teng, F.; Chu, Lung; Rey, Juan C.; Bernard, Douglas A.; Li, Jiangwei; Li, Junling; Moroz, V.; Boksha, Victor V.

1998-06-01

Proximity Correction is the technology for which the most of IC manufacturers are committed already. The final intended result of correction is affected by many factors other than the optical characteristics of the mask-stepper system, such as photoresist exposure, post-exposure bake and development parameters, etch selectivity and anisotropy, and underlying topography. The most advanced industry and research groups already reported immediate need to consider wafer topography as one of the major components during a Proximity Correction procedure. In the present work we are discussing the corners rounding effect (which eventually cause electrical leakage) observed for the elements of Poly2 layer for a Flash Memory Design. It was found that the rounding originated by three- dimensional effects due to variation of photoresist thickness resulting from the non-planar substrate. Our major goal was to understand the reasons and correct corner rounding. As a result of this work highly effective layout correction methodology was demonstrated and manufacturable Depth Of Focus was achieved. Another purpose of the work was to demonstrate complete integration flow for a Flash Memory Design based on photolithography; deposition/etch; ion implantation/oxidation/diffusion; and device simulators.

Optimal two-stage enrichment design correcting for biomarker misclassification.

PubMed

Zang, Yong; Guo, Beibei

2018-01-01

The enrichment design is an important clinical trial design to detect the treatment effect of the molecularly targeted agent (MTA) in personalized medicine. Under this design, patients are stratified into marker-positive and marker-negative subgroups based on their biomarker statuses and only the marker-positive patients are enrolled into the trial and randomized to receive either the MTA or a standard treatment. As the biomarker plays a key role in determining the enrollment of the trial, a misclassification of the biomarker can induce substantial bias, undermine the integrity of the trial, and seriously affect the treatment evaluation. In this paper, we propose a two-stage optimal enrichment design that utilizes the surrogate marker to correct for the biomarker misclassification. The proposed design is optimal in the sense that it maximizes the probability of correctly classifying each patient's biomarker status based on the surrogate marker information. In addition, after analytically deriving the bias caused by the biomarker misclassification, we develop a likelihood ratio test based on the EM algorithm to correct for such bias. We conduct comprehensive simulation studies to investigate the operating characteristics of the optimal design and the results confirm the desirable performance of the proposed design.

Functional design specification for the problem data system. [space shuttle

NASA Technical Reports Server (NTRS)

Boatman, T. W.

1975-01-01

The purpose of the Functional Design Specification is to outline the design for the Problem Data System. The Problem Data System is a computer-based data management system designed to track the status of problems and corrective actions pertinent to space shuttle hardware.

Facilitating preemptive hardware system design using partial reconfiguration techniques.

PubMed

Dondo Gazzano, Julio; Rincon, Fernando; Vaderrama, Carlos; Villanueva, Felix; Caba, Julian; Lopez, Juan Carlos

2014-01-01

In FPGA-based control system design, partial reconfiguration is especially well suited to implement preemptive systems. In real-time systems, the deadline for critical task can compel the preemption of noncritical one. Besides, an asynchronous event can demand immediate attention and, then, force launching a reconfiguration process for high-priority task implementation. If the asynchronous event is previously scheduled, an explicit activation of the reconfiguration process is performed. If the event cannot be previously programmed, such as in dynamically scheduled systems, an implicit activation to the reconfiguration process is demanded. This paper provides a hardware-based approach to explicit and implicit activation of the partial reconfiguration process in dynamically reconfigurable SoCs and includes all the necessary tasks to cope with this issue. Furthermore, the reconfiguration service introduced in this work allows remote invocation of the reconfiguration process and then the remote integration of off-chip components. A model that offers component location transparency is also presented to enhance and facilitate system integration.

Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques

PubMed Central

Rincon, Fernando; Vaderrama, Carlos; Villanueva, Felix; Caba, Julian; Lopez, Juan Carlos

2014-01-01

In FPGA-based control system design, partial reconfiguration is especially well suited to implement preemptive systems. In real-time systems, the deadline for critical task can compel the preemption of noncritical one. Besides, an asynchronous event can demand immediate attention and, then, force launching a reconfiguration process for high-priority task implementation. If the asynchronous event is previously scheduled, an explicit activation of the reconfiguration process is performed. If the event cannot be previously programmed, such as in dynamically scheduled systems, an implicit activation to the reconfiguration process is demanded. This paper provides a hardware-based approach to explicit and implicit activation of the partial reconfiguration process in dynamically reconfigurable SoCs and includes all the necessary tasks to cope with this issue. Furthermore, the reconfiguration service introduced in this work allows remote invocation of the reconfiguration process and then the remote integration of off-chip components. A model that offers component location transparency is also presented to enhance and facilitate system integration. PMID:24672292

Design study of Software-Implemented Fault-Tolerance (SIFT) computer

NASA Technical Reports Server (NTRS)

Wensley, J. H.; Goldberg, J.; Green, M. W.; Kutz, W. H.; Levitt, K. N.; Mills, M. E.; Shostak, R. E.; Whiting-Okeefe, P. M.; Zeidler, H. M.

1982-01-01

Software-implemented fault tolerant (SIFT) computer design for commercial aviation is reported. A SIFT design concept is addressed. Alternate strategies for physical implementation are considered. Hardware and software design correctness is addressed. System modeling and effectiveness evaluation are considered from a fault-tolerant point of view.

The Application of Acoustic Measurements and Audio Recordings for Diagnosis of In-Flight Hardware Anomalies

NASA Technical Reports Server (NTRS)

Welsh, David; Denham, Samuel; Allen, Christopher

2011-01-01

In many cases, an initial symptom of hardware malfunction is unusual or unexpected acoustic noise. Many industries such as automotive, heating and air conditioning, and petro-chemical processing use noise and vibration data along with rotating machinery analysis techniques to identify noise sources and correct hardware defects. The NASA/Johnson Space Center Acoustics Office monitors the acoustic environment of the International Space Station (ISS) through periodic sound level measurement surveys. Trending of the sound level measurement survey results can identify in-flight hardware anomalies. The crew of the ISS also serves as a "detection tool" in identifying unusual hardware noises; in these cases the spectral analysis of audio recordings made on orbit can be used to identify hardware defects that are related to rotating components such as fans, pumps, and compressors. In this paper, three examples of the use of sound level measurements and audio recordings for the diagnosis of in-flight hardware anomalies are discussed: identification of blocked inter-module ventilation (IMV) ducts, diagnosis of abnormal ISS Crew Quarters rack exhaust fan noise, and the identification and replacement of a defective flywheel assembly in the Treadmill with Vibration Isolation (TVIS) hardware. In each of these examples, crew time was saved by identifying the off nominal component or condition that existed and in directing in-flight maintenance activities to address and correct each of these problems.

COTD: Reference-free Hardware Trojan Detection in Gate-level Netlist

DTIC Science & Technology

2017-03-01

modern designs , the constraint of time- to-market window, and the cost restriction of final product highly drive the horizontal design process. The...third-party intellectual properties (3PIPs) are widely used while they expose a design to hardware Trojans (HTs) that may tamper with the design and...activated. Some work have investigated hardware Trojans in early design stages and several techniques have been proposed to study the switching

Development and characteristics of the hardware for Skylab experiment S015

NASA Technical Reports Server (NTRS)

Thirolf, R. G.

1975-01-01

Details are given regarding the hardware for the Skylab S015 experiment, which was designed to detect the effects of zero gravity on cell growth rates. Experience gained in hardware-related considerations is presented for use of researchers concerned with future research of this type and further study of the S015 results. Brief descriptions are given of the experiment hardware, the hardware configuration for the critical design review, the major configuration changes, the final configuration, and the postflight review and analysis. An appendix describes pertinent documentation, film, and hardware that are available to qualified researchers; sources for additional or special information are given.

The design of flight hardware: Organizational and technical ideas from the MITRE/WPI Shuttle Program

NASA Technical Reports Server (NTRS)

Looft, F. J.

1986-01-01

The Mitre Corporation of Bedford Mass. and the Worcester Polytechnic Institute are developing several experiments for a future Shuttle flight. Several design practices for the development of the electrical equipment for the flight hardware have been standardized. Some of the ideas are presented, not as hard and fast rules but rather in the interest of stimulating discussions for sharing such ideas.

Fifty Years of Observing Hardware and Human Behavior

NASA Technical Reports Server (NTRS)

McMann, Joe

2011-01-01

During this half-day workshop, Joe McMann presented the lessons learned during his 50 years of experience in both industry and government, which included all U.S. manned space programs, from Mercury to the ISS. He shared his thoughts about hardware and people and what he has learned from first-hand experience. Included were such topics as design, testing, design changes, development, failures, crew expectations, hardware, requirements, and meetings.

Sterilization of space hardware.

NASA Technical Reports Server (NTRS)

Pflug, I. J.

1971-01-01

Discussion of various techniques of sterilization of space flight hardware using either destructive heating or the action of chemicals. Factors considered in the dry-heat destruction of microorganisms include the effects of microbial water content, temperature, the physicochemical properties of the microorganism and adjacent support, and nature of the surrounding gas atmosphere. Dry-heat destruction rates of microorganisms on the surface, between mated surface areas, or buried in the solid material of space vehicle hardware are reviewed, along with alternative dry-heat sterilization cycles, thermodynamic considerations, and considerations of final sterilization-process design. Discussed sterilization chemicals include ethylene oxide, formaldehyde, methyl bromide, dimethyl sulfoxide, peracetic acid, and beta-propiolactone.

Designing an Ergonomically Correct CNC Workstation on a Shoe String Budget.

ERIC Educational Resources Information Center

Lightner, Stan

2001-01-01

Describes research to design and construct ergonomically correct work stations for Computer Numerical Control machine tools. By designing ergonomically correct work stations, industrial technology teachers help protect students from repetitive motion injuries. (Contains 12 references.) (JOW)

The Evolution of Exercise Hardware on ISS: Past, Present, and Future

NASA Technical Reports Server (NTRS)

Buxton, R. E.; Kalogera, K. L.; Hanson, A. M.

2017-01-01

During 16 years in low-Earth orbit, the suite of exercise hardware aboard the International Space Station (ISS) has matured significantly. Today, the countermeasure system supports an array of physical-training protocols and serves as an extensive research platform. Future hardware designs are required to have smaller operational envelopes and must also mitigate known physiologic issues observed in long-duration spaceflight. Taking lessons learned from the long history of space exercise will be important to successful development and implementation of future, compact exercise hardware. The evolution of exercise hardware as deployed on the ISS has implications for future exercise hardware and operations. Key lessons learned from the early days of ISS have helped to: 1. Enhance hardware performance (increased speed and loads). 2. Mature software interfaces. 3. Compare inflight exercise workloads to pre-, in-, and post-flight musculoskeletal and aerobic conditions. 4. Improve exercise comfort. 5. Develop complimentary hardware for research and operations. Current ISS exercise hardware includes both custom and commercial-off-the-shelf (COTS) hardware. Benefits and challenges to this approach have prepared engineering teams to take a hybrid approach when designing and implementing future exercise hardware. Significant effort has gone into consideration of hardware instrumentation and wearable devices that provide important data to monitor crew health and performance.

Human Centered Hardware Modeling and Collaboration

NASA Technical Reports Server (NTRS)

Stambolian Damon; Lawrence, Brad; Stelges, Katrine; Henderson, Gena

2013-01-01

In order to collaborate engineering designs among NASA Centers and customers, to in clude hardware and human activities from multiple remote locations, live human-centered modeling and collaboration across several sites has been successfully facilitated by Kennedy Space Center. The focus of this paper includes innovative a pproaches to engineering design analyses and training, along with research being conducted to apply new technologies for tracking, immersing, and evaluating humans as well as rocket, vehic le, component, or faci lity hardware utilizing high resolution cameras, motion tracking, ergonomic analysis, biomedical monitoring, wor k instruction integration, head-mounted displays, and other innovative human-system integration modeling, simulation, and collaboration applications.

Scalability, Timing, and System Design Issues for Intrinsic Evolvable Hardware

NASA Technical Reports Server (NTRS)

Hereford, James; Gwaltney, David

2004-01-01

In this paper we address several issues pertinent to intrinsic evolvable hardware (EHW). The first issue is scalability; namely, how the design space scales as the programming string for the programmable device gets longer. We develop a model for population size and the number of generations as a function of the programming string length, L, and show that the number of circuit evaluations is an O(L2) process. We compare our model to several successful intrinsic EHW experiments and discuss the many implications of our model. The second issue that we address is the timing of intrinsic EHW experiments. We show that the processing time is a small part of the overall time to derive or evolve a circuit and that major improvements in processor speed alone will have only a minimal impact on improving the scalability of intrinsic EHW. The third issue we consider is the system-level design of intrinsic EHW experiments. We review what other researchers have done to break the scalability barrier and contend that the type of reconfigurable platform and the evolutionary algorithm are tied together and impose limits on each other.

Energy efficient engine: Fan test hardware detailed design report

NASA Technical Reports Server (NTRS)

Sullivan, T. J.

1980-01-01

A single stage fan and quarter stage booster were designed for the energy efficient engine. The fan has an inlet radius ratio of 0.342 and a specific flow rate of 208.9 Kg/S sq m (42.8 lbm/sec sq ft). The fan rotor has 32 medium aspect ratio (2.597) titanium blades with a partspan shroud at 55% blade height. The design corrected fan tip speed is 411.5 M/S (1350 ft/sec). The quarter stage island splits the total fan flow with approximately 22% of the flow being supercharged by the quarter stage rotor. The fan bypass ratio is 6.8. The core flow total pressure ratio is 1.67 and the fan bypass pressure ratio is 1.65. The design details of the fan and booster blading, and the fan frame and static structure for the fan configuration are presented.

Simulation verification techniques study: Simulation self test hardware design and techniques report

NASA Technical Reports Server (NTRS)

1974-01-01

The final results are presented of the hardware verification task. The basic objectives of the various subtasks are reviewed along with the ground rules under which the overall task was conducted and which impacted the approach taken in deriving techniques for hardware self test. The results of the first subtask and the definition of simulation hardware are presented. The hardware definition is based primarily on a brief review of the simulator configurations anticipated for the shuttle training program. The results of the survey of current self test techniques are presented. The data sources that were considered in the search for current techniques are reviewed, and results of the survey are presented in terms of the specific types of tests that are of interest for training simulator applications. Specifically, these types of tests are readiness tests, fault isolation tests and incipient fault detection techniques. The most applicable techniques were structured into software flows that are then referenced in discussions of techniques for specific subsystems.

High-Speed Isolation Board for Flight Hardware Testing

NASA Technical Reports Server (NTRS)

Yamamoto, Clifford K.; Goodpasture, Richard L.

2011-01-01

There is a need to provide a portable and cost-effective galvanic isolation between ground support equipment and flight hardware such that any unforeseen voltage differential between ground and power supplies is eliminated. An interface board was designed for use between the ground support equipment and the flight hardware that electrically isolates all input and output signals and faithfully reproduces them on each side of the interface. It utilizes highly integrated multi-channel isolating devices to minimize size and reduce assembly time. This single-board solution provides appropriate connector hardware and breakout of required flight signals to individual connectors as needed for various ground support equipment. The board utilizes multi-channel integrated circuits that contain transformer coupling, thereby allowing input and output signals to be isolated from one another while still providing high-fidelity reproduction of the signal up to 90 MHz. The board also takes in a single-voltage power supply input from the ground support equipment and in turn provides a transformer-derived isolated voltage supply to power the portion of the circuitry that is electrically connected to the flight hardware. Prior designs used expensive opto-isolated couplers that were required for each signal to isolate and were time-consuming to assemble. In addition, these earlier designs were bulky and required a 2U rack-mount enclosure. The new design is smaller than a piece of 8.5 11-in. (.22 28-mm) paper and can be easily hand-carried where needed. The flight hardware in question is based on a lineage of existing software-defined radios (SDRs) that utilize a common interface connector with many similar input-output signals present. There are currently four to five variations of this SDR, and more upcoming versions are planned based on the more recent design.

Real-time lens distortion correction: speed, accuracy and efficiency

NASA Astrophysics Data System (ADS)

Bax, Michael R.; Shahidi, Ramin

2014-11-01

Optical lens systems suffer from nonlinear geometrical distortion. Optical imaging applications such as image-enhanced endoscopy and image-based bronchoscope tracking require correction of this distortion for accurate localization, tracking, registration, and measurement of image features. Real-time capability is desirable for interactive systems and live video. The use of a texture-mapping graphics accelerator, which is standard hardware on current motherboard chipsets and add-in video graphics cards, to perform distortion correction is proposed. Mesh generation for image tessellation, an error analysis, and performance results are presented. It is shown that distortion correction using commodity graphics hardware is substantially faster than using the main processor and can be performed at video frame rates (faster than 30 frames per second), and that the polar-based method of mesh generation proposed here is more accurate than a conventional grid-based approach. Using graphics hardware to perform distortion correction is not only fast and accurate but also efficient as it frees the main processor for other tasks, which is an important issue in some real-time applications.

FPS-RAM: Fast Prefix Search RAM-Based Hardware for Forwarding Engine

NASA Astrophysics Data System (ADS)

Zaitsu, Kazuya; Yamamoto, Koji; Kuroda, Yasuto; Inoue, Kazunari; Ata, Shingo; Oka, Ikuo

Ternary content addressable memory (TCAM) is becoming very popular for designing high-throughput forwarding engines on routers. However, TCAM has potential problems in terms of hardware and power costs, which limits its ability to deploy large amounts of capacity in IP routers. In this paper, we propose new hardware architecture for fast forwarding engines, called fast prefix search RAM-based hardware (FPS-RAM). We designed FPS-RAM hardware with the intent of maintaining the same search performance and physical user interface as TCAM because our objective is to replace the TCAM in the market. Our RAM-based hardware architecture is completely different from that of TCAM and has dramatically reduced the costs and power consumption to 62% and 52%, respectively. We implemented FPS-RAM on an FPGA to examine its lookup operation.

FPGA-Based Efficient Hardware/Software Co-Design for Industrial Systems with Consideration of Output Selection

NASA Astrophysics Data System (ADS)

Deliparaschos, Kyriakos M.; Michail, Konstantinos; Zolotas, Argyrios C.; Tzafestas, Spyros G.

2016-05-01

This work presents a field programmable gate array (FPGA)-based embedded software platform coupled with a software-based plant, forming a hardware-in-the-loop (HIL) that is used to validate a systematic sensor selection framework. The systematic sensor selection framework combines multi-objective optimization, linear-quadratic-Gaussian (LQG)-type control, and the nonlinear model of a maglev suspension. A robustness analysis of the closed-loop is followed (prior to implementation) supporting the appropriateness of the solution under parametric variation. The analysis also shows that quantization is robust under different controller gains. While the LQG controller is implemented on an FPGA, the physical process is realized in a high-level system modeling environment. FPGA technology enables rapid evaluation of the algorithms and test designs under realistic scenarios avoiding heavy time penalty associated with hardware description language (HDL) simulators. The HIL technique facilitates significant speed-up in the required execution time when compared to its software-based counterpart model.

VME rollback hardware for time warp multiprocessor systems

NASA Technical Reports Server (NTRS)

Robb, Michael J.; Buzzell, Calvin A.

1992-01-01

The purpose of the research effort is to develop and demonstrate innovative hardware to implement specific rollback and timing functions required for efficient queue management and precision timekeeping in multiprocessor discrete event simulations. The previously completed phase 1 effort demonstrated the technical feasibility of building hardware modules which eliminate the state saving overhead of the Time Warp paradigm used in distributed simulations on multiprocessor systems. The current phase 2 effort will build multiple pre-production rollback hardware modules integrated with a network of Sun workstations, and the integrated system will be tested by executing a Time Warp simulation. The rollback hardware will be designed to interface with the greatest number of multiprocessor systems possible. The authors believe that the rollback hardware will provide for significant speedup of large scale discrete event simulation problems and allow multiprocessors using Time Warp to dramatically increase performance.

Choice of word length in the design of a specialized hardware for lossless wavelet compression of medical images

NASA Astrophysics Data System (ADS)

Urriza, Isidro; Barragan, Luis A.; Artigas, Jose I.; Garcia, Jose I.; Navarro, Denis

1997-11-01

Image compression plays an important role in the archiving and transmission of medical images. Discrete cosine transform (DCT)-based compression methods are not suitable for medical images because of block-like image artifacts that could mask or be mistaken for pathology. Wavelet transforms (WTs) are used to overcome this problem. When implementing WTs in hardware, finite precision arithmetic introduces quantization errors. However, lossless compression is usually required in the medical image field. Thus, the hardware designer must look for the optimum register length that, while ensuring the lossless accuracy criteria, will also lead to a high-speed implementation with small chip area. In addition, wavelet choice is a critical issue that affects image quality as well as system design. We analyze the filters best suited to image compression that appear in the literature. For them, we obtain the maximum quantization errors produced in the calculation of the WT components. Thus, we deduce the minimum word length required for the reconstructed image to be numerically identical to the original image. The theoretical results are compared with experimental results obtained from algorithm simulations on random test images. These results enable us to compare the hardware implementation cost of the different filter banks. Moreover, to reduce the word length, we have analyzed the case of increasing the integer part of the numbers while maintaining constant the word length when the scale increases.

Design and evaluation of a fault-tolerant multiprocessor using hardware recovery blocks

NASA Technical Reports Server (NTRS)

Lee, Y. H.; Shin, K. G.

1982-01-01

A fault-tolerant multiprocessor with a rollback recovery mechanism is discussed. The rollback mechanism is based on the hardware recovery block which is a hardware equivalent to the software recovery block. The hardware recovery block is constructed by consecutive state-save operations and several state-save units in every processor and memory module. When a fault is detected, the multiprocessor reconfigures itself to replace the faulty component and then the process originally assigned to the faulty component retreats to one of the previously saved states in order to resume fault-free execution. A mathematical model is proposed to calculate both the coverage of multi-step rollback recovery and the risk of restart. A performance evaluation in terms of task execution time is also presented.

Monitoring and Hardware Management for Critical Fusion Plasma Instrumentation

NASA Astrophysics Data System (ADS)

Carvalho, Paulo F.; Santos, Bruno; Correia, Miguel; Combo, Álvaro M.; Rodrigues, AntÓnio P.; Pereira, Rita C.; Fernandes, Ana; Cruz, Nuno; Sousa, Jorge; Carvalho, Bernardo B.; Batista, AntÓnio J. N.; Correia, Carlos M. B. A.; Gonçalves, Bruno

2018-01-01

Controlled nuclear fusion aims to obtain energy by particles collision confined inside a nuclear reactor (Tokamak). These ionized particles, heavier isotopes of hydrogen, are the main elements inside of plasma that is kept at high temperatures (millions of Celsius degrees). Due to high temperatures and magnetic confinement, plasma is exposed to several sources of instabilities which require a set of procedures by the control and data acquisition systems throughout fusion experiments processes. Control and data acquisition systems often used in nuclear fusion experiments are based on the Advanced Telecommunication Computer Architecture (AdvancedTCA®) standard introduced by the Peripheral Component Interconnect Industrial Manufacturers Group (PICMG®), to meet the demands of telecommunications that require large amount of data (TB) transportation at high transfer rates (Gb/s), to ensure high availability including features such as reliability, serviceability and redundancy. For efficient plasma control, systems are required to collect large amounts of data, process it, store for later analysis, make critical decisions in real time and provide status reports either from the experience itself or the electronic instrumentation involved. Moreover, systems should also ensure the correct handling of detected anomalies and identified faults, notify the system operator of occurred events, decisions taken to acknowledge and implemented changes. Therefore, for everything to work in compliance with specifications it is required that the instrumentation includes hardware management and monitoring mechanisms for both hardware and software. These mechanisms should check the system status by reading sensors, manage events, update inventory databases with hardware system components in use and maintenance, store collected information, update firmware and installed software modules, configure and handle alarms to detect possible system failures and prevent emergency scenarios

Physics Model-Based Scatter Correction in Multi-Source Interior Computed Tomography.

PubMed

Gong, Hao; Li, Bin; Jia, Xun; Cao, Guohua

2018-02-01

Multi-source interior computed tomography (CT) has a great potential to provide ultra-fast and organ-oriented imaging at low radiation dose. However, X-ray cross scattering from multiple simultaneously activated X-ray imaging chains compromises imaging quality. Previously, we published two hardware-based scatter correction methods for multi-source interior CT. Here, we propose a software-based scatter correction method, with the benefit of no need for hardware modifications. The new method is based on a physics model and an iterative framework. The physics model was derived analytically, and was used to calculate X-ray scattering signals in both forward direction and cross directions in multi-source interior CT. The physics model was integrated to an iterative scatter correction framework to reduce scatter artifacts. The method was applied to phantom data from both Monte Carlo simulations and physical experimentation that were designed to emulate the image acquisition in a multi-source interior CT architecture recently proposed by our team. The proposed scatter correction method reduced scatter artifacts significantly, even with only one iteration. Within a few iterations, the reconstructed images fast converged toward the "scatter-free" reference images. After applying the scatter correction method, the maximum CT number error at the region-of-interests (ROIs) was reduced to 46 HU in numerical phantom dataset and 48 HU in physical phantom dataset respectively, and the contrast-noise-ratio at those ROIs increased by up to 44.3% and up to 19.7%, respectively. The proposed physics model-based iterative scatter correction method could be useful for scatter correction in dual-source or multi-source CT.

Acoustical Testing Laboratory Developed to Support the Low-Noise Design of Microgravity Space Flight Hardware

NASA Technical Reports Server (NTRS)

Cooper, Beth A.

2001-01-01

The NASA John H. Glenn Research Center at Lewis Field has designed and constructed an Acoustical Testing Laboratory to support the low-noise design of microgravity space flight hardware. This new laboratory will provide acoustic emissions testing and noise control services for a variety of customers, particularly for microgravity space flight hardware that must meet International Space Station limits on noise emissions. These limits have been imposed by the space station to support hearing conservation, speech communication, and safety goals as well as to prevent noise-induced vibrations that could impact microgravity research data. The Acoustical Testing Laboratory consists of a 23 by 27 by 20 ft (height) convertible hemi/anechoic chamber and separate sound-attenuating test support enclosure. Absorptive 34-in. fiberglass wedges in the test chamber provide an anechoic environment down to 100 Hz. A spring-isolated floor system affords vibration isolation above 3 Hz. These criteria, along with very low design background levels, will enable the acquisition of accurate and repeatable acoustical measurements on test articles, up to a full space station rack in size, that produce very little noise. Removable floor wedges will allow the test chamber to operate in either a hemi/anechoic or anechoic configuration, depending on the size of the test article and the specific test being conducted. The test support enclosure functions as a control room during normal operations but, alternatively, may be used as a noise-control enclosure for test articles that require the operation of noise-generating test support equipment.

Development of robotics facility docking test hardware

NASA Technical Reports Server (NTRS)

Loughead, T. E.; Winkler, R. V.

1984-01-01

Design and fabricate test hardware for NASA's George C. Marshall Space Flight Center (MSFC) are reported. A docking device conceptually developed was fabricated, and two docking targets which provide high and low mass docking loads were required and were represented by an aft 61.0 cm section of a Hubble space telescope (ST) mockup and an upgrading of an existing multimission modular spacecraft (MSS) mockup respectively. A test plan is developed for testing the hardware.

Reconfigurable Hardware for Compressing Hyperspectral Image Data

NASA Technical Reports Server (NTRS)

Aranki, Nazeeh; Namkung, Jeffrey; Villapando, Carlos; Kiely, Aaron; Klimesh, Matthew; Xie, Hua

2010-01-01

High-speed, low-power, reconfigurable electronic hardware has been developed to implement ICER-3D, an algorithm for compressing hyperspectral-image data. The algorithm and parts thereof have been the topics of several NASA Tech Briefs articles, including Context Modeler for Wavelet Compression of Hyperspectral Images (NPO-43239) and ICER-3D Hyperspectral Image Compression Software (NPO-43238), which appear elsewhere in this issue of NASA Tech Briefs. As described in more detail in those articles, the algorithm includes three main subalgorithms: one for computing wavelet transforms, one for context modeling, and one for entropy encoding. For the purpose of designing the hardware, these subalgorithms are treated as modules to be implemented efficiently in field-programmable gate arrays (FPGAs). The design takes advantage of industry- standard, commercially available FPGAs. The implementation targets the Xilinx Virtex II pro architecture, which has embedded PowerPC processor cores with flexible on-chip bus architecture. It incorporates an efficient parallel and pipelined architecture to compress the three-dimensional image data. The design provides for internal buffering to minimize intensive input/output operations while making efficient use of offchip memory. The design is scalable in that the subalgorithms are implemented as independent hardware modules that can be combined in parallel to increase throughput. The on-chip processor manages the overall operation of the compression system, including execution of the top-level control functions as well as scheduling, initiating, and monitoring processes. The design prototype has been demonstrated to be capable of compressing hyperspectral data at a rate of 4.5 megasamples per second at a conservative clock frequency of 50 MHz, with a potential for substantially greater throughput at a higher clock frequency. The power consumption of the prototype is less than 6.5 W. The reconfigurability (by means of reprogramming) of

RF control hardware design for CYCIAE-100 cyclotron

NASA Astrophysics Data System (ADS)

Yin, Zhiguo; Fu, Xiaoliang; Ji, Bin; Zhao, Zhenlu; Zhang, Tianjue; Li, Pengzhan; Wei, Junyi; Xing, Jiansheng; Wang, Chuan

2015-11-01

The Beijing Radioactive Ion-beam Facility project is being constructed by BRIF division of China Institute of Atomic Energy. In this project, a 100 MeV high intensity compact proton cyclotron is built for multiple applications. The first successful beam extraction of CYCIAE-100 cyclotron was done in the middle of 2014. The extracted proton beam energy is 100 MeV and the beam current is more than 20 μA. The RF system of the CYCIAE-100 cyclotron includes two half-wavelength cavities, two 100 kW tetrode amplifiers and power transmission line systems (all above are independent from each other) and two sets of Low Level RF control crates. Each set of LLRF control includes an amplitude control unit, a tuning control unit, a phase control unit, a local Digital Signal Process control unit and an Advanced RISC Machines based EPICS IOC unit. These two identical LLRF control crates share one common reference clock and take advantages of modern digital technologies (e.g. DSP and Direct Digital Synthesizer) to achieve closed loop voltage and phase regulations of the dee-voltage. In the beam commission, the measured dee-voltage stability of RF system is better than 0.1% and phase stability is better than 0.03°. The hardware design of the LLRF system will be reviewed in this paper.

Apollo Guidance, Navigation, and Control (GNC) Hardware Overview

NASA Technical Reports Server (NTRS)

Interbartolo, Michael

2009-01-01

This viewgraph presentation reviews basic guidance, navigation and control (GNC) concepts, examines the Command and Service Module (CSM) and Lunar Module (LM) GNC organization and discusses the primary GNC and the CSM Stabilization and Control System (SCS), as well as other CSM-specific hardware. The LM Abort Guidance System (AGS), Control Electronics System (CES) and other LM-specific hardware are also addressed. Three subsystems exist on each vehicle: the computer subsystem (CSS), the inertial subsystem (ISS) and the optical subsystem (OSS). The CSS and ISS are almost identical between CSM and LM and each is designed to operate independently. CSM SCS hardware are highlighted, including translation control, rotation controls, gyro assemblies, a gyro display coupler and flight director attitude indicators. The LM AGS hardware are also highlighted and include the abort electronics assembly and the abort sensor assembly; while the LM CES hardware includes the attitude controller assembly, thrust/translation controller assemblies and the ascent engine arming assemble. Other common hardware including the Orbital Rate Display - Earth and Lunar (ORDEAL) and the Crewman Optical Alignment Sight (COAS), a docking aid, are also highlighted.

A Comprehensive Reliability Methodology for Assessing Risk of Reusing Failed Hardware Without Corrective Actions with and Without Redundancy

NASA Technical Reports Server (NTRS)

Putcha, Chandra S.; Mikula, D. F. Kip; Dueease, Robert A.; Dang, Lan; Peercy, Robert L.

1997-01-01

This paper deals with the development of a reliability methodology to assess the consequences of using hardware, without failure analysis or corrective action, that has previously demonstrated that it did not perform per specification. The subject of this paper arose from the need to provide a detailed probabilistic analysis to calculate the change in probability of failures with respect to the base or non-failed hardware. The methodology used for the analysis is primarily based on principles of Monte Carlo simulation. The random variables in the analysis are: Maximum Time of Operation (MTO) and operation Time of each Unit (OTU) The failure of a unit is considered to happen if (OTU) is less than MTO for the Normal Operational Period (NOP) in which this unit is used. NOP as a whole uses a total of 4 units. Two cases are considered. in the first specialized scenario, the failure of any operation or system failure is considered to happen if any of the units used during the NOP fail. in the second specialized scenario, the failure of any operation or system failure is considered to happen only if any two of the units used during the MOP fail together. The probability of failure of the units and the system as a whole is determined for 3 kinds of systems - Perfect System, Imperfect System 1 and Imperfect System 2. in a Perfect System, the operation time of the failed unit is the same as that of the MTO. In an Imperfect System 1, the operation time of the failed unit is assumed as 1 percent of the MTO. In an Imperfect System 2, the operation time of the failed unit is assumed as zero. in addition, simulated operation time of failed units is assumed as 10 percent of the corresponding units before zero value. Monte Carlo simulation analysis is used for this study. Necessary software has been developed as part of this study to perform the reliability calculations. The results of the analysis showed that the predicted change in failure probability (P(sub F)) for the

Human-machine interface hardware: The next decade

NASA Technical Reports Server (NTRS)

Marcus, Elizabeth A.

1991-01-01

In order to understand where human-machine interface hardware is headed, it is important to understand where we are today, how we got there, and what our goals for the future are. As computers become more capable, faster, and programs become more sophisticated, it becomes apparent that the interface hardware is the key to an exciting future in computing. How can a user interact and control a seemingly limitless array of parameters effectively? Today, the answer is most often a limitless array of controls. The link between these controls and human sensory motor capabilities does not utilize existing human capabilities to their full extent. Interface hardware for teleoperation and virtual environments is now facing a crossroad in design. Therefore, we as developers need to explore how the combination of interface hardware, human capabilities, and user experience can be blended to get the best performance today and in the future.

Space Technology 5: Changing the Mission Design without Changing the Hardware

NASA Technical Reports Server (NTRS)

Carlisle, Candace C.; Webb, Evan H.; Slavin, James A.

2005-01-01

The Space Technology 5 (ST-5) Project is part of NASA's New Millennium Program. The validation objectives are to demonstrate the research-quality science capability of the ST-5 spacecraft; to operate the three spacecraft as a constellation; and to design, develop, test and flight-validate three capable micro-satellites with new technologies. A three-month flight demonstration phase is planned, beginning in March 2006. This year, the mission was re-planned for a Pegasus XL dedicated launch into an elliptical polar orbit (instead of the Originally-planned Geosynchronous Transfer Orbit.) The re-plan allows the mission to achieve the same high-level technology validation objectives with a different launch vehicle. The new mission design involves a revised science validation strategy, a new orbit and different communication strategy, while minimizing changes to the ST-5 spacecraft itself. The constellation operations concepts have also been refined. While the system engineers, orbit analysts, and operations teams were re-planning the mission, the implementation team continued to make progress on the flight hardware. Most components have been delivered, and the first spacecraft is well into integration and test.

Framework for Development and Distribution of Hardware Acceleration

NASA Astrophysics Data System (ADS)

Thomas, David B.; Luk, Wayne W.

2002-07-01

This paper describes IGOL, a framework for developing reconfigurable data processing applications. While IGOL was originally designed to target imaging and graphics systems, its structure is sufficiently general to support a broad range of applications. IGOL adopts a four-layer architecture: application layer, operation layer, appliance layer and configuration layer. This architecture is intended to separate and co-ordinate both the development and execution of hardware and software components. Hardware developers can use IGOL as an instance testbed for verification and benchmarking, as well as for distribution. Software application developers can use IGOL to discover hardware accelerated data processors, and to access them in a transparent, non-hardware specific manner. IGOL provides extensive support for the RC1000-PP board via the Handel-C language, and a wide selection of image processing filters have been developed. IGOL also supplies plug-ins to enable such filters to be incorporated in popular applications such as Premiere, Winamp, VirtualDub and DirectShow. Moreover, IGOL allows the automatic use of multiple cards to accelerate an application, demonstrated using DirectShow. To enable transparent acceleration without sacrificing performance, a three-tiered COM (Component Object Model) API has been designed and implemented. This API provides a well-defined and extensible interface which facilitates the development of hardware data processors that can accelerate multiple applications.

System-level protection and hardware Trojan detection using weighted voting.

PubMed

Amin, Hany A M; Alkabani, Yousra; Selim, Gamal M I

2014-07-01

The problem of hardware Trojans is becoming more serious especially with the widespread of fabless design houses and design reuse. Hardware Trojans can be embedded on chip during manufacturing or in third party intellectual property cores (IPs) during the design process. Recent research is performed to detect Trojans embedded at manufacturing time by comparing the suspected chip with a golden chip that is fully trusted. However, Trojan detection in third party IP cores is more challenging than other logic modules especially that there is no golden chip. This paper proposes a new methodology to detect/prevent hardware Trojans in third party IP cores. The method works by gradually building trust in suspected IP cores by comparing the outputs of different untrusted implementations of the same IP core. Simulation results show that our method achieves higher probability of Trojan detection over a naive implementation of simple voting on the output of different IP cores. In addition, experimental results show that the proposed method requires less hardware overhead when compared with a simple voting technique achieving the same degree of security.

Teaching Robotics Software with the Open Hardware Mobile Manipulator

ERIC Educational Resources Information Center

Vona, M.; Shekar, N. H.

2013-01-01

The "open hardware mobile manipulator" (OHMM) is a new open platform with a unique combination of features for teaching robotics software and algorithms. On-board low- and high-level processors support real-time embedded programming and motor control, as well as higher-level coding with contemporary libraries. Full hardware designs and…

Applying reconfigurable hardware to the analysis of multispectral and hyperspectral imagery

NASA Astrophysics Data System (ADS)

Leeser, Miriam E.; Belanovic, Pavle; Estlick, Michael; Gokhale, Maya; Szymanski, John J.; Theiler, James P.

2002-01-01

Unsupervised clustering is a powerful technique for processing multispectral and hyperspectral images. Last year, we reported on an implementation of k-means clustering for multispectral images. Our implementation in reconfigurable hardware processed 10 channel multispectral images two orders of magnitude faster than a software implementation of the same algorithm. The advantage of using reconfigurable hardware to accelerate k-means clustering is clear; the disadvantage is the hardware implementation worked for one specific dataset. It is a non-trivial task to change this implementation to handle a dataset with different number of spectral channels, bits per spectral channel, or number of pixels; or to change the number of clusters. These changes required knowledge of the hardware design process and could take several days of a designer's time. Since multispectral data sets come in many shapes and sizes, being able to easily change the k-means implementation for these different data sets is important. For this reason, we have developed a parameterized implementation of the k-means algorithm. Our design is parameterized by the number of pixels in an image, the number of channels per pixel, and the number of bits per channel as well as the number of clusters. These parameters can easily be changed in a few minutes by someone not familiar with the design process. The resulting implementation is very close in performance to the original hardware implementation. It has the added advantage that the parameterized design compiles approximately three times faster than the original.

Design of Test Support Hardware for Advanced Space Suits

NASA Technical Reports Server (NTRS)

Watters, Jeffrey A.; Rhodes, Richard

2013-01-01

As a member of the Space Suit Assembly Development Engineering Team, I designed and built test equipment systems to support the development of the next generation of advanced space suits. During space suit testing it is critical to supply the subject with two functions: (1) cooling to remove metabolic heat, and (2) breathing air to pressurize the space suit. The objective of my first project was to design, build, and certify an improved Space Suit Cooling System for manned testing in a 1-G environment. This design had to be portable and supply a minimum cooling rate of 2500 BTU/hr. The Space Suit Cooling System is a robust, portable system that supports very high metabolic rates. It has a highly adjustable cool rate and is equipped with digital instrumentation to monitor the flowrate and critical temperatures. It can supply a variable water temperature down to 34 deg., and it can generate a maximum water flowrate of 2.5 LPM. My next project was to design and build a Breathing Air System that was capable of supply facility air to subjects wearing the Z-2 space suit. The system intakes 150 PSIG breathing air and regulates it to two operating pressures: 4.3 and 8.3 PSIG. It can also provide structural capabilities at 1.5x operating pressure: 6.6 and 13.2 PSIG, respectively. It has instrumentation to monitor flowrate, as well as inlet and outlet pressures. The system has a series of relief valves to fully protect itself in case of regulator failure. Both projects followed a similar design methodology. The first task was to perform research on existing concepts to develop a sufficient background knowledge. Then mathematical models were developed to size components and simulate system performance. Next, mechanical and electrical schematics were generated and presented at Design Reviews. After the systems were approved by the suit team, all the hardware components were specified and procured. The systems were then packaged, fabricated, and thoroughly tested. The next step

Reconfigurable Hardware Adapts to Changing Mission Demands

NASA Technical Reports Server (NTRS)

2003-01-01

A new class of computing architectures and processing systems, which use reconfigurable hardware, is creating a revolutionary approach to implementing future spacecraft systems. With the increasing complexity of electronic components, engineers must design next-generation spacecraft systems with new technologies in both hardware and software. Derivation Systems, Inc., of Carlsbad, California, has been working through NASA s Small Business Innovation Research (SBIR) program to develop key technologies in reconfigurable computing and Intellectual Property (IP) soft cores. Founded in 1993, Derivation Systems has received several SBIR contracts from NASA s Langley Research Center and the U.S. Department of Defense Air Force Research Laboratories in support of its mission to develop hardware and software for high-assurance systems. Through these contracts, Derivation Systems began developing leading-edge technology in formal verification, embedded Java, and reconfigurable computing for its PF3100, Derivational Reasoning System (DRS ), FormalCORE IP, FormalCORE PCI/32, FormalCORE DES, and LavaCORE Configurable Java Processor, which are designed for greater flexibility and security on all space missions.

Mitigating Communication Delays in Remotely Connected Hardware-in-the-loop Experiments

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cale, James; Johnson, Brian; Dall'Anese, Emiliano

Here, this paper introduces a potential approach for mitigating the effects of communication delays between multiple, closed-loop hardware-in-the-loop experiments which are virtually connected, yet physically separated. The method consists of an analytical method for the compensation of communication delays, along with the supporting computational and communication infrastructure. The control design leverages tools for the design of observers for the compensation of measurement errors in systems with time-varying delays. The proposed methodology is validated through computer simulation and hardware experimentation connecting hardware-in-the-loop experiments conducted between laboratories separated by a distance of over 100 km.

Mitigating Communication Delays in Remotely Connected Hardware-in-the-loop Experiments

DOE PAGES

Cale, James; Johnson, Brian; Dall'Anese, Emiliano; ...

2018-03-30

Here, this paper introduces a potential approach for mitigating the effects of communication delays between multiple, closed-loop hardware-in-the-loop experiments which are virtually connected, yet physically separated. The method consists of an analytical method for the compensation of communication delays, along with the supporting computational and communication infrastructure. The control design leverages tools for the design of observers for the compensation of measurement errors in systems with time-varying delays. The proposed methodology is validated through computer simulation and hardware experimentation connecting hardware-in-the-loop experiments conducted between laboratories separated by a distance of over 100 km.

Verification of the FtCayuga fault-tolerant microprocessor system. Volume 2: Formal specification and correctness theorems

NASA Technical Reports Server (NTRS)

Bickford, Mark; Srivas, Mandayam

1991-01-01

Presented here is a formal specification and verification of a property of a quadruplicately redundant fault tolerant microprocessor system design. A complete listing of the formal specification of the system and the correctness theorems that are proved are given. The system performs the task of obtaining interactive consistency among the processors using a special instruction on the processors. The design is based on an algorithm proposed by Pease, Shostak, and Lamport. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, providing certain preconditions hold, using a computer aided design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover.

Real-time orthorectification by FPGA-based hardware acceleration

NASA Astrophysics Data System (ADS)

Kuo, David; Gordon, Don

2010-10-01

Orthorectification that corrects the perspective distortion of remote sensing imagery, providing accurate geolocation and ease of correlation to other images is a valuable first-step in image processing for information extraction. However, the large amount of metadata and the floating-point matrix transformations required to operate on each pixel make this a computation and I/O (Input/Output) intensive process. As result much imagery is either left unprocessed or loses timesensitive value in the long processing cycle. However, the computation on each pixel can be reduced substantially by using computational results of the neighboring pixels and accelerated by special pipelined hardware architecture in one to two orders of magnitude. A specialized coprocessor that is implemented inside an FPGA (Field Programmable Gate Array) chip and surrounded by vendorsupported hardware IP (Intellectual Property) shares the computation workload with CPU through PCI-Express interface. The ultimate speed of one pixel per clock (125 MHz) is achieved by the pipelined systolic array architecture. The optimal partition between software and hardware, the timing profile among image I/O and computation, and the highly automated GUI (Graphical User Interface) that fully exploits this speed increase to maximize overall image production throughput will also be discussed. The software that runs on a workstation with the acceleration hardware orthorectifies 16 Megapixels per second, which is 16 times faster than without the hardware. It turns the production time from months to days. A real-life successful story of an imaging satellite company that adopted such workstations for their orthorectified imagery production will be presented. The potential candidacy of the image processing computation that can be accelerated more efficiently by the same approach will also be analyzed.

Designing multifocal corneal models to correct presbyopia by laser ablation

NASA Astrophysics Data System (ADS)

Alarcón, Aixa; Anera, Rosario G.; Del Barco, Luis Jiménez; Jiménez, José R.

2012-01-01

Two multifocal corneal models and an aspheric model designed to correct presbyopia by corneal photoablation were evaluated. The design of each model was optimized to achieve the best visual quality possible for both near and distance vision. In addition, we evaluated the effect of myosis and pupil decentration on visual quality. The corrected model with the central zone for near vision provides better results since it requires less ablated corneal surface area, permits higher addition values, presents stabler visual quality with pupil-size variations and lower high-order aberrations.

Electronic hardware design of electrical capacitance tomography systems.

PubMed

Saied, I; Meribout, M

2016-06-28

Electrical tomography techniques for process imaging are very prominent for industrial applications, such as the oil and gas industry and chemical refineries, owing to their ability to provide the flow regime of a flowing fluid within a relatively high throughput. Among the various techniques, electrical capacitance tomography (ECT) is gaining popularity due to its non-invasive nature and its capability to differentiate between different phases based on their permittivity distribution. In recent years, several hardware designs have been provided for ECT systems that have improved its resolution of measurements to be around attofarads (aF, 10(-18) F), or the number of channels, that is required to be large for some applications that require a significant amount of data. In terms of image acquisition time, some recent systems could achieve a throughput of a few hundred frames per second, while data processing time could be achieved in only a few milliseconds per frame. This paper outlines the concept and main features of the most recent front-end and back-end electronic circuits dedicated for ECT systems. In this paper, multiple-excitation capacitance polling, a front-end electronic technique, shows promising results for ECT systems to acquire fast data acquisition speeds. A highly parallel field-programmable gate array (FPGA) based architecture for a fast reconstruction algorithm is also described. This article is part of the themed issue 'Supersensing through industrial process tomography'. © 2016 The Author(s).

Hardware architecture design of a fast global motion estimation method

NASA Astrophysics Data System (ADS)

Liang, Chaobing; Sang, Hongshi; Shen, Xubang

2015-12-01

VLSI implementation of gradient-based global motion estimation (GME) faces two main challenges: irregular data access and high off-chip memory bandwidth requirement. We previously proposed a fast GME method that reduces computational complexity by choosing certain number of small patches containing corners and using them in a gradient-based framework. A hardware architecture is designed to implement this method and further reduce off-chip memory bandwidth requirement. On-chip memories are used to store coordinates of the corners and template patches, while the Gaussian pyramids of both the template and reference frame are stored in off-chip SDRAMs. By performing geometric transform only on the coordinates of the center pixel of a 3-by-3 patch in the template image, a 5-by-5 area containing the warped 3-by-3 patch in the reference image is extracted from the SDRAMs by burst read. Patched-based and burst mode data access helps to keep the off-chip memory bandwidth requirement at the minimum. Although patch size varies at different pyramid level, all patches are processed in term of 3x3 patches, so the utilization of the patch-processing circuit reaches 100%. FPGA implementation results show that the design utilizes 24,080 bits on-chip memory and for a sequence with resolution of 352x288 and frequency of 60Hz, the off-chip bandwidth requirement is only 3.96Mbyte/s, compared with 243.84Mbyte/s of the original gradient-based GME method. This design can be used in applications like video codec, video stabilization, and super-resolution, where real-time GME is a necessity and minimum memory bandwidth requirement is appreciated.

Criticality as a Set-Point for Adaptive Behavior in Neuromorphic Hardware

PubMed Central

Srinivasa, Narayan; Stepp, Nigel D.; Cruz-Albrecht, Jose

2015-01-01

Neuromorphic hardware are designed by drawing inspiration from biology to overcome limitations of current computer architectures while forging the development of a new class of autonomous systems that can exhibit adaptive behaviors. Several designs in the recent past are capable of emulating large scale networks but avoid complexity in network dynamics by minimizing the number of dynamic variables that are supported and tunable in hardware. We believe that this is due to the lack of a clear understanding of how to design self-tuning complex systems. It has been widely demonstrated that criticality appears to be the default state of the brain and manifests in the form of spontaneous scale-invariant cascades of neural activity. Experiment, theory and recent models have shown that neuronal networks at criticality demonstrate optimal information transfer, learning and information processing capabilities that affect behavior. In this perspective article, we argue that understanding how large scale neuromorphic electronics can be designed to enable emergent adaptive behavior will require an understanding of how networks emulated by such hardware can self-tune local parameters to maintain criticality as a set-point. We believe that such capability will enable the design of truly scalable intelligent systems using neuromorphic hardware that embrace complexity in network dynamics rather than avoiding it. PMID:26648839

From MIMO-OFDM Algorithms to a Real-Time Wireless Prototype: A Systematic Matlab-to-Hardware Design Flow

NASA Astrophysics Data System (ADS)

Weijers, Jan-Willem; Derudder, Veerle; Janssens, Sven; Petré, Frederik; Bourdoux, André

2006-12-01

To assess the performance of forthcoming 4th generation wireless local area networks, the algorithmic functionality is usually modelled using a high-level mathematical software package, for instance, Matlab. In order to validate the modelling assumptions against the real physical world, the high-level functional model needs to be translated into a prototype. A systematic system design methodology proves very valuable, since it avoids, or, at least reduces, numerous design iterations. In this paper, we propose a novel Matlab-to-hardware design flow, which allows to map the algorithmic functionality onto the target prototyping platform in a systematic and reproducible way. The proposed design flow is partly manual and partly tool assisted. It is shown that the proposed design flow allows to use the same testbench throughout the whole design flow and avoids time-consuming and error-prone intermediate translation steps.

Contact lens design with slope-constrained Q-type aspheres for myopia correction

NASA Astrophysics Data System (ADS)

Peng, Wei-Jei; Cheng, Yuan-Chieh; Hsu, Wei-Yao; Yu, Zong-Ru; Ho, Cheng-Fang; Abou-El-Hossein, Khaled

2017-08-01

The design of the rigid contact lens (CL) with slope-constrained Q-type aspheres for myopia correction is presented in this paper. The spherical CL is the most common type for myopia correction, however the spherical aberration (SA) caused from the pupil dilation in dark leads to the degradation of visual acuity which cannot be corrected by spherical surface. The spherical and aspheric CLs are designed respectively based on Liou's schematic eye model, and the criterion is the modulation transfer function (MTF) at the frequency of 100 line pair per mm, which corresponds to the normal vision of one arc-minute. After optimization, the MTF of the aspheric design is superior to that of the spherical design, because the aspheric surface corrects the SA for improving the visual acuity in dark. For avoiding the scratch caused from the contact profilometer, the aspheric surface is designed to match the measurability of the interferometer. The Q-type aspheric surface is employed to constrain the root-mean-square (rms) slope of the departure from a best-fit sphere directly, because the fringe density is limited by the interferometer. The maximum sag departure from a best-fit sphere is also controlled according to the measurability of the aspheric stitching interferometer (ASI). The inflection point is removed during optimization for measurability and appearance. In this study, the aspheric CL is successfully designed with Q-type aspheres for the measurability of the interferometer. It not only corrects the myopia but also eliminates the SA for improving the visual acuity in dark based on the schematic eye model.

Intracavity adaptive optics. 1: Astigmatism correction performance.

PubMed

Spinhirne, J M; Anafi, D; Freeman, R H; Garcia, H R

1981-03-15

A detailed experimental study has been conducted on adaptive optical control methodologies inside a laser resonator. A comparison is presented of several optimization techniques using a multidither zonal coherent optical adaptive technique system within a laser resonator for the correction of astigmatism. A dramatic performance difference is observed when optimizing on beam quality compared with optimizing on power-in-the-bucket. Experimental data are also presented on proper selection criteria for dither frequencies when controlling phase front errors. The effects of hardware limitations and design considerations on the performance of the system are presented, and general conclusions and physical interpretations on the results are made when possible.

No-hardware-signature cybersecurity-crypto-module: a resilient cyber defense agent

NASA Astrophysics Data System (ADS)

Zaghloul, A. R. M.; Zaghloul, Y. A.

2014-06-01

We present an optical cybersecurity-crypto-module as a resilient cyber defense agent. It has no hardware signature since it is bitstream reconfigurable, where single hardware architecture functions as any selected device of all possible ones of the same number of inputs. For a two-input digital device, a 4-digit bitstream of 0s and 1s determines which device, of a total of 16 devices, the hardware performs as. Accordingly, the hardware itself is not physically reconfigured, but its performance is. Such a defense agent allows the attack to take place, rendering it harmless. On the other hand, if the system is already infected with malware sending out information, the defense agent allows the information to go out, rendering it meaningless. The hardware architecture is immune to side attacks since such an attack would reveal information on the attack itself and not on the hardware. This cyber defense agent can be used to secure a point-to-point, point-to-multipoint, a whole network, and/or a single entity in the cyberspace. Therefore, ensuring trust between cyber resources. It can provide secure communication in an insecure network. We provide the hardware design and explain how it works. Scalability of the design is briefly discussed. (Protected by United States Patents No.: US 8,004,734; US 8,325,404; and other National Patents worldwide.)

GPU accelerated manifold correction method for spinning compact binaries

NASA Astrophysics Data System (ADS)

Ran, Chong-xi; Liu, Song; Zhong, Shuang-ying

2018-04-01

The graphics processing unit (GPU) acceleration of the manifold correction algorithm based on the compute unified device architecture (CUDA) technology is designed to simulate the dynamic evolution of the Post-Newtonian (PN) Hamiltonian formulation of spinning compact binaries. The feasibility and the efficiency of parallel computation on GPU have been confirmed by various numerical experiments. The numerical comparisons show that the accuracy on GPU execution of manifold corrections method has a good agreement with the execution of codes on merely central processing unit (CPU-based) method. The acceleration ability when the codes are implemented on GPU can increase enormously through the use of shared memory and register optimization techniques without additional hardware costs, implying that the speedup is nearly 13 times as compared with the codes executed on CPU for phase space scan (including 314 × 314 orbits). In addition, GPU-accelerated manifold correction method is used to numerically study how dynamics are affected by the spin-induced quadrupole-monopole interaction for black hole binary system.

Hardware Acceleration of Adaptive Neural Algorithms.

DOE Office of Scientific and Technical Information (OSTI.GOV)

James, Conrad D.

As tradit ional numerical computing has faced challenges, researchers have turned towards alternative computing approaches to reduce power - per - computation metrics and improve algorithm performance. Here, we describe an approach towards non - conventional computing that strengthens the connection between machine learning and neuroscience concepts. The Hardware Acceleration of Adaptive Neural Algorithms (HAANA) project ha s develop ed neural machine learning algorithms and hardware for applications in image processing and cybersecurity. While machine learning methods are effective at extracting relevant features from many types of data, the effectiveness of these algorithms degrades when subjected to real - worldmore » conditions. Our team has generated novel neural - inspired approa ches to improve the resiliency and adaptability of machine learning algorithms. In addition, we have also designed and fabricated hardware architectures and microelectronic devices specifically tuned towards the training and inference operations of neural - inspired algorithms. Finally, our multi - scale simulation framework allows us to assess the impact of microelectronic device properties on algorithm performance.« less

Development of Enhanced Avionics Flight Hardware Selection Process

NASA Technical Reports Server (NTRS)

Smith, K.; Watson, G. L.

2003-01-01

The primary objective of this research was to determine the processes and feasibility of using commercial off-the-shelf PC104 hardware for flight applications. This would lead to a faster, better, and cheaper approach to low-budget programs as opposed to the design, procurement. and fabrication of space flight hardware. This effort will provide experimental evaluation with results of flight environmental testing. Also, a method and/or suggestion used to bring test hardware up to flight standards will be given. Several microgravity programs, such as the Equiaxed Dendritic Solidification Experiment, Self-Diffusion in Liquid Elements, and various other programs, are interested in PC104 environmental testing to establish the limits of this technology.

The JPL telerobot operator control station. Part 1: Hardware

NASA Technical Reports Server (NTRS)

Kan, Edwin P.; Tower, John T.; Hunka, George W.; Vansant, Glenn J.

1989-01-01

The Operator Control Station of the Jet Propulsion Laboratory (JPL)/NASA Telerobot Demonstrator System provides the man-machine interface between the operator and the system. It provides all the hardware and software for accepting human input for the direct and indirect (supervised) manipulation of the robot arms and tools for task execution. Hardware and software are also provided for the display and feedback of information and control data for the operator's consumption and interaction with the task being executed. The hardware design, system architecture, and its integration and interface with the rest of the Telerobot Demonstrator System are discussed.

Magnetic Field Apparatus (MFA) Hardware Test

NASA Technical Reports Server (NTRS)

Anderson, Ken; Boody, April; Reed, Dave; Wang, Chung; Stuckey, Bob; Cox, Dave

1999-01-01

The objectives of this study are threefold: (1) Provide insight into water delivery in microgravity and determine optimal germination paper wetting for subsequent seed germination in microgravity; (2) Observe the behavior of water exposed to a strong localized magnetic field in microgravity; and (3) Simulate the flow of fixative (using water) through the hardware. The Magnetic Field Apparatus (MFA) is a new piece of hardware slated to fly on the Space Shuttle in early 2001. MFA is designed to expose plant tissue to magnets in a microgravity environment, deliver water to the plant tissue, record photographic images of plant tissue, and deliver fixative to the plant tissue.

Exercise Countermeasure Hardware Evolution on ISS: The First Decade.

PubMed

Korth, Deborah W

2015-12-01

The hardware systems necessary to support exercise countermeasures to the deconditioning associated with microgravity exposure have evolved and improved significantly during the first decade of the International Space Station (ISS), resulting in both new types of hardware and enhanced performance capabilities for initial hardware items. The original suite of countermeasure hardware supported the first crews to arrive on the ISS and the improved countermeasure system delivered in later missions continues to serve the astronauts today with increased efficacy. Due to aggressive hardware development schedules and constrained budgets, the initial approach was to identify existing spaceflight-certified exercise countermeasure equipment, when available, and modify it for use on the ISS. Program management encouraged the use of commercial-off-the-shelf (COTS) hardware, or hardware previously developed (heritage hardware) for the Space Shuttle Program. However, in many cases the resultant hardware did not meet the additional requirements necessary to support crew health maintenance during long-duration missions (3 to 12 mo) and anticipated future utilization activities in support of biomedical research. Hardware development was further complicated by performance requirements that were not fully defined at the outset and tended to evolve over the course of design and fabrication. Modifications, ranging from simple to extensive, were necessary to meet these evolving requirements in each case where heritage hardware was proposed. Heritage hardware was anticipated to be inherently reliable without the need for extensive ground testing, due to its prior positive history during operational spaceflight utilization. As a result, developmental budgets were typically insufficient and schedules were too constrained to permit long-term evaluation of dedicated ground-test units ("fleet leader" type testing) to identify reliability issues when applied to long-duration use. In most cases

A Method of Sky Ripple Residual Nonuniformity Reduction for a Cooled Infrared Imager and Hardware Implementation.

PubMed

Li, Yiyang; Jin, Weiqi; Li, Shuo; Zhang, Xu; Zhu, Jin

2017-05-08

Cooled infrared detector arrays always suffer from undesired ripple residual nonuniformity (RNU) in sky scene observations. The ripple residual nonuniformity seriously affects the imaging quality, especially for small target detection. It is difficult to eliminate it using the calibration-based techniques and the current scene-based nonuniformity algorithms. In this paper, we present a modified temporal high-pass nonuniformity correction algorithm using fuzzy scene classification. The fuzzy scene classification is designed to control the correction threshold so that the algorithm can remove ripple RNU without degrading the scene details. We test the algorithm on a real infrared sequence by comparing it to several well-established methods. The result shows that the algorithm has obvious advantages compared with the tested methods in terms of detail conservation and convergence speed for ripple RNU correction. Furthermore, we display our architecture with a prototype built on a Xilinx Virtex-5 XC5VLX50T field-programmable gate array (FPGA), which has two advantages: (1) low resources consumption; and (2) small hardware delay (less than 10 image rows). It has been successfully applied in an actual system.

Exascale Hardware Architectures Working Group

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hemmert, S; Ang, J; Chiang, P

2011-03-15

is relatively immediate, as there is only a small window of opportunity to influence hardware design for 2018 machines. Given the short timeline a firm co-design methodology with vendors is of prime importance.« less

Automated power distribution system hardware. [for space station power supplies

NASA Technical Reports Server (NTRS)

Anderson, Paul M.; Martin, James A.; Thomason, Cindy

1989-01-01

An automated power distribution system testbed for the space station common modules has been developed. It incorporates automated control and monitoring of a utility-type power system. Automated power system switchgear, control and sensor hardware requirements, hardware design, test results, and potential applications are discussed. The system is designed so that the automated control and monitoring of the power system is compatible with both a 208-V, 20-kHz single-phase AC system and a high-voltage (120 to 150 V) DC system.

Microbiologic assay of space hardware.

NASA Technical Reports Server (NTRS)

Favero, M. S.

1971-01-01

Review of the procedures used in the microbiological examination of space hardware. The general procedure for enumerating aerobic and anaerobic microorganisms and spores is outlined. Culture media and temperature-time cycles used for incubation are reviewed, along with assay systems designed for the enumeration of aerobic and anaerobic spores. The special problems which are discussed are involved in the precise and accurate enumeration of microorganisms on surfaces and in the neutralization of viable organisms buried inside solid materials that could be released to a planet's surface if the solid should be fractured. Special attention is given to sampling procedures including also the indirect techniques of surface assays of space hardware such as those using detachable or fallout strips. Some data on comparative levels of microbial contamination on lunar and planetary spacecraft are presented.

Interim Service ISDN Satellite (ISIS) hardware experiment development for advanced ISDN satellite designs and experiments

NASA Technical Reports Server (NTRS)

Pepin, Gerard R.

1992-01-01

The Interim Service Integrated Service Digital Network (ISDN) Satellite (ISIS) Hardware Experiment Development for Advanced Satellite Designs describes the development of the ISDN Satellite Terminal Adapter (ISTA) capable of translating ISDN protocol traffic into Time Division Multiple Access (TDMA) signals for use by a communications satellite. The ISTA connects the Type 1 Network Termination (NT1) via the U-interface on the line termination side of the CPE to the RS-499 interface for satellite uplink. The same ISTA converts in the opposite direction the RS-499 to U-interface data with a simple switch setting.

Error correcting circuit design with carbon nanotube field effect transistors

NASA Astrophysics Data System (ADS)

Liu, Xiaoqiang; Cai, Li; Yang, Xiaokuo; Liu, Baojun; Liu, Zhongyong

2018-03-01

In this work, a parallel error correcting circuit based on (7, 4) Hamming code is designed and implemented with carbon nanotube field effect transistors, and its function is validated by simulation in HSpice with the Stanford model. A grouping method which is able to correct multiple bit errors in 16-bit and 32-bit application is proposed, and its error correction capability is analyzed. Performance of circuits implemented with CNTFETs and traditional MOSFETs respectively is also compared, and the former shows a 34.4% decrement of layout area and a 56.9% decrement of power consumption.

Use of CCSDS Packets Over SpaceWire to Control Hardware

NASA Technical Reports Server (NTRS)

Haddad, Omar; Blau, Michael; Haghani, Noosha; Yuknis, William; Albaijes, Dennis

2012-01-01

For the Lunar Reconnaissance Orbiter, the Command and Data Handling subsystem consisted of several electronic hardware assemblies that were connected with SpaceWire serial links. Electronic hardware would be commanded/controlled and telemetry data was obtained using the SpaceWire links. Prior art focused on parallel data buses and other types of serial buses, which were not compatible with the SpaceWire and the core flight executive (CFE) software bus. This innovation applies to anything that utilizes both SpaceWire networks and the CFE software. The CCSDS (Consultative Committee for Space Data Systems) packet contains predetermined values in its payload fields that electronic hardware attached at the terminus of the SpaceWire node would decode, interpret, and execute. The hardware s interpretation of the packet data would enable the hardware to change its state/configuration (command) or generate status (telemetry). The primary purpose is to provide an interface that is compatible with the hardware and the CFE software bus. By specifying the format of the CCSDS packet, it is possible to specify how the resulting hardware is to be built (in terms of digital logic) that results in a hardware design that can be controlled by the CFE software bus in the final application

Hardware and software status of QCDOC

NASA Astrophysics Data System (ADS)

Boyle, P. A.; Chen, D.; Christ, N. H.; Clark, M.; Cohen, S. D.; Cristian, C.; Dong, Z.; Gara, A.; Joó, B.; Jung, C.; Kim, C.; Levkova, L.; Liao, X.; Liu, G.; Mawhinney, R. D.; Ohta, S.; Petrov, K.; Wettig, T.; Yamaguchi, A.

2004-03-01

QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation.

Stretched Lens Array (SLA) Photovoltaic Concentrator Hardware Development and Testing

NASA Technical Reports Server (NTRS)

Piszczor, Michael; O'Neill, Mark J.; Eskenazi, Michael

2003-01-01

Over the past two years, the Stretched Lens Array (SLA) photovoltaic concentrator has evolved, under a NASA contract, from a concept with small component demonstrators to operational array hardware that is ready for space validation testing. A fully-functional four panel SLA solar array has been designed, built and tested. This paper will summarize the focus of the hardware development effort, discuss the results of recent testing conducted under this program and present the expected performance of a full size 7kW array designed to meet the requirements of future space missions.

Support for Diagnosis of Custom Computer Hardware

NASA Technical Reports Server (NTRS)

Molock, Dwaine S.

2008-01-01

The Coldfire SDN Diagnostics software is a flexible means of exercising, testing, and debugging custom computer hardware. The software is a set of routines that, collectively, serve as a common software interface through which one can gain access to various parts of the hardware under test and/or cause the hardware to perform various functions. The routines can be used to construct tests to exercise, and verify the operation of, various processors and hardware interfaces. More specifically, the software can be used to gain access to memory, to execute timer delays, to configure interrupts, and configure processor cache, floating-point, and direct-memory-access units. The software is designed to be used on diverse NASA projects, and can be customized for use with different processors and interfaces. The routines are supported, regardless of the architecture of a processor that one seeks to diagnose. The present version of the software is configured for Coldfire processors on the Subsystem Data Node processor boards of the Solar Dynamics Observatory. There is also support for the software with respect to Mongoose V, RAD750, and PPC405 processors or their equivalents.

Transistor Level Circuit Experiments using Evolvable Hardware

NASA Technical Reports Server (NTRS)

Stoica, A.; Zebulum, R. S.; Keymeulen, D.; Ferguson, M. I.; Daud, Taher; Thakoor, A.

2005-01-01

The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

On the use of inexact, pruned hardware in atmospheric modelling

PubMed Central

Düben, Peter D.; Joven, Jaume; Lingamneni, Avinash; McNamara, Hugh; De Micheli, Giovanni; Palem, Krishna V.; Palmer, T. N.

2014-01-01

Inexact hardware design, which advocates trading the accuracy of computations in exchange for significant savings in area, power and/or performance of computing hardware, has received increasing prominence in several error-tolerant application domains, particularly those involving perceptual or statistical end-users. In this paper, we evaluate inexact hardware for its applicability in weather and climate modelling. We expand previous studies on inexact techniques, in particular probabilistic pruning, to floating point arithmetic units and derive several simulated set-ups of pruned hardware with reasonable levels of error for applications in atmospheric modelling. The set-up is tested on the Lorenz ‘96 model, a toy model for atmospheric dynamics, using software emulation for the proposed hardware. The results show that large parts of the computation tolerate the use of pruned hardware blocks without major changes in the quality of short- and long-time diagnostics, such as forecast errors and probability density functions. This could open the door to significant savings in computational cost and to higher resolution simulations with weather and climate models. PMID:24842031

Hardware Development Process for Human Research Facility Applications

NASA Technical Reports Server (NTRS)

Bauer, Liz

2000-01-01

The simple goal of the Human Research Facility (HRF) is to conduct human research experiments on the International Space Station (ISS) astronauts during long-duration missions. This is accomplished by providing integration and operation of the necessary hardware and software capabilities. A typical hardware development flow consists of five stages: functional inputs and requirements definition, market research, design life cycle through hardware delivery, crew training, and mission support. The purpose of this presentation is to guide the audience through the early hardware development process: requirement definition through selecting a development path. Specific HRF equipment is used to illustrate the hardware development paths. The source of hardware requirements is the science community and HRF program. The HRF Science Working Group, consisting of SCientists from various medical disciplines, defined a basic set of equipment with functional requirements. This established the performance requirements of the hardware. HRF program requirements focus on making the hardware safe and operational in a space environment. This includes structural, thermal, human factors, and material requirements. Science and HRF program requirements are defined in a hardware requirements document which includes verification methods. Once the hardware is fabricated, requirements are verified by inspection, test, analysis, or demonstration. All data is compiled and reviewed to certify the hardware for flight. Obviously, the basis for all hardware development activities is requirement definition. Full and complete requirement definition is ideal prior to initiating the hardware development. However, this is generally not the case, but the hardware team typically has functional inputs as a guide. The first step is for engineers to conduct market research based on the functional inputs provided by scientists. CommerCially available products are evaluated against the science requirements as

Design and fabrication of a freeform phase plate for high-order ocular aberration correction

NASA Astrophysics Data System (ADS)

Yi, Allen Y.; Raasch, Thomas W.

2005-11-01

In recent years it has become possible to measure and in some instances to correct the high-order aberrations of human eyes. We have investigated the correction of wavefront error of human eyes by using phase plates designed to compensate for that error. The wavefront aberrations of the four eyes of two subjects were experimentally determined, and compensating phase plates were machined with an ultraprecision diamond-turning machine equipped with four independent axes. A slow-tool servo freeform trajectory was developed for the machine tool path. The machined phase-correction plates were measured and compared with the original design values to validate the process. The position of the phase-plate relative to the pupil is discussed. The practical utility of this mode of aberration correction was investigated with visual acuity testing. The results are consistent with the potential benefit of aberration correction but also underscore the critical positioning requirements of this mode of aberration correction. This process is described in detail from optical measurements, through machining process design and development, to final results.

Hardware demonstration of flexible beam control

NASA Technical Reports Server (NTRS)

Schaechter, D. B.

1980-01-01

An experiment employing a pinned-free flexible beam has been constructed to demonstrate and verify several facets of the control of flexible structures. The desired features of the experiment are to demonstrate active shape control, active dynamic control, adaptive control, various control law design approaches, and associated hardware requirements and mechanization difficulties. This paper contains the analytical work performed in support of the facility development, the final design specifications, control law synthesis, and some preliminary results.

Design and implementation of the tree-based fuzzy logic controller.

PubMed

Liu, B D; Huang, C Y

1997-01-01

In this paper, a tree-based approach is proposed to design the fuzzy logic controller. Based on the proposed methodology, the fuzzy logic controller has the following merits: the fuzzy control rule can be extracted automatically from the input-output data of the system and the extraction process can be done in one-pass; owing to the fuzzy tree inference structure, the search spaces of the fuzzy inference process are largely reduced; the operation of the inference process can be simplified as a one-dimensional matrix operation because of the fuzzy tree approach; and the controller has regular and modular properties, so it is easy to be implemented by hardware. Furthermore, the proposed fuzzy tree approach has been applied to design the color reproduction system for verifying the proposed methodology. The color reproduction system is mainly used to obtain a color image through the printer that is identical to the original one. In addition to the software simulation, an FPGA is used to implement the prototype hardware system for real-time application. Experimental results show that the effect of color correction is quite good and that the prototype hardware system can operate correctly under the condition of 30 MHz clock rate.

Contamination of planets by nonsterile flight hardware.

NASA Technical Reports Server (NTRS)

Wolfson, R. P.; Craven, C. W.

1971-01-01

The various factors about space missions and spacecraft involved in the study of nonsterile space flight hardware with respect to their effects on planetary quarantine are reviewed. It is shown that methodology currently exists to evaluate the various potential contamination sources and to take appropriate steps in the design of spacecraft ha rdware and mission parameters so that quarantine constraints are met. This work should be done for each program so that the latest knowledge pertaining to various biological questions is utilized, and so that the specific hardware designs of the program can be assessed. The general trend of specific recommendations include: (1) biasing the launch trajectory away from planet to assure against accidental impact of the spacecraft; (2) selecting planetary orbits that meet quarantine requirements - both for accidental impact and for minimizing contamination probabilities due to ejecta; and (3) manufacturing and handling spacecraft under cleanliness conditions assuring minimum bioload.

Hardware Testing for the Optical PAyload for Lasercomm Science (OPALS)

NASA Technical Reports Server (NTRS)

Slagle, Amanda

2011-01-01

Hardware for several subsystems of the proposed Optical PAyload for Lasercomm Science (OPALS), including the gimbal and avionics, was tested. Microswitches installed on the gimbal were evaluated to verify that their point of actuation would remain within the acceptable range even if the switches themselves move slightly during launch. An inspection of the power board was conducted to ensure that all power and ground signals were isolated, that polarized components were correctly oriented, and that all components were intact and securely soldered. Initial testing on the power board revealed several minor problems, but once they were fixed the power board was shown to function correctly. All tests and inspections were documented for future use in verifying launch requirements.

Hardware/software codesign for embedded RISC core

NASA Astrophysics Data System (ADS)

Liu, Peng

2001-12-01

This paper describes hardware/software codesign method of the extendible embedded RISC core VIRGO, which based on MIPS-I instruction set architecture. VIRGO is described by Verilog hardware description language that has five-stage pipeline with shared 32-bit cache/memory interface, and it is controlled by distributed control scheme. Every pipeline stage has one small controller, which controls the pipeline stage status and cooperation among the pipeline phase. Since description use high level language and structure is distributed, VIRGO core has highly extension that can meet the requirements of application. We take look at the high-definition television MPEG2 MPHL decoder chip, constructed the hardware/software codesign virtual prototyping machine that can research on VIRGO core instruction set architecture, and system on chip memory size requirements, and system on chip software, etc. We also can evaluate the system on chip design and RISC instruction set based on the virtual prototyping machine platform.

Hardware Evolution of Analog Speed Controllers for a DC Motor

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; Ferguson, Michael I.

2003-01-01

Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a Field Programmable Transistor Array (FPTA). The performance of these evolved controllers is compared to that of a conventional proportional-integral (PI) controller.

A DSP-based neural network non-uniformity correction algorithm for IRFPA

NASA Astrophysics Data System (ADS)

Liu, Chong-liang; Jin, Wei-qi; Cao, Yang; Liu, Xiu

2009-07-01

An effective neural network non-uniformity correction (NUC) algorithm based on DSP is proposed in this paper. The non-uniform response in infrared focal plane array (IRFPA) detectors produces corrupted images with a fixed-pattern noise(FPN).We introduced and analyzed the artificial neural network scene-based non-uniformity correction (SBNUC) algorithm. A design of DSP-based NUC development platform for IRFPA is described. The DSP hardware platform designed is of low power consumption, with 32-bit fixed point DSP TMS320DM643 as the kernel processor. The dependability and expansibility of the software have been improved by DSP/BIOS real-time operating system and Reference Framework 5. In order to realize real-time performance, the calibration parameters update is set at a lower task priority then video input and output in DSP/BIOS. In this way, calibration parameters updating will not affect video streams. The work flow of the system and the strategy of real-time realization are introduced. Experiments on real infrared imaging sequences demonstrate that this algorithm requires only a few frames to obtain high quality corrections. It is computationally efficient and suitable for all kinds of non-uniformity.

Hardware Removal in Craniomaxillofacial Trauma

PubMed Central

Cahill, Thomas J.; Gandhi, Rikesh; Allori, Alexander C.; Marcus, Jeffrey R.; Powers, David; Erdmann, Detlev; Hollenbeck, Scott T.; Levinson, Howard

2015-01-01

Background Craniomaxillofacial (CMF) fractures are typically treated with open reduction and internal fixation. Open reduction and internal fixation can be complicated by hardware exposure or infection. The literature often does not differentiate between these 2 entities; so for this study, we have considered all hardware exposures as hardware infections. Approximately 5% of adults with CMF trauma are thought to develop hardware infections. Management consists of either removing the hardware versus leaving it in situ. The optimal approach has not been investigated. Thus, a systematic review of the literature was undertaken and a resultant evidence-based approach to the treatment and management of CMF hardware infections was devised. Materials and Methods A comprehensive search of journal articles was performed in parallel using MEDLINE, Web of Science, and ScienceDirect electronic databases. Keywords and phrases used were maxillofacial injuries; facial bones; wounds and injuries; fracture fixation, internal; wound infection; and infection. Our search yielded 529 articles. To focus on CMF fractures with hardware infections, the full text of English-language articles was reviewed to identify articles focusing on the evaluation and management of infected hardware in CMF trauma. Each article’s reference list was manually reviewed and citation analysis performed to identify articles missed by the search strategy. There were 259 articles that met the full inclusion criteria and form the basis of this systematic review. The articles were rated based on the level of evidence. There were 81 grade II articles included in the meta-analysis. Result Our meta-analysis revealed that 7503 patients were treated with hardware for CMF fractures in the 81 grade II articles. Hardware infection occurred in 510 (6.8%) of these patients. Of those infections, hardware removal occurred in 264 (51.8%) patients; hardware was left in place in 166 (32.6%) patients; and in 80 (15.6%) cases

The robust corrective action priority-an improved approach for selecting competing corrective actions in FMEA based on principle of robust design

NASA Astrophysics Data System (ADS)

Sutrisno, Agung; Gunawan, Indra; Vanany, Iwan

2017-11-01

In spite of being integral part in risk - based quality improvement effort, studies improving quality of selection of corrective action priority using FMEA technique are still limited in literature. If any, none is considering robustness and risk in selecting competing improvement initiatives. This study proposed a theoretical model to select risk - based competing corrective action by considering robustness and risk of competing corrective actions. We incorporated the principle of robust design in counting the preference score among corrective action candidates. Along with considering cost and benefit of competing corrective actions, we also incorporate the risk and robustness of corrective actions. An example is provided to represent the applicability of the proposed model.

A Student Experiment Method for Learning the Basics of Embedded Software Technologies Including Hardware/Software Co-design

NASA Astrophysics Data System (ADS)

Kambe, Hidetoshi; Mitsui, Hiroyasu; Endo, Satoshi; Koizumi, Hisao

The applications of embedded system technologies have spread widely in various products, such as home appliances, cellular phones, automobiles, industrial machines and so on. Due to intensified competition, embedded software has expanded its role in realizing sophisticated functions, and new development methods like a hardware/software (HW/SW) co-design for uniting HW and SW development have been researched. The shortfall of embedded SW engineers was estimated to be approximately 99,000 in the year 2006, in Japan. Embedded SW engineers should understand HW technologies and system architecture design as well as SW technologies. However, a few universities offer this kind of education systematically. We propose a student experiment method for learning the basics of embedded system development, which includes a set of experiments for developing embedded SW, developing embedded HW and experiencing HW/SW co-design. The co-design experiment helps students learn about the basics of embedded system architecture design and the flow of designing actual HW and SW modules. We developed these experiments and evaluated them.

Computer hardware for radiologists: Part I

PubMed Central

Indrajit, IK; Alam, A

2010-01-01

Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU), the chipset, the random access memory (RAM), the memory modules, bus, storage drives, and ports. The personnel computer (PC) has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs). The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called “buses”. The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute “programs”. A Pentium® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM) is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration. PMID:21042437

A Method of Sky Ripple Residual Nonuniformity Reduction for a Cooled Infrared Imager and Hardware Implementation

PubMed Central

Li, Yiyang; Jin, Weiqi; Li, Shuo; Zhang, Xu; Zhu, Jin

2017-01-01

Cooled infrared detector arrays always suffer from undesired ripple residual nonuniformity (RNU) in sky scene observations. The ripple residual nonuniformity seriously affects the imaging quality, especially for small target detection. It is difficult to eliminate it using the calibration-based techniques and the current scene-based nonuniformity algorithms. In this paper, we present a modified temporal high-pass nonuniformity correction algorithm using fuzzy scene classification. The fuzzy scene classification is designed to control the correction threshold so that the algorithm can remove ripple RNU without degrading the scene details. We test the algorithm on a real infrared sequence by comparing it to several well-established methods. The result shows that the algorithm has obvious advantages compared with the tested methods in terms of detail conservation and convergence speed for ripple RNU correction. Furthermore, we display our architecture with a prototype built on a Xilinx Virtex-5 XC5VLX50T field-programmable gate array (FPGA), which has two advantages: (1) low resources consumption; and (2) small hardware delay (less than 10 image rows). It has been successfully applied in an actual system. PMID:28481320

Compensation of long-range process effects on photomasks by design data correction

NASA Astrophysics Data System (ADS)

Schneider, Jens; Bloecker, Martin; Ballhorn, Gerd; Belic, Nikola; Eisenmann, Hans; Keogan, Danny

2002-12-01

CD requirements for advanced photomasks are getting very demanding for the 100 nm-node and below; the ITRS roadmap requires CD uniformities below 10 nm for the most critical layers. To reach this goal, statistical as well as systematic CD contributions must be minimized. Here, we focus on the reduction of systematic CD variations across the masks that may be caused by process effects, e.g. dry etch loading. We address this topic by compensating such effects via design data correction analogous to proximity correction. Dry etch loading is modeled by gaussian convolution of pattern densities. Data correction is done geometrically by edge shifting. As the effect amplitude has an order of magnitude of 10 nm this can only be done on e-beam writers with small address grids to reduce big CD steps in the design data. We present modeling and correction results for special mask patterns with very strong pattern density variations showing that the compensation method is able to reduce CD uniformity by 50-70% depending on pattern details. The data correction itself is done with a new module developed especially to compensate long-range effects and fits nicely into the common data flow environment.

Hardware problems encountered in solar heating and cooling systems

NASA Technical Reports Server (NTRS)

Cash, M.

1978-01-01

Numerous problems in the design, production, installation, and operation of solar energy systems are discussed. Described are hardware problems, which range from simple to obscure and complex, and their resolution.

Testing Microgravity Flight Hardware Concepts on the NASA KC-135

NASA Technical Reports Server (NTRS)

Motil, Susan M.; Harrivel, Angela R.; Zimmerli, Gregory A.

2001-01-01

This paper provides an overview of utilizing the NASA KC-135 Reduced Gravity Aircraft for the Foam Optics and Mechanics (FOAM) microgravity flight project. The FOAM science requirements are summarized, and the KC-135 test-rig used to test hardware concepts designed to meet the requirements are described. Preliminary results regarding foam dispensing, foam/surface slip tests, and dynamic light scattering data are discussed in support of the flight hardware development for the FOAM experiment.

Management of a CFD organization in support of space hardware development

NASA Technical Reports Server (NTRS)

Schutzenhofer, L. A.; Mcconnaughey, P. K.; Mcconnaughey, H. V.; Wang, T. S.

1991-01-01

The management strategy of NASA-Marshall's CFD branch in support of space hardware development and code validation implements various elements of total quality management. The strategy encompasses (1) a teaming strategy which focuses on the most pertinent problem, (2) quick-turnaround analysis, (3) the evaluation of retrofittable design options through sensitivity analysis, and (4) coordination between the chief engineer and the hardware contractors. Advanced-technology concepts are being addressed via the definition of technology-development projects whose products are transferable to hardware programs and the integration of research activities with industry, government agencies, and universities, on the basis of the 'consortium' concept.

Space biology initiative program definition review. Trade study 3: Hardware miniaturization versus cost

NASA Technical Reports Server (NTRS)

Jackson, L. Neal; Crenshaw, John, Sr.; Davidson, William L.; Herbert, Frank J.; Bilodeau, James W.; Stoval, J. Michael; Sutton, Terry

1989-01-01

The optimum hardware miniaturization level with the lowest cost impact for space biology hardware was determined. Space biology hardware and/or components/subassemblies/assemblies which are the most likely candidates for application of miniaturization are to be defined and relative cost impacts of such miniaturization are to be analyzed. A mathematical or statistical analysis method with the capability to support development of parametric cost analysis impacts for levels of production design miniaturization are provided.

Real-Time Hardware-in-the-Loop Simulation of Ares I Launch Vehicle

NASA Technical Reports Server (NTRS)

Tobbe, Patrick; Matras, Alex; Walker, David; Wilson, Heath; Fulton, Chris; Alday, Nathan; Betts, Kevin; Hughes, Ryan; Turbe, Michael

2009-01-01

The Ares Real-Time Environment for Modeling, Integration, and Simulation (ARTEMIS) has been developed for use by the Ares I launch vehicle System Integration Laboratory at the Marshall Space Flight Center. The primary purpose of the Ares System Integration Laboratory is to test the vehicle avionics hardware and software in a hardware - in-the-loop environment to certify that the integrated system is prepared for flight. ARTEMIS has been designed to be the real-time simulation backbone to stimulate all required Ares components for verification testing. ARTE_VIIS provides high -fidelity dynamics, actuator, and sensor models to simulate an accurate flight trajectory in order to ensure realistic test conditions. ARTEMIS has been designed to take advantage of the advances in underlying computational power now available to support hardware-in-the-loop testing to achieve real-time simulation with unprecedented model fidelity. A modular realtime design relying on a fully distributed computing architecture has been implemented.

Correction Capability in the 3 Anatomic Planes of Different Pedicle Screw Designs in Scoliosis Instrumentation.

PubMed

Wang, Xiaoyu; Aubin, Carl-Eric; Coleman, John; Rawlinson, Jeremy

2017-05-01

Computer simulations to compare the correction capabilities of different pedicle screws in adolescent idiopathic scoliosis (AIS) instrumentations. To compare the correction and resulting bone-screw forces associated with different pedicle screws in scoliosis instrumentations. Pedicle screw fixation is widely used in surgical instrumentation for spinal deformity treatment. Screw design, correction philosophies, and surgical techniques are constantly evolving to achieve better control of the vertebrae and correction of the spinal deformity. Yet, there remains a lack of biomechanical studies that quantify the effects and advantages of different screw designs in terms of correction kinematics. The correction capabilities of fixed-angle, multiaxial, uniaxial, and saddle axial screws were kinematically analyzed, simulated, and compared. These simulations were based on the screw patterns and correction techniques proposed by 2 experienced surgeons for 2 AIS cases. Additional instrumentations were assessed to compare the correction and resulting bone-screw forces associated with each type of screw. The fixed-angle, uniaxial and saddle axial screws had similar kinematic behavior and performed better than multiaxial screws in the coronal and transverse planes (8% and 30% greater simulated corrections, respectively). Uniaxial and multiaxial screws were less effective than fixed-angle and saddle axial screws in transmitting compression/distraction to the anterior spine because of their sagittal plane mobility between the screw head and shank. Only the saddle axial screws allow vertebra angle in the sagittal plane to be independently adjusted. Pedicle screws of different designs performed differently for deformity corrections or for compensating screw placement variations in different anatomic planes. For a given AIS case, screw types should be determined based on the particular instrumentation objectives, the deformity's stiffness and characteristics so as to make the best of

Factors Influencing the Design, Establishment, Administration, and Governance of Correctional Education for Females

ERIC Educational Resources Information Center

Ellis, Johnica; McFadden, Cheryl; Colaric, Susan

2008-01-01

This article summarizes the results of a study conducted to investigate factors influencing the organizational design, establishment, administration, and governance of correctional education for females. The research involved interviews with correctional and community college administrators and practitioners representing North Carolina female…

Novel Principles and Techniques to Create a Natural Design in Female Hairline Correction Surgery.

PubMed

Park, Jae Hyun

2015-12-01

Female hairline correction surgery is becoming increasingly popular. However, no guidelines or methods of female hairline design have been introduced to date. The purpose of this study was to create an initial framework based on the novel principles of female hairline design and then use artistic ability and experience to fine tune this framework. An understanding of the concept of 5 areas (frontal area, frontotemporal recess area, temporal peak, infratemple area, and sideburns) and 5 points (C, A, B, T, and S) is required for female hairline correction surgery (the 5A5P principle). The general concepts of female hairline correction surgery and natural design methods are, herein, explained with a focus on the correlations between these 5 areas and 5 points. A natural and aesthetic female hairline can be created with application of the above-mentioned concepts. The 5A5P principle of forming the female hairline is very useful in female hairline correction surgery.

Novel Principles and Techniques to Create a Natural Design in Female Hairline Correction Surgery

PubMed Central

2015-01-01

Abstract Background: Female hairline correction surgery is becoming increasingly popular. However, no guidelines or methods of female hairline design have been introduced to date. Methods: The purpose of this study was to create an initial framework based on the novel principles of female hairline design and then use artistic ability and experience to fine tune this framework. An understanding of the concept of 5 areas (frontal area, frontotemporal recess area, temporal peak, infratemple area, and sideburns) and 5 points (C, A, B, T, and S) is required for female hairline correction surgery (the 5A5P principle). The general concepts of female hairline correction surgery and natural design methods are, herein, explained with a focus on the correlations between these 5 areas and 5 points. Results: A natural and aesthetic female hairline can be created with application of the above-mentioned concepts. Conclusion: The 5A5P principle of forming the female hairline is very useful in female hairline correction surgery. PMID:26894014

Low-power hardware implementation of movement decoding for brain computer interface with reduced-resolution discrete cosine transform.

PubMed

Minho Won; Albalawi, Hassan; Xin Li; Thomas, Donald E

2014-01-01

This paper describes a low-power hardware implementation for movement decoding of brain computer interface. Our proposed hardware design is facilitated by two novel ideas: (i) an efficient feature extraction method based on reduced-resolution discrete cosine transform (DCT), and (ii) a new hardware architecture of dual look-up table to perform discrete cosine transform without explicit multiplication. The proposed hardware implementation has been validated for movement decoding of electrocorticography (ECoG) signal by using a Xilinx FPGA Zynq-7000 board. It achieves more than 56× energy reduction over a reference design using band-pass filters for feature extraction.

Final Scientific/Technical Report for "Enabling Exascale Hardware and Software Design through Scalable System Virtualization"

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dinda, Peter August

2015-03-17

This report describes the activities, findings, and products of the Northwestern University component of the "Enabling Exascale Hardware and Software Design through Scalable System Virtualization" project. The purpose of this project has been to extend the state of the art of systems software for high-end computing (HEC) platforms, and to use systems software to better enable the evaluation of potential future HEC platforms, for example exascale platforms. Such platforms, and their systems software, have the goal of providing scientific computation at new scales, thus enabling new research in the physical sciences and engineering. Over time, the innovations in systems softwaremore » for such platforms also become applicable to more widely used computing clusters, data centers, and clouds. This was a five-institution project, centered on the Palacios virtual machine monitor (VMM) systems software, a project begun at Northwestern, and originally developed in a previous collaboration between Northwestern University and the University of New Mexico. In this project, Northwestern (including via our subcontract to the University of Pittsburgh) contributed to the continued development of Palacios, along with other team members. We took the leadership role in (1) continued extension of support for emerging Intel and AMD hardware, (2) integration and performance enhancement of overlay networking, (3) connectivity with architectural simulation, (4) binary translation, and (5) support for modern Non-Uniform Memory Access (NUMA) hosts and guests. We also took a supporting role in support for specialized hardware for I/O virtualization, profiling, configurability, and integration with configuration tools. The efforts we led (1-5) were largely successful and executed as expected, with code and papers resulting from them. The project demonstrated the feasibility of a virtualization layer for HEC computing, similar to such layers for cloud or datacenter computing. For effort (3

Hardware Trojans - Prevention, Detection, Countermeasures (A Literature Review)

DTIC Science & Technology

2011-07-01

Phase and Location . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Hardware Trojan Actions...12 3.4 Trigger Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Prevention 14 4.1 Prevention...The specification is then realised into specific tar- 4 UNCLASSIFIED UNCLASSIFIED DSTO–TN–1012 get technologies with consideration of functional and

Fastener Retention Requirements and Practices in Spaceflight Hardware

NASA Technical Reports Server (NTRS)

Dasgupta, Rajib

2004-01-01

This presentation reviews the requirements for safety critical fasteners in spaceflight hardware. Included in the presentation are design guidelines and information for Locking Helicoils, key locked inserts and thinwalled inserts, self locking screws and bolts. locknuts, and a locking adhesives, Loctite and Vibratite.

The Additional Secondary Phase Correction System for AIS Signals

PubMed Central

Wang, Xiaoye; Zhang, Shufang; Sun, Xiaowen

2017-01-01

This paper looks at the development and implementation of the additional secondary phase factor (ASF) real-time correction system for the Automatic Identification System (AIS) signal. A large number of test data were collected using the developed ASF correction system and the propagation characteristics of the AIS signal that transmits at sea and the ASF real-time correction algorithm of the AIS signal were analyzed and verified. Accounting for the different hardware of the receivers in the land-based positioning system and the variation of the actual environmental factors, the ASF correction system corrects original measurements of positioning receivers in real time and provides corrected positioning accuracy within 10 m. PMID:28362330

CASIS Fact Sheet: Hardware and Facilities

NASA Technical Reports Server (NTRS)

Solomon, Michael R.; Romero, Vergel

2016-01-01

Vencore is a proven information solutions, engineering, and analytics company that helps our customers solve their most complex challenges. For more than 40 years, we have designed, developed and delivered mission-critical solutions as our customers' trusted partner. The Engineering Services Contract, or ESC, provides engineering and design services to the NASA organizations engaged in development of new technologies at the Kennedy Space Center. Vencore is the ESC prime contractor, with teammates that include Stinger Ghaffarian Technologies, Sierra Lobo, Nelson Engineering, EASi, and Craig Technologies. The Vencore team designs and develops systems and equipment to be used for the processing of space launch vehicles, spacecraft, and payloads. We perform flight systems engineering for spaceflight hardware and software; develop technologies that serve NASA's mission requirements and operations needs for the future. Our Flight Payload Support (FPS) team at Kennedy Space Center (KSC) provides engineering, development, and certification services as well as payload integration and management services to NASA and commercial customers. Our main objective is to assist principal investigators (PIs) integrate their science experiments into payload hardware for research aboard the International Space Station (ISS), commercial spacecraft, suborbital vehicles, parabolic flight aircrafts, and ground-based studies. Vencore's FPS team is AS9100 certified and a recognized implementation partner for the Center for Advancement of Science in Space (CASIS

Requirements analysis for a hardware, discrete-event, simulation engine accelerator

NASA Astrophysics Data System (ADS)

Taylor, Paul J., Jr.

1991-12-01

An analysis of a general Discrete Event Simulation (DES), executing on the distributed architecture of an eight mode Intel PSC/2 hypercube, was performed. The most time consuming portions of the general DES algorithm were determined to be the functions associated with message passing of required simulation data between processing nodes of the hypercube architecture. A behavioral description, using the IEEE standard VHSIC Hardware Description and Design Language (VHDL), for a general DES hardware accelerator is presented. The behavioral description specifies the operational requirements for a DES coprocessor to augment the hypercube's execution of DES simulations. The DES coprocessor design implements the functions necessary to perform distributed discrete event simulations using a conservative time synchronization protocol.

Design and Development of Multi-Purpose CCD Camera System with Thermoelectric Cooling: Hardware

NASA Astrophysics Data System (ADS)

Kang, Y.-W.; Byun, Y. I.; Rhee, J. H.; Oh, S. H.; Kim, D. K.

2007-12-01

We designed and developed a multi-purpose CCD camera system for three kinds of CCDs; KAF-0401E(768×512), KAF-1602E(1536×1024), KAF-3200E(2184×1472) made by KODAK Co.. The system supports fast USB port as well as parallel port for data I/O and control signal. The packing is based on two stage circuit boards for size reduction and contains built-in filter wheel. Basic hardware components include clock pattern circuit, A/D conversion circuit, CCD data flow control circuit, and CCD temperature control unit. The CCD temperature can be controlled with accuracy of approximately 0.4° C in the max. range of temperature, Δ 33° C. This CCD camera system has with readout noise 6 e^{-}, and system gain 5 e^{-}/ADU. A total of 10 CCD camera systems were produced and our tests show that all of them show passable performance.

Energy Efficient Engine: High-pressure compressor test hardware detailed design report

NASA Technical Reports Server (NTRS)

Howe, David C.; Marchant, R. D.

1988-01-01

The objective of the NASA Energy Efficient Engine program is to identify and verify the technology required to achieve significant reductions in fuel consumption and operating cost for future commercial gas turbine engines. The design and analysis is documented of the high pressure compressor which was tested as part of the Pratt and Whitney effort under the Energy Efficient Engine program. This compressor was designed to produce a 14:1 pressure ratio in ten stages with an adiabatic efficiency of 88.2 percent in the flight propulsion system. The corresponding expected efficiency for the compressor component test rig is 86.5 percent. Other performance goals are a surge margin of 20 percent, a corrected flow rate of 35.2 kg/sec (77.5 lb/sec), and a life of 20,000 missions and 30,000 hours. Low loss, highly loaded airfoils are used to increase efficiency while reducing the parts count. Active clearance control and case trenches in abradable strips over the blade tips are included in the compressor component design to further increase the efficiency potential. The test rig incorporates variable geometry stator vanes in all stages to permit maximum flexibility in developing stage-to-stage matching. This provision precluded active clearance control on the rear case of the test rig. Both the component and rig designs meet or exceed design requirements with the exception of life goals, which will be achievable with planned advances in materials technology.

Round Girls in Square Computers: Feminist Perspectives on the Aesthetics of Computer Hardware.

ERIC Educational Resources Information Center

Carr-Chellman, Alison A.; Marra, Rose M.; Roberts, Shari L.

2002-01-01

Considers issues related to computer hardware, aesthetics, and gender. Explores how gender has influenced the design of computer hardware and how these gender-driven aesthetics may have worked to maintain, extend, or alter gender distinctions, roles, and stereotypes; discusses masculine media representations; and presents an alternative model.…

Design of the OMPS limb sensor correction algorithm

NASA Astrophysics Data System (ADS)

Jaross, Glen; McPeters, Richard; Seftor, Colin; Kowitt, Mark

The Sensor Data Records (SDR) for the Ozone Mapping and Profiler Suite (OMPS) on NPOESS (National Polar-orbiting Operational Environmental Satellite System) contains geolocated and calibrated radiances, and are similar to the Level 1 data of NASA Earth Observing System and other programs. The SDR algorithms (one for each of the 3 OMPS focal planes) are the processes by which the Raw Data Records (RDR) from the OMPS sensors are converted into the records that contain all data necessary for ozone retrievals. Consequently, the algorithms must correct and calibrate Earth signals, geolocate the data, and identify and ingest collocated ancillary data. As with other limb sensors, ozone profile retrievals are relatively insensitive to calibration errors due to the use of altitude normalization and wavelength pairing. But the profile retrievals as they pertain to OMPS are not immune from sensor changes. In particular, the OMPS Limb sensor images an altitude range of > 100 km and a spectral range of 290-1000 nm on its detector. Uncorrected sensor degradation and spectral registration drifts can lead to changes in the measured radiance profile, which in turn affects the ozone trend measurement. Since OMPS is intended for long-term monitoring, sensor calibration is a specific concern. The calibration is maintained via the ground data processing. This means that all sensor calibration data, including direct solar measurements, are brought down in the raw data and processed separately by the SDR algorithms. One of the sensor corrections performed by the algorithm is the correction for stray light. The imaging spectrometer and the unique focal plane design of OMPS makes these corrections particularly challenging and important. Following an overview of the algorithm flow, we will briefly describe the sensor stray light characterization and the correction approach used in the code.

Hardware architecture for projective model calculation and false match refining using random sample consensus algorithm

NASA Astrophysics Data System (ADS)

Azimi, Ehsan; Behrad, Alireza; Ghaznavi-Ghoushchi, Mohammad Bagher; Shanbehzadeh, Jamshid

2016-11-01

The projective model is an important mapping function for the calculation of global transformation between two images. However, its hardware implementation is challenging because of a large number of coefficients with different required precisions for fixed point representation. A VLSI hardware architecture is proposed for the calculation of a global projective model between input and reference images and refining false matches using random sample consensus (RANSAC) algorithm. To make the hardware implementation feasible, it is proved that the calculation of the projective model can be divided into four submodels comprising two translations, an affine model and a simpler projective mapping. This approach makes the hardware implementation feasible and considerably reduces the required number of bits for fixed point representation of model coefficients and intermediate variables. The proposed hardware architecture for the calculation of a global projective model using the RANSAC algorithm was implemented using Verilog hardware description language and the functionality of the design was validated through several experiments. The proposed architecture was synthesized by using an application-specific integrated circuit digital design flow utilizing 180-nm CMOS technology as well as a Virtex-6 field programmable gate array. Experimental results confirm the efficiency of the proposed hardware architecture in comparison with software implementation.

Preliminary control law and hardware designs for a ride quality augmentation system for commuter aircraft. Phase 2

NASA Technical Reports Server (NTRS)

Davis, D. J.; Linse, D. J.; Suikat, R.; Entz, D. P.

1986-01-01

The continued investigation of the design of Ride Quality Augmentation Systems (RQAS) for commuter aircraft is described. The purpose of these RQAS is the reduction of the vertical and lateral acceleration response of the aircraft due to atmospheric turbulence by the application of active control. The current investigations include the refinement of the sample data feedback control laws based on the control-rate-weighting and output-weighting optimal control design techniqes. These control designs were evaluated using aircraft time simulations driven by Dryden spectra turbulence. Fixed gain controllers were tested throughout the aircrft operating envelope. The preliminary design of the hardware modifications necessary to implement and test the RQAS on a commuter aircraft is included. These include a separate surface elevator and the flap modifications to provide both direct lift and roll control. A preliminary failure mode investigation was made for the proposed configuration. The results indicate that vertical acceleration reductions of 45% and lateral reductions of more than 50% are possible. A fixed gain controller appears to be feasible with only minor response degradation.

Open source hardware and software platform for robotics and artificial intelligence applications

NASA Astrophysics Data System (ADS)

Liang, S. Ng; Tan, K. O.; Lai Clement, T. H.; Ng, S. K.; Mohammed, A. H. Ali; Mailah, Musa; Azhar Yussof, Wan; Hamedon, Zamzuri; Yussof, Zulkifli

2016-02-01

Recent developments in open source hardware and software platforms (Android, Arduino, Linux, OpenCV etc.) have enabled rapid development of previously expensive and sophisticated system within a lower budget and flatter learning curves for developers. Using these platform, we designed and developed a Java-based 3D robotic simulation system, with graph database, which is integrated in online and offline modes with an Android-Arduino based rubbish picking remote control car. The combination of the open source hardware and software system created a flexible and expandable platform for further developments in the future, both in the software and hardware areas, in particular in combination with graph database for artificial intelligence, as well as more sophisticated hardware, such as legged or humanoid robots.

A Flexible Hardware Test and Demonstration Platform for the Fractionated System Architecture YETE

NASA Astrophysics Data System (ADS)

Kempf, Florian; Haber, Roland; Tzschichholz, Tristan; Mikschl, Tobias; Hilgarth, Alexander; Montenegro, Sergio; Schilling, Klaus

2016-08-01

This paper introduces a hardware-in-the loop test and demonstration platform for the YETE system architecture for fractionated spacecraft. It is designed for rapid prototyping and testing of distributed control approaches for the YETE architecture subject to varying network topologies and transmission channel properties between the individual YETE hardware nodes.

Characterization and correction of cupping effect artefacts in cone beam CT

PubMed Central

Hunter, AK; McDavid, WD

2012-01-01

Objective The purpose of this study was to demonstrate and correct the cupping effect artefact that occurs owing to the presence of beam hardening and scatter radiation during image acquisition in cone beam CT (CBCT). Methods A uniform aluminium cylinder (6061) was used to demonstrate the cupping effect artefact on the Planmeca Promax 3D CBCT unit (Planmeca OY, Helsinki, Finland). The cupping effect was studied using a line profile plot of the grey level values using ImageJ software (National Institutes of Health, Bethesda, MD). A hardware-based correction method using copper pre-filtration was used to address this artefact caused by beam hardening and a software-based subtraction algorithm was used to address scatter contamination. Results The hardware-based correction used to address the effects of beam hardening suppressed the cupping effect artefact but did not eliminate it. The software-based correction used to address the effects of scatter resulted in elimination of the cupping effect artefact. Conclusion Compensating for the presence of beam hardening and scatter radiation improves grey level uniformity in CBCT. PMID:22378754

Pre-Hardware Optimization of Spacecraft Image Processing Software Algorithms and Hardware Implementation

NASA Technical Reports Server (NTRS)

Kizhner, Semion; Flatley, Thomas P.; Hestnes, Phyllis; Jentoft-Nilsen, Marit; Petrick, David J.; Day, John H. (Technical Monitor)

2001-01-01

Spacecraft telemetry rates have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image processing application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms and re-configurable computing hardware technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processing (DSP). It has been shown in [1] and [2] that this configuration can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft. However, since this technology is still maturing, intensive pre-hardware steps are necessary to achieve the benefits of hardware implementation. This paper describes these steps for the GOES-8 application, a software project developed using Interactive Data Language (IDL) (Trademark of Research Systems, Inc.) on a Workstation/UNIX platform. The solution involves converting the application to a PC/Windows/RC platform, selected mainly by the availability of low cost, adaptable high-speed RC hardware. In order for the hybrid system to run, the IDL software was modified to account for platform differences. It was interesting to examine the gains and losses in performance on the new platform, as well as unexpected observations before implementing hardware. After substantial pre-hardware optimization steps, the necessity of hardware implementation for bottleneck code in the PC environment became evident and solvable beginning with the methodology described in [1], [2], and implementing a novel methodology for this specific application [6]. The PC-RC interface bandwidth problem for the

Scaling Retro-Commissioning to Small Commercial Buildings: A Turnkey Automated Hardware-Software Solution

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lin, Guanjing; Granderson, J.; Brambley, Michael R.

2015-07-01

In the United States, small commercial buildings represent 51% of total floor space of all commercial buildings and consume nearly 3 quadrillion Btu (3.2 quintillion joule) of site energy annually, presenting an enormous opportunity for energy savings. Retro-commissioning (RCx), the process through which professional energy service providers identify and correct operational problems, has proven to be a cost-effective means to achieve median energy savings of 16%. However, retro-commissioning is not typically conducted at scale throughout the commercial stock. Very few small commercial buildings are retro-commissioned because utility expenses are relatively modest, margins are tighter, and capital for improvements is limited.more » In addition, small buildings do not have in-house staff with the expertise to identify improvement opportunities. In response, a turnkey hardware-software solution was developed to enable cost-effective, monitoring-based RCx of small commercial buildings. This highly tailored solution enables non-commissioning providers to identify energy and comfort problems, as well as associated cost impacts and remedies. It also facilitates scale by offering energy service providers the means to streamline their existing processes and reduce costs by more than half. The turnkey RCx sensor suitcase consists of two primary components: a suitcase of sensors for short-term building data collection that guides users through the process of deploying and retrieving their data and a software application that automates analysis of sensor data, identifies problems and generates recommendations. This paper presents the design and testing of prototype models, including descriptions of the hardware design, analysis algorithms, performance testing, and plans for dissemination.« less

Ripple-aware optical proximity correction fragmentation for back-end-of-line designs

NASA Astrophysics Data System (ADS)

Wang, Jingyu; Wilkinson, William

2018-01-01

Accurate characterization of image rippling is critical in early detection of back-end-of-line (BEOL) patterning weakpoints, as most defects are strongly associated with excessive rippling that does not get effectively compensated by optical proximity correction (OPC). We correlate image contour with design shapes to account for design geometry-dependent rippling signature, and explore the best practice of OPC fragmentation for BEOL geometries. Specifically, we predict the optimum contour as allowed by the lithographic process and illumination conditions and locate ripple peaks, valleys, and inflection points. This allows us to identify potential process weakpoints and segment the mask accordingly to achieve the best correction results.

On verifying a high-level design. [cost and error analysis

NASA Technical Reports Server (NTRS)

Mathew, Ben; Wehbeh, Jalal A.; Saab, Daniel G.

1993-01-01

An overview of design verification techniques is presented, and some of the current research in high-level design verification is described. Formal hardware description languages that are capable of adequately expressing the design specifications have been developed, but some time will be required before they can have the expressive power needed to be used in real applications. Simulation-based approaches are more useful in finding errors in designs than they are in proving the correctness of a certain design. Hybrid approaches that combine simulation with other formal design verification techniques are argued to be the most promising over the short term.

New Directions for Hardware-assisted Trusted Computing Policies (Position Paper)

NASA Astrophysics Data System (ADS)

Bratus, Sergey; Locasto, Michael E.; Ramaswamy, Ashwin; Smith, Sean W.

The basic technological building blocks of the TCG architecture seem to be stabilizing. As a result, we believe that the focus of the Trusted Computing (TC) discipline must naturally shift from the design and implementation of the hardware root of trust (and the subsequent trust chain) to the higher-level application policies. Such policies must build on these primitives to express new sets of security goals. We highlight the relationship between enforcing these types of policies and debugging, since both activities establish the link between expected and actual application behavior. We argue that this new class of policies better fits developers' mental models of expected application behaviors, and we suggest a hardware design direction for enabling the efficient interpretation of such policies.

Open Source Hardware for DIY Environmental Sensing

NASA Astrophysics Data System (ADS)

Aufdenkampe, A. K.; Hicks, S. D.; Damiano, S. G.; Montgomery, D. S.

2014-12-01

The Arduino open source electronics platform has been very popular within the DIY (Do It Yourself) community for several years, and it is now providing environmental science researchers with an inexpensive alternative to commercial data logging and transmission hardware. Here we present the designs for our latest series of custom Arduino-based dataloggers, which include wireless communication options like self-meshing radio networks and cellular phone modules. The main Arduino board uses a custom interface board to connect to various research-grade sensors to take readings of turbidity, dissolved oxygen, water depth and conductivity, soil moisture, solar radiation, and other parameters. Sensors with SDI-12 communications can be directly interfaced to the logger using our open Arduino-SDI-12 software library (https://github.com/StroudCenter/Arduino-SDI-12). Different deployment options are shown, like rugged enclosures to house the loggers and rigs for mounting the sensors in both fresh water and marine environments. After the data has been collected and transmitted by the logger, the data is received by a mySQL-PHP stack running on a web server that can be accessed from anywhere in the world. Once there, the data can be visualized on web pages or served though REST requests and Water One Flow (WOF) services. Since one of the main benefits of using open source hardware is the easy collaboration between users, we are introducing a new web platform for discussion and sharing of ideas and plans for hardware and software designs used with DIY environmental sensors and data loggers.

Color correction strategies in optical design

NASA Astrophysics Data System (ADS)

Pfisterer, Richard N.; Vorndran, Shelby D.

2014-12-01

An overview of color correction strategies is presented. Starting with basic first-order aberration theory, we identify known color corrected solutions for doublets and triplets. Reviewing the modern approaches of Robb-Mercado, Rayces-Aguilar, and C. de Albuquerque et al, we find that they confirm the existence of glass combinations for doublets and triplets that yield color corrected solutions that we already know exist. Finally we explore the use of the y, ӯ diagram in conjunction with aberration theory to identify the solution space of glasses capable of leading to color corrected solutions in arbitrary optical systems.

Optically buffered Jones-matrix-based multifunctional optical coherence tomography with polarization mode dispersion correction

PubMed Central

Hong, Young-Joo; Makita, Shuichi; Sugiyama, Satoshi; Yasuno, Yoshiaki

2014-01-01

Polarization mode dispersion (PMD) degrades the performance of Jones-matrix-based polarization-sensitive multifunctional optical coherence tomography (JM-OCT). The problem is specially acute for optically buffered JM-OCT, because the long fiber in the optical buffering module induces a large amount of PMD. This paper aims at presenting a method to correct the effect of PMD in JM-OCT. We first mathematically model the PMD in JM-OCT and then derive a method to correct the PMD. This method is a combination of simple hardware modification and subsequent software correction. The hardware modification is introduction of two polarizers which transform the PMD into global complex modulation of Jones matrix. Subsequently, the software correction demodulates the global modulation. The method is validated with an experimentally obtained point spread function with a mirror sample, as well as by in vivo measurement of a human retina. PMID:25657888

Eye gaze correction with stereovision for video-teleconferencing.

PubMed

Yang, Ruigang; Zhang, Zhengyou

2004-07-01

The lack of eye contact in desktop video teleconferencing substantially reduces the effectiveness of video contents. While expensive and bulky hardware is available on the market to correct eye gaze, researchers have been trying to provide a practical software-based solution to bring video-teleconferencing one step closer to the mass market. This paper presents a novel approach: Based on stereo analysis combined with rich domain knowledge (a personalized face model), we synthesize, using graphics hardware, a virtual video that maintains eye contact. A 3D stereo head tracker with a personalized face model is used to compute initial correspondences across two views. More correspondences are then added through template and feature matching. Finally, all the correspondence information is fused together for view synthesis using view morphing techniques. The combined methods greatly enhance the accuracy and robustness of the synthesized views. Our current system is able to generate an eye-gaze corrected video stream at five frames per second on a commodity 1 GHz PC.

Generation of Unbiased Ionospheric Corrections in Brazilian Region for GNSS positioning based on SSR concept

NASA Astrophysics Data System (ADS)

Monico, J. F. G.; De Oliveira, P. S., Jr.; Morel, L.; Fund, F.; Durand, S.; Durand, F.

2017-12-01

Mitigation of ionospheric effects on GNSS (Global Navigation Satellite System) signals is very challenging, especially for GNSS positioning applications based on SSR (State Space Representation) concept, which requires the knowledge of spatial correlated errors with considerable accuracy level (centimeter). The presence of satellite and receiver hardware biases on GNSS measurements difficult the proper estimation of ionospheric corrections, reducing their physical meaning. This problematic can lead to ionospheric corrections biased of several meters and often presenting negative values, which is physically not possible. In this contribution, we discuss a strategy to obtain SSR ionospheric corrections based on GNSS measurements from CORS (Continuous Operation Reference Stations) Networks with minimal presence of hardware biases and consequently physical meaning. Preliminary results are presented on generation and application of such corrections for simulated users located in Brazilian region under high level of ionospheric activity.

The VLSI design of the sub-band filterbank in MP3 decoding

NASA Astrophysics Data System (ADS)

Liu, Jia-Xin; Luo, Li

2018-03-01

The sub-band filterbank is one of the most important modules which has the largest amount of calculation in MP3 decoding. In order to save CPU resources and integrate the sub-band filterbank part into MP3 IP core, the hardware circuit of the sub-band filterbank module is designed in this paper. A fast algorithm suit for hardware implementation is proposed and achieved on FPGA development board. The results show that the sub-band filterbank function is correct in the case of using very few registers and the amount of calculation and ROM resources are reduced greatly.

Utility of an emulation and simulation computer model for air revitalization system hardware design, development, and test

NASA Technical Reports Server (NTRS)

Yanosy, J. L.; Rowell, L. F.

1985-01-01

Efforts to make increasingly use of suitable computer programs in the design of hardware have the potential to reduce expenditures. In this context, NASA has evaluated the benefits provided by software tools through an application to the Environmental Control and Life Support (ECLS) system. The present paper is concerned with the benefits obtained by an employment of simulation tools in the case of the Air Revitalization System (ARS) of a Space Station life support system. Attention is given to the ARS functions and components, a computer program overview, a SAND (solid amine water desorbed) bed model description, a model validation, and details regarding the simulation benefits.

Hardware system of X-wave generator with simple driving pulses

NASA Astrophysics Data System (ADS)

Li, Xu; Li, Yaqin; Xiao, Feng; Ding, Mingyue; Yuchi, Ming

2013-03-01

The limited diffraction beams such as X-wave have the properties of larger depth of field. Thus, it has the potential to generate ultra-high frame rate ultrasound images. However, in practice, the real-time generation of X-wave ultrasonic field requires complex and high-cost system, especially the precise and specific voltage time distribution part for the excitation of each distinct array element. In order to simplify the hardware realization of X-wave, based on the previous works, X-wave excitation signals were decomposed and expressed as the superposition of a group of simple driving pulses, such as rectangular and triangular waves. The hardware system for the X-wave generator was also designed. The generator consists of a computer for communication with the circuit, universal serial bus (USB) based micro-controller unit (MCU) for data transmission, field programmable gate array (FPGA) based Direct Digital Synthesizer(DDS), 12-bit digital-to-analog (D/A) converter and a two stage amplifier.The hardware simulation results show that the designed system can generate the waveforms at different radius approximating the theoretical X-wave excitations with a maximum error of 0.49% triggered by the quantification of amplitude data.

Programming languages and compiler design for realistic quantum hardware.

PubMed

Chong, Frederic T; Franklin, Diana; Martonosi, Margaret

2017-09-13

Quantum computing sits at an important inflection point. For years, high-level algorithms for quantum computers have shown considerable promise, and recent advances in quantum device fabrication offer hope of utility. A gap still exists, however, between the hardware size and reliability requirements of quantum computing algorithms and the physical machines foreseen within the next ten years. To bridge this gap, quantum computers require appropriate software to translate and optimize applications (toolflows) and abstraction layers. Given the stringent resource constraints in quantum computing, information passed between layers of software and implementations will differ markedly from in classical computing. Quantum toolflows must expose more physical details between layers, so the challenge is to find abstractions that expose key details while hiding enough complexity.

Programming languages and compiler design for realistic quantum hardware

NASA Astrophysics Data System (ADS)

Chong, Frederic T.; Franklin, Diana; Martonosi, Margaret

2017-09-01

Quantum computing sits at an important inflection point. For years, high-level algorithms for quantum computers have shown considerable promise, and recent advances in quantum device fabrication offer hope of utility. A gap still exists, however, between the hardware size and reliability requirements of quantum computing algorithms and the physical machines foreseen within the next ten years. To bridge this gap, quantum computers require appropriate software to translate and optimize applications (toolflows) and abstraction layers. Given the stringent resource constraints in quantum computing, information passed between layers of software and implementations will differ markedly from in classical computing. Quantum toolflows must expose more physical details between layers, so the challenge is to find abstractions that expose key details while hiding enough complexity.

Electronic processing and control system with programmable hardware

NASA Technical Reports Server (NTRS)

Alkalaj, Leon (Inventor); Fang, Wai-Chi (Inventor); Newell, Michael A. (Inventor)

1998-01-01

A computer system with reprogrammable hardware allowing dynamically allocating hardware resources for different functions and adaptability for different processors and different operating platforms. All hardware resources are physically partitioned into system-user hardware and application-user hardware depending on the specific operation requirements. A reprogrammable interface preferably interconnects the system-user hardware and application-user hardware.

Real Time Target Tracking Using Dedicated Vision Hardware

NASA Astrophysics Data System (ADS)

Kambies, Keith; Walsh, Peter

1988-03-01

This paper describes a real-time vision target tracking system developed by Adaptive Automation, Inc. and delivered to NASA's Launch Equipment Test Facility, Kennedy Space Center, Florida. The target tracking system is part of the Robotic Application Development Laboratory (RADL) which was designed to provide NASA with a general purpose robotic research and development test bed for the integration of robot and sensor systems. One of the first RADL system applications is the closing of a position control loop around a six-axis articulated arm industrial robot using a camera and dedicated vision processor as the input sensor so that the robot can locate and track a moving target. The vision system is inside of the loop closure of the robot tracking system, therefore, tight throughput and latency constraints are imposed on the vision system that can only be met with specialized hardware and a concurrent approach to the processing algorithms. State of the art VME based vision boards capable of processing the image at frame rates were used with a real-time, multi-tasking operating system to achieve the performance required. This paper describes the high speed vision based tracking task, the system throughput requirements, the use of dedicated vision hardware architecture, and the implementation design details. Important to the overall philosophy of the complete system was the hierarchical and modular approach applied to all aspects of the system, hardware and software alike, so there is special emphasis placed on this topic in the paper.

Hardware test program for evaluation of baseline range/range rate sensor concept

NASA Technical Reports Server (NTRS)

1985-01-01

The Hardware Test Program for evaluation of the baseline range/range rate sensor concept was initiated 11 September 1984. This ninth report covers the period 12 May through 11 June 1885. A contract amendment adding a second phase has extended the Hardware Test Program through 10 December 1985. The objective of the added program phase is to establish range and range measurement accuracy and radar signature characteristics for a typical spacecraft target. Phase I of the Hardware Test Program was designed to reduce the risks associated with the Range/Range Rate (R/R) Sensor baseline design approach. These risks are associated with achieving the sensor performance required for the two modes of operation, the Interrupted CW (ICW) mode for initial acquisition and tracking to close-in ranges, and the CW mode, providing coverage during the final docking maneuver. The risks associated with these modes of operation have to do with the realization of adequate sensitivity to operate to their individual maximum ranges.

Hardware Design and Implementation of a Wavelet De-Noising Procedure for Medical Signal Preprocessing

PubMed Central

Chen, Szi-Wen; Chen, Yuan-Ho

2015-01-01

In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz. PMID:26501290

Hardware design and implementation of a wavelet de-noising procedure for medical signal preprocessing.

PubMed

Chen, Szi-Wen; Chen, Yuan-Ho

2015-10-16

In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz.

Highly efficient simulation environment for HDTV video decoder in VLSI design

NASA Astrophysics Data System (ADS)

Mao, Xun; Wang, Wei; Gong, Huimin; He, Yan L.; Lou, Jian; Yu, Lu; Yao, Qingdong; Pirsch, Peter

2002-01-01

With the increase of the complex of VLSI such as the SoC (System on Chip) of MPEG-2 Video decoder with HDTV scalability especially, simulation and verification of the full design, even as high as the behavior level in HDL, often proves to be very slow, costly and it is difficult to perform full verification until late in the design process. Therefore, they become bottleneck of the procedure of HDTV video decoder design, and influence it's time-to-market mostly. In this paper, the architecture of Hardware/Software Interface of HDTV video decoder is studied, and a Hardware-Software Mixed Simulation (HSMS) platform is proposed to check and correct error in the early design stage, based on the algorithm of MPEG-2 video decoding. The application of HSMS to target system could be achieved by employing several introduced approaches. Those approaches speed up the simulation and verification task without decreasing performance.

Structural Design Requirements and Factors of Safety for Spaceflight Hardware: For Human Spaceflight. Revision A

NASA Technical Reports Server (NTRS)

Bernstein, Karen S.; Kujala, Rod; Fogt, Vince; Romine, Paul

2011-01-01

This document establishes the structural requirements for human-rated spaceflight hardware including launch vehicles, spacecraft and payloads. These requirements are applicable to Government Furnished Equipment activities as well as all related contractor, subcontractor and commercial efforts. These requirements are not imposed on systems other than human-rated spacecraft, such as ground test articles, but may be tailored for use in specific cases where it is prudent to do so such as for personnel safety or when assets are at risk. The requirements in this document are focused on design rather than verification. Implementation of the requirements is expected to be described in a Structural Verification Plan (SVP), which should describe the verification of each structural item for the applicable requirements. The SVP may also document unique verifications that meet or exceed these requirements with NASA Technical Authority approval.

Performance of the Extravehicular Mobility Unit (EMU) Airlock Coolant Loop Remediation (A/L CLR) Hardware - Final

NASA Technical Reports Server (NTRS)

Steele, John W.; Rector, Tony; Gazda, Daniel; Lewis, John

2011-01-01

An EMU water processing kit (Airlock Coolant Loop Recovery -- A/L CLR) was developed as a corrective action to Extravehicular Mobility Unit (EMU) coolant flow disruptions experienced on the International Space Station (ISS) in May of 2004 and thereafter. A conservative duty cycle and set of use parameters for A/L CLR use and component life were initially developed and implemented based on prior analysis results and analytical modeling. Several initiatives were undertaken to optimize the duty cycle and use parameters of the hardware. Examination of post-flight samples and EMU Coolant Loop hardware provided invaluable information on the performance of the A/L CLR and has allowed for an optimization of the process. The intent of this paper is to detail the evolution of the A/L CLR hardware, efforts to optimize the duty cycle and use parameters, and the final recommendations for implementation in the post-Shuttle retirement era.

Analysis of a hardware and software fault tolerant processor for critical applications

NASA Technical Reports Server (NTRS)

Dugan, Joanne B.

1993-01-01

Computer systems for critical applications must be designed to tolerate software faults as well as hardware faults. A unified approach to tolerating hardware and software faults is characterized by classifying faults in terms of duration (transient or permanent) rather than source (hardware or software). Errors arising from transient faults can be handled through masking or voting, but errors arising from permanent faults require system reconfiguration to bypass the failed component. Most errors which are caused by software faults can be considered transient, in that they are input-dependent. Software faults are triggered by a particular set of inputs. Quantitative dependability analysis of systems which exhibit a unified approach to fault tolerance can be performed by a hierarchical combination of fault tree and Markov models. A methodology for analyzing hardware and software fault tolerant systems is applied to the analysis of a hypothetical system, loosely based on the Fault Tolerant Parallel Processor. The models consider both transient and permanent faults, hardware and software faults, independent and related software faults, automatic recovery, and reconfiguration.

EUV process improvement with novel litho track hardware

NASA Astrophysics Data System (ADS)

Stokes, Harold; Harumoto, Masahiko; Tanaka, Yuji; Kaneyama, Koji; Pieczulewski, Charles; Asai, Masaya

2017-03-01

Currently, there are many developments in the field of EUV lithography that are helping to move it towards increased HVM feasibility. Targeted improvements in hardware design for advanced lithography are of interest to our group specifically for metrics such as CD uniformity, LWR, and defect density. Of course, our work is focused on EUV process steps that are specifically affected by litho track performance, and consequently, can be improved by litho track design improvement and optimization. In this study we are building on our experience to provide continual improvement for LWR, CDU, and Defects as applied to a standard EUV process by employing novel hardware solutions on our SOKUDO DUO coat develop track system. Although it is preferable to achieve such improvements post-etch process we feel, as many do, that improvements after patterning are a precursor to improvements after etching. We hereby present our work utilizing the SOKUDO DUO coat develop track system with an ASML NXE:3300 in the IMEC (Leuven, Belgium) cleanroom environment to improve aggressive dense L/S patterns.

Streamlined design and self reliant hardware for active control of precision space structures

NASA Technical Reports Server (NTRS)

Hyland, David C.; King, James A.; Phillips, Douglas J.

1994-01-01

Precision space structures may require active vibration control to satisfy critical performance requirements relating to line-of-sight pointing accuracy and the maintenance of precise, internal alignments. In order for vibration control concepts to become operational, it is necessary that their benefits be practically demonstrated in large scale ground-based experiments. A unique opportunity to carry out such demonstrations on a wide variety of experimental testbeds was provided by the NASA Control-Structure Integration (CSI) Guest Investigator (GI) Program. This report surveys the experimental results achieved by the Harris Corporation GI team on both Phases 1 and 2 of the program and provides a detailed description of Phase 2 activities. The Phase 1 results illustrated the effectiveness of active vibration control for space structures and demonstrated a systematic methodology for control design, implementation test. In Phase 2, this methodology was significantly streamlined to yield an on-site, single session design/test capability. Moreover, the Phase 2 research on adaptive neural control techniques made significant progress toward fully automated, self-reliant space structure control systems. As a further thrust toward productized, self-contained vibration control systems, the Harris Phase II activity concluded with experimental demonstration of new vibration isolation hardware suitable for a wide range of space-flight and ground-based commercial applications.The CSI GI Program Phase 1 activity was conducted under contract NASA1-18872, and the Phase 2 activity was conducted under NASA1-19372.

Test Program for Stirling Radioisotope Generator Hardware at NASA Glenn Research Center

NASA Technical Reports Server (NTRS)

Lewandowski, Edward J.; Bolotin, Gary S.; Oriti, Salvatore M.

2015-01-01

Stirling-based energy conversion technology has demonstrated the potential of high efficiency and low mass power systems for future space missions. This capability is beneficial, if not essential, to making certain deep space missions possible. Significant progress was made developing the Advanced Stirling Radioisotope Generator (ASRG), a 140-W radioisotope power system. A variety of flight-like hardware, including Stirling convertors, controllers, and housings, was designed and built under the ASRG flight development project. To support future Stirling-based power system development NASA has proposals that, if funded, will allow this hardware to go on test at the NASA Glenn Research Center. While future flight hardware may not be identical to the hardware developed under the ASRG flight development project, many components will likely be similar, and system architectures may have heritage to ASRG. Thus, the importance of testing the ASRG hardware to the development of future Stirling-based power systems cannot be understated. This proposed testing will include performance testing, extended operation to establish an extensive reliability database, and characterization testing to quantify subsystem and system performance and better understand system interfaces. This paper details this proposed test program for Stirling radioisotope generator hardware at NASA Glenn. It explains the rationale behind the proposed tests and how these tests will meet the stated objectives.

An evaluation of Skylab habitability hardware

NASA Technical Reports Server (NTRS)

Stokes, J.

1974-01-01

For effective mission performance, participants in space missions lasting 30-60 days or longer must be provided with hardware to accommodate their personal needs. Such habitability hardware was provided on Skylab. Equipment defined as habitability hardware was that equipment composing the food system, water system, sleep system, waste management system, personal hygiene system, trash management system, and entertainment equipment. Equipment not specifically defined as habitability hardware but which served that function were the Wardroom window, the exercise equipment, and the intercom system, which was occasionally used for private communications. All Skylab habitability hardware generally functioned as intended for the three missions, and most items could be considered as adequate concepts for future flights of similar duration. Specific components were criticized for their shortcomings.

16 CFR 1508.6 - Hardware.

Code of Federal Regulations, 2011 CFR

2011-01-01

... eliminates from any hardware accessible to a child within the crib the possibility of the hardware's... foreseeable damage or abuse. (b) Locking or latching devices used to secure dropside rails shall require a...

16 CFR 1508.6 - Hardware.

Code of Federal Regulations, 2010 CFR

2010-01-01

... eliminates from any hardware accessible to a child within the crib the possibility of the hardware's... foreseeable damage or abuse. (b) Locking or latching devices used to secure dropside rails shall require a...

DDL:Digital systems design language

NASA Technical Reports Server (NTRS)

Shival, S. G.

1980-01-01

Hardware description languages are valuable tools in such applications as hardware design, system documentation, and logic design training. DDL is convenient medium for inputting design details into hardware-design automation system. It is suitable for describing digital systems at gate, register transfer, and major combinational block level.

A Framework for Assessing the Reusability of Hardware (Reusable Rocket Engines)

NASA Technical Reports Server (NTRS)

Childress-Thompson, Rhonda; Farrington, Philip; Thomas, Dale

2016-01-01

Within the space flight community, reusability has taken center stage as the new buzzword. In order for reusable hardware to be competitive with its expendable counterpart, two major elements must be closely scrutinized. First, recovery and refurbishment costs must be lower than the development and acquisition costs. Additionally, the reliability for reused hardware must remain the same (or nearly the same) as "first use" hardware. Therefore, it is imperative that a systematic approach be established to enhance the development of reusable systems. However, before the decision can be made on whether it is more beneficial to reuse hardware or to replace it, the parameters that are needed to deem hardware worthy of reuse must be identified. For reusable hardware to be successful, the factors that must be considered are reliability (integrity, life, number of uses), operability (maintenance, accessibility), and cost (procurement, retrieval, refurbishment). These three factors are essential to the successful implementation of reusability while enabling the ability to meet performance goals. Past and present strategies and attempts at reuse within the space industry will be examined to identify important attributes of reusability that can be used to evaluate hardware when contemplating reusable versus expendable options. This paper will examine why reuse must be stated as an initial requirement rather than included as an afterthought in the final design. Late in the process, changes in the overall objective/purpose of components typically have adverse effects that potentially negate the benefits. A methodology for assessing the viability of reusing hardware will be presented by using the Space Shuttle Main Engine (SSME) to validate the approach. Because reliability, operability, and costs are key drivers in making this critical decision, they will be used to assess requirements for reuse as applied to components of the SSME.

Environmental Conditions for Space Flight Hardware: A Survey

NASA Technical Reports Server (NTRS)

Plante, Jeannette; Lee, Brandon

2005-01-01

Interest in generalization of the physical environment experienced by NASA hardware from the natural Earth environment (on the launch pad), man-made environment on Earth (storage acceptance an d qualification testing), the launch environment, and the space environment, is ed to find commonality among our hardware in an effort to reduce cost and complexity. NASA is entering a period of increase in its number of planetary missions and it is important to understand how our qualification requirements will evolve with and track these new environments. Environmental conditions are described for NASA projects in several ways for the different periods of the mission life cycle. At the beginning, the mission manager defines survivability requirements based on the mission length, orbit, launch date, launch vehicle, and other factors . such as the use of reactor engines. Margins are then applied to these values (temperature extremes, vibration extremes, radiation tolerances, etc,) and a new set of conditions is generalized for design requirements. Mission assurance documents will then assign an additional margin for reliability, and a third set of values is provided for during testing. A fourth set of environmental condition values may evolve intermittently from heritage hardware that has been tested to a level beyond the actual mission requirement. These various sets of environment figures can make it quite confusing and difficult to capture common hardware environmental requirements. Environmental requirement information can be found in a wide variety of places. The most obvious is with the individual projects. We can easily get answers to questions about temperature extremes being used and radiation tolerance goals, but it is more difficult to map the answers to the process that created these requirements: for design, for qualification, and for actual environment with no margin applied. Not everyone assigned to a NASA project may have that kind of insight, as many have

Hardware design and implementation of fast DOA estimation method based on multicore DSP

NASA Astrophysics Data System (ADS)

Guo, Rui; Zhao, Yingxiao; Zhang, Yue; Lin, Qianqiang; Chen, Zengping

2016-10-01

In this paper, we present a high-speed real-time signal processing hardware platform based on multicore digital signal processor (DSP). The real-time signal processing platform shows several excellent characteristics including high performance computing, low power consumption, large-capacity data storage and high speed data transmission, which make it able to meet the constraint of real-time direction of arrival (DOA) estimation. To reduce the high computational complexity of DOA estimation algorithm, a novel real-valued MUSIC estimator is used. The algorithm is decomposed into several independent steps and the time consumption of each step is counted. Based on the statistics of the time consumption, we present a new parallel processing strategy to distribute the task of DOA estimation to different cores of the real-time signal processing hardware platform. Experimental results demonstrate that the high processing capability of the signal processing platform meets the constraint of real-time direction of arrival (DOA) estimation.

HiCAT Software Infrastructure: Safe hardware control with object oriented Python

NASA Astrophysics Data System (ADS)

Moriarty, Christopher; Brooks, Keira; Soummer, Remi

2018-01-01

High contrast imaging for Complex Aperture Telescopes (HiCAT) is a testbed designed to demonstrate coronagraphy and wavefront control for segmented on-axis space telescopes such as envisioned for LUVOIR. To limit the air movements in the testbed room, software interfaces for several different hardware components were developed to completely automate operations. When developing software interfaces for many different pieces of hardware, unhandled errors are commonplace and can prevent the software from properly closing a hardware resource. Some fragile components (e.g. deformable mirrors) can be permanently damaged because of this. We present an object oriented Python-based infrastructure to safely automate hardware control and optical experiments. Specifically, conducting high-contrast imaging experiments while monitoring humidity and power status along with graceful shutdown processes even for unexpected errors. Python contains a construct called a “context manager” that allows you define code to run when a resource is opened or closed. Context managers ensure that a resource is properly closed, even when unhandled errors occur. Harnessing the context manager design, we also use Python’s multiprocessing library to monitor humidity and power status without interrupting the experiment. Upon detecting a safety problem, the master process sends an event to the child process that triggers the context managers to gracefully close any open resources. This infrastructure allows us to queue up several experiments and safely operate the testbed without a human in the loop.

Design of a Single Channel Modulated Wideband Converter for Wideband Spectrum Sensing: Theory, Architecture and Hardware Implementation

PubMed Central

Liu, Weisong; Huang, Zhitao; Wang, Xiang; Sun, Weichao

2017-01-01

In a cognitive radio sensor network (CRSN), wideband spectrum sensing devices which aims to effectively exploit temporarily vacant spectrum intervals as soon as possible are of great importance. However, the challenge of increasingly high signal frequency and wide bandwidth requires an extremely high sampling rate which may exceed today’s best analog-to-digital converters (ADCs) front-end bandwidth. Recently, the newly proposed architecture called modulated wideband converter (MWC), is an attractive analog compressed sensing technique that can highly reduce the sampling rate. However, the MWC has high hardware complexity owing to its parallel channel structure especially when the number of signals increases. In this paper, we propose a single channel modulated wideband converter (SCMWC) scheme for spectrum sensing of band-limited wide-sense stationary (WSS) signals. With one antenna or sensor, this scheme can save not only sampling rate but also hardware complexity. We then present a new, SCMWC based, single node CR prototype System, on which the spectrum sensing algorithm was tested. Experiments on our hardware prototype show that the proposed architecture leads to successful spectrum sensing. And the total sampling rate as well as hardware size is only one channel’s consumption of MWC. PMID:28471410

Benchmarking Model Variants in Development of a Hardware-in-the-Loop Simulation System

NASA Technical Reports Server (NTRS)

Aretskin-Hariton, Eliot D.; Zinnecker, Alicia M.; Kratz, Jonathan L.; Culley, Dennis E.; Thomas, George L.

2016-01-01

Distributed engine control architecture presents a significant increase in complexity over traditional implementations when viewed from the perspective of system simulation and hardware design and test. Even if the overall function of the control scheme remains the same, the hardware implementation can have a significant effect on the overall system performance due to differences in the creation and flow of data between control elements. A Hardware-in-the-Loop (HIL) simulation system is under development at NASA Glenn Research Center that enables the exploration of these hardware dependent issues. The system is based on, but not limited to, the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k). This paper describes the step-by-step conversion from the self-contained baseline model to the hardware in the loop model, and the validation of each step. As the control model hardware fidelity was improved during HIL system development, benchmarking simulations were performed to verify that engine system performance characteristics remained the same. The results demonstrate the goal of the effort; the new HIL configurations have similar functionality and performance compared to the baseline C-MAPSS40k system.

Current trends in hardware and software for brain-computer interfaces (BCIs)

NASA Astrophysics Data System (ADS)

Brunner, P.; Bianchi, L.; Guger, C.; Cincotti, F.; Schalk, G.

2011-04-01

A brain-computer interface (BCI) provides a non-muscular communication channel to people with and without disabilities. BCI devices consist of hardware and software. BCI hardware records signals from the brain, either invasively or non-invasively, using a series of device components. BCI software then translates these signals into device output commands and provides feedback. One may categorize different types of BCI applications into the following four categories: basic research, clinical/translational research, consumer products, and emerging applications. These four categories use BCI hardware and software, but have different sets of requirements. For example, while basic research needs to explore a wide range of system configurations, and thus requires a wide range of hardware and software capabilities, applications in the other three categories may be designed for relatively narrow purposes and thus may only need a very limited subset of capabilities. This paper summarizes technical aspects for each of these four categories of BCI applications. The results indicate that BCI technology is in transition from isolated demonstrations to systematic research and commercial development. This process requires several multidisciplinary efforts, including the development of better integrated and more robust BCI hardware and software, the definition of standardized interfaces, and the development of certification, dissemination and reimbursement procedures.

Extensible Hardware Architecture for Mobile Robots

NASA Technical Reports Server (NTRS)

Park, Eric; Kobayashi, Linda; Lee, Susan Y.

2005-01-01

The Intelligent Robotics Group at NASA Ames Research Center has developed a new mobile robot hardware architecture designed for extensibility and reconfigurability. Currently implemented on the k9 rover. and won to be integrated onto the K10 series of human-robot collaboration research robots, this architecture allows for rapid changes in instrumentation configuration and provides a high degree of modularity through a synergistic mix of off-the-shelf and custom designed components, allowing eased transplantation into a wide vane6 of mobile robot platforms. A component level overview of this architecture is presented along with a description of the changes required for implementation on K10 , followed by plans for future work.

Proof of concept of a simple computer-assisted technique for correcting bone deformities.

PubMed

Ma, Burton; Simpson, Amber L; Ellis, Randy E

2007-01-01

We propose a computer-assisted technique for correcting bone deformities using the Ilizarov method. Our technique is an improvement over prior art in that it does not require a tracking system, navigation hardware and software, or intraoperative registration. Instead, we rely on a postoperative CT scan to obtain all of the information necessary to plan the correction and compute a correction schedule for the patient. Our laboratory experiments using plastic phantoms produced deformity corrections accurate to within 3.0 degrees of rotation and 1 mm of lengthening.

Data Applicability of Heritage and New Hardware for Launch Vehicle System Reliability Models

NASA Technical Reports Server (NTRS)

Al Hassan Mohammad; Novack, Steven

2015-01-01

Many launch vehicle systems are designed and developed using heritage and new hardware. In most cases, the heritage hardware undergoes modifications to fit new functional system requirements, impacting the failure rates and, ultimately, the reliability data. New hardware, which lacks historical data, is often compared to like systems when estimating failure rates. Some qualification of applicability for the data source to the current system should be made. Accurately characterizing the reliability data applicability and quality under these circumstances is crucial to developing model estimations that support confident decisions on design changes and trade studies. This presentation will demonstrate a data-source classification method that ranks reliability data according to applicability and quality criteria to a new launch vehicle. This method accounts for similarities/dissimilarities in source and applicability, as well as operating environments like vibrations, acoustic regime, and shock. This classification approach will be followed by uncertainty-importance routines to assess the need for additional data to reduce uncertainty.

Hardware cleanliness methodology and certification

NASA Technical Reports Server (NTRS)

Harvey, Gale A.; Lash, Thomas J.; Rawls, J. Richard

1995-01-01

Inadequacy of mass loss cleanliness criteria for selection of materials for contamination sensitive uses, and processing of flight hardware for contamination sensitive instruments is discussed. Materials selection for flight hardware is usually based on mass loss (ASTM E-595). However, flight hardware cleanliness (MIL 1246A) is a surface cleanliness assessment. It is possible for materials (e.g. Sil-Pad 2000) to pass ASTM E-595 and fail MIL 1246A class A by orders of magnitude. Conversely, it is possible for small amounts of nonconforming material (Huma-Seal conformal coating) to not present significant cleanliness problems to an optical flight instrument. Effective cleaning (precleaning, precision cleaning, and ultra cleaning) and cleanliness verification are essential for contamination sensitive flight instruments. Polish cleaning of hardware, e.g. vacuum baking for vacuum applications, and storage of clean hardware, e.g. laser optics, is discussed. Silicone materials present special concerns for use in space because of the rapid conversion of the outgassed residues to glass by solar ultraviolet radiation and/or atomic oxygen. Non ozone depleting solvent cleaning and institutional support for cleaning and certification are also discussed.

Mission Management Computer and Sequencing Hardware for RLV-TD HEX-01 Mission

NASA Astrophysics Data System (ADS)

Gupta, Sukrat; Raj, Remya; Mathew, Asha Mary; Koshy, Anna Priya; Paramasivam, R.; Mookiah, T.

2017-12-01

Reusable Launch Vehicle-Technology Demonstrator Hypersonic Experiment (RLV-TD HEX-01) mission posed some unique challenges in the design and development of avionics hardware. This work presents the details of mission critical avionics hardware mainly Mission Management Computer (MMC) and sequencing hardware. The Navigation, Guidance and Control (NGC) chain for RLV-TD is dual redundant with cross-strapped Remote Terminals (RTs) interfaced through MIL-STD-1553B bus. MMC is Bus Controller on the 1553 bus, which does the function of GPS aided navigation, guidance, digital autopilot and sequencing for the RLV-TD launch vehicle in different periodicities (10, 20, 500 ms). Digital autopilot execution in MMC with a periodicity of 10 ms (in ascent phase) is introduced for the first time and successfully demonstrated in the flight. MMC is built around Intel i960 processor and has inbuilt fault tolerance features like ECC for memories. Fault Detection and Isolation schemes are implemented to isolate the failed MMC. The sequencing hardware comprises Stage Processing System (SPS) and Command Execution Module (CEM). SPS is `RT' on the 1553 bus which receives the sequencing and control related commands from MMCs and posts to downstream modules after proper error handling for final execution. SPS is designed as a high reliability system by incorporating various fault tolerance and fault detection features. CEM is a relay based module for sequence command execution.

Fault Detection and Correction for the Solar Dynamics Observatory Attitude Control System

NASA Technical Reports Server (NTRS)

Starin, Scott R.; Vess, Melissa F.; Kenney, Thomas M.; Maldonado, Manuel D.; Morgenstern, Wendy M.

2007-01-01

The Solar Dynamics Observatory is an Explorer-class mission that will launch in early 2009. The spacecraft will operate in a geosynchronous orbit, sending data 24 hours a day to a devoted ground station in White Sands, New Mexico. It will carry a suite of instruments designed to observe the Sun in multiple wavelengths at unprecedented resolution. The Atmospheric Imaging Assembly includes four telescopes with focal plane CCDs that can image the full solar disk in four different visible wavelengths. The Extreme-ultraviolet Variability Experiment will collect time-correlated data on the activity of the Sun's corona. The Helioseismic and Magnetic Imager will enable study of pressure waves moving through the body of the Sun. The attitude control system on Solar Dynamics Observatory is responsible for four main phases of activity. The physical safety of the spacecraft after separation must be guaranteed. Fine attitude determination and control must be sufficient for instrument calibration maneuvers. The mission science mode requires 2-arcsecond control according to error signals provided by guide telescopes on the Atmospheric Imaging Assembly, one of the three instruments to be carried. Lastly, accurate execution of linear and angular momentum changes to the spacecraft must be provided for momentum management and orbit maintenance. In thsp aper, single-fault tolerant fault detection and correction of the Solar Dynamics Observatory attitude control system is described. The attitude control hardware suite for the mission is catalogued, with special attention to redundancy at the hardware level. Four reaction wheels are used where any three are satisfactory. Four pairs of redundant thrusters are employed for orbit change maneuvers and momentum management. Three two-axis gyroscopes provide full redundancy for rate sensing. A digital Sun sensor and two autonomous star trackers provide two-out-of-three redundancy for fine attitude determination. The use of software to maximize

Real-time look-up table-based color correction for still image stabilization of digital cameras without using frame memory

NASA Astrophysics Data System (ADS)

Luo, Lin-Bo; An, Sang-Woo; Wang, Chang-Shuai; Li, Ying-Chun; Chong, Jong-Wha

2012-09-01

Digital cameras usually decrease exposure time to capture motion-blur-free images. However, this operation will generate an under-exposed image with a low-budget complementary metal-oxide semiconductor image sensor (CIS). Conventional color correction algorithms can efficiently correct under-exposed images; however, they are generally not performed in real time and need at least one frame memory if they are implemented by hardware. The authors propose a real-time look-up table-based color correction method that corrects under-exposed images with hardware without using frame memory. The method utilizes histogram matching of two preview images, which are exposed for a long and short time, respectively, to construct an improved look-up table (ILUT) and then corrects the captured under-exposed image in real time. Because the ILUT is calculated in real time before processing the captured image, this method does not require frame memory to buffer image data, and therefore can greatly save the cost of CIS. This method not only supports single image capture, but also bracketing to capture three images at a time. The proposed method was implemented by hardware description language and verified by a field-programmable gate array with a 5 M CIS. Simulations show that the system can perform in real time with a low cost and can correct the color of under-exposed images well.

Event management for large scale event-driven digital hardware spiking neural networks.

PubMed

Caron, Louis-Charles; D'Haene, Michiel; Mailhot, Frédéric; Schrauwen, Benjamin; Rouat, Jean

2013-09-01

The interest in brain-like computation has led to the design of a plethora of innovative neuromorphic systems. Individually, spiking neural networks (SNNs), event-driven simulation and digital hardware neuromorphic systems get a lot of attention. Despite the popularity of event-driven SNNs in software, very few digital hardware architectures are found. This is because existing hardware solutions for event management scale badly with the number of events. This paper introduces the structured heap queue, a pipelined digital hardware data structure, and demonstrates its suitability for event management. The structured heap queue scales gracefully with the number of events, allowing the efficient implementation of large scale digital hardware event-driven SNNs. The scaling is linear for memory, logarithmic for logic resources and constant for processing time. The use of the structured heap queue is demonstrated on a field-programmable gate array (FPGA) with an image segmentation experiment and a SNN of 65,536 neurons and 513,184 synapses. Events can be processed at the rate of 1 every 7 clock cycles and a 406×158 pixel image is segmented in 200 ms. Copyright © 2013 Elsevier Ltd. All rights reserved.

Advances in flexible optrode hardware for use in cybernetic insects

NASA Astrophysics Data System (ADS)

Register, Joseph; Callahan, Dennis M.; Segura, Carlos; LeBlanc, John; Lissandrello, Charles; Kumar, Parshant; Salthouse, Christopher; Wheeler, Jesse

2017-08-01

Optogenetic manipulation is widely used to selectively excite and silence neurons in laboratory experiments. Recent efforts to miniaturize the components of optogenetic systems have enabled experiments on freely moving animals, but further miniaturization is required for freely flying insects. In particular, miniaturization of high channel-count optical waveguides are needed for high-resolution interfaces. Thin flexible waveguide arrays are needed to bend light around tight turns to access small anatomical targets. We present the design of lightweight miniaturized optogentic hardware and supporting electronics for the untethered steering of dragonfly flight. The system is designed to enable autonomous flight and includes processing, guidance sensors, solar power, and light stimulators. The system will weigh less than 200mg and be worn by the dragonfly as a backpack. The flexible implant has been designed to provide stimuli around nerves through micron scale apertures of adjacent neural tissue without the use of heavy hardware. We address the challenges of lightweight optogenetics and the development of high contrast polymer waveguides for this purpose.

Hardware realization of an SVM algorithm implemented in FPGAs

NASA Astrophysics Data System (ADS)

Wiśniewski, Remigiusz; Bazydło, Grzegorz; Szcześniak, Paweł

2017-08-01

The paper proposes a technique of hardware realization of a space vector modulation (SVM) of state function switching in matrix converter (MC), oriented on the implementation in a single field programmable gate array (FPGA). In MC the SVM method is based on the instantaneous space-vector representation of input currents and output voltages. The traditional computation algorithms usually involve digital signal processors (DSPs) which consumes the large number of power transistors (18 transistors and 18 independent PWM outputs) and "non-standard positions of control pulses" during the switching sequence. Recently, hardware implementations become popular since computed operations may be executed much faster and efficient due to nature of the digital devices (especially concurrency). In the paper, we propose a hardware algorithm of SVM computation. In opposite to the existing techniques, the presented solution applies COordinate Rotation DIgital Computer (CORDIC) method to solve the trigonometric operations. Furthermore, adequate arithmetic modules (that is, sub-devices) used for intermediate calculations, such as code converters or proper sectors selectors (for output voltages and input current) are presented in detail. The proposed technique has been implemented as a design described with the use of Verilog hardware description language. The preliminary results of logic implementation oriented on the Xilinx FPGA (particularly, low-cost device from Artix-7 family from Xilinx was used) are also presented.

Pile-up correction by Genetic Algorithm and Artificial Neural Network

NASA Astrophysics Data System (ADS)

Kafaee, M.; Saramad, S.

2009-08-01

Pile-up distortion is a common problem for high counting rates radiation spectroscopy in many fields such as industrial, nuclear and medical applications. It is possible to reduce pulse pile-up using hardware-based pile-up rejections. However, this phenomenon may not be eliminated completely by this approach and the spectrum distortion caused by pile-up rejection can be increased as well. In addition, inaccurate correction or rejection of pile-up artifacts in applications such as energy dispersive X-ray (EDX) spectrometers can lead to losses of counts, will give poor quantitative results and even false element identification. Therefore, it is highly desirable to use software-based models to predict and correct any recognized pile-up signals in data acquisition systems. The present paper describes two new intelligent approaches for pile-up correction; the Genetic Algorithm (GA) and Artificial Neural Networks (ANNs). The validation and testing results of these new methods have been compared, which shows excellent agreement with the measured data with 60Co source and NaI detector. The Monte Carlo simulation of these new intelligent algorithms also shows their advantages over hardware-based pulse pile-up rejection methods.

78 FR 15755 - Proposed Revision to Design of Structures, Components, Equipment and Systems; Correction

Federal Register 2010, 2011, 2012, 2013, 2014

2013-03-12

... NUCLEAR REGULATORY COMMISSION [NRC-2013-0041] Proposed Revision to Design of Structures, Components, Equipment and Systems; Correction AGENCY: Nuclear Regulatory Commission. ACTION: Standard review... for comments of the proposed revision in Chapter 3, ``Design of Structures, Components, Equipment, and...

Test Program for Stirling Radioisotope Generator Hardware at NASA Glenn Research Center

NASA Technical Reports Server (NTRS)

Lewandowski, Edward J.; Bolotin, Gary S.; Oriti, Salvatore M.

2014-01-01

Stirling-based energy conversion technology has demonstrated the potential of high efficiency and low mass power systems for future space missions. This capability is beneficial, if not essential, to making certain deep space missions possible. Significant progress was made developing the Advanced Stirling Radioisotope Generator (ASRG), a 140-watt radioisotope power system. A variety of flight-like hardware, including Stirling convertors, controllers, and housings, was designed and built under the ASRG flight development project. To support future Stirling-based power system development NASA has proposals that, if funded, will allow this hardware to go on test at the NASA Glenn Research Center (GRC). While future flight hardware may not be identical to the hardware developed under the ASRG flight development project, many components will likely be similar, and system architectures may have heritage to ASRG. Thus the importance of testing the ASRG hardware to the development of future Stirling-based power systems cannot be understated. This proposed testing will include performance testing, extended operation to establish an extensive reliability database, and characterization testing to quantify subsystem and system performance and better understand system interfaces. This paper details this proposed test program for Stirling radioisotope generator hardware at NASA GRC. It explains the rationale behind the proposed tests and how these tests will meet the stated objectives.

Space biology initiative program definition review. Trade study 2: Prototype utilization in the development of space biology hardware

NASA Technical Reports Server (NTRS)

Jackson, L. Neal; Crenshaw, John, Sr.; Schulze, Arthur E.; Wood, H. J., Jr.

1989-01-01

The objective was to define the factors which space flight hardware developers and planners should consider when determining: (1) the number of hardware units required to support program; (2) design level of the units; and (3) most efficient means of utilization of the units. The analysis considered technology risk, maintainability, reliability, and safety design requirements for achieving the delivery of highest quality flight hardware. Relative cost impacts of the utilization of prototyping were identified. The development of Space Biology Initiative research hardware will involve intertwined hardware/software activities. Experience has shown that software development can be an expensive portion of a system design program. While software prototyping could imply the development of a significantly different end item, an operational system prototype must be considered to be a combination of software and hardware. Hundreds of factors were identified that could be considered in determining the quantity and types of prototypes that should be constructed. In developing the decision models, these factors were combined and reduced by approximately ten-to-one in order to develop a manageable structure based on the major determining factors. The Baseline SBI hardware list of Appendix D was examined and reviewed in detail; however, from the facts available it was impossible to identify the exact types and quantities of prototypes required for each of these items. Although the factors that must be considered could be enumerated for each of these pieces of equipment, the exact status and state of development of the equipment is variable and uncertain at this time.

16 CFR 1509.7 - Hardware.

Code of Federal Regulations, 2010 CFR

2010-01-01

... NON-FULL-SIZE BABY CRIBS § 1509.7 Hardware. (a) The hardware in a non-full-size baby crib shall be... abuse. (b) Non-full-size baby cribs shall incorporate locking or latching devices for dropsides or... non-full-size baby crib. ...

Impact of the column hardware volume on resolution in very high pressure liquid chromatography non-invasive investigations.

PubMed

Gritti, Fabrice; McDonald, Thomas; Gilar, Martin

2015-11-13

The impact of the column hardware volume (≃ 1.7 μL) on the optimum reduced plate heights of a series of short 2.1 mm × 50 mm columns (hold-up volume ≃ 80-90 μL) packed with 1.8 μm HSS-T3, 1.7 μm BEH-C18, 1.7 μm CSH-C18, 1.6 μm CORTECS-C18+, and 1.7 μm BEH-C4 particles was investigated. A rapid and non-invasive method based on the reduction of the system dispersion (to only 0.15 μL(2)) of an I-class Acquity system and on the corrected plate heights (for system dispersion) of five weakly retained n-alkanophenones in RPLC was proposed. Evidence for sample dispersion through the column hardware volume was also revealed from the experimental plot of the peak capacities for smooth linear gradients versus the corrected efficiency of a weakly retained alkanophenone (isocratic runs). The plot is built for a constant gradient steepness irrespective of the applied flow rates (0.01-0.30 mL/min) and column lengths (2, 3, 5, and 10 cm). The volume variance caused by column endfittings and frits was estimated in between 0.1 and 0.7 μL(2) depending on the applied flow rate. After correction for system and hardware dispersion, the minimum reduced plate heights of short (5 cm) and narrow-bore (2.1mm i.d.) beds packed with sub-2 μm fully and superficially porous particles were found close to 1.5 and 0.7, respectively, instead of the classical h values of 2.0 and 1.4 for the whole column assembly. Copyright © 2015 Elsevier B.V. All rights reserved.

ZEUS hardware control system

NASA Astrophysics Data System (ADS)

Loveless, R.; Erhard, P.; Ficenec, J.; Gather, K.; Heath, G.; Iacovacci, M.; Kehres, J.; Mobayyen, M.; Notz, D.; Orr, R.; Orr, R.; Sephton, A.; Stroili, R.; Tokushuku, K.; Vogel, W.; Whitmore, J.; Wiggers, L.

1989-12-01

The ZEUS collaboration is building a system to monitor, control and document the hardware of the ZEUS detector. This system is based on a network of VAX computers and microprocessors connected via ethernet. The database for the hardware values will be ADAMO tables; the ethernet connection will be DECNET, TCP/IP, or RPC. Most of the documentation will also be kept in ADAMO tables for easy access by users.

Design and fabrication of an autonomous rendezvous and docking sensor using off-the-shelf hardware

NASA Technical Reports Server (NTRS)

Grimm, Gary E.; Bryan, Thomas C.; Howard, Richard T.; Book, Michael L.

1991-01-01

NASA Marshall Space Flight Center (MSFC) has developed and tested an engineering model of an automated rendezvous and docking sensor system composed of a video camera ringed with laser diodes at two wavelengths and a standard remote manipulator system target that has been modified with retro-reflective tape and 830 and 780 mm optical filters. TRW has provided additional engineering analysis, design, and manufacturing support, resulting in a robust, low cost, automated rendezvous and docking sensor design. We have addressed the issue of space qualification using off-the-shelf hardware components. We have also addressed the performance problems of increased signal to noise ratio, increased range, increased frame rate, graceful degradation through component redundancy, and improved range calibration. Next year, we will build a breadboard of this sensor. The phenomenology of the background scene of a target vehicle as viewed against earth and space backgrounds under various lighting conditions will be simulated using the TRW Dynamic Scene Generator Facility (DSGF). Solar illumination angles of the target vehicle and candidate docking target ranging from eclipse to full sun will be explored. The sensor will be transportable for testing at the MSFC Flight Robotics Laboratory (EB24) using the Dynamic Overhead Telerobotic Simulator (DOTS).

A hardware fast tracker for the ATLAS trigger

NASA Astrophysics Data System (ADS)

Asbah, Nedaa

2016-09-01

The trigger system of the ATLAS experiment is designed to reduce the event rate from the LHC nominal bunch crossing at 40 MHz to about 1 kHz, at the design luminosity of 1034 cm-2 s-1. After a successful period of data taking from 2010 to early 2013, the LHC already started with much higher instantaneous luminosity. This will increase the load on High Level Trigger system, the second stage of the selection based on software algorithms. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project. It is a hardware processor that will provide, at every Level-1 accepted event (100 kHz) and within 100 microseconds, full tracking information for tracks with momentum as low as 1 GeV. Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance. FTK exploits hardware technologies with massive parallelism, combining Associative Memory ASICs, FPGAs and high-speed communication links.

Circuit Design Optimization Using Genetic Algorithm with Parameterized Uniform Crossover

NASA Astrophysics Data System (ADS)

Bao, Zhiguo; Watanabe, Takahiro

Evolvable hardware (EHW) is a new research field about the use of Evolutionary Algorithms (EAs) to construct electronic systems. EHW refers in a narrow sense to use evolutionary mechanisms as the algorithmic drivers for system design, while in a general sense to the capability of the hardware system to develop and to improve itself. Genetic Algorithm (GA) is one of typical EAs. We propose optimal circuit design by using GA with parameterized uniform crossover (GApuc) and with fitness function composed of circuit complexity, power, and signal delay. Parameterized uniform crossover is much more likely to distribute its disruptive trials in an unbiased manner over larger portions of the space, then it has more exploratory power than one and two-point crossover, so we have more chances of finding better solutions. Its effectiveness is shown by experiments. From the results, we can see that the best elite fitness, the average value of fitness of the correct circuits and the number of the correct circuits of GApuc are better than that of GA with one-point crossover or two-point crossover. The best case of optimal circuits generated by GApuc is 10.18% and 6.08% better in evaluating value than that by GA with one-point crossover and two-point crossover, respectively.

Design, Development, and Testing of a UAV Hardware-in-the-Loop Testbed for Aviation and Airspace Prognostics Research

NASA Technical Reports Server (NTRS)

Kulkarni, Chetan; Teubert, Chris; Gorospe, George; Burgett, Drew; Quach, Cuong C.; Hogge, Edward

2016-01-01

The airspace is becoming more and more complicated, and will continue to do so in the future with the integration of Unmanned Aerial Vehicles (UAVs), autonomy, spacecraft, other forms of aviation technology into the airspace. The new technology and complexity increases the importance and difficulty of safety assurance. Additionally, testing new technologies on complex aviation systems & systems of systems can be very difficult, expensive, and sometimes unsafe in real life scenarios. Prognostic methodology provides an estimate of the health and risks of a component, vehicle, or airspace and knowledge of how that will change over time. That measure is especially useful in safety determination, mission planning, and maintenance scheduling. The developed testbed will be used to validate prediction algorithms for the real-time safety monitoring of the National Airspace System (NAS) and the prediction of unsafe events. The framework injects flight related anomalies related to ground systems, routing, airport congestion, etc. to test and verify algorithms for NAS safety. In our research work, we develop a live, distributed, hardware-in-the-loop testbed for aviation and airspace prognostics along with exploring further research possibilities to verify and validate future algorithms for NAS safety. The testbed integrates virtual aircraft using the X-Plane simulator and X-PlaneConnect toolbox, UAVs using onboard sensors and cellular communications, and hardware in the loop components. In addition, the testbed includes an additional research framework to support and simplify future research activities. It enables safe, accurate, and inexpensive experimentation and research into airspace and vehicle prognosis that would not have been possible otherwise. This paper describes the design, development, and testing of this system. Software reliability, safety and latency are some of the critical design considerations in development of the testbed. Integration of HITL elements in

NDAS Hardware Translation Layer Development

NASA Technical Reports Server (NTRS)

Nazaretian, Ryan N.; Holladay, Wendy T.

2011-01-01

The NASA Data Acquisition System (NDAS) project is aimed to replace all DAS software for NASA s Rocket Testing Facilities. There must be a software-hardware translation layer so the software can properly talk to the hardware. Since the hardware from each test stand varies, drivers for each stand have to be made. These drivers will act more like plugins for the software. If the software is being used in E3, then the software should point to the E3 driver package. If the software is being used at B2, then the software should point to the B2 driver package. The driver packages should also be filled with hardware drivers that are universal to the DAS system. For example, since A1, A2, and B2 all use the Preston 8300AU signal conditioners, then the driver for those three stands should be the same and updated collectively.

Hardware for dynamic quantum computing.

PubMed

Ryan, Colm A; Johnson, Blake R; Ristè, Diego; Donovan, Brian; Ohki, Thomas A

2017-10-01

We describe the hardware, gateware, and software developed at Raytheon BBN Technologies for dynamic quantum information processing experiments on superconducting qubits. In dynamic experiments, real-time qubit state information is fed back or fed forward within a fraction of the qubits' coherence time to dynamically change the implemented sequence. The hardware presented here covers both control and readout of superconducting qubits. For readout, we created a custom signal processing gateware and software stack on commercial hardware to convert pulses in a heterodyne receiver into qubit state assignments with minimal latency, alongside data taking capability. For control, we developed custom hardware with gateware and software for pulse sequencing and steering information distribution that is capable of arbitrary control flow in a fraction of superconducting qubit coherence times. Both readout and control platforms make extensive use of field programmable gate arrays to enable tailored qubit control systems in a reconfigurable fabric suitable for iterative development.

Integrating Reconfigurable Hardware-Based Grid for High Performance Computing

PubMed Central

Dondo Gazzano, Julio; Sanchez Molina, Francisco; Rincon, Fernando; López, Juan Carlos

2015-01-01

FPGAs have shown several characteristics that make them very attractive for high performance computing (HPC). The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use. However, there are still some difficulties when using reconfigurable platforms as accelerator that need to be addressed: the need of an in-depth application study to identify potential acceleration, the lack of tools for the deployment of computational problems in distributed hardware platforms, and the low portability of components, among others. This work proposes a complete grid infrastructure for distributed high performance computing based on dynamically reconfigurable FPGAs. Besides, a set of services designed to facilitate the application deployment is described. An example application and a comparison with other hardware and software implementations are shown. Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process. PMID:25874241

Hardware device binding and mutual authentication

DOEpatents

Hamlet, Jason R; Pierson, Lyndon G

2014-03-04

Detection and deterrence of device tampering and subversion by substitution may be achieved by including a cryptographic unit within a computing device for binding multiple hardware devices and mutually authenticating the devices. The cryptographic unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a binding PUF value. The cryptographic unit uses the binding PUF value during an enrollment phase and subsequent authentication phases. During a subsequent authentication phase, the cryptographic unit uses the binding PUF values of the multiple hardware devices to generate a challenge to send to the other device, and to verify a challenge received from the other device to mutually authenticate the hardware devices.

An Overview of Hardware for Protein Crystallization in a Magnetic Field.

PubMed

Yan, Er-Kai; Zhang, Chen-Yan; He, Jin; Yin, Da-Chuan

2016-11-16

Protein crystallization under a magnetic field is an interesting research topic because a magnetic field may provide a special environment to acquire improved quality protein crystals. Because high-quality protein crystals are very useful in high-resolution structure determination using diffraction techniques (X-ray, neutron, and electron diffraction), research using magnetic fields in protein crystallization has attracted substantial interest; some studies have been performed in the past two decades. In this research field, the hardware is especially essential for successful studies because the environment is special and the design and utilization of the research apparatus in such an environment requires special considerations related to the magnetic field. This paper reviews the hardware for protein crystallization (including the magnet systems and the apparatus designed for use in a magnetic field) and progress in this area. Future prospects in this field will also be discussed.

Hardware and software reliability estimation using simulations

NASA Technical Reports Server (NTRS)

Swern, Frederic L.

1994-01-01

The simulation technique is used to explore the validation of both hardware and software. It was concluded that simulation is a viable means for validating both hardware and software and associating a reliability number with each. This is useful in determining the overall probability of system failure of an embedded processor unit, and improving both the code and the hardware where necessary to meet reliability requirements. The methodologies were proved using some simple programs, and simple hardware models.

Fracture of fusion mass after hardware removal in patients with high sagittal imbalance.

PubMed

Sedney, Cara L; Daffner, Scott D; Stefanko, Jared J; Abdelfattah, Hesham; Emery, Sanford E; France, John C

2016-04-01

patients who underwent surgery for ASD after a remote fusion. These patients later developed a fracture of the fusion mass after hardware removal from their previously successfully fused segment. All patients had a high sagittal imbalance and had previously undergone multiple spinal operations. The development of a spontaneous fracture of the fusion mass may be related to sagittal imbalance. Consideration should be given to reimplanting hardware for these patients, even across good fusions, to prevent spontaneous fracture of these areas if the sagittal imbalance is not corrected.

A Modular Framework for Modeling Hardware Elements in Distributed Engine Control Systems

NASA Technical Reports Server (NTRS)

Zinnecker, Alicia M.; Culley, Dennis E.; Aretskin-Hariton, Eliot D.

2014-01-01

Progress toward the implementation of distributed engine control in an aerospace application may be accelerated through the development of a hardware-in-the-loop (HIL) system for testing new control architectures and hardware outside of a physical test cell environment. One component required in an HIL simulation system is a high-fidelity model of the control platform: sensors, actuators, and the control law. The control system developed for the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k) provides a verifiable baseline for development of a model for simulating a distributed control architecture. This distributed controller model will contain enhanced hardware models, capturing the dynamics of the transducer and the effects of data processing, and a model of the controller network. A multilevel framework is presented that establishes three sets of interfaces in the control platform: communication with the engine (through sensors and actuators), communication between hardware and controller (over a network), and the physical connections within individual pieces of hardware. This introduces modularity at each level of the model, encouraging collaboration in the development and testing of various control schemes or hardware designs. At the hardware level, this modularity is leveraged through the creation of a Simulink(R) library containing blocks for constructing smart transducer models complying with the IEEE 1451 specification. These hardware models were incorporated in a distributed version of the baseline C-MAPSS40k controller and simulations were run to compare the performance of the two models. The overall tracking ability differed only due to quantization effects in the feedback measurements in the distributed controller. Additionally, it was also found that the added complexity of the smart transducer models did not prevent real-time operation of the distributed controller model, a requirement of an HIL system.

A Modular Framework for Modeling Hardware Elements in Distributed Engine Control Systems

NASA Technical Reports Server (NTRS)

Zinnecker, Alicia M.; Culley, Dennis E.; Aretskin-Hariton, Eliot D.

2015-01-01

Progress toward the implementation of distributed engine control in an aerospace application may be accelerated through the development of a hardware-in-the-loop (HIL) system for testing new control architectures and hardware outside of a physical test cell environment. One component required in an HIL simulation system is a high-fidelity model of the control platform: sensors, actuators, and the control law. The control system developed for the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k) provides a verifiable baseline for development of a model for simulating a distributed control architecture. This distributed controller model will contain enhanced hardware models, capturing the dynamics of the transducer and the effects of data processing, and a model of the controller network. A multilevel framework is presented that establishes three sets of interfaces in the control platform: communication with the engine (through sensors and actuators), communication between hardware and controller (over a network), and the physical connections within individual pieces of hardware. This introduces modularity at each level of the model, encouraging collaboration in the development and testing of various control schemes or hardware designs. At the hardware level, this modularity is leveraged through the creation of a SimulinkR library containing blocks for constructing smart transducer models complying with the IEEE 1451 specification. These hardware models were incorporated in a distributed version of the baseline C-MAPSS40k controller and simulations were run to compare the performance of the two models. The overall tracking ability differed only due to quantization effects in the feedback measurements in the distributed controller. Additionally, it was also found that the added complexity of the smart transducer models did not prevent real-time operation of the distributed controller model, a requirement of an HIL system.

A Modular Framework for Modeling Hardware Elements in Distributed Engine Control Systems

NASA Technical Reports Server (NTRS)

Zinnecker, Alicia Mae; Culley, Dennis E.; Aretskin-Hariton, Eliot D.

2014-01-01

Progress toward the implementation of distributed engine control in an aerospace application may be accelerated through the development of a hardware-in-the-loop (HIL) system for testing new control architectures and hardware outside of a physical test cell environment. One component required in an HIL simulation system is a high-fidelity model of the control platform: sensors, actuators, and the control law. The control system developed for the Commercial Modular Aero-Propulsion System Simulation 40k (40,000 pound force thrust) (C-MAPSS40k) provides a verifiable baseline for development of a model for simulating a distributed control architecture. This distributed controller model will contain enhanced hardware models, capturing the dynamics of the transducer and the effects of data processing, and a model of the controller network. A multilevel framework is presented that establishes three sets of interfaces in the control platform: communication with the engine (through sensors and actuators), communication between hardware and controller (over a network), and the physical connections within individual pieces of hardware. This introduces modularity at each level of the model, encouraging collaboration in the development and testing of various control schemes or hardware designs. At the hardware level, this modularity is leveraged through the creation of a Simulink (R) library containing blocks for constructing smart transducer models complying with the IEEE 1451 specification. These hardware models were incorporated in a distributed version of the baseline C-MAPSS40k controller and simulations were run to compare the performance of the two models. The overall tracking ability differed only due to quantization effects in the feedback measurements in the distributed controller. Additionally, it was also found that the added complexity of the smart transducer models did not prevent real-time operation of the distributed controller model, a requirement of an HIL

Cognon Neural Model Software Verification and Hardware Implementation Design

NASA Astrophysics Data System (ADS)

Haro Negre, Pau

Little is known yet about how the brain can recognize arbitrary sensory patterns within milliseconds using neural spikes to communicate information between neurons. In a typical brain there are several layers of neurons, with each neuron axon connecting to ˜104 synapses of neurons in an adjacent layer. The information necessary for cognition is contained in theses synapses, which strengthen during the learning phase in response to newly presented spike patterns. Continuing on the model proposed in "Models for Neural Spike Computation and Cognition" by David H. Staelin and Carl H. Staelin, this study seeks to understand cognition from an information theoretic perspective and develop potential models for artificial implementation of cognition based on neuronal models. To do so we focus on the mathematical properties and limitations of spike-based cognition consistent with existing neurological observations. We validate the cognon model through software simulation and develop concepts for an optical hardware implementation of a network of artificial neural cognons.

Initial SVS Integrated Technology Evaluation Flight Test Requirements and Hardware Architecture

NASA Technical Reports Server (NTRS)

Harrison, Stella V.; Kramer, Lynda J.; Bailey, Randall E.; Jones, Denise R.; Young, Steven D.; Harrah, Steven D.; Arthur, Jarvis J.; Parrish, Russell V.

2003-01-01

This document presents the flight test requirements for the Initial Synthetic Vision Systems Integrated Technology Evaluation flight Test to be flown aboard NASA Langley's ARIES aircraft and the final hardware architecture implemented to meet these requirements. Part I of this document contains the hardware, software, simulator, and flight operations requirements for this light test as they were defined in August 2002. The contents of this section are the actual requirements document that was signed for this flight test. Part II of this document contains information pertaining to the hardware architecture that was realized to meet these requirements as presented to and approved by a Critical Design Review Panel prior to installation on the B-757 Airborne Research Integrated Experiments Systems (ARIES) airplane. This information includes a description of the equipment, block diagrams of the architecture, layouts of the workstations, and pictures of the actual installations.

Computer program for design of two-dimensional supersonic turbine rotor blades with boundary-layer correction

NASA Technical Reports Server (NTRS)

Goldman, L. J.; Scullin, V. J.

1971-01-01

A FORTRAN 4 computer program for the design of two-dimensional supersonic rotor blade sections corrected for boundary-layer displacement thickness is presented. The ideal rotor is designed by the method of characteristics to produce vortex flow within the blade passage. The boundary-layer parameters are calculated by Cohen and Reshotoko's method for laminar flow and Sasman and Cresci's method for turbulent flow. The program input consists essentially of the blade surface Mach number distribution and total flow conditions. The primary output is the corrected blade profile and the boundary-layer parameters.

Coupled Loads Analysis of the Modified NASA Barge Pegasus and Space Launch System Hardware

NASA Technical Reports Server (NTRS)

Knight, J. Brent

2015-01-01

A Coupled Loads Analysis (CLA) has been performed for barge transport of Space Launch System hardware on the recently modified NASA barge Pegasus. The barge re-design was facilitated with detailed finite element analyses by the ARMY Corps of Engineers - Marine Design Center. The Finite Element Model (FEM) utilized in the design was also used in the subject CLA. The Pegasus FEM and CLA results are presented as well as a comparison of the analysis process to that of a payload being transported to space via the Space Shuttle. Discussion of the dynamic forcing functions is included as well. The process of performing a dynamic CLA of NASA hardware during marine transport is thought to be a first and can likely support minimization of undue conservatism.

Marketing and Distributive Education Curriculum Guide: Hardware-Building Materials, Farm and Garden.

ERIC Educational Resources Information Center

Cluck, Janice Bora

Designed to be used with the General Marketing Curriculum Planning Guide (ED 156 860), this guide is intended to provide the curriculum coordinator with a basis for planning a comprehensive program in the field of marketing for farm and garden hardware building materials; it is designed also to allow marketing and distributive education…

RighTime: A real time clock correcting program for MS-DOS-based computer systems

NASA Technical Reports Server (NTRS)

Becker, G. Thomas

1993-01-01

A computer program is described which effectively eliminates the misgivings of the DOS system clock in PC/AT-class computers. RighTime is a small, sophisticated memory-resident program that automatically corrects both the DOS system clock and the hardware 'CMOS' real time clock (RTC) in real time. RighTime learns what corrections are required without operator interaction beyond the occasional accurate time set. Both warm (power on) and cool (power off) errors are corrected, usually yielding better than one part per million accuracy in the typical desktop computer with no additional hardware, and RighTime increases the system clock resolution from approximately 0.0549 second to 0.01 second. Program tools are also available which allow visualization of RighTime's actions, verification of its performance, display of its history log, and which provide data for graphing of the system clock behavior. The program has found application in a wide variety of industries, including astronomy, satellite tracking, communications, broadcasting, transportation, public utilities, manufacturing, medicine, and the military.

Experience with procuring, deploying and maintaining hardware at remote co-location centre

NASA Astrophysics Data System (ADS)

Bärring, O.; Bonfillou, E.; Clement, B.; Coelho Dos Santos, M.; Dore, V.; Gentit, A.; Grossir, A.; Salter, W.; Valsan, L.; Xafi, A.

2014-05-01

In May 2012 CERN signed a contract with the Wigner Data Centre in Budapest for an extension to CERN's central computing facility beyond its current boundaries set by electrical power and cooling available for computing. The centre is operated as a remote co-location site providing rack-space, electrical power and cooling for server, storage and networking equipment acquired by CERN. The contract includes a 'remote-hands' services for physical handling of hardware (rack mounting, cabling, pushing power buttons, ...) and maintenance repairs (swapping disks, memory modules, ...). However, only CERN personnel have network and console access to the equipment for system administration. This report gives an insight to adaptations of hardware architecture, procurement and delivery procedures undertaken enabling remote physical handling of the hardware. We will also describe tools and procedures developed for automating the registration, burn-in testing, acceptance and maintenance of the equipment as well as an independent but important change to the IT assets management (ITAM) developed in parallel as part of the CERN IT Agile Infrastructure project. Finally, we will report on experience from the first large delivery of 400 servers and 80 SAS JBOD expansion units (24 drive bays) to Wigner in March 2013. Changes were made to the abstract file on 13/06/2014 to correct errors, the pdf file was unchanged.

Ultra-low noise miniaturized neural amplifier with hardware averaging.

PubMed

Dweiri, Yazan M; Eggers, Thomas; McCallum, Grant; Durand, Dominique M

2015-08-01

Peripheral nerves carry neural signals that could be used to control hybrid bionic systems. Cuff electrodes provide a robust and stable interface but the recorded signal amplitude is small (<3 μVrms 700 Hz-7 kHz), thereby requiring a baseline noise of less than 1 μVrms for a useful signal-to-noise ratio (SNR). Flat interface nerve electrode (FINE) contacts alone generate thermal noise of at least 0.5 μVrms therefore the amplifier should add as little noise as possible. Since mainstream neural amplifiers have a baseline noise of 2 μVrms or higher, novel designs are required. Here we apply the concept of hardware averaging to nerve recordings obtained with cuff electrodes. An optimization procedure is developed to minimize noise and power simultaneously. The novel design was based on existing neural amplifiers (Intan Technologies, LLC) and is validated with signals obtained from the FINE in chronic dog experiments. We showed that hardware averaging leads to a reduction in the total recording noise by a factor of 1/√N or less depending on the source resistance. Chronic recording of physiological activity with FINE using the presented design showed significant improvement on the recorded baseline noise with at least two parallel operation transconductance amplifiers leading to a 46.1% reduction at N = 8. The functionality of these recordings was quantified by the SNR improvement and shown to be significant for N = 3 or more. The present design was shown to be capable of generating <1.5 μVrms total recording baseline noise when connected to a FINE placed on the sciatic nerve of an awake animal. An algorithm was introduced to find the value of N that can minimize both the power consumption and the noise in order to design a miniaturized ultralow-noise neural amplifier. These results demonstrate the efficacy of hardware averaging on noise improvement for neural recording with cuff electrodes, and can accommodate the presence of high source impedances that are

Web-Compatible Graphics Visualization Framework for Online Instruction and Assessment of Hardware Concepts

ERIC Educational Resources Information Center

Chandramouli, Magesh; Chittamuru, Siva-Teja

2016-01-01

This paper explains the design of a graphics-based virtual environment for instructing computer hardware concepts to students, especially those at the beginner level. Photorealistic visualizations and simulations are designed and programmed with interactive features allowing students to practice, explore, and test themselves on computer hardware…

The Impact of Flight Hardware Scavenging on Space Logistics

NASA Technical Reports Server (NTRS)

Oeftering, Richard C.

2011-01-01

For a given fixed launch vehicle capacity the logistics payload delivered to the moon may be only roughly 20 percent of the payload delivered to the International Space Station (ISS). This is compounded by the much lower flight frequency to the moon and thus low availability of spares for maintenance. This implies that lunar hardware is much more scarce and more costly per kilogram than ISS and thus there is much more incentive to preserve hardware. The Constellation Lunar Surface System (LSS) program is considering ways of utilizing hardware scavenged from vehicles including the Altair lunar lander. In general, the hardware will have only had a matter of hours of operation yet there may be years of operational life remaining. By scavenging this hardware the program, in effect, is treating vehicle hardware as part of the payload. Flight hardware may provide logistics spares for system maintenance and reduce the overall logistics footprint. This hardware has a wide array of potential applications including expanding the power infrastructure, and exploiting in-situ resources. Scavenging can also be seen as a way of recovering the value of, literally, billions of dollars worth of hardware that would normally be discarded. Scavenging flight hardware adds operational complexity and steps must be taken to augment the crew s capability with robotics, capabilities embedded in flight hardware itself, and external processes. New embedded technologies are needed to make hardware more serviceable and scavengable. Process technologies are needed to extract hardware, evaluate hardware, reconfigure or repair hardware, and reintegrate it into new applications. This paper also illustrates how scavenging can be used to drive down the cost of the overall program by exploiting the intrinsic value of otherwise discarded flight hardware.

A Systematic Software, Firmware, and Hardware Codesign Methodology for Digital Signal Processing

DTIC Science & Technology

2014-03-01

possible mappings ...................................................60 Table 25. Possible optimal leaf -nodes... size weight and power UAV unmanned aerial vehicle UHF ultra-high frequency UML universal modeling language Verilog verify logic VHDL VHSIC...optimal leaf -nodes to some design patterns for embedded system design. Software and hardware partitioning is a very difficult challenge in the field of

3D Printed Fluidic Hardware for DNA Assembly

DTIC Science & Technology

2015-04-10

A3909 stepper motor driver, were soldered onto the milled circuit board (Supplementary Figure 8). Custom Arduino - based firmware was written to take...initiatives such as the FabLab Foundation10. Access to digital fabrication tools and open electronics, such as Arduino and Raspberry Pi, enables access to...hardware for assembly of DNA- based genetic circuits. Solid-phase DNA synthesis has declined in price, enabling researchers to routinely design and

Design-corrected variation by centre in mortality reduction in the ERSPC randomised prostate cancer screening trial.

PubMed

Hakama, Matti; Moss, Sue M; Stenman, Ulf-Hakan; Roobol, Monique J; Zappa, Marco; Carlsson, Sigrid; Randazzo, Marco; Nelen, Vera; Hugosson, Jonas

2017-06-01

Objectives To calculate design-corrected estimates of the effect of screening on prostate cancer mortality by centre in the European Randomised Study of Screening for Prostate Cancer (ERSPC). Setting The ERSPC has shown a 21% reduction in prostate cancer mortality in men invited to screening with follow-up truncated at 13 years. Centres either used pre-consent randomisation (effectiveness design) or post-consent randomisation (efficacy design). Methods In six centres (three effectiveness design, three efficacy design) with follow-up until the end of 2010, or maximum 13 years, the effect of screening was estimated as both effectiveness (mortality reduction in the target population) and efficacy (reduction in those actually screened). Results The overall crude prostate cancer mortality risk ratio in the intervention arm vs control arm for the six centres was 0.79 ranging from a 14% increase to a 38% reduction. The risk ratio was 0.85 in centres with effectiveness design and 0.73 in those with efficacy design. After correcting for design, overall efficacy was 27%, 24% in pre-consent and 29% in post-consent centres, ranging between a 12% increase and a 52% reduction. Conclusion The estimated overall effect of screening in attenders (efficacy) was a 27% reduction in prostate cancer mortality at 13 years' follow-up. The variation in efficacy between centres was greater than the range in risk ratio without correction for design. The centre-specific variation in the mortality reduction could not be accounted for by the randomisation method.

Space Telecommunications Radio Systems (STRS) Hardware Architecture Standard: Release 1.0 Hardware Section

NASA Technical Reports Server (NTRS)

Reinhart, Richard C.; Kacpura, Thomas J.; Smith, Carl R.; Liebetreu, John; Hill, Gary; Mortensen, Dale J.; Andro, Monty; Scardelletti, Maximilian C.; Farrington, Allen

2008-01-01

This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

Innovative Contamination Certification of Multi-Mission Flight Hardware

NASA Technical Reports Server (NTRS)

Hansen, Patricia A.; Hughes, David W.; Montt, Kristina M.; Triolo, Jack J.

1998-01-01

Maintaining contamination certification of multi-mission flight hardware is an innovative approach to controlling mission costs. Methods for assessing ground induced degradation between missions have been employed by the Hubble Space Telescope (HST) Project for the multi-mission (servicing) hardware. By maintaining the cleanliness of the hardware between missions, and by controlling the materials added to the hardware during modification and refurbishment both project funding for contamination recertification and schedule have been significantly reduced. These methods will be discussed and HST hardware data will be presented.

Innovative Contamination Certification of Multi-Mission Flight Hardware

NASA Technical Reports Server (NTRS)

Hansen, Patricia A.; Hughes, David W.; Montt, Kristina M.; Triolo, Jack J.

1999-01-01

Maintaining contamination certification of multi-mission flight hardware is an innovative approach to controlling mission costs. Methods for assessing ground induced degradation between missions have been employed by the Hubble Space Telescope (HST) Project for the multi-mission (servicing) hardware. By maintaining the cleanliness of the hardware between missions, and by controlling the materials added to the hardware during modification and refurbishment both project funding for contamination recertification and schedule have been significantly reduced. These methods will be discussed and HST hardware data will be presented.

Wireless Energy Harvesting Two-Way Relay Networks with Hardware Impairments.

PubMed

Peng, Chunling; Li, Fangwei; Liu, Huaping

2017-11-13

This paper considers a wireless energy harvesting two-way relay (TWR) network where the relay has energy-harvesting abilities and the effects of practical hardware impairments are taken into consideration. In particular, power splitting (PS) receiver is adopted at relay to harvests the power it needs for relaying the information between the source nodes from the signals transmitted by the source nodes, and hardware impairments is assumed suffered by each node. We analyze the effect of hardware impairments [-20]on both decode-and-forward (DF) relaying and amplify-and-forward (AF) relaying networks. By utilizing the obtained new expressions of signal-to-noise-plus-distortion ratios, the exact analytical expressions of the achievable sum rate and ergodic capacities for both DF and AF relaying protocols are derived. Additionally, the optimal power splitting (OPS) ratio that maximizes the instantaneous achievable sum rate is formulated and solved for both protocols. The performances of DF and AF protocols are evaluated via numerical results, which also show the effects of various network parameters on the system performance and on the OPS ratio design.

Recycling Flight Hardware Components and Systems to Reduce Next Generation Research Costs

NASA Technical Reports Server (NTRS)

Turner, Wlat

2011-01-01

With the recent 'new direction' put forth by President Obama identifying NASA's new focus in research rather than continuing on a path to return to the Moon and Mars, the focus of work at Kennedy Space Center (KSC) may be changing dramatically. Research opportunities within the micro-gravity community potentially stands at the threshold of resurgence when the new direction of the agency takes hold for the next generation of experimenters. This presentation defines a strategy for recycling flight experiment components or part numbers, in order to reduce research project costs, not just in component selection and fabrication, but in expediting qualification of hardware for flight. A key component of the strategy is effective communication of relevant flight hardware information and available flight hardware components to researchers, with the goal of 'short circuiting' the design process for flight experiments

Neutron Imaging for Selective Laser Melting Inconel Hardware with Internal Passages

NASA Technical Reports Server (NTRS)

Tramel, Terri L.; Norwood, Joseph K.; Bilheux, Hassina

2014-01-01

Additive Manufacturing is showing great promise for the development of new innovative designs and large potential life cycle cost reduction for the Aerospace Industry. However, more development work is required to move this technology into space flight hardware production. With selective laser melting (SLM), hardware that once consisted of multiple, carefully machined and inspected pieces, joined together can be made in one part. However standard inspection techniques cannot be used to verify that the internal passages are within dimensional tolerances or surface finish requirements. NASA/MSFC traveled to Oak Ridge National Lab's (ORNL) Spallation Neutron Source to perform some non-destructive, proof of concept imaging measurements to assess the capabilities to understand internal dimensional tolerances and internal passages surface roughness. This presentation will describe 1) the goals of this proof of concept testing, 2) the lessons learned when designing and building these Inconel 718 test specimens to minimize beam time, 3) the neutron imaging test setup and test procedure to get the images, 4) the initial results in images, volume and a video, 4) the assessment of using this imaging technique to gather real data for designing internal flow passages in SLM manufacturing aerospace hardware, and lastly 5) how proper cleaning of the internal passages is critically important. In summary, the initial results are very promising and continued development of a technique to assist in SLM development for aerospace components is desired by both NASA and ORNL. A plan forward that benefits both ORNL and NASA will also be presented, based on the promising initial results. The initial images and volume reconstruction showed that clean, clear images of the internal passages geometry are obtainable. These clear images of the internal passages of simple geometries will be compared to the build model to determine any differences. One surprising result was that a new cleaning

An Overview of Hardware for Protein Crystallization in a Magnetic Field

PubMed Central

Yan, Er-Kai; Zhang, Chen-Yan; He, Jin; Yin, Da-Chuan

2016-01-01

Protein crystallization under a magnetic field is an interesting research topic because a magnetic field may provide a special environment to acquire improved quality protein crystals. Because high-quality protein crystals are very useful in high-resolution structure determination using diffraction techniques (X-ray, neutron, and electron diffraction), research using magnetic fields in protein crystallization has attracted substantial interest; some studies have been performed in the past two decades. In this research field, the hardware is especially essential for successful studies because the environment is special and the design and utilization of the research apparatus in such an environment requires special considerations related to the magnetic field. This paper reviews the hardware for protein crystallization (including the magnet systems and the apparatus designed for use in a magnetic field) and progress in this area. Future prospects in this field will also be discussed. PMID:27854318

Use of Heritage Hardware on MPCV Exploration Flight Test One

NASA Technical Reports Server (NTRS)

Rains, George Edward; Cross, Cynthia D.

2011-01-01

Due to an aggressive schedule for the first orbital test flight of an unmanned Orion capsule, known as Exploration Flight Test One (EFT1), combined with severe programmatic funding constraints, an effort was made to identify heritage hardware, i.e., already existing, flight-certified components from previous manned space programs, which might be available for use on EFT1. With the end of the Space Shuttle Program, no current means exists to launch Multi Purpose Logistics Modules (MPLMs) to the International Space Station (ISS), and so the inventory of many flight-certified Shuttle and MPLM components are available for other purposes. Two of these items are the Shuttle Ground Support Equipment Heat Exchanger (GSE Hx) and the MPLM cabin Positive Pressure Relief Assembly (PPRA). In preparation for the utilization of these components by the Orion Program, analyses and testing of the hardware were performed. The PPRA had to be analyzed to determine its susceptibility to pyrotechnic shock, and vibration testing had to be performed, since those environments are predicted to be significantly more severe during an Orion mission than those the hardware was originally designed to accommodate. The GSE Hx had to be tested for performance with the Orion thermal working fluids, which are different from those used by the Space Shuttle. This paper summarizes the certification of the use of heritage hardware for EFT1.

Pulseq: A rapid and hardware-independent pulse sequence prototyping framework.

PubMed

Layton, Kelvin J; Kroboth, Stefan; Jia, Feng; Littin, Sebastian; Yu, Huijun; Leupold, Jochen; Nielsen, Jon-Fredrik; Stöcker, Tony; Zaitsev, Maxim

2017-04-01

Implementing new magnetic resonance experiments, or sequences, often involves extensive programming on vendor-specific platforms, which can be time consuming and costly. This situation is exacerbated when research sequences need to be implemented on several platforms simultaneously, for example, at different field strengths. This work presents an alternative programming environment that is hardware-independent, open-source, and promotes rapid sequence prototyping. A novel file format is described to efficiently store the hardware events and timing information required for an MR pulse sequence. Platform-dependent interpreter modules convert the file to appropriate instructions to run the sequence on MR hardware. Sequences can be designed in high-level languages, such as MATLAB, or with a graphical interface. Spin physics simulation tools are incorporated into the framework, allowing for comparison between real and virtual experiments. Minimal effort is required to implement relatively advanced sequences using the tools provided. Sequences are executed on three different MR platforms, demonstrating the flexibility of the approach. A high-level, flexible and hardware-independent approach to sequence programming is ideal for the rapid development of new sequences. The framework is currently not suitable for large patient studies or routine scanning although this would be possible with deeper integration into existing workflows. Magn Reson Med 77:1544-1552, 2017. © 2016 International Society for Magnetic Resonance in Medicine. © 2016 International Society for Magnetic Resonance in Medicine.

Hardware and Programmatic Progress on the Ares I-X Flight Test

NASA Technical Reports Server (NTRS)

Davis, Stephan R.

2008-01-01

In less than two years, the National Aeronautics and Space Administration (NASA) will execute the Ares I-X mission. This will be the first flight of the Ares I crew launch vehicle; which, together with the Ares V cargo launch vehicle (Figure 1), will eventually send humans to the Moon, Mars, and beyond. As the countdown to this first Ares mission continues, personnel from across the Ares I-X Mission Management Office (MMO) are finalizing designs and, in some cases, already fabricating vehicle hardware in preparation for an April 2009 launch. This paper will discuss the hardware and programmatic progress of the Ares I-X mission.

Micro sensor node for air pollutant monitoring: hardware and software issues.

PubMed

Choi, Sukwon; Kim, Nakyoung; Cha, Hojung; Ha, Rhan

2009-01-01

Wireless sensor networks equipped with various gas sensors have been actively used for air quality monitoring. Previous studies have typically explored system issues that include middleware or networking performance, but most research has barely considered the details of the hardware and software of the sensor node itself. In this paper, we focus on the design and implementation of a sensor board for air pollutant monitoring applications. Several hardware and software issues are discussed to explore the possibilities of a practical WSN-based air pollution monitoring system. Through extensive experiments and evaluation, we have determined the various characteristics of the gas sensors and their practical implications for air pollutant monitoring systems.

Neural Networks Based Approach to Enhance Space Hardware Reliability

NASA Technical Reports Server (NTRS)

Zebulum, Ricardo S.; Thakoor, Anilkumar; Lu, Thomas; Franco, Lauro; Lin, Tsung Han; McClure, S. S.

2011-01-01

This paper demonstrates the use of Neural Networks as a device modeling tool to increase the reliability analysis accuracy of circuits targeted for space applications. The paper tackles a number of case studies of relevance to the design of Flight hardware. The results show that the proposed technique generates more accurate models than the ones regularly used to model circuits.

Quantum annealing correction with minor embedding

NASA Astrophysics Data System (ADS)

Vinci, Walter; Albash, Tameem; Paz-Silva, Gerardo; Hen, Itay; Lidar, Daniel A.

2015-10-01

Quantum annealing provides a promising route for the development of quantum optimization devices, but the usefulness of such devices will be limited in part by the range of implementable problems as dictated by hardware constraints. To overcome constraints imposed by restricted connectivity between qubits, a larger set of interactions can be approximated using minor embedding techniques whereby several physical qubits are used to represent a single logical qubit. However, minor embedding introduces new types of errors due to its approximate nature. We introduce and study quantum annealing correction schemes designed to improve the performance of quantum annealers in conjunction with minor embedding, thus leading to a hybrid scheme defined over an encoded graph. We argue that this scheme can be efficiently decoded using an energy minimization technique provided the density of errors does not exceed the per-site percolation threshold of the encoded graph. We test the hybrid scheme using a D-Wave Two processor on problems for which the encoded graph is a two-level grid and the Ising model is known to be NP-hard. The problems we consider are frustrated Ising model problem instances with "planted" (a priori known) solutions. Applied in conjunction with optimized energy penalties and decoding techniques, we find that this approach enables the quantum annealer to solve minor embedded instances with significantly higher success probability than it would without error correction. Our work demonstrates that quantum annealing correction can and should be used to improve the robustness of quantum annealing not only for natively embeddable problems but also when minor embedding is used to extend the connectivity of physical devices.

A programmable and portable NMES device for drop foot correction and blood flow assist applications.

PubMed

Breen, Paul P; Corley, Gavin J; O'Keeffe, Derek T; Conway, Richard; Olaighin, Gearóid

2009-04-01

The Duo-STIM, a new, programmable and portable neuromuscular stimulation system for drop foot correction and blood flow assist applications is presented. The system consists of a programmer unit and a portable, programmable stimulator unit. The portable stimulator features fully programmable, sensor-controlled, constant-voltage, dual-channel stimulation and accommodates a range of customized stimulation profiles. Trapezoidal and free-form adaptive stimulation intensity envelope algorithms are provided for drop foot correction applications, while time dependent and activity dependent algorithms are provided for blood flow assist applications. A variety of sensor types can be used with the portable unit, including force sensitive resistor-based foot switches and MEMS-based accelerometer and gyroscope devices. The paper provides a detailed description of the hardware and block-level system design for both units. The programming and operating procedures for the system are also presented. Finally, functional bench test results for the system are presented.

A programmable and portable NMES device for drop foot correction and blood flow assist applications.

PubMed

Breen, Paul P; Corley, Gavin J; O'Keeffe, Derek T; Conway, Richard; OLaighin, Gearoid

2007-01-01

The Duo-STIM, a new, programmable and portable neuromuscular stimulation system for drop foot correction and blood flow assist applications is presented. The system consists of a programmer unit and a portable, programmable stimulator unit. The portable stimulator features fully programmable, sensor-controlled, constant-voltage, dual-channel stimulation and accommodates a range of customized stimulation profiles. Trapezoidal and free-form adaptive stimulation intensity envelope algorithms are provided for drop foot correction applications, while time dependent and activity dependent algorithms are provided for blood flow assist applications. A variety of sensor types can be used with the portable unit, including force sensitive resistor based foot switches and NMES based accelerometer and gyroscope devices. The paper provides a detailed description of the hardware and block-level system design for both units. The programming and operating procedures for the system are also presented. Finally, functional bench test results for the system are presented.

Orbiter CIU/IUS communications hardware evaluation

NASA Technical Reports Server (NTRS)

Huth, G. K.

1979-01-01

The DOD and NASA inertial upper stage communication system design, hardware specifications and interfaces were analyzed to determine their compatibility with the Orbiter payload communications equipment (Payload Interrogator, Payload Signal Processors, Communications Interface Unit, and the Orbiter operational communications equipment (the S-Band and Ku-band systems). Topics covered include (1) IUS/shuttle Orbiter communications interface definition; (2) Orbiter avionics equipment serving the IUS; (3) IUS communication equipment; (4) IUS/shuttle Orbiter RF links; (5) STDN/TDRS S-band related activities; and (6) communication interface unit/Orbiter interface issues. A test requirement plan overview is included.

Workmanship Challenges for NASA Mission Hardware

NASA Technical Reports Server (NTRS)

Plante, Jeannette

2010-01-01

This slide presentation reviews several challenges in workmanship for NASA mission hardware development. Several standards for NASA workmanship exist, that are required for all programs, projects, contracts and subcontracts. These Standards contain our best known methods for avoiding past assembly problems and defects. These best practices may not be available if suppliers are used who are not compliant with them. Compliance includes having certified operators and inspectors. Some examples of problems that have occured from the lack of requirements flow-down to contractors are reviewed. The presentation contains a detailed example of the challenge in regards to The Packaging "Design" Dilemma.

The use of real-time, hardware-in-the-loop simulation in the design and development of the new Hughes HS601 spacecraft attitude control system

NASA Technical Reports Server (NTRS)

Slafer, Loren I.

1989-01-01

Realtime simulation and hardware-in-the-loop testing is being used extensively in all phases of the design, development, and testing of the attitude control system (ACS) for the new Hughes HS601 satellite bus. Realtime, hardware-in-the-loop simulation, integrated with traditional analysis and pure simulation activities is shown to provide a highly efficient and productive overall development program. Implementation of high fidelity simulations of the satellite dynamics and control system algorithms, capable of real-time execution (using applied Dynamics International's System 100), provides a tool which is capable of being integrated with the critical flight microprocessor to create a mixed simulation test (MST). The MST creates a highly accurate, detailed simulated on-orbit test environment, capable of open and closed loop ACS testing, in which the ACS design can be validated. The MST is shown to provide a valuable extension of traditional test methods. A description of the MST configuration is presented, including the spacecraft dynamics simulation model, sensor and actuator emulators, and the test support system. Overall system performance parameters are presented. MST applications are discussed; supporting ACS design, developing on-orbit system performance predictions, flight software development and qualification testing (augmenting the traditional software-based testing), mission planning, and a cost-effective subsystem-level acceptance test. The MST is shown to provide an ideal tool in which the ACS designer can fly the spacecraft on the ground.

Evaluation of methods for determining hardware projected life

NASA Technical Reports Server (NTRS)

1971-01-01

An investigation of existing methods of predicting hardware life is summarized by reviewing programs having long life requirements, current research efforts on long life problems, and technical papers reporting work on life predicting techniques. The results indicate that there are no accurate quantitative means to predict hardware life for system level hardware. The effectiveness of test programs and the cause of hardware failures is considered.

Broadband astigmatism-corrected spectrometer design using a toroidal lens and a special filter

NASA Astrophysics Data System (ADS)

Ge, Xianying; Chen, Siying; Zhang, Yinchao; Chen, He; Guo, Pan; Mu, Taotao; Yang, Jian; Bu, Zhichao

2015-01-01

In the paper, a method to obtain a broadband, astigmatism-corrected spectrometer based on the existing Czerny-Turner spectrometer is proposed. The theories of astigmatism correction using a toroidal lens and a special filter are described in detail. Performance comparisons of the modified spectrometer and the traditional spectrometer are also presented. Results show that with the new design the RMS spot radius in sagittal view is one-eightieth of that in the traditional spectrometer over a broadband spectral range from 300 to 700 nm, without changing or moving any optical elements in the traditional spectrometer.

VEG-01: Veggie Hardware Verification Testing

NASA Technical Reports Server (NTRS)

Massa, Gioia; Newsham, Gary; Hummerick, Mary; Morrow, Robert; Wheeler, Raymond

2013-01-01

The Veggie plant/vegetable production system is scheduled to fly on ISS at the end of2013. Since much of the technology associated with Veggie has not been previously tested in microgravity, a hardware validation flight was initiated. This test will allow data to be collected about Veggie hardware functionality on ISS, allow crew interactions to be vetted for future improvements, validate the ability of the hardware to grow and sustain plants, and collect data that will be helpful to future Veggie investigators as they develop their payloads. Additionally, food safety data on the lettuce plants grown will be collected to help support the development of a pathway for the crew to safely consume produce grown on orbit. Significant background research has been performed on the Veggie plant growth system, with early tests focusing on the development of the rooting pillow concept, and the selection of fertilizer, rooting medium and plant species. More recent testing has been conducted to integrate the pillow concept into the Veggie hardware and to ensure that adequate water is provided throughout the growth cycle. Seed sanitation protocols have been established for flight, and hardware sanitation between experiments has been studied. Methods for shipping and storage of rooting pillows and the development of crew procedures and crew training videos for plant activities on-orbit have been established. Science verification testing was conducted and lettuce plants were successfully grown in prototype Veggie hardware, microbial samples were taken, plant were harvested, frozen, stored and later analyzed for microbial growth, nutrients, and A TP levels. An additional verification test, prior to the final payload verification testing, is desired to demonstrate similar growth in the flight hardware and also to test a second set of pillows containing zinnia seeds. Issues with root mat water supply are being resolved, with final testing and flight scheduled for later in 2013.

Veggie and the VEG-01 Hardware Validation Test

NASA Technical Reports Server (NTRS)

Massa, Gioia; wheeler, Ray; Smith, Trent

2015-01-01

This presentation presents a brief overview of KSC plant science hardware for space and then details the Veggie hardware and the VEG-01 hardware validation test. The test results and future plans are discussed.

A hardware implementation of the discrete Pascal transform for image processing

NASA Astrophysics Data System (ADS)

Goodman, Thomas J.; Aburdene, Maurice F.

2006-02-01

The discrete Pascal transform is a polynomial transform with applications in pattern recognition, digital filtering, and digital image processing. It already has been shown that the Pascal transform matrix can be decomposed into a product of binary matrices. Such a factorization leads to a fast and efficient hardware implementation without the use of multipliers, which consume large amounts of hardware. We recently developed a field-programmable gate array (FPGA) implementation to compute the Pascal transform. Our goal was to demonstrate the computational efficiency of the transform while keeping hardware requirements at a minimum. Images are uploaded into memory from a remote computer prior to processing, and the transform coefficients can be offloaded from the FPGA board for analysis. Design techniques like as-soon-as-possible scheduling and adder sharing allowed us to develop a fast and efficient system. An eight-point, one-dimensional transform completes in 13 clock cycles and requires only four adders. An 8x8 two-dimensional transform completes in 240 cycles and requires only a top-level controller in addition to the one-dimensional transform hardware. Finally, through minor modifications to the controller, the transform operations can be pipelined to achieve 100% utilization of the four adders, allowing one eight-point transform to complete every seven clock cycles.

Programmable hardware for reconfigurable computing systems

NASA Astrophysics Data System (ADS)

Smith, Stephen

1996-10-01

In 1945 the work of J. von Neumann and H. Goldstein created the principal architecture for electronic computation that has now lasted fifty years. Nevertheless alternative architectures have been created that have computational capability, for special tasks, far beyond that feasible with von Neumann machines. The emergence of high capacity programmable logic devices has made the realization of these architectures practical. The original ENIAC and EDVAC machines were conceived to solve special mathematical problems that were far from today's concept of 'killer applications.' In a similar vein programmable hardware computation is being used today to solve unique mathematical problems. Our programmable hardware activity is focused on the research and development of novel computational systems based upon the reconfigurability of our programmable logic devices. We explore our programmable logic architectures and their implications for programmable hardware. One programmable hardware board implementation is detailed.

Software requirements flow-down and preliminary software design for the G-CLEF spectrograph

NASA Astrophysics Data System (ADS)

Evans, Ian N.; Budynkiewicz, Jamie A.; DePonte Evans, Janet; Miller, Joseph B.; Onyuksel, Cem; Paxson, Charles; Plummer, David A.

2016-08-01

The Giant Magellan Telescope (GMT)-Consortium Large Earth Finder (G-CLEF) is a fiber-fed, precision radial velocity (PRV) optical echelle spectrograph that will be the first light instrument on the GMT. The G-CLEF instrument device control subsystem (IDCS) provides software control of the instrument hardware, including the active feedback loops that are required to meet the G-CLEF PRV stability requirements. The IDCS is also tasked with providing operational support packages that include data reduction pipelines and proposal preparation tools. A formal, but ultimately pragmatic approach is being used to establish a complete and correct set of requirements for both the G-CLEF device control and operational support packages. The device control packages must integrate tightly with the state-machine driven software and controls reference architecture designed by the GMT Organization. A model-based systems engineering methodology is being used to develop a preliminary design that meets these requirements. Through this process we have identified some lessons that have general applicability to the development of software for ground-based instrumentation. For example, tasking an individual with overall responsibility for science/software/hardware integration is a key step to ensuring effective integration between these elements. An operational concept document that includes detailed routine and non- routine operational sequences should be prepared in parallel with the hardware design process to tie together these elements and identify any gaps. Appropriate time-phasing of the hardware and software design phases is important, but revisions to driving requirements that impact software requirements and preliminary design are inevitable. Such revisions must be carefully managed to ensure efficient use of resources.

Computer hardware fault administration

DOEpatents

Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

2010-09-14

Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

QCAPUF: QCA-based physically unclonable function as a hardware security primitive

NASA Astrophysics Data System (ADS)

Abutaleb, M. M.

2018-04-01

Physically unclonable functions (PUFs) are increasingly used as innovative security primitives to provide the hardware authentication and identification as well as the secret key generation based on unique and random variations in identically fabricated devices. Security and low power have appeared to become two crucial necessities to modern designs. As an emerging nanoelectronic technology, a quantum-dot cellular automata (QCA) can achieve ultra-low power consumption as well as an extremely small area for implementing digital designs. However, there are various classes of permanent defects that can happen during the manufacture of QCA devices. The recent extensive research has been focused on how to eliminate errors in QCA structures resulting from fabrication variances. By a completely different vision, to turn this disadvantage into an advantage, this paper presents a novel QCA-based PUF (QCAPUF) architecture to exploit the unique physical characteristics of fabricated QCA cells in order to produce different hardware fingerprint instances. This architecture is composed of proposed logic and interconnect blocks that have critical vulnerabilities and perform unexpected logical operations. The behaviour of QCAPUF is thoroughly analysed through physical relations and simulations. Results confirm that the proposed QCAPUF has state of the art PUF characteristics in the QCA technology. This paper will serve as a basis for further research into QCA-based hardware security primitives and applications.

Environmental Control and Life Support (ECLS) Hardware Commonality for Exploration Vehicles

NASA Technical Reports Server (NTRS)

Carrasquillo, Robyn; Anderson, Molly

2012-01-01

In August 2011, the Environmental Control and Life Support Systems (ECLSS) technical community, along with associated stakeholders, held a workshop to review NASA s plans for Exploration missions and vehicles with two objectives: revisit the Exploration Atmospheres Working Group (EAWG) findings from 2006, and discuss preliminary ECLSS architecture concepts and technology choices for Exploration vehicles, identifying areas for potential common hardware or technologies to be utilized. Key considerations for selection of vehicle design total pressure and percent oxygen include operational concepts for extravehicular activity (EVA) and prebreathe protocols, materials flammability, and controllability within pressure and oxygen ranges. New data for these areas since the 2006 study were presented and discussed, and the community reached consensus on conclusions and recommendations for target design pressures for each Exploration vehicle concept. For the commonality study, the workshop identified many areas of potential commonality across the Exploration vehicles as well as with heritage International Space Station (ISS) and Shuttle hardware. Of the 36 ECLSS functions reviewed, 16 were considered to have strong potential for commonality, 13 were considered to have some potential commonality, and 7 were considered to have limited potential for commonality due to unique requirements or lack of sufficient heritage hardware. These findings, which will be utilized in architecture studies and budget exercises going forward, are presented in detail.

Architecture of a platform for hardware-in-the-loop simulation of flying vehicle control systems

NASA Astrophysics Data System (ADS)

Belokon', S. A.; Zolotukhin, Yu. N.; Filippov, M. N.

2017-07-01

A hardware-software platform is presented, which is designed for the development and hardware-in-the-loop simulation of flying vehicle control systems. This platform ensures the construction of the mathematical model of the plant, development of algorithms and software for onboard radioelectronic equipment and ground control station, and visualization of the three-dimensional model of the vehicle and external environment of the cockpit in the simulator training mode.

Hardware efficient monitoring of input/output signals

NASA Technical Reports Server (NTRS)

Driscoll, Kevin R. (Inventor); Hall, Brendan (Inventor); Paulitsch, Michael (Inventor)

2012-01-01

A communication device comprises first and second circuits to implement a plurality of ports via which the communicative device is operable to communicate over a plurality of communication channels. For each of the plurality of ports, the communication device comprises: command hardware that includes a first transmitter to transmit data over a respective one of the plurality of channels and a first receiver to receive data from the respective one of the plurality of channels; and monitor hardware that includes a second receiver coupled to the first transmitter and a third receiver coupled to the respective one of the plurality of channels. The first circuit comprises the command hardware for a first subset of the plurality of ports. The second circuit comprises the monitor hardware for the first subset of the plurality of ports and the command hardware for a second subset of the plurality of ports.

Methodology for Assessing Reusability of Spaceflight Hardware

NASA Technical Reports Server (NTRS)

Childress-Thompson, Rhonda; Thomas, L. Dale; Farrington, Phillip

2017-01-01

In 2011 the Space Shuttle, the only Reusable Launch Vehicle (RLV) in the world, returned to earth for the final time. Upon retirement of the Space Shuttle, the United States (U.S.) no longer possessed a reusable vehicle or the capability to send American astronauts to space. With the National Aeronautics and Space Administration (NASA) out of the RLV business and now only pursuing Expendable Launch Vehicles (ELV), not only did companies within the U.S. start to actively pursue the development of either RLVs or reusable components, but entities around the world began to venture into the reusable market. For example, SpaceX and Blue Origin are developing reusable vehicles and engines. The Indian Space Research Organization is developing a reusable space plane and Airbus is exploring the possibility of reusing its first stage engines and avionics housed in the flyback propulsion unit referred to as the Advanced Expendable Launcher with Innovative engine Economy (Adeline). Even United Launch Alliance (ULA) has announced plans for eventually replacing the Atlas and Delta expendable rockets with a family of RLVs called Vulcan. Reuse can be categorized as either fully reusable, the situation in which the entire vehicle is recovered, or partially reusable such as the National Space Transportation System (NSTS) where only the Space Shuttle, Space Shuttle Main Engines (SSME), and Solid Rocket Boosters (SRB) are reused. With this influx of renewed interest in reusability for space applications, it is imperative that a systematic approach be developed for assessing the reusability of spaceflight hardware. The partially reusable NSTS offered many opportunities to glean lessons learned; however, when it came to efficient operability for reuse the Space Shuttle and its associated hardware fell short primarily because of its two to four-month turnaround time. Although there have been several attempts at designing RLVs in the past with the X-33, Venture Star and Delta Clipper

Summary of materials and hardware performance on LDEF

NASA Technical Reports Server (NTRS)

Dursch, Harry; Pippin, Gary; Teichman, Lou

1993-01-01

A wide variety of materials and experiment support hardware were flown on the Long Duration Exposure Facility (LDEF). Postflight testing has determined the effects of the almost 6 years of low-earth orbit (LEO) exposure on this hardware. An overview of the results are presented. Hardware discussed includes adhesives, fasteners, lubricants, data storage systems, solar cells, seals, and the LDEF structure. Lessons learned from the testing and analysis of LDEF hardware is also presented.

Distributed and Modular CAN-Based Architecture for Hardware Control and Sensor Data Integration

PubMed Central

Losada, Diego P.; Fernández, Joaquín L.; Paz, Enrique; Sanz, Rafael

2017-01-01

In this article, we present a CAN-based (Controller Area Network) distributed system to integrate sensors, actuators and hardware controllers in a mobile robot platform. With this work, we provide a robust, simple, flexible and open system to make hardware elements or subsystems communicate, that can be applied to different robots or mobile platforms. Hardware modules can be connected to or disconnected from the CAN bus while the system is working. It has been tested in our mobile robot Rato, based on a RWI (Real World Interface) mobile platform, to replace the old sensor and motor controllers. It has also been used in the design of two new robots: BellBot and WatchBot. Currently, our hardware integration architecture supports different sensors, actuators and control subsystems, such as motor controllers and inertial measurement units. The integration architecture was tested and compared with other solutions through a performance analysis of relevant parameters such as transmission efficiency and bandwidth usage. The results conclude that the proposed solution implements a lightweight communication protocol for mobile robot applications that avoids transmission delays and overhead. PMID:28467381

Distributed and Modular CAN-Based Architecture for Hardware Control and Sensor Data Integration.

PubMed

Losada, Diego P; Fernández, Joaquín L; Paz, Enrique; Sanz, Rafael

2017-05-03

In this article, we present a CAN-based (Controller Area Network) distributed system to integrate sensors, actuators and hardware controllers in a mobile robot platform. With this work, we provide a robust, simple, flexible and open system to make hardware elements or subsystems communicate, that can be applied to different robots or mobile platforms. Hardware modules can be connected to or disconnected from the CAN bus while the system is working. It has been tested in our mobile robot Rato, based on a RWI (Real World Interface) mobile platform, to replace the old sensor and motor controllers. It has also been used in the design of two new robots: BellBot and WatchBot. Currently, our hardware integration architecture supports different sensors, actuators and control subsystems, such as motor controllers and inertial measurement units. The integration architecture was tested and compared with other solutions through a performance analysis of relevant parameters such as transmission efficiency and bandwidth usage. The results conclude that the proposed solution implements a lightweight communication protocol for mobile robot applications that avoids transmission delays and overhead.

Getting expert systems off the ground: Lessons learned from integrating model-based diagnostics with prototype flight hardware

NASA Technical Reports Server (NTRS)

Stephan, Amy; Erikson, Carol A.

1991-01-01

As an initial attempt to introduce expert system technology into an onboard environment, a model based diagnostic system using the TRW MARPLE software tool was integrated with prototype flight hardware and its corresponding control software. Because this experiment was designed primarily to test the effectiveness of the model based reasoning technique used, the expert system ran on a separate hardware platform, and interactions between the control software and the model based diagnostics were limited. While this project met its objective of showing that model based reasoning can effectively isolate failures in flight hardware, it also identified the need for an integrated development path for expert system and control software for onboard applications. In developing expert systems that are ready for flight, artificial intelligence techniques must be evaluated to determine whether they offer a real advantage onboard, identify which diagnostic functions should be performed by the expert systems and which are better left to the procedural software, and work closely with both the hardware and the software developers from the beginning of a project to produce a well designed and thoroughly integrated application.

High-performance reconfigurable hardware architecture for restricted Boltzmann machines.

PubMed

Ly, Daniel Le; Chow, Paul

2010-11-01

Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications has been limited. A primary cause for this lack of adoption is that neural networks are usually implemented as software running on general-purpose processors. Hence, a hardware implementation that can exploit the inherent parallelism in neural networks is desired. This paper investigates how the restricted Boltzmann machine (RBM), which is a popular type of neural network, can be mapped to a high-performance hardware architecture on field-programmable gate array (FPGA) platforms. The proposed modular framework is designed to reduce the time complexity of the computations through heavily customized hardware engines. A method to partition large RBMs into smaller congruent components is also presented, allowing the distribution of one RBM across multiple FPGA resources. The framework is tested on a platform of four Xilinx Virtex II-Pro XC2VP70 FPGAs running at 100 MHz through a variety of different configurations. The maximum performance was obtained by instantiating an RBM of 256 × 256 nodes distributed across four FPGAs, which resulted in a computational speed of 3.13 billion connection-updates-per-second and a speedup of 145-fold over an optimized C program running on a 2.8-GHz Intel processor.

Improving the efficiency of a user-driven learning system with reconfigurable hardware. Application to DNA splicing.

PubMed

Lemoine, E; Merceron, D; Sallantin, J; Nguifo, E M

1999-01-01

This paper describes a new approach to problem solving by splitting up problem component parts between software and hardware. Our main idea arises from the combination of two previously published works. The first one proposed a conceptual environment of concept modelling in which the machine and the human expert interact. The second one reported an algorithm based on reconfigurable hardware system which outperforms any kind of previously published genetic data base scanning hardware or algorithms. Here we show how efficient the interaction between the machine and the expert is when the concept modelling is based on reconfigurable hardware system. Their cooperation is thus achieved with an real time interaction speed. The designed system has been partially applied to the recognition of primate splice junctions sites in genetic sequences.

Space hardware designs, volume 1

NASA Technical Reports Server (NTRS)

Meyer, Rudolf X.; Cribbs, Richard; Honda, Mark; Ma, Christina; Robson, Christopher

1994-01-01

The design of a solar sail space vehicle with a novel sail deployment mechanism is described. The sail is triangular in shape and is deployed and stabilized by three miniature spacecraft, one at each corner of the triangle. A concept demonstrator for a spherical microrover for the exploration of a planetary surface is described. Lastly, laboratory experiments have been conducted to study the migration of thin oil films on metal surfaces in the presence of a thermal gradient.

Software and hardware infrastructure for research in electrophysiology

PubMed Central

Mouček, Roman; Ježek, Petr; Vařeka, Lukáš; Řondík, Tomáš; Brůha, Petr; Papež, Václav; Mautner, Pavel; Novotný, Jiří; Prokop, Tomáš; Štěbeták, Jan

2014-01-01

As in other areas of experimental science, operation of electrophysiological laboratory, design and performance of electrophysiological experiments, collection, storage and sharing of experimental data and metadata, analysis and interpretation of these data, and publication of results are time consuming activities. If these activities are well organized and supported by a suitable infrastructure, work efficiency of researchers increases significantly. This article deals with the main concepts, design, and development of software and hardware infrastructure for research in electrophysiology. The described infrastructure has been primarily developed for the needs of neuroinformatics laboratory at the University of West Bohemia, the Czech Republic. However, from the beginning it has been also designed and developed to be open and applicable in laboratories that do similar research. After introducing the laboratory and the whole architectural concept the individual parts of the infrastructure are described. The central element of the software infrastructure is a web-based portal that enables community researchers to store, share, download and search data and metadata from electrophysiological experiments. The data model, domain ontology and usage of semantic web languages and technologies are described. Current data publication policy used in the portal is briefly introduced. The registration of the portal within Neuroscience Information Framework is described. Then the methods used for processing of electrophysiological signals are presented. The specific modifications of these methods introduced by laboratory researches are summarized; the methods are organized into a laboratory workflow. Other parts of the software infrastructure include mobile and offline solutions for data/metadata storing and a hardware stimulator communicating with an EEG amplifier and recording software. PMID:24639646

Software and hardware infrastructure for research in electrophysiology.

PubMed

Mouček, Roman; Ježek, Petr; Vařeka, Lukáš; Rondík, Tomáš; Brůha, Petr; Papež, Václav; Mautner, Pavel; Novotný, Jiří; Prokop, Tomáš; Stěbeták, Jan

2014-01-01

As in other areas of experimental science, operation of electrophysiological laboratory, design and performance of electrophysiological experiments, collection, storage and sharing of experimental data and metadata, analysis and interpretation of these data, and publication of results are time consuming activities. If these activities are well organized and supported by a suitable infrastructure, work efficiency of researchers increases significantly. This article deals with the main concepts, design, and development of software and hardware infrastructure for research in electrophysiology. The described infrastructure has been primarily developed for the needs of neuroinformatics laboratory at the University of West Bohemia, the Czech Republic. However, from the beginning it has been also designed and developed to be open and applicable in laboratories that do similar research. After introducing the laboratory and the whole architectural concept the individual parts of the infrastructure are described. The central element of the software infrastructure is a web-based portal that enables community researchers to store, share, download and search data and metadata from electrophysiological experiments. The data model, domain ontology and usage of semantic web languages and technologies are described. Current data publication policy used in the portal is briefly introduced. The registration of the portal within Neuroscience Information Framework is described. Then the methods used for processing of electrophysiological signals are presented. The specific modifications of these methods introduced by laboratory researches are summarized; the methods are organized into a laboratory workflow. Other parts of the software infrastructure include mobile and offline solutions for data/metadata storing and a hardware stimulator communicating with an EEG amplifier and recording software.

Tri-FAST Hardware-in-the-Loop Simulation. Volume I. Tri-FAST Hardware-in-the-Loop Simulation at the Advanced Simulation Center

DTIC Science & Technology

1979-03-28

TECHNICAL REPORT T-79-43 TRI- FAST HARDWARE-IN-THE-LOOP SIMULATION Volume 1: Trn FAST Hardware-In-the. Loop Simulation at the Advanced Simulation...Identify by block number) Tri- FAST Hardware-in-the-Loop ACSL Advanced Simulation Center Simulation RF Target Models I a. AfIACT ( sin -oveme skit N nem...e n tdositr by block number) The purpose of this report is to document the Tri- FAST missile simulation development and the seeker hardware-in-the

34 CFR 403.100 - What are the requirements for designating a State corrections educational agency to administer...

Code of Federal Regulations, 2010 CFR

2010-07-01

... corrections educational agency to administer the Programs for Criminal Offenders? 403.100 Section 403.100... ADULT EDUCATION, DEPARTMENT OF EDUCATION STATE VOCATIONAL AND APPLIED TECHNOLOGY EDUCATION PROGRAM What... § 403.100 What are the requirements for designating a State corrections educational agency to administer...

Remote hardware-reconfigurable robotic camera

NASA Astrophysics Data System (ADS)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar; Maya-Rueda, Selene E.

2001-10-01

In this work, a camera with integrated image processing capabilities is discussed. The camera is based on an imager coupled to an FPGA device (Field Programmable Gate Array) which contains an architecture for real-time computer vision low-level processing. The architecture can be reprogrammed remotely for application specific purposes. The system is intended for rapid modification and adaptation for inspection and recognition applications, with the flexibility of hardware and software reprogrammability. FPGA reconfiguration allows the same ease of upgrade in hardware as a software upgrade process. The camera is composed of a digital imager coupled to an FPGA device, two memory banks, and a microcontroller. The microcontroller is used for communication tasks and FPGA programming. The system implements a software architecture to handle multiple FPGA architectures in the device, and the possibility to download a software/hardware object from the host computer into its internal context memory. System advantages are: small size, low power consumption, and a library of hardware/software functionalities that can be exchanged during run time. The system has been validated with an edge detection and a motion processing architecture, which will be presented in the paper. Applications targeted are in robotics, mobile robotics, and vision based quality control.

Data to hardware binding with physical unclonable functions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hamlet, Jason

The various technologies presented herein relate to binding data (e.g., software) to hardware, wherein the hardware is to utilize the data. The generated binding can be utilized to detect whether at least one of the hardware or the data has been modified between an initial moment (enrollment) and a later moment (authentication). During enrollment, an enrollment value is generated that includes a signature of the data, a first response from a PUF located on the hardware, and a code word. During authentication, a second response from the PUF is utilized to authenticate any of the content in the enrollment value,more » and based upon the authentication, a determination can be made regarding whether the hardware and/or the data have been modified. If modification is detected then a mitigating operation can be performed, e.g., the hardware is prevented from utilizing the data. If no modification is detected, the data can be utilized.« less

Recent Developments in Hardware-in-the-Loop Formation Navigation and Control

NASA Technical Reports Server (NTRS)

Mitchell, Jason W.; Luquette, Richard J.

2005-01-01

The Formation Flying Test-Bed (FFTB) at NASA Goddard Space Flight Center (GSFC) provides a hardware-in-the-loop test environment for formation navigation and control. The facility is evolving as a modular, hybrid, dynamic simulation facility for end-tc-end guidance, navigation, and control (GN&C) design and analysis of formation flying spacecraft. The core capabilities of the FFTB, as a platform for testing critical hardware and software algorithms in-the-loop, are reviewed with a focus on many recent improvements. Two significant upgrades to the FFTB are a message-oriented middleware (MOM) architecture, and a software crosslink for inter-spacecraft ranging. The MOM architecture provides a common messaging bus for software agents, easing integration, arid supporting the GSFC Mission Services Evolution Center (GMSEC) architecture via software bridge. Additionally, the FFTB s hardware capabilities are expanding. Recently, two Low-Power Transceivers (LPTs) with ranging capability have been introduced into the FFTB. The LPT crosslinks will be connected to a modified Crosslink Channel Simulator (CCS), which applies realistic space-environment effects to the Radio Frequency (RF) signals produced by the LPTs.

Growth in spaceflight hardware results in alterations to the transcriptome and proteome

NASA Astrophysics Data System (ADS)

Basu, Proma; Kruse, Colin P. S.; Luesse, Darron R.; Wyatt, Sarah E.

2017-11-01

The Biological Research in Canisters (BRIC) hardware has been used to house many biology experiments on both the Space Transport System (STS, commonly known as the space shuttle) and the International Space Station (ISS). However, microscopic examination of Arabidopsis seedlings by Johnson et al. (2015) indicated the hardware itself may affect cell morphology. The experiment herein was designed to assess the effects of the BRIC-Petri Dish Fixation Units (BRIC-PDFU) hardware on the transcriptome and proteome of Arabidopsis seedlings. To our knowledge, this is the first transcriptomic and proteomic comparison of Arabidopsis seedlings grown with and without hardware. Arabidopsis thaliana wild-type Columbia (Col-0) seeds were sterilized and bulk plated on forty-four 60 mm Petri plates, of which 22 were integrated into the BRIC-PDFU hardware and 22 were maintained in closed containers at Ohio University. Seedlings were grown for approximately 3 days, fixed with RNAlater® and stored at -80 °C prior to RNA and protein extraction, with proteins separated into membrane and soluble fractions prior to analysis. The RNAseq analysis identified 1651 differentially expressed genes; MS/MS analysis identified 598 soluble and 589 membrane proteins differentially abundant both at p < .05. Fold enrichment analysis of gene ontology terms related to differentially expressed transcripts and proteins highlighted a variety of stress responses. Some of these genes and proteins have been previously identified in spaceflight experiments, indicating that these genes and proteins may be perturbed by both conditions.

Progress on PEEM3 -- An Aberration Corrected X-Ray Photoemission Electron Microscope at the ALS

DOE Office of Scientific and Technical Information (OSTI.GOV)

MacDowell, A. A.; Feng, J.; DeMello, A.

2007-01-19

A new ultrahigh-resolution photoemission electron microscope called PEEM3 is being developed and built at the Advanced Light Source (ALS). An electron mirror combined with a much-simplified magnetic dipole separator is to be used to provide simultaneous correction of spherical and chromatic aberrations. It is installed on an elliptically polarized undulator (EPU) beamline, and will be operated with very high spatial resolution and high flux to study the composition, structure, electric and magnetic properties of complex materials. The instrument has been designed and is described. The instrumental hardware is being deployed in 2 phases. The first phase is the deployment ofmore » a standard PEEM type microscope consisting of the standard linear array of electrostatic electron lenses. The second phase will be the installation of the aberration corrected upgrade to improve resolution and throughput. This paper describes progress as the instrument enters the commissioning part of the first phase.« less

Progress on PEEM3 - An Aberration Corrected X-Ray PhotoemissionElectron Microscope at the ALS

DOE Office of Scientific and Technical Information (OSTI.GOV)

MacDowell, Alastair A.; Feng, J.; DeMello, A.

2006-05-20

A new ultrahigh-resolution photoemission electron microscope called PEEM3 is being developed and built at the Advanced Light Source (ALS). An electron mirror combined with a much-simplified magnetic dipole separator is to be used to provide simultaneous correction of spherical and chromatic aberrations. It is installed on an elliptically polarized undulator (EPU) beamline, and will be operated with very high spatial resolution and high flux to study the composition, structure, electric and magnetic properties of complex materials. The instrument has been designed and is described. The instrumental hardware is being deployed in 2 phases. The first phase is the deployment ofmore » a standard PEEM type microscope consisting of the standard linear array of electrostatic electron lenses. The second phase will be the installation of the aberration corrected upgrade to improve resolution and throughput. This paper describes progress as the instrument enters the commissioning part of the first phase.« less

Use of Heritage Hardware on Orion MPCV Exploration Flight Test One

NASA Technical Reports Server (NTRS)

Rains, George Edward; Cross, Cynthia D.

2012-01-01

Due to an aggressive schedule for the first space flight of an unmanned Orion capsule, currently known as Exploration Flight Test One (EFT1), combined with severe programmatic funding constraints, an effort was made within the Orion Program to identify heritage hardware, i.e., already existing, flight-certified components from previous manned space programs, which might be available for use on EFT1. With the end of the Space Shuttle Program, no current means exists to launch Multi-Purpose Logistics Modules (MPLMs) to the International Space Station (ISS), and so the inventory of many flight-certified Shuttle and MPLM components are available for other purposes. Two of these items are the MPLM cabin Positive Pressure Relief Assembly (PPRA), and the Shuttle Ground Support Equipment Heat Exchanger (GSE HX). In preparation for the utilization of these components by the Orion Program, analyses and testing of the hardware were performed. The PPRA had to be analyzed to determine its susceptibility to pyrotechnic shock, and vibration testing had to be performed, since those environments are predicted to be more severe during an Orion mission than those the hardware was originally designed to accommodate. The GSE HX had to be tested for performance with the Orion thermal working fluids, which are different from those used by the Space Shuttle. This paper summarizes the activities required in order to utilize heritage hardware for EFT1.

An Environmental for Hardware-in-the-Loop Formation Navigation and Control

NASA Technical Reports Server (NTRS)

Burns, Rich; Naasz, Bo; Gaylor, Dave; Higinbotham, John

2004-01-01

Recent interest in formation flying satellite systems has spurred a considerable amount of research in the relative navigation and control of satellites. Development in this area has included new estimation and control algorithms as well as sensor and actuator development specifically geared toward the relative control problem. This paper describes a simulation facility, the Formation Flying Test Bed (FFTB) at NASA Goddard Space Flight Center, which allows engineers to test new algorithms for the formation flying problem with relevant GN&C hardware in a closed loop simulation. The FFTB currently supports the inclusion of GPS receiver hardware in the simulation loop. Support for satellite crosslink ranging technology is at a prototype stage. This closed-loop, hardware inclusive simulation capability permits testing of navigation and control software in the presence of the actual hardware with which the algorithms must interact. This capability provides the navigation or control developer with a perspective on how the algorithms perform as part of the closed-loop system. In this paper, the overall design and evolution of the FFTB are presented. Each component of the FFTB is then described. Interfaces between the components of the FFTB are shown and the interfaces to and between navigation and control software are described. Finally, an example of closed-loop formation control with GPS receivers in the loop is presented.

Research on starlight hardware-in-the-loop simulator

NASA Astrophysics Data System (ADS)

Zhang, Ying; Gao, Yang; Qu, Huiyang; Liu, Dongfang; Du, Huijie; Lei, Jie

2016-10-01

The starlight navigation is considered to be one of the most important methods for spacecraft navigation. Starlight simulation system is a high-precision system with large fields of view, designed to test the starlight navigation sensor performance on the ground. A complete hardware-in-the-loop simulation of the system has been built. The starlight simulator is made up of light source, light source controller, light filter, LCD, collimator and control computer. LCD is the key display component of the system, and is installed at the focal point of the collimator. For the LCD cannot emit light itself, so light source and light source power controller is specially designed for the brightness demanded by the LCD. Light filter is designed for the dark background which is also needed in the simulation.

Loads and Structural Dynamics Requirements for Spaceflight Hardware

NASA Technical Reports Server (NTRS)

Schultz, Kenneth P.

2011-01-01

The purpose of this document is to establish requirements relating to the loads and structural dynamics technical discipline for NASA and commercial spaceflight launch vehicle and spacecraft hardware. Requirements are defined for the development of structural design loads and recommendations regarding methodologies and practices for the conduct of load analyses are provided. As such, this document represents an implementation of NASA STD-5002. Requirements are also defined for structural mathematical model development and verification to ensure sufficient accuracy of predicted responses. Finally, requirements for model/data delivery and exchange are specified to facilitate interactions between Launch Vehicle Providers (LVPs), Spacecraft Providers (SCPs), and the NASA Technical Authority (TA) providing insight/oversight and serving in the Independent Verification and Validation role. In addition to the analysis-related requirements described above, a set of requirements are established concerning coupling phenomena or other interaction between structural dynamics and aerodynamic environments or control or propulsion system elements. Such requirements may reasonably be considered structure or control system design criteria, since good engineering practice dictates consideration of and/or elimination of the identified conditions in the development of those subsystems. The requirements are included here, however, to ensure that such considerations are captured in the design space for launch vehicles (LV), spacecraft (SC) and the Launch Abort Vehicle (LAV). The requirements in this document are focused on analyses to be performed to develop data needed to support structural verification. As described in JSC 65828, Structural Design Requirements and Factors of Safety for Spaceflight Hardware, implementation of the structural verification requirements is expected to be described in a Structural Verification Plan (SVP), which should describe the verification of each

An update on SCARLET hardware development and flight programs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jones, P.A.; Murphy, D.M.; Piszczor, M.F.

1995-10-01

Solar Concentrator Array with Refractive Linear Element Technology (SCARLET) is one of the first practical photovoltaic concentrator array technologies that offers a number of benefits for space applications (i.e. high array efficiency, protection from space radiation effects, a relatively light weight system, minimized plasma interactions, etc.) The line-focus concentrator concept, however, also offers two very important advantages: (1) low-cost mass production potential of the lens material; and (2) relaxation of precise array tracking requirements to only a single axis. These benefits offer unique capabilities to both commercial and government spacecraft users, specifically those interested in high radiation missions, such asmore » MEO orbits, and electric-powered propulsion LEO-to-GEO orbit raising applications. SCARLET is an aggressive hardware development and flight validation program sponsored by the Ballistic Missile Defense Organization (BMDO) and NASA Lewis Research Center. Its intent is to bring technology to the level of performance and validation necessary for use by various government and commercial programs. The first phase of the SCARLET program culminated with the design, development and fabrication of a small concentrator array for flight on the METEOR satellite. This hardware will be the first in-space demonstration of concentrator technology at the `array level` and will provide valuable in-orbit performance measurements. The METEOR satellite is currently planned for a September/October 1995 launch. The next phase of the program is the development of large array for use by one of the NASA New Millenium Program missions. This hardware will incorporate a number of the significant improvements over the basic METEOR design. This presentation will address the basic SCARLET technology, examine its benefits to users, and describe the expected improvements for future missions.« less

Long life assurance study for manned spacecraft long life hardware. Volume 1: Summary of long life assurance guidelines

NASA Technical Reports Server (NTRS)

1972-01-01

A long life assurance program for the development of design, process, test, and application guidelines for achieving reliable spacecraft hardware was conducted. The study approach consisted of a review of technical data performed concurrently with a survey of the aerospace industry. The data reviewed included design and operating characteristics, failure histories and solutions, and similar documents. The topics covered by the guidelines are reported. It is concluded that long life hardware is achieved through meticulous attention to many details and no simple set of rules can suffice.

OpenMM 4: A Reusable, Extensible, Hardware Independent Library for High Performance Molecular Simulation.

PubMed

Eastman, Peter; Friedrichs, Mark S; Chodera, John D; Radmer, Randall J; Bruns, Christopher M; Ku, Joy P; Beauchamp, Kyle A; Lane, Thomas J; Wang, Lee-Ping; Shukla, Diwakar; Tye, Tony; Houston, Mike; Stich, Timo; Klein, Christoph; Shirts, Michael R; Pande, Vijay S

2013-01-08

OpenMM is a software toolkit for performing molecular simulations on a range of high performance computing architectures. It is based on a layered architecture: the lower layers function as a reusable library that can be invoked by any application, while the upper layers form a complete environment for running molecular simulations. The library API hides all hardware-specific dependencies and optimizations from the users and developers of simulation programs: they can be run without modification on any hardware on which the API has been implemented. The current implementations of OpenMM include support for graphics processing units using the OpenCL and CUDA frameworks. In addition, OpenMM was designed to be extensible, so new hardware architectures can be accommodated and new functionality (e.g., energy terms and integrators) can be easily added.

Hardware for Accelerating N-Modular Redundant Systems for High-Reliability Computing

NASA Technical Reports Server (NTRS)

Dobbs, Carl, Sr.

2012-01-01

A hardware unit has been designed that reduces the cost, in terms of performance and power consumption, for implementing N-modular redundancy (NMR) in a multiprocessor device. The innovation monitors transactions to memory, and calculates a form of sumcheck on-the-fly, thereby relieving the processors of calculating the sumcheck in software

Software for Managing Inventory of Flight Hardware

NASA Technical Reports Server (NTRS)

Salisbury, John; Savage, Scott; Thomas, Shirman

2003-01-01

The Flight Hardware Support Request System (FHSRS) is a computer program that relieves engineers at Marshall Space Flight Center (MSFC) of most of the non-engineering administrative burden of managing an inventory of flight hardware. The FHSRS can also be adapted to perform similar functions for other organizations. The FHSRS affords a combination of capabilities, including those formerly provided by three separate programs in purchasing, inventorying, and inspecting hardware. The FHSRS provides a Web-based interface with a server computer that supports a relational database of inventory; electronic routing of requests and approvals; and electronic documentation from initial request through implementation of quality criteria, acquisition, receipt, inspection, storage, and final issue of flight materials and components. The database lists both hardware acquired for current projects and residual hardware from previous projects. The increased visibility of residual flight components provided by the FHSRS has dramatically improved the re-utilization of materials in lieu of new procurements, resulting in a cost savings of over $1.7 million. The FHSRS includes subprograms for manipulating the data in the database, informing of the status of a request or an item of hardware, and searching the database on any physical or other technical characteristic of a component or material. The software structure forces normalization of the data to facilitate inquiries and searches for which users have entered mixed or inconsistent values.

Agile hardware and software systems engineering for critical military space applications

NASA Astrophysics Data System (ADS)

Huang, Philip M.; Knuth, Andrew A.; Krueger, Robert O.; Garrison-Darrin, Margaret A.

2012-06-01

The Multi Mission Bus Demonstrator (MBD) is a successful demonstration of agile program management and system engineering in a high risk technology application where utilizing and implementing new, untraditional development strategies were necessary. MBD produced two fully functioning spacecraft for a military/DOD application in a record breaking time frame and at dramatically reduced costs. This paper discloses the adaptation and application of concepts developed in agile software engineering to hardware product and system development for critical military applications. This challenging spacecraft did not use existing key technology (heritage hardware) and created a large paradigm shift from traditional spacecraft development. The insertion of new technologies and methods in space hardware has long been a problem due to long build times, the desire to use heritage hardware, and lack of effective process. The role of momentum in the innovative process can be exploited to tackle ongoing technology disruptions and allowing risk interactions to be mitigated in a disciplined manner. Examples of how these concepts were used during the MBD program will be delineated. Maintaining project momentum was essential to assess the constant non recurring technological challenges which needed to be retired rapidly from the engineering risk liens. Development never slowed due to tactical assessment of the hardware with the adoption of the SCRUM technique. We adapted this concept as a representation of mitigation of technical risk while allowing for design freeze later in the program's development cycle. By using Agile Systems Engineering and Management techniques which enabled decisive action, the product development momentum effectively was used to produce two novel space vehicles in a fraction of time with dramatically reduced cost.

UniBoard: generic hardware for radio astronomy signal processing

NASA Astrophysics Data System (ADS)

Hargreaves, J. E.

2012-09-01

UniBoard is a generic high-performance computing platform for radio astronomy, developed as a Joint Research Activity in the RadioNet FP7 Programme. The hardware comprises eight Altera Stratix IV Field Programmable Gate Arrays (FPGAs) interconnected by a high speed transceiver mesh. Each FPGA is connected to two DDR3 memory modules and three external 10Gbps ports. In addition, a total of 128 low voltage differential input lines permit connection to external ADC cards. The DSP capability of the board exceeds 644E9 complex multiply-accumulate operations per second. The first production run of eight boards was distributed to partners in The Netherlands, France, Italy, UK, China and Korea in May 2011, with a further production runs completed in December 2011 and early 2012. The function of the board is determined by the firmware loaded into its FPGAs. Current applications include beamformers, correlators, digital receivers, RFI mitigation for pulsar astronomy, and pulsar gating and search machines The new UniBoard based correlator for the European VLBI network (EVN) uses an FX architecture with half the resources of the board devoted to station based processing: delay and phase correction and channelization, and half to the correlation function. A single UniBoard can process a 64MHz band from 32 stations, 2 polarizations, sampled at 8 bit. Adding more UniBoards can expand the total bandwidth of the correlator. The design is able to process both prerecorded and real time (eVLBI) data.

Nonuniformity correction algorithm with efficient pixel offset estimation for infrared focal plane arrays.

PubMed

Orżanowski, Tomasz

2016-01-01

This paper presents an infrared focal plane array (IRFPA) response nonuniformity correction (NUC) algorithm which is easy to implement by hardware. The proposed NUC algorithm is based on the linear correction scheme with the useful method of pixel offset correction coefficients update. The new approach to IRFPA response nonuniformity correction consists in the use of pixel response change determined at the actual operating conditions in relation to the reference ones by means of shutter to compensate a pixel offset temporal drift. Moreover, it permits to remove any optics shading effect in the output image as well. To show efficiency of the proposed NUC algorithm some test results for microbolometer IRFPA are presented.

Targeting multiple heterogeneous hardware platforms with OpenCL

NASA Astrophysics Data System (ADS)

Fox, Paul A.; Kozacik, Stephen T.; Humphrey, John R.; Paolini, Aaron; Kuller, Aryeh; Kelmelis, Eric J.

2014-06-01

The OpenCL API allows for the abstract expression of parallel, heterogeneous computing, but hardware implementations have substantial implementation differences. The abstractions provided by the OpenCL API are often insufficiently high-level to conceal differences in hardware architecture. Additionally, implementations often do not take advantage of potential performance gains from certain features due to hardware limitations and other factors. These factors make it challenging to produce code that is portable in practice, resulting in much OpenCL code being duplicated for each hardware platform being targeted. This duplication of effort offsets the principal advantage of OpenCL: portability. The use of certain coding practices can mitigate this problem, allowing a common code base to be adapted to perform well across a wide range of hardware platforms. To this end, we explore some general practices for producing performant code that are effective across platforms. Additionally, we explore some ways of modularizing code to enable optional optimizations that take advantage of hardware-specific characteristics. The minimum requirement for portability implies avoiding the use of OpenCL features that are optional, not widely implemented, poorly implemented, or missing in major implementations. Exposing multiple levels of parallelism allows hardware to take advantage of the types of parallelism it supports, from the task level down to explicit vector operations. Static optimizations and branch elimination in device code help the platform compiler to effectively optimize programs. Modularization of some code is important to allow operations to be chosen for performance on target hardware. Optional subroutines exploiting explicit memory locality allow for different memory hierarchies to be exploited for maximum performance. The C preprocessor and JIT compilation using the OpenCL runtime can be used to enable some of these techniques, as well as to factor in hardware

Power Efficient Hardware Architecture of SHA-1 Algorithm for Trusted Mobile Computing

NASA Astrophysics Data System (ADS)

Kim, Mooseop; Ryou, Jaecheol

The Trusted Mobile Platform (TMP) is developed and promoted by the Trusted Computing Group (TCG), which is an industry standard body to enhance the security of the mobile computing environment. The built-in SHA-1 engine in TMP is one of the most important circuit blocks and contributes the performance of the whole platform because it is used as key primitives supporting platform integrity and command authentication. Mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for low power SHA-1 circuit are required. In this paper, we present a novel and efficient hardware architecture of low power SHA-1 design for TMP. Our low power SHA-1 hardware can compute 512-bit data block using less than 7,000 gates and has a power consumption about 1.1 mA on a 0.25μm CMOS process.

DESIGN OF TWO-DIMENSIONAL SUPERSONIC TURBINE ROTOR BLADES WITH BOUNDARY-LAYER CORRECTION

NASA Technical Reports Server (NTRS)

Goldman, L. J.

1994-01-01

A computer program has been developed for the design of supersonic rotor blades where losses are accounted for by correcting the ideal blade geometry for boundary layer displacement thickness. The ideal blade passage is designed by the method of characteristics and is based on establishing vortex flow within the passage. Boundary-layer parameters (displacement and momentum thicknesses) are calculated for the ideal passage, and the final blade geometry is obtained by adding the displacement thicknesses to the ideal nozzle coordinates. The boundary-layer parameters are also used to calculate the aftermixing conditions downstream of the rotor blades assuming the flow mixes to a uniform state. The computer program input consists essentially of the rotor inlet and outlet Mach numbers, upper- and lower-surface Mach numbers, inlet flow angle, specific heat ratio, and total flow conditions. The program gas properties are set up for air. Additional gases require changes to be made to the program. The computer output consists of the corrected rotor blade coordinates, the principal boundary-layer parameters, and the aftermixing conditions. This program is written in FORTRAN IV for batch execution and has been implemented on an IBM 7094. This program was developed in 1971.

First Light with the NRAO Transient Event Capture Hardware

NASA Astrophysics Data System (ADS)

Langston, Glen; Rumberg, B.; Brandt, P.

2007-12-01

The design, implementation and testing of the first NRAO Event Capture data acquisition system is presented. The NRAO in Green Bank is developing a set of new data acquisition systems based on the U.C. Berkeley CASPER IBOB/ADC/BEE2 hardware. We describe the hardware configuration and initial experiences with the development system. We present first astronomical tests of the Event Capture system, using the 43m telescope (140ft). These observations were carried out at 900 MHz. The observations were made on 2007 July 8 and 9 towards the Crab pulsar, the galactic center, the Moon and two test observations while the 43m was pointed at Zenith (straight up). The Event Capture is one of several on-going FPGA based data acquisition projects being implemented for the Robert C. Byrd Green Bank Telescope (GBT) and for the 43m telescopes. The NRAO Configurable Instrument Collaboration for Agile Data Acquisition (CICADA) program is described at: http://wikio.nrao.edu/bin/view/CICADA

INTEGRATED MONITORING HARDWARE DEVELOPMENTS AT LOS ALAMOS

DOE Office of Scientific and Technical Information (OSTI.GOV)

R. PARKER; J. HALBIG; ET AL

1999-09-01

The hardware of the integrated monitoring system supports a family of instruments having a common internal architecture and firmware. Instruments can be easily configured from application-specific personality boards combined with common master-processor and high- and low-voltage power supply boards, and basic operating firmware. The instruments are designed to function autonomously to survive power and communication outages and to adapt to changing conditions. The personality boards allow measurement of gross gammas and neutrons, neutron coincidence and multiplicity, and gamma spectra. In addition, the Intelligent Local Node (ILON) provides a moderate-bandwidth network to tie together instruments, sensors, and computers.

Analysis of systems hardware flown on LDEF: New findings and comparison to other retrieved spacecraft hardware

NASA Astrophysics Data System (ADS)

Dursch, Harry; Bohnhoff-Hlavacek, Gail; Blue, Donald; Hansen, Patricia

1995-09-01

The Long Duration Exposure Facility (LDEF) was retrieved in 1990 after spending 69 months in low-earth-orbit (LEO). A wide variety of mechanical, electrical, thermal, and optical systems, subsystems, and components were flown on LDEF. The Systems Special Investigation Group (Systems SIG) was formed by NASA to investigate the effects of the 69 month exposure on systems related hardware and to coordinate and collate all systems analysis of LDEF hardware. This report is the Systems SIG final report which updates earlier findings and compares LDEF systems findings to results from other retrieved spacecraft hardware such as Hubble Space Telescope. Also included are sections titled (1) Effects of Long Duration Space Exposure on Optical Scatter, (2) Contamination Survey of LDEF, and (3) Degradation of Optical Materials in Space.

Analysis of systems hardware flown on LDEF: New findings and comparison to other retrieved spacecraft hardware

NASA Technical Reports Server (NTRS)

Dursch, Harry; Bohnhoff-Hlavacek, Gail; Blue, Donald; Hansen, Patricia

1995-01-01

The Long Duration Exposure Facility (LDEF) was retrieved in 1990 after spending 69 months in low-earth-orbit (LEO). A wide variety of mechanical, electrical, thermal, and optical systems, subsystems, and components were flown on LDEF. The Systems Special Investigation Group (Systems SIG) was formed by NASA to investigate the effects of the 69 month exposure on systems related hardware and to coordinate and collate all systems analysis of LDEF hardware. This report is the Systems SIG final report which updates earlier findings and compares LDEF systems findings to results from other retrieved spacecraft hardware such as Hubble Space Telescope. Also included are sections titled (1) Effects of Long Duration Space Exposure on Optical Scatter, (2) Contamination Survey of LDEF, and (3) Degradation of Optical Materials in Space.

Growth in spaceflight hardware results in alterations to the transcriptome and proteome.

PubMed

Basu, Proma; Kruse, Colin P S; Luesse, Darron R; Wyatt, Sarah E

2017-11-01

The Biological Research in Canisters (BRIC) hardware has been used to house many biology experiments on both the Space Transport System (STS, commonly known as the space shuttle) and the International Space Station (ISS). However, microscopic examination of Arabidopsis seedlings by Johnson et al. (2015) indicated the hardware itself may affect cell morphology. The experiment herein was designed to assess the effects of the BRIC-Petri Dish Fixation Units (BRIC-PDFU) hardware on the transcriptome and proteome of Arabidopsis seedlings. To our knowledge, this is the first transcriptomic and proteomic comparison of Arabidopsis seedlings grown with and without hardware. Arabidopsis thaliana wild-type Columbia (Col-0) seeds were sterilized and bulk plated on forty-four 60 mm Petri plates, of which 22 were integrated into the BRIC-PDFU hardware and 22 were maintained in closed containers at Ohio University. Seedlings were grown for approximately 3 days, fixed with RNAlater ® and stored at -80 °C prior to RNA and protein extraction, with proteins separated into membrane and soluble fractions prior to analysis. The RNAseq analysis identified 1651 differentially expressed genes; MS/MS analysis identified 598 soluble and 589 membrane proteins differentially abundant both at p < .05. Fold enrichment analysis of gene ontology terms related to differentially expressed transcripts and proteins highlighted a variety of stress responses. Some of these genes and proteins have been previously identified in spaceflight experiments, indicating that these genes and proteins may be perturbed by both conditions. Copyright © 2017 The Committee on Space Research (COSPAR). Published by Elsevier Ltd. All rights reserved.

CHeCS: International Space Station Medical Hardware Catalog

NASA Technical Reports Server (NTRS)

2008-01-01

The purpose of this catalog is to provide a detailed description of each piece of hardware in the Crew Health Care System (CHeCS), including subpacks associated with the hardware, and to briefly describe the interfaces between the hardware and the ISS. The primary user of this document is the Space Medicine/Medical Operations ISS Biomedical Flight Controllers (ISS BMEs).

Issues Related to Large Flight Hardware Acoustic Qualification Testing

NASA Technical Reports Server (NTRS)

Kolaini, Ali R.; Perry, Douglas C.; Kern, Dennis L.

2011-01-01

The characteristics of acoustical testing volumes generated by reverberant chambers or a circle of loudspeakers with and without large flight hardware within the testing volume are significantly different. The parameters attributing to these differences are normally not accounted for through analysis or acoustic tests prior to the qualification testing without the test hardware present. In most cases the control microphones are kept at least 2-ft away from hardware surfaces, chamber walls, and speaker surfaces to minimize the impact of the hardware in controlling the sound field. However, the acoustic absorption and radiation of sound by hardware surfaces may significantly alter the sound pressure field controlled within the chamber/speaker volume to a given specification. These parameters often result in an acoustic field that may provide under/over testing scenarios for flight hardware. In this paper the acoustic absorption by hardware surfaces will be discussed in some detail. A simple model is provided to account for some of the observations made from Mars Science Laboratory spacecraft that recently underwent acoustic qualification tests in a reverberant chamber.

Bias Corrections for Standardized Effect Size Estimates Used with Single-Subject Experimental Designs

ERIC Educational Resources Information Center

Ugille, Maaike; Moeyaert, Mariola; Beretvas, S. Natasha; Ferron, John M.; Van den Noortgate, Wim

2014-01-01

A multilevel meta-analysis can combine the results of several single-subject experimental design studies. However, the estimated effects are biased if the effect sizes are standardized and the number of measurement occasions is small. In this study, the authors investigated 4 approaches to correct for this bias. First, the standardized effect…

Using Innovative Technologies for Manufacturing and Evaluating Rocket Engine Hardware

NASA Technical Reports Server (NTRS)

Betts, Erin M.; Hardin, Andy

2011-01-01

Many of the manufacturing and evaluation techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As we enter into a new space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt new and innovative techniques for manufacturing and evaluating hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, manufacturing techniques such as Direct Metal Laser Sintering (DMLS) and white light scanning are being adopted and evaluated for their use on J-2X, with hopes of employing both technologies on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powdered metal manufacturing process in order to produce complex part geometries. The white light technique is a non-invasive method that can be used to inspect for geometric feature alignment. Both the DMLS manufacturing method and the white light scanning technique have proven to be viable options for manufacturing and evaluating rocket engine hardware, and further development and use of these techniques is recommended.

Development of inspection techniques for quantitatively measuring surface contamination on SRM hardware

NASA Technical Reports Server (NTRS)

Law, R. D.

1989-01-01

A contaminant is any material or substance which is potentially undesirable or which may adversely affect any part, component, or assembly. Contamination control of SRM hardware surfaces is a serious concern, for both Thiokol and NASA, with particular concern for contaminants which may adversely affect bonding surfaces. The purpose of this study is to develop laboratory analytical techniques which will make it possible to certify the cleanliness of any designated surface, with special focus on particulates (dust, dirt, lint, etc.), oils (hydrocarbons, silicones, plasticizers, etc.), and greases (HD-2, fluorocarbon grease, etc.). The hardware surfaces of concern will include D6AC steel, aluminum alloys, anodized aluminum alloys, glass/phenolic, carbon/phenolic, NBR/asbestos-silica, and EPDM rubber.

Reducing NPR 7120.5D to Practice: Transitioning from Design Reviews to the SIR Hardware Review

NASA Technical Reports Server (NTRS)

Taylor, Randall

2011-01-01

The Gravity Recovery And Interior Laboratory (GRAIL) mission was the first Jet Propulsion Laboratory (JPL) project initiated under NASA's revised rules for space flight project management, NPR 7120.5D, "NASA Space Flight Program and Project Management Requirements." NASA selected GRAIL through a competitive Announcement of Opportunity process and funded its Phase B Preliminary Design effort. The team's first major milestone was a JPL institutional milestone, the Project Mission System Review (PMSR), which proved an excellent tune-up for the end-of-Phase-B NASA life-cycle review, the Preliminary Design Review (PDR). Building on JPL experience on the Prometheus and Juno projects, the team successfully organized for and conducted these reviews on an aggressive schedule. For the Project Critical Design Review (CDR), lessons learned from the PDR and updated Standing Review Board (SRB) practices from the Agency were factored into the review preparation effort. Additionally, the review was held at the Principal Investigator's institution, the Massachusetts Institute of Technology, rather than at the project management center (JPL), which necessitated additional cross-country coordination steps. The PMSR, PDR, and CDR were design reviews and largely paper-oriented. For the System Integration Review (SIR), the project needed to transition to a hardware review and deal with paper in a very different manner. While many of the practices employed for the design reviews were modified and retained (e.g., review preparation team, gate products management, pre-reviews, SRB coordination), the review agenda, presentation style, and slide templates were significantly changed. A key success factor concerned the handling of project open paper, which was succinctly and effectively communicated to the SRB in presentations.This paper provides a brief overview of the GRAIL mission and its project management challenges, provides a detailed description of project SIR preparation and execution

Using Innovative Techniques for Manufacturing Rocket Engine Hardware

NASA Technical Reports Server (NTRS)

Betts, Erin M.; Reynolds, David C.; Eddleman, David E.; Hardin, Andy

2011-01-01

Many of the manufacturing techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As we enter into a new space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt new and innovative techniques for manufacturing hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, manufacturing techniques such as Direct Metal Laser Sintering (DMLS) are being adopted and evaluated for their use on J-2X, with hopes of employing this technology on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powder metal manufacturing process in order to produce complex part geometries. Marshall Space Flight Center (MSFC) has recently hot-fire tested a J-2X gas generator discharge duct that was manufactured using DMLS. The duct was inspected and proof tested prior to the hot-fire test. Using the Workhorse Gas Generator (WHGG) test setup at MSFC?s East Test Area test stand 116, the duct was subject to extreme J-2X gas generator environments and endured a total of 538 seconds of hot-fire time. The duct survived the testing and was inspected after the test. DMLS manufacturing has proven to be a viable option for manufacturing rocket engine hardware, and further development and use of this manufacturing method is recommended.

OpenMM 4: A Reusable, Extensible, Hardware Independent Library for High Performance Molecular Simulation

PubMed Central

Eastman, Peter; Friedrichs, Mark S.; Chodera, John D.; Radmer, Randall J.; Bruns, Christopher M.; Ku, Joy P.; Beauchamp, Kyle A.; Lane, Thomas J.; Wang, Lee-Ping; Shukla, Diwakar; Tye, Tony; Houston, Mike; Stich, Timo; Klein, Christoph; Shirts, Michael R.; Pande, Vijay S.

2012-01-01

OpenMM is a software toolkit for performing molecular simulations on a range of high performance computing architectures. It is based on a layered architecture: the lower layers function as a reusable library that can be invoked by any application, while the upper layers form a complete environment for running molecular simulations. The library API hides all hardware-specific dependencies and optimizations from the users and developers of simulation programs: they can be run without modification on any hardware on which the API has been implemented. The current implementations of OpenMM include support for graphics processing units using the OpenCL and CUDA frameworks. In addition, OpenMM was designed to be extensible, so new hardware architectures can be accommodated and new functionality (e.g., energy terms and integrators) can be easily added. PMID:23316124

Hardware Prototyping of Neural Network based Fetal Electrocardiogram Extraction

NASA Astrophysics Data System (ADS)

Hasan, M. A.; Reaz, M. B. I.

2012-01-01

The aim of this paper is to model the algorithm for Fetal ECG (FECG) extraction from composite abdominal ECG (AECG) using VHDL (Very High Speed Integrated Circuit Hardware Description Language) for FPGA (Field Programmable Gate Array) implementation. Artificial Neural Network that provides efficient and effective ways of separating FECG signal from composite AECG signal has been designed. The proposed method gives an accuracy of 93.7% for R-peak detection in FHR monitoring. The designed VHDL model is synthesized and fitted into Altera's Stratix II EP2S15F484C3 using the Quartus II version 8.0 Web Edition for FPGA implementation.

Efficient color correction method for smartphone camera-based health monitoring application.

PubMed

Duc Dang; Chae Ho Cho; Daeik Kim; Oh Seok Kwon; Jo Woon Chong

2017-07-01

Smartphone health monitoring applications are recently highlighted due to the rapid development of hardware and software performance of smartphones. However, color characteristics of images captured by different smartphone models are dissimilar each other and this difference may give non-identical health monitoring results when the smartphone health monitoring applications monitor physiological information using their embedded smartphone cameras. In this paper, we investigate the differences in color properties of the captured images from different smartphone models and apply a color correction method to adjust dissimilar color values obtained from different smartphone cameras. Experimental results show that the color corrected images using the correction method provide much smaller color intensity errors compared to the images without correction. These results can be applied to enhance the consistency of smartphone camera-based health monitoring applications by reducing color intensity errors among the images obtained from different smartphones.

Ground station hardware for the ATS-F millimeter wave experiment

NASA Technical Reports Server (NTRS)

Duffield, T. L.

1973-01-01

The results are presented of a program to design, fabricate, test, and install a primary ATS-F millimeter wave ground receiving station. Propagation parameters at millimeter waves are discussed along with the objective of the overall experiment. A general description is given of the receiving system and its function in the experiment. Typical receiver characteristics are presented which show that the experiment is entirely feasible from a link SNR standpoint. The receiving system hardware designs are discussed with separate treatment given to the propagation and the radiometer receiver designs. The modification and relocation are described of an existing 15-ft antenna to meet the ATS-F requirements. The design of a dual frequency feed subsystem and self calibration equipment is included.

Development of hardwares and computer interface for a two-degree-of-freedom robot

NASA Technical Reports Server (NTRS)

Nguyen, Charles C.; Pooran, Farhad J.

1987-01-01

The research results that were obtained are reviewed. Then the robot actuator, the selection of the data acquisition system, and the design of the power amplifier will be discussed. The machine design of the robot manipulator will then be presented. After that, the integration of the developed hardware into the open-loop system will also be discussed. Current and future research work is addressed.

Contamination Control and Hardware Processing Solutions at Marshall Space Flight Center

NASA Technical Reports Server (NTRS)

Burns, DeWitt H.; Hampton, Tammy; Huey, LaQuieta; Mitchell, Mark; Norwood, Joey; Lowrey, Nikki

2012-01-01

The Contamination Control Team of Marshall Space Flight Center's Materials and Processes Laboratory supports many Programs/ Projects that design, manufacture, and test a wide range of hardware types that are sensitive to contamination and foreign object damage (FOD). Examples where contamination/FOD concerns arise include sensitive structural bondline failure, critical orifice blockage, seal leakage, and reactive fluid compatibility (liquid oxygen, hydrazine) as well as performance degradation of sensitive instruments or spacecraft surfaces such as optical elements and thermal control systems. During the design phase, determination of the sensitivity of a hardware system to different types or levels of contamination/FOD is essential. A contamination control and FOD control plan must then be developed and implemented through all phases of ground processing, and, sometimes, on-orbit use, recovery, and refurbishment. Implementation of proper controls prevents cost and schedule impacts due to hardware damage or rework and helps assure mission success. Current capabilities are being used to support recent and on-going activities for multiple Mission Directorates / Programs such as International Space Station (ISS), James Webb Space Telescope (JWST), Space Launch System (SLS) elements (tanks, engines, booster), etc. The team also advances Green Technology initiatives and addresses materials obsolescence issues for NASA and external customers, most notably in the area of solvent replacement (e.g. aqueous cleaners containing hexavalent chrome, ozone depleting chemicals (CFC s and HCFC's), suspect carcinogens). The team evaluates new surface cleanliness inspection and cleaning technologies (e.g. plasma cleaning), and maintains databases for processing support materials as well as outgassing and optical compatibility test results for spaceflight environments.

Hardware Implementation of a MIMO Decoder Using Matrix Factorization Based Channel Estimation

NASA Astrophysics Data System (ADS)

Islam, Mohammad Tariqul; Numan, Mostafa Wasiuddin; Misran, Norbahiah; Ali, Mohd Alauddin Mohd; Singh, Mandeep

2011-05-01

This paper presents an efficient hardware realization of multiple-input multiple-output (MIMO) wireless communication decoder that utilizes the available resources by adopting the technique of parallelism. The hardware is designed and implemented on Xilinx Virtex™-4 XC4VLX60 field programmable gate arrays (FPGA) device in a modular approach which simplifies and eases hardware update, and facilitates testing of the various modules independently. The decoder involves a proficient channel estimation module that employs matrix factorization on least squares (LS) estimation to reduce a full rank matrix into a simpler form in order to eliminate matrix inversion. This results in performance improvement and complexity reduction of the MIMO system. Performance evaluation of the proposed method is validated through MATLAB simulations which indicate 2 dB improvement in terms of SNR compared to LS estimation. Moreover complexity comparison is performed in terms of mathematical operations, which shows that the proposed approach appreciably outperforms LS estimation at a lower complexity and represents a good solution for channel estimation technique.

77 FR 16661 - Tuberculosis in Cattle and Bison; State and Zone Designations; NM; Correction

Federal Register 2010, 2011, 2012, 2013, 2014

2012-03-22

...-0124] Tuberculosis in Cattle and Bison; State and Zone Designations; NM; Correction AGENCY: Animal and... in the regulatory text of an interim rule that amended the bovine tuberculosis regulations by establishing two separate zones with different tuberculosis risk classifications for the State of New Mexico...

An Environment for Hardware-in-the-Loop Formation Navigation and Control Simulation

NASA Technical Reports Server (NTRS)

Burns, Rich

2004-01-01

Recent interest in formation flying satellite systems has spurred a considerable amount of research in the relative navigation and control of satellites. Development in this area has included new estimation and control algorithms as well as sensor and actuator development specifically geared toward the relative control problem. This paper describes a simulation facility, the Formation Flying Testbed (FFTB) at NASA's Goddard Space Flight Center, which allows engineers to test new algorithms for the formation flying problem with relevant GN&C hardware in a closed loop simulation. The FFTB currently supports the injection of GPS receiver hardware into the simulation loop, and support for satellite crosslink ranging technology is at a prototype stage. This closed-loop, hardware inclusive simulation capability permits testing of navigation and control software in the presence of the actual hardware with which the algorithms must interact. This capability provides the navigation or control developer with a perspective on how the algorithms perform as part of the closed-loop system. In this paper, the overall design and evolution of the FFTB are presented. Each component of the FFTB is then described in detail. Interfaces between the components of the FFTB are shown and the interfaces to and between navigation and control software are described in detail. Finally, an example of closed-loop formation control with GPS receivers in the loop is presented and results are analyzed.

Movable Ground Based Recovery System for Reuseable Space Flight Hardware

NASA Technical Reports Server (NTRS)

Sarver, George L. (Inventor)

2013-01-01

A reusable space flight launch system is configured to eliminate complex descent and landing systems from the space flight hardware and move them to maneuverable ground based systems. Precision landing of the reusable space flight hardware is enabled using a simple, light weight aerodynamic device on board the flight hardware such as a parachute, and one or more translating ground based vehicles such as a hovercraft that include active speed, orientation and directional control. The ground based vehicle maneuvers itself into position beneath the descending flight hardware, matching its speed and direction and captures the flight hardware. The ground based vehicle will contain propulsion, command and GN&C functionality as well as space flight hardware landing cushioning and retaining hardware. The ground based vehicle propulsion system enables longitudinal and transverse maneuverability independent of its physical heading.

Space biology initiative program definition review. Trade study 5: Modification of existing hardware (COTS) versus new hardware build cost analysis

NASA Technical Reports Server (NTRS)

Jackson, L. Neal; Crenshaw, John, Sr.; Davidson, William L.; Blacknall, Carolyn; Bilodeau, James W.; Stoval, J. Michael; Sutton, Terry

1989-01-01

The JSC Life Sciences Project Division has been directly supporting NASA Headquarters, Life Sciences Division, in the preparation of data from JSC and ARC to assist in defining the Space Biology Initiative (SBI). GE Government Services and Horizon Aerospace have provided contract support for the development and integration of review data, reports, presentations, and detailed supporting data. An SBI Definition (Non-Advocate) Review at NASA Headquarters, Code B, has been scheduled for the June-July 1989 time period. In a previous NASA Headquarters review, NASA determined that additional supporting data would be beneficial to determine the potential advantages in modifying commercial off-the-shelf (COTS) hardware for some SBI hardware items. In order to meet the demands of program implementation planning with the definition review in late spring of 1989, the definition trade study analysis must be adjusted in scope and schedule to be complete for the SBI Definition (Non-Advocate) Review. The relative costs of modifying existing commercial off-the-shelf (COTS) hardware is compared to fabricating new hardware. An historical basis for new build versus modifying COTS to meet current NMI specifications for manned space flight hardware is surveyed and identified. Selected SBI hardware are identified as potential candidates for off-the-shelf modification and statistical estimates on the relative cost of modifying COTS versus new build are provided.

Hierarchical image-based rendering using texture mapping hardware

DOE Office of Scientific and Technical Information (OSTI.GOV)

Max, N

1999-01-15

Multi-layered depth images containing color and normal information for subobjects in a hierarchical scene model are precomputed with standard z-buffer hardware for six orthogonal views. These are adaptively selected according to the proximity of the viewpoint, and combined using hardware texture mapping to create ''reprojected'' output images for new viewpoints. (If a subobject is too close to the viewpoint, the polygons in the original model are rendered.) Specific z-ranges are selected from the textures with the hardware alpha test to give accurate 3D reprojection. The OpenGL color matrix is used to transform the precomputed normals into their orientations in themore » final view, for hardware shading.« less

Toward Evolvable Hardware Chips: Experiments with a Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Stoica, Adrian

1998-01-01

Evolvable Hardware is reconfigurable hardware that self-configures under the control of an evolutionary algorithm. We search for a hardware configuration can be performed using software models or, faster and more accurate, directly in reconfigurable hardware. Several experiments have demonstrated the possibility to automatically synthesize both digital and analog circuits. The paper introduces an approach to automated synthesis of CMOS circuits, based on evolution on a Programmable Transistor Array (PTA). The approach is illustrated with a software experiment showing evolutionary synthesis of a circuit with a desired DC characteristic. A hardware implementation of a test PTA chip is then described, and the same evolutionary experiment is performed on the chip demonstrating circuit synthesis/self-configuration directly in hardware.

Design for Assured Safe Jettison Operations

NASA Astrophysics Data System (ADS)

Herd, Andrew; Shea, Matt

2010-09-01

The International Space Station is coming toward the end of the assembly process and will enter "steady state" operations. During this time and also in the future, there arises the need for removing items from station, and in some instances this is achieved through jettison, either robotic or crew initiated. To control this practice at the ISS Partner level, a policy document has been developed. The policy states: "While there are risks inherent in jettisoning objects, the ISS Program recognizes that there may be significant benefits in terms of operational flexibility, crew safety, etc. A thorough assessment of the risks vs. the benefits will be conducted whenever a proposal to jettison an object is made. It is the intent of the ISS Program to limit the number of objects that are jettisoned from the ISS ...". The policy addresses hardware that: "may fall into one or more of the following categories: 1. Items that pose a safety issue for the ISS or for return onboard a visiting vehicle(contamination, materials degradation, etc.) 2. Items that negatively impact ISS utilization, return or on-orbit stowage manifests 3. Items that represent an Extravehicular Activity(EVA) timeline savings large enough to reduce the sum of the risks of EVA exposure time and the orbital environment’s hazardous debris population, compared to the sum of such risks without a jettison. 4. Items that are designed for jettison ". [1] Through the use of jettison to date, as a disposal means, operational experiences have been gained during and as a result of post-disposal event analysis. The data collected has allowed a generic assessment of issues(and best practices) and the proposal of ways in which process corrective action can be taken to assure future safe jettison operations. The improvements proposed emphasize the ways in which design can offer key interface and hardware response characteristics to the jettison event and the subsequent orbital and re-entry profile. There exist simple

Estimating the cost of major ongoing cost plus hardware development programs

NASA Technical Reports Server (NTRS)

Bush, J. C.

1990-01-01

Approaches are developed for forecasting the cost of major hardware development programs while these programs are in the design and development C/D phase. Three approaches are developed: a schedule assessment technique for bottom-line summary cost estimation, a detailed cost estimation approach, and an intermediate cost element analysis procedure. The schedule assessment technique was developed using historical cost/schedule performance data.

Danny Weber, a student experimenter, discusses experiment hardware for STS-7

NASA Technical Reports Server (NTRS)

1983-01-01

Danny Weber, a student from Cornell University, discusses the hardware for an experiment he devised, with Astronaut Norman E. Thagard, STS-7 mission specialist. The experiment is entitled 'Effect of weightlessness on arthritis'. The cage and monitoring equipment shown are designed to use rats as the subjects for the study. Weber was attending Hunter College High School when he submitted the experiment.

Tinker's Toys: Lessons from Bank Street: Hardware.

ERIC Educational Resources Information Center

Tinker, Robert

1985-01-01

Bank Street Laboratory (a set of hardware/software tools for measuring temperature, light, and sound) consists of a board that plugs into Apple microcomputers, cabling, software, and six probes. Discusses the laboratory's hardware, including the analog-to-digital converter, multiplier chip, and modular connectors. Circuit diagrams of components…

Generalized algebraic scene-based nonuniformity correction algorithm.

PubMed

Ratliff, Bradley M; Hayat, Majeed M; Tyo, J Scott

2005-02-01

A generalization of a recently developed algebraic scene-based nonuniformity correction algorithm for focal plane array (FPA) sensors is presented. The new technique uses pairs of image frames exhibiting arbitrary one- or two-dimensional translational motion to compute compensator quantities that are then used to remove nonuniformity in the bias of the FPA response. Unlike its predecessor, the generalization does not require the use of either a blackbody calibration target or a shutter. The algorithm has a low computational overhead, lending itself to real-time hardware implementation. The high-quality correction ability of this technique is demonstrated through application to real IR data from both cooled and uncooled infrared FPAs. A theoretical and experimental error analysis is performed to study the accuracy of the bias compensator estimates in the presence of two main sources of error.

Hardware device to physical structure binding and authentication

DOEpatents

Hamlet, Jason R.; Stein, David J.; Bauer, Todd M.

2013-08-20

Detection and deterrence of device tampering and subversion may be achieved by including a cryptographic fingerprint unit within a hardware device for authenticating a binding of the hardware device and a physical structure. The cryptographic fingerprint unit includes an internal physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generate an internal PUF value. Binding logic is coupled to receive the internal PUF value, as well as an external PUF value associated with the physical structure, and generates a binding PUF value, which represents the binding of the hardware device and the physical structure. The cryptographic fingerprint unit also includes a cryptographic unit that uses the binding PUF value to allow a challenger to authenticate the binding.

NASA Hardware Heads to Kennedy For Flight Preparations

NASA Image and Video Library

2018-01-24

The Orion stage adapter will be part of the first integrated flight of NASA's heavy-lift rocket, the Space Launch System, and the Orion spacecraft. The adapter, approximately 5 feet tall and 18 feet in diameter, was designed and built at NASA's Marshall Space Flight Center in Huntsville, Alabama, with advanced friction stir welding technology. It will connect the SLS interim cryogenic propulsion stage to Orion on the first flight that will help engineers check out and verify the agency's new deep-space exploration systems. Inside the adapter, engineers installed special brackets and cabling for the 13 CubeSats that will fly as secondary payloads. The Cubesats are boot-box-sized science and technology investigations that will help pave the way for future human exploration in deep space. The Orion stage adapter flight article recently finished major testing of the avionics system that will deploy the CubeSats. Technicians at NASA's Kennedy Space Center, Florida, will install the secondary payloads and engineers will examine the hardware before it is stacked on the interim cryogenic propulsion stage in the Vehicle Assembly Building prior to launch. For more information about SLS hardware, visit nasa.gov/sls.

Visualizing the Future of Research on Post Secondary Correctional Education: Designs, Data, and Deliverables

ERIC Educational Resources Information Center

Wheeldon, J.

2011-01-01

Providing post-secondary education in correctional settings has emerged as one of the best ways to reduce recidivism, save taxpayer dollars, and promote post release employment and community reintegration. While a number of studies exist, this paper argues persistent challenges connected to research design, data collection, and the communication…

Using Innovative Technologies for Manufacturing Rocket Engine Hardware

NASA Technical Reports Server (NTRS)

Betts, E. M.; Eddleman, D. E.; Reynolds, D. C.; Hardin, N. A.

2011-01-01

Many of the manufacturing techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As the United States enters into the next space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt innovative techniques for manufacturing hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, rapid manufacturing techniques such as Direct Metal Laser Sintering (DMLS) are being adopted and evaluated for their use on NASA s Space Launch System (SLS) upper stage engine, J-2X, with hopes of employing this technology on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powder metal manufacturing process in order to produce complex part geometries. Marshall Space Flight Center (MSFC) has recently hot-fire tested a J-2X gas generator (GG) discharge duct that was manufactured using DMLS. The duct was inspected and proof tested prior to the hot-fire test. Using a workhorse gas generator (WHGG) test fixture at MSFC's East Test Area, the duct was subjected to extreme J-2X hot gas environments during 7 tests for a total of 537 seconds of hot-fire time. The duct underwent extensive post-test evaluation and showed no signs of degradation. DMLS manufacturing has proven to be a viable option for manufacturing rocket engine hardware, and further development and use of this manufacturing method is recommended.

Fast automatic correction of motion artifacts in shoulder MRI

NASA Astrophysics Data System (ADS)

Manduca, Armando; McGee, Kiaran P.; Welch, Edward B.; Felmlee, Joel P.; Ehman, Richard L.

2001-07-01

The ability to correct certain types of MR images for motion artifacts from the raw data alone by iterative optimization of an image quality measure has recently been demonstrated. In the first study on a large data set of clinical images, we showed that such an autocorrection technique significantly improved the quality of clinical rotator cuff images, and performed almost as well as navigator echo correction while never degrading an image. One major criticism of such techniques is that they are computationally intensive, and reports of the processing time required have ranged form a few minutes to tens of minutes per slice. In this paper we describe a variety of improvements to our algorithm as well as approaches to correct sets of adjacent slices efficiently. The resulting algorithm is able to correct 256x256x20 clinical shoulder data sets for motion at an effective rate of 1 second/image on a standard commercial workstation. Future improvements in processor speeds and/or the use of specialized hardware will translate directly to corresponding reductions in this calculation time.

A Survey of Display Hardware and Software.

ERIC Educational Resources Information Center

Poore, Jesse H., Jr.; And Others

Reported are two papers which deal with the fundamentals of display hardware and software in computer systems. The first report presents the basic principles of display hardware in terms of image generation from buffers presumed to be loaded and controlled by a digital computer. The concepts surrounding the electrostatic tube, the electromagnetic…

An environmental testing facility for Space Station Freedom power management and distribution hardware

NASA Technical Reports Server (NTRS)

Jackola, Arthur S.; Hartjen, Gary L.

1992-01-01

The plans for a new test facility, including new environmental test systems, which are presently under construction, and the major environmental Test Support Equipment (TSE) used therein are addressed. This all-new Rocketdyne facility will perform space simulation environmental tests on Power Management and Distribution (PMAD) hardware to Space Station Freedom (SSF) at the Engineering Model, Qualification Model, and Flight Model levels of fidelity. Testing will include Random Vibration in three axes - Thermal Vacuum, Thermal Cycling and Thermal Burn-in - as well as numerous electrical functional tests. The facility is designed to support a relatively high throughput of hardware under test, while maintaining the high standards required for a man-rated space program.

Ka-Band Wide-Bandgap Solid-State Power Amplifier: Hardware Validation

NASA Technical Reports Server (NTRS)

Epp, L.; Khan, P.; Silva, A.

2005-01-01

Motivated by recent advances in wide-bandgap (WBG) gallium nitride (GaN) semiconductor technology, there is considerable interest in developing efficient solid-state power amplifiers (SSPAs) as an alternative to the traveling-wave tube amplifier (TWTA) for space applications. This article documents proof-of-concept hardware used to validate power-combining technologies that may enable a 120-W, 40 percent power-added efficiency (PAE) SSPA. Results in previous articles [1-3] indicate that architectures based on at least three power combiner designs are likely to enable the target SSPA. Previous architecture performance analyses and estimates indicate that the proposed architectures can power combine 16 to 32 individual monolithic microwave integrated circuits (MMICs) with >80 percent combining efficiency. This combining efficiency would correspond to MMIC requirements of 5- to 10-W output power and >48 percent PAE. In order to validate the performance estimates of the three proposed architectures, measurements of proof-of-concept hardware are reported here.

Designing Secure Systems on Reconfigurable Hardware

DTIC Science & Technology

2008-07-01

Jeff White Department of Electrical and Computer Engineering University of California, Santa Barbara Santa Barbara, CA 93106 {nick callegari,valamehr...ece.ucsb.edu, jdwhite08@engineering.ucsb.edu Ryan Kastner Department of Computer Science and Engineering University of California, San Diego La Jolla...Transactions on Design Automation of Electronic Systems (TODAES), Vol. 13, No. 3, July 2008, 1-24 14. ABSTRACT see report 15. SUBJECT TERMS 16

Applications of Modeling and Simulation for Flight Hardware Processing at Kennedy Space Center

NASA Technical Reports Server (NTRS)

Marshall, Jennifer L.

2010-01-01

The Boeing Design Visualization Group (DVG) is responsible for the creation of highly-detailed representations of both on-site facilities and flight hardware using computer-aided design (CAD) software, with a focus on the ground support equipment (GSE) used to process and prepare the hardware for space. Throughout my ten weeks at this center, I have had the opportunity to work on several projects: the modification of the Multi-Payload Processing Facility (MPPF) High Bay, weekly mapping of the Space Station Processing Facility (SSPF) floor layout, kinematics applications for the Orion Command Module (CM) hatches, and the design modification of the Ares I Upper Stage hatch for maintenance purposes. The main goal of each of these projects was to generate an authentic simulation or representation using DELMIA V5 software. This allowed for evaluation of facility layouts, support equipment placement, and greater process understanding once it was used to demonstrate future processes to customers and other partners. As such, I have had the opportunity to contribute to a skilled team working on diverse projects with a central goal of providing essential planning resources for future center operations.

Burbank uses the Neurospat hardware in the Columbus Module

NASA Image and Video Library

2012-03-15

ISS030-E-177227 (15 March 2012) --- NASA astronaut Dan Burbank, Expedition 30 commander, uses Neurospat hardware to perform a science session with the European Space Agency PASSAGES experiment in the Columbus laboratory of the International Space Station. PASSAGES is designed to test how astronauts interpret visual information in weightlessness. It aims at studying the effects of microgravity on the use of the 'Eye-Height' strategy for estimating allowed actions in an environment, and whether this could possibly decrease after a long exposure to weightlessness.

Burbank uses the Neurospat hardware in the Columbus Module

NASA Image and Video Library

2012-03-15

ISS030-E-177225 (15 March 2012) --- NASA astronaut Dan Burbank, Expedition 30 commander, uses Neurospat hardware to perform a science session with the European Space Agency PASSAGES experiment in the Columbus laboratory of the International Space Station. PASSAGES is designed to test how astronauts interpret visual information in weightlessness. It aims at studying the effects of microgravity on the use of the 'Eye-Height' strategy for estimating allowed actions in an environment, and whether this could possibly decrease after a long exposure to weightlessness.

Study and design of cryogenic propellant acquisition systems. Volume 1: Design studies

NASA Technical Reports Server (NTRS)

Burge, G. W.; Blackmon, J. B.

1973-01-01

An in-depth study and selection of practical propellant surface tension acquisition system designs for two specific future cryogenic space vehicles, an advanced cryogenic space shuttle auxiliary propulsion system and an advanced space propulsion module is reported. A supporting laboratory scale experimental program was also conducted to provide design information critical to concept finalization and selection. Designs using localized pressure isolated surface tension screen devices were selected for each application and preliminary designs were generated. Based on these designs, large scale acquisition prototype hardware was designed and fabricated to be compatible with available NASA-MSFC feed system hardware.

Application and design of solar photovoltaic system

NASA Astrophysics Data System (ADS)

Tianze, Li; Hengwei, Lu; Chuan, Jiang; Luan, Hou; Xia, Zhang

2011-02-01

Solar modules, power electronic equipments which include the charge-discharge controller, the inverter, the test instrumentation and the computer monitoring, and the storage battery or the other energy storage and auxiliary generating plant make up of the photovoltaic system which is shown in the thesis. PV system design should follow to meet the load supply requirements, make system low cost, seriously consider the design of software and hardware, and make general software design prior to hardware design in the paper. To take the design of PV system for an example, the paper gives the analysis of the design of system software and system hardware, economic benefit, and basic ideas and steps of the installation and the connection of the system. It elaborates on the information acquisition, the software and hardware design of the system, the evaluation and optimization of the system. Finally, it shows the analysis and prospect of the application of photovoltaic technology in outer space, solar lamps, freeways and communications.

Returned Solar Max hardware degradation study results

NASA Technical Reports Server (NTRS)

Triolo, Jack J.; Ousley, Gilbert W.

1989-01-01

The Solar Maximum Repair Mission returned with the replaced hardware that had been in low Earth orbit for over four years. The materials of this returned hardware gave the aerospace community an opportunity to study the realtime effects of atomic oxygen, solar radiation, impact particles, charged particle radiation, and molecular contamination. The results of these studies are summarized.

On two new trends in evolvable hardware: employment of HDL-based structuring, and design of multi-functional circuits

NASA Technical Reports Server (NTRS)

Stoica, A.; Keymeulen, D.; Zebulum, R. S.; Ferguson, M. I.; Guo, X.

2002-01-01

This paper comments on some directions of growth for evolvable hardware, proposes research directions that address the scalability problem and gives examples of results in novel areas approached by EHW.

Transform coding for hardware-accelerated volume rendering.

PubMed

Fout, Nathaniel; Ma, Kwan-Liu

2007-01-01

Hardware-accelerated volume rendering using the GPU is now the standard approach for real-time volume rendering, although limited graphics memory can present a problem when rendering large volume data sets. Volumetric compression in which the decompression is coupled to rendering has been shown to be an effective solution to this problem; however, most existing techniques were developed in the context of software volume rendering, and all but the simplest approaches are prohibitive in a real-time hardware-accelerated volume rendering context. In this paper we present a novel block-based transform coding scheme designed specifically with real-time volume rendering in mind, such that the decompression is fast without sacrificing compression quality. This is made possible by consolidating the inverse transform with dequantization in such a way as to allow most of the reprojection to be precomputed. Furthermore, we take advantage of the freedom afforded by off-line compression in order to optimize the encoding as much as possible while hiding this complexity from the decoder. In this context we develop a new block classification scheme which allows us to preserve perceptually important features in the compression. The result of this work is an asymmetric transform coding scheme that allows very large volumes to be compressed and then decompressed in real-time while rendering on the GPU.

DATAS Hardware Diagnostic Tests

DOT National Transportation Integrated Search

1990-10-01

This document is reference material for personnel using the Data Link and : Analysis System (DATAS) for hardware diagnostic testing. Included in this : document is a brief overall description of the DATAS, and a thorough : description of how to opera...

Correcting lenticular astigmatism by reinstating the correct neuromuscular message.

PubMed

Yee, John William

2013-07-01

The spasm of the oblique muscles can contribute to lenticular astigmatism. The visual cortex interprets the tension of the oblique muscles as an eye that is in near focus mode. It overrides the response to the information generated by depth perception to bring a distant image into focus. Any excessive effort to bring it into focus will not be successful and continuing to make that effort can cause a misalignment in the tension of the rectus muscles. This in turn can directly induce corneal astigmatism and indirectly induce lenticular astigmatism. The astigmatic eye can still bring a near image into focus, but a distant image remains aberrant. The design of a special contact lens to treat lenticular astigmatism is similar to the design of a contact lens to treat corneal astigmatism by means of orthoculogy (or ortho C) as outlined in the paper Correcting Corneal Astigmatism by Reinstating the Correct Neuromuscular Message. The ortho C lens is worn for about two minutes to attend to the blur and distorted aspects of "simple myopic astigmatism". Both of these refractive errors are corrected simultaneously. Once the oblique muscles become "loose" due to a "contact lens draw", it triggers the visual cortex to reinstate the proper neuromotor message to stimulate the ciliary muscle (the muscle that controls the shape of the crystalline lens) to relax along a certain meridian-which in turn "flattens" the crystalline lens along that meridian to bring a blur and distorted image in the distance into focus. The correction only takes a few minutes because the ciliary muscle of an astigmatic eye was not compromised. The correction is not strictly due to an ortho C lens. Its design is the same for corneal astigmatism or lenticular astigmatism. The purpose of the design is to "loosen" the oblique muscles in a certain manner depending on the degree of astigmatism instead of a specific type of astigmatism. The visual cortex can discriminate whether to correct for corneal astigmatism

The Unified Floating Point Vector Coprocessor for Reconfigurable Hardware

NASA Astrophysics Data System (ADS)

Kathiara, Jainik

There has been an increased interest recently in using embedded cores on FPGAs. Many of the applications that make use of these cores have floating point operations. Due to the complexity and expense of floating point hardware, these algorithms are usually converted to fixed point operations or implemented using floating-point emulation in software. As the technology advances, more and more homogeneous computational resources and fixed function embedded blocks are added to FPGAs and hence implementation of floating point hardware becomes a feasible option. In this research we have implemented a high performance, autonomous floating point vector Coprocessor (FPVC) that works independently within an embedded processor system. We have presented a unified approach to vector and scalar computation, using a single register file for both scalar operands and vector elements. The Hybrid vector/SIMD computational model of FPVC results in greater overall performance for most applications along with improved peak performance compared to other approaches. By parameterizing vector length and the number of vector lanes, we can design an application specific FPVC and take optimal advantage of the FPGA fabric. For this research we have also initiated designing a software library for various computational kernels, each of which adapts FPVC's configuration and provide maximal performance. The kernels implemented are from the area of linear algebra and include matrix multiplication and QR and Cholesky decomposition. We have demonstrated the operation of FPVC on a Xilinx Virtex 5 using the embedded PowerPC.

Design of a cardiac monitor in terms of parameters of QRS complex.

PubMed

Chen, Zhen-cheng; Ni, Li-li; Su, Ke-ping; Wang, Hong-yan; Jiang, Da-zong

2002-08-01

Objective. To design a portable cardiac monitor system based on the available ordinary ECG machine and works on the basis of QRS parameters. Method. The 80196 single chip microcomputer was used as the central microprocessor and real time electrocardiac signal was collected and analyzed [correction of analysized] in the system. Result. Apart from the performance of an ordinary monitor, this machine possesses also the following functions: arrhythmia analysis, HRV analysis, alarm, freeze, and record of automatic papering. Convenient in carrying, the system is powered by AC or DC sources. Stability, low power and low cost are emphasized in the hardware design; and modularization method is applied in software design. Conclusion. Popular in usage and low cost made the portable monitor system suitable for use under simple conditions.

BASS Hardware Setup

NASA Image and Video Library

2016-01-27

ISS046e025945 (01/27/2016) --- NASA astronaut Tim Kopra sets up hardware for the Burning and Suppression of Solids – Milliken, or BASS-M, experiment. The BASS-M investigation tests flame-retardant cotton fabrics to determine how well they resist burning in microgravity. Results benefit research on flame-retardant textiles that can be used on Earth and in space

Hardware Design for a Fixed-Wing Airborne Gravity Measurement System

DTIC Science & Technology

1986-12-22

worldwide navigation system currently available that is sufficiently accurate for deter- mining Eotvos correction in airborne gravimetry is the Global...better in defining the strength of precipitation . The radar display is compact enough to be mounted on the cockpit, thus giving the pilots better...of the proposed AGMS version 3 MISCELLANEOUS AIRCRAFT CONSIDERATIONS Autopilot One of the most important considerations in airborne gravimetry is

Hardware survey for the avionics test bed

NASA Technical Reports Server (NTRS)

Cobb, J. M.

1981-01-01

A survey of maor hardware items that could possibly be used in the development of an avionics test bed for space shuttle attached or autonomous large space structures was conducted in NASA Johnson Space Center building 16. The results of the survey are organized to show the hardware by laboratory usage. Computer systems in each laboratory are described in some detail.

Easy Handling of Sensors and Actuators over TCP/IP Networks by Open Source Hardware/Software

PubMed Central

Mejías, Andrés; Herrera, Reyes S.; Márquez, Marco A.; Calderón, Antonio José; González, Isaías; Andújar, José Manuel

2017-01-01

There are several specific solutions for accessing sensors and actuators present in any process or system through a TCP/IP network, either local or a wide area type like the Internet. The usage of sensors and actuators of different nature and diverse interfaces (SPI, I2C, analogue, etc.) makes access to them from a network in a homogeneous and secure way more complex. A framework, including both software and hardware resources, is necessary to simplify and unify networked access to these devices. In this paper, a set of open-source software tools, specifically designed to cover the different issues concerning the access to sensors and actuators, and two proposed low-cost hardware architectures to operate with the abovementioned software tools are presented. They allow integrated and easy access to local or remote sensors and actuators. The software tools, integrated in the free authoring tool Easy Java and Javascript Simulations (EJS) solve the interaction issues between the subsystem that integrates sensors and actuators into the network, called convergence subsystem in this paper, and the Human Machine Interface (HMI)—this one designed using the intuitive graphical system of EJS—located on the user’s computer. The proposed hardware architectures and software tools are described and experimental implementations with the proposed tools are presented. PMID:28067801

Easy Handling of Sensors and Actuators over TCP/IP Networks by Open Source Hardware/Software.

PubMed

Mejías, Andrés; Herrera, Reyes S; Márquez, Marco A; Calderón, Antonio José; González, Isaías; Andújar, José Manuel

2017-01-05

There are several specific solutions for accessing sensors and actuators present in any process or system through a TCP/IP network, either local or a wide area type like the Internet. The usage of sensors and actuators of different nature and diverse interfaces (SPI, I2C, analogue, etc.) makes access to them from a network in a homogeneous and secure way more complex. A framework, including both software and hardware resources, is necessary to simplify and unify networked access to these devices. In this paper, a set of open-source software tools, specifically designed to cover the different issues concerning the access to sensors and actuators, and two proposed low-cost hardware architectures to operate with the abovementioned software tools are presented. They allow integrated and easy access to local or remote sensors and actuators. The software tools, integrated in the free authoring tool Easy Java and Javascript Simulations (EJS) solve the interaction issues between the subsystem that integrates sensors and actuators into the network, called convergence subsystem in this paper, and the Human Machine Interface (HMI)-this one designed using the intuitive graphical system of EJS-located on the user's computer. The proposed hardware architectures and software tools are described and experimental implementations with the proposed tools are presented.

Design and hardware-in-loop implementation of collision avoidance algorithms for heavy commercial road vehicles

NASA Astrophysics Data System (ADS)

Rajaram, Vignesh; Subramanian, Shankar C.

2016-07-01

An important aspect from the perspective of operational safety of heavy road vehicles is the detection and avoidance of collisions, particularly at high speeds. The development of a collision avoidance system is the overall focus of the research presented in this paper. The collision avoidance algorithm was developed using a sliding mode controller (SMC) and compared to one developed using linear full state feedback in terms of performance and controller effort. Important dynamic characteristics such as load transfer during braking, tyre-road interaction, dynamic brake force distribution and pneumatic brake system response were considered. The effect of aerodynamic drag on the controller performance was also studied. The developed control algorithms have been implemented on a Hardware-in-Loop experimental set-up equipped with the vehicle dynamic simulation software, IPG/TruckMaker®. The evaluation has been performed for realistic traffic scenarios with different loading and road conditions. The Hardware-in-Loop experimental results showed that the SMC and full state feedback controller were able to prevent the collision. However, when the discrepancies in the form of parametric variations were included, the SMC provided better results in terms of reduced stopping distance and lower controller effort compared to the full state feedback controller.

Defining Exercise Performance Metrics for Flight Hardware Development

NASA Technical Reports Server (NTRS)

Beyene, Nahon M.

2004-01-01

The space industry has prevailed over numerous design challenges in the spirit of exploration. Manned space flight entails creating products for use by humans and the Johnson Space Center has pioneered this effort as NASA's center for manned space flight. NASA Astronauts use a suite of flight exercise hardware to maintain strength for extravehicular activities and to minimize losses in muscle mass and bone mineral density. With a cycle ergometer, treadmill, and the Resistive Exercise Device available on the International Space Station (ISS), the Space Medicine community aspires to reproduce physical loading schemes that match exercise performance in Earth s gravity. The resistive exercise device presents the greatest challenge with the duty of accommodating 20 different exercises and many variations on the core set of exercises. This paper presents a methodology for capturing engineering parameters that can quantify proper resistive exercise performance techniques. For each specified exercise, the method provides engineering parameters on hand spacing, foot spacing, and positions of the point of load application at the starting point, midpoint, and end point of the exercise. As humans vary in height and fitness levels, the methodology presents values as ranges. In addition, this method shows engineers the proper load application regions on the human body. The methodology applies to resistive exercise in general and is in use for the current development of a Resistive Exercise Device. Exercise hardware systems must remain available for use and conducive to proper exercise performance as a contributor to mission success. The astronauts depend on exercise hardware to support extended stays aboard the ISS. Future plans towards exploration of Mars and beyond acknowledge the necessity of exercise. Continuous improvement in technology and our understanding of human health maintenance in space will allow us to support the exploration of Mars and the future of space

A Low-Complexity and High-Performance 2D Look-Up Table for LDPC Hardware Implementation

NASA Astrophysics Data System (ADS)

Chen, Jung-Chieh; Yang, Po-Hui; Lain, Jenn-Kaie; Chung, Tzu-Wen

In this paper, we propose a low-complexity, high-efficiency two-dimensional look-up table (2D LUT) for carrying out the sum-product algorithm in the decoding of low-density parity-check (LDPC) codes. Instead of employing adders for the core operation when updating check node messages, in the proposed scheme, the main term and correction factor of the core operation are successfully merged into a compact 2D LUT. Simulation results indicate that the proposed 2D LUT not only attains close-to-optimal bit error rate performance but also enjoys a low complexity advantage that is suitable for hardware implementation.

Parallel Processing with Digital Signal Processing Hardware and Software

NASA Technical Reports Server (NTRS)

Swenson, Cory V.

1995-01-01

The assembling and testing of a parallel processing system is described which will allow a user to move a Digital Signal Processing (DSP) application from the design stage to the execution/analysis stage through the use of several software tools and hardware devices. The system will be used to demonstrate the feasibility of the Algorithm To Architecture Mapping Model (ATAMM) dataflow paradigm for static multiprocessor solutions of DSP applications. The individual components comprising the system are described followed by the installation procedure, research topics, and initial program development.

Design Time Optimization for Hardware Watermarking Protection of HDL Designs

PubMed Central

Castillo, E.; Morales, D. P.; García, A.; Parrilla, L.; Todorovich, E.; Meyer-Baese, U.

2015-01-01

HDL-level design offers important advantages for the application of watermarking to IP cores, but its complexity also requires tools automating these watermarking algorithms. A new tool for signature distribution through combinational logic is proposed in this work. IPP@HDL, a previously proposed high-level watermarking technique, has been employed for evaluating the tool. IPP@HDL relies on spreading the bits of a digital signature at the HDL design level using combinational logic included within the original system. The development of this new tool for the signature distribution has not only extended and eased the applicability of this IPP technique, but it has also improved the signature hosting process itself. Three algorithms were studied in order to develop this automated tool. The selection of a cost function determines the best hosting solutions in terms of area and performance penalties on the IP core to protect. An 1D-DWT core and MD5 and SHA1 digital signatures were used in order to illustrate the benefits of the new tool and its optimization related to the extraction logic resources. Among the proposed algorithms, the alternative based on simulated annealing reduces the additional resources while maintaining an acceptable computation time and also saving designer effort and time. PMID:25861681

MetAlign 3.0: performance enhancement by efficient use of advances in computer hardware.

PubMed

Lommen, Arjen; Kools, Harrie J

2012-08-01

A new, multi-threaded version of the GC-MS and LC-MS data processing software, metAlign, has been developed which is able to utilize multiple cores on one PC. This new version was tested using three different multi-core PCs with different operating systems. The performance of noise reduction, baseline correction and peak-picking was 8-19 fold faster compared to the previous version on a single core machine from 2008. The alignment was 5-10 fold faster. Factors influencing the performance enhancement are discussed. Our observations show that performance scales with the increase in processor core numbers we currently see in consumer PC hardware development.

Weight and the Future of Space Flight Hardware Cost Modeling

NASA Technical Reports Server (NTRS)

Prince, Frank A.

2003-01-01

Weight has been used as the primary input variable for cost estimating almost as long as there have been parametric cost models. While there are good reasons for using weight, serious limitations exist. These limitations have been addressed by multi-variable equations and trend analysis in models such as NAFCOM, PRICE, and SEER; however, these models have not be able to address the significant time lags that can occur between the development of similar space flight hardware systems. These time lags make the cost analyst's job difficult because insufficient data exists to perform trend analysis, and the current set of parametric models are not well suited to accommodating process improvements in space flight hardware design, development, build and test. As a result, people of good faith can have serious disagreement over the cost for new systems. To address these shortcomings, new cost modeling approaches are needed. The most promising approach is process based (sometimes called activity) costing. Developing process based models will require a detailed understanding of the functions required to produce space flight hardware combined with innovative approaches to estimating the necessary resources. Particularly challenging will be the lack of data at the process level. One method for developing a model is to combine notional algorithms with a discrete event simulation and model changes to the total cost as perturbations to the program are introduced. Despite these challenges, the potential benefits are such that efforts should be focused on developing process based cost models.

49 CFR 238.105 - Train electronic hardware and software safety.

Code of Federal Regulations, 2011 CFR

2011-10-01

... 49 Transportation 4 2011-10-01 2011-10-01 false Train electronic hardware and software safety. 238... and General Requirements § 238.105 Train electronic hardware and software safety. The requirements of this section apply to electronic hardware and software used to control or monitor safety functions in...

49 CFR 238.105 - Train electronic hardware and software safety.

Code of Federal Regulations, 2014 CFR

2014-10-01

... 49 Transportation 4 2014-10-01 2014-10-01 false Train electronic hardware and software safety. 238... and General Requirements § 238.105 Train electronic hardware and software safety. The requirements of this section apply to electronic hardware and software used to control or monitor safety functions in...

49 CFR 238.105 - Train electronic hardware and software safety.

Code of Federal Regulations, 2012 CFR

2012-10-01

... 49 Transportation 4 2012-10-01 2012-10-01 false Train electronic hardware and software safety. 238... and General Requirements § 238.105 Train electronic hardware and software safety. The requirements of this section apply to electronic hardware and software used to control or monitor safety functions in...

49 CFR 238.105 - Train electronic hardware and software safety.

Code of Federal Regulations, 2013 CFR

2013-10-01

... 49 Transportation 4 2013-10-01 2013-10-01 false Train electronic hardware and software safety. 238... and General Requirements § 238.105 Train electronic hardware and software safety. The requirements of this section apply to electronic hardware and software used to control or monitor safety functions in...

Speed challenge: a case for hardware implementation in soft-computing

NASA Technical Reports Server (NTRS)

Daud, T.; Stoica, A.; Duong, T.; Keymeulen, D.; Zebulum, R.; Thomas, T.; Thakoor, A.

2000-01-01

For over a decade, JPL has been actively involved in soft computing research on theory, architecture, applications, and electronics hardware. The driving force in all our research activities, in addition to the potential enabling technology promise, has been creation of a niche that imparts orders of magnitude speed advantage by implementation in parallel processing hardware with algorithms made especially suitable for hardware implementation. We review our work on neural networks, fuzzy logic, and evolvable hardware with selected application examples requiring real time response capabilities.

Augmented burst-error correction for UNICON laser memory. [digital memory

NASA Technical Reports Server (NTRS)

Lim, R. S.

1974-01-01

A single-burst-error correction system is described for data stored in the UNICON laser memory. In the proposed system, a long fire code with code length n greater than 16,768 bits was used as an outer code to augment an existing inner shorter fire code for burst error corrections. The inner fire code is a (80,64) code shortened from the (630,614) code, and it is used to correct a single-burst-error on a per-word basis with burst length b less than or equal to 6. The outer code, with b less than or equal to 12, would be used to correct a single-burst-error on a per-page basis, where a page consists of 512 32-bit words. In the proposed system, the encoding and error detection processes are implemented by hardware. A minicomputer, currently used as a UNICON memory management processor, is used on a time-demanding basis for error correction. Based upon existing error statistics, this combination of an inner code and an outer code would enable the UNICON system to obtain a very low error rate in spite of flaws affecting the recorded data.

The Correction of Myopia Evaluation Trial: lessons from the study design.

PubMed

Hyman, L; Gwiazda, J

2004-01-01

The Correction of Myopia Evaluation Trial (COMET), a multicentre clinical trial based in 4 schools of optometry in the United States, evaluated the effect of progressive addition lenses versus single vision lenses on myopia progression in an ethnically diverse group of 469 myopic children aged 6 to 11 years. Completion of the clinical trial phase of the study provides an opportunity to evaluate aspects of the study design that contribute to its success. This article describes aspects of the study design that were influential in ensuring the smooth conduct of COMET. These include a dedicated team of investigators, an organisational structure with strong leadership and an independent Co-ordinating Centre, regular communication among investigators, flexible and creative approaches to recruitment and retention, sensitivity to concerns for child safety and child participation, and methods for enhancing and monitoring data reliability. The experience with COMET has provided a number of valuable lessons for all aspects of the study design that should benefit the development and implementation of future clinical trials, particularly those done in similar populations of children. The use of a carefully designed protocol using standard methods by dedicated members of the study team is essential in ensuring achievement of the study aims.

Hardware in the Loop at Megawatt-Scale Power | Energy Systems Integration

Science.gov Websites

Facility | NREL Hardware in the Loop at Megawatt-Scale Power Hardware in the Loop at Megawatt -Scale Power Hardware-in-the-loop simulation is not new, but the Energy System Integration Facility's -in-the-loop co-simulation. For more information, read the power hardware-in-the-loop factsheet. Text

3D graphics hardware accelerator programming methods for real-time visualization systems

NASA Astrophysics Data System (ADS)

Souetov, Andrew E.

2001-02-01

The paper deals with new approaches in software design for creating real-time applications that use modern graphics acceleration hardware. The growing complexity of such type of software compels programmers to use different types of CASE systems in design and development process. The subject under discussion is integration of such systems in a development process, their effective use, and the combination of these new methods with the necessity to produce optimal codes. A method of simulation integration and modeling tools in real-time software development cycle is described.

3D graphics hardware accelerator programming methods for real-time visualization systems

NASA Astrophysics Data System (ADS)

Souetov, Andrew E.

2000-02-01

The paper deals with new approaches in software design for creating real-time applications that use modern graphics acceleration hardware. The growing complexity of such type of software compels programmers to use different types of CASE systems in design and development process. The subject under discussion is integration of such systems in a development process, their effective use, and the combination of these new methods with the necessity to produce optimal codes. A method of simulation integration and modeling tools in real-time software development cycle is described.

Stripe nonuniformity correction for infrared imaging system based on single image optimization

NASA Astrophysics Data System (ADS)

Hua, Weiping; Zhao, Jufeng; Cui, Guangmang; Gong, Xiaoli; Ge, Peng; Zhang, Jiang; Xu, Zhihai

2018-06-01

Infrared imaging is often disturbed by stripe nonuniformity noise. Scene-based correction method can effectively reduce the impact of stripe noise. In this paper, a stripe nonuniformity correction method based on differential constraint is proposed. Firstly, the gray distribution of stripe nonuniformity is analyzed and the penalty function is constructed by the difference of horizontal gradient and vertical gradient. With the weight function, the penalty function is optimized to obtain the corrected image. Comparing with other single-frame approaches, experiments show that the proposed method performs better in both subjective and objective analysis, and does less damage to edge and detail. Meanwhile, the proposed method runs faster. We have also discussed the differences between the proposed idea and multi-frame methods. Our method is finally well applied in hardware system.

An Open Hardware seismic data recorder - a solid basis for citizen science

NASA Astrophysics Data System (ADS)

Mertl, Stefan

2015-04-01

"Ruwai" is a 24-Bit Open Hardware seismic data recorder. It is built up of four stackable printed circuit boards fitting the Arduino Mega 2560 microcontroller prototyping platform. An interface to the BeagleBone Black single-board computer enables extensive data storage, -processing and networking capabilities. The four printed circuit boards provide a uBlox Lea-6T GPS module and real-time clock (GPS Timing shield), an Texas Instruments ADS1274 24-Bit analog to digital converter (ADC main shield), an analog input section with a Texas Instruments PGA281 programmable gain amplifier and an analog anti-aliasing filter (ADC analog interface pga) and the power conditioning based on 9-36V DC input (power supply shield). The Arduino Mega 2560 is used for controlling the hardware components, timestamping sampled data using the GPS timing information and transmitting the data to the BeagleBone Black single-board computer. The BeagleBone Black provides local data storage, wireless mesh networking using the optimized link state routing daemon and differential GNSS positioning using the RTKLIB software. The complete hardware and software is published under free software - or open hardware licenses and only free software (e.g. KiCad) was used for the development to facilitate the reusability of the design and increases the sustainability of the project. "Ruwai" was developed within the framework of the "Community Environmental Observation Network (CEON)" (http://www.mertl-research.at/ceon/) which was supported by the Internet Foundation Austria (IPA) within the NetIdee 2013 call.

Wavefront correction and high-resolution in vivo OCT imaging with an objective integrated multi-actuator adaptive lens

PubMed Central

Bonora, Stefano; Jian, Yifan; Zhang, Pengfei; Zam, Azhar; Pugh, Edward N.; Zawadzki, Robert J.; Sarunic, Marinko V.

2015-01-01

Adaptive optics is rapidly transforming microscopy and high-resolution ophthalmic imaging. The adaptive elements commonly used to control optical wavefronts are liquid crystal spatial light modulators and deformable mirrors. We introduce a novel Multi-actuator Adaptive Lens that can correct aberrations to high order, and which has the potential to increase the spread of adaptive optics to many new applications by simplifying its integration with existing systems. Our method combines an adaptive lens with an imaged-based optimization control that allows the correction of images to the diffraction limit, and provides a reduction of hardware complexity with respect to existing state-of-the-art adaptive optics systems. The Multi-actuator Adaptive Lens design that we present can correct wavefront aberrations up to the 4th order of the Zernike polynomial characterization. The performance of the Multi-actuator Adaptive Lens is demonstrated in a wide field microscope, using a Shack-Hartmann wavefront sensor for closed loop control. The Multi-actuator Adaptive Lens and image-based wavefront-sensorless control were also integrated into the objective of a Fourier Domain Optical Coherence Tomography system for in vivo imaging of mouse retinal structures. The experimental results demonstrate that the insertion of the Multi-actuator Objective Lens can generate arbitrary wavefronts to correct aberrations down to the diffraction limit, and can be easily integrated into optical systems to improve the quality of aberrated images. PMID:26368169

Wavefront correction and high-resolution in vivo OCT imaging with an objective integrated multi-actuator adaptive lens.

PubMed

Bonora, Stefano; Jian, Yifan; Zhang, Pengfei; Zam, Azhar; Pugh, Edward N; Zawadzki, Robert J; Sarunic, Marinko V

2015-08-24

Adaptive optics is rapidly transforming microscopy and high-resolution ophthalmic imaging. The adaptive elements commonly used to control optical wavefronts are liquid crystal spatial light modulators and deformable mirrors. We introduce a novel Multi-actuator Adaptive Lens that can correct aberrations to high order, and which has the potential to increase the spread of adaptive optics to many new applications by simplifying its integration with existing systems. Our method combines an adaptive lens with an imaged-based optimization control that allows the correction of images to the diffraction limit, and provides a reduction of hardware complexity with respect to existing state-of-the-art adaptive optics systems. The Multi-actuator Adaptive Lens design that we present can correct wavefront aberrations up to the 4th order of the Zernike polynomial characterization. The performance of the Multi-actuator Adaptive Lens is demonstrated in a wide field microscope, using a Shack-Hartmann wavefront sensor for closed loop control. The Multi-actuator Adaptive Lens and image-based wavefront-sensorless control were also integrated into the objective of a Fourier Domain Optical Coherence Tomography system for in vivo imaging of mouse retinal structures. The experimental results demonstrate that the insertion of the Multi-actuator Objective Lens can generate arbitrary wavefronts to correct aberrations down to the diffraction limit, and can be easily integrated into optical systems to improve the quality of aberrated images.

Development of a hardware-based AC microgrid for AC stability assessment

NASA Astrophysics Data System (ADS)

Swanson, Robert R.

As more power electronic-based devices enable the development of high-bandwidth AC microgrids, the topic of microgrid power distribution stability has become of increased interest. Recently, researchers have proposed a relatively straightforward method to assess the stability of AC systems based upon the time-constants of sources, the net bus capacitance, and the rate limits of sources. In this research, a focus has been to develop a hardware test system to evaluate AC system stability. As a first step, a time domain model of a two converter microgrid was established in which a three phase inverter acts as a power source and an active rectifier serves as an adjustable constant power AC load. The constant power load can be utilized to create rapid power flow transients to the generating system. As a second step, the inverter and active rectifier were designed using a Smart Power Module IGBT for switching and an embedded microcontroller as a processor for algorithm implementation. The inverter and active rectifier were designed to operate simultaneously using a synchronization signal to ensure each respective local controller operates in a common reference frame. Finally, the physical system was created and initial testing performed to validate the hardware functionality as a variable amplitude and variable frequency AC system.

SIMPL Systems, or: Can We Design Cryptographic Hardware without Secret Key Information?

NASA Astrophysics Data System (ADS)

Rührmair, Ulrich

This paper discusses a new cryptographic primitive termed SIMPL system. Roughly speaking, a SIMPL system is a special type of Physical Unclonable Function (PUF) which possesses a binary description that allows its (slow) public simulation and prediction. Besides this public key like functionality, SIMPL systems have another advantage: No secret information is, or needs to be, contained in SIMPL systems in order to enable cryptographic protocols - neither in the form of a standard binary key, nor as secret information hidden in random, analog features, as it is the case for PUFs. The cryptographic security of SIMPLs instead rests on (i) a physical assumption on their unclonability, and (ii) a computational assumption regarding the complexity of simulating their output. This novel property makes SIMPL systems potentially immune against many known hardware and software attacks, including malware, side channel, invasive, or modeling attacks.

A low power biomedical signal processor ASIC based on hardware software codesign.

PubMed

Nie, Z D; Wang, L; Chen, W G; Zhang, T; Zhang, Y T

2009-01-01

A low power biomedical digital signal processor ASIC based on hardware and software codesign methodology was presented in this paper. The codesign methodology was used to achieve higher system performance and design flexibility. The hardware implementation included a low power 32bit RISC CPU ARM7TDMI, a low power AHB-compatible bus, and a scalable digital co-processor that was optimized for low power Fast Fourier Transform (FFT) calculations. The co-processor could be scaled for 8-point, 16-point and 32-point FFTs, taking approximate 50, 100 and 150 clock circles, respectively. The complete design was intensively simulated using ARM DSM model and was emulated by ARM Versatile platform, before conducted to silicon. The multi-million-gate ASIC was fabricated using SMIC 0.18 microm mixed-signal CMOS 1P6M technology. The die area measures 5,000 microm x 2,350 microm. The power consumption was approximately 3.6 mW at 1.8 V power supply and 1 MHz clock rate. The power consumption for FFT calculations was less than 1.5 % comparing with the conventional embedded software-based solution.

Flight Design System-1 System Design Document. Volume 9: Executive logic flow, program design language

NASA Technical Reports Server (NTRS)

1979-01-01

The detailed logic flow for the Flight Design System Executive is presented. The system is designed to provide the hardware/software capability required for operational support of shuttle flight planning.

The modified distal horizontal metatarsal osteotomy for correction of bunionette deformity.

PubMed

Radl, Roman; Leithner, Andreas; Koehler, Wolfgang; Scheipl, Susanne; Windhager, Reinhard

2005-06-01

Bunionette is a common deformity for which a number of operative procedures have been described. The objective of this study was to evaluate the results of a modified distal horizontal metatarsal osteotomy in the correction of symptomatic bunionette. Metatarsal osteotomies were done in 21 feet in 14 patients (11 females, three males) with an average age of 44 (range 20 to 67) years at the time of operation. The average followup was 32 (range 12 to 52) months. The average Lesser Toe Metatarsophalangeal-Interphalangeal Score of the American Orthopaedic Foot and Ankle Society increased from 42 points (range 24 to 50) preoperatively to 87 points (range 60 to 100) at the last followup. The fifth metatarsophalangeal angle averaged 18 degrees (5 to 38 degrees) preoperatively and 5 degrees (-5 to 26 degrees) at final followup. The 4-5 intermetatarsal angle averaged 14 degrees (10 to 20 degrees) preoperatively and 9 degrees (5 to 12 degrees) at final followup. Hardware was removed from two feet and scheduled for a third foot because of symptomatic skin irritation. The modified distal horizontal metatarsal osteotomy is a stable and reliable method for correction of bunionette. Unsatisfactory results in our patients were related to prominent hardware.

Evaluating the Applicability of Heritage Flight Hardware in Orion Environmental Control and Life Support Systems

NASA Technical Reports Server (NTRS)

Cross, Cynthia D.; Lewis, John F.; Barido, Richard A.; Carrasquillo, Robyn; Rains, George E.

2011-01-01

Recent changes in the overall NASA vision has resulted in further cost and schedule challenges for the Orion program. As a result, additional scrutiny has been focused on the use of new developments for hardware in the environmental control and life support systems. This paper will examine the Orion architecture as it is envisioned to support missions to the International Space Station and future exploration missions and determine what if any functions can be satisfied through the use of existing, heritage hardware designs. An initial evaluation of each component is included and where a heritage component was deemed likely further details are examined. Key technical parameters, mass, volume and vibration loads are a few of the specific items that are evaluated. Where heritage hardware has been identified that may be substituted in the Orion architecture a discussion of key requirement changes that may need to be made as well as recommendation to further evaluate applicability are noted.

P-MASS and P-GBA: Two new hardware developments for growing plants in space

NASA Technical Reports Server (NTRS)

Hoehn, Alexander; Luttges, Marvin W.; Robinson, Michael C.; Stodieck, Louis S.; Kliss, Mark H.

1994-01-01

Plant growth, and especially plant performance experiments in microgravity are limited by the currently available plant growth facilities (low light levels, inadequate nutrient delivery and atmosphere conditioning systems, insufficient science instrumentation, infrequent flight opportunities). In addition, mission durations of 10 to 14 days aboard the NSTS Space Shuttle allow for only brief periods of microgravity exposure with respect to the life cycle of a plant. Based on seed germination experiments, using the Generic BioProcessing Apparatus hardware (GBA), two new payloads have been designed specifically for plant growth. These payloads provide new opportunities for plant gravitational and space biology research and emphasize the investigation of plant performance (photosynthesis, biomass accumulations) in microgravity. The Plant-Module for Autonomous Space Support (P-MASS) was designed to utilize microgravity exposure times in excess of 30 days on the first flight of the recoverable COMET satellite (Commercial Experiment Transporter). The Plant-Generic Bioprocessing Apparatus (P-GBA), is designed for the National Space Transportation System (NSTS) Space Shuttle middeck and the SPACEHAB environment. The P-GBA is an evolution from the GBA hardware and P-MASS (plant chamber and instrumentation). The available light levels of both payloads more than double currently available capabilities.

A hardware architecture for real-time shadow removal in high-contrast video

NASA Astrophysics Data System (ADS)

Verdugo, Pablo; Pezoa, Jorge E.; Figueroa, Miguel

2017-09-01

Broadcasting an outdoor sports event at daytime is a challenging task due to the high contrast that exists between areas in the shadow and light conditions within the same scene. Commercial cameras typically do not handle the high dynamic range of such scenes in a proper manner, resulting in broadcast streams with very little shadow detail. We propose a hardware architecture for real-time shadow removal in high-resolution video, which reduces the shadow effect and simultaneously improves shadow details. The algorithm operates only on the shadow portions of each video frame, thus improving the results and producing more realistic images than algorithms that operate on the entire frame, such as simplified Retinex and histogram shifting. The architecture receives an input in the RGB color space, transforms it into the YIQ space, and uses color information from both spaces to produce a mask of the shadow areas present in the image. The mask is then filtered using a connected components algorithm to eliminate false positives and negatives. The hardware uses pixel information at the edges of the mask to estimate the illumination ratio between light and shadow in the image, which is then used to correct the shadow area. Our prototype implementation simultaneously processes up to 7 video streams of 1920×1080 pixels at 60 frames per second on a Xilinx Kintex-7 XC7K325T FPGA.

Is a 4-bit synaptic weight resolution enough? - constraints on enabling spike-timing dependent plasticity in neuromorphic hardware.

PubMed

Pfeil, Thomas; Potjans, Tobias C; Schrader, Sven; Potjans, Wiebke; Schemmel, Johannes; Diesmann, Markus; Meier, Karlheinz

2012-01-01

Large-scale neuromorphic hardware systems typically bear the trade-off between detail level and required chip resources. Especially when implementing spike-timing dependent plasticity, reduction in resources leads to limitations as compared to floating point precision. By design, a natural modification that saves resources would be reducing synaptic weight resolution. In this study, we give an estimate for the impact of synaptic weight discretization on different levels, ranging from random walks of individual weights to computer simulations of spiking neural networks. The FACETS wafer-scale hardware system offers a 4-bit resolution of synaptic weights, which is shown to be sufficient within the scope of our network benchmark. Our findings indicate that increasing the resolution may not even be useful in light of further restrictions of customized mixed-signal synapses. In addition, variations due to production imperfections are investigated and shown to be uncritical in the context of the presented study. Our results represent a general framework for setting up and configuring hardware-constrained synapses. We suggest how weight discretization could be considered for other backends dedicated to large-scale simulations. Thus, our proposition of a good hardware verification practice may rise synergy effects between hardware developers and neuroscientists.

ANNarchy: a code generation approach to neural simulations on parallel hardware

PubMed Central

Vitay, Julien; Dinkelbach, Helge Ü.; Hamker, Fred H.

2015-01-01

Many modern neural simulators focus on the simulation of networks of spiking neurons on parallel hardware. Another important framework in computational neuroscience, rate-coded neural networks, is mostly difficult or impossible to implement using these simulators. We present here the ANNarchy (Artificial Neural Networks architect) neural simulator, which allows to easily define and simulate rate-coded and spiking networks, as well as combinations of both. The interface in Python has been designed to be close to the PyNN interface, while the definition of neuron and synapse models can be specified using an equation-oriented mathematical description similar to the Brian neural simulator. This information is used to generate C++ code that will efficiently perform the simulation on the chosen parallel hardware (multi-core system or graphical processing unit). Several numerical methods are available to transform ordinary differential equations into an efficient C++code. We compare the parallel performance of the simulator to existing solutions. PMID:26283957

Compact FPGA hardware architecture for public key encryption in embedded devices.

PubMed

Rodríguez-Flores, Luis; Morales-Sandoval, Miguel; Cumplido, René; Feregrino-Uribe, Claudia; Algredo-Badillo, Ignacio

2018-01-01

Security is a crucial requirement in the envisioned applications of the Internet of Things (IoT), where most of the underlying computing platforms are embedded systems with reduced computing capabilities and energy constraints. In this paper we present the design and evaluation of a scalable low-area FPGA hardware architecture that serves as a building block to accelerate the costly operations of exponentiation and multiplication in [Formula: see text], commonly required in security protocols relying on public key encryption, such as in key agreement, authentication and digital signature. The proposed design can process operands of different size using the same datapath, which exhibits a significant reduction in area without loss of efficiency if compared to representative state of the art designs. For example, our design uses 96% less standard logic than a similar design optimized for performance, and 46% less resources than other design optimized for area. Even using fewer area resources, our design still performs better than its embedded software counterparts (190x and 697x).

Effect of color visualization and display hardware on the visual assessment of pseudocolor medical images

PubMed Central

Zabala-Travers, Silvina; Choi, Mina; Cheng, Wei-Chung

2015-01-01

Purpose: Even though the use of color in the interpretation of medical images has increased significantly in recent years, the ad hoc manner in which color is handled and the lack of standard approaches have been associated with suboptimal and inconsistent diagnostic decisions with a negative impact on patient treatment and prognosis. The purpose of this study is to determine if the choice of color scale and display device hardware affects the visual assessment of patterns that have the characteristics of functional medical images. Methods: Perfusion magnetic resonance imaging (MRI) was the basis for designing and performing experiments. Synthetic images resembling brain dynamic-contrast enhanced MRI consisting of scaled mixtures of white, lumpy, and clustered backgrounds were used to assess the performance of a rainbow (“jet”), a heated black-body (“hot”), and a gray (“gray”) color scale with display devices of different quality on the detection of small changes in color intensity. The authors used a two-alternative, forced-choice design where readers were presented with 600 pairs of images. Each pair consisted of two images of the same pattern flipped along the vertical axis with a small difference in intensity. Readers were asked to select the image with the highest intensity. Three differences in intensity were tested on four display devices: a medical-grade three-million-pixel display, a consumer-grade monitor, a tablet device, and a phone. Results: The estimates of percent correct show that jet outperformed hot and gray in the high and low range of the color scales for all devices with a maximum difference in performance of 18% (confidence intervals: 6%, 30%). Performance with hot was different for high and low intensity, comparable to jet for the high range, and worse than gray for lower intensity values. Similar performance was seen between devices using jet and hot, while gray performance was better for handheld devices. Time of performance was

OS friendly microprocessor architecture: Hardware level computer security

NASA Astrophysics Data System (ADS)

Jungwirth, Patrick; La Fratta, Patrick

2016-05-01

We present an introduction to the patented OS Friendly Microprocessor Architecture (OSFA) and hardware level computer security. Conventional microprocessors have not tried to balance hardware performance and OS performance at the same time. Conventional microprocessors have depended on the Operating System for computer security and information assurance. The goal of the OS Friendly Architecture is to provide a high performance and secure microprocessor and OS system. We are interested in cyber security, information technology (IT), and SCADA control professionals reviewing the hardware level security features. The OS Friendly Architecture is a switched set of cache memory banks in a pipeline configuration. For light-weight threads, the memory pipeline configuration provides near instantaneous context switching times. The pipelining and parallelism provided by the cache memory pipeline provides for background cache read and write operations while the microprocessor's execution pipeline is running instructions. The cache bank selection controllers provide arbitration to prevent the memory pipeline and microprocessor's execution pipeline from accessing the same cache bank at the same time. This separation allows the cache memory pages to transfer to and from level 1 (L1) caching while the microprocessor pipeline is executing instructions. Computer security operations are implemented in hardware. By extending Unix file permissions bits to each cache memory bank and memory address, the OSFA provides hardware level computer security.

New Approaches in Force-Limited Vibration Testing of Flight Hardware

NASA Technical Reports Server (NTRS)

Kolaini, Ali R.; Kern, Dennis L.

2012-01-01

To qualify flight hardware for random vibration environments the following methods are used to limit the loads in the aerospace industry: (1) Response limiting and notching (2) Simple TDOF model (3) Semi-empirical force limits (4) Apparent mass, etc. and (5) Impedance method. In all these methods attempts are made to remove conservatism due to the mismatch in impedances between the test and the flight configurations of the hardware that are being qualified. Assumption is the hardware interfaces have correlated responses. A new method that takes into account the un-correlated hardware interface responses are described in this presentation.

PLC Hardware Discrimination using RF-DNA fingerprinting

DTIC Science & Technology

2014-06-19

PLC HARDWARE DISCRIMINATION USING RF-DNA FINGERPRINTING THESIS Bradley C. Wright, Civilian, USAF AFIT-ENG-T-14-J-12 DEPARTMENT OF THE AIR FORCE AIR...protection in the United States. AFIT-ENG-T-14-J-12 PLC HARDWARE DISCRIMINATION USING RF-DNA FINGERPRINTING THESIS Presented to the Faculty Department...DISCRIMINATION USING RF-DNA FINGERPRINTING Bradley C. Wright, B.S.E.E. Civilian, USAF Approved: /signed/ Maj Samuel J. Stone, PhD (Chairman) /signed/ Michael A

rf design of a pulse compressor with correction cavity chain for klystron-based compact linear collider

NASA Astrophysics Data System (ADS)

Wang, Ping; Zha, Hao; Syratchev, Igor; Shi, Jiaru; Chen, Huaibi

2017-11-01

We present an X-band high-power pulse compression system for a klystron-based compact linear collider. In this system design, one rf power unit comprises two klystrons, a correction cavity chain, and two SLAC Energy Doubler (SLED)-type X-band pulse compressors (SLEDX). An rf pulse passes the correction cavity chain, by which the pulse shape is modified. The rf pulse is then equally split into two ways, each deploying a SLEDX to compress the rf power. Each SLEDX produces a short pulse with a length of 244 ns and a peak power of 217 MW to power four accelerating structures. With the help of phase-to-amplitude modulation, the pulse has a dedicated shape to compensate for the beam loading effect in accelerating structures. The layout of this system and the rf design and parameters of the new pulse compressor are described in this work.

Fast interactive elastic registration of 12-bit multi-spectral images with subvoxel accuracy using display hardware

NASA Astrophysics Data System (ADS)

Noordmans, Herke Jan; de Roode, Rowland; Verdaasdonk, Rudolf

2007-03-01

Multi-spectral images of human tissue taken in-vivo often contain image alignment problems as patients have difficulty in retaining their posture during the acquisition time of 20 seconds. Previously, it has been attempted to correct motion errors with image registration software developed for MR or CT data but these algorithms have been proven to be too slow and erroneous for practical use with multi-spectral images. A new software package has been developed which allows the user to play a decisive role in the registration process as the user can monitor the progress of the registration continuously and force it in the right direction when it starts to fail. The software efficiently exploits videocard hardware to gain speed and to provide a perfect subvoxel correspondence between registration field and display. An 8 bit graphic card was used to efficiently register and resample 12 bit images using the hardware interpolation modes present on the graphic card. To show the feasibility of this new registration process, the software was applied in clinical practice evaluating the dosimetry for psoriasis and KTP laser treatment. The microscopic differences between images of normal skin and skin exposed to UV light proved that an affine registration step including zooming and slanting is critical for a subsequent elastic match to have success. The combination of user interactive registration software with optimal addressing the potentials of PC video card hardware greatly improves the speed of multi spectral image registration.

BLACKCOMB2: Hardware-software co-design for non-volatile memory in exascale systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mudge, Trevor