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Sample records for correct hardware design

  1. A hardware implementation of a provably correct design of a fault-tolerant clock synchronization circuit

    NASA Technical Reports Server (NTRS)

    Torres-Pomales, Wilfredo

    1993-01-01

    A fault-tolerant clock synchronization system was designed to a proven correct formal specification. Formal methods were used in the development of this specification. A description of the system and an analysis of the tests performed are presented. Plots of typical experimental results are included.

  2. Design of an IRFPA nonuniformity correction algorithm to be implemented as a real-time hardware prototype

    NASA Astrophysics Data System (ADS)

    Fenner, Jonathan W.; Simon, Solomon H.; Eden, Dayton D.

    1994-07-01

    As new IR focal plane array (IRFPA) technologies become available, improved methods for coping with array errors must be developed. Traditional methods of nonuniformity correction using simple calibration mode are not adequate to compensate for the inherent nonuniformity and 1/f noise in some arrays. In an effort to compensate for nonuniformity in a HgCdTe IRFPA, and to reduce the effects of 1/f noise over a time interval, a new dynamic neural network (NN) based algorithm was implemented. The algorithm compensates for nonuniformities, and corrects for 1/f noise. A gradient descent algorithm is used with nearest neighbor feedback for training, creating a dynamic model of the IRFPA's gains and offsets, then updating and correcting them continuously. Improvements to the NN include implementation on a IBM 486 computer system, and a close examination of simulated scenes to test the algorithms boundaries. Preliminary designs for a real-time hardware prototype have been developed as well. Simulations were implemented to test the algorithm's ability to correct under a variety of conditions. A wide range of background noise, 1/f noise, object intensities, and background intensities were used. Results indicate that this algorithm can correct efficiently down to the background noise. Our conclusions are that NN based adaptive algorithms will supplement the effectiveness of IRFPA's.

  3. Resampling in hyperspectral cameras as an alternative to correcting keystone in hardware, with focus on benefits for optical design and data quality

    NASA Astrophysics Data System (ADS)

    Fridman, Andrei; Høye, Gudrun; Løke, Trond

    2014-05-01

    Current high-resolution hyperspectral cameras attempt to correct misregistration errors in hardware. This severely limits other specifications of the hyperspectral camera, such as spatial resolution and light gathering capacity. If resampling is used to correct keystone in software instead of in hardware, then these stringent requirements could be lifted. Preliminary designs show that a resampling camera should be able to resolve at least 3000-5000 pixels, while at the same time collecting up to four times more light than the majority of current high spatial resolution cameras. A virtual camera software, specifically developed for this purpose, was used to compare the performance of resampling and hardware corrected cameras. Different criteria are suggested for quantifying the camera performance. The simulations showed that the performance of a resampling camera is comparable to that of a hardware corrected camera with 0.1 pixel residual keystone, and that the use of a more advanced resampling method than the commonly used linear interpolation, such as high-resolution cubic splines, is highly beneficial for the data quality of the resampled image. Our findings suggest that if high-resolution sensors are available, it would be better to use resampling instead of trying to correct keystone in hardware.

  4. Resampling in hyperspectral cameras as an alternative to correcting keystone in hardware, with focus on benefits for the optical design and data quality

    NASA Astrophysics Data System (ADS)

    Fridman, Andrei; Høye, Gudrun; Løke, Trond

    2013-06-01

    Current high-resolution hyperspectral cameras attempt to correct misregistration errors in hardware. Usually, it is required that aberrations in the optical system must be controlled with precision 0.1 pixel or smaller. This severely limits other specifications of the hyperspectral camera, such as spatial resolution and light gathering capacity, and often requires very tight tolerances. If resampling is used to correct keystone in software instead of in hardware, then these stringent requirements could be lifted. Preliminary designs show that a resampling camera should be able to resolve at least 3000-5000 pixels, while at the same time collecting up to four times more light than the majority of current high spatial resolution cameras that correct keystone in hardware (HW corrected cameras). A Virtual Camera software, specifically developed for this purpose, was used to compare the performance of resampling cameras and HW corrected cameras. For the cameras where a large keystone is corrected by resampling, different resampling methods are investigated. Different criteria are suggested for quantifying performance, and the tested cameras are compared according to these criteria. The simulations showed that the performance of a resampling camera is comparable to that of a HW corrected camera with 0.1 pixel residual keystone, and that the use of a more advanced resampling method than the commonly used linear interpolation - such as for instance high-resolution cubic splines - is highly beneficial for the data quality of the resampled image. Our findings suggest that if high-resolution sensors are available, it would be better to use resampling instead of trying to correct keystone in hardware.

  5. Correctness properties for iterated hardware structures

    NASA Technical Reports Server (NTRS)

    Windley, Phillip J.

    1993-01-01

    Iterated structures occur frequently in hardware. This paper describes properties required of mathematical relations that can be implemented iteratively and demonstrates the use of these properties on a generalized class of adders. This work provides a theoretical basis for the correct synthesis of iterated arithmetic structures.

  6. Fundamental Hardware Design in PVS

    NASA Technical Reports Server (NTRS)

    Leathrum, James F., Jr.

    1997-01-01

    The development of Programmable Logic Devices (PLDs) has introduced programming as a primary tool in the development of digital circuits. This work attempts to create a generic verification environment in which designs can be specified and verified using the Prototype Verification System (PVS). This is accomplished by providing library support for general hardware constructs. The environment is intended for use with any PLD and any PLD programming language. The goal of the environment is to allow the easy translation of digital designs to PVS and provide sufficient support to make verification possible without a great deal of effort.

  7. X-15 Hardware Design Challenges

    NASA Technical Reports Server (NTRS)

    Storms, Harrison A., Jr.

    1991-01-01

    Historical events in the development of the X-15 hardware design are presented. Some of the topics covered include: (1) drivers that led to the development of the X-15; (2) X-15 space research objectives; (3) original performance targets; (4) the X-15 typical mission; (5) X-15 dimensions and weight; (5) the propulsion system; (6) X-15 development milestones; (7) engineering and manufacturing challenges; (8) the X-15 structure; (9) ballistic flight control; (10) landing gear; (11) nose gear; and (12) an X-15 program recap.

  8. Comparative Modal Analysis of Sieve Hardware Designs

    NASA Technical Reports Server (NTRS)

    Thompson, Nathaniel

    2012-01-01

    The CMTB Thwacker hardware operates as a testbed analogue for the Flight Thwacker and Sieve components of CHIMRA, a device on the Curiosity Rover. The sieve separates particles with a diameter smaller than 150 microns for delivery to onboard science instruments. The sieving behavior of the testbed hardware should be similar to the Flight hardware for the results to be meaningful. The elastodynamic behavior of both sieves was studied analytically using the Rayleigh Ritz method in conjunction with classical plate theory. Finite element models were used to determine the mode shapes of both designs, and comparisons between the natural frequencies and mode shapes were made. The analysis predicts that the performance of the CMTB Thwacker will closely resemble the performance of the Flight Thwacker within the expected steady state operating regime. Excitations of the testbed hardware that will mimic the flight hardware were recommended, as were those that will improve the efficiency of the sieving process.

  9. Hardware

    NASA Technical Reports Server (NTRS)

    1999-01-01

    The full complement of EDOMP investigations called for a broad spectrum of flight hardware ranging from commercial items, modified for spaceflight, to custom designed hardware made to meet the unique requirements of testing in the space environment. In addition, baseline data collection before and after spaceflight required numerous items of ground-based hardware. Two basic categories of ground-based hardware were used in EDOMP testing before and after flight: (1) hardware used for medical baseline testing and analysis, and (2) flight-like hardware used both for astronaut training and medical testing. To ensure post-landing data collection, hardware was required at both the Kennedy Space Center (KSC) and the Dryden Flight Research Center (DFRC) landing sites. Items that were very large or sensitive to the rigors of shipping were housed permanently at the landing site test facilities. Therefore, multiple sets of hardware were required to adequately support the prime and backup landing sites plus the Johnson Space Center (JSC) laboratories. Development of flight hardware was a major element of the EDOMP. The challenges included obtaining or developing equipment that met the following criteria: (1) compact (small size and light weight), (2) battery-operated or requiring minimal spacecraft power, (3) sturdy enough to survive the rigors of spaceflight, (4) quiet enough to pass acoustics limitations, (5) shielded and filtered adequately to assure electromagnetic compatibility with spacecraft systems, (6) user-friendly in a microgravity environment, and (7) accurate and efficient operation to meet medical investigative requirements.

  10. Space hardware designs, volume 1

    NASA Technical Reports Server (NTRS)

    Meyer, Rudolf X.; Cribbs, Richard; Honda, Mark; Ma, Christina; Robson, Christopher

    1994-01-01

    The design of a solar sail space vehicle with a novel sail deployment mechanism is described. The sail is triangular in shape and is deployed and stabilized by three miniature spacecraft, one at each corner of the triangle. A concept demonstrator for a spherical microrover for the exploration of a planetary surface is described. Lastly, laboratory experiments have been conducted to study the migration of thin oil films on metal surfaces in the presence of a thermal gradient.

  11. Digital Hardware Design Teaching: An Alternative Approach

    ERIC Educational Resources Information Center

    Benkrid, Khaled; Clayton, Thomas

    2012-01-01

    This article presents the design and implementation of a complete review of undergraduate digital hardware design teaching in the School of Engineering at the University of Edinburgh. Four guiding principles have been used in this exercise: learning-outcome driven teaching, deep learning, affordability, and flexibility. This has identified…

  12. Design considerations for space flight hardware

    NASA Technical Reports Server (NTRS)

    Glover, Daniel

    1990-01-01

    The environmental and design constraints are reviewed along with some insight into the established design and quality assurance practices that apply to low earth orbit (LEO) space flight hardware. It is intended as an introduction for people unfamiliar with space flight considerations. Some basic data and a bibliography are included.

  13. Shuttle mission simulator hardware conceptual design report

    NASA Technical Reports Server (NTRS)

    Burke, J. F.

    1973-01-01

    The detailed shuttle mission simulator hardware requirements are discussed. The conceptual design methods, or existing technology, whereby those requirements will be fulfilled are described. Information of a general nature on the total design problem plus specific details on how these requirements are to be satisfied are reported. The configuration of the simulator is described and the capabilities for various types of training are identified.

  14. Access flight hardware design and development

    NASA Technical Reports Server (NTRS)

    Rogers, John F.; Tutterow, Robin D.

    1987-01-01

    Several items were found to be of immense value in the design and development of the Assembly Concept for Construction of Erectable Space Structures (ACCESS) hardware. The early availability of mock-up and engineering test hardware helped to develop the concept and prove the feasibility of the experiment. The extensive neutral buoyancy testing was invaluable in developing the procedures and timelines, proving that the hardware functioned as intended, and effectively trained the astronauts. The early involvement of the crew systems/astronaut personnel was extremely beneficial in shaping the design to meet the EVA compatibility requirements. Also, the early definition of coupled loads and on-orbit dynamic responses can not be overemphasized due to the relative uncertainty in the magnitude of these loads and their impact on the design.

  15. Microprocessor Design Using Hardware Description Language

    ERIC Educational Resources Information Center

    Mita, Rosario; Palumbo, Gaetano

    2008-01-01

    The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

  16. Design guidelines for robotically serviceable hardware

    NASA Technical Reports Server (NTRS)

    Gordon, Scott A.

    1988-01-01

    Research being conducted at the Goddard Space Flight Center into the development of guidelines for the design of robotically serviceable spaceflight hardware is described. A mock-up was built based on an existing spaceflight system demonstrating how these guidelines can be applied to actual hardware. The report examines the basic servicing philosophy being studied and how this philosophy is reflected in the formulation of design guidelines for robotic servicing. A description of the mock-up is presented with emphasis on the design features that make it robot friendly. Three robotic servicing schemes fulfilling the design guidelines were developed for the mock-up. These servicing schemes are examined as to how their implementation was affected by the constraints of the spacecraft system on which the mock-up is based.

  17. SuperCDMS Cold Hardware Design

    SciTech Connect

    Al Kenany, S.; Rolla, Julie A.; Godfrey, Gary; Brink, Paul L.; Seitz, Dennis N.; Figueroa-Feliciano, Enectali; Huber, Martin E.; Hines, Bruce A.; Irwin, Kent D.; /NIST, Boulder

    2012-06-13

    We discuss the current design of the cold hardware and cold electronics to be used in the upcoming SuperCDMS Soudan deployment. Engineering challenges associated with such concerns as thermal isolation, microphonics, radiopurity, and power dissipation are discussed, along with identifying the design changes necessary for SuperCDMS SNOLAB. The Cryogenic Dark Matter Search (CDMS) employs ultrapure 1-inch thick, 3-inch diameter germanium crystals operating below 50 mK in a dilution cryostat. These detectors give an ionization and phonon signal, which gives us rejection capabilities regarding background events versus dark matter signals.

  18. Design Space Issues for Intrinsic Evolvable Hardware

    NASA Technical Reports Server (NTRS)

    Hereford, James; Gwaltney, David

    2004-01-01

    This paper discusses the problem of increased programming time for intrinsic evolvable hardware (EM) as the complexity of the circuit grows. As the circuit becomes more complex, then more components will be required and a longer programming string, L, is required. We develop equations for the size of the population, n, and the number of generations required for the population to converge, based on L. Our analytical results show that even though the design search space grows as 2L (assuming a binary programming string), the number of circuit evaluations, n*ngen, only grows as O(Lg3), or slightly less than O(L). This makes evolvable techniques a good tool for exploring large design spaces. The major hurdle for intrinsic EHW is evaluation time for each possible circuit. The evaluation time involves downloading the bit string to the device, updating the device configuration, measuring the output and then transferring the output data to the control processor. Each of these steps must be done for each member of the population. The processing time of the computer becomes negligible since the selection/crossover/mutation steps are only done once per generation. Evaluation time presently limits intrinsic evolvable hardware techniques to designing only small or medium-sized circuits. To evolve large or complicated circuits, several researchers have proposed using hierarchical design or reuse techniques where submodules are combined together to form complex circuits. However, these practical approaches limit the search space of available designs and preclude utilizing parasitic coupling or other effects within the programmable device. The practical approaches also raise the issue of why intrinsic EHW techniques do not easily apply to large design spaces, since the analytical results show only an O(L) complexity growth.

  19. Theorem Proving in Intel Hardware Design

    NASA Technical Reports Server (NTRS)

    O'Leary, John

    2009-01-01

    For the past decade, a framework combining model checking (symbolic trajectory evaluation) and higher-order logic theorem proving has been in production use at Intel. Our tools and methodology have been used to formally verify execution cluster functionality (including floating-point operations) for a number of Intel products, including the Pentium(Registered TradeMark)4 and Core(TradeMark)i7 processors. Hardware verification in 2009 is much more challenging than it was in 1999 - today s CPU chip designs contain many processor cores and significant firmware content. This talk will attempt to distill the lessons learned over the past ten years, discuss how they apply to today s problems, outline some future directions.

  20. Employing ISRU Models to Improve Hardware Design

    NASA Technical Reports Server (NTRS)

    Linne, Diane L.

    2010-01-01

    An analytical model for hydrogen reduction of regolith was used to investigate the effects of several key variables on the energy and mass performance of reactors for a lunar in-situ resource utilization oxygen production plant. Reactor geometry, reaction time, number of reactors, heat recuperation, heat loss, and operating pressure were all studied to guide hardware designers who are developing future prototype reactors. The effects of heat recuperation where the incoming regolith is pre-heated by the hot spent regolith before transfer was also investigated for the first time. In general, longer reaction times per batch provide a lower overall energy, but also result in larger and heavier reactors. Three reactors with long heat-up times results in similar energy requirements as a two-reactor system with all other parameters the same. Three reactors with heat recuperation results in energy reductions of 20 to 40 percent compared to a three-reactor system with no heat recuperation. Increasing operating pressure can provide similar energy reductions as heat recuperation for the same reaction times.

  1. The Art of Space Flight Exercise Hardware: Design and Implementation

    NASA Technical Reports Server (NTRS)

    Beyene, Nahom M.

    2004-01-01

    The design of space flight exercise hardware depends on experience with crew health maintenance in a microgravity environment, history in development of flight-quality exercise hardware, and a foundation for certifying proper project management and design methodology. Developed over the past 40 years, the expertise in designing exercise countermeasures hardware at the Johnson Space Center stems from these three aspects of design. The medical community has steadily pursued an understanding of physiological changes in humans in a weightless environment and methods of counteracting negative effects on the cardiovascular and musculoskeletal system. The effects of weightlessness extend to the pulmonary and neurovestibular system as well with conditions ranging from motion sickness to loss of bone density. Results have shown losses in water weight and muscle mass in antigravity muscle groups. With the support of university-based research groups and partner space agencies, NASA has identified exercise to be the primary countermeasure for long-duration space flight. The history of exercise hardware began during the Apollo Era and leads directly to the present hardware on the International Space Station. Under the classifications of aerobic and resistive exercise, there is a clear line of development from the early devices to the countermeasures hardware used today. In support of all engineering projects, the engineering directorate has created a structured framework for project management. Engineers have identified standards and "best practices" to promote efficient and elegant design of space exercise hardware. The quality of space exercise hardware depends on how well hardware requirements are justified by exercise performance guidelines and crew health indicators. When considering the microgravity environment of the device, designers must consider performance of hardware separately from the combined human-in-hardware system. Astronauts are the caretakers of the hardware

  2. Automated Hardware Design via Evolutionary Search

    NASA Technical Reports Server (NTRS)

    Lohn, Jason D.; Colombano, Silvano P.

    2000-01-01

    The goal of this research is to investigate the application of evolutionary search to the process of automated engineering design. Evolutionary search techniques involve the simulation of Darwinian mechanisms by computer algorithms. In recent years, such techniques have attracted much attention because they are able to tackle a wide variety of difficult problems and frequently produce acceptable solutions. The results obtained are usually functional, often surprising, and typically "messy" because the algorithms are told to concentrate on the overriding objective and not elegance or simplicity. advantages. First, faster design cycles translate into time and, hence, cost savings. Second, automated design techniques can be made to scale well and hence better deal with increasing amounts of design complexity. Third, design quality can increase because design properties can be specified a priori. For example, size and weight specifications of a device, smaller and lighter than the best known design, might be optimized by the automated design technique. The domain of electronic circuit design is an advantageous platform in which to study automated design techniques because it is a rich design space that is well understood, permitting human-created designs to be compared to machine- generated designs. developed for circuit design was to automatically produce high-level integrated electronic circuit designs whose properties permit physical implementation in silicon. This process entailed designing an effective evolutionary algorithm and solving a difficult multiobjective optimization problem. FY 99 saw many accomplishments in this effort.

  3. The monarch parallel processor hardware design

    SciTech Connect

    Rettberg, R.D.; Crowther, W.R.; Carvey, P.P.; Tomlinson, R.S. )

    1990-04-01

    The authors report on their development of the Monarch parallel processor. Today, the Monarch's design is largely done and well into implementation. The high-speed interconnection network has been tested with two-micron switch chips, logging more than 30,000 device hours of operation at 125 mega bits per second passing over 10{sup 16} bits. The processor's logic design is almost complete and simulated. The memory controller and concentrator remain to be designed. The authors have analyzed the software in detail with the use of hand-coded examples, a simulator, and a rudimentary compiler. The authors are currently seeking support to finish the implementation.

  4. Magnetic resonance elastography hardware design: a survey.

    PubMed

    Tse, Z T H; Janssen, H; Hamed, A; Ristic, M; Young, I; Lamperth, M

    2009-05-01

    Magnetic resonance elastography (MRE) is an emerging technique capable of measuring the shear modulus of tissue. A suspected tumour can be identified by comparing its properties with those of tissues surrounding it; this can be achieved even in deep-lying areas as long as mechanical excitation is possible. This would allow non-invasive methods for cancer-related diagnosis in areas not accessible with conventional palpation. An actuating mechanism is required to generate the necessary tissue displacements directly on the patient in the scanner and three different approaches, in terms of actuator action and position, exist to derive stiffness measurements. However, the magnetic resonance (MR) environment places considerable constraints on the design of such devices, such as the possibility of mutual interference between electrical components, the scanner field, and radio frequency pulses, and the physical space restrictions of the scanner bore. This paper presents a review of the current solutions that have been developed for MRE devices giving particular consideration to the design criteria including the required vibration frequency and amplitude in different applications, the issue of MR compatibility, actuation principles, design complexity, and scanner synchronization issues. The future challenges in this field are also described. PMID:19499839

  5. Flight Hardware Packaging Design for Stringent EMC Radiated Emission Requirements

    NASA Technical Reports Server (NTRS)

    Lortz, Charlene L.; Huang, Chi-Chien N.; Ravich, Joshua A.; Steiner, Carl N.

    2013-01-01

    This packaging design approach can help heritage hardware meet a flight project's stringent EMC radiated emissions requirement. The approach requires only minor modifications to a hardware's chassis and mainly concentrates on its connector interfaces. The solution is to raise the surface area where the connector is mounted by a few millimeters using a pedestal, and then wrapping with conductive tape from the cable backshell down to the surface-mounted connector. This design approach has been applied to JPL flight project subsystems. The EMC radiated emissions requirements for flight projects can vary from benign to mission critical. If the project's EMC requirements are stringent, the best approach to meet EMC requirements would be to design an EMC control program for the project early on and implement EMC design techniques starting with the circuit board layout. This is the ideal scenario for hardware that is built from scratch. Implementation of EMC radiated emissions mitigation techniques can mature as the design progresses, with minimal impact to the design cycle. The real challenge exists for hardware that is planned to be flown following a built-to-print approach, in which heritage hardware from a past project with a different set of requirements is expected to perform satisfactorily for a new project. With acceptance of heritage, the design would already be established (circuit board layout and components have already been pre-determined), and hence any radiated emissions mitigation techniques would only be applicable at the packaging level. The key is to take a heritage design with its known radiated emissions spectrum and repackage, or modify its chassis design so that it would have a better chance of meeting the new project s radiated emissions requirements.

  6. Design Tools for Reconfigurable Hardware in Orbit (RHinO)

    NASA Technical Reports Server (NTRS)

    French, Mathew; Graham, Paul; Wirthlin, Michael; Larchev, Gregory; Bellows, Peter; Schott, Brian

    2004-01-01

    The Reconfigurable Hardware in Orbit (RHinO) project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. These tools leverage an established FPGA design environment and focus primarily on space effects mitigation and power optimization. The project is creating software to automatically test and evaluate the single-event-upsets (SEUs) sensitivities of an FPGA design and insert mitigation techniques. Extensions into the tool suite will also allow evolvable algorithm techniques to reconfigure around single-event-latchup (SEL) events. In the power domain, tools are being created for dynamic power visualiization and optimization. Thus, this technology seeks to enable the use of Reconfigurable Hardware in Orbit, via an integrated design tool-suite aiming to reduce risk, cost, and design time of multimission reconfigurable space processors using SRAM-based FPGAs.

  7. Lab at Home: Hardware Kits for a Digital Design Lab

    ERIC Educational Resources Information Center

    Oliver, J. P.; Haim, F.

    2009-01-01

    An innovative laboratory methodology for an introductory digital design course is presented. Instead of having traditional lab experiences, where students have to come to school classrooms, a "lab at home" concept is proposed. Students perform real experiments in their own homes, using hardware kits specially developed for this purpose. They…

  8. Temporal high-pass non-uniformity correction algorithm based on grayscale mapping and hardware implementation

    NASA Astrophysics Data System (ADS)

    Jin, Minglei; Jin, Weiqi; Li, Yiyang; Li, Shuo

    2015-08-01

    In this paper, we propose a novel scene-based non-uniformity correction algorithm for infrared image processing-temporal high-pass non-uniformity correction algorithm based on grayscale mapping (THP and GM). The main sources of non-uniformity are: (1) detector fabrication inaccuracies; (2) non-linearity and variations in the read-out electronics and (3) optical path effects. The non-uniformity will be reduced by non-uniformity correction (NUC) algorithms. The NUC algorithms are often divided into calibration-based non-uniformity correction (CBNUC) algorithms and scene-based non-uniformity correction (SBNUC) algorithms. As non-uniformity drifts temporally, CBNUC algorithms must be repeated by inserting a uniform radiation source which SBNUC algorithms do not need into the view, so the SBNUC algorithm becomes an essential part of infrared imaging system. The SBNUC algorithms' poor robustness often leads two defects: artifacts and over-correction, meanwhile due to complicated calculation process and large storage consumption, hardware implementation of the SBNUC algorithms is difficult, especially in Field Programmable Gate Array (FPGA) platform. The THP and GM algorithm proposed in this paper can eliminate the non-uniformity without causing defects. The hardware implementation of the algorithm only based on FPGA has two advantages: (1) low resources consumption, and (2) small hardware delay: less than 20 lines, it can be transplanted to a variety of infrared detectors equipped with FPGA image processing module, it can reduce the stripe non-uniformity and the ripple non-uniformity.

  9. Energy Efficient Engine combustor test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Burrus, D. L.; Chahrour, C. A.; Foltz, H. L.; Sabla, P. E.; Seto, S. P.; Taylor, J. R.

    1984-01-01

    The Energy Efficient Engine (E3) Combustor Development effort was conducted as part of the overall NASA/GE E3 Program. This effort included the selection of an advanced double-annular combustion system design. The primary intent was to evolve a design which meets the stringent emissions and life goals of the E3 as well as all of the usual performance requirements of combustion systems for modern turbofan engines. Numerous detailed design studies were conducted to define the features of the combustion system design. Development test hardware was fabricated, and an extensive testing effort was undertaken to evaluate the combustion system subcomponents in order to verify and refine the design. Technology derived from this development effort will be incorporated into the engine combustion system hardware design. This advanced engine combustion system will then be evaluated in component testing to verify the design intent. What is evolving from this development effort is an advanced combustion system capable of satisfying all of the combustion system design objectives and requirements of the E3. Fuel nozzle, diffuser, starting, and emissions design studies are discussed.

  10. Hardware Design of the Energy Efficient Fall Detection Device

    NASA Astrophysics Data System (ADS)

    Skorodumovs, A.; Avots, E.; Hofmanis, J.; Korāts, G.

    2016-04-01

    Health issues for elderly people may lead to different injuries obtained during simple activities of daily living. Potentially the most dangerous are unintentional falls that may be critical or even lethal to some patients due to the heavy injury risk. In the project "Wireless Sensor Systems in Telecare Application for Elderly People", we have developed a robust fall detection algorithm for a wearable wireless sensor. To optimise the algorithm for hardware performance and test it in field, we have designed an accelerometer based wireless fall detector. Our main considerations were: a) functionality - so that the algorithm can be applied to the chosen hardware, and b) power efficiency - so that it can run for a very long time. We have picked and tested the parts, built a prototype, optimised the firmware for lowest consumption, tested the performance and measured the consumption parameters. In this paper, we discuss our design choices and present the results of our work.

  11. Hardware Design Improvements to the Major Constituent Analyzer

    NASA Technical Reports Server (NTRS)

    Combs, Scott; Schwietert, Daniel; Anaya, Marcial; DeWolf, Shannon; Merrill, Dave; Gardner, Ben D.; Thoresen, Souzan; Granahan, John; Belcher, Paul; Matty, Chris

    2011-01-01

    The Major Constituent Analyzer (MCA) onboard the International Space Station (ISS) is designed to monitor the major constituents of the ISS's internal atmosphere. This mass spectrometer based system is an integral part of the Environmental Control and Life Support System (ECLSS) and is a primary tool for the management of ISS atmosphere composition. As a part of NASA Change Request CR10773A, several alterations to the hardware have been made to accommodate improved MCA logistics. First, the ORU 08 verification gas assembly has been modified to allow the verification gas cylinder to be installed on orbit. The verification gas is an essential MCA consumable that requires periodic replenishment. Designing the cylinder for subassembly transport reduces the size and weight of the maintained item for launch. The redesign of the ORU 08 assembly includes a redesigned housing, cylinder mounting apparatus, and pneumatic connection. The second hardware change is a redesigned wiring harness for the ORU 02 analyzer. The ORU 02 electrical connector interface was damaged in a previous on-orbit installation, and this necessitated the development of a temporary fix while a more permanent solution was developed. The new wiring harness design includes flexible cable as well as indexing fasteners and guide-pins, and provides better accessibility during the on-orbit maintenance operation. This presentation will describe the hardware improvements being implemented for MCA as well as the expected improvement to logistics and maintenance.

  12. HSCT Sector Combustor Hardware Modifications for Improved Combustor Design

    NASA Technical Reports Server (NTRS)

    Greenfield, Stuart C.; Heberling, Paul V.; Moertle, George E.

    2005-01-01

    An alternative to the stepped-dome design for the lean premixed prevaporized (LPP) combustor has been developed. The new design uses the same premixer types as the stepped-dome design: integrated mixer flameholder (IMFH) tubes and a cyclone swirler pilot. The IMFH fuel system has been taken to a new level of development. Although the IMFH fuel system design developed in this Task is not intended to be engine-like hardware, it does have certain characteristics of engine hardware, including separate fuel circuits for each of the fuel stages. The four main stage fuel circuits are integrated into a single system which can be withdrawn from the combustor as a unit. Additionally, two new types of liner cooling have been designed. The resulting lean blowout data was found to correlate well with the Lefebvre parameter. As expected, CO and unburned hydrocarbons emissions were shown to have an approximately linear relationship, even though some scatter was present in the data, and the CO versus flame temperature data showed the typical cupped shape. Finally, the NOx emissions data was shown to agree well with a previously developed correlation based on emissions data from Configuration 3 tests performed at GEAE. The design variations of the cyclone swirler pilot that were investigated in this study did not significantly change the NOx emissions from the baseline design (GEAE Configuration 3) at supersonic cruise conditions.

  13. IDEAS and App Development Internship in Hardware and Software Design

    NASA Technical Reports Server (NTRS)

    Alrayes, Rabab D.

    2016-01-01

    In this report, I will discuss the tasks and projects I have completed while working as an electrical engineering intern during the spring semester of 2016 at NASA Kennedy Space Center. In the field of software development, I completed tasks for the G-O Caching Mobile App and the Asbestos Management Information System (AMIS) Web App. The G-O Caching Mobile App was written in HTML, CSS, and JavaScript on the Cordova framework, while the AMIS Web App is written in HTML, CSS, JavaScript, and C# on the AngularJS framework. My goals and objectives on these two projects were to produce an app with an eye-catching and intuitive User Interface (UI), which will attract more employees to participate; to produce a fully-tested, fully functional app which supports workforce engagement and exploration; to produce a fully-tested, fully functional web app that assists technicians working in asbestos management. I also worked in hardware development on the Integrated Display and Environmental Awareness System (IDEAS) wearable technology project. My tasks on this project were focused in PCB design and camera integration. My goals and objectives for this project were to successfully integrate fully functioning custom hardware extenders on the wearable technology headset to minimize the size of hardware on the smart glasses headset for maximum user comfort; to successfully integrate fully functioning camera onto the headset. By the end of this semester, I was able to successfully develop four extender boards to minimize hardware on the headset, and assisted in integrating a fully-functioning camera into the system.

  14. Design-to-fabricate: maker hardware requires maker software.

    PubMed

    Schmidt, Ryan; Ratto, Matt

    2013-01-01

    As a result of consumer-level 3D printers' increasing availability and affordability, the audience for 3D-design tools has grown considerably. However, current tools are ill-suited for these users. They have steep learning curves and don't take into account that the end goal is a physical object, not a digital model. A new class of "maker"-level design tools is needed to accompany this new commodity hardware. However, recent examples of such tools achieve accessibility primarily by constraining functionality. In contrast, the meshmixer project is building tools that provide accessibility and expressive power by leveraging recent computer graphics research in geometry processing. The project members have had positive experiences with several 3D-design-to-print workshops and are exploring several design-to-fabricate problems. This article is part of a special issue on 3D printing. PMID:24808128

  15. Towards improved hardware component attenuation correction in PET/MR hybrid imaging

    NASA Astrophysics Data System (ADS)

    Paulus, D. H.; Tellmann, L.; Quick, H. H.

    2013-11-01

    In positron emission tomography/computed tomography (PET/CT) hybrid imaging attenuation correction (AC) of the patient tissue and patient table is performed by converting the CT-based Hounsfield units (HU) to linear attenuation coefficients (LAC) of PET. When applied to the new field of hardware component AC in PET/magnetic resonance (MR) hybrid imaging, this conversion method may result in local overcorrection of PET activity values. The aim of this study thus was to optimize the conversion parameters for CT-based AC of hardware components in PET/MR. Systematic evaluation and optimization of the HU to LAC conversion parameters has been performed for the hardware component attenuation map (µ-map) of a flexible radiofrequency (RF) coil used in PET/MR imaging. Furthermore, spatial misregistration of this RF coil to its µ-map was simulated by shifting the µ-map in different directions and the effect on PET quantification was evaluated. Measurements of a PET NEMA standard emission phantom were performed on an integrated hybrid PET/MR system. Various CT parameters were used to calculate different µ-maps for the flexible RF coil and to evaluate the impact on the PET activity concentration. A 511 keV transmission scan of the local RF coil was used as standard of reference to adapt the slope of the conversion from HUs to LACs at 511 keV. The average underestimation of the PET activity concentration due to the non-attenuation corrected RF coil in place was calculated to be 5.0% in the overall phantom. When considering attenuation only in the upper volume of the phantom, the average difference to the reference scan without RF coil is 11.0%. When the PET/CT conversion is applied, an average overestimation of 3.1% (without extended CT scale) and 4.2% (with extended CT scale) is observed in the top volume of the NEMA phantom. Using the adapted conversion resulting from this study, the deviation in the top volume of the phantom is reduced to -0.5% and shows the lowest

  16. Health Maintenance System (HMS) Hardware Research, Design, and Collaboration

    NASA Technical Reports Server (NTRS)

    Gonzalez, Stefanie M.

    2010-01-01

    The Space Life Sciences division (SLSD) concentrates on optimizing a crew member's health. Developments are translated into innovative engineering solutions, research growth, and community awareness. This internship incorporates all those areas by targeting various projects. The main project focuses on integrating clinical and biomedical engineering principles to design, develop, and test new medical kits scheduled for launch in the Spring of 2011. Additionally, items will be tagged with Radio Frequency Interference Devices (RFID) to keep track of the inventory. The tags will then be tested to optimize Radio Frequency feed and feed placement. Research growth will occur with ground based experiments designed to measure calcium encrusted deposits in the International Space Station (ISS). The tests will assess the urine calcium levels with Portable Clinical Blood Analyzer (PCBA) technology. If effective then a model for urine calcium will be developed and expanded to microgravity environments. To support collaboration amongst the subdivisions of SLSD the architecture of the Crew Healthcare Systems (CHeCS) SharePoint site has been redesigned for maximum efficiency. Community collaboration has also been established with the University of Southern California, Dept. of Aeronautical Engineering and the Food and Drug Administration (FDA). Hardware disbursements will transpire within these communities to support planetary surface exploration and to serve as an educational tool demonstrating how ground based medicine influenced the technological development of space hardware.

  17. Hardware accelerator design for tracking in smart camera

    NASA Astrophysics Data System (ADS)

    Singh, Sanjay; Dunga, Srinivasa Murali; Saini, Ravi; Mandal, A. S.; Shekhar, Chandra; Vohra, Anil

    2011-10-01

    Smart Cameras are important components in video analysis. For video analysis, smart cameras needs to detect interesting moving objects, track such objects from frame to frame, and perform analysis of object track in real time. Therefore, the use of real-time tracking is prominent in smart cameras. The software implementation of tracking algorithm on a general purpose processor (like PowerPC) could achieve low frame rate far from real-time requirements. This paper presents the SIMD approach based hardware accelerator designed for real-time tracking of objects in a scene. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA. Resulted frame rate is 30 frames per second for 250x200 resolution video in gray scale.

  18. Modular implementation of a digital hardware design automation system

    NASA Astrophysics Data System (ADS)

    Masud, M.

    An automation system based on AHPL (A Hardware Programming Language) was developed. The project may be divided into three distinct phases: (1) Upgrading of AHPL to make it more universally applicable; (2) Implementation of a compiler for the language; and (3) illustration of how the compiler may be used to support several phases of design activities. Several new features were added to AHPL. These include: application-dependent parameters, mutliple clocks, asynchronous results, functional registers and primitive functions. The new language, called Universal AHPL, has been defined rigorously. The compiler design is modular. The parsing is done by an automatic parser generated from the SLR(1)BNF grammar of the language. The compiler produces two data bases from the AHPL description of a circuit. The first one is a tabular representation of the circuit, and the second one is a detailed interconnection linked list. The two data bases provide a means to interface the compiler to application-dependent CAD systems.

  19. Design and test hardware for a solar array switching unit

    NASA Technical Reports Server (NTRS)

    Patil, A. R.; Cho, B. H.; Sable, D.; Lee, F. C.

    1992-01-01

    This paper describes the control of a pulse width modulated (PWM) type sequential shunt switching unit (SSU) for spacecraft applications. It is found that the solar cell output capacitance has a significant impact on SSU design. Shorting of this cell capacitance by the PWM switch causes input current surges. These surges are minimized by the use of a series filter inductor. The system with a filter is analyzed for ripple and the control to output-voltage transfer function. Stable closed loop design considerations are discussed. The results are supported by modeling and measurements of loop gain and of closed-loop bus impedance on test hardware for NASA's 120 V Earth Observation System (EOS). The analysis and modeling are also applicable to NASA's 160 V Space Station power system.

  20. Process of videotape making: presentation design, software, and hardware

    NASA Astrophysics Data System (ADS)

    Dickinson, Robert R.; Brady, Dan R.; Bennison, Tim; Burns, Thomas; Pines, Sheldon

    1991-06-01

    The use of technical video tape presentations for communicating abstractions of complex data is now becoming commonplace. While the use of video tapes in the day-to-day work of scientists and engineers is still in its infancy, their use as applications oriented conferences is now growing rapidly. Despite these advancements, there is still very little that is written down about the process of making technical videotapes. For printed media, different presentation styles are well known for categories such as results reports, executive summary reports, and technical papers and articles. In this paper, the authors present ideas on the topic of technical videotape presentation design in a format that is worth referring to. They have started to document the ways in which the experience of media specialist, teaching professionals, and character animators can be applied to scientific animation. Software and hardware considerations are also discussed. For this portion, distinctions are drawn between the software and hardware required for computer animation (frame at a time) productions, and live recorded interaction with a computer graphics display.

  1. Design time optimization for hardware watermarking protection of HDL designs.

    PubMed

    Castillo, E; Morales, D P; García, A; Parrilla, L; Todorovich, E; Meyer-Baese, U

    2015-01-01

    HDL-level design offers important advantages for the application of watermarking to IP cores, but its complexity also requires tools automating these watermarking algorithms. A new tool for signature distribution through combinational logic is proposed in this work. IPP@HDL, a previously proposed high-level watermarking technique, has been employed for evaluating the tool. IPP@HDL relies on spreading the bits of a digital signature at the HDL design level using combinational logic included within the original system. The development of this new tool for the signature distribution has not only extended and eased the applicability of this IPP technique, but it has also improved the signature hosting process itself. Three algorithms were studied in order to develop this automated tool. The selection of a cost function determines the best hosting solutions in terms of area and performance penalties on the IP core to protect. An 1D-DWT core and MD5 and SHA1 digital signatures were used in order to illustrate the benefits of the new tool and its optimization related to the extraction logic resources. Among the proposed algorithms, the alternative based on simulated annealing reduces the additional resources while maintaining an acceptable computation time and also saving designer effort and time. PMID:25861681

  2. Design Time Optimization for Hardware Watermarking Protection of HDL Designs

    PubMed Central

    Castillo, E.; Morales, D. P.; García, A.; Parrilla, L.; Todorovich, E.; Meyer-Baese, U.

    2015-01-01

    HDL-level design offers important advantages for the application of watermarking to IP cores, but its complexity also requires tools automating these watermarking algorithms. A new tool for signature distribution through combinational logic is proposed in this work. IPP@HDL, a previously proposed high-level watermarking technique, has been employed for evaluating the tool. IPP@HDL relies on spreading the bits of a digital signature at the HDL design level using combinational logic included within the original system. The development of this new tool for the signature distribution has not only extended and eased the applicability of this IPP technique, but it has also improved the signature hosting process itself. Three algorithms were studied in order to develop this automated tool. The selection of a cost function determines the best hosting solutions in terms of area and performance penalties on the IP core to protect. An 1D-DWT core and MD5 and SHA1 digital signatures were used in order to illustrate the benefits of the new tool and its optimization related to the extraction logic resources. Among the proposed algorithms, the alternative based on simulated annealing reduces the additional resources while maintaining an acceptable computation time and also saving designer effort and time. PMID:25861681

  3. INO340 telescope control system: hardware design and development

    NASA Astrophysics Data System (ADS)

    Jafarzadeh, Asghar; Ravanmehr, Reza

    2014-07-01

    In order to meet high image quality requirements of the INO340 telescope, one of the significant issues is the design and development of the Telescope Control System (TCS) architecture. The architecture of TCS is designed based on distributed control system configuration, which consists of four major subsystems: Telescope Control System supervisor (TCSS), Dome Control System (DCS), Mount Control System (MCS), and Active Optic System (AOS). Another system which plays important role in the hardware architecture is Interlock System (ILS), which is responsible for safety of staff, telescope and data. ILS architecture is also designed, using distributed system method based on the fail-safe PLCs. All subsystems of TCS are designed with an adequate safety subsystem, which are responsible for the safety of the subsystem and communicates through reliable lines with the main controller, placed in control room. In this paper, we explain the innovative architecture of Telescope Control System together with Interlock System and in brief show the interface control issues between different subsystems.

  4. Hardware synthesis from DDL. [Digital Design Language for computer aided design and test of LSI

    NASA Technical Reports Server (NTRS)

    Shah, A. M.; Shiva, S. G.

    1981-01-01

    The details of the digital systems can be conveniently input into the design automation system by means of Hardware Description Languages (HDL). The Computer Aided Design and Test (CADAT) system at NASA MSFC is used for the LSI design. The Digital Design Language (DDL) has been selected as HDL for the CADAT System. DDL translator output can be used for the hardware implementation of the digital design. This paper addresses problems of selecting the standard cells from the CADAT standard cell library to realize the logic implied by the DDL description of the system.

  5. Hardware design and implementation of the closed-orbit feedback system at APS

    SciTech Connect

    Barr, D.; Chung, Youngjoo

    1996-10-01

    The Advanced Photon Source (APS) storage ring will utilize a closed-orbit feedback system in order to produce a more stable beam. The specified orbit measurement resolution is 25 microns for global feedback and 1 micron for local feedback. The system will sample at 4 kHz and provide a correction bandwidth of 100 Hz. At this bandwidth, standard rf BPMs will provide a resolution of 0.7 micron, while specialized miniature BPMs positioned on either side of the insertion devices for local feedback will provide a resolution of 0.2 micron (1). The measured BPM noise floor for standard BPMs is 0.06 micron per root hertz mA. Such a system has been designed, simulated, and tested on a small scale (2). This paper covers the actual hardware design and layout of the entire closed-loop system. This includes commercial hardware components, in addition to many components designed and built in-house. The paper will investigate the large-scale workings of all these devices, as well as an overall view of each piece of hardware used.

  6. Towards improved hardware component attenuation correction in PET/MR hybrid imaging.

    PubMed

    Paulus, D H; Tellmann, L; Quick, H H

    2013-11-21

    In positron emission tomography/computed tomography (PET/CT) hybrid imaging attenuation correction (AC) of the patient tissue and patient table is performed by converting the CT-based Hounsfield units (HU) to linear attenuation coefficients (LAC) of PET. When applied to the new field of hardware component AC in PET/magnetic resonance (MR) hybrid imaging, this conversion method may result in local overcorrection of PET activity values. The aim of this study thus was to optimize the conversion parameters for CT-based AC of hardware components in PET/MR. Systematic evaluation and optimization of the HU to LAC conversion parameters has been performed for the hardware component attenuation map (µ-map) of a flexible radiofrequency (RF) coil used in PET/MR imaging. Furthermore, spatial misregistration of this RF coil to its µ-map was simulated by shifting the µ-map in different directions and the effect on PET quantification was evaluated. Measurements of a PET NEMA standard emission phantom were performed on an integrated hybrid PET/MR system. Various CT parameters were used to calculate different µ-maps for the flexible RF coil and to evaluate the impact on the PET activity concentration. A 511 keV transmission scan of the local RF coil was used as standard of reference to adapt the slope of the conversion from HUs to LACs at 511 keV. The average underestimation of the PET activity concentration due to the non-attenuation corrected RF coil in place was calculated to be 5.0% in the overall phantom. When considering attenuation only in the upper volume of the phantom, the average difference to the reference scan without RF coil is 11.0%. When the PET/CT conversion is applied, an average overestimation of 3.1% (without extended CT scale) and 4.2% (with extended CT scale) is observed in the top volume of the NEMA phantom. Using the adapted conversion resulting from this study, the deviation in the top volume of the phantom is reduced to -0.5% and shows the lowest

  7. Scalability, Timing, and System Design Issues for Intrinsic Evolvable Hardware

    NASA Technical Reports Server (NTRS)

    Hereford, James; Gwaltney, David

    2004-01-01

    In this paper we address several issues pertinent to intrinsic evolvable hardware (EHW). The first issue is scalability; namely, how the design space scales as the programming string for the programmable device gets longer. We develop a model for population size and the number of generations as a function of the programming string length, L, and show that the number of circuit evaluations is an O(L2) process. We compare our model to several successful intrinsic EHW experiments and discuss the many implications of our model. The second issue that we address is the timing of intrinsic EHW experiments. We show that the processing time is a small part of the overall time to derive or evolve a circuit and that major improvements in processor speed alone will have only a minimal impact on improving the scalability of intrinsic EHW. The third issue we consider is the system-level design of intrinsic EHW experiments. We review what other researchers have done to break the scalability barrier and contend that the type of reconfigurable platform and the evolutionary algorithm are tied together and impose limits on each other.

  8. Hardware design of a spherical mini-rover

    NASA Technical Reports Server (NTRS)

    Tarlton, John

    1992-01-01

    In this hardware project the students designed the prototype of a novel mini-rover for the exploration of a planetary surface. In an actual application, a large number of such miniature roving devices would be released from a landing craft. Each rover would be equipped with a Cd 109 radio-isotope source (a gamma ray emitter) irradiating the planetary surface below the rover, and an x-ray fluorescence detector for a quantitative assay of high atomic weight elements in the planet's surface. (Similar, miniaturized, hand-held devices have recently been developed for use in gold mines). The device developed by the students was limited to demonstrating the mechanical and electrical drive. The geometric external shape is a sphere; hence there is no danger of the rover being turned on its back and stopped. Propulsion is by means of an interior mass, eccentric to the sphere and driven by an electric motor. In an inter-disciplinary effort in mechanical and electrical engineering, the students designed the mechanical parts, built the transistorized circuit board, and tested the device.

  9. Simplified method for the hardware implementation of nonuniformity correction on a resistor-array infrared scene projector

    NASA Astrophysics Data System (ADS)

    Jones, Lawrence E.; Olson, Eric M.; Murrer, Robert Lee, Jr.; Andrews, Allen R.

    1997-07-01

    Ever increasing developments in imaging infrared (IR) seekers that are being designed for Ballistic Missile Defense Office guided interceptor programs have amplified the necessity for robust hardware-in-the-loop (HWIL) testing to reduce program risk. Successful IR HWIL testing requires a high fidelity spatial, spectral, and temporal IR projector. Recent characterization measurements of a 512 X 512 metal-oxide semiconductor field-effect transistor (MOSFET) resistor array show that resistor array technology is a leading contender for the IR projector. As with any array device, nonuniform performance between individual elements of the array is a concern. This paper addresses a simplified approach to accomplishing the nonuniformity correction of a resistor array in real-time. The first step in this process is to obtain a nominal output curve typical of the resistors' MOSFET output. The key feature of this simplified process is that all output curves specific to individual resistors can be related to this typical curve with a simple gain and offset correction. In practice, the inverse of the typical output curve is stored in a look-up table in order to obtain the required command for a desired output and then a correcting gain and offset are applied. Results from this process show great promise.

  10. Energy efficient engine: Fan test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Sullivan, T. J.

    1980-01-01

    A single stage fan and quarter stage booster were designed for the energy efficient engine. The fan has an inlet radius ratio of 0.342 and a specific flow rate of 208.9 Kg/S sq m (42.8 lbm/sec sq ft). The fan rotor has 32 medium aspect ratio (2.597) titanium blades with a partspan shroud at 55% blade height. The design corrected fan tip speed is 411.5 M/S (1350 ft/sec). The quarter stage island splits the total fan flow with approximately 22% of the flow being supercharged by the quarter stage rotor. The fan bypass ratio is 6.8. The core flow total pressure ratio is 1.67 and the fan bypass pressure ratio is 1.65. The design details of the fan and booster blading, and the fan frame and static structure for the fan configuration are presented.

  11. [Design of an FPGA-based image guided surgery hardware platform].

    PubMed

    Zou, Fa-Dong; Qin, Bin-Jie

    2008-07-01

    An FPGA-Based Image Guided Surgery Hardware Platform has been designed and implemented in this paper. The hardware platform can provide hardware acceleration for image guided surgery. It is completed with a video decoder interface, a DDR memory controller, a 12C bus controller, an interrupt controller and so on. It is able to perform real time video endoscopy image capturing in the surgery and to preserve the hardware interface for image guided surgery algorithm module. PMID:18973036

  12. Hardware architecture design of a fast global motion estimation method

    NASA Astrophysics Data System (ADS)

    Liang, Chaobing; Sang, Hongshi; Shen, Xubang

    2015-12-01

    VLSI implementation of gradient-based global motion estimation (GME) faces two main challenges: irregular data access and high off-chip memory bandwidth requirement. We previously proposed a fast GME method that reduces computational complexity by choosing certain number of small patches containing corners and using them in a gradient-based framework. A hardware architecture is designed to implement this method and further reduce off-chip memory bandwidth requirement. On-chip memories are used to store coordinates of the corners and template patches, while the Gaussian pyramids of both the template and reference frame are stored in off-chip SDRAMs. By performing geometric transform only on the coordinates of the center pixel of a 3-by-3 patch in the template image, a 5-by-5 area containing the warped 3-by-3 patch in the reference image is extracted from the SDRAMs by burst read. Patched-based and burst mode data access helps to keep the off-chip memory bandwidth requirement at the minimum. Although patch size varies at different pyramid level, all patches are processed in term of 3x3 patches, so the utilization of the patch-processing circuit reaches 100%. FPGA implementation results show that the design utilizes 24,080 bits on-chip memory and for a sequence with resolution of 352x288 and frequency of 60Hz, the off-chip bandwidth requirement is only 3.96Mbyte/s, compared with 243.84Mbyte/s of the original gradient-based GME method. This design can be used in applications like video codec, video stabilization, and super-resolution, where real-time GME is a necessity and minimum memory bandwidth requirement is appreciated.

  13. Electronic hardware design of electrical capacitance tomography systems.

    PubMed

    Saied, I; Meribout, M

    2016-06-28

    Electrical tomography techniques for process imaging are very prominent for industrial applications, such as the oil and gas industry and chemical refineries, owing to their ability to provide the flow regime of a flowing fluid within a relatively high throughput. Among the various techniques, electrical capacitance tomography (ECT) is gaining popularity due to its non-invasive nature and its capability to differentiate between different phases based on their permittivity distribution. In recent years, several hardware designs have been provided for ECT systems that have improved its resolution of measurements to be around attofarads (aF, 10(-18) F), or the number of channels, that is required to be large for some applications that require a significant amount of data. In terms of image acquisition time, some recent systems could achieve a throughput of a few hundred frames per second, while data processing time could be achieved in only a few milliseconds per frame. This paper outlines the concept and main features of the most recent front-end and back-end electronic circuits dedicated for ECT systems. In this paper, multiple-excitation capacitance polling, a front-end electronic technique, shows promising results for ECT systems to acquire fast data acquisition speeds. A highly parallel field-programmable gate array (FPGA) based architecture for a fast reconstruction algorithm is also described. This article is part of the themed issue 'Supersensing through industrial process tomography'. PMID:27185964

  14. Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques

    PubMed Central

    Rincon, Fernando; Vaderrama, Carlos; Villanueva, Felix; Caba, Julian; Lopez, Juan Carlos

    2014-01-01

    In FPGA-based control system design, partial reconfiguration is especially well suited to implement preemptive systems. In real-time systems, the deadline for critical task can compel the preemption of noncritical one. Besides, an asynchronous event can demand immediate attention and, then, force launching a reconfiguration process for high-priority task implementation. If the asynchronous event is previously scheduled, an explicit activation of the reconfiguration process is performed. If the event cannot be previously programmed, such as in dynamically scheduled systems, an implicit activation to the reconfiguration process is demanded. This paper provides a hardware-based approach to explicit and implicit activation of the partial reconfiguration process in dynamically reconfigurable SoCs and includes all the necessary tasks to cope with this issue. Furthermore, the reconfiguration service introduced in this work allows remote invocation of the reconfiguration process and then the remote integration of off-chip components. A model that offers component location transparency is also presented to enhance and facilitate system integration. PMID:24672292

  15. RF control hardware design for CYCIAE-100 cyclotron

    NASA Astrophysics Data System (ADS)

    Yin, Zhiguo; Fu, Xiaoliang; Ji, Bin; Zhao, Zhenlu; Zhang, Tianjue; Li, Pengzhan; Wei, Junyi; Xing, Jiansheng; Wang, Chuan

    2015-11-01

    The Beijing Radioactive Ion-beam Facility project is being constructed by BRIF division of China Institute of Atomic Energy. In this project, a 100 MeV high intensity compact proton cyclotron is built for multiple applications. The first successful beam extraction of CYCIAE-100 cyclotron was done in the middle of 2014. The extracted proton beam energy is 100 MeV and the beam current is more than 20 μA. The RF system of the CYCIAE-100 cyclotron includes two half-wavelength cavities, two 100 kW tetrode amplifiers and power transmission line systems (all above are independent from each other) and two sets of Low Level RF control crates. Each set of LLRF control includes an amplitude control unit, a tuning control unit, a phase control unit, a local Digital Signal Process control unit and an Advanced RISC Machines based EPICS IOC unit. These two identical LLRF control crates share one common reference clock and take advantages of modern digital technologies (e.g. DSP and Direct Digital Synthesizer) to achieve closed loop voltage and phase regulations of the dee-voltage. In the beam commission, the measured dee-voltage stability of RF system is better than 0.1% and phase stability is better than 0.03°. The hardware design of the LLRF system will be reviewed in this paper.

  16. Design of Test Support Hardware for Advanced Space Suits

    NASA Technical Reports Server (NTRS)

    Watters, Jeffrey A.; Rhodes, Richard

    2013-01-01

    As a member of the Space Suit Assembly Development Engineering Team, I designed and built test equipment systems to support the development of the next generation of advanced space suits. During space suit testing it is critical to supply the subject with two functions: (1) cooling to remove metabolic heat, and (2) breathing air to pressurize the space suit. The objective of my first project was to design, build, and certify an improved Space Suit Cooling System for manned testing in a 1-G environment. This design had to be portable and supply a minimum cooling rate of 2500 BTU/hr. The Space Suit Cooling System is a robust, portable system that supports very high metabolic rates. It has a highly adjustable cool rate and is equipped with digital instrumentation to monitor the flowrate and critical temperatures. It can supply a variable water temperature down to 34 deg., and it can generate a maximum water flowrate of 2.5 LPM. My next project was to design and build a Breathing Air System that was capable of supply facility air to subjects wearing the Z-2 space suit. The system intakes 150 PSIG breathing air and regulates it to two operating pressures: 4.3 and 8.3 PSIG. It can also provide structural capabilities at 1.5x operating pressure: 6.6 and 13.2 PSIG, respectively. It has instrumentation to monitor flowrate, as well as inlet and outlet pressures. The system has a series of relief valves to fully protect itself in case of regulator failure. Both projects followed a similar design methodology. The first task was to perform research on existing concepts to develop a sufficient background knowledge. Then mathematical models were developed to size components and simulate system performance. Next, mechanical and electrical schematics were generated and presented at Design Reviews. After the systems were approved by the suit team, all the hardware components were specified and procured. The systems were then packaged, fabricated, and thoroughly tested. The next step

  17. Hardware Evolution of Closed-Loop Controller Designs

    NASA Technical Reports Server (NTRS)

    Gwaltney, David; Ferguson, Ian

    2002-01-01

    Poster presentation will outline on-going efforts at NASA, MSFC to employ various Evolvable Hardware experimental platforms in the evolution of digital and analog circuitry for application to automatic control. Included will be information concerning the application of commercially available hardware and software along with the use of the JPL developed FPTA2 integrated circuit and supporting JPL developed software. Results to date will be presented.

  18. Hardware-software partitioning for the design of system on chip by neural network optimization method

    NASA Astrophysics Data System (ADS)

    Pan, Zhongliang; Li, Wei; Shao, Qingyi; Chen, Ling

    2011-12-01

    In the design procedure of system on chip (SoC), it is needed to make use of hardware-software co-design technique owing to the great complexity of SoC. One of main steps in hardware-software co-design is how to carry out the partitioning of a system into hardware and software components. The efficient approaches for hardware-software partitioning can achieve good system performance, which is superior to the techniques that use software only or use hardware only. In this paper, a method based on neural networks is presented for the hardware-software partitioning of system on chip. The discrete Hopfield neural networks corresponding to the problem of hardware-software partitioning is built, the states of neural neurons are able to represent whether the required components or functionalities are to be implemented in hardware or software. An algorithm based on the principle of simulated annealing is designed, which can be used to compute the minimal energy states of neural networks, therefore the optimal partitioning schemes are obtained. The experimental results show that the hardware-software partitioning method proposed in this paper can obtain the near optimal partitioning for a lot of example circuits.

  19. Pyroshock Simulation Systems: Are We Correctly Qualifying Flight Hardware for Pyroshock Environments?

    NASA Technical Reports Server (NTRS)

    Kolaini, Ali R.; Nayeri, Reza; Kern, Dennis L.

    2009-01-01

    There are several methods of shock testing that are commonly used by the aerospace industry to qualify flight hardware to pyroshock environments. In some cases the shock results and in particular the shock response spectra computed from these tests were interpreted in such a way as to satisfy the testing requirements and were often considered successful for flight hardware qualification. However, close scrutiny of these acquired shock data suggest gross violation of the pyroshock qualification requirements. There are several issues, both in terms of the shock generation mechanisms and the shock signature acquisition and analysis that have led to improper qualification of flight hardware. In this paper some factors contributing to the misinterpretation of the shock data are reviewed. First, issues with the hardware fixturing and instrumentation that may lead to incorrect shock testing are discussed. Second, issues facing the shock simulation systems and pyrotechnic testing are reviewed. Finally, issues pertaining to the data acquisition and analysis are briefly discussed.

  20. Interim Service ISDN Satellite (ISIS) hardware experiment design for advanced ISDN satellite design and experiments

    NASA Technical Reports Server (NTRS)

    Pepin, Gerard R.

    1992-01-01

    The Interim Service Integrated Services Digital Network (ISDN) Satellite (ISIS) Hardware Experiment Design for Advanced Satellite Designs describes the design of the ISDN Satellite Terminal Adapter (ISTA) capable of translating ISDN protocol traffic into time division multiple access (TDMA) signals for use by a communications satellite. The ISTA connects the Type 1 Network Termination (NT1) via the U-interface on the line termination side of the CPE to the V.35 interface for satellite uplink. The same ISTA converts in the opposite direction the V.35 to U-interface data with a simple switch setting.

  1. Functional design specification for Stowage List And Hardware Tracking System (SLAHTS). [space shuttles

    NASA Technical Reports Server (NTRS)

    Keltner, D. J.

    1975-01-01

    This functional design specification defines the total systems approach to meeting the requirements stated in the Detailed Requirements Document for Stowage List and Hardware Tracking System for the space shuttle program. The stowage list and hardware tracking system is identified at the system and subsystem level with each subsystem defined as a function of the total system.

  2. Design of digital hardware system for pulse signals.

    PubMed

    Lee, J; Kim, J; Lee, M

    2001-12-01

    In this study, we have developed the digital hardware system which performs signal processing necessary for the filtering to eliminate noises by inputting pulse wave signals from the sensor group. With a view to obtain clinically effective information, we analyzed structural elements of pulse waveform and, thus, conducted a systematic classification. What is more, we performed the modeling of the digital filter by using the Steiglitz-McBride iteration method in order to get the same results with output signals coming out of an galvanometer of analog type of existing Pulse diagnosis system with input signals entering into galvanometer and coming out of the amp group of the Pulse diagnosis system. PMID:11708398

  3. Cognon Neural Model Software Verification and Hardware Implementation Design

    NASA Astrophysics Data System (ADS)

    Haro Negre, Pau

    Little is known yet about how the brain can recognize arbitrary sensory patterns within milliseconds using neural spikes to communicate information between neurons. In a typical brain there are several layers of neurons, with each neuron axon connecting to ˜104 synapses of neurons in an adjacent layer. The information necessary for cognition is contained in theses synapses, which strengthen during the learning phase in response to newly presented spike patterns. Continuing on the model proposed in "Models for Neural Spike Computation and Cognition" by David H. Staelin and Carl H. Staelin, this study seeks to understand cognition from an information theoretic perspective and develop potential models for artificial implementation of cognition based on neuronal models. To do so we focus on the mathematical properties and limitations of spike-based cognition consistent with existing neurological observations. We validate the cognon model through software simulation and develop concepts for an optical hardware implementation of a network of artificial neural cognons.

  4. Verifying the "correctness" of your optical proximity correction designs

    NASA Astrophysics Data System (ADS)

    Malhotra, Vinod K.; Chang, Fang C.

    1999-07-01

    The emerging demand for smaller and smaller IC features, undiminished by the delay of next generation stepper technologies, has increased the need for OPC and PSM designs that are becoming critical for leading-edge IC manufacturing. However, modifications made to the original layout by OPC or PSM deign tools in general, exclude the use of conventional design verification tools to verify the modified designs. Therefore, the question of design 'correctness' often goes unanswered until after the wafers have been printed. This is extremely costly in terms of time and money. In this paper, we address the critical issue that has thus far remained open, the development of methods for physical verification of OPC designs. Our approach uses fast lithography simulation to map the modified mask design to the final patterns produced on the wafer. The simulated wafer pattern is matched against the specified tolerances and the problem areas are reported. It is a hierarchical verification tool. The hierarchical processing of the data makes it a high performance tool and keeps the data volume in check. We validate this technology by comparing the simulation results with the experimental data. In addition, performance measurements indicate that it is an effective and practical solution to the problem of verifying correctness of full-chip OPC designs.

  5. Biomolecular Design of an Integrated Software and Hardware System for Cryptography

    NASA Astrophysics Data System (ADS)

    Hirabayashi, Miki; Kojima, Hiroaki; Oiwa, Kazuhiro

    In the DNA-based molecular computation, calculation procedures described by the hardware design can provide an effective physical random source for the theoretically unbreakable encryption system. To realize its practical application, we present a new information processing idea.

  6. Intrinsic Hardware Evolution for the Design and Reconfiguration of Analog Speed Controllers for a DC Motor

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; Ferguson, Michael I.

    2003-01-01

    Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a second generation Field Programmable Transistor Array (FPTA2). The performance of an evolved controller is compared to that of a conventional proportional-integral (PI) controller. It is shown that hardware evolution is able to create a compact design that provides good performance, while using considerably less functional electronic components than the conventional design. Additionally, the use of hardware evolution to provide fault tolerance by reconfiguring the design is explored. Experimental results are presented showing that significant recovery of capability can be made in the face of damaging induced faults.

  7. Energy efficient engine low-pressure compressor component test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Michael, C. J.; Halle, J. E.

    1981-01-01

    The aerodynamic and mechanical design description of the low pressure compressor component of the Energy Efficient Engine were used. The component was designed to meet the requirements of the Flight Propulsion System while maintaining a low cost approach in providing a low pressure compressor design for the Integrated Core/Low Spool test required in the Energy Efficient Engine Program. The resulting low pressure compressor component design meets or exceeds all design goals with the exception of surge margin. In addition, the expense of hardware fabrication for the Integrated Core/Low Spool test has been minimized through the use of existing minor part hardware.

  8. Multiple IMU system hardware interface design, volume 2

    NASA Technical Reports Server (NTRS)

    Landey, M.; Brown, D.

    1975-01-01

    The design of each system component is described. Emphasis is placed on functional requirements unique in this system, including data bus communication, data bus transmitters and receivers, and ternary-to-binary torquing decision logic. Mechanization drawings are presented.

  9. Savannah River Site reactor hardware design modification study

    SciTech Connect

    Fisher, J.E.

    1990-03-01

    A study was undertaken to assess the merits of proposed design modifications to the SRS reactors. The evaluation was based on the responses calculated by the RELAP5 systems code to double-ended guillotine break loss-of-coolant-accidents (DEGB LOCAs). The three concepts evaluated were (a) elevated plenum inlet piping with a guard vessel and clamshell enclosures, (b) closure of both rotovalves in the affected loop, and (c) closure of the pump suction valve in the affected loop. Each concept included a fast reactor shutdown (to 65% power in 100 ms) and a 2-s ac pump trip. For the elevated piping design, system recovery was predicted for breaks in the plenum inlet or pump suction piping; response to the pump discharge break location did not show improvement compared to the present system configuration. The rotovalve closure design improved system response to plenum inlet or pump discharge breaks; recovery was not predicted for pump suction breaks. The pump suction valve closure design demonstrated system recovery for all break locations downstream of the valve. A combination of features is recommended to ensure liquid inventory recovery for all break locations. The elevated piping design performance during pump discharge breaks would be improved with addition of a dc pump trip in the affected loop. Valve closure design performance for a break location in the short section of piping between the reactor concrete shield and the pump suction valve would benefit from the clamshell enclosing that section of piping. 12 refs., 10 figs., 2 tabs.

  10. Hardware design document for the Infrasound Prototype for a CTBT IMS station

    SciTech Connect

    Breding, D.R.; Kromer, R.P.; Whitaker, R.W.; Sandoval, T.

    1997-11-01

    The Hardware Design Document (HDD) describes the various hardware components used in the Comprehensive Test Ban Treaty (CTBT) Infrasound Prototype and their interrelationships. It divides the infrasound prototype into hardware configurations items (HWCIs). The HDD uses techniques such as block diagrams and parts lists to present this information. The level of detail provided in the following sections should be sufficient to allow potential users to procure and install the infrasound system. Infrasonic monitoring is a low cost, robust, and effective technology for detecting atmospheric explosions. Low frequencies from explosion signals propagate to long ranges (few thousand kilometers) where they can be detected with an array of sensors.

  11. Hardware removal - extremity

    MedlinePlus

    Surgeons use hardware such as pins, plates, or screws to help fix a broken bone or to correct an abnormality in ... of pain or other problems related to the hardware, you may have surgery to remove the hardware. ...

  12. Energy efficient engine combustor test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Zeisser, M. H.; Greene, W.; Dubiel, D. J.

    1982-01-01

    The combustor for the Energy Efficient Engine is an annular, two-zone component. As designed, it either meets or exceeds all program goals for performance, safety, durability, and emissions, with the exception of oxides of nitrogen. When compared to the configuration investigated under the NASA-sponsored Experimental Clean Combustor Program, which was used as a basis for design, the Energy Efficient Engine combustor component has several technology advancements. The prediffuser section is designed with short, strutless, curved-walls to provide a uniform inlet airflow profile. Emissions control is achieved by a two-zone combustor that utilizes two types of fuel injectors to improve fuel atomization for more complete combustion. The combustor liners are a segmented configuration to meet the durability requirements at the high combustor operating pressures and temperatures. Liner cooling is accomplished with a counter-parallel FINWALL technique, which provides more effective heat transfer with less coolant.

  13. Hardware acceleration of a Monte Carlo simulation for photodynamic therapy [corrected] treatment planning.

    PubMed

    Lo, William Chun Yip; Redmond, Keith; Luu, Jason; Chow, Paul; Rose, Jonathan; Lilge, Lothar

    2009-01-01

    Monte Carlo (MC) simulations are being used extensively in the field of medical biophysics, particularly for modeling light propagation in tissues. The high computation time for MC limits its use to solving only the forward solutions for a given source geometry, emission profile, and optical interaction coefficients of the tissue. However, applications such as photodynamic therapy treatment planning or image reconstruction in diffuse optical tomography require solving the inverse problem given a desired dose distribution or absorber distribution, respectively. A faster means for performing MC simulations would enable the use of MC-based models for accomplishing such tasks. To explore this possibility, a digital hardware implementation of a MC simulation based on the Monte Carlo for Multi-Layered media (MCML) software was implemented on a development platform with multiple field-programmable gate arrays (FPGAs). The hardware performed the MC simulation on average 80 times faster and was 45 times more energy efficient than the MCML software executed on a 3-GHz Intel Xeon processor. The resulting isofluence lines closely matched those produced by MCML in software, diverging by only less than 0.1 mm for fluence levels as low as 0.00001 cm(-2) in a skin model. PMID:19256707

  14. Performance/price estimates for cortex-scale hardware: a design space exploration.

    PubMed

    Zaveri, Mazad S; Hammerstrom, Dan

    2011-04-01

    In this paper, we revisit the concept of virtualization. Virtualization is useful for understanding and investigating the performance/price and other trade-offs related to the hardware design space. Moreover, it is perhaps the most important aspect of a hardware design space exploration. Such a design space exploration is a necessary part of the study of hardware architectures for large-scale computational models for intelligent computing, including AI, Bayesian, bio-inspired and neural models. A methodical exploration is needed to identify potentially interesting regions in the design space, and to assess the relative performance/price points of these implementations. As an example, in this paper we investigate the performance/price of (digital and mixed-signal) CMOS and hypothetical CMOL (nanogrid) technology based hardware implementations of human cortex-scale spiking neural systems. Through this analysis, and the resulting performance/price points, we demonstrate, in general, the importance of virtualization, and of doing these kinds of design space explorations. The specific results suggest that hybrid nanotechnology such as CMOL is a promising candidate to implement very large-scale spiking neural systems, providing a more efficient utilization of the density and storage benefits of emerging nano-scale technologies. In general, we believe that the study of such hypothetical designs/architectures will guide the neuromorphic hardware community towards building large-scale systems, and help guide research trends in intelligent computing, and computer engineering. PMID:21232918

  15. Hardware Design and Testing of SUPERball, A Modular Tensegrity Robot

    NASA Technical Reports Server (NTRS)

    Sabelhaus, Andrew P.; Bruce, Jonathan; Caluwaerts, Ken; Chen, Yangxin; Lu, Dizhou; Liu, Yuejia; Agogino, Adrian K.; SunSpiral, Vytas; Agogino, Alice M.

    2014-01-01

    We are developing a system of modular, autonomous "tensegrity end-caps" to enable the rapid exploration of untethered tensegrity robot morphologies and functions. By adopting a self-contained modular approach, different end-caps with various capabilities (such as peak torques, or motor speeds), can be easily combined into new tensegrity robots composed of rods, cables, and actuators of different scale (such as in length, mass, peak loads, etc). As a first step in developing this concept, we are in the process of designing and testing the end-caps for SUPERball (Spherical Underactuated Planetary Exploration Robot), a project at the Dynamic Tensegrity Robotics Lab (DTRL) within NASA Ames's Intelligent Robotics Group. This work discusses the evolving design concepts and test results that have gone into the structural, mechanical, and sensing aspects of SUPERball. This representative tensegrity end-cap design supports robust and repeatable untethered mobility tests of the SUPERball, while providing high force, high displacement actuation, with a low-friction, compliant cabling system.

  16. Savannah River Site reactor hardware design modification study

    SciTech Connect

    Fisher, J.E.

    1990-01-01

    A study was undertaken to assess the merits of proposed design modifications to the Savannah River Site (SRS) reactors. The evaluation was based on the responses calculated by the RELAP5 systems code to double-ended guillotine break loss-of-coolant-accidents (DEGB LOCAs). The three concepts evaluated were (a) elevated plenum inlet piping with a guard vessel and clamshell enclosures, (b) closure of both rotovalves in the affected loop, and (c) closure of the pump suction valve in the affected loop. Each concept included a fast reactor shutdown (to 65% power in 100 ms) and a 2-s ac pump trip. System recovery potential was evaluated for break locations at the pump suction, the pump discharge, and the plenum inlet. The code version used was RELAP5/MOD2.5 version 3d3, a preliminary version of RELAP5/MOD3. The model was a three-dimensional representation of the K-Reactor water plenum and moderator tank. It included explicit representations of all six loops, which were based on the configuration of L-Reactor. A combination of features is recommended to ensure liquid inventory recovery for all break locations. Valve closure design performance for a break location in the short section of piping between the reactor concrete shield and the pump suction valve would benefit from the clamshell enclosing that section of piping. 7 refs., 10 figs., 2 tabs.

  17. Internet-based hardware/software co-design framework for embedded 3D graphics applications

    NASA Astrophysics Data System (ADS)

    Yeh, Chi-Tsai; Wang, Chun-Hao; Huang, Ing-Jer; Wong, Weng-Fai

    2011-12-01

    Advances in technology are making it possible to run three-dimensional (3D) graphics applications on embedded and handheld devices. In this article, we propose a hardware/software co-design environment for 3D graphics application development that includes the 3D graphics software, OpenGL ES application programming interface (API), device driver, and 3D graphics hardware simulators. We developed a 3D graphics system-on-a-chip (SoC) accelerator using transaction-level modeling (TLM). This gives software designers early access to the hardware even before it is ready. On the other hand, hardware designers also stand to gain from the more complex test benches made available in the software for verification. A unique aspect of our framework is that it allows hardware and software designers from geographically dispersed areas to cooperate and work on the same framework. Designs can be entered and executed from anywhere in the world without full access to the entire framework, which may include proprietary components. This results in controlled and secure transparency and reproducibility, granting leveled access to users of various roles.

  18. An FPGA hardware/software co-design towards evolvable spiking neural networks for robotics application.

    PubMed

    Johnston, S P; Prasad, G; Maguire, L; McGinnity, T M

    2010-12-01

    This paper presents an approach that permits the effective hardware realization of a novel Evolvable Spiking Neural Network (ESNN) paradigm on Field Programmable Gate Arrays (FPGAs). The ESNN possesses a hybrid learning algorithm that consists of a Spike Timing Dependent Plasticity (STDP) mechanism fused with a Genetic Algorithm (GA). The design and implementation direction utilizes the latest advancements in FPGA technology to provide a partitioned hardware/software co-design solution. The approach achieves the maximum FPGA flexibility obtainable for the ESNN paradigm. The algorithm was applied as an embedded intelligent system robotic controller to solve an autonomous navigation and obstacle avoidance problem. PMID:21117269

  19. Study of the adaptability of existing hardware designs to a Pioneer Saturn/Uranus probe

    NASA Technical Reports Server (NTRS)

    1973-01-01

    The basic concept of designing a scientific entry probe for the expected range of environments at Saturn or Uranus and making the probe compatible with the interface constraints of the Pioneer spacecraft was investigated for launches in the early 1980's. It was found that the amount of hardware commonality between that used in the Pioneer Venus program and that for the Saturn/Uranus probe was approximately 85%. It is recommended that additional development studies be conducted to improve the hardware definitions of the probe design for the following: heat shield, battery, nose cap jettisoning, and thermal control insulation.

  20. Full chip correction of EUV design

    NASA Astrophysics Data System (ADS)

    Lorusso, G. F.; Hendrickx, E.; Fenger, G. L.; Niroomand, A.

    2010-04-01

    Extreme Ultraviolet Lithography (EUVL) is currently the most promising technology for advanced manufacturing nodes: it recently demonstrated the feasibility of 32nm and 22nm node devices, and pre-production tools are expected to be delivered by 2010. Generally speaking, EUVL is less in need of Optical Proximity Correction (OPC) as compared to 193nm lithography, and the device feasibility studies were indeed carried out with limited or no correction. However, a rigorous optical correction strategy and an appropriate Electronic Design Automation (EDA) infrastructure is critical to face the challenges of the 22nm node and beyond, and EUV-specific effects such as flare and shadowing have to be fully integrated in the correction flow and properly tested. This study aims to assess in detail the quality of a full chip optical correction for a EUV design, as well to discuss the available approaches to compensate for EUV-specific effects. Extensive data sets have been collected on the ASML EUV Alpha-Demo Tool (ADT) using the latest IMEC baseline resist Shin-Etsu SEVR59. In total about 1300 CD measurements at wafer level and 700 at mask level were used as input for model calibration and validation. The smallest feature size in the data set was 32nm. Both one-dimensional and two-dimensional structures through CD and pitch were measured. The mask used in this calibration exercise allowed the authors to modulate flare by varying tiling densities within the range expected in the final design. The OPC model was fitted and validated against the CD data collected on the EUV ADT. The shadowing effect was modeled by means of a single bias correction throughout the design. Horizontal and vertical features of different type through pitch and CD were used to calibrate the shadowing correction, and the extent of the validity of the single bias approach is discussed. In addition, the quality of the generated full-chip flare maps has been tested against experimental results, and the model

  1. Hardware-Efficient and Fully Autonomous Quantum Error Correction in Superconducting Circuits

    NASA Astrophysics Data System (ADS)

    Kapit, Eliot

    2016-04-01

    Superconducting qubits are among the most promising platforms for building a quantum computer. However, individual qubit coherence times are not far past the scalability threshold for quantum error correction, meaning that millions of physical devices would be required to construct a useful quantum computer. Consequently, further increases in coherence time are very desirable. In this Letter, we blueprint a simple circuit consisting of two transmon qubits and two additional lossy qubits or resonators, which is passively protected against all single-qubit quantum error channels through a combination of continuous driving and engineered dissipation. Photon losses are rapidly corrected through two-photon drive fields implemented with driven superconducting quantum interference device couplings, and dephasing from random potential fluctuations is heavily suppressed by the drive fields used to implement the multiqubit Hamiltonian. Comparing our theoretical model to published noise estimates from recent experiments on flux and transmon qubits, we find that logical state coherence could be improved by a factor of 40 or more compared to the individual qubit T1 and T2 using this technique. We thus demonstrate that there is substantial headroom for improving the coherence of modern superconducting qubits with a fairly modest increase in device complexity.

  2. Hardware-Efficient and Fully Autonomous Quantum Error Correction in Superconducting Circuits.

    PubMed

    Kapit, Eliot

    2016-04-15

    Superconducting qubits are among the most promising platforms for building a quantum computer. However, individual qubit coherence times are not far past the scalability threshold for quantum error correction, meaning that millions of physical devices would be required to construct a useful quantum computer. Consequently, further increases in coherence time are very desirable. In this Letter, we blueprint a simple circuit consisting of two transmon qubits and two additional lossy qubits or resonators, which is passively protected against all single-qubit quantum error channels through a combination of continuous driving and engineered dissipation. Photon losses are rapidly corrected through two-photon drive fields implemented with driven superconducting quantum interference device couplings, and dephasing from random potential fluctuations is heavily suppressed by the drive fields used to implement the multiqubit Hamiltonian. Comparing our theoretical model to published noise estimates from recent experiments on flux and transmon qubits, we find that logical state coherence could be improved by a factor of 40 or more compared to the individual qubit T_{1} and T_{2} using this technique. We thus demonstrate that there is substantial headroom for improving the coherence of modern superconducting qubits with a fairly modest increase in device complexity. PMID:27127945

  3. When "Less is More": The Optimal Design of Language Laboratory Hardware.

    ERIC Educational Resources Information Center

    Kershaw, Gary; Boyd, Gary

    1980-01-01

    The results of a process of designing, building, and "de-bugging" two replacement language laboratory hardware systems at Concordia University (Montreal) are described. Because commercially available systems did not meet specifications within budgetary constraints, the systems were built by the university technical department. The systems replaced…

  4. The design of flight hardware: Organizational and technical ideas from the MITRE/WPI Shuttle Program

    NASA Technical Reports Server (NTRS)

    Looft, F. J.

    1986-01-01

    The Mitre Corporation of Bedford Mass. and the Worcester Polytechnic Institute are developing several experiments for a future Shuttle flight. Several design practices for the development of the electrical equipment for the flight hardware have been standardized. Some of the ideas are presented, not as hard and fast rules but rather in the interest of stimulating discussions for sharing such ideas.

  5. Design Considerations in Development of Minicomputer-Based Computer Aided Instructional Hardware Systems.

    ERIC Educational Resources Information Center

    Wells, C. H.

    A minicomputer-based computer-assisted instructional (CAI) system was designed at the University of Texas Medical Branch in an attempt to lower both the excessive hardware costs and the inordinate amount of time required for the preparation of each hour of instructional material associated with traditional CAI systems. A prototype system with an…

  6. A Design of the Signal Processing Hardware Platform for Communication Systems

    NASA Astrophysics Data System (ADS)

    Lee, Byung Wook; Cho, Sung Ho

    In this letter, an efficient hardware platform for the digital signal processing for OFDM communication systems is presented. The hardware platform consists of a single FPGA having 900K gates, two DSPs with maximum 8,000 MIPS at 1GHz clock, 2-channel ADC and DAC supporting maximum 125MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16d software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.

  7. Test Hardware Design for Flightlike Operation of Advanced Stirling Convertors (ASC-E3)

    NASA Technical Reports Server (NTRS)

    Oriti, Salvatore M.

    2012-01-01

    NASA Glenn Research Center (GRC) has been supporting development of the Advanced Stirling Radioisotope Generator (ASRG) since 2006. A key element of the ASRG project is providing life, reliability, and performance testing of the Advanced Stirling Convertor (ASC). For this purpose, the Thermal Energy Conversion branch at GRC has been conducting extended operation of a multitude of free-piston Stirling convertors. The goal of this effort is to generate long-term performance data (tens of thousands of hours) simultaneously on multiple units to build a life and reliability database. The test hardware for operation of these convertors was designed to permit in-air investigative testing, such as performance mapping over a range of environmental conditions. With this, there was no requirement to accurately emulate the flight hardware. For the upcoming ASC-E3 units, the decision has been made to assemble the convertors into a flight-like configuration. This means the convertors will be arranged in the dual-opposed configuration in a housing that represents the fit, form, and thermal function of the ASRG. The goal of this effort is to enable system level tests that could not be performed with the traditional test hardware at GRC. This offers the opportunity to perform these system-level tests much earlier in the ASRG flight development, as they would normally not be performed until fabrication of the qualification unit. This paper discusses the requirements, process, and results of this flight-like hardware design activity.

  8. Test Hardware Design for Flight-Like Operation of Advanced Stirling Convertors

    NASA Technical Reports Server (NTRS)

    Oriti, Salvatore M.

    2012-01-01

    NASA Glenn Research Center (GRC) has been supporting development of the Advanced Stirling Radioisotope Generator (ASRG) since 2006. A key element of the ASRG project is providing life, reliability, and performance testing of the Advanced Stirling Convertor (ASC). For this purpose, the Thermal Energy Conversion branch at GRC has been conducting extended operation of a multitude of free-piston Stirling convertors. The goal of this effort is to generate long-term performance data (tens of thousands of hours) simultaneously on multiple units to build a life and reliability database. The test hardware for operation of these convertors was designed to permit in-air investigative testing, such as performance mapping over a range of environmental conditions. With this, there was no requirement to accurately emulate the flight hardware. For the upcoming ASC-E3 units, the decision has been made to assemble the convertors into a flight-like configuration. This means the convertors will be arranged in the dual-opposed configuration in a housing that represents the fit, form, and thermal function of the ASRG. The goal of this effort is to enable system level tests that could not be performed with the traditional test hardware at GRC. This offers the opportunity to perform these system-level tests much earlier in the ASRG flight development, as they would normally not be performed until fabrication of the qualification unit. This paper discusses the requirements, process, and results of this flight-like hardware design activity.

  9. A Comprehensive Reliability Methodology for Assessing Risk of Reusing Failed Hardware Without Corrective Actions with and Without Redundancy

    NASA Technical Reports Server (NTRS)

    Putcha, Chandra S.; Mikula, D. F. Kip; Dueease, Robert A.; Dang, Lan; Peercy, Robert L.

    1997-01-01

    This paper deals with the development of a reliability methodology to assess the consequences of using hardware, without failure analysis or corrective action, that has previously demonstrated that it did not perform per specification. The subject of this paper arose from the need to provide a detailed probabilistic analysis to calculate the change in probability of failures with respect to the base or non-failed hardware. The methodology used for the analysis is primarily based on principles of Monte Carlo simulation. The random variables in the analysis are: Maximum Time of Operation (MTO) and operation Time of each Unit (OTU) The failure of a unit is considered to happen if (OTU) is less than MTO for the Normal Operational Period (NOP) in which this unit is used. NOP as a whole uses a total of 4 units. Two cases are considered. in the first specialized scenario, the failure of any operation or system failure is considered to happen if any of the units used during the NOP fail. in the second specialized scenario, the failure of any operation or system failure is considered to happen only if any two of the units used during the MOP fail together. The probability of failure of the units and the system as a whole is determined for 3 kinds of systems - Perfect System, Imperfect System 1 and Imperfect System 2. in a Perfect System, the operation time of the failed unit is the same as that of the MTO. In an Imperfect System 1, the operation time of the failed unit is assumed as 1 percent of the MTO. In an Imperfect System 2, the operation time of the failed unit is assumed as zero. in addition, simulated operation time of failed units is assumed as 10 percent of the corresponding units before zero value. Monte Carlo simulation analysis is used for this study. Necessary software has been developed as part of this study to perform the reliability calculations. The results of the analysis showed that the predicted change in failure probability (P(sub F)) for the

  10. Object oriented design (OOD) in real-time hardware-in-the-loop (HWIL) simulations

    NASA Astrophysics Data System (ADS)

    Morris, Joe; Richard, Henri; Lowman, Alan; Youngren, Rob

    2006-05-01

    Using Object Oriented Design (OOD) concepts in AMRDEC's Hardware-in-the Loop (HWIL) real-time simulations allows the user to interchange parts of the simulation to meet test requirements. A large-scale three-spectral band simulator connected via a high speed reflective memory ring for time-critical data transfers to PC controllers connected by non real-time Ethernet protocols is used to separate software objects from logical entities close to their respective controlled hardware. Each standalone object does its own dynamic initialization, real-time processing, and end of run processing; therefore it can be easily maintained and updated. A Resource Allocation Program (RAP) is also utilized along with a device table to allocate, organize, and document the communication protocol between the software and hardware components. A GUI display program lists all allocations and deallocations of HWIL memory and hardware resources. This interactive program is also used to clean up defunct allocations of dead processes. Three examples are presented using the OOD and RAP concepts. The first is the control of an ACUTRONICS built three-axis flight table using the same control for calibration and real-time functions. The second is the transportability of a six-degree-of-freedom (6-DOF) simulation from an Onyx residence to a Linux-PC. The third is the replacement of the 6-DOF simulation with a replay program to drive the facility with archived run data for demonstration or analysis purposes.

  11. The design and hardware implementation of a low-power real-time seizure detection algorithm

    NASA Astrophysics Data System (ADS)

    Raghunathan, Shriram; Gupta, Sumeet K.; Ward, Matthew P.; Worth, Robert M.; Roy, Kaushik; Irazoqui, Pedro P.

    2009-10-01

    Epilepsy affects more than 1% of the world's population. Responsive neurostimulation is emerging as an alternative therapy for the 30% of the epileptic patient population that does not benefit from pharmacological treatment. Efficient seizure detection algorithms will enable closed-loop epilepsy prostheses by stimulating the epileptogenic focus within an early onset window. Critically, this is expected to reduce neuronal desensitization over time and lead to longer-term device efficacy. This work presents a novel event-based seizure detection algorithm along with a low-power digital circuit implementation. Hippocampal depth-electrode recordings from six kainate-treated rats are used to validate the algorithm and hardware performance in this preliminary study. The design process illustrates crucial trade-offs in translating mathematical models into hardware implementations and validates statistical optimizations made with empirical data analyses on results obtained using a real-time functioning hardware prototype. Using quantitatively predicted thresholds from the depth-electrode recordings, the auto-updating algorithm performs with an average sensitivity and selectivity of 95.3 ± 0.02% and 88.9 ± 0.01% (mean ± SEα = 0.05), respectively, on untrained data with a detection delay of 8.5 s [5.97, 11.04] from electrographic onset. The hardware implementation is shown feasible using CMOS circuits consuming under 350 nW of power from a 250 mV supply voltage from simulations on the MIT 180 nm SOI process.

  12. Skylab SO71/SO72 circadian periodicity experiment. [experimental design and checkout of hardware

    NASA Technical Reports Server (NTRS)

    Fairchild, M. K.; Hartmann, R. A.

    1973-01-01

    The circadian rhythm hardware activities from 1965 through 1973 are considered. A brief history of the programs leading to the development of the combined Skylab SO71/SO72 Circadian Periodicity Experiment (CPE) is given. SO71 is the Skylab experiment number designating the pocket mouse circadian experiment, and SO72 designates the vinegar gnat circadian experiment. Final design modifications and checkout of the CPE, integration testing with the Apollo service module CSM 117 and the launch preparation and support tasks at Kennedy Space Center are reported.

  13. Accelerating a MPEG-4 video decoder through custom software/hardware co-design

    NASA Astrophysics Data System (ADS)

    Díaz, Jorge L.; Barreto, Dacil; García, Luz; Marrero, Gustavo; Carballo, Pedro P.; Núñez, Antonio

    2007-05-01

    In this paper we present a novel methodology to accelerate an MPEG-4 video decoder using software/hardware co-design for wireless DAB/DMB networks. Software support includes the services provided by the embedded kernel μC/OS-II, and the application tasks mapped to software. Hardware support includes several custom co-processors and a communication architecture with bridges to the main system bus and with a dual port SRAM. Synchronization among tasks is achieved at two levels, by a hardware protocol and by kernel level scheduling services. Our reference application is an MPEG-4 video decoder composed of several software functions and written using a special C++ library named CASSE. Profiling and space exploration techniques were used previously over the Advanced Simple Profile (ASP) MPEG-4 decoder to determinate the best HW/SW partition developed here. This research is part of the ARTEMI project and its main goal is the establishment of methodologies for the design of real-time complex digital systems using Programmable Logic Devices with embedded microprocessors as target technology and the design of multimedia systems for broadcasting networks as reference application.

  14. A Principled Kernel Testbed for Hardware/Software Co-Design Research

    SciTech Connect

    Kaiser, Alex; Williams, Samuel; Madduri, Kamesh; Ibrahim, Khaled; Bailey, David; Demmel, James; Strohmaier, Erich

    2010-04-01

    Recently, advances in processor architecture have become the driving force for new programming models in the computing industry, as ever newer multicore processor designs with increasing number of cores are introduced on schedules regimented by marketing demands. As a result, collaborative parallel (rather than simply concurrent) implementations of important applications, programming languages, models, and even algorithms have been forced to adapt to these architectures to exploit the available raw performance. We believe that this optimization regime is flawed. In this paper, we present an alternate approach that, rather than starting with an existing hardware/software solution laced with hidden assumptions, defines the computational problems of interest and invites architects, researchers and programmers to implement novel hardware/software co-designed solutions. Our work builds on the previous ideas of computational dwarfs, motifs, and parallel patterns by selecting a representative set of essential problems for which we provide: An algorithmic description; scalable problem definition; illustrative reference implementations; verification schemes. This testbed will enable comparative research in areas such as parallel programming models, languages, auto-tuning, and hardware/software codesign. For simplicity, we focus initially on the computational problems of interest to the scientific computing community but proclaim the methodology (and perhaps a subset of the problems) as applicable to other communities. We intend to broaden the coverage of this problem space through stronger community involvement.

  15. Hardware design to accelerate PNG encoder for binary mask compression on FPGA

    NASA Astrophysics Data System (ADS)

    Kachouri, Rostom; Akil, Mohamed

    2015-02-01

    PNG (Portable Network Graphics) is a lossless compression method for real-world pictures. Since its specification, it continues to attract the interest of the image processing community. Indeed, PNG is an extensible file format for portable and well-compressed storage of raster images. In addition, it supports all of Black and White (binary mask), grayscale, indexed-color, and truecolor images. Within the framework of the Demat+ project which intend to propose a complete solution for storage and retrieval of scanned documents, we address in this paper a hardware design to accelerate the PNG encoder for binary mask compression on FPGA. For this, an optimized architecture is proposed as part of an hybrid software and hardware co-operating system. For its evaluation, the new designed PNG IP has been implemented on the ALTERA Arria II GX EP2AGX125EF35" FPGA. The experimental results show a good match between the achieved compression ratio, the computational cost and the used hardware resources.

  16. Thermal Performance of a Customized Multilayer Insulation (MLI). Design and Fabrication of Test Facility Hardware

    NASA Technical Reports Server (NTRS)

    Leonhard, K. E.

    1975-01-01

    The design, fabrication, and assembly of hardware for testing the performance of a customized multilayer insulation are discussed. System components described include the thermal payload simulator, the modified cryoshroud, and a tank back pressure control device designed to maintain a constant liquid boiling point during the thermal evaluation of the multilayer insulation. The thermal payload simulator will provide a constant temperature surface in the range of 20.5 to 417K (37 to 750R) for the insulated tank to view. The cryoshroud was modified to establish a low temperature black body cavity while limiting liquid hydrogen usage to a minimum feasible rate.

  17. Design and Control of Compliant Tensegrity Robots Through Simulation and Hardware Validation

    NASA Technical Reports Server (NTRS)

    Caluwaerts, Ken; Despraz, Jeremie; Iscen, Atil; Sabelhaus, Andrew P.; Bruce, Jonathan; Schrauwen, Benjamin; Sunspiral, Vytas

    2014-01-01

    To better understand the role of tensegrity structures in biological systems and their application to robotics, the Dynamic Tensegrity Robotics Lab at NASA Ames Research Center has developed and validated two different software environments for the analysis, simulation, and design of tensegrity robots. These tools, along with new control methodologies and the modular hardware components developed to validate them, are presented as a system for the design of actuated tensegrity structures. As evidenced from their appearance in many biological systems, tensegrity ("tensile-integrity") structures have unique physical properties which make them ideal for interaction with uncertain environments. Yet these characteristics, such as variable structural compliance, and global multi-path load distribution through the tension network, make design and control of bio-inspired tensegrity robots extremely challenging. This work presents the progress in using these two tools in tackling the design and control challenges. The results of this analysis includes multiple novel control approaches for mobility and terrain interaction of spherical tensegrity structures. The current hardware prototype of a six-bar tensegrity, code-named ReCTeR, is presented in the context of this validation.

  18. Design and control of compliant tensegrity robots through simulation and hardware validation

    PubMed Central

    Caluwaerts, Ken; Despraz, Jérémie; Işçen, Atıl; Sabelhaus, Andrew P.; Bruce, Jonathan; Schrauwen, Benjamin; SunSpiral, Vytas

    2014-01-01

    To better understand the role of tensegrity structures in biological systems and their application to robotics, the Dynamic Tensegrity Robotics Lab at NASA Ames Research Center, Moffett Field, CA, USA, has developed and validated two software environments for the analysis, simulation and design of tensegrity robots. These tools, along with new control methodologies and the modular hardware components developed to validate them, are presented as a system for the design of actuated tensegrity structures. As evidenced from their appearance in many biological systems, tensegrity (‘tensile–integrity’) structures have unique physical properties that make them ideal for interaction with uncertain environments. Yet, these characteristics make design and control of bioinspired tensegrity robots extremely challenging. This work presents the progress our tools have made in tackling the design and control challenges of spherical tensegrity structures. We focus on this shape since it lends itself to rolling locomotion. The results of our analyses include multiple novel control approaches for mobility and terrain interaction of spherical tensegrity structures that have been tested in simulation. A hardware prototype of a spherical six-bar tensegrity, the Reservoir Compliant Tensegrity Robot, is used to empirically validate the accuracy of simulation. PMID:24990292

  19. Design and control of compliant tensegrity robots through simulation and hardware validation.

    PubMed

    Caluwaerts, Ken; Despraz, Jérémie; Işçen, Atıl; Sabelhaus, Andrew P; Bruce, Jonathan; Schrauwen, Benjamin; SunSpiral, Vytas

    2014-09-01

    To better understand the role of tensegrity structures in biological systems and their application to robotics, the Dynamic Tensegrity Robotics Lab at NASA Ames Research Center, Moffett Field, CA, USA, has developed and validated two software environments for the analysis, simulation and design of tensegrity robots. These tools, along with new control methodologies and the modular hardware components developed to validate them, are presented as a system for the design of actuated tensegrity structures. As evidenced from their appearance in many biological systems, tensegrity ('tensile-integrity') structures have unique physical properties that make them ideal for interaction with uncertain environments. Yet, these characteristics make design and control of bioinspired tensegrity robots extremely challenging. This work presents the progress our tools have made in tackling the design and control challenges of spherical tensegrity structures. We focus on this shape since it lends itself to rolling locomotion. The results of our analyses include multiple novel control approaches for mobility and terrain interaction of spherical tensegrity structures that have been tested in simulation. A hardware prototype of a spherical six-bar tensegrity, the Reservoir Compliant Tensegrity Robot, is used to empirically validate the accuracy of simulation. PMID:24990292

  20. Radiation Mitigation and Power Optimization Design Tools for Reconfigurable Hardware in Orbit

    NASA Technical Reports Server (NTRS)

    French, Matthew; Graham, Paul; Wirthlin, Michael; Wang, Li; Larchev, Gregory

    2005-01-01

    The Reconfigurable Hardware in Orbit (RHinO)project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. In the second year of the project, design tools that leverage an established FPGA design environment have been created to visualize and analyze an FPGA circuit for radiation weaknesses and power inefficiencies. For radiation, a single event Upset (SEU) emulator, persistence analysis tool, and a half-latch removal tool for Xilinx/Virtex-II devices have been created. Research is underway on a persistence mitigation tool and multiple bit upsets (MBU) studies. For power, synthesis level dynamic power visualization and analysis tools have been completed. Power optimization tools are under development and preliminary test results are positive.

  1. Combined Cycle Engine Large-Scale Inlet for Mode Transition Experiments: System Identification Rack Hardware Design

    NASA Technical Reports Server (NTRS)

    Thomas, Randy; Stueber, Thomas J.

    2013-01-01

    The System Identification (SysID) Rack is a real-time hardware-in-the-loop data acquisition (DAQ) and control instrument rack that was designed and built to support inlet testing in the NASA Glenn Research Center 10- by 10-Foot Supersonic Wind Tunnel. This instrument rack is used to support experiments on the Combined-Cycle Engine Large-Scale Inlet for Mode Transition Experiment (CCE? LIMX). The CCE?LIMX is a testbed for an integrated dual flow-path inlet configuration with the two flow paths in an over-and-under arrangement such that the high-speed flow path is located below the lowspeed flow path. The CCE?LIMX includes multiple actuators that are designed to redirect airflow from one flow path to the other; this action is referred to as "inlet mode transition." Multiple phases of experiments have been planned to support research that investigates inlet mode transition: inlet characterization (Phase-1) and system identification (Phase-2). The SysID Rack hardware design met the following requirements to support Phase-1 and Phase-2 experiments: safely and effectively move multiple actuators individually or synchronously; sample and save effector control and position sensor feedback signals; automate control of actuator positioning based on a mode transition schedule; sample and save pressure sensor signals; and perform DAQ and control processes operating at 2.5 KHz. This document describes the hardware components used to build the SysID Rack including their function, specifications, and system interface. Furthermore, provided in this document are a SysID Rack effectors signal list (signal flow); system identification experiment setup; illustrations indicating a typical SysID Rack experiment; and a SysID Rack performance overview for Phase-1 and Phase-2 experiments. The SysID Rack described in this document was a useful tool to meet the project objectives.

  2. Interim Service ISDN Satellite (ISIS) hardware experiment development for advanced ISDN satellite designs and experiments

    NASA Technical Reports Server (NTRS)

    Pepin, Gerard R.

    1992-01-01

    The Interim Service Integrated Service Digital Network (ISDN) Satellite (ISIS) Hardware Experiment Development for Advanced Satellite Designs describes the development of the ISDN Satellite Terminal Adapter (ISTA) capable of translating ISDN protocol traffic into Time Division Multiple Access (TDMA) signals for use by a communications satellite. The ISTA connects the Type 1 Network Termination (NT1) via the U-interface on the line termination side of the CPE to the RS-499 interface for satellite uplink. The same ISTA converts in the opposite direction the RS-499 to U-interface data with a simple switch setting.

  3. Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology

    NASA Astrophysics Data System (ADS)

    Lata Murotiya, Sneh; Gupta, Anu

    2016-05-01

    This paper proposes a hardware-efficient low-power 2-bit ternary arithmetic logic unit (TALU) design in carbon nano tube field effect transistor technology. The proposed TALU architecture combines adder-subtractor and Ex-OR cell in one cell, thereby reducing the number of transistors by 71% in comparison with other TALU architecture. Further, the proposed TALU is optimised at transistor level with a new pass-transistor logic-based encoder circuit. Hspice simulation results show that the proposed design attains great advantages in power and power-delay product for addition and multiplication operations than reported designs. For instant, at power supply of 0.9 V, the proposed TALU consumes on average 91% and 95% less energy compared to their existing counterparts, for addition and multiplication operations, respectively.

  4. Color correction strategies in optical design

    NASA Astrophysics Data System (ADS)

    Pfisterer, Richard N.; Vorndran, Shelby D.

    2014-12-01

    An overview of color correction strategies is presented. Starting with basic first-order aberration theory, we identify known color corrected solutions for doublets and triplets. Reviewing the modern approaches of Robb-Mercado, Rayces-Aguilar, and C. de Albuquerque et al, we find that they confirm the existence of glass combinations for doublets and triplets that yield color corrected solutions that we already know exist. Finally we explore the use of the y, ӯ diagram in conjunction with aberration theory to identify the solution space of glasses capable of leading to color corrected solutions in arbitrary optical systems.

  5. A processor for MPEG decoder SOC: a software/hardware co-design approach

    NASA Astrophysics Data System (ADS)

    Yu, Guojun; Yao, Qingdong; Liu, Peng; Jiang, Zhidi; Li, Fuping

    2005-03-01

    Media processing such as real-time compression and decompression of video signal is now expected to be the driving force in the evolution of media processor. In this paper, a hardware and software co-design approach is introduced for a 32-bit media processor: MediaDsp3201 (briefly, MD32), which is realized in 0.18μm TSMC, 200MHz and can achieve 200 million multiply-accumulate (MAC) operations per second. In our design, we have emerged RISC and DSP into one processor (RISC/DSP). Based on the analysis of inherent characteristics of video processing algorithms, media enhancement instructions are adopted into MD32"instruction set. The media extension instructions are physically realized in the processor core, and improves video processing performance effectively with negligible additional hardware cost (2.7%). Considering the high complexity of the operation for media instructions, technology named scalable super pipeline is used to resolve problem of the time delay of pipeline stage (mainly EX stage). Simulation results show that our method can reduce more than 31% and 23% instructions for IDCT compared to MMX and SSE"s implementation and 40% for MC compared to MMX"s implementation.

  6. VLSI realization of learning vector quantization with hardware/software co-design for different applications

    NASA Astrophysics Data System (ADS)

    An, Fengwei; Akazawa, Toshinobu; Yamasaki, Shogo; Chen, Lei; Jürgen Mattausch, Hans

    2015-04-01

    This paper reports a VLSI realization of learning vector quantization (LVQ) with high flexibility for different applications. It is based on a hardware/software (HW/SW) co-design concept for on-chip learning and recognition and designed as a SoC in 180 nm CMOS. The time consuming nearest Euclidean distance search in the LVQ algorithm’s competition layer is efficiently implemented as a pipeline with parallel p-word input. Since neuron number in the competition layer, weight values, input and output number are scalable, the requirements of many different applications can be satisfied without hardware changes. Classification of a d-dimensional input vector is completed in n × \\lceil d/p \\rceil + R clock cycles, where R is the pipeline depth, and n is the number of reference feature vectors (FVs). Adjustment of stored reference FVs during learning is done by the embedded 32-bit RISC CPU, because this operation is not time critical. The high flexibility is verified by the application of human detection with different numbers for the dimensionality of the FVs.

  7. A hardware-software co-design approach to a JPEG encoder design for a planetary micro-rover application

    NASA Astrophysics Data System (ADS)

    Sarma, S.; Udupa, S.; Bhardwaj, K. M.; Parameswaran, K.; Malik, N. K.

    2011-01-01

    Micro-rovers aimed with the objective of planetary exploration of moons and heavenly bodies are becoming focus of many space missions. These micro-rover missions face hard challenges of harsh environment and resource constraints such as power and transmission bandwidth. The image data collected by the on-board cameras are often not possible to transmit to ground due to low bandwidth or adequate transmission duration. The JPEG image compression standard that is developed by the Joint Photographic Experts Group committee for use in compressing digital images and full color photographic images is ubiquitous and is a useful solution to the problem. In this paper, a hardware-software based co-design approach is presented with the aim to implement a JPEG encoder for reducing the transmission bandwidth requirement of a planetary micro-rover. A pipelined hardware architecture of the JPEG encoder requiring reduced hardware resources and power is designed for PowerPC and MIL-1750 processor interface and its performance and resource utilization using standard images of various sizes and quality settings for both these processor architecture is compared. Results are substantiated using extensive simulation and RTL implementation in FPGA. Based on these studies an efficient architecture is arrived at for use in a planetary microrover for future exploration by an Indian moon mission.

  8. Preliminary design of flight hardware for two-phase fluid research

    NASA Technical Reports Server (NTRS)

    Hustvedt, D. C.; Oonk, R. L.

    1982-01-01

    This study defined the preliminary designs of flight software for the Space Shuttle Orbiter for three two-phase fluid research experiments: (1) liquid reorientation - to study the motion of liquid in tanks subjected to small accelerations; (2) pool boiling - to study low-gravity boiling from horizontal cylinders; and (3) flow boiling - to study low-gravity forced flow boiling heat transfer and flow phenomena in a heated horizontal tube. The study consisted of eight major tasks: reassessment of the existing experiment designs, assessment of the Spacelab facility approach, assessment of the individual carry-on approach, selection of the preferred approach, preliminary design of flight hardware, safety analysis, preparation of a development plan, estimates of detailed design, fabrication and ground testing costs. The most cost effective design approach for the experiments is individual carry-ons in the Orbiter middeck. The experiments were designed to fit into one or two middeck lockers. Development schedules for the detailed design, fabrication and ground testing ranged from 15 1/2 to 18 months. Minimum costs (in 1981 dollars) ranged from $463K for the liquid reorientation experiment to $998K for the pool boiling experiment.

  9. SensoTube: A Scalable Hardware Design Architecture for Wireless Sensors and Actuators Networks Nodes in the Agricultural Domain.

    PubMed

    Piromalis, Dimitrios; Arvanitis, Konstantinos

    2016-01-01

    Wireless Sensor and Actuators Networks (WSANs) constitute one of the most challenging technologies with tremendous socio-economic impact for the next decade. Functionally and energy optimized hardware systems and development tools maybe is the most critical facet of this technology for the achievement of such prospects. Especially, in the area of agriculture, where the hostile operating environment comes to add to the general technological and technical issues, reliable and robust WSAN systems are mandatory. This paper focuses on the hardware design architectures of the WSANs for real-world agricultural applications. It presents the available alternatives in hardware design and identifies their difficulties and problems for real-life implementations. The paper introduces SensoTube, a new WSAN hardware architecture, which is proposed as a solution to the various existing design constraints of WSANs. The establishment of the proposed architecture is based, firstly on an abstraction approach in the functional requirements context, and secondly, on the standardization of the subsystems connectivity, in order to allow for an open, expandable, flexible, reconfigurable, energy optimized, reliable and robust hardware system. The SensoTube implementation reference model together with its encapsulation design and installation are analyzed and presented in details. Furthermore, as a proof of concept, certain use cases have been studied in order to demonstrate the benefits of migrating existing designs based on the available open-source hardware platforms to SensoTube architecture. PMID:27527180

  10. Design of OLED gamma correction system based on the LUT

    NASA Astrophysics Data System (ADS)

    Tai, Yonghang; Yun, Lijun; Shi, Junsheng; Chen, Zaiqing; Li, Qiong

    2011-11-01

    Gamma correction is an important processing in reproduce images information realizing of video source. In order to improve the image sharpness of the OLED micro-display, a Gamma correction system was established to compensate for the gray scale distortion of the micro-display which is caused by the difference between the optical and electrical characteristic property. Based on the North OLEiD Company's 0.5 inch OLED, We proposed a Gamma correction system to converts 8 bits input signal into 9 bits displayed on the OLED. It used Microchip as the MCU and the master of the I2C serial bus, Development of the hardware system measurement verified the correction of VGA and CVBS video input and the picture quality also apparently improved.

  11. Hardware synthesis from DDL description. [simulating a digital system for computerized design of large scale integrated circuits

    NASA Technical Reports Server (NTRS)

    Shiva, S. G.; Shah, A. M.

    1980-01-01

    The details of digital systems can be conveniently input into the design automation system by means of hardware description language (HDL). The computer aided design and test (CADAT) system at NASA MSFC is used for the LSI design. The digital design language (DDL) was selected as HDL for the CADAT System. DDL translator output can be used for the hardware implementation of the digital design. Problems of selecting the standard cells from the CADAT standard cell library to realize the logic implied by the DDL description of the system are addressed.

  12. Acoustical Testing Laboratory Developed to Support the Low-Noise Design of Microgravity Space Flight Hardware

    NASA Technical Reports Server (NTRS)

    Cooper, Beth A.

    2001-01-01

    The NASA John H. Glenn Research Center at Lewis Field has designed and constructed an Acoustical Testing Laboratory to support the low-noise design of microgravity space flight hardware. This new laboratory will provide acoustic emissions testing and noise control services for a variety of customers, particularly for microgravity space flight hardware that must meet International Space Station limits on noise emissions. These limits have been imposed by the space station to support hearing conservation, speech communication, and safety goals as well as to prevent noise-induced vibrations that could impact microgravity research data. The Acoustical Testing Laboratory consists of a 23 by 27 by 20 ft (height) convertible hemi/anechoic chamber and separate sound-attenuating test support enclosure. Absorptive 34-in. fiberglass wedges in the test chamber provide an anechoic environment down to 100 Hz. A spring-isolated floor system affords vibration isolation above 3 Hz. These criteria, along with very low design background levels, will enable the acquisition of accurate and repeatable acoustical measurements on test articles, up to a full space station rack in size, that produce very little noise. Removable floor wedges will allow the test chamber to operate in either a hemi/anechoic or anechoic configuration, depending on the size of the test article and the specific test being conducted. The test support enclosure functions as a control room during normal operations but, alternatively, may be used as a noise-control enclosure for test articles that require the operation of noise-generating test support equipment.

  13. Hybrid Modeling for Scenario-Based Evaluation of Failure Effects in Advanced Hardware-Software Designs

    NASA Technical Reports Server (NTRS)

    Malin, Jane T.; Fleming, Land; Throop, David

    2001-01-01

    This paper describes an incremental scenario-based simulation approach to evaluation of intelligent software for control and management of hardware systems. A hybrid continuous/discrete event simulation of the hardware dynamically interacts with the intelligent software in operations scenarios. Embedded anomalous conditions and failures in simulated hardware can lead to emergent software behavior and identification of missing or faulty software or hardware requirements. An approach is described for extending simulation-based automated incremental failure modes and effects analysis, to support concurrent evaluation of intelligent software and the hardware controlled by the software

  14. Design and Development of Multi-Purpose CCD Camera System with Thermoelectric Cooling: Hardware

    NASA Astrophysics Data System (ADS)

    Kang, Y.-W.; Byun, Y. I.; Rhee, J. H.; Oh, S. H.; Kim, D. K.

    2007-12-01

    We designed and developed a multi-purpose CCD camera system for three kinds of CCDs; KAF-0401E(768×512), KAF-1602E(1536×1024), KAF-3200E(2184×1472) made by KODAK Co.. The system supports fast USB port as well as parallel port for data I/O and control signal. The packing is based on two stage circuit boards for size reduction and contains built-in filter wheel. Basic hardware components include clock pattern circuit, A/D conversion circuit, CCD data flow control circuit, and CCD temperature control unit. The CCD temperature can be controlled with accuracy of approximately 0.4° C in the max. range of temperature, Δ 33° C. This CCD camera system has with readout noise 6 e^{-}, and system gain 5 e^{-}/ADU. A total of 10 CCD camera systems were produced and our tests show that all of them show passable performance.

  15. Structural Design Requirements and Factors of Safety for Spaceflight Hardware: For Human Spaceflight. Revision A

    NASA Technical Reports Server (NTRS)

    Bernstein, Karen S.; Kujala, Rod; Fogt, Vince; Romine, Paul

    2011-01-01

    This document establishes the structural requirements for human-rated spaceflight hardware including launch vehicles, spacecraft and payloads. These requirements are applicable to Government Furnished Equipment activities as well as all related contractor, subcontractor and commercial efforts. These requirements are not imposed on systems other than human-rated spacecraft, such as ground test articles, but may be tailored for use in specific cases where it is prudent to do so such as for personnel safety or when assets are at risk. The requirements in this document are focused on design rather than verification. Implementation of the requirements is expected to be described in a Structural Verification Plan (SVP), which should describe the verification of each structural item for the applicable requirements. The SVP may also document unique verifications that meet or exceed these requirements with NASA Technical Authority approval.

  16. Final Scientific/Technical Report for "Enabling Exascale Hardware and Software Design through Scalable System Virtualization"

    SciTech Connect

    Dinda, Peter August

    2015-03-17

    This report describes the activities, findings, and products of the Northwestern University component of the "Enabling Exascale Hardware and Software Design through Scalable System Virtualization" project. The purpose of this project has been to extend the state of the art of systems software for high-end computing (HEC) platforms, and to use systems software to better enable the evaluation of potential future HEC platforms, for example exascale platforms. Such platforms, and their systems software, have the goal of providing scientific computation at new scales, thus enabling new research in the physical sciences and engineering. Over time, the innovations in systems software for such platforms also become applicable to more widely used computing clusters, data centers, and clouds. This was a five-institution project, centered on the Palacios virtual machine monitor (VMM) systems software, a project begun at Northwestern, and originally developed in a previous collaboration between Northwestern University and the University of New Mexico. In this project, Northwestern (including via our subcontract to the University of Pittsburgh) contributed to the continued development of Palacios, along with other team members. We took the leadership role in (1) continued extension of support for emerging Intel and AMD hardware, (2) integration and performance enhancement of overlay networking, (3) connectivity with architectural simulation, (4) binary translation, and (5) support for modern Non-Uniform Memory Access (NUMA) hosts and guests. We also took a supporting role in support for specialized hardware for I/O virtualization, profiling, configurability, and integration with configuration tools. The efforts we led (1-5) were largely successful and executed as expected, with code and papers resulting from them. The project demonstrated the feasibility of a virtualization layer for HEC computing, similar to such layers for cloud or datacenter computing. For effort (3

  17. Hardware/software co-design of global cloud system resolving models

    NASA Astrophysics Data System (ADS)

    Wehner, Michael F.; Oliker, Leonid; Shalf, John; Donofrio, David; Drummond, Leroy A.; Heikes, Ross; Kamil, Shoaib; Kono, Celal; Miller, Norman; Miura, Hiroaki; Mohiyuddin, Marghoob; Randall, David; Yang, Woo-Sun

    2011-04-01

    We present an analysis of the performance aspects of an atmospheric general circulation model at the ultra-high resolution required to resolve individual cloud systems and describe alternative technological paths to realize the integration of such a model in the relatively near future. Due to a superlinear scaling of the computational burden dictated by the Courant stability criterion, the solution of the equations of motion dominate the calculation at these ultra-high resolutions. From this extrapolation, it is estimated that a credible kilometer scale atmospheric model would require a sustained computational rate of at least 28 Petaflop/s to provide scientifically useful climate simulations. Our design study portends an alternate strategy for practical power-efficient implementations of next-generation ultra-scale systems. We demonstrate that hardware/software co-design of low-power embedded processor technology could be exploited to design a custom machine tailored to ultra-high resolution climate model specifications at relatively affordable cost and power considerations. A strawman machine design is presented consisting of in excess of 20 million processing elements that effectively exploits forthcoming many-core chips. The system pushes the limits of domain decomposition to increase explicit parallelism, and suggests that functional partitioning of sub-components of the climate code (much like the coarse-grained partitioning of computation between the atmospheric, ocean, land, and ice components of current coupled models) may be necessary for future performance scaling.

  18. Real-time multi-dimensional processing hardware designs research activities

    SciTech Connect

    Current, W. . Dept. of Electrical Engineering and Computer Science)

    1990-10-31

    In this final report, we summarize some of our results from September 1989 to October 1990. The design, construction, and testing of a four-processor prototype multi-processor (RTP) board using TI TMS320C25 DSP chips has been completed and is reported upon in our separately submitted Final Report on the RADON TRANSFORM COMPUTER'' Project.'' The design of our fully custom CMOS VLSI chip has been completed. The chip has been designed, the layout completed, and the chip is now going through its final pre-fabrication simulations. We are now finishing the extensive detailed final documentation of the R/Bchip. This extensive documentation will be provided to Steve Azevedo when we have submitted the chip for fabrication. The present status of the custom chip design activity is summarized in Section II. Evaluations of the hardware requirements for fast filtering of data for filtered backprojection (item 3) have been completed and are summarized in our separately submitted Final Report on the RADON TRANSFORM COMPUTER'' Project.'' We briefly summarize the new custom CMOS VLSI unified Radon transform/backprojection IC architecture, layout, and simulated performance.

  19. Streamlined design and self reliant hardware for active control of precision space structures

    NASA Technical Reports Server (NTRS)

    Hyland, David C.; King, James A.; Phillips, Douglas J.

    1994-01-01

    Precision space structures may require active vibration control to satisfy critical performance requirements relating to line-of-sight pointing accuracy and the maintenance of precise, internal alignments. In order for vibration control concepts to become operational, it is necessary that their benefits be practically demonstrated in large scale ground-based experiments. A unique opportunity to carry out such demonstrations on a wide variety of experimental testbeds was provided by the NASA Control-Structure Integration (CSI) Guest Investigator (GI) Program. This report surveys the experimental results achieved by the Harris Corporation GI team on both Phases 1 and 2 of the program and provides a detailed description of Phase 2 activities. The Phase 1 results illustrated the effectiveness of active vibration control for space structures and demonstrated a systematic methodology for control design, implementation test. In Phase 2, this methodology was significantly streamlined to yield an on-site, single session design/test capability. Moreover, the Phase 2 research on adaptive neural control techniques made significant progress toward fully automated, self-reliant space structure control systems. As a further thrust toward productized, self-contained vibration control systems, the Harris Phase II activity concluded with experimental demonstration of new vibration isolation hardware suitable for a wide range of space-flight and ground-based commercial applications.The CSI GI Program Phase 1 activity was conducted under contract NASA1-18872, and the Phase 2 activity was conducted under NASA1-19372.

  20. Design and fabrication of an autonomous rendezvous and docking sensor using off-the-shelf hardware

    NASA Technical Reports Server (NTRS)

    Grimm, Gary E.; Bryan, Thomas C.; Howard, Richard T.; Book, Michael L.

    1991-01-01

    NASA Marshall Space Flight Center (MSFC) has developed and tested an engineering model of an automated rendezvous and docking sensor system composed of a video camera ringed with laser diodes at two wavelengths and a standard remote manipulator system target that has been modified with retro-reflective tape and 830 and 780 mm optical filters. TRW has provided additional engineering analysis, design, and manufacturing support, resulting in a robust, low cost, automated rendezvous and docking sensor design. We have addressed the issue of space qualification using off-the-shelf hardware components. We have also addressed the performance problems of increased signal to noise ratio, increased range, increased frame rate, graceful degradation through component redundancy, and improved range calibration. Next year, we will build a breadboard of this sensor. The phenomenology of the background scene of a target vehicle as viewed against earth and space backgrounds under various lighting conditions will be simulated using the TRW Dynamic Scene Generator Facility (DSGF). Solar illumination angles of the target vehicle and candidate docking target ranging from eclipse to full sun will be explored. The sensor will be transportable for testing at the MSFC Flight Robotics Laboratory (EB24) using the Dynamic Overhead Telerobotic Simulator (DOTS).

  1. Space Technology 5: Changing the Mission Design without Changing the Hardware

    NASA Technical Reports Server (NTRS)

    Carlisle, Candace C.; Webb, Evan H.; Slavin, James A.

    2005-01-01

    The Space Technology 5 (ST-5) Project is part of NASA's New Millennium Program. The validation objectives are to demonstrate the research-quality science capability of the ST-5 spacecraft; to operate the three spacecraft as a constellation; and to design, develop, test and flight-validate three capable micro-satellites with new technologies. A three-month flight demonstration phase is planned, beginning in March 2006. This year, the mission was re-planned for a Pegasus XL dedicated launch into an elliptical polar orbit (instead of the Originally-planned Geosynchronous Transfer Orbit.) The re-plan allows the mission to achieve the same high-level technology validation objectives with a different launch vehicle. The new mission design involves a revised science validation strategy, a new orbit and different communication strategy, while minimizing changes to the ST-5 spacecraft itself. The constellation operations concepts have also been refined. While the system engineers, orbit analysts, and operations teams were re-planning the mission, the implementation team continued to make progress on the flight hardware. Most components have been delivered, and the first spacecraft is well into integration and test.

  2. Hardware Design and Implementation of a Wavelet De-Noising Procedure for Medical Signal Preprocessing

    PubMed Central

    Chen, Szi-Wen; Chen, Yuan-Ho

    2015-01-01

    In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz. PMID:26501290

  3. Hardware design and implementation of a wavelet de-noising procedure for medical signal preprocessing.

    PubMed

    Chen, Szi-Wen; Chen, Yuan-Ho

    2015-01-01

    In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz. PMID:26501290

  4. Simulation verification techniques study: Simulation self test hardware design and techniques report

    NASA Technical Reports Server (NTRS)

    1974-01-01

    The final results are presented of the hardware verification task. The basic objectives of the various subtasks are reviewed along with the ground rules under which the overall task was conducted and which impacted the approach taken in deriving techniques for hardware self test. The results of the first subtask and the definition of simulation hardware are presented. The hardware definition is based primarily on a brief review of the simulator configurations anticipated for the shuttle training program. The results of the survey of current self test techniques are presented. The data sources that were considered in the search for current techniques are reviewed, and results of the survey are presented in terms of the specific types of tests that are of interest for training simulator applications. Specifically, these types of tests are readiness tests, fault isolation tests and incipient fault detection techniques. The most applicable techniques were structured into software flows that are then referenced in discussions of techniques for specific subsystems.

  5. Energy Efficient Engine: High-pressure compressor test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Howe, David C.; Marchant, R. D.

    1988-01-01

    The objective of the NASA Energy Efficient Engine program is to identify and verify the technology required to achieve significant reductions in fuel consumption and operating cost for future commercial gas turbine engines. The design and analysis is documented of the high pressure compressor which was tested as part of the Pratt and Whitney effort under the Energy Efficient Engine program. This compressor was designed to produce a 14:1 pressure ratio in ten stages with an adiabatic efficiency of 88.2 percent in the flight propulsion system. The corresponding expected efficiency for the compressor component test rig is 86.5 percent. Other performance goals are a surge margin of 20 percent, a corrected flow rate of 35.2 kg/sec (77.5 lb/sec), and a life of 20,000 missions and 30,000 hours. Low loss, highly loaded airfoils are used to increase efficiency while reducing the parts count. Active clearance control and case trenches in abradable strips over the blade tips are included in the compressor component design to further increase the efficiency potential. The test rig incorporates variable geometry stator vanes in all stages to permit maximum flexibility in developing stage-to-stage matching. This provision precluded active clearance control on the rear case of the test rig. Both the component and rig designs meet or exceed design requirements with the exception of life goals, which will be achievable with planned advances in materials technology.

  6. A parallel algorithm for error correction in high-throughput short-read data on CUDA-enabled graphics hardware.

    PubMed

    Shi, Haixiang; Schmidt, Bertil; Liu, Weiguo; Müller-Wittig, Wolfgang

    2010-04-01

    Emerging DNA sequencing technologies open up exciting new opportunities for genome sequencing by generating read data with a massive throughput. However, produced reads are significantly shorter and more error-prone compared to the traditional Sanger shotgun sequencing method. This poses challenges for de novo DNA fragment assembly algorithms in terms of both accuracy (to deal with short, error-prone reads) and scalability (to deal with very large input data sets). In this article, we present a scalable parallel algorithm for correcting sequencing errors in high-throughput short-read data so that error-free reads can be available before DNA fragment assembly, which is of high importance to many graph-based short-read assembly tools. The algorithm is based on spectral alignment and uses the Compute Unified Device Architecture (CUDA) programming model. To gain efficiency we are taking advantage of the CUDA texture memory using a space-efficient Bloom filter data structure for spectrum membership queries. We have tested the runtime and accuracy of our algorithm using real and simulated Illumina data for different read lengths, error rates, input sizes, and algorithmic parameters. Using a CUDA-enabled mass-produced GPU (available for less than US$400 at any local computer outlet), this results in speedups of 12-84 times for the parallelized error correction, and speedups of 3-63 times for both sequential preprocessing and parallelized error correction compared to the publicly available Euler-SR program. Our implementation is freely available for download from http://cuda-ec.sourceforge.net . PMID:20426693

  7. The design of a hardware testing system for the D Zero Detector

    SciTech Connect

    Angstadt, R.; Johnson, M.; Martin, M.; Matulik, M.; Utes, M.

    1991-11-01

    Testing a system as large as the D Zero data acquisition system is difficult. This paper describes the use of IBM compatible personal computers in a hardware test system that can run on any size system from an engineer`s test bench to the entire subsystem in the D Zero Detector. The test system uses a PC to VME bus interface for the local testing and the Token Ring network for more global testing. This system has been implemented for several different hardware systems in D Zero.

  8. Designing multifocal corneal models to correct presbyopia by laser ablation

    NASA Astrophysics Data System (ADS)

    Alarcón, Aixa; Anera, Rosario G.; Del Barco, Luis Jiménez; Jiménez, José R.

    2012-01-01

    Two multifocal corneal models and an aspheric model designed to correct presbyopia by corneal photoablation were evaluated. The design of each model was optimized to achieve the best visual quality possible for both near and distance vision. In addition, we evaluated the effect of myosis and pupil decentration on visual quality. The corrected model with the central zone for near vision provides better results since it requires less ablated corneal surface area, permits higher addition values, presents stabler visual quality with pupil-size variations and lower high-order aberrations.

  9. Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Biagioni, A.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Rossetti, D.; Simula, F.; Tosoratto, L.; Vicini, P.

    2015-12-01

    In the attempt to develop an interconnection architecture optimized for hybrid HPC systems dedicated to scientific computing, we designed APEnet+, a point-to-point, low-latency and high-performance network controller supporting 6 fully bidirectional off-board links over a 3D torus topology. The first release of APEnet+ (named V4) was a board based on a 40 nm Altera FPGA, integrating 6 channels at 34 Gbps of raw bandwidth per direction and a PCIe Gen2 x8 host interface. It has been the first-of-its-kind device to implement an RDMA protocol to directly read/write data from/to Fermi and Kepler NVIDIA GPUs using NVIDIA peer-to-peer and GPUDirect RDMA protocols, obtaining real zero-copy GPU-to-GPU transfers over the network. The latest generation of APEnet+ systems (now named V5) implements a PCIe Gen3 x8 host interface on a 28 nm Altera Stratix V FPGA, with multi-standard fast transceivers (up to 14.4 Gbps) and an increased amount of configurable internal resources and hardware IP cores to support main interconnection standard protocols. Herein we present the APEnet+ V5 architecture, the status of its hardware and its system software design. Both its Linux Device Driver and the low-level libraries have been redeveloped to support the PCIe Gen3 protocol, introducing optimizations and solutions based on hardware/software co-design.

  10. [Design and implementation of real-time processing platform for movement error correction of hyperspectrual imaging].

    PubMed

    Yu, Tao; Hu, Bing-liang; Gao, Xiao-hui; Wei, Ru-yi; Jing, Juan-juan

    2012-08-01

    The approach that deals with compressed and packed image data transmitted from satellite to the ground is too slow for real-time application occasion, it also has huge image, multi-processing step and complexity recovery arithmetic synchronously, so it is urgent to build accurate and fast data processing platform for real-time processing. For the moment, the platform for data recovery and error correction is much less, the so-called successful platform may directly affect the effect of target detection and identification because of processing speed, precision, flexibility, configuration and upgrade. The platform we build is to set spatial modulation spectrometer as the research goal, We design and implement a hardware platform based on Xilinx Virtex-5 FPGA, It is combined with ISE IP soft-core resources which is configurable, high-precision and flexible by focusing on analyzing key aspects of the hardware platform. And the relevant test data were drawn, then a good way for spectrum recovery and error correction was explored. PMID:23156797

  11. Design of Application-Specific Instructions and Hardware Accelerator for Reed-Solomon Codecs

    NASA Astrophysics Data System (ADS)

    Lee, Jung H.; Lee, Jaesung; Sunwoo, Myung H.

    2003-12-01

    This paper presents new application-specific digital signal processor (ASDSP) instructions and their hardware accelerator to efficiently implement Reed-Solomon (RS) encoding and decoding, which is one of the most widely used forward error control (FEC) algorithms. The proposed ASDSP architecture can implement various programmable primitive polynomials, and thus, hardwired RS codecs can be replaced. The new instructions and their hardware accelerator perform Galois field (GF) operations using the proposed GF multiplier and adder. Therefore, the proposed digital signal processor (DSP) architecture can significantly reduce the number of clock cycles compared with existing DSP chips. The proposed GF multiplier was implemented using the Faraday 0.25[InlineEquation not available: see fulltext.]m standard cell library and it can perform RS decoding at a rate up to 228.1 Mbps at 130 MHz.

  12. Design of the high-speed framing, FEC, and interleaving hardware used in a 5.4km free-space optical communication experiment

    NASA Astrophysics Data System (ADS)

    Greco, Joseph A.

    2009-08-01

    The forward error correction (FEC) and interleaver realizations used in a 5.4 km horizontal-path link experiment incorporated several unique elements that were specifically tailored to address turbulence-induced fading. To facilitate optimization studies, this hardware was designed to afford a high degree of flexibility in the FEC code structure and interleaver length. An essential aspect of this structure was the standards-compliant client interface, which provided seamless connectivity to fiber-based terrestrial networks. Through the use of an OTU1 (2.667 Gbaud) architecture with nonstandard interleaving, error-free transmission was achieved in the presence of strong scintillation that produced fade events that frequently exceeded 10 ms in duration. This work was sponsored by the Department of Defense, RRCO DDR&E, under Air Force Contract FA8721-05-C-0002. Opinions, interpretations, conclusions and recommendations are those of the authors and are not necessarily endorsed by the United States Government.

  13. Hardware Controller DNA Synthesizer

    Energy Science and Technology Software Center (ESTSC)

    1995-07-27

    The program controls the operation of various hardware components of an automatic 12-channel parrallel oligosynthesizer. This involves accepting information regarding the DNA sequence to be generated and converting this into a series of instructions to I/O ports to actuate the appropriate hardware components. The design and function of the software is specific to a particular hardware platform and has no utility for controlling other configurations.

  14. Study of orbit correction for eRHIC FFAG design

    SciTech Connect

    Liu, C.; Hao, Y.; Litvinenko, V.; Meot, F.; Minty, M.; Ptitsyn, V.; Trbojevic, D.

    2015-05-03

    The unique feature of the orbits in the eRHIC Fixed Field Alternating Gradient (FFAG) design is that multiple accelerating and decelerating bunches pass through the same magnets with different horizontal offsets. Therefore, it is critical for the eRHIC FFAG to correct multiple orbits in the same vacuum pipe for better spin transmission and alignment of colliding beams. In this report, the effects on orbits from multiple error sources will be studied. The orbit correction method will be described and results will be presented.

  15. Design and hardware-in-loop implementation of collision avoidance algorithms for heavy commercial road vehicles

    NASA Astrophysics Data System (ADS)

    Rajaram, Vignesh; Subramanian, Shankar C.

    2016-07-01

    An important aspect from the perspective of operational safety of heavy road vehicles is the detection and avoidance of collisions, particularly at high speeds. The development of a collision avoidance system is the overall focus of the research presented in this paper. The collision avoidance algorithm was developed using a sliding mode controller (SMC) and compared to one developed using linear full state feedback in terms of performance and controller effort. Important dynamic characteristics such as load transfer during braking, tyre-road interaction, dynamic brake force distribution and pneumatic brake system response were considered. The effect of aerodynamic drag on the controller performance was also studied. The developed control algorithms have been implemented on a Hardware-in-Loop experimental set-up equipped with the vehicle dynamic simulation software, IPG/TruckMaker®. The evaluation has been performed for realistic traffic scenarios with different loading and road conditions. The Hardware-in-Loop experimental results showed that the SMC and full state feedback controller were able to prevent the collision. However, when the discrepancies in the form of parametric variations were included, the SMC provided better results in terms of reduced stopping distance and lower controller effort compared to the full state feedback controller.

  16. Groundwater modeling in RCRA assessment, corrective action design and evaluation

    SciTech Connect

    Rybak, I.; Henley, W.

    1995-12-31

    Groundwater modeling was conducted to design, implement, modify, and terminate corrective action at several RCRA sites in EPA Region 4. Groundwater flow, contaminant transport and unsaturated zone air flow models were used depending on the complexity of the site and the corrective action objectives. Software used included Modflow, Modpath, Quickflow, Bioplume 2, and AIR3D. Site assessment data, such as aquifer properties, site description, and surface water characteristics for each facility were used in constructing the models and designing the remedial systems. Modeling, in turn, specified additional site assessment data requirements for the remedial system design. The specific purpose of computer modeling is discussed with several case studies. These consist, among others, of the following: evaluation of the mechanism of the aquifer system and selection of a cost effective remedial option, evaluation of the capture zone of a pumping system, prediction of the system performance for different and difficult hydrogeologic settings, evaluation of the system performance, and trouble-shooting for the remedial system operation. Modeling is presented as a useful tool for corrective action system design, performance, evaluation, and trouble-shooting. The case studies exemplified the integration of diverse data sources, understanding the mechanism of the aquifer system, and evaluation of the performance of alternative remediation systems in a cost-effective manner. Pollutants of concern include metals and PAHs.

  17. SIMPL Systems, or: Can We Design Cryptographic Hardware without Secret Key Information?

    NASA Astrophysics Data System (ADS)

    Rührmair, Ulrich

    This paper discusses a new cryptographic primitive termed SIMPL system. Roughly speaking, a SIMPL system is a special type of Physical Unclonable Function (PUF) which possesses a binary description that allows its (slow) public simulation and prediction. Besides this public key like functionality, SIMPL systems have another advantage: No secret information is, or needs to be, contained in SIMPL systems in order to enable cryptographic protocols - neither in the form of a standard binary key, nor as secret information hidden in random, analog features, as it is the case for PUFs. The cryptographic security of SIMPLs instead rests on (i) a physical assumption on their unclonability, and (ii) a computational assumption regarding the complexity of simulating their output. This novel property makes SIMPL systems potentially immune against many known hardware and software attacks, including malware, side channel, invasive, or modeling attacks.

  18. Design of a hardware track finder (Fast Tracker) for the ATLAS trigger

    NASA Astrophysics Data System (ADS)

    Cavaliere, V.; Adelman, J.; Albicocco, P.; Alison, J.; Ancu, L. S.; Anderson, J.; Andari, N.; Andreani, A.; Andreazza, A.; Annovi, A.; Antonelli, M.; Asbah, N.; Atkinson, M.; Baines, J.; Barberio, E.; Beccherle, R.; Beretta, M.; Bertolucci, F.; Biesuz, N. V.; Blair, R.; Bogdan, M.; Boveia, A.; Britzger, D.; Bryant, P.; Burghgrave, B.; Calderini, G.; Camplani, A.; Cavasinni, V.; Chakraborty, D.; Chang, P.; Cheng, Y.; Citraro, S.; Citterio, M.; Crescioli, F.; Dawe, N.; Dell'Orso, M.; Donati, S.; Dondero, P.; Drake, G.; Gadomski, S.; Gatta, M.; Gentsos, C.; Giannetti, P.; Gkaitatzis, S.; Gramling, J.; Howarth, J. W.; Iizawa, T.; Ilic, N.; Jiang, Z.; Kaji, T.; Kasten, M.; Kawaguchi, Y.; Kim, Y. K.; Kimura, N.; Klimkovich, T.; Kolb, M.; Kordas, K.; Krizka, K.; Kubota, T.; Lanza, A.; Li, H. L.; Liberali, V.; Lisovyi, M.; Liu, L.; Love, J.; Luciano, P.; Luongo, C.; Magalotti, D.; Maznas, I.; Meroni, C.; Mitani, T.; Nasimi, H.; Negri, A.; Neroutsos, P.; Neubauer, M.; Nikolaidis, S.; Okumura, Y.; Pandini, C.; Petridou, C.; Piendibene, M.; Proudfoot, J.; Rados, P.; Roda, C.; Rossi, E.; Sakurai, Y.; Sampsonidis, D.; Saxon, J.; Schmitt, S.; Schoening, A.; Shochet, M.; Shojaii, S.; Soltveit, H.; Sotiropoulou, C. L.; Stabile, A.; Swiatlowski, M.; Tang, F.; Taylor, P. T.; Testa, M.; Tompkins, L.; Vercesi, V.; Volpi, G.; Wang, R.; Watari, R.; Webster, J.; Wu, X.; Yorita, K.; Yurkewicz, A.; Zeng, J. C.; Zhang, J.; Zou, R.

    2016-02-01

    The use of tracking information at the trigger level in the LHC Run II period is crucial for the trigger and data acquisition system and will be even more so as contemporary collisions that occur at every bunch crossing will increase in Run III. The Fast TracKer is part of the ATLAS trigger upgrade project; it is a hardware processor that will provide every Level-1 accepted event (100 kHz) and within 100μs, full tracking information for tracks with momentum as low as 1 GeV . Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance.

  19. Hardware description languages

    NASA Technical Reports Server (NTRS)

    Tucker, Jerry H.

    1994-01-01

    Hardware description languages are special purpose programming languages. They are primarily used to specify the behavior of digital systems and are rapidly replacing traditional digital system design techniques. This is because they allow the designer to concentrate on how the system should operate rather than on implementation details. Hardware description languages allow a digital system to be described with a wide range of abstraction, and they support top down design techniques. A key feature of any hardware description language environment is its ability to simulate the modeled system. The two most important hardware description languages are Verilog and VHDL. Verilog has been the dominant language for the design of application specific integrated circuits (ASIC's). However, VHDL is rapidly gaining in popularity.

  20. Design of an integrated hardware interface for AOSLO image capture and cone-targeted stimulus delivery

    PubMed Central

    Yang, Qiang; Arathorn, David W.; Tiruveedhula, Pavan; Vogel, Curtis R.; Roorda, Austin

    2010-01-01

    We demonstrate an integrated FPGA solution to project highly stabilized, aberration-corrected stimuli directly onto the retina by means of real-time retinal image motion signals in combination with high speed modulation of a scanning laser. By reducing the latency between target location prediction and stimulus delivery, the stimulus location accuracy, in a subject with good fixation, is improved to 0.15 arcminutes from 0.26 arcminutes in our earlier solution. We also demonstrate the new FPGA solution is capable of delivering stabilized large stimulus pattern (up to 256x256 pixels) to the retina. PMID:20721171

  1. An introduction to the BANNING design automation system for shuttle microelectronic hardware development

    NASA Technical Reports Server (NTRS)

    Mcgrady, W. J.

    1979-01-01

    The BANNING MOS design system is presented. It complements rather than supplant the normal design activities associated with the design and fabrication of low-power digital electronic equipment. BANNING is user-oriented and requires no programming experience to use effectively. It provides the user a simulation capability to aid in his circuit design and it eliminates most of the manual operations involved in the layout and artwork generation of integrated circuits. An example of its operation is given and some additional background reading is provided.

  2. Software algorithm and hardware design for real-time implementation of new spectral estimator

    PubMed Central

    2014-01-01

    Background Real-time spectral analyzers can be difficult to implement for PC computer-based systems because of the potential for high computational cost, and algorithm complexity. In this work a new spectral estimator (NSE) is developed for real-time analysis, and compared with the discrete Fourier transform (DFT). Method Clinical data in the form of 216 fractionated atrial electrogram sequences were used as inputs. The sample rate for acquisition was 977 Hz, or approximately 1 millisecond between digital samples. Real-time NSE power spectra were generated for 16,384 consecutive data points. The same data sequences were used for spectral calculation using a radix-2 implementation of the DFT. The NSE algorithm was also developed for implementation as a real-time spectral analyzer electronic circuit board. Results The average interval for a single real-time spectral calculation in software was 3.29 μs for NSE versus 504.5 μs for DFT. Thus for real-time spectral analysis, the NSE algorithm is approximately 150× faster than the DFT. Over a 1 millisecond sampling period, the NSE algorithm had the capability to spectrally analyze a maximum of 303 data channels, while the DFT algorithm could only analyze a single channel. Moreover, for the 8 second sequences, the NSE spectral resolution in the 3-12 Hz range was 0.037 Hz while the DFT spectral resolution was only 0.122 Hz. The NSE was also found to be implementable as a standalone spectral analyzer board using approximately 26 integrated circuits at a cost of approximately $500. The software files used for analysis are included as a supplement, please see the Additional files 1 and 2. Conclusions The NSE real-time algorithm has low computational cost and complexity, and is implementable in both software and hardware for 1 millisecond updates of multichannel spectra. The algorithm may be helpful to guide radiofrequency catheter ablation in real time. PMID:24886214

  3. A Student Experiment Method for Learning the Basics of Embedded Software Technologies Including Hardware/Software Co-design

    NASA Astrophysics Data System (ADS)

    Kambe, Hidetoshi; Mitsui, Hiroyasu; Endo, Satoshi; Koizumi, Hisao

    The applications of embedded system technologies have spread widely in various products, such as home appliances, cellular phones, automobiles, industrial machines and so on. Due to intensified competition, embedded software has expanded its role in realizing sophisticated functions, and new development methods like a hardware/software (HW/SW) co-design for uniting HW and SW development have been researched. The shortfall of embedded SW engineers was estimated to be approximately 99,000 in the year 2006, in Japan. Embedded SW engineers should understand HW technologies and system architecture design as well as SW technologies. However, a few universities offer this kind of education systematically. We propose a student experiment method for learning the basics of embedded system development, which includes a set of experiments for developing embedded SW, developing embedded HW and experiencing HW/SW co-design. The co-design experiment helps students learn about the basics of embedded system architecture design and the flow of designing actual HW and SW modules. We developed these experiments and evaluated them.

  4. FPGA-Based Efficient Hardware/Software Co-Design for Industrial Systems with Consideration of Output Selection

    NASA Astrophysics Data System (ADS)

    Deliparaschos, Kyriakos M.; Michail, Konstantinos; Zolotas, Argyrios C.; Tzafestas, Spyros G.

    2016-05-01

    This work presents a field programmable gate array (FPGA)-based embedded software platform coupled with a software-based plant, forming a hardware-in-the-loop (HIL) that is used to validate a systematic sensor selection framework. The systematic sensor selection framework combines multi-objective optimization, linear-quadratic-Gaussian (LQG)-type control, and the nonlinear model of a maglev suspension. A robustness analysis of the closed-loop is followed (prior to implementation) supporting the appropriateness of the solution under parametric variation. The analysis also shows that quantization is robust under different controller gains. While the LQG controller is implemented on an FPGA, the physical process is realized in a high-level system modeling environment. FPGA technology enables rapid evaluation of the algorithms and test designs under realistic scenarios avoiding heavy time penalty associated with hardware description language (HDL) simulators. The HIL technique facilitates significant speed-up in the required execution time when compared to its software-based counterpart model.

  5. Design requirements for SRB production control system. Volume 3: Package evaluation, modification and hardware

    NASA Technical Reports Server (NTRS)

    1981-01-01

    The software package evaluation was designed to analyze commercially available, field-proven, production control or manufacturing resource planning management technology and software package. The analysis was conducted by comparing SRB production control software requirements and conceptual system design to software package capabilities. The methodology of evaluation and the findings at each stage of evaluation are described. Topics covered include: vendor listing; request for information (RFI) document; RFI response rate and quality; RFI evaluation process; and capabilities versus requirements.

  6. Acoustic Treatment Design Scaling Methods. Volume 3; Test Plans, Hardware, Results, and Evaluation

    NASA Technical Reports Server (NTRS)

    Yu, J.; Kwan, H. W.; Echternach, D. K.; Kraft, R. E.; Syed, A. A.

    1999-01-01

    The ability to design, build, and test miniaturized acoustic treatment panels on scale-model fan rigs representative of the full-scale engine provides not only a cost-savings, but an opportunity to optimize the treatment by allowing tests of different designs. To be able to use scale model treatment as a full-scale design tool, it is necessary that the designer be able to reliably translate the scale model design and performance to an equivalent full-scale design. The primary objective of the study presented in this volume of the final report was to conduct laboratory tests to evaluate liner acoustic properties and validate advanced treatment impedance models. These laboratory tests include DC flow resistance measurements, normal incidence impedance measurements, DC flow and impedance measurements in the presence of grazing flow, and in-duct liner attenuation as well as modal measurements. Test panels were fabricated at three different scale factors (i.e., full-scale, half-scale, and one-fifth scale) to support laboratory acoustic testing. The panel configurations include single-degree-of-freedom (SDOF) perforated sandwich panels, SDOF linear (wire mesh) liners, and double-degree-of-freedom (DDOF) linear acoustic panels.

  7. Hardware and software design for a National Instrument-based magnetic induction tomography system for prospective biomedical applications.

    PubMed

    Wei, Hsin-Yu; Soleimani, Manuchehr

    2012-05-01

    Magnetic induction tomography (MIT) is a new and emerging type of tomography technique that is able to map the passive electromagnetic properties (in particular conductivity) of an object. Excitation coils are used to induce eddy currents in the medium, and the magnetic field produced by the induced eddy current is then sensed by the receiver coils. Because of its non-invasive and contactless feature, it becomes an attractive technique for many applications (especially in biomedical area) compared to traditional contact electrode-based electrical impedance tomography. Due to the low contrast in conductivity between biological tissues, an accurate and stable hardware system is necessary. Most MIT systems in the literature employ external signal generators, power amplifiers and highly stable down-conversion electronics to obtain a satisfactory phase measurement. However, this would increase design complexity substantially. In this paper, a National Instrument-based MIT system is developed at the University of Bath, aiming for biomedical applications. The system utilizes National Instrument products to accomplish all signal driving, switching and data acquisition tasks, which ease the system design whilst providing satisfactory performance. This paper presents a full-scaled medical MIT system, from the sensor and system hardware design, eddy current model verification to the image reconstruction software: the performance of this MIT instrumentation system is characterized in detail, including the system accuracy and system stability. The methods of solving eddy current problem are presented. The reconstructed images of detecting the presence of saline solutions are also included in this paper, which show the capability of national instrument products to be developed into a full-scaled biomedical MIT system, by demonstrating the practical experimental results. PMID:22531316

  8. ACTIVE FILTER HARDWARE DESIGN & PERFORMANCE FOR THE DIII-D PLASMA CONTROL SYSTEM

    SciTech Connect

    SELLERS,D; FERRON,J.R; WALKER,M.L; BROESCH,J.D

    2003-10-01

    OAK-B135 The digital plasma control system (PCS), currently in operation on the DIII-D tokamak, requires inputs from a large number of sensors. Due to the nature of the digitizers and the relative noisy environment from which these signals are derived, each of the 32 signals must be conditioned via an active filter. Two different types of filters, Chebyshev and Bessel with fixed frequencies: 100 Hz Bessel was used for filtering the motional Stark effect diagnostic data. 800 Hz Bessel was designed to filter plasma control data and 1200 Hz Chebyshev is used with closed loop control of choppers. The performance of the plasma control system is greatly influenced by how well the actual filter responses match the software model used in the control system algorithms. This paper addresses the various issues facing the designer in matching the electrical design with the theoretical.

  9. Blackcomb: Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems

    SciTech Connect

    Schreiber, Robert

    2014-11-26

    Summary of technical results of Blackcomb Memory Devices We explored various different memory technologies (STTRAM, PCRAM, FeRAM, and ReRAM). The progress can be classified into three categories, below. Modeling and Tool Releases Various modeling tools have been developed over the last decade to help in the design of SRAM or DRAM-based memory hierarchies. To explore new design opportunities that NVM technologies can bring to the designers, we have developed similar high-level models for NVM, including PCRAMsim [Dong 2009], NVSim [Dong 2012], and NVMain [Poremba 2012]. NVSim is a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies. On the other side, NVMain is a cycle accurate main memory simulator designed to simulate emerging nonvolatile memories at the architectural level. We have released these models as open source tools and provided contiguous support to them. We also proposed PS3-RAM, which is a fast, portable and scalable statistical STT-RAM reliability analysis model [Wen 2012]. Design Space Exploration and Optimization With the support of these models, we explore different device/circuit optimization techniques. For example, in [Niu 2012a] we studied the power reduction technique for the application of ECC scheme in ReRAM designs and proposed to use ECC code to relax the BER (Bit Error Rate) requirement of a single memory to improve the write energy consumption and latency for both 1T1R and cross-point ReRAM designs. In [Xu 2011], we proposed a methodology to design STT-RAM for different optimization goals such as read performance, write performance and write energy by leveraging the trade-off between write current and write time of MTJ. We also studied the tradeoffs in building a reliable crosspoint Re

  10. The J-2X Upper Stage Engine: From Design to Hardware

    NASA Technical Reports Server (NTRS)

    Byrd, Thomas

    2010-01-01

    NASA is well on its way toward developing a new generation of launch vehicles to support of national space policy to retire the Space Shuttle fleet, complete the International Space Station, and return to the Moon as the first step in resuming this nation s exploration of deep space. The Constellation Program is developing the launch vehicles, spacecraft, surface systems, and ground systems to support those plans. Two launch vehicles will support those ambitious plans the Ares I and Ares V. (Figure 1) The J-2X Upper Stage Engine is a critical element of both of these new launchers. This paper will provide an overview of the J-2X design background, progress to date in design, testing, and manufacturing. The Ares I crew launch vehicle will lift the Orion crew exploration vehicle and up to four astronauts into low Earth orbit (LEO) to rendezvous with the space station or the first leg of mission to the Moon. The Ares V cargo launch vehicle is designed to lift a lunar lander into Earth orbit where it will be docked with the Orion spacecraft, and provide the thrust for the trans-lunar journey. While these vehicles bear some visual resemblance to the 1960s-era Saturn vehicles that carried astronauts to the Moon, the Ares vehicles are designed to carry more crew and more cargo to more places to carry out more ambitious tasks than the vehicles they succeed. The government/industry team designing the Ares rockets is mining a rich history of technology and expertise from the Shuttle, Saturn and other programs and seeking commonality where feasible between the Ares crew and cargo rockets as a way to minimize risk, shorten development times, and live within the budget constraints of its original guidance.

  11. Design of a hardware/software FPGA-based driver system for a large area high resolution CCD image sensor

    NASA Astrophysics Data System (ADS)

    Chen, Ying; Xu, Wanpeng; Zhao, Rongsheng; Chen, Xiangning

    2014-09-01

    A hardware/software field programmable gate array (FPGA)-based driver system was proposed and demonstrated for the KAF-39000 large area high resolution charge coupled device (CCD). The requirements of the KAF-39000 driver system were analyzed. The structure of "microprocessor with application specific integrated circuit (ASIC) chips" was implemented to design the driver system. The system test results showed that dual channels of imaging analog data were obtained with a frame rate of 0.87 frame/s. The frequencies of horizontal timing and vertical timing were 22.9 MHz and 28.7 kHz, respectively, which almost reached the theoretical value of 24 MHz and 30 kHz, respectively.

  12. Toward a Performance/Resilience Tool for Hardware/Software Co-Design of High-Performance Computing Systems

    SciTech Connect

    Engelmann, Christian; Naughton, III, Thomas J

    2013-01-01

    xSim is a simulation-based performance investigation toolkit that permits running high-performance computing (HPC) applications in a controlled environment with millions of concurrent execution threads, while observing application performance in a simulated extreme-scale system for hardware/software co-design. The presented work details newly developed features for xSim that permit the injection of MPI process failures, the propagation/detection/notification of such failures within the simulation, and their handling using application-level checkpoint/restart. These new capabilities enable the observation of application behavior and performance under failure within a simulated future-generation HPC system using the most common fault handling technique.

  13. Hardware and software design for an electromagnetic induction tomography (EMT) system for high contrast metal process applications

    NASA Astrophysics Data System (ADS)

    Ma, X.; Peyton, A. J.; Higson, S. R.; Lyons, A.; Dickinson, S. J.

    2006-01-01

    This paper presents the latest development of an EMT system designed for use in the metal production industry such as imaging molten steel flow profiles during continuous casting. The system that has been developed is based on a commercial data acquisition board residing in a PC host computer and programmed in the LabView graphical language. The paper reviews the new EMT hardware electronics and software. The noise effects and the detectability limits of the system are given in the paper followed by the system sensitivity map analysis. Optimal image reconstructions, including the simultaneous iterative reconstruction technique (SIRT) and non-iterative Tikhonov regularization, truncated singular value decomposition (TSVD), are also discussed and applied for the system. The system has been demonstrated in real time (10 frames s-1 for 5 kHz excitation) with test phantoms that represent typical metal flow profiles such as central, annular stream and multiple streams.

  14. Energy efficient engine high pressure turbine test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Halila, E. E.; Lenahan, D. T.; Thomas, T. T.

    1982-01-01

    The high pressure turbine configuration for the Energy Efficient Engine is built around a two-stage design system. Moderate aerodynamic loading for both stages is used to achieve the high level of turbine efficiency. Flowpath components are designed for 18,000 hours of life, while the static and rotating structures are designed for 36,000 hours of engine operation. Both stages of turbine blades and vanes are air-cooled incorporating advanced state of the art in cooling technology. Direct solidification (DS) alloys are used for blades and one stage of vanes, and an oxide dispersion system (ODS) alloy is used for the Stage 1 nozzle airfoils. Ceramic shrouds are used as the material composition for the Stage 1 shroud. An active clearance control (ACC) system is used to control the blade tip to shroud clearances for both stages. Fan air is used to impinge on the shroud casing support rings, thereby controlling the growth rate of the shroud. This procedure allows close clearance control while minimizing blade tip to shroud rubs.

  15. Design and implementation of a new real-time frequency sensor used as hardware countermeasure.

    PubMed

    Jiménez-Naharro, Raúl; Gómez-Galán, Juan Antonio; Sánchez-Raya, Manuel; Gómez-Bravo, Fernando; Pedro-Carrasco, Manuel

    2013-01-01

    A new digital countermeasure against attacks related to the clock frequency is presented. This countermeasure, known as frequency sensor, consists of a local oscillator, a transition detector, a measurement element and an output block. The countermeasure has been designed using a full-custom technique implemented in an Application-Specific Integrated Circuit (ASIC), and the implementation has been verified and characterized with an integrated design using a 0.35 mm standard Complementary Metal Oxide Semiconductor (CMOS) technology (Very Large Scale Implementation-VLSI implementation). The proposed solution is configurable in resolution time and allowed range of period, achieving a minimum resolution time of only 1.91 ns and an initialization time of 5.84 ns. The proposed VLSI implementation shows better results than other solutions, such as digital ones based on semi-custom techniques and analog ones based on band pass filters, all design parameters considered. Finally, a counter has been used to verify the good performance of the countermeasure in avoiding the success of an attack. PMID:24008285

  16. The Effect of Predicted Vehicle Displacement on Ground Crew Task Performance and Hardware Design

    NASA Technical Reports Server (NTRS)

    Atencio, Laura Ashley; Reynolds, David W.

    2011-01-01

    NASA continues to explore new launch vehicle concepts that will carry astronauts to low- Earth orbit to replace the soon-to-be retired Space Transportation System (STS) shuttle. A tall vertically stacked launch vehicle (> or =300 ft) is exposed to the natural environment while positioned on the launch pad. Varying directional winds and vortex shedding cause the vehicle to sway in an oscillating motion. Ground crews working high on the tower and inside the vehicle during launch preparations will be subjected to this motion while conducting critical closeout tasks such as mating fluid and electrical connectors and carrying heavy objects. NASA has not experienced performing these tasks in such environments since the Saturn V, which was serviced from a movable (but rigid) service structure; commercial launchers are likewise attended by a service structure that moves away from the vehicle for launch. There is concern that vehicle displacement may hinder ground crew operations, impact the ground system designs, and ultimately affect launch availability. The vehicle sway assessment objective is to replicate predicted frequencies and displacements of these tall vehicles, examine typical ground crew tasks, and provide insight into potential vehicle design considerations and ground crew performance guidelines. This paper outlines the methodology, configurations, and motion testing performed while conducting the vehicle displacement assessment that will be used as a Technical Memorandum for future vertically stacked vehicle designs.

  17. Preliminary control law and hardware designs for a ride quality augmentation system for commuter aircraft. Phase 2

    NASA Technical Reports Server (NTRS)

    Davis, D. J.; Linse, D. J.; Suikat, R.; Entz, D. P.

    1986-01-01

    The continued investigation of the design of Ride Quality Augmentation Systems (RQAS) for commuter aircraft is described. The purpose of these RQAS is the reduction of the vertical and lateral acceleration response of the aircraft due to atmospheric turbulence by the application of active control. The current investigations include the refinement of the sample data feedback control laws based on the control-rate-weighting and output-weighting optimal control design techniqes. These control designs were evaluated using aircraft time simulations driven by Dryden spectra turbulence. Fixed gain controllers were tested throughout the aircrft operating envelope. The preliminary design of the hardware modifications necessary to implement and test the RQAS on a commuter aircraft is included. These include a separate surface elevator and the flap modifications to provide both direct lift and roll control. A preliminary failure mode investigation was made for the proposed configuration. The results indicate that vertical acceleration reductions of 45% and lateral reductions of more than 50% are possible. A fixed gain controller appears to be feasible with only minor response degradation.

  18. Design and Implementation of a Hardware Channel Board for Holographic Data Storage

    NASA Astrophysics Data System (ADS)

    Yoon, Pilsang; Kim, Haksun; Park, Jooyoun; Jung, Heungsang; Park, Gwitae

    2009-03-01

    A channel board has been designed, manufactured, and used for real-time recording and reading processes. The channel coding and decoding algorithms were implemented on Xilinx field-programmable gate array (FPGA) devices. For fast data transmission between the channel board and personal computer (PC), a universal serial bus (USB) 2.0 interface is installed in the channel board. The firmware and device driver for USB interface achieved a transfer rate of 34 Mbyte/s. A holographic data storage system records a video stream, which was successfully retrieved and reconstructed without error.

  19. Hardware-Based Non-Optimum Factors for Launch Vehicle Structural Design

    NASA Technical Reports Server (NTRS)

    Wu, K. Chauncey; Cerro, Jeffrey A.

    2010-01-01

    During aerospace vehicle conceptual and preliminary design, empirical non-optimum factors are typically applied to predicted structural component weights to account for undefined manufacturing and design details. Non-optimum factors are developed here for 32 aluminum-lithium 2195 orthogrid panels comprising the liquid hydrogen tank barrel of the Space Shuttle External Tank using measured panel weights and manufacturing drawings. Minimum values for skin thickness, axial and circumferential blade stiffener thickness and spacing, and overall panel thickness are used to estimate individual panel weights. Panel non-optimum factors computed using a coarse weights model range from 1.21 to 1.77, and a refined weights model (including weld lands and skin and stiffener transition details) yields non-optimum factors of between 1.02 and 1.54. Acreage panels have an average 1.24 non-optimum factor using the coarse model, and 1.03 with the refined version. The observed consistency of these acreage non-optimum factors suggests that relatively simple models can be used to accurately predict large structural component weights for future launch vehicles.

  20. The design and fabrication of the Centaur neutral buoyancy trainer and related hardware

    NASA Technical Reports Server (NTRS)

    Ware, Alan S.; Hollingsworth, Michael

    1986-01-01

    Two full scale mockups of the Centaur upper stage were designed, fabricated and delivered to NASA. One was the Centaur Weightless Environment Training Facility (WETF) trainer and the other was the Centaur 1-G mockup. The Centaur upper stage booster is designed to carry the spacecraft Galileo to Jupiter, and the spacecraft Ulysses to an orbit around the Sun after launch from the Space Shuttle. The flight vehicle has several Extravehicular Activity (EVA) contingency tasks that require crew training. This need for crew training generated the requirement for the Centaur WETF crew trainer, which is high fidelity in areas of expected crew interface. During the production of the Centaur WETF crew trainer, the need for a jumper cable from Centaur to the Orbiter was identified. This EVA contingency task would be the installation of a cable from the Orbiter cargo bay sill to various command data boxes on Centaur to allow crew control deployment should a failure occur. This task required the upgrading of volumetric boxes on the trainer to a high fidelity configuration including electrical connector installation and cable routing.

  1. Hardly Hardware

    ERIC Educational Resources Information Center

    Lott, Debra

    2007-01-01

    In a never-ending search for new and inspirational still-life objects, the author discovered that home improvement retailers make great resources for art teachers. Hardware and building materials are inexpensive and have interesting and variable shapes. She especially liked the dryer-vent coils and the electrical conduit. These items can be…

  2. Designing an Ergonomically Correct CNC Workstation on a Shoe String Budget.

    ERIC Educational Resources Information Center

    Lightner, Stan

    2001-01-01

    Describes research to design and construct ergonomically correct work stations for Computer Numerical Control machine tools. By designing ergonomically correct work stations, industrial technology teachers help protect students from repetitive motion injuries. (Contains 12 references.) (JOW)

  3. Final Report: Enabling Exascale Hardware and Software Design through Scalable System Virtualization

    SciTech Connect

    Bridges, Patrick G.

    2015-02-01

    In this grant, we enhanced the Palacios virtual machine monitor to increase its scalability and suitability for addressing exascale system software design issues. This included a wide range of research on core Palacios features, large-scale system emulation, fault injection, perfomrance monitoring, and VMM extensibility. This research resulted in large number of high-impact publications in well-known venues, the support of a number of students, and the graduation of two Ph.D. students and one M.S. student. In addition, our enhanced version of the Palacios virtual machine monitor has been adopted as a core element of the Hobbes operating system under active DOE-funded research and development.

  4. [The hardware design of a portable gastrointestinal wireless endoscope image receiver].

    PubMed

    Zhang, Si-jie; Zeng, Xiao-ping; Zheng, Xiao-lin; Xie, Li-ying; Peng, Cheng-lin

    2006-05-01

    The portable gastrointestinal wireless endoscope image receiver is developed and based on TMS320C6211 DSP. It can receive and demodulate the modulated signal which is transmitted from the camera-capsule, and then output the video signal. The synchronizing signals offered by SAA7114H are made best of and are used to design the time logic circuit. The fitful video signal can be collected under the control of the time logic circuit. The circuit can automatically get rid of useless blank data and only collect effective and good-quality video signals, and storage them in CF card. In addition, the image signal can be processed and compressed by DSP, and thus the data storage space and the data- analyzing time can be saved. PMID:16929775

  5. Design of software and hardware components for a six-degrees of freedom optical position sensor

    SciTech Connect

    Garcia, F.N.

    1997-06-01

    This report summarizes the evaluation of a fully compatible and operational data acquisition system for a six-degrees of freedom optical sensor (SixDOF). The SixDOF, developed at Lawrence Livermore National Laboratory by Charles Vann, is capable of tracking an object`s position in all its six degrees of freedom without any datum specification by means of two reflective surfaces mounted on the object. To make the SixDOF operational and thus validate its underlying physics, a signal processing system has been designed so that information from the sensor is transferred accurately and efficiently to a computer. In addition, a six-degrees of freedom positioning stage has been built in efforts to calibrate the sensor in real time. A crucial design constraint is the necessity to build the complete data acquisition system so that it be small and most importantly portable. The prototype of the SixDOF system proved to be capable of crudely detecting changes in the position of an object in all six spatial degrees of freedom. An accuracy of around 0.5 mm is estimated presently even though the position of the two reflectors on the object is seen to significantly influence the accuracy of the sensor. The resolution of the sensor is not quite understood yet because of uncertainties in the actual spot size of the laser, however, field of the view has been seen to increase as the resolution decreases. The decoupling (calibration) of the sensor data proved to be rather successful although some coupling still exists. This coupling, however, is almost certain to come from the crudeness in the alignment of the optics within the sensor.

  6. Correction.

    PubMed

    2015-11-01

    In the article by Heuslein et al, which published online ahead of print on September 3, 2015 (DOI: 10.1161/ATVBAHA.115.305775), a correction was needed. Brett R. Blackman was added as the penultimate author of the article. The article has been corrected for publication in the November 2015 issue. PMID:26490278

  7. Design and implementation of coating hardware for the Hobby-Eberly Telescope wide-field corrector

    NASA Astrophysics Data System (ADS)

    Good, John; Lee, Hanshin; Hill, Gary J.; Vattiat, Brian; Perry, David; Kriel, Herman; Savage, Richard

    2014-07-01

    A major upgrade of the HET is in progress that will substantially increase the pupil size to 10 meters and the field of view to 22 arc-minutes by replacing the spherical aberration corrector. The new Wide Field Corrector is a 4-element assembly weighing 750kg and measuring 1.34 meters diameter by 2.1 meter in length. Special fixtures were required in order to support the mirrors of the Wide-Field Corrector and adapt them to the coaters chamber, during the vacuum coating process. For the 1 meter-class mirrors, the only suitable support interface was located on a 80mm wide cylindrical surface on the periphery of each mirror. The vacuum compatible system had to support the mirrors with the surface facing downward, and accommodate thermal ranges from ambient to 100C without inducing stresses in the substrate. The fixture also had to accommodate washing, as well as support of witness samples during testing and production runs, and provide masking for alignment fixtures in the center apertures of each mirror. Design principles, materials, implementation details, as well as lessons learned are covered*.

  8. Reducing NPR 7120.5D to Practice: Transitioning from Design Reviews to the SIR Hardware Review

    NASA Technical Reports Server (NTRS)

    Taylor, Randall

    2011-01-01

    The Gravity Recovery And Interior Laboratory (GRAIL) mission was the first Jet Propulsion Laboratory (JPL) project initiated under NASA's revised rules for space flight project management, NPR 7120.5D, "NASA Space Flight Program and Project Management Requirements." NASA selected GRAIL through a competitive Announcement of Opportunity process and funded its Phase B Preliminary Design effort. The team's first major milestone was a JPL institutional milestone, the Project Mission System Review (PMSR), which proved an excellent tune-up for the end-of-Phase-B NASA life-cycle review, the Preliminary Design Review (PDR). Building on JPL experience on the Prometheus and Juno projects, the team successfully organized for and conducted these reviews on an aggressive schedule. For the Project Critical Design Review (CDR), lessons learned from the PDR and updated Standing Review Board (SRB) practices from the Agency were factored into the review preparation effort. Additionally, the review was held at the Principal Investigator's institution, the Massachusetts Institute of Technology, rather than at the project management center (JPL), which necessitated additional cross-country coordination steps. The PMSR, PDR, and CDR were design reviews and largely paper-oriented. For the System Integration Review (SIR), the project needed to transition to a hardware review and deal with paper in a very different manner. While many of the practices employed for the design reviews were modified and retained (e.g., review preparation team, gate products management, pre-reviews, SRB coordination), the review agenda, presentation style, and slide templates were significantly changed. A key success factor concerned the handling of project open paper, which was succinctly and effectively communicated to the SRB in presentations.This paper provides a brief overview of the GRAIL mission and its project management challenges, provides a detailed description of project SIR preparation and execution

  9. Design of Improved Error Correction Decoder Using Error Detecting Information of Modulation Code in Digital Versatile Disc Systems

    NASA Astrophysics Data System (ADS)

    Lee, Joohyun; Lee, Jaejin

    2006-02-01

    We present a powerful error control decoder which can be used in all kinds of digital versatile disk (DVD) systems. The decoder exploits the error information from the modulation decoder in order to increase the error correcting capability. We can identify that the modulation decoder in DVD system can detect errors more than 60% of total errors when burst errors are occurred. In results, for a decoded block, error correcting capability of the proposed scheme is improved up to 25% more than that of the original error control decoder. Also, a pipeline-balanced Reed-Solomon Product Code (RSPC) decoder with a low hardware complexity is designed to maximize the throughput. The maximum throughput of the RSPC decoder is 740 Mbps at 100 MHz and the number of gate counts is 20.3 K for RS(182,172,11) decoder and 30.7 K for RS(208,192,17) decoder, respectively.

  10. Correction.

    PubMed

    2015-12-01

    In the article by Narayan et al (Narayan O, Davies JE, Hughes AD, Dart AM, Parker KH, Reid C, Cameron JD. Central aortic reservoir-wave analysis improves prediction of cardiovascular events in elderly hypertensives. Hypertension. 2015;65:629–635. doi: 10.1161/HYPERTENSIONAHA.114.04824), which published online ahead of print December 22, 2014, and appeared in the March 2015 issue of the journal, some corrections were needed.On page 632, Figure, panel A, the label PRI has been corrected to read RPI. In panel B, the text by the upward arrow, "10% increase in kd,” has been corrected to read, "10% decrease in kd." The corrected figure is shown below.The authors apologize for these errors. PMID:26558821

  11. Standard gas hardware

    NASA Technical Reports Server (NTRS)

    Spencer, Stan

    1995-01-01

    The Sierra College Space Technology Program is currently building their third GAS payload in addition to a small satellite. The project is supported by an ARPA/TRP grant. One aspect of the grant is the design of standard hardware for Get Away Specials (GAS) payloads. A standard structure has been designed and work is progressing on a standard battery box and computer.

  12. Correction

    NASA Astrophysics Data System (ADS)

    1995-04-01

    Seismic images of the Brooks Range, Arctic Alaska, reveal crustal-scale duplexing: Correction Geology, v. 23, p. 65 68 (January 1995) The correct Figure 4A, for the loose insert, is given here. See Figure 4A below. Corrected inserts will be available to those requesting copies of the article from the senior author, Gary S. Fuis, U.S. Geological Survey, 345 Middlefield Road, Menlo Park, CA 94025. Figure 4A. P-wave velocity model of Brooks Range region (thin gray contours) with migrated wide-angle reflections (heavy red lines) and migreated vertical-incidence reflections (short black lines) superimposed. Velocity contour interval is 0.25 km/s; 4,5, and 6 km/s contours are labeled. Estimated error in velocities is one contour interval. Symbols on faults shown at top are as in Figure 2 caption.

  13. Correction.

    PubMed

    2016-02-01

    Neogi T, Jansen TLTA, Dalbeth N, et al. 2015 Gout classification criteria: an American College of Rheumatology/European League Against Rheumatism collaborative initiative. Ann Rheum Dis 2015;74:1789–98. The name of the 20th author was misspelled. The correct spelling is Janitzia Vazquez-Mellado. We regret the error. PMID:26881284

  14. On two new trends in evolvable hardware: employment of HDL-based structuring, and design of multi-functional circuits

    NASA Technical Reports Server (NTRS)

    Stoica, A.; Keymeulen, D.; Zebulum, R. S.; Ferguson, M. I.; Guo, X.

    2002-01-01

    This paper comments on some directions of growth for evolvable hardware, proposes research directions that address the scalability problem and gives examples of results in novel areas approached by EHW.

  15. Correction.

    PubMed

    2016-02-01

    In the article by Guessous et al (Guessous I, Pruijm M, Ponte B, Ackermann D, Ehret G, Ansermot N, Vuistiner P, Staessen J, Gu Y, Paccaud F, Mohaupt M, Vogt B, Pechère-Bertschi A, Martin PY, Burnier M, Eap CB, Bochud M. Associations of ambulatory blood pressure with urinary caffeine and caffeine metabolite excretions. Hypertension. 2015;65:691–696. doi: 10.1161/HYPERTENSIONAHA.114.04512), which published online ahead of print December 8, 2014, and appeared in the March 2015 issue of the journal, a correction was needed.One of the author surnames was misspelled. Antoinette Pechère-Berstchi has been corrected to read Antoinette Pechère-Bertschi.The authors apologize for this error. PMID:26763012

  16. Hardware-software-co-design of parallel and distributed systems using a behavioural programming and multi-process model with high-level synthesis

    NASA Astrophysics Data System (ADS)

    Bosse, Stefan

    2011-05-01

    A new design methodology for parallel and distributed embedded systems is presented using the behavioural hardware compiler ConPro providing an imperative programming model based on concurrently communicating sequential processes (CSP) with an extensive set of interprocess-communication primitives and guarded atomic actions. The programming language and the compiler-based synthesis process enables the design of constrained power- and resourceaware embedded systems with pure Register-Transfer-Logic (RTL) efficiently mapped to FPGA and ASIC technologies. Concurrency is modelled explicitly on control- and datapath level. Additionally, concurrency on data-path level can be automatically explored and optimized by different schedulers. The CSP programming model can be synthesized to hardware (SoC) and software (C,ML) models and targets. A common source for both hardware and software implementation with identical functional behaviour is used. Processes and objects of the entire design can be distributed on different hardware and software platforms, for example, several FPGA components and software executed on several microprocessors, providing a parallel and distributed system. Intersystem-, interprocess-, and object communication is automatically implemented with serial links, not visible on programming level. The presented design methodology has the benefit of high modularity, freedom of choice of target technologies, and system architecture. Algorithms can be well matched to and distributed on different suitable execution platforms and implementation technologies, using a unique programming model, providing a balance of concurrency and resource complexity. An extended case study of a communication protocol used in high-density sensor-actuator networks should demonstrate and compare the design of a hardware and software target. The communication protocol is suited for high-density intra-and interchip networks.

  17. A framework for the design and specification of hard real-time, hardware-in-the-loop simulations of large, avionic systems

    NASA Astrophysics Data System (ADS)

    Ricks, Kenneth Gerald

    High-level design tools for the design and specification of avionic systems and real-time systems currently exist. However, real-time, hardware-in-the-loop simulations of avionic systems are based upon principles fundamentally different than those used to design avionic systems and represent a specialized case of real-time systems. As a result, the high-level software tools used to design avionic systems and real-time systems cannot be applied to the design of real-time, hardware-in-the-loop simulations of avionic systems. For this reason, such simulations of avionic systems should not be considered part of the domain containing avionic systems or general-purpose real-time systems and should be considered as an application domain unto itself for which design tools are unavailable. To fill this void, this dissertation proposes a framework for the design and specification of real-time, hardware-in-the-loop simulations of avionic systems. This framework is based upon a new specification language called the Simulation Architecture Description Language. This specification language is a graphical language with constructs and semantics defined to provide the user with the capability to completely define the simulation and its software execution characteristics at various levels of abstraction. The language includes a new method for combining precedence constraints for a single software process. These semantics provide a more accurate description of the behavior of software systems having a dynamic job structure than existing semantics. An environment that supports the execution of simulation software having the semantics defined within this language is also described. A toolset that interfaces to the language and provides additional functionality such as design analysis, schedulability analysis, and simulation file generation is also discussed. This framework provides a complete design and specification environment for real-time, hardware-in-the-loop simulations of

  18. Correction.

    PubMed

    2015-05-22

    The Circulation Research article by Keith and Bolli (“String Theory” of c-kitpos Cardiac Cells: A New Paradigm Regarding the Nature of These Cells That May Reconcile Apparently Discrepant Results. Circ Res. 2015:116:1216-1230. doi: 10.1161/CIRCRESAHA.116.305557) states that van Berlo et al (2014) observed that large numbers of fibroblasts and adventitial cells, some smooth muscle and endothelial cells, and rare cardiomyocytes originated from c-kit positive progenitors. However, van Berlo et al reported that only occasional fibroblasts and adventitial cells derived from c-kit positive progenitors in their studies. Accordingly, the review has been corrected to indicate that van Berlo et al (2014) observed that large numbers of endothelial cells, with some smooth muscle cells and fibroblasts, and more rarely cardiomyocytes, originated from c-kit positive progenitors in their murine model. The authors apologize for this error, and the error has been noted and corrected in the online version of the article, which is available at http://circres.ahajournals.org/content/116/7/1216.full ( PMID:25999426

  19. Correction

    NASA Astrophysics Data System (ADS)

    1998-12-01

    Alleged mosasaur bite marks on Late Cretaceous ammonites are limpet (patellogastropod) home scars Geology, v. 26, p. 947 950 (October 1998) This article had the following printing errors: p. 947, Abstract, line 11, “sepia” should be “septa” p. 947, 1st paragraph under Introduction, line 2, “creep” should be “deep” p. 948, column 1, 2nd paragraph, line 7, “creep” should be “deep” p. 949, column 1, 1st paragraph, line 1, “creep” should be “deep” p. 949, column 1, 1st paragraph, line 5, “19774” should be “1977)” p. 949, column 1, 4th paragraph, line 7, “in particular” should be “In particular” CORRECTION Mammalian community response to the latest Paleocene thermal maximum: An isotaphonomic study in the northern Bighorn Basin, Wyoming Geology, v. 26, p. 1011 1014 (November 1998) An error appeared in the References Cited. The correct reference appears below: Fricke, H. C., Clyde, W. C., O'Neil, J. R., and Gingerich, P. D., 1998, Evidence for rapid climate change in North America during the latest Paleocene thermal maximum: Oxygen isotope compositions of biogenic phosphate from the Bighorn Basin (Wyoming): Earth and Planetary Science Letters, v. 160, p. 193 208.

  20. NASA HUNCH Hardware

    NASA Technical Reports Server (NTRS)

    Hall, Nancy R.; Wagner, James; Phelps, Amanda

    2014-01-01

    What is NASA HUNCH? High School Students United with NASA to Create Hardware-HUNCH is an instructional partnership between NASA and educational institutions. This partnership benefits both NASA and students. NASA receives cost-effective hardware and soft goods, while students receive real-world hands-on experiences. The 2014-2015 was the 12th year of the HUNCH Program. NASA Glenn Research Center joined the program that already included the NASA Johnson Space Flight Center, Marshall Space Flight Center, Langley Research Center and Goddard Space Flight Center. The program included 76 schools in 24 states and NASA Glenn worked with the following five schools in the HUNCH Build to Print Hardware Program: Medina Career Center, Medina, OH; Cattaraugus Allegheny-BOCES, Olean, NY; Orleans Niagara-BOCES, Medina, NY; Apollo Career Center, Lima, OH; Romeo Engineering and Tech Center, Washington, MI. The schools built various parts of an International Space Station (ISS) middeck stowage locker and learned about manufacturing process and how best to build these components to NASA specifications. For the 2015-2016 school year the schools will be part of a larger group of schools building flight hardware consisting of 20 ISS middeck stowage lockers for the ISS Program. The HUNCH Program consists of: Build to Print Hardware; Build to Print Soft Goods; Design and Prototyping; Culinary Challenge; Implementation: Web Page and Video Production.

  1. Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description

    NASA Astrophysics Data System (ADS)

    Algredo-Badillo, Ignacio; Feregrino-Uribe, Claudia; Cumplido, René; Morales-Sandoval, Miguel

    MD5 is a cryptographic algorithm used for authentication. When implemented in hardware, the performance is affected by the data dependency of the iterative compression function. In this paper, a new functional description is proposed with the aim of achieving higher throughput by mean of reducing the critical path and latency. This description can be used in similar structures of other hash algorithms, such as SHA-1, SHA-2 and RIPEMD-160, which have comparable data dependence. The proposed MD5 hardware architecture achieves a high throughput/area ratio, results of implementation in an FPGA are presented and discussed, as well as comparisons against related works.

  2. A novel visual hardware behavioral language

    NASA Technical Reports Server (NTRS)

    Li, Xueqin; Cheng, H. D.

    1992-01-01

    Most hardware behavioral languages just use texts to describe the behavior of the desired hardware design. This is inconvenient for VLSI designers who enjoy using the schematic approach. The proposed visual hardware behavioral language has the ability to graphically express design information using visual parallel models (blocks), visual sequential models (processes) and visual data flow graphs (which consist of primitive operational icons, control icons, and Data and Synchro links). Thus, the proposed visual hardware behavioral language can not only specify hardware concurrent and sequential functionality, but can also visually expose parallelism, sequentiality, and disjointness (mutually exclusive operations) for the hardware designers. That would make the hardware designers capture the design ideas easily and explicitly using this visual hardware behavioral language.

  3. New Designs for Correctional Education and Training Programs.

    ERIC Educational Resources Information Center

    McCollum, Sylvia G.

    1973-01-01

    The challenge confronting creative educators concerned with using the correctional experience in positive ways is to structure an educational delivery system which takes into account the wide range of individual differences among people whose only common denominator is "serving time." Inherent is the problem of staff and public resistance to…

  4. 78 FR 32988 - Core Principles and Other Requirements for Designated Contract Markets; Correction

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-06-03

    ... and Other Requirements for Designated Contract Markets (77 FR 36612, June 19, 2012). The final rule... Markets; Correction AGENCY: Commodity Futures Trading Commission. ACTION: Final rule; correction. SUMMARY... Other Requirements for Designated Contract Markets by inserting a missing instruction to add Appendix...

  5. Characterization of a Solid Oxide Fuel Cell Gas Turbine Hybrid System Based on a Factorial Design of Experiments Using Hardware Simulation

    SciTech Connect

    Restrepo, Bernardo; Banta, Larry E.; Tucker, David

    2012-10-01

    A full factorial experimental design and a replicated fractional factorial design were carried out using the Hybrid Performance (HyPer) project facility installed at the National Energy Technology Laboratory (NETL), U.S. Department of Energy to simulate gasifer/fuel cell/turbine hybrid power systems. The HyPer facility uses hardware in the loop (HIL) technology that couples a modified recuperated gas turbine cycle with hardware driven by a solid oxide fuel cell model. A 34 full factorial design (FFD) was selected to study the effects of four factors: cold-air, hot-air, bleed-air bypass valves, and the electric load on different parameters such as cathode and turbine inlet temperatures, pressure and mass flow. The results obtained, compared with former results where the experiments were made using one-factor-at-a-time (OFAT), show that no strong interactions between the factors are present in the different parameters of the system. This work also presents a fractional factorial design (ffd) 34-2 in order to analyze replication of the experiments. In addition, a new envelope is described based on the results of the design of experiments (DoE), compared with OFAT experiments, and analyzed in an off-design integrated fuel cell/gas turbine framework. This paper describes the methodology, strategy, and results of these experiments that bring new knowledge concerning the operating state space for this kind of power generation system.

  6. Coding design for error correcting output codes based on perceptron

    NASA Astrophysics Data System (ADS)

    Zhou, Jin-Deng; Wang, Xiao-Dan; Zhou, Hong-Jian; Cui, Yong-Hua; Jing, Sun

    2012-05-01

    It is known that error-correcting output codes (ECOC) is a common way to model multiclass classification problems, in which the research of encoding based on data is attracting more and more attention. We propose a method for learning ECOC with the help of a single-layered perception neural network. To achieve this goal, the code elements of ECOC are mapped to the weights of network for the given decoding strategy, and an object function with the constrained weights is used as a cost function of network. After the training, we can obtain a coding matrix including lots of subgroups of class. Experimental results on artificial data and University of California Irvine with logistic linear classifier and support vector machine as the binary learner show that our scheme provides better performance of classification with shorter length of coding matrix than other state-of-the-art encoding strategies.

  7. Sterilization of space hardware.

    NASA Technical Reports Server (NTRS)

    Pflug, I. J.

    1971-01-01

    Discussion of various techniques of sterilization of space flight hardware using either destructive heating or the action of chemicals. Factors considered in the dry-heat destruction of microorganisms include the effects of microbial water content, temperature, the physicochemical properties of the microorganism and adjacent support, and nature of the surrounding gas atmosphere. Dry-heat destruction rates of microorganisms on the surface, between mated surface areas, or buried in the solid material of space vehicle hardware are reviewed, along with alternative dry-heat sterilization cycles, thermodynamic considerations, and considerations of final sterilization-process design. Discussed sterilization chemicals include ethylene oxide, formaldehyde, methyl bromide, dimethyl sulfoxide, peracetic acid, and beta-propiolactone.

  8. Hardware Accelerated Simulated Radiography

    SciTech Connect

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-04-12

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32 bit floating point texture capabilities to obtain validated solutions to the radiative transport equation for X-rays. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedra that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester. We show that the hardware accelerated solution is faster than the current technique used by scientists.

  9. Factors Influencing the Design, Establishment, Administration, and Governance of Correctional Education for Females

    ERIC Educational Resources Information Center

    Ellis, Johnica; McFadden, Cheryl; Colaric, Susan

    2008-01-01

    This article summarizes the results of a study conducted to investigate factors influencing the organizational design, establishment, administration, and governance of correctional education for females. The research involved interviews with correctional and community college administrators and practitioners representing North Carolina female…

  10. The use of real-time, hardware-in-the-loop simulation in the design and development of the new Hughes HS601 spacecraft attitude control system

    NASA Technical Reports Server (NTRS)

    Slafer, Loren I.

    1989-01-01

    Realtime simulation and hardware-in-the-loop testing is being used extensively in all phases of the design, development, and testing of the attitude control system (ACS) for the new Hughes HS601 satellite bus. Realtime, hardware-in-the-loop simulation, integrated with traditional analysis and pure simulation activities is shown to provide a highly efficient and productive overall development program. Implementation of high fidelity simulations of the satellite dynamics and control system algorithms, capable of real-time execution (using applied Dynamics International's System 100), provides a tool which is capable of being integrated with the critical flight microprocessor to create a mixed simulation test (MST). The MST creates a highly accurate, detailed simulated on-orbit test environment, capable of open and closed loop ACS testing, in which the ACS design can be validated. The MST is shown to provide a valuable extension of traditional test methods. A description of the MST configuration is presented, including the spacecraft dynamics simulation model, sensor and actuator emulators, and the test support system. Overall system performance parameters are presented. MST applications are discussed; supporting ACS design, developing on-orbit system performance predictions, flight software development and qualification testing (augmenting the traditional software-based testing), mission planning, and a cost-effective subsystem-level acceptance test. The MST is shown to provide an ideal tool in which the ACS designer can fly the spacecraft on the ground.

  11. Door Hardware and Installations; Carpentry: 901894.

    ERIC Educational Resources Information Center

    Dade County Public Schools, Miami, FL.

    The curriculum guide outlines a course designed to provide instruction in the selection, preparation, and installation of hardware for door assemblies. The course is divided into five blocks of instruction (introduction to doors and hardware, door hardware, exterior doors and jambs, interior doors and jambs, and a quinmester post-test) totaling…

  12. 16 CFR 1508.6 - Hardware.

    Code of Federal Regulations, 2011 CFR

    2011-01-01

    ... 16 Commercial Practices 2 2011-01-01 2011-01-01 false Hardware. 1508.6 Section 1508.6 Commercial... FULL-SIZE BABY CRIBS § 1508.6 Hardware. (a) A crib shall be designed and constructed in a manner that eliminates from any hardware accessible to a child within the crib the possibility of the...

  13. The Space Operations Simulation Center (SOSC) and Closed-loop Hardware Testing for Orion Rendezvous System Design

    NASA Technical Reports Server (NTRS)

    D'Souza, Christopher; Milenkovich, Zoran; Wilson, Zachary; Huich, David; Bendle, John; Kibler, Angela

    2011-01-01

    The Space Operations Simulation Center (SOSC) at the Lockheed Martin (LM) Waterton Campus in Littleton, Colorado is a dynamic test environment focused on Autonomous Rendezvous and Docking (AR&D) development testing and risk reduction activities. The SOSC supports multiple program pursuits and accommodates testing Guidance, Navigation, and Control (GN&C) algorithms for relative navigation, hardware testing and characterization, as well as software and test process development. The SOSC consists of a high bay (60 meters long by 15.2 meters wide by 15.2 meters tall) with dual six degree-of-freedom (6DOF) motion simulators and a single fixed base 6DOF robot. The large testing area (maximum sensor-to-target effective range of 60 meters) allows for large-scale, flight-like simulations of proximity maneuvers and docking events. The facility also has two apertures for access to external extended-range outdoor target test operations. In addition, the facility contains four Mission Operations Centers (MOCs) with connectivity to dual high bay control rooms and a data/video interface room. The high bay is rated at Class 300,000 (. 0.5 m maximum particles/m3) cleanliness and includes orbital lighting simulation capabilities.

  14. The telescope control of the ASTRI SST-2M prototype for the Cherenkov telescope Array: hardware and software design architecture

    NASA Astrophysics Data System (ADS)

    Antolini, Elisa; Cascone, Enrico; Schwarz, Joseph; Stringhetti, Luca; Tanci, Claudio; Tosti, Gino; Aisa, Damiano; Aisa, Simone; Bagaglia, Marco; Busatta, Andrea; Campeggi, Carlo; Cefala, Marco; Farnesini, Lucio; Giacomel, Stefano; Marchiori, Gianpiero; Marcuzzi, Enrico; Nucciarelli, Giuliano; Piluso, Antonfranco

    2014-07-01

    ASTRI (Astrofisica con Specchi a Tecnologia Replicante Italiana) is a flagship project of the Italian Ministry of Research and led by the Italian National Institute of Astrophysics (INAF). One of its aims is to develop, within the Cherenkov Telescope Array (CTA) framework, an end-to-end small-sized telescope prototype in a dual-mirror configuration (SST-2M) in order to investigate the energy range E ~ 1-100 TeV. A long-term goal of the ASTRI program is the production of an ASTRI/CTA mini-array composed of seven SST-2M telescopes. The prototype, named ASTRI SST-2M, is seen as a standalone system that needs only network and power connections to work. The software system that is being developed to control the prototype is the base for the Mini-Array Software System (MASS), which has the task to make possible the operation of both the ASTRI SST-2M prototype and the ASTRI/CTA mini-array. The scope of this contribution is to give an overview of the hardware and software architecture adopted for the ASTRI SST- 2M prototype, showing how to apply state of the art industrial technologies to telescope control and monitoring systems.

  15. Hardware Counter Multiplexing

    Energy Science and Technology Software Center (ESTSC)

    2000-10-13

    The Hardware Counter Multiplexer works with the built-in counter registers on computer processors. These counters record various low-level events as software runs, but they can not record all possible events at the same time. This software helps work around that limitation by counting a series of different events in sequence over a period of time. This in turn allows programmers to measure interesting combinations of events, rather than single events. The software is designed tomore » work with multithreaded or single-threaded programs.« less

  16. Energy efficient engine: Turbine intermediate case and low-pressure turbine component test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Leach, K.; Thulin, R. D.; Howe, D. C.

    1982-01-01

    A four stage, low pressure turbine component has been designed to power the fan and low pressure compressor system in the Energy Efficient Engine. Designs for a turbine intermediate case and an exit guide vane assembly also have been established. The components incorporate numerous technology features to enhance efficiency, durability, and performance retention. These designs reflect a positive step towards improving engine fuel efficiency on a component level. The aerodynamic and thermal/mechanical designs of the intermediate case and low pressure turbine components are presented and described. An overview of the predicted performance of the various component designs is given.

  17. Growth and development of Arabidopsis in the Advanced Biological Research System (ABRS) hardware designed for the International Space Station

    NASA Astrophysics Data System (ADS)

    Savidge, Rodney

    Wild type (Col 0) Arabidopsis thaliana were grown in a growth chamber within the single mid-deck sized Advanced Biological Research System (ABRS) spaceflight hardware developed by NASA Kennedy Space Center. Before beginning this experiment, the plants, each rooted in individual transferable tubes containing nutrients, were cultivated hydroponically on halfstrength Hoagland's solution beneath either LED lighting similar to that provided by the ABRS growth chamber or white fluorescent lighting. The leaves of the basal whorl of plants pre-grown in ABRS lighting were small and purplish at the start of the experiment, whereas those under fluorescent lighting were larger and green. The plants were transferred to the ABRS soon after their inflorescence axes had started to elongate, and thereafter they were maintained under preset conditions (22 o C, approximately 1500 ppm CO2 , predominantly 125 µmol m-2 s-1 PAR) with pulses of water provided at 1-3 d intervals (as needed) to the module into which the root tubes were inserted. That module was pre-treated with half-strength Hoagland's nutrient solution on day 0, but no additional nutrients were provided the plants thereafter. Strong primary growth of all inflorescence stems occurred soon after initiating the ABRS experiment, and the plants began forming an overarching canopy of flowering stems beneath the LED lighting module within two weeks. After 38 days the root module was littered with seeds, siliques and abscised leaves, but all plants remained alive. Plants pre-grown in ABRS lighting were more advanced toward senescence, and leaves and stems of plants pre-grown in fluorescent lighting although greener were also acquiring a purplish hue. Microscopy revealed that the flowering stems achieved no secondary growth; however, progressive inward conversion of pith parenchyma into sclerenchyma cells did occur resulting in the inflorescence stems becoming abnormally woody.

  18. 78 FR 15755 - Proposed Revision to Design of Structures, Components, Equipment and Systems; Correction

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-03-12

    ... March 1, 2013 (41 FR 13911), that announced the solicitation for comments of the proposed revision in Chapter 3, ``Design of Structures, Components, Equipment, and Systems'' and is soliciting public comment... COMMISSION Proposed Revision to Design of Structures, Components, Equipment and Systems; Correction...

  19. 75 FR 38129 - Freescale Semiconductor, Inc., Hardware/Software Design and Manufacturing A Including On-Site...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-07-01

    ... published in the Federal Register on May 28, 2010 (75 FR 30070). At the request of the State Agency, the... Manufacturing A Including On-Site Leased Workers From TAC Worldwide, GDA Technologies, Inc., Manpower, Ion..., GDA Technologies, Inc., Manpower, Ion Design, Design Solutions, Inc., Veriseo, SilconElite and...

  20. Design and development of a wireless sensor network to monitor snow depth in multiple catchments in the American River basin, California: hardware selection and sensor placement techniques

    NASA Astrophysics Data System (ADS)

    Kerkez, B.; Rice, R.; Glaser, S. D.; Bales, R. C.; Saksa, P. C.

    2010-12-01

    A 100-node wireless sensor network (WSN) was designed for the purpose of monitoring snow depth in two watersheds, spanning 3 km2 in the American River basin, in the central Sierra Nevada of California. The network will be deployed as a prototype project that will become a core element of a larger water information system for the Sierra Nevada. The site conditions range from mid-elevation forested areas to sub-alpine terrain with light forest cover. Extreme temperature and humidity fluctuations, along with heavy rain and snowfall events, create particularly challenging conditions for wireless communications. We show how statistics gathered from a previously deployed 60-node WSN, located in the Southern Sierra Critical Zone Observatory, were used to inform design. We adapted robust network hardware, manufactured by Dust Networks for highly demanding industrial monitoring, and added linear amplifiers to the radios to improve transmission distances. We also designed a custom data-logging board to interface the WSN hardware with snow-depth sensors. Due to the large distance between sensing locations, and complexity of terrain, we analyzed network statistics to select the location of repeater nodes, to create a redundant and reliable mesh. This optimized network topology will maximize transmission distances, while ensuring power-efficient network operations throughout harsh winter conditions. At least 30 of the 100 nodes will actively sense snow depth, while the remainder will act as sensor-ready repeaters in the mesh. Data from a previously conducted snow survey was used to create a Gaussian Process model of snow depth; variance estimates produced by this model were used to suggest near-optimal locations for snow-depth sensors to measure the variability across a 1 km2 grid. We compare the locations selected by the sensor placement algorithm to those made through expert opinion, and offer explanations for differences resulting from each approach.

  1. Constructing Hardware in a Scale Embedded Language

    Energy Science and Technology Software Center (ESTSC)

    2014-08-21

    Chisel is a new open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. Chisel is embedded in the Scala programming language, which raises the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. From the same source, Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to pass onmore » to standard ASIC or FPGA tools for synthesis and place and route.« less

  2. Open-source hardware for medical devices

    PubMed Central

    2016-01-01

    Open-source hardware is hardware whose design is made publicly available so anyone can study, modify, distribute, make and sell the design or the hardware based on that design. Some open-source hardware projects can potentially be used as active medical devices. The open-source approach offers a unique combination of advantages, including reducing costs and faster innovation. This article compares 10 of open-source healthcare projects in terms of how easy it is to obtain the required components and build the device. PMID:27158528

  3. Constructing Hardware in a Scale Embedded Language

    SciTech Connect

    Bachan, John

    2014-08-21

    Chisel is a new open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. Chisel is embedded in the Scala programming language, which raises the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. From the same source, Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to pass on to standard ASIC or FPGA tools for synthesis and place and route.

  4. Hardware removal - extremity

    MedlinePlus

    ... this page: //medlineplus.gov/ency/article/007644.htm Hardware removal - extremity To use the sharing features on this page, please enable JavaScript. Surgeons use hardware such as pins, plates, or screws to help ...

  5. Engineering aspects and hardware verification of a volume producable solid oxide fuel cell stack design for diesel auxiliary power units

    NASA Astrophysics Data System (ADS)

    Stelter, Michael; Reinert, Andreas; Mai, Björn Erik; Kuznecov, Mihail

    A solid oxide fuel cell (SOFC) stack module is presented that is designed for operation on diesel reformate in an auxiliary power unit (APU). The stack was designed using a top-down approach, based on a specification of an APU system that is installed on board of vehicles. The stack design is planar, modular and scalable with stamped sheet metal interconnectors. It features thin membrane electrode assemblies (MEAs), such as electrolyte supported cells (ESC) and operates at elevated temperatures around 800 °C. The stack has a low pressure drop in both the anode and the cathode to facilitate a simple system layout. An overview of the technical targets met so far is given. A stack power density of 0.2 kW l -1 has been demonstrated in a fully integrated, thermally self-sustaining APU prototype running with diesel and without an external water supply.

  6. Modular hardware synthesis using an HDL. [Hardware Description Language

    NASA Technical Reports Server (NTRS)

    Covington, J. A.; Shiva, S. G.

    1981-01-01

    Although hardware description languages (HDL) are becoming more and more necessary to automated design systems, their application is complicated due to the difficulty in translating the HDL description into an implementable format, nonfamiliarity of hardware designers with high-level language programming, nonuniform design methodologies and the time and costs involved in transfering HDL design software. Digital design language (DDL) suffers from all of the above problems and in addition can only by synthesized on a complete system and not on its subparts, making it unsuitable for synthesis using standard modules or prefabricated chips such as those required in LSI or VLSI circuits. The present paper presents a method by which the DDL translator can be made to generate modular equations that will allow the system to be synthesized as an interconnection of lower-level modules. The method involves the introduction of a new language construct called a Module which provides for the separate translation of all equations bounded by it.

  7. The Space Operations Simulation Center (SOSC) and Closed-Loop Hardware Testing for Orion Rendezvous System Design

    NASA Technical Reports Server (NTRS)

    Milenkovic, Zoran; DSouza, Christopher; Huish, David; Bendle, John; Kibler, Angela

    2012-01-01

    The exploration goals of Orion / MPCV Project will require a mature Rendezvous, Proximity Operations and Docking (RPOD) capability. Ground testing autonomous docking with a next-generation sensor such as the Vision Navigation Sensor (VNS) is a critical step along the path of ensuring successful execution of autonomous RPOD for Orion. This paper will discuss the testing rationale, the test configuration, the test limitations and the results obtained from tests that have been performed at the Lockheed Martin Space Operations Simulation Center (SOSC) to evaluate and mature the Orion RPOD system. We will show that these tests have greatly increased the confidence in the maturity of the Orion RPOD design, reduced some of the latent risks and in doing so validated the design philosophy of the Orion RPOD system. This paper is organized as follows: first, the objectives of the test are given. Descriptions of the SOSC facility, and the Orion RPOD system and associated components follow. The details of the test configuration of the components in question are presented prior to discussing preliminary results of the tests. The paper concludes with closing comments.

  8. Designedly Incomplete Utterances: A Pedagogical Practice for Eliciting Knowledge Displays in Error Correction Sequences.

    ERIC Educational Resources Information Center

    Koshik, Irene

    2002-01-01

    Uses a conversation analytic framework to analyze a practice used by teachers in 1-0-1, second language writing conferences when eliciting self-correction of students' written language errors. This type of turn used to elicit a knowledge display from the student is labeled designedly incomplete utterance (DIU). Teachers use DIUs made up of…

  9. Visualizing the Future of Research on Post Secondary Correctional Education: Designs, Data, and Deliverables

    ERIC Educational Resources Information Center

    Wheeldon, J.

    2011-01-01

    Providing post-secondary education in correctional settings has emerged as one of the best ways to reduce recidivism, save taxpayer dollars, and promote post release employment and community reintegration. While a number of studies exist, this paper argues persistent challenges connected to research design, data collection, and the communication…

  10. 78 FR 28291 - Unblocking of 1 Individual Designated Pursuant to Executive Order 13572; Correction

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-05-14

    ... Persons with Respect to Human Rights Abuses in Syria'' from the list of Specially Designated Nationals and... President issued Executive Order 13572, ``Blocking Property of Certain Persons with Respect to Human Rights.../622-0077. Correction In the notice published in the Federal Register on April 25, 2013 at 78 FR...

  11. Bias Corrections for Standardized Effect Size Estimates Used with Single-Subject Experimental Designs

    ERIC Educational Resources Information Center

    Ugille, Maaike; Moeyaert, Mariola; Beretvas, S. Natasha; Ferron, John M.; Van den Noortgate, Wim

    2014-01-01

    A multilevel meta-analysis can combine the results of several single-subject experimental design studies. However, the estimated effects are biased if the effect sizes are standardized and the number of measurement occasions is small. In this study, the authors investigated 4 approaches to correct for this bias. First, the standardized effect…

  12. The APACHE survey hardware and software design: Tools for an automatic search of small-size transiting exoplanets

    NASA Astrophysics Data System (ADS)

    Christille, Jean-Marc; Bernagozzi, A.; Bertolini, E.; Calcidese, P.; Carbognani, A.; Cenadelli, D.; Damasso, M.; Giacobbe, P.; Lanteri, L.; Lattanzi, M. G.; Sozzetti, A.; Smart, R.

    2013-04-01

    Small-size ground-based telescopes can effectively be used to look for transiting rocky planets around nearby low-mass M stars using the photometric transit method, as recently demonstrated for example by the MEarth project. Since 2008 at the Astronomical Observatory of the Autonomous Region of Aosta Valley (OAVdA), we have been preparing for the long-term photometric survey APACHE, aimed at finding transiting small-size planets around thousands of nearby early and mid-M dwarfs. APACHE (A PAthway toward the Characterization of Habitable Earths) is designed to use an array of five dedicated and identical 40-cm Ritchey-Chretien telescopes and its observations started at the beginning of summer 2012. The main characteristics of the survey final set up and the preliminary results from the first weeks of observations will be discussed.

  13. Hardware description ADSP-21020 40-bit floating point DSP as designed in a remotely controlled digital CW Doppler radar

    SciTech Connect

    Morrison, R.E.; Robinson, S.H.

    1991-01-01

    A continuous wave Doppler radar system has been designed which is portable, easily deployed, and remotely controlled. The heart of this system is a DSP/control board using Analog Devices ADSP-21020 40-bit floating point digital signal processor (DSP) microprocessor. Two 18-bit audio A/D converters provide digital input to the DSP/controller board for near real time target detection. Program memory for the DSP is dual ported with an Intel 87C51 microcontroller allowing DSP code to be up-loaded or down-loaded from a central controlling computer. The 87C51 provides overall system control for the remote radar and includes a time-of-day/day-of-year real time clock, system identification (ID) switches, and input/output (I/O) expansion by an Intel 82C55 I/O expander. 5 refs., 8 figs., 2 tabs.

  14. Electrical Safety for Human Space Flight Payload Hardware

    NASA Astrophysics Data System (ADS)

    Runnells, James A.

    2010-09-01

    Human Space Flight payload hardware designs must address both mission success and safety requirements for flight on the Space Shuttle, International Space Station(ISS), or International Partner(IP) Launch Vehicles. Flight hardware generally can be considered either Government Furnished Equipment(GFE) or Payload hardware, although some Commercial-off-the-shelf(COTS) hardware is also flown. In this case we will use the payload flight hardware system safety perspective, which closely resembles the GFE system safety process with a few exceptions. Why is Human space flight hardware treated differently than ground hardware? The key reason flight hardware is treated more conservatively than ground hardware is the relative impact to crew and vehicle, and the relative inability to provide immediate recovery of a disabled space vehicle or crewmember on-orbit. One aspect of safe payload flight hardware design is Electrical Power Systems(EPS), including the safe design and operations of electrical power systems for payloads.

  15. Open-loop correction of horizontal turbulence: system design and result.

    PubMed

    Mu, Quanquan; Cao, Zhaoliang; Li, Dayu; Hu, Lifa; Xuan, Li

    2008-08-10

    Adaptive optics systems often work in a closed-loop configuration due to the hysteretic and nonlinearity properties of conventional deformable mirrors. Because of the high-precision wavefront generation and nonhysteretic properties of liquid-crystal devices, the open-loop control becomes possible. Open-loop control is a requirement for advanced adaptive optics concepts. We designed an open-loop adaptive optics system with a liquid-crystal-on-silicon wavefront corrector. This system is simple, fast, and can save much more light compared to conventional liquid-crystal-based closed-loop systems. The detailed principle, construction, and operation are discussed. The 500 m horizontal turbulence correction experiment was done using a 250 mm telescope in the laboratory. The whole system can reach a 60 Hz correction frequency. Evaluation of the correction precision was done at closed-loop configuration, which is 0.2 lambda (lambda=0.633 microm) in peak to valley. The dynamic image under open-loop correction got the same resolution compared to closed-loop correction. The whole system reached 0.68 arc sec resolution capability at open-loop correction, which is slightly larger than the system's diffraction-limited resolution of 0.65 arc sec. PMID:18690274

  16. Fault tolerant VLSI (Very Large-Scale Integration) design using error correcting codes

    NASA Astrophysics Data System (ADS)

    Hartmann, C. R.; Lala, P. K.; Ali, A. M.; Ganguly, S.; Visweswaran, G. S.

    1989-02-01

    Very Large-Scale Integration (VLSI) provides the opportunity to design fault tolerant, self-checking circuits with on-chip, concurrent error correction. This study determines the applicability of a variety of error-detecting, error-correcting codes (EDAC) in high speed digital data processors and buses. In considering both microcircuit faults and bus faults, some of the codes examined are: Berger, repetition, parity, residue, and Modified Reflected Binary codes. The report describes the improvement in fault tolerance obtained as a result of implementing these EDAC schemes and the associated penalties in circuit area.

  17. Correction of magnetooptic device phase errors in optical correlators through filter design modifications

    NASA Technical Reports Server (NTRS)

    Downie, John D.; Reid, Max B.; Hine, Butler P.

    1991-01-01

    We address the problem of optical phase errors in an optical correlator introduced by the input and filter plane spatial light modulators. Specifically, we study a laboratory correlator with magnetooptic spatial light modulator (MOSLM) devices. We measure and characterize the phase errors, analyze their effects on the correlation process, and discuss a means of correction through a design modification of the binary phase-only optical filter function. The phase correction technique is found to produce correlation results close to those of an error-free correlator.

  18. Broadband astigmatism-corrected spectrometer design using a toroidal lens and a special filter

    NASA Astrophysics Data System (ADS)

    Ge, Xianying; Chen, Siying; Zhang, Yinchao; Chen, He; Guo, Pan; Mu, Taotao; Yang, Jian; Bu, Zhichao

    2015-01-01

    In the paper, a method to obtain a broadband, astigmatism-corrected spectrometer based on the existing Czerny-Turner spectrometer is proposed. The theories of astigmatism correction using a toroidal lens and a special filter are described in detail. Performance comparisons of the modified spectrometer and the traditional spectrometer are also presented. Results show that with the new design the RMS spot radius in sagittal view is one-eightieth of that in the traditional spectrometer over a broadband spectral range from 300 to 700 nm, without changing or moving any optical elements in the traditional spectrometer.

  19. Novel Principles and Techniques to Create a Natural Design in Female Hairline Correction Surgery

    PubMed Central

    2015-01-01

    Abstract Background: Female hairline correction surgery is becoming increasingly popular. However, no guidelines or methods of female hairline design have been introduced to date. Methods: The purpose of this study was to create an initial framework based on the novel principles of female hairline design and then use artistic ability and experience to fine tune this framework. An understanding of the concept of 5 areas (frontal area, frontotemporal recess area, temporal peak, infratemple area, and sideburns) and 5 points (C, A, B, T, and S) is required for female hairline correction surgery (the 5A5P principle). The general concepts of female hairline correction surgery and natural design methods are, herein, explained with a focus on the correlations between these 5 areas and 5 points. Results: A natural and aesthetic female hairline can be created with application of the above-mentioned concepts. Conclusion: The 5A5P principle of forming the female hairline is very useful in female hairline correction surgery. PMID:26894014

  20. Towards composition of verified hardware devices

    NASA Technical Reports Server (NTRS)

    Schubert, E. Thomas; Levitt, K.; Cohen, G. C.

    1991-01-01

    Computers are being used where no affordable level of testing is adequate. Safety and life critical systems must find a replacement for exhaustive testing to guarantee their correctness. Through a mathematical proof, hardware verification research has focused on device verification and has largely ignored system composition verification. To address these deficiencies, we examine how the current hardware verification methodology can be extended to verify complete systems.

  1. Viscous microstructural dampers with aligned holes: design procedure including the edge correction.

    PubMed

    Homentcovschi, Dorel; Miles, Ronald N

    2007-09-01

    The paper is a continuation of the works "Modelling of viscous damping of perforated planar micromechanical structures. Applications in acoustics" [Homentcovschi and Miles, J. Acoust. Soc. Am. 116, 2939-2947 (2004)] and "Viscous Damping of Perforated Planar Micromechanical Structures" [Homentcovschi and Miles, Sensors Actuators, A119, 544-552 (2005)] where design formulas for the case of an offset (staggered) system of holes was provided. The present work contains design formulas for perforated planar microstructures used in MEMS devices (such as proof-masses in accelerometers, backplates in microphones, micromechanical switches, resonators, tunable microoptical interferometers, etc.) in the case of aligned (nonstaggered) holes of circular and square section. The given formulas assure a minimum total damping coefficient (including the squeeze film damping and the direct and indirect resistance of the holes) for an assigned open area. The paper also gives a simple edge correction, making it possible to consider real (finite) perforated planar microstructures. The proposed edge correction is validated by comparison with the results obtained by FEM simulations: the relative error is found to be smaller than 0.04%. By putting together the design formulas with the edge correction a simple integrated design procedure for obtaining viscous perforated dampers with assigned properties is obtained. PMID:17927414

  2. Thermal Hardware for the Thermal Analyst

    NASA Technical Reports Server (NTRS)

    Steinfeld, David

    2015-01-01

    The presentation will be given at the 26th Annual Thermal Fluids Analysis Workshop (TFAWS 2015) hosted by the Goddard Space Flight Center (GSFC) Thermal Engineering Branch (Code 545). NCTS 21070-1. Most Thermal analysts do not have a good background into the hardware which thermally controls the spacecraft they design. SINDA and Thermal Desktop models are nice, but knowing how this applies to the actual thermal hardware (heaters, thermostats, thermistors, MLI blanketing, optical coatings, etc...) is just as important. The course will delve into the thermal hardware and their application techniques on actual spacecraft. Knowledge of how thermal hardware is used and applied will make a thermal analyst a better engineer.

  3. Computer hardware description languages - A tutorial

    NASA Technical Reports Server (NTRS)

    Shiva, S. G.

    1979-01-01

    The paper introduces hardware description languages (HDL) as useful tools for hardware design and documentation. The capabilities and limitations of HDLs are discussed along with the guidelines needed in selecting an appropriate HDL. The directions for future work are provided and attention is given to the implementation of HDLs in microcomputers.

  4. 16 CFR 1508.6 - Hardware.

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... 16 Commercial Practices 2 2010-01-01 2010-01-01 false Hardware. 1508.6 Section 1508.6 Commercial Practices CONSUMER PRODUCT SAFETY COMMISSION FEDERAL HAZARDOUS SUBSTANCES ACT REGULATIONS REQUIREMENTS FOR FULL-SIZE BABY CRIBS § 1508.6 Hardware. (a) A crib shall be designed and constructed in a manner...

  5. Research on bottlenecks of RAID controller hardware

    NASA Astrophysics Data System (ADS)

    Tan, Zhihu; Chen, Jie; Hu, Huaixiang

    2008-12-01

    RAID systems provide both improved capacity and performance as compared to single disk by striping data to multiple disks, and improve reliability efficiently by redundancy techniques, now RAID becomes key storage device for massive storage system. There are two ways to implement the RAID system: the first is to implement as a software subsystem under PC platform, the second is to implement as a hardware controller. The second one is more common. We have designed and implemented a RAID hardware controller, which called DSDM-FC2000. This paper discusses three kinds of bottlenecks of the DSDM-FC2000 RAID hardware controller: PCI transmission bottleneck, memory access bottleneck and CPU computation bottleneck, and then presents an optimized hardware XOR algorithm which can improve the RAID performance efficiently. Finally this paper gives some advises on designing new generation RAID controller hardware.

  6. Commercial Aircraft Maintenance Experience Relating to Engine External Hardware

    NASA Technical Reports Server (NTRS)

    Soditus, Sharon M.

    2006-01-01

    Airlines are extremely sensitive to the amount of dollars spent on maintaining the external engine hardware in the field. Analysis reveals that many problems revolve around a central issue, reliability. Fuel and oil leakage due to seal failure and electrical fault messages due to wire harness failures play a major role in aircraft delays and cancellations (D&C's) and scheduled maintenance. Correcting these items on the line requires a large investment of engineering resources and manpower after the fact. The smartest and most cost effective philosophy is to build the best hardware the first time. The only way to do that is to completely understand and model the operating environment, study the field experience of similar designs and to perform extensive testing.

  7. Hardware-Accelerated Simulated Radiography

    SciTech Connect

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-08-04

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32-bit floating point texture capabilities to obtain solutions to the radiative transport equation for X-rays. The hardware accelerated solutions are accurate enough to enable scientists to explore the experimental design space with greater efficiency than the methods currently in use. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedral meshes that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester.

  8. Design and analysis of site-specific single-strand nicking endonucleases for gene correction.

    PubMed

    Metzger, Michael J; Certo, Michael T

    2014-01-01

    Single-strand nicking endonucleases ("nickases") have been shown to induce homology-mediated gene correction with reduced toxicity of DNA double-strand break-producing enzymes, and nickases have been engineered from both homing endonuclease and FokI-based scaffolds. We describe the strategies used to engineer these site-specific nickases as well as the in vitro methods used to confirm their activity and specificity. Additionally, we describe the Traffic Light Reporter system, which uses a flow cytometric assay to simultaneously detect both gene repair and mutagenic nonhomologous end-joining outcomes at a single targeted site in mammalian cells. With these methods, novel nickases can be designed and tested for use in gene correction with novel target sites. PMID:24557907

  9. Hardware Testing and System Evaluation: Procedures to Evaluate Commodity Hardware for Production Clusters

    SciTech Connect

    Goebel, J

    2004-02-27

    Without stable hardware any program will fail. The frustration and expense of supporting bad hardware can drain an organization, delay progress, and frustrate everyone involved. At Stanford Linear Accelerator Center (SLAC), we have created a testing method that helps our group, SLAC Computer Services (SCS), weed out potentially bad hardware and purchase the best hardware at the best possible cost. Commodity hardware changes often, so new evaluations happen periodically each time we purchase systems and minor re-evaluations happen for revised systems for our clusters, about twice a year. This general framework helps SCS perform correct, efficient evaluations. This article outlines SCS's computer testing methods and our system acceptance criteria. We expanded the basic ideas to other evaluations such as storage, and we think the methods outlined in this article has helped us choose hardware that is much more stable and supportable than our previous purchases. We have found that commodity hardware ranges in quality, so systematic method and tools for hardware evaluation were necessary. This article is based on one instance of a hardware purchase, but the guidelines apply to the general problem of purchasing commodity computer systems for production computational work.

  10. Effective safety measures with tests followed by design correction for aerospace structures

    NASA Astrophysics Data System (ADS)

    Matsumura, Taiki

    Analytical and computational prediction tools enable us to design aircraft and spacecraft components with high degree of confidence. While the accuracy of such predictions has been improved over the years, uncertainty continues to be added by new materials and new technology introduced in order to improve performance. This requires us to have reality checks, such as tests, in order to make sure that the prediction tools are reliable enough to ensure safety. While tests can reveal unsafe designs and lead to design correction, these tests are very costly. Therefore, it is important to manage such a design-test-correction cycle effectively. In this dissertation, we consider three important test stages in the lifecycle of an aviation system. First, we dealt with characterization tests that reveal failure modes of new materials or new geometrical arrangements. We investigated the challenge associated with getting the best characterization with a limited number of tests. We have found that replicating tests to attenuate the effect of noise in observation is not necessary because some surrogate models can serve as a noise filter without having replicated data. Instead, we should focus on exploring the design space with different structural configurations in order to discover unknown failure modes. Next, we examined post-design tests for design acceptance followed by possible redesign. We looked at the question of how to balance the desire for better performance achieved by redesign against the cost of redesign. We proposed a design optimization framework that provides tradeoff information between the expected performance improvement by redesign and the probability of redesign, equivalent to the cost of redesign. We also demonstrated that the proposed method can reduce the performance loss due to a conservative reliability estimate. The ultimate test, finally, is whether the structures do not fail in flight. Once an accident occurs, an accident investigation takes place

  11. Initial Hardware Development Schedule

    NASA Technical Reports Server (NTRS)

    Culpepper, William X.

    1991-01-01

    The hardware development schedule for the Common Lunar Lander's (CLLs) tracking system is presented. Among the topics covered are the following: historical perspective, solution options, industry contacts, and the rationale for selection.

  12. Mechanically verified hardware implementing an 8-bit parallel IO Byzantine agreement processor

    NASA Technical Reports Server (NTRS)

    Moore, J. Strother

    1992-01-01

    Consider a network of four processors that use the Oral Messages (Byzantine Generals) Algorithm of Pease, Shostak, and Lamport to achieve agreement in the presence of faults. Bevier and Young have published a functional description of a single processor that, when interconnected appropriately with three identical others, implements this network under the assumption that the four processors step in synchrony. By formalizing the original Pease, et al work, Bevier and Young mechanically proved that such a network achieves fault tolerance. We develop, formalize, and discuss a hardware design that has been mechanically proven to implement their processor. In particular, we formally define mapping functions from the abstract state space of the Bevier-Young processor to a concrete state space of a hardware module and state a theorem that expresses the claim that the hardware correctly implements the processor. We briefly discuss the Brock-Hunt Formal Hardware Description Language which permits designs both to be proved correct with the Boyer-Moore theorem prover and to be expressed in a commercially supported hardware description language for additional electrical analysis and layout. We briefly describe our implementation.

  13. Orbiter CIU/IUS communications hardware evaluation

    NASA Technical Reports Server (NTRS)

    Huth, G. K.

    1979-01-01

    Inertial Upper Stage (IUS) and DoD Communication Interface Unit (CIU) communication system design, hardware specifications, and interfaces were evaluated to determine their compatibility with the Orbiter payload communication and data handling equipment and the Orbiter network communication equipment.

  14. Bion 11 mission hardware.

    PubMed

    Golov, V K; Magedov, V S; Skidmore, M G; Hines, J W; Kozlovskaya, I B; Korolkov, V I

    2000-01-01

    The mission hardware provided for Bion 11 shared primate experiments included the launch vehicle, biosatellite, spaceflight operational systems, spacecraft recovery systems, life support systems, bioinstrumentation, and data collection systems. Under the unique Russia/US bilateral contract, the sides worked together to ensure the reliability and quality of hardware supporting the primate experiments. Parameters recorded inflight covered biophysical, biochemical, biopotential, environmental, and system operational status. PMID:11543453

  15. Prime focus wide-field corrector designs with lossless atmospheric dispersion correction

    SciTech Connect

    Saunders, Will; Gillingham, Peter; Smith, Greg; Kent, Steve; Doel, Peter

    2014-07-18

    Wide-Field Corrector designs are presented for the Blanco and Mayall telescopes, the CFHT and the AAT. The designs are Terezibh-style, with 5 or 6 lenses, and modest negative optical power. They have 2.2-3 degree fields of view, with curved and telecentric focal surfaces suitable for fiber spectroscopy. Some variants also allow wide-field imaging, by changing the last WFC element. Apart from the adaptation of the Terebizh design for spectroscopy, the key feature is a new concept for a 'Compensating Lateral Atmospheric Dispersion Corrector', with two of the lenses being movable laterally by small amounts. This provides excellent atmospheric dispersion correction, without any additional surfaces or absorption. A novel and simple mechanism for providing the required lens motions is proposed, which requires just 3 linear actuators for each of the two moving lenses.

  16. Applying a Genetic Algorithm to Reconfigurable Hardware

    NASA Technical Reports Server (NTRS)

    Wells, B. Earl; Weir, John; Trevino, Luis; Patrick, Clint; Steincamp, Jim

    2004-01-01

    This paper investigates the feasibility of applying genetic algorithms to solve optimization problems that are implemented entirely in reconfgurable hardware. The paper highlights the pe$ormance/design space trade-offs that must be understood to effectively implement a standard genetic algorithm within a modem Field Programmable Gate Array, FPGA, reconfgurable hardware environment and presents a case-study where this stochastic search technique is applied to standard test-case problems taken from the technical literature. In this research, the targeted FPGA-based platform and high-level design environment was the Starbridge Hypercomputing platform, which incorporates multiple Xilinx Virtex II FPGAs, and the Viva TM graphical hardware description language.

  17. Formal hardware verification of digital circuits

    NASA Technical Reports Server (NTRS)

    Joyce, J.; Seger, C.-J.

    1991-01-01

    The use of formal methods to verify the correctness of digital circuits is less constrained by the growing complexity of digital circuits than conventional methods based on exhaustive simulation. This paper briefly outlines three main approaches to formal hardware verification: symbolic simulation, state machine analysis, and theorem-proving.

  18. Design and progress toward a multi-conjugate adaptive optics system for distributed aberration correction

    SciTech Connect

    Baker, K; Olivier, S; Tucker, J; Silva, D; Gavel, D; Lim, R; Gratrix, E

    2004-08-17

    This article investigates the use of a multi-conjugate adaptive optics system to improve the field-of-view for the system. The emphasis of this research is to develop techniques to improve the performance of optical systems with applications to horizontal imaging. The design and wave optics simulations of the proposed system are given. Preliminary results from the multi-conjugate adaptive optics system are also presented. The experimental system utilizes a liquid-crystal spatial light modulator and an interferometric wave-front sensor for correction and sensing of the phase aberrations, respectively.

  19. The correct lens mount lightweighting design and thermal stress OPD analysis in Cassegrain telescope

    NASA Astrophysics Data System (ADS)

    Hsu, Ming-Ying; Chan, Chia-Yen; Lin, Wei-Cheng; Chang, Shenq-Tsong; Huang, Ting-Ming

    2013-09-01

    This study is trying to evaluate different lens barrel material, caused lens stress OPD (Optical Path Different) in different temperature condition. The Cassegrain telescope's correct lens assembly are including as correct lens, lens mount, spacer, mount barrel and retainer. The lens barrel initial design is made by invar, but system mass limit is need to lightweighting to meet requirement. Therefore, the lens barrel material is tried to replace to lower density material, such as aluminum and titanium alloy. Meanwhile, the aluminum or titanium alloy material properties CTE (Coefficient of Thermal Expansion) are larger then invar. Thus, the high CTE material will introduce larger thermal stress into the optical system in different temperature condition. This article is analysis the correct lens assembly thermal stress and optical performance in different lens mount material. From above conditions, using FEM (Finite Element Method) and optical software, simulation and optimization the lens mount to achieve system mass requirement.

  20. Microbiologic assay of space hardware.

    NASA Technical Reports Server (NTRS)

    Favero, M. S.

    1971-01-01

    Review of the procedures used in the microbiological examination of space hardware. The general procedure for enumerating aerobic and anaerobic microorganisms and spores is outlined. Culture media and temperature-time cycles used for incubation are reviewed, along with assay systems designed for the enumeration of aerobic and anaerobic spores. The special problems which are discussed are involved in the precise and accurate enumeration of microorganisms on surfaces and in the neutralization of viable organisms buried inside solid materials that could be released to a planet's surface if the solid should be fractured. Special attention is given to sampling procedures including also the indirect techniques of surface assays of space hardware such as those using detachable or fallout strips. Some data on comparative levels of microbial contamination on lunar and planetary spacecraft are presented.

  1. Decoding: Codes and hardware implementation

    NASA Technical Reports Server (NTRS)

    Sulzer, M. P.; Woodman, R. F.

    1983-01-01

    The MST radars vary considerably from one installation to the next in the type of hardware, operating schedule and associated personnel. Most such systems do not have the computing power to decode in software when the decoding must be performed for each received pulse, as is required for certain sets of phase codes. These sets provide the best signal to sidelobe ratio when operating at the minimum band length allowed by the bandwidth of the transmitter. The development of the hardware phase decoder, and the applicability of each to decoding MST radar signals are discussed. A new design for a decoder which is very inexpensive to build, easy to add to an existing system and is capable of decoding on each received pulse using codes with a band length as short as one microsecond is presented.

  2. DESIGN OF TWO-DIMENSIONAL SUPERSONIC TURBINE ROTOR BLADES WITH BOUNDARY-LAYER CORRECTION

    NASA Technical Reports Server (NTRS)

    Goldman, L. J.

    1994-01-01

    A computer program has been developed for the design of supersonic rotor blades where losses are accounted for by correcting the ideal blade geometry for boundary layer displacement thickness. The ideal blade passage is designed by the method of characteristics and is based on establishing vortex flow within the passage. Boundary-layer parameters (displacement and momentum thicknesses) are calculated for the ideal passage, and the final blade geometry is obtained by adding the displacement thicknesses to the ideal nozzle coordinates. The boundary-layer parameters are also used to calculate the aftermixing conditions downstream of the rotor blades assuming the flow mixes to a uniform state. The computer program input consists essentially of the rotor inlet and outlet Mach numbers, upper- and lower-surface Mach numbers, inlet flow angle, specific heat ratio, and total flow conditions. The program gas properties are set up for air. Additional gases require changes to be made to the program. The computer output consists of the corrected rotor blade coordinates, the principal boundary-layer parameters, and the aftermixing conditions. This program is written in FORTRAN IV for batch execution and has been implemented on an IBM 7094. This program was developed in 1971.

  3. Computer hardware fault administration

    DOEpatents

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-09-14

    Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

  4. Space shuttle main engine hardware simulation

    NASA Technical Reports Server (NTRS)

    Vick, H. G.; Hampton, P. W.

    1985-01-01

    The Huntsville Simulation Laboratory (HSL) provides a simulation facility to test and verify the space shuttle main engine (SSME) avionics and software system using a maximum complement of flight type hardware. The HSL permits evaluations and analyses of the SSME avionics hardware, software, control system, and mathematical models. The laboratory has performed a wide spectrum of tests and verified operational procedures to ensure system component compatibility under all operating conditions. It is a test bed for integration of hardware/software/hydraulics. The HSL is and has been an invaluable tool in the design and development of the SSME.

  5. The design of flux-corrected transport (FCT) algorithms on structured grids

    NASA Astrophysics Data System (ADS)

    Zalesak, Steven T.

    2005-12-01

    A given flux-corrected transport (FCT) algorithm consists of three components: (1) a high order algorithm to which it reduces in smooth parts of the flow field; (2) a low order algorithm to which it reduces in parts of the flow devoid of smoothness; and (3) a flux limiter which calculates the weights assigned to the high and low order algorithms, in flux form, in the various regions of the flow field. In this dissertation, we describe a set of design principles that significantly enhance the accuracy and robustness of FCT algorithms by enhancing the accuracy and robustness of each of the three components individually. These principles include the use of very high order spatial operators in the design of the high order fluxes, the use of non-clipping flux limiters, the appropriate choice of constraint variables in the critical flux-limiting step, and the implementation of a "failsafe" flux-limiting strategy. We show via standard test problems the kind of algorithm performance one can expect if these design principles are adhered to. We give examples of applications of these design principles in several areas of physics. Finally, we compare the performance of these enhanced algorithms with that of other recent front-capturing methods.

  6. Testing of hardware implementation of infrared image enhancing algorithm

    NASA Astrophysics Data System (ADS)

    Dulski, R.; Sosnowski, T.; PiÄ tkowski, T.; Trzaskawka, P.; Kastek, M.; Kucharz, J.

    2012-10-01

    The interpretation of IR images depends on radiative properties of observed objects and surrounding scenery. Skills and experience of an observer itself are also of great importance. The solution to improve the effectiveness of observation is utilization of algorithm of image enhancing capable to improve the image quality and the same effectiveness of object detection. The paper presents results of testing the hardware implementation of IR image enhancing algorithm based on histogram processing. Main issue in hardware implementation of complex procedures for image enhancing algorithms is high computational cost. As a result implementation of complex algorithms using general purpose processors and software usually does not bring satisfactory results. Because of high efficiency requirements and the need of parallel operation, the ALTERA's EP2C35F672 FPGA device was used. It provides sufficient processing speed combined with relatively low power consumption. A digital image processing and control module was designed and constructed around two main integrated circuits: a FPGA device and a microcontroller. Programmable FPGA device performs image data processing operations which requires considerable computing power. It also generates the control signals for array readout, performs NUC correction and bad pixel mapping, generates the control signals for display module and finally executes complex image processing algorithms. Implemented adaptive algorithm is based on plateau histogram equalization. Tests were performed on real IR images of different types of objects registered in different spectral bands. The simulations and laboratory experiments proved the correct operation of the designed system in executing the sophisticated image enhancement.

  7. Removal of broken hardware.

    PubMed

    Hak, David J; McElvany, Matthew

    2008-02-01

    Despite advances in metallurgy, fatigue failure of hardware is common when a fracture fails to heal. Revision procedures can be difficult, usually requiring removal of intact or broken hardware. Several different methods may need to be attempted to successfully remove intact or broken hardware. Broken intramedullary nail cross-locking screws may be advanced out by impacting with a Steinmann pin. Broken open-section (Küntscher type) intramedullary nails may be removed using a hook. Closed-section cannulated intramedullary nails require additional techniques, such as the use of guidewires or commercially available extraction tools. Removal of broken solid nails requires use of a commercial ratchet grip extractor or a bone window to directly impact the broken segment. Screw extractors, trephines, and extraction bolts are useful for removing stripped or broken screws. Cold-welded screws and plates can complicate removal of locked implants and require the use of carbide drills or high-speed metal cutting tools. Hardware removal can be a time-consuming process, and no single technique is uniformly successful. PMID:18252842

  8. The Hardware Dilemma.

    ERIC Educational Resources Information Center

    ELECTRONIC Learning, 1983

    1983-01-01

    Profiles 24 microcomputers used by educators in elementary and secondary schools, presenting information from manufacturers (price, memory, languages, keyboard, screen display, graphics, sound, color, networking, compatible machine) and teacher commentary. Four micro-guides dealing with understanding specifications, finding hardware reviews,…

  9. Development of robotics facility docking test hardware

    NASA Technical Reports Server (NTRS)

    Loughead, T. E.; Winkler, R. V.

    1984-01-01

    Design and fabricate test hardware for NASA's George C. Marshall Space Flight Center (MSFC) are reported. A docking device conceptually developed was fabricated, and two docking targets which provide high and low mass docking loads were required and were represented by an aft 61.0 cm section of a Hubble space telescope (ST) mockup and an upgrading of an existing multimission modular spacecraft (MSS) mockup respectively. A test plan is developed for testing the hardware.

  10. The Design of Flux-Corrected Transport (FCT) Algorithms For Structured Grids

    NASA Astrophysics Data System (ADS)

    Zalesak, Steven T.

    A given flux-corrected transport (FCT) algorithm consists of three components: 1) a high order algorithm to which it reduces in smooth parts of the flow; 2) a low order algorithm to which it reduces in parts of the flow devoid of smoothness; and 3) a flux limiter which calculates the weights assigned to the high and low order fluxes in various regions of the flow field. One way of optimizing an FCT algorithm is to optimize each of these three components individually. We present some of the ideas that have been developed over the past 30 years toward this end. These include the use of very high order spatial operators in the design of the high order fluxes, non-clipping flux limiters, the appropriate choice of constraint variables in the critical flux-limiting step, and the implementation of a "failsafe" flux-limiting strategy.

  11. Design and real time implementation of single phase boost power factor correction converter.

    PubMed

    Bouafassa, Amar; Rahmani, Lazhar; Mekhilef, Saad

    2015-03-01

    This paper presents a real time implementation of the single-phase power factor correction (PFC) AC-DC boost converter. A combination of higher order sliding mode controller based on super twisting algorithm and predictive control techniques are implemented to improve the performance of the boost converter. Due to the chattering effects, the higher order sliding mode control (HOSMC) is designed. Also, the predictive technique is modified taking into account the large computational delays. The robustness of the controller is verified conducting simulation in MATLAB, the results show good performances in both steady and transient states. An experiment is conducted through a test bench based on dSPACE 1104. The experimental results proved that the proposed controller enhanced the performance of the converter under different parameters variations. PMID:25457043

  12. The Design of Flux-Corrected Transport (FCT) Algorithms for Structured Grids

    NASA Astrophysics Data System (ADS)

    Zalesak, Steven T.

    A given flux-corrected transport (FCT) algorithm consists of three components: (1) a high order algorithm to which it reduces in smooth parts of the flow; (2) a low order algorithm to which it reduces in parts of the flow devoid of smoothness; and (3) a flux limiter which calculates the weights assigned to the high and low order fluxes in various regions of the flow field. One way of optimizing an FCT algorithm is to optimize each of these three components individually. We present some of the ideas that have been developed over the past 30 years toward this end. These include the use of very high order spatial operators in the design of the high order fluxes, non-clipping flux limiters, the appropriate choice of constraint variables in the critical flux-limiting step, and the implementation of a "failsafe" flux-limiting strategy. This chapter confines itself to the design of FCT algorithms for structured grids, using a finite volume formalism, for this is the area with which the present author is most familiar. The reader will find excellent material on the design of FCT algorithms for unstructured grids, using both finite volume and finite element formalisms, in the chapters by Professors Löhner, Baum, Kuzmin, Turek, and Möller in the present volume.

  13. Subclass problem-dependent design for error-correcting output codes.

    PubMed

    Escalera, Sergio; Tax, David M J; Pujol, Oriol; Radeva, Petia; Duin, Robert P W

    2008-06-01

    A common way to model multi-class classification problems is by means of Error-Correcting Output Codes (ECOC). Given a multi-class problem, the ECOC technique designs a code word for each class, where each position of the code identifies the membership of the class for a given binary problem. A classification decision is obtained by assigning the label of the class with the closest code. One of the main requirements of the ECOC design is that the base classifier is capable of splitting each sub-group of classes from each binary problem. However, we can not guarantee that a linear classifier model convex regions. Furthermore, non-linear classifiers also fail to manage some type of surfaces. In this paper, we present a novel strategy to model multi-class classification problems using sub-class information in the ECOC framework. Complex problems are solved by splitting the original set of classes into sub-classes, and embedding the binary problems in a problem-dependent ECOC design. Experimental results show that the proposed splitting procedure yields a better performance when the class overlap or the distribution of the training objects conceil the decision boundaries for the base classifier. The results are even more significant when one has a sufficiently large training size. PMID:18421109

  14. Safe to Fly: Certifying COTS Hardware for Spaceflight

    NASA Technical Reports Server (NTRS)

    Fichuk, Jessica L.

    2011-01-01

    Providing hardware for the astronauts to use on board the Space Shuttle or International Space Station (ISS) involves a certification process that entails evaluating hardware safety, weighing risks, providing mitigation, and verifying requirements. Upon completion of this certification process, the hardware is deemed safe to fly. This process from start to finish can be completed as quickly as 1 week or can take several years in length depending on the complexity of the hardware and whether the item is a unique custom design. One area of cost and schedule savings that NASA implements is buying Commercial Off the Shelf (COTS) hardware and certifying it for human spaceflight as safe to fly. By utilizing commercial hardware, NASA saves time not having to develop, design and build the hardware from scratch, as well as a timesaving in the certification process. By utilizing COTS hardware, the current detailed certification process can be simplified which results in schedule savings. Cost savings is another important benefit of flying COTS hardware. Procuring COTS hardware for space use can be more economical than custom building the hardware. This paper will investigate the cost savings associated with certifying COTS hardware to NASA s standards rather than performing a custom build.

  15. Design and Implementation of an Online Auxiliary System for Correcting Japanese Composition

    ERIC Educational Resources Information Center

    Liu, Yuqin; Jiang, Guohai; Han, Lanling; Lin, Mingxing

    2013-01-01

    In language learning, error correction information given by teachers for student compositions is of great value in both teaching and learning. However, in traditional paper-based error correction mode, error correction information is easily lost and cannot be fed back to students systematically. The aim of this research is to provide maximum…

  16. DCSP hardware maintenance system

    SciTech Connect

    Pazmino, M.

    1995-11-01

    This paper discusses the necessary changes to be implemented on the hardware side of the DCSP database. DCSP is currently tracking hardware maintenance costs in six separate databases. The goal is to develop a system that combines all data and works off a single database. Some of the tasks that will be discussed in this paper include adding the capability for report generation, creating a help package and preparing a users guide, testing the executable file, and populating the new database with data taken from the old database. A brief description of the basic process used in developing the system will also be discussed. Conclusions about the future of the database and the delivery of the final product are then addressed, based on research and the desired use of the system.

  17. Evolvable, reconfigurable hardware for future space systems

    NASA Technical Reports Server (NTRS)

    Stoica, A.; Zebulum, R. S.; Keymeulen, D.; Ferguson, M. I.; Thakoor, A.

    2002-01-01

    This paper overviews Evolvable Hardware (EHW) technology, examining its potential for enhancing survivability and flexibility of future space systems. EHW refers to selfconfiguration of electronic hardware by evolutionary/genetic search mechanisms. Evolvable Hardware can maintain existing functionality in the presence of faults and degradations due to aging, temperature and radiation. It can also configure itself for new functionality when required for mission changes or encountered opportunities. The paper illustrates hardware evolution in silicon using a JPL-designed programmable device reconfigurable at transistor level as the platform and a genetic algorithm running on a DSP as the reconfiguration mechanism. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The experiments demonstrate functional recovery from faults as well as from degradation at extreme temperatures indicating the possibility of expanding the operational range of extreme electronics through evolved circuit solutions.

  18. RRFC hardware operation manual

    SciTech Connect

    Abhold, M.E.; Hsue, S.T.; Menlove, H.O.; Walton, G.

    1996-05-01

    The Research Reactor Fuel Counter (RRFC) system was developed to assay the {sup 235}U content in spent Material Test Reactor (MTR) type fuel elements underwater in a spent fuel pool. RRFC assays the {sup 235}U content using active neutron coincidence counting and also incorporates an ion chamber for gross gamma-ray measurements. This manual describes RRFC hardware, including detectors, electronics, and performance characteristics.

  19. Exascale Hardware Architectures Working Group

    SciTech Connect

    Hemmert, S; Ang, J; Chiang, P; Carnes, B; Doerfler, D; Leininger, M; Dosanjh, S; Fields, P; Koch, K; Laros, J; Noe, J; Quinn, T; Torrellas, J; Vetter, J; Wampler, C; White, A

    2011-03-15

    relatively immediate, as there is only a small window of opportunity to influence hardware design for 2018 machines. Given the short timeline a firm co-design methodology with vendors is of prime importance.

  20. Analysis and Design of a Gated Envelope Feedback Technique for Automatic Hardware Reconfiguration of RFIC Power Amplifiers, with Full On-Chip Implementation in Gallium Arsenide Heterojunction Bipolar Transistor Technology

    NASA Astrophysics Data System (ADS)

    Constantin, Nicolas Gerard David

    In this doctoral dissertation, the author presents the theoretical foundation, the analysis and design of analog and RF circuits, the chip level implementation, and the experimental validation pertaining to a new radio frequency integrated circuit (RFIC) power amplifier (PA) architecture that is intended for wireless portable transceivers. A method called Gated Envelope Feedback is proposed to allow the automatic hardware reconfiguration of a stand-alone RFIC PA in multiple states for power efficiency improvement purposes. The method uses self-operating and fully integrated circuitry comprising RF power detection, switching and sequential logic, and RF envelope feedback in conjunction with a hardware gating function for triggering and activating current reduction mechanisms as a function of the transmitted RF power level. Because of the critical role that RFIC PA components occupy in modern wireless transceivers, and given the major impact that these components have on the overall RF performances and energy consumption in wireless transceivers, very significant benefits stem from the underlying innovations. The method has been validated through the successful design of a 1.88GHz COMA RFIC PA with automatic hardware reconfiguration capability, using an industry renowned state-of-the-art GaAs HBT semiconductor process developed and owned by Skyworks Solutions, Inc., USA. The circuit techniques that have enabled the successful and full on-chip embodiment of the technique are analyzed in details. The IC implementation is discussed, and experimental results showing significant current reduction upon automatic hardware reconfiguration, gain regulation performances, and compliance with the stringent linearity requirements for COMA transmission demonstrate that the gated envelope feedback method is a viable and promising approach to automatic hardware reconfiguration of RFIC PA's for current reduction purposes. Moreover, in regard to on-chip integration of advanced PA

  1. Hardware development process for Human Research facility applications

    NASA Astrophysics Data System (ADS)

    Bauer, Liz

    2000-01-01

    The simple goal of the Human Research Facility (HRF) is to conduct human research experiments on the International Space Station (ISS) astronauts during long-duration missions. This is accomplished by providing integration and operation of the necessary hardware and software capabilities. A typical hardware development flow consists of five stages: functional inputs and requirements definition, market research, design life cycle through hardware delivery, crew training, and mission support. The purpose of this presentation is to guide the audience through the early hardware development process: requirement definition through selecting a development path. Specific HRF equipment is used to illustrate the hardware development paths. .

  2. Method for Automated Bone Shape Correction within Bone Distraction Procedure

    NASA Astrophysics Data System (ADS)

    Blynskiy, F. Yu

    2016-01-01

    The method for automated bone shape correction within bone distraction procedure is presented. High precision deformation angle measurement is provided by the software for X- Ray images processing. Special BDC v.1.0.1. application is designed. The purpose of the BDC is modeling of the bone geometry structure to calculate the appropriate distraction forces. The correction procedure control is realized by the hardware of the distraction system.

  3. A CLIPS based personal computer hardware diagnostic system

    NASA Technical Reports Server (NTRS)

    Whitson, George M.

    1991-01-01

    Often the person designated to repair personal computers has little or no knowledge of how to repair a computer. Described here is a simple expert system to aid these inexperienced repair people. The first component of the system leads the repair person through a number of simple system checks such as making sure that all cables are tight and that the dip switches are set correctly. The second component of the system assists the repair person in evaluating error codes generated by the computer. The final component of the system applies a large knowledge base to attempt to identify the component of the personal computer that is malfunctioning. We have implemented and tested our design with a full system to diagnose problems for an IBM compatible system based on the 8088 chip. In our tests, the inexperienced repair people found the system very useful in diagnosing hardware problems.

  4. Design and simulation of e-calendar system circuits

    NASA Astrophysics Data System (ADS)

    Liu, Li-jun

    2015-02-01

    The digital calendar circuits controlled by 80C52 have been designed based on Proteus simulation software. The whole design process is made of three parts: hardware circuits, software programming and software simulation. Finally, it shows that the circuit design of hardware and software is correct through Proteus software simulation. The method of circuit design is systematic and practical, which will provide certain design ideas and reference value for display circuit in the future.

  5. Circulation control lift generation experiment: Hardware development

    NASA Technical Reports Server (NTRS)

    Panontin, T. L.

    1985-01-01

    A circulation control airfoil and its accompanying hardware were developed to allow the investigation of lift generation that is independent of airfoil angle of attack and relative flow velocity. The test equipment, designed for use in a water tunnel, includes the blown airfoil, the support systems for both flow visualization and airfoil load measurement, and the fluid control system, which utilizes hydraulic technology. The primary design tasks, the selected solutions, and the unforseen problems involved in the development of these individual components of hardware are described.

  6. Human Centered Hardware Modeling and Collaboration

    NASA Technical Reports Server (NTRS)

    Stambolian Damon; Lawrence, Brad; Stelges, Katrine; Henderson, Gena

    2013-01-01

    In order to collaborate engineering designs among NASA Centers and customers, to in clude hardware and human activities from multiple remote locations, live human-centered modeling and collaboration across several sites has been successfully facilitated by Kennedy Space Center. The focus of this paper includes innovative a pproaches to engineering design analyses and training, along with research being conducted to apply new technologies for tracking, immersing, and evaluating humans as well as rocket, vehic le, component, or faci lity hardware utilizing high resolution cameras, motion tracking, ergonomic analysis, biomedical monitoring, wor k instruction integration, head-mounted displays, and other innovative human-system integration modeling, simulation, and collaboration applications.

  7. Mir hardware heritage

    NASA Technical Reports Server (NTRS)

    Portree, David S. F.

    1995-01-01

    The heritage of the major Mir complex hardware elements is described. These elements include Soyuz-TM and Progress-M; the Kvant, Kvant 2, and Kristall modules; and the Mir base block. Configuration changes and major mission events of the Salyut 6, Salyut 7, and Mir multiport space stations are described in detail for the period 1977-1994. A comparative chronology of U.S. and Soviet/Russian manned spaceflight is also given for that period. The 68 illustrations include comparative scale drawings of U.S. and Russian spacecraft as well as sequential drawings depicting missions and mission events.

  8. Robustness in Digital Hardware

    NASA Astrophysics Data System (ADS)

    Woods, Roger; Lightbody, Gaye

    The growth in electronics has probably been the equivalent of the Industrial Revolution in the past century in terms of how much it has transformed our daily lives. There is a great dependency on technology whether it is in the devices that control travel (e.g., in aircraft or cars), our entertainment and communication systems, or our interaction with money, which has been empowered by the onset of Internet shopping and banking. Despite this reliance, there is still a danger that at some stage devices will fail within the equipment's lifetime. The purpose of this chapter is to look at the factors causing failure and address possible measures to improve robustness in digital hardware technology and specifically chip technology, giving a long-term forecast that will not reassure the reader!

  9. Magnetic Field Apparatus (MFA) Hardware Test

    NASA Technical Reports Server (NTRS)

    Anderson, Ken; Boody, April; Reed, Dave; Wang, Chung; Stuckey, Bob; Cox, Dave

    1999-01-01

    The objectives of this study are threefold: (1) Provide insight into water delivery in microgravity and determine optimal germination paper wetting for subsequent seed germination in microgravity; (2) Observe the behavior of water exposed to a strong localized magnetic field in microgravity; and (3) Simulate the flow of fixative (using water) through the hardware. The Magnetic Field Apparatus (MFA) is a new piece of hardware slated to fly on the Space Shuttle in early 2001. MFA is designed to expose plant tissue to magnets in a microgravity environment, deliver water to the plant tissue, record photographic images of plant tissue, and deliver fixative to the plant tissue.

  10. Codem: software/hardware codesign for embedded multicore systems supporting hardware services

    NASA Astrophysics Data System (ADS)

    Wang, Chao; Li, Xi; Zhou, Xuehai; Nedjah, Nadia; Wang, Aili

    2015-01-01

    Efficient software/hardware codesign is posing significant challenges to embedded systems. This paper proposes Codem, a software/hardware codesign flow for embedded systems, which models both processors and Intellectual Property (IP) cores as services. Tasks are regarded as abstract instructions which can be scheduled to IP cores for parallel execution automatically. In order to guide the hardware implementations of the hot spot functions, this paper incorporates a novel hot spot-based profiling technique to observe the hot spot functions while the application is being simulated. Furthermore, based on the hot spot of various applications, an adaptive mapping algorithm is presented to partition the application into multiple software/hardware tasks. We test the profiling-based design flow with classic Sort applications. Experimental results demonstrate that Codem can efficiently help researchers to identify the hot spots, and also outline a new direction to combine profiling techniques with state-of-the-art reconfigurable computing platforms for specific task acceleration.

  11. Fine figure correction and other applications using novel MRF fluid designed for ultra-low roughness

    NASA Astrophysics Data System (ADS)

    Maloney, Chris; Oswald, Eric S.; Dumas, Paul

    2015-10-01

    An increasing number of technologies require ultra-low roughness (ULR) surfaces. Magnetorheological Finishing (MRF) is one of the options for meeting the roughness specifications for high-energy laser, EUV and X-ray applications. A novel MRF fluid, called C30, has been developed to finish surfaces to ULR. This novel MRF fluid is able to achieve <1.5Å RMS roughness on fused silica and other materials, but has a lower material removal rate with respect to other MRF fluids. As a result of these properties, C30 can also be used for applications in addition to finishing ULR surfaces. These applications include fine figure correction, figure correcting extremely soft materials and removing cosmetic defects. The effectiveness of these new applications is explored through experimental data. The low removal rate of C30 gives MRF the capability to fine figure correct low amplitude errors that are usually difficult to correct with higher removal rate fluids. The ability to figure correct extremely soft materials opens up MRF to a new realm of materials that are difficult to polish. C30 also offers the ability to remove cosmetic defects that often lead to failure during visual quality inspections. These new applications for C30 expand the niche in which MRF is typically used for.

  12. Hardware assisted hypervisor introspection.

    PubMed

    Shi, Jiangyong; Yang, Yuexiang; Tang, Chuan

    2016-01-01

    In this paper, we introduce hypervisor introspection, an out-of-box way to monitor the execution of hypervisors. Similar to virtual machine introspection which has been proposed to protect virtual machines in an out-of-box way over the past decade, hypervisor introspection can be used to protect hypervisors which are the basis of cloud security. Virtual machine introspection tools are usually deployed either in hypervisor or in privileged virtual machines, which might also be compromised. By utilizing hardware support including nested virtualization, EPT protection and #BP, we are able to monitor all hypercalls belongs to the virtual machines of one hypervisor, include that of privileged virtual machine and even when the hypervisor is compromised. What's more, hypercall injection method is used to simulate hypercall-based attacks and evaluate the performance of our method. Experiment results show that our method can effectively detect hypercall-based attacks with some performance cost. Lastly, we discuss our furture approaches of reducing the performance cost and preventing the compromised hypervisor from detecting the existence of our introspector, in addition with some new scenarios to apply our hypervisor introspection system. PMID:27330913

  13. Hardware multiplier processor

    DOEpatents

    Pierce, Paul E.

    1986-01-01

    A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

  14. Hardware multiplier processor

    DOEpatents

    Pierce, P.E.

    A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

  15. Analysis and design of modular three-phase power factor correction schemes for utility interface

    NASA Astrophysics Data System (ADS)

    Hahn, Jae-Hong

    The extensive use of non-linear and electronically switched loads in power system has lead to higher incidences of harmonic distortion of the voltage and current waveforms. Harmonic currents degrade power quality and are considered the main source of many system malfunctions. Technical guidelines and standards regarding suppressions of system harmonic contents have been enacted. This dissertation proposes several new three-phase power factor correction (PFC) schemes using single-phase PFC modules. An integrated single-switch approach is first proposed. This is essentially an add-on solution to standard ASD's. This approach is based on circulating third harmonic current between neutral and DC mid-point by utilizing a lossless resistor. Single-phase PFC emulates this resistor to control the amplitude of the current, which is implemented by the dynamic breaking chopper available in standard adjustable speed drives (ASD's). This approach is also capable of reducing harmonic distortion in multiple drives. Analysis, design and simulations are conducted to determine the performance of the proposed scheme with different line impedances and with and without dc-link inductance in the ASD. Experimental results are presented using commercial ASD retrofitted with the proposed approach. Second scheme proposes a three-phase PFC using two standard single-phase PFC modules. In this approach, three-phase input is transformed into two-phase by means of 0.14 pu autotransformer. Two standard single-phase PFC modules are employed to process two-phase power to do output. Split inductors and diodes are employed to limit the interaction between the two phases. A method to eliminate the interaction between phases is also described. Due to cascade operation of two PFC stages, low frequency (120Hz) ripple in dc-link is cancelled. An active interphase transformer (IPT) scheme is proposed to draw sinusoidal input line currents, in the third study. This scheme utilizes a unique combination of a

  16. Hardware demonstration of flexible beam control

    NASA Technical Reports Server (NTRS)

    Schaechter, D. B.

    1980-01-01

    An experiment employing a pinned-free flexible beam has been constructed to demonstrate and verify several facets of the control of flexible structures. The desired features of the experiment are to demonstrate active shape control, active dynamic control, adaptive control, various control law design approaches, and associated hardware requirements and mechanization difficulties. This paper contains the analytical work performed in support of the facility development, the final design specifications, control law synthesis, and some preliminary results.

  17. Experiences with the design and construction of wideband spectral line and pulsar instrumentation with CASPER hardware and software: the digital backend system

    NASA Astrophysics Data System (ADS)

    Ford, John M.; Prestage, Richard M.; Bloss, Marty

    2014-07-01

    NRAO recently built the Digital Backend System (DIBAS) for the Shanghai Astronomical Observatory's (SHAO) 65 meter radio telescope. The machine was created from the design of the VErsatile GBT Astronomical Spec- trometer (VEGAS) by adding pulsar search and timing modes to complement the VEGAS spectral line modes. Together the pulsar and spectral line modes cover all anticipated science requirements for the 65 meter, except VLBI. This paper introduces the radio telescope backend and explores the project management challenges of the project. These include managing the high level of reuse of existing FPGA designs, an aggressive schedule for the project, and the software design constraints imposed on the project.

  18. Hardware Removal in Craniomaxillofacial Trauma

    PubMed Central

    Cahill, Thomas J.; Gandhi, Rikesh; Allori, Alexander C.; Marcus, Jeffrey R.; Powers, David; Erdmann, Detlev; Hollenbeck, Scott T.; Levinson, Howard

    2015-01-01

    Background Craniomaxillofacial (CMF) fractures are typically treated with open reduction and internal fixation. Open reduction and internal fixation can be complicated by hardware exposure or infection. The literature often does not differentiate between these 2 entities; so for this study, we have considered all hardware exposures as hardware infections. Approximately 5% of adults with CMF trauma are thought to develop hardware infections. Management consists of either removing the hardware versus leaving it in situ. The optimal approach has not been investigated. Thus, a systematic review of the literature was undertaken and a resultant evidence-based approach to the treatment and management of CMF hardware infections was devised. Materials and Methods A comprehensive search of journal articles was performed in parallel using MEDLINE, Web of Science, and ScienceDirect electronic databases. Keywords and phrases used were maxillofacial injuries; facial bones; wounds and injuries; fracture fixation, internal; wound infection; and infection. Our search yielded 529 articles. To focus on CMF fractures with hardware infections, the full text of English-language articles was reviewed to identify articles focusing on the evaluation and management of infected hardware in CMF trauma. Each article’s reference list was manually reviewed and citation analysis performed to identify articles missed by the search strategy. There were 259 articles that met the full inclusion criteria and form the basis of this systematic review. The articles were rated based on the level of evidence. There were 81 grade II articles included in the meta-analysis. Result Our meta-analysis revealed that 7503 patients were treated with hardware for CMF fractures in the 81 grade II articles. Hardware infection occurred in 510 (6.8%) of these patients. Of those infections, hardware removal occurred in 264 (51.8%) patients; hardware was left in place in 166 (32.6%) patients; and in 80 (15.6%) cases

  19. Onboard utilization of ground control points for image correction. Volume 4: Correlation analysis software design

    NASA Technical Reports Server (NTRS)

    1981-01-01

    The software utilized for image correction accuracy measurement is described. The correlation analysis program is written to allow the user various tools to analyze different correlation algorithms. The algorithms were tested using LANDSAT imagery in two different spectral bands. Three classification algorithms are implemented.

  20. Flight Avionics Hardware Roadmap

    NASA Technical Reports Server (NTRS)

    Some, Raphael; Goforth, Monte; Chen, Yuan; Powell, Wes; Paulick, Paul; Vitalpur, Sharada; Buscher, Deborah; Wade, Ray; West, John; Redifer, Matt; Partridge, Harry; Sherman, Aaron; McCabe, Mary

    2014-01-01

    The Avionics Technology Roadmap takes an 80% approach to technology investment in spacecraft avionics. It delineates a suite of technologies covering foundational, component, and subsystem-levels, which directly support 80% of future NASA space mission needs. The roadmap eschews high cost, limited utility technologies in favor of lower cost, and broadly applicable technologies with high return on investment. The roadmap is also phased to support future NASA mission needs and desires, with a view towards creating an optimized investment portfolio that matures specific, high impact technologies on a schedule that matches optimum insertion points of these technologies into NASA missions. The roadmap looks out over 15+ years and covers some 114 technologies, 58 of which are targeted for TRL6 within 5 years, with 23 additional technologies to be at TRL6 by 2020. Of that number, only a few are recommended for near term investment: 1. Rad Hard High Performance Computing 2. Extreme temperature capable electronics and packaging 3. RFID/SAW-based spacecraft sensors and instruments 4. Lightweight, low power 2D displays suitable for crewed missions 5. Radiation tolerant Graphics Processing Unit to drive crew displays 6. Distributed/reconfigurable, extreme temperature and radiation tolerant, spacecraft sensor controller and sensor modules 7. Spacecraft to spacecraft, long link data communication protocols 8. High performance and extreme temperature capable C&DH subsystem In addition, the roadmap team recommends several other activities that it believes are necessary to advance avionics technology across NASA: center dot Engage the OCT roadmap teams to coordinate avionics technology advances and infusion into these roadmaps and their mission set center dot Charter a team to develop a set of use cases for future avionics capabilities in order to decouple this roadmap from specific missions center dot Partner with the Software Steering Committee to coordinate computing hardware

  1. Teaching Robotics Software with the Open Hardware Mobile Manipulator

    ERIC Educational Resources Information Center

    Vona, M.; Shekar, N. H.

    2013-01-01

    The "open hardware mobile manipulator" (OHMM) is a new open platform with a unique combination of features for teaching robotics software and algorithms. On-board low- and high-level processors support real-time embedded programming and motor control, as well as higher-level coding with contemporary libraries. Full hardware designs and…

  2. CHeCS Commanding Hardware

    NASA Technical Reports Server (NTRS)

    Moore, Jamie

    2010-01-01

    This slide presentation reviews the Crew Health Care System (CHeCS) commanding hardware. It includes information on the hardware status, commanding plan, and command training status with specific information the EV-CPDS 2 and 3, TEPC, MEC, and T2

  3. Lunar and Martian hardware commonality

    NASA Technical Reports Server (NTRS)

    Davis, Hubert P.; Johnson, Robert E.; Phillips, Paul G.; Spear, Donald S.; Stump, William R.; Williams, Franklin U.

    1986-01-01

    A number of different hardware elements were examined for possible Moon/Mars program commonality. These include manned landers; cargo landers, a trans-Mars injection (TMI) stage, traverse vehicles, unmanned surface rovers, habitation modules, and power supplies. Preliminary analysis indicates that it is possible to build a common two-stage manned lander. A single-stage, reusable lander may be practical for the lunar cast, but much less so for the Martian case, and commonality may therefore exist only at the subsystem level. A modified orbit transfer vehicle was examined as a potential cargo lander. Potential cargoes to various destinations were calculated for a Shuttle external tank sized TMI stage. A nuclear powered, long range traverse vehicle was conceptually designed and commonality is considered feasible. Short range, unmanned rovers can be made common without great effort. A surface habitation module may be difficult to make common due to difficulties in landing certain shapes on the Martian surface with aerobraking landers. Common nuclear power sources appear feasible. High temperature radiators appear easy to make common. Low temperature radiators may be difficult to make common. In most of these cases, Martian requirements determine the design.

  4. Economic impact of syndesmosis hardware removal.

    PubMed

    Lalli, Trapper A J; Matthews, Leslie J; Hanselman, Andrew E; Hubbard, David F; Bramer, Michelle A; Santrock, Robert D

    2015-09-01

    Ankle syndesmosis injuries are commonly seen with 5-10% of sprains and 10% of ankle fractures involving injury to the ankle syndesmosis. Anatomic reduction has been shown to be the most important predictor of clinical outcomes. Optimal surgical management has been a subject of debate in the literature. The method of fixation, number of screws, screw size, and number of cortices are all controversial. Postoperative hardware removal has also been widely debated in the literature. Some surgeons advocate for elective hardware removal prior to resuming full weightbearing. Returning to the operating room for elective hardware removal results in increased cost to the patient, potential for infection or complication(s), and missed work days for the patient. Suture button devices and bioabsorbable screw fixation present other options, but cortical screw fixation remains the gold standard. This retrospective review was designed to evaluate the economic impact of a second operative procedure for elective removal of 3.5mm cortical syndesmosis screws. Two hundred and two patients with ICD-9 code for "open treatment of distal tibiofibular joint (syndesmosis) disruption" were identified. The medical records were reviewed for those who underwent elective syndesmosis hardware removal. The primary outcome measurements included total hospital billing charges and total hospital billing collection. Secondary outcome measurements included average individual patient operative costs and average operating room time. Fifty-six patients were included in the study. Our institution billed a total of $188,271 (USD) and collected $106,284 (55%). The average individual patient operating room cost was $3579. The average operating room time was 67.9 min. To the best of our knowledge, no study has previously provided cost associated with syndesmosis hardware removal. Our study shows elective syndesmosis hardware removal places substantial economic burden on both the patient and the healthcare system

  5. Explosive-actuated valve design concept that eliminates blow-by. [for the TOPS spacecraft trajectory correction propulsion subsystem

    NASA Technical Reports Server (NTRS)

    Hagler, R., Jr.

    1974-01-01

    A method of evaluating the normally open normally closed, explosive actuated valves that were selected for use in the trajectory correction propulsion subsystem of the Thermoelectric Outer Planet Spacecraft (TOPS) program is presented. The design philosophy which determined the requirements for highly reliable valves that could provide the performance capability during long duration (10 year) missions to the outer planets is discussed. The techniques that were used to fabricate the valves and manifold ten valves into an assembly with the capability of five propellant-flow initiation/isolation sequences are described. The test program, which was conducted to verify valve design requirements, is outlined and the more significant results are shown.

  6. Using the FLUKA Monte Carlo Code to Simulate the Interactions of Ionizing Radiation with Matter to Assist and Aid Our Understanding of Ground Based Accelerator Testing, Space Hardware Design, and Secondary Space Radiation Environments

    NASA Technical Reports Server (NTRS)

    Reddell, Brandon

    2015-01-01

    Designing hardware to operate in the space radiation environment is a very difficult and costly activity. Ground based particle accelerators can be used to test for exposure to the radiation environment, one species at a time, however, the actual space environment cannot be duplicated because of the range of energies and isotropic nature of space radiation. The FLUKA Monte Carlo code is an integrated physics package based at CERN that has been under development for the last 40+ years and includes the most up-to-date fundamental physics theory and particle physics data. This work presents an overview of FLUKA and how it has been used in conjunction with ground based radiation testing for NASA and improve our understanding of secondary particle environments resulting from the interaction of space radiation with matter.

  7. Optical design of a color-corrected 2.75 g visual loupe

    NASA Astrophysics Data System (ADS)

    Cakmakci, Ozan

    2013-11-01

    The key contribution is the optical design of a 2.75 g 2.5× magnification visual loupe developed within the Defense Advanced Research Projects Agency Manufacturable Gradient Index (M-GRIN) phase 2 program. We present a visual loupe (i.e., a Galilean telescope) that is constructed by a positive optical power objective lens that makes use of a spherical gradient index profile and a negative optical power eye lens that collimates the light for visual use. The optical materials and the preform thickness in the design are judiciously designed to be manufacturable within the spherical gradient index design rules available today. A comparison of the M-GRIN design to an all-plastic homogeneous baseline design shows that the M-GRIN design reduces the weight from 4.15 to 2.75 g while maintaining equivalent optical performance of the baseline.

  8. Exercise Countermeasure Hardware Evolution on ISS: The First Decade.

    PubMed

    Korth, Deborah W

    2015-12-01

    The hardware systems necessary to support exercise countermeasures to the deconditioning associated with microgravity exposure have evolved and improved significantly during the first decade of the International Space Station (ISS), resulting in both new types of hardware and enhanced performance capabilities for initial hardware items. The original suite of countermeasure hardware supported the first crews to arrive on the ISS and the improved countermeasure system delivered in later missions continues to serve the astronauts today with increased efficacy. Due to aggressive hardware development schedules and constrained budgets, the initial approach was to identify existing spaceflight-certified exercise countermeasure equipment, when available, and modify it for use on the ISS. Program management encouraged the use of commercial-off-the-shelf (COTS) hardware, or hardware previously developed (heritage hardware) for the Space Shuttle Program. However, in many cases the resultant hardware did not meet the additional requirements necessary to support crew health maintenance during long-duration missions (3 to 12 mo) and anticipated future utilization activities in support of biomedical research. Hardware development was further complicated by performance requirements that were not fully defined at the outset and tended to evolve over the course of design and fabrication. Modifications, ranging from simple to extensive, were necessary to meet these evolving requirements in each case where heritage hardware was proposed. Heritage hardware was anticipated to be inherently reliable without the need for extensive ground testing, due to its prior positive history during operational spaceflight utilization. As a result, developmental budgets were typically insufficient and schedules were too constrained to permit long-term evaluation of dedicated ground-test units ("fleet leader" type testing) to identify reliability issues when applied to long-duration use. In most cases

  9. Transistor Level Circuit Experiments using Evolvable Hardware

    NASA Technical Reports Server (NTRS)

    Stoica, A.; Zebulum, R. S.; Keymeulen, D.; Ferguson, M. I.; Daud, Taher; Thakoor, A.

    2005-01-01

    The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

  10. Management of SSME hardware life utilization

    NASA Technical Reports Server (NTRS)

    Pauschke, J. M.

    1986-01-01

    Statistical and probabilistic reliability methodologies were developed for the determination of hardware life limits for the Space Shuttle Main Engine (SSME). Both methodologies require that a mathematical reliability model of the engine (system) performance be developed as a function of the reliabilities of the components and parts. The system reliability model should be developed from the Failute Modes and Effects Analysis/Critical Items List. The statistical reliability methodology establishes hardware life limits directly from the failure distributions of the components and parts obtained from statistically-designed testing. The probabilistic reliability methodology establishes hardware life limits from a decision analysis methodology which incorporates the component/part reliabilities obtained from a probabilistic structural analysis, a calibrated maintenance program, inspection techniques, and fabrication procedures. Probilistic structural analysis is recommended as a tool to prioritize upgrading of the components and parts. The Weibull probability distribution is presently being investigated by NASA/MSFC to characterize the failure distribution of the SSME hardware from a limited data base of failures.

  11. Support for Diagnosis of Custom Computer Hardware

    NASA Technical Reports Server (NTRS)

    Molock, Dwaine S.

    2008-01-01

    The Coldfire SDN Diagnostics software is a flexible means of exercising, testing, and debugging custom computer hardware. The software is a set of routines that, collectively, serve as a common software interface through which one can gain access to various parts of the hardware under test and/or cause the hardware to perform various functions. The routines can be used to construct tests to exercise, and verify the operation of, various processors and hardware interfaces. More specifically, the software can be used to gain access to memory, to execute timer delays, to configure interrupts, and configure processor cache, floating-point, and direct-memory-access units. The software is designed to be used on diverse NASA projects, and can be customized for use with different processors and interfaces. The routines are supported, regardless of the architecture of a processor that one seeks to diagnose. The present version of the software is configured for Coldfire processors on the Subsystem Data Node processor boards of the Solar Dynamics Observatory. There is also support for the software with respect to Mongoose V, RAD750, and PPC405 processors or their equivalents.

  12. Computer hardware for radiologists: Part I

    PubMed Central

    Indrajit, IK; Alam, A

    2010-01-01

    Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU), the chipset, the random access memory (RAM), the memory modules, bus, storage drives, and ports. The personnel computer (PC) has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs). The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called “buses”. The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute “programs”. A Pentium® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM) is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration. PMID:21042437

  13. Computer hardware for radiologists: Part I.

    PubMed

    Indrajit, Ik; Alam, A

    2010-08-01

    Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU), the chipset, the random access memory (RAM), the memory modules, bus, storage drives, and ports. The personnel computer (PC) has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs). The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called "buses". The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute "programs". A Pentium(®) 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM) is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration. PMID:21042437

  14. Pixel response non-uniformity correction for multi-TDICCD camera based on FPGA

    NASA Astrophysics Data System (ADS)

    Zhai, Guofang

    2013-10-01

    A non-uniformity correction algorithm is proposed and implemented on a Field-Programmable Gate Array (FPGA) hardware platform to solve a pixel response non-uniformity(PRNU) problem of multi Time Delay and Integration Charge Couple Device(TDICCD) camera. The non-uniformity are introduced and the synthetical correction algorithm is presented, in which the two-point correction method is used in a single channel, gain averaging correction method among multi-channel and the sceneadaptive correction method among multi-TDICCD. Then, the correction algorithm is designed. Finally, analyzing the FPGA ability for fix-point processing, the correction algorithm is optimized, and implemented on FPGA. Testing results indicate that the non-uniformity can be decreased from 8.27% to 0.51% for three TDICCDs camera's images with the proposed correction algorithm, proving that this correction algorithm is with high real-time performance, great engineering realization and satisfaction for the system requirements.

  15. Manipulation hardware for microgravity research

    SciTech Connect

    Herndon, J.N.; Glassell, R.L.; Butler, P.L.; Williams, D.M. ); Rohn, D.A. . Lewis Research Center); Miller, J.H. )

    1990-01-01

    The establishment of permanent low earth orbit occupation on the Space Station Freedom will present new opportunities for the introduction of productive flexible automation systems into the microgravity environment of space. The need for robust and reliable robotic systems to support experimental activities normally intended by astronauts will assume great importance. Many experimental modules on the space station are expected to require robotic systems for ongoing experimental operations. When implementing these systems, care must be taken not to introduce deleterious effects on the experiments or on the space station itself. It is important to minimize the acceleration effects on the experimental items being handled while also minimizing manipulator base reaction effects on adjacent experiments and on the space station structure. NASA Lewis Research Center has been performing research on these manipulator applications, focusing on improving the basic manipulator hardware, as well as developing improved manipulator control algorithms. By utilizing the modular manipulator concepts developed during the Laboratory Telerobotic Manipulator program, Oak Ridge National Laboratory has developed an experimental testbed system called the Microgravity Manipulator, incorporating two pitch-yaw modular positioners to provide a 4 dof experimental manipulator arm. A key feature in the design for microgravity manipulation research was the use of traction drives for torque transmission in the modular pitch-yaw differentials.

  16. Design and calibration of a six-axis MEMS sensor array for use in scoliosis correction surgery

    NASA Astrophysics Data System (ADS)

    Benfield, David; Yue, Shichao; Lou, Edmond; Moussa, Walied A.

    2014-08-01

    A six-axis sensor array has been developed to quantify the 3D force and moment loads applied in scoliosis correction surgery. Initially this device was developed to be applied during scoliosis correction surgery and augmented onto existing surgical instrumentation, however, use as a general load sensor is also feasible. The development has included the design, microfabrication, deployment and calibration of a sensor array. The sensor array consists of four membrane devices, each containing piezoresistive sensing elements, generating a total of 16 differential voltage outputs. The calibration procedure has made use of a custom built load application frame, which allows quantified forces and moments to be applied and compared to the outputs from the sensor array. Linear or non-linear calibration equations are generated to convert the voltage outputs from the sensor array back into 3D force and moment information for display or analysis.

  17. 75 FR 67166 - Designation of Two Individuals Pursuant to Executive Order 13224; Correction

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-11-01

    ... the Federal Register of October 25, 2010, in FR Doc. 2010-26809, on page 65556, in the second column... Office of Foreign Assets Control Designation of Two Individuals Pursuant to Executive Order 13224... designation of two individuals pursuant to Executive Order 13224 of September 23, 2001, ``Blocking...

  18. Rethinking image registration on customizable hardware

    NASA Astrophysics Data System (ADS)

    Bowman, David; Tahtali, Murat; Lambert, Andrew

    2010-08-01

    Image registration is one of the most important tasks in image processing and is frequently one of the most computationally intensive. In cases where there is a high likelihood of finding the exact template in the search image, correlation-based methods predominate. Presumably this is because the computational complexity of a correlation operation can be reduced substantially by transforming the task into the frequency domain. Alternative methods such as minimum Sum of Squared Differences (minSSD) are not so tractable and are normally disfavored. This bias is justified when dealing with conventional computer processors since the operations must be conducted in an essentially sequential manner however we demonstrate it is normally unjustified when the processing is undertaken on customizable hardware such as FPGAs where tasks can be temporally and/or spatially parallelized. This is because the gate-based logic of an FPGA is better suited to the tasks of minSSD i.e. signed-addition hardware can be very cheaply implemented in FPGA fabric, and square operations are easily implemented via a look-up table. In contrast, correlationbased methods require extensive use of multiplier hardware which cannot be so cheaply implemented in the device. Even with modern DSP-oriented FPGAs which contain many "hard" multipliers we experience at least an order of magnitude increase in the number of minSSD hardware modules we can implement compared to cross-correlation modules. We demonstrate successful use and comparison of techniques within an FPGA for registration and correction of turbulence degraded images.

  19. NDAS Hardware Translation Layer Development

    NASA Technical Reports Server (NTRS)

    Nazaretian, Ryan N.; Holladay, Wendy T.

    2011-01-01

    The NASA Data Acquisition System (NDAS) project is aimed to replace all DAS software for NASA s Rocket Testing Facilities. There must be a software-hardware translation layer so the software can properly talk to the hardware. Since the hardware from each test stand varies, drivers for each stand have to be made. These drivers will act more like plugins for the software. If the software is being used in E3, then the software should point to the E3 driver package. If the software is being used at B2, then the software should point to the B2 driver package. The driver packages should also be filled with hardware drivers that are universal to the DAS system. For example, since A1, A2, and B2 all use the Preston 8300AU signal conditioners, then the driver for those three stands should be the same and updated collectively.

  20. Hardware problems encountered in solar heating and cooling systems

    NASA Technical Reports Server (NTRS)

    Cash, M.

    1978-01-01

    Numerous problems in the design, production, installation, and operation of solar energy systems are discussed. Described are hardware problems, which range from simple to obscure and complex, and their resolution.

  1. Designing risk communications: completing and correcting mental models of hazardous processes, Part I.

    PubMed

    Atman, C J; Bostrom, A; Fischhoff, B; Morgan, M G

    1994-10-01

    Many risk communications are intended to help the lay public make complex decisions about risk. To guide risk communicators with this objective, a mental models approach to the design and characterization of risk communications is proposed. Building on text comprehension and mental models research, this approach offers an integrated set of methods to help the risk communication designer choose and analyze risk communication content, structure, and organization. An applied example shows that two radon brochures designed with this approach present roughly the same expert facts as a radon brochure widely distributed by the U.S. EPA but meet higher standards on other content, structure, and organization criteria. PMID:7800862

  2. Improved design of subcritical and supercritical cascades using complex characteristics and boundary layer correction

    NASA Technical Reports Server (NTRS)

    Sanz, J. M.

    1983-01-01

    The method of complex characteristics and hodograph transformation for the design of shockless airfoils was extended to design supercritical cascades with high solidities and large inlet angles. This capability was achieved by introducing a conformal mapping of the hodograph domain onto an ellipse and expanding the solution in terms of Tchebycheff polynomials. A computer code was developd based on this idea. A number of airfoils designed with the code are presented. Various supercritical and subcritical compressor, turbine and propeller sections are shown. The lag-entrainment method for the calculation of a turbulent boundary layer was incorporated to the inviscid design code. The results of this calculation are shown for the airfoils described. The elliptic conformal transformation developed to map the hodograph domain onto an ellipse can be used to generate a conformal grid in the physical domain of a cascade of airfoils with open trailing edges with a single transformation. A grid generated with this transformation is shown for the Korn airfoil.

  3. Design of an input filter for power factor correction (PFC) AC to DC converters employing an active ripple cancellation

    SciTech Connect

    Lee, D.Y.; Cho, B.H.

    1996-12-31

    An active input filter for power factor correction (PFC) circuit employing ripple current cancellation is proposed to reduce the filter`s size and cost.Switching ripple current can be filtered by an active circuit from the line current. A single stage passive filter with the active filter compensation circuit, a high filter can be synthesized to meet the electromagnetic interference (EMI) and power factor requirements. Analysis of the active filter and design procedure are detailed. Simulation result is presented to verify the high order filter characteristics of proposed scheme.

  4. Stanford Hardware Development Program

    NASA Technical Reports Server (NTRS)

    Peterson, A.; Linscott, I.; Burr, J.

    1986-01-01

    Architectures for high performance, digital signal processing, particularly for high resolution, wide band spectrum analysis were developed. These developments are intended to provide instrumentation for NASA's Search for Extraterrestrial Intelligence (SETI) program. The real time signal processing is both formal and experimental. The efficient organization and optimal scheduling of signal processing algorithms were investigated. The work is complemented by efforts in processor architecture design and implementation. A high resolution, multichannel spectrometer that incorporates special purpose microcoded signal processors is being tested. A general purpose signal processor for the data from the multichannel spectrometer was designed to function as the processing element in a highly concurrent machine. The processor performance required for the spectrometer is in the range of 1000 to 10,000 million instructions per second (MIPS). Multiple node processor configurations, where each node performs at 100 MIPS, are sought. The nodes are microprogrammable and are interconnected through a network with high bandwidth for neighboring nodes, and medium bandwidth for nodes at larger distance. The implementation of both the current mutlichannel spectrometer and the signal processor as Very Large Scale Integration CMOS chip sets was commenced.

  5. FUGM hardware operation manual

    SciTech Connect

    Wenz, T.R.; Menlove, H.O.; Halbig, J.K.

    1997-05-01

    This manual describes the detector design features, performance, and operating characteristics of the Fugen reactor gate monitor for monitoring fresh and spent fuel transfers between the core and storage ponds. This system consists of two monitors located at each end of the transfer chute. The larger monitor contains two {sup 3}He tubes, two fission chambers, and two ion chambers. The smaller monitor, used for direction of motion redundancy, contains two ion chambers. All detectors provide information for identifying the type, fresh or spent UOX or MOX fuel, and direction of the fuel transfer. The gamma-ray and neutron detector (GRAND-3) electronics package supplies power to the radiation sensors and collects the radiation data for storage on a laptop computer. The system is designed to operate unattended with data collection by the inspectors occurring on 90-day time intervals. This manual also includes radiation data for the six types of fuel transfers and equipment transfers along with the direction of motion information collected during the installation at the Fugen reactor.

  6. The design of a parallax-correcting anthropometer for replication in nonspecialized machine shops.

    PubMed

    Ross, W D

    1985-01-01

    A fixed-rod, slider with a window, a double-scribed line for viewing a measuring tape affixed to the rod, and a sturdy footpiece are design features of an anthropometer for measuring projected lengths. The new instrument is designed to replace contemporary models which may be inaccessible to investigators with limited budgets or currency restrictions. None of the design features are beyond the ingenuity of local machinists to modify, find alternate materials, and use different machine procedures. The same principles of construction can be applied in making sliding calipers with straight and recurved branches. While there is some loss in portability of the fixed-length anthropometer, the improved stability and superior visual scale more than compensate for the disadvantages and make the new anthropometer a candidate for the instrument of choice in obtaining projected length measurements. PMID:3976873

  7. Hardware-Efficient Monitoring of I/O Signals

    NASA Technical Reports Server (NTRS)

    Driscoll, Kevin R.; Hall, Brendan; Paulitsch, Michael

    2009-01-01

    In this invention, command and monitor functionality is moved between the two independent pieces of hardware, in which one had been dedicated to command and the other had been dedicated to monitor, such that some command and some monitor functionality appears in each. The only constraint is that the monitor for signal cannot be in the same hardware as the command I/O it is monitoring. The splitting of the command outputs between independent pieces of hardware may require some communication between them, i.e. an intra-switch trunk line. This innovation reduces the amount of wasted hardware and allows the two independent pieces of hardware to be designed identically in order to save development costs.

  8. VME rollback hardware for time warp multiprocessor systems

    NASA Technical Reports Server (NTRS)

    Robb, Michael J.; Buzzell, Calvin A.

    1992-01-01

    The purpose of the research effort is to develop and demonstrate innovative hardware to implement specific rollback and timing functions required for efficient queue management and precision timekeeping in multiprocessor discrete event simulations. The previously completed phase 1 effort demonstrated the technical feasibility of building hardware modules which eliminate the state saving overhead of the Time Warp paradigm used in distributed simulations on multiprocessor systems. The current phase 2 effort will build multiple pre-production rollback hardware modules integrated with a network of Sun workstations, and the integrated system will be tested by executing a Time Warp simulation. The rollback hardware will be designed to interface with the greatest number of multiprocessor systems possible. The authors believe that the rollback hardware will provide for significant speedup of large scale discrete event simulation problems and allow multiprocessors using Time Warp to dramatically increase performance.

  9. 77 FR 16661 - Tuberculosis in Cattle and Bison; State and Zone Designations; NM; Correction

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-03-22

    ... (74 FR 12055-12058, Docket No. APHIS-2008- 0124), we amended the bovine tuberculosis regulations by... (74 FR 12055-12058, Docket No. APHIS-2008-0124). DATES: Effective Date: March 22, 2012. FOR FURTHER... Inspection Service 9 CFR Part 77 Tuberculosis in Cattle and Bison; State and Zone Designations;...

  10. Reconfigurable Hardware Adapts to Changing Mission Demands

    NASA Technical Reports Server (NTRS)

    2003-01-01

    A new class of computing architectures and processing systems, which use reconfigurable hardware, is creating a revolutionary approach to implementing future spacecraft systems. With the increasing complexity of electronic components, engineers must design next-generation spacecraft systems with new technologies in both hardware and software. Derivation Systems, Inc., of Carlsbad, California, has been working through NASA s Small Business Innovation Research (SBIR) program to develop key technologies in reconfigurable computing and Intellectual Property (IP) soft cores. Founded in 1993, Derivation Systems has received several SBIR contracts from NASA s Langley Research Center and the U.S. Department of Defense Air Force Research Laboratories in support of its mission to develop hardware and software for high-assurance systems. Through these contracts, Derivation Systems began developing leading-edge technology in formal verification, embedded Java, and reconfigurable computing for its PF3100, Derivational Reasoning System (DRS ), FormalCORE IP, FormalCORE PCI/32, FormalCORE DES, and LavaCORE Configurable Java Processor, which are designed for greater flexibility and security on all space missions.

  11. HARDWARE AND SOFTWARE STATUS OF QCDOC.

    SciTech Connect

    BOYLE,P.A.; CHEN,D.; CHRIST,N.H.; PETROV.K.; ET AL.

    2003-07-15

    QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation.

  12. Modulator design for x-ray scatter correction using primary modulation: Material selection

    SciTech Connect

    Gao Hewei; Zhu Lei; Fahrig, Rebecca

    2010-08-15

    Purpose: An optimal material selection for primary modulator is proposed in order to minimize beam hardening of the modulator in x-ray cone-beam computed tomography (CBCT). Recently, a measurement-based scatter correction method using primary modulation has been developed and experimentally verified. In the practical implementation, beam hardening of the modulator blocker is a limiting factor because it causes inconsistency in the primary signal and therefore degrades the accuracy of scatter correction. Methods: This inconsistency can be purposely assigned to the effective transmission factor of the modulator whose variation as a function of object filtration represents the magnitude of beam hardening of the modulator. In this work, the authors show that the variation reaches a minimum when the K-edge of the modulator material is near the mean energy of the system spectrum. Accordingly, an optimal material selection can be carried out in three steps. First, estimate and evaluate the polychromatic spectrum for a given x-ray system including both source and detector; second, calculate the mean energy of the spectrum and decide the candidate materials whose K-edge energies are near the mean energy; third, select the optimal material from the candidates after considering both the magnitude of beam hardening and the physical and chemical properties. Results: A tabletop x-ray CBCT system operated at 120 kVp is used to validate the material selection method in both simulations and experiments, from which the optimal material for this x-ray system is then chosen. With the transmission factor initially being 0.905 and 0.818, simulations show that erbium provides the least amount of variation as a function of object filtrations (maximum variations are 2.2% and 4.3%, respectively, only one-third of that for copper). With different combinations of aluminum and copper filtrations (simulating a range of object thicknesses), measured overall variations are 2.5%, 1.0%, and 8

  13. Design and evaluation of an actuated knee implant for postoperative ligament imbalance correction.

    PubMed

    Collo, A; Almouahed, S; Poignet, P; Hamitouche, C; Stindel, E

    2016-04-01

    In Total Knee Arthroplasty (TKA), the collateral ligament tensioning stage cannot be standardised for all patients and relies heavily on the surgeon's experience and perception. Intraoperative inaccuracies are practically unavoidable and may give rise to severe postoperative complications, leading to the need for revision surgery already a few years after primary TKA. This work proposes a novel instrumented tibial component able to detect collateral ligament laxity conditions right after primary TKA and, if needed, to compensate for them in the postoperative period. A miniaturised actuation system, designed to be embedded in the tibial baseplate, was initially evaluated by means of 3D simulations and then fabricated as a full-scale prototype. Stability and force sensors tests carried out on a knee simulator allowed to assess the effectiveness of the proposed design under normal working conditions and provided valuable insights for future work and improvements. PMID:26832392

  14. Hardware cleanliness methodology and certification

    NASA Technical Reports Server (NTRS)

    Harvey, Gale A.; Lash, Thomas J.; Rawls, J. Richard

    1995-01-01

    Inadequacy of mass loss cleanliness criteria for selection of materials for contamination sensitive uses, and processing of flight hardware for contamination sensitive instruments is discussed. Materials selection for flight hardware is usually based on mass loss (ASTM E-595). However, flight hardware cleanliness (MIL 1246A) is a surface cleanliness assessment. It is possible for materials (e.g. Sil-Pad 2000) to pass ASTM E-595 and fail MIL 1246A class A by orders of magnitude. Conversely, it is possible for small amounts of nonconforming material (Huma-Seal conformal coating) to not present significant cleanliness problems to an optical flight instrument. Effective cleaning (precleaning, precision cleaning, and ultra cleaning) and cleanliness verification are essential for contamination sensitive flight instruments. Polish cleaning of hardware, e.g. vacuum baking for vacuum applications, and storage of clean hardware, e.g. laser optics, is discussed. Silicone materials present special concerns for use in space because of the rapid conversion of the outgassed residues to glass by solar ultraviolet radiation and/or atomic oxygen. Non ozone depleting solvent cleaning and institutional support for cleaning and certification are also discussed.

  15. ROMPS critical design review. Volume 1: Hardware

    NASA Technical Reports Server (NTRS)

    Dobbs, M. E.

    1992-01-01

    Topics concerning the Robot-Operated Material Processing in Space (ROMPS) Program are presented in viewgraph form and include the following: a systems overview; servocontrol and servomechanisms; testbed and simulation results; system V controller; robot module; furnace module; SCL experiment supervisor; SCL script sample processing control; SCL experiment supervisor fault handling; block diagrams; hitchhiker interfaces; battery systems; watchdog timers; mechanical/thermal systems; and fault conditions and recovery.

  16. Lectotype designations and taxonomic corrections on Neotropical Scutelleridae described by G. Breddin (Hemiptera: Heteroptera).

    PubMed

    Rédei, Dávid; Tsai, Jing-Fu; Eger, Joseph E Jr

    2016-01-01

    Lectotypes are designated and documented for the following species and infrasubspecific taxa: Dystus villosus Breddin, 1904; Lobothyreus breviceps Breddin, 1914; Pachycoris torridus (Scopoli, 1772) var. laetissimus Breddin, 1906 (originally proposed as var. laetissima); P. torridus var. moestissimus Breddin, 1906 (originally proposed as var. moestissima); Polytes speculiger Breddin, 1914. The identities of the taxa in concern are clarified. The following new junior subjective synonyms are proposed: Pachycoris torridus (Scopoli, 1772) = P. torridus var. laetissimus Breddin, 1906, syn. nov., = P. torridus var. moestissimus Breddin, 1906, syn. nov. PMID:27395692

  17. A successful 3D seismic survey in the ``no-data zone,`` offshore Mississippi delta: Survey design and refraction static correction processing

    SciTech Connect

    Carvill, C.; Faris, N.; Chambers, R.

    1996-12-31

    This is a success story of survey design and refraction static correction processing of a large 3D seismic survey in the South Pass area of the Mississippi delta. In this transition zone, subaqueous mudflow gullies and lobes of the delta, in various states of consolidation and gas saturation, are strong absorbers of seismic energy. Seismic waves penetrating the mud are severely restricted in bandwidth and variously delayed by changes in mud velocity and thickness. Using a delay-time refraction static correction method, the authors find compensation for the various delays, i.e., static corrections, commonly vary 150 ms over a short distance. Application of the static corrections markedly improves the seismic stack volume. This paper shows that intelligent survey design and delay-time refraction static correction processing economically eliminate the historic no data status of this area.

  18. Monte Carlo-based diode design for correction-less small field dosimetry

    NASA Astrophysics Data System (ADS)

    Charles, P. H.; Crowe, S. B.; Kairn, T.; Knight, R. T.; Hill, B.; Kenny, J.; Langton, C. M.; Trapp, J. V.

    2013-07-01

    Due to their small collecting volume, diodes are commonly used in small field dosimetry. However, the relative sensitivity of a diode increases with decreasing small field size. Conversely, small air gaps have been shown to cause a significant decrease in the sensitivity of a detector as the field size is decreased. Therefore, this study uses Monte Carlo simulations to look at introducing air upstream to diodes such that they measure with a constant sensitivity across all field sizes in small field dosimetry. Varying thicknesses of air were introduced onto the upstream end of two commercial diodes (PTW 60016 photon diode and PTW 60017 electron diode), as well as a theoretical unenclosed silicon chip using field sizes as small as 5 mm × 5 mm. The metric \\frac{{D_{w,Q} }}{{D_{Det,Q} }} used in this study represents the ratio of the dose to a point of water to the dose to the diode active volume, for a particular field size and location. The optimal thickness of air required to provide a constant sensitivity across all small field sizes was found by plotting \\frac{{D_{w,Q} }}{{D_{Det,Q} }} as a function of introduced air gap size for various field sizes, and finding the intersection point of these plots. That is, the point at which \\frac{{D_{w,Q} }}{{D_{Det,Q} }} was constant for all field sizes was found. The optimal thickness of air was calculated to be 3.3, 1.15 and 0.10 mm for the photon diode, electron diode and unenclosed silicon chip, respectively. The variation in these results was due to the different design of each detector. When calculated with the new diode design incorporating the upstream air gap, k_{Q_{clin} ,Q_{msr} }^{f_{clin} ,f_{msr} } was equal to unity to within statistical uncertainty (0.5%) for all three diodes. Cross-axis profile measurements were also improved with the new detector design. The upstream air gap could be implanted on the commercial diodes via a cap consisting of the air cavity surrounded by water equivalent material. The

  19. Error correction using a bit redundancy

    NASA Astrophysics Data System (ADS)

    Schweikert, Robert; Dolainsky, Frank; Foerster, Hans Peter; Vinck, Adrianus Johannes

    1989-11-01

    Communication satellite systems are featuring increased use of channel coding methods for error correction. This paper describes a procedure which uses only one bit redundancy. Decoding this code is extremely simple and permits a significant reduction in requisite transmission capacity. The code is particularly useful where high transmission speeds are needed. The structure of the code is well suited for realizing decoder installations with an application-specific, integrated circuit. The VLSI design for a CMOS-gate-array for such a realization is discussed. Concatenated with other codes, the present code leads to significant hardware savings; an example concatenation with the Reed-Solomon code is shown.

  20. The JPL telerobot operator control station. Part 1: Hardware

    NASA Technical Reports Server (NTRS)

    Kan, Edwin P.; Tower, John T.; Hunka, George W.; Vansant, Glenn J.

    1989-01-01

    The Operator Control Station of the Jet Propulsion Laboratory (JPL)/NASA Telerobot Demonstrator System provides the man-machine interface between the operator and the system. It provides all the hardware and software for accepting human input for the direct and indirect (supervised) manipulation of the robot arms and tools for task execution. Hardware and software are also provided for the display and feedback of information and control data for the operator's consumption and interaction with the task being executed. The hardware design, system architecture, and its integration and interface with the rest of the Telerobot Demonstrator System are discussed.

  1. Nomenclatural corrections, neotype designation and new subspecies description in the genus Suiriri (Aves: Passeriformes: Tyrannidae).

    PubMed

    Kirwan, Guy M; Steinheimer, Frank D; Raposo, Marcos A; Zimmer, Kevin J

    2014-01-01

    Zimmer et al. (2001) documented two morphological and vocal forms within what was then known as Suiriri suiriri affinis, and described the short-billed form as Suiriri islerorum. However, studies of the Burmeister type material held at the Natural History Collections of the Martin-Luther-University Halle-Wittenberg, Germany, revealed the types of Suiriri s. affinis (Burmeister, 1856) to be the same taxon as Suiriri islerorum, which name therefore becomes a junior synonym. No published name is available for the long-billed form. A new name is therefore introduced by an original description in accordance with the International code on zoological nomenclature. The original type material of S. s. bahiae (Berlepsch, 1893) is confirmed to be lost; a neotype is designated. PMID:24872051

  2. Reconfigurable Hardware for Compressing Hyperspectral Image Data

    NASA Technical Reports Server (NTRS)

    Aranki, Nazeeh; Namkung, Jeffrey; Villapando, Carlos; Kiely, Aaron; Klimesh, Matthew; Xie, Hua

    2010-01-01

    High-speed, low-power, reconfigurable electronic hardware has been developed to implement ICER-3D, an algorithm for compressing hyperspectral-image data. The algorithm and parts thereof have been the topics of several NASA Tech Briefs articles, including Context Modeler for Wavelet Compression of Hyperspectral Images (NPO-43239) and ICER-3D Hyperspectral Image Compression Software (NPO-43238), which appear elsewhere in this issue of NASA Tech Briefs. As described in more detail in those articles, the algorithm includes three main subalgorithms: one for computing wavelet transforms, one for context modeling, and one for entropy encoding. For the purpose of designing the hardware, these subalgorithms are treated as modules to be implemented efficiently in field-programmable gate arrays (FPGAs). The design takes advantage of industry- standard, commercially available FPGAs. The implementation targets the Xilinx Virtex II pro architecture, which has embedded PowerPC processor cores with flexible on-chip bus architecture. It incorporates an efficient parallel and pipelined architecture to compress the three-dimensional image data. The design provides for internal buffering to minimize intensive input/output operations while making efficient use of offchip memory. The design is scalable in that the subalgorithms are implemented as independent hardware modules that can be combined in parallel to increase throughput. The on-chip processor manages the overall operation of the compression system, including execution of the top-level control functions as well as scheduling, initiating, and monitoring processes. The design prototype has been demonstrated to be capable of compressing hyperspectral data at a rate of 4.5 megasamples per second at a conservative clock frequency of 50 MHz, with a potential for substantially greater throughput at a higher clock frequency. The power consumption of the prototype is less than 6.5 W. The reconfigurability (by means of reprogramming) of

  3. Hardware description languages for systolic architectures

    SciTech Connect

    Lewis, P.S.

    1984-10-01

    Systolic principles can be used to construct special purpose computer systems that achieve high throughput by exploiting algorithmic properties. These principles of regularity, localized communications, and parallel/pipelined execution nicely match the capabilities of integrated circuit technology. Hence, systolic arrays are an attractive method for building high-speed special-purpose hardware to rapidly solve sophisticated problems. However, the use of special-purpose hardware limits the applications base, making fixed costs such as those associated with system design much more critical. Although design costs are in part reduced by the very nature of systolic systems, further reduction can result from the use of automated design and descriptive tools. The design process stretches from the conception of the algorithm and its mapping onto an architecture down to the electronic implementation. In general, a good set of design tools allows the designer to describe, test, and trade off only those factors that are important at that particular point in the design process. A principle requirement in automating the design process is a formal notational mechanism that is capable of providing complete and unambiguous descriptions of the concepts being explored. This notational mechanism then provides a common basis for comparisons between alternate methods and an input mechanism to automated design tools. This thesis identifies the notational features that are necessary for the description of highly parallel, regular architectures such as systolic arrays. A set of language criteria is developed. A number of the more popular HDLs are evaluated using these criteria and their shortcomings noted. 65 references.

  4. A Hemispherical Sparse Phased Array Design For Low Frequency Transcranial Focused Ultrasound Applications Without Skull-Specific Phase Aberration Correction

    NASA Astrophysics Data System (ADS)

    Yin, Xiangtao; Hynynen, Kullervo

    2006-05-01

    A sparse large-element hemispherical phased array scheme was investigated for low frequency transcranial focused ultrasound applications without skull-specific phase aberration correction. The simulated transcranial focused beams in brain from the randomly distributed sparse array elements (0.25 MHz, 125 mm radius of curvature, 250 mm diameter, 50% sparsity of 953 square elements of 10 mm spacing) could be steered without skull specific aberration correction at 0.25 MHz. The 28 foci were on average 1.7±1.2 mm shifted from their intended locations. The average -3 dB beam width and length were 3.3±1.2 mm and 6.3±2.2 mm, respectively. The sidelobe levels ranged from 28% to 62% of the peak pressure values. The focal beam was steerable 35 mm laterally away from the transducer center axis and 30 mm axially in the transducer center axis when the sidelobe pressure values were 50% of or less than the peak pressure values. This allows the array to be mechanically aimed to one quarter of the brain and then electronically steered. The sparse array design offers a tradeoff between the best beam steering range and the manageable number of elements for a practical clinical system.

  5. Hardware Selection: A Nontechnical Approach.

    ERIC Educational Resources Information Center

    Kiteka, Sebastian F.

    Presented in nontechnical language, this guide suggests criteria for the selection of three computer hardware essentials--a microcomputer, a monitor, and a printer. Factors to be considered in selecting the microcomputer are identified and discussed, including what the computer is to be used for, dealer support, software availability, modem…

  6. Police Communications: Humans and Hardware.

    ERIC Educational Resources Information Center

    Zannes, Estelle

    This volume presents an overview of police communications and analyzes the relationships between the people and hardware in the police system. Chapters discuss the development and use of such communication devices as the telegraph, telephone, and computers; the role of mass media, feedback, and communicative settings in human communication;…

  7. Microcomputer Hardware. Energy Technology Series.

    ERIC Educational Resources Information Center

    Technical Education Research Centre-Southwest, Waco, TX.

    This course in microcomputer hardware is one of 16 courses in the Energy Technology Series developed for an Energy Conservation-and-Use Technology curriculum. Intended for use in two-year postsecondary technical institutions to prepare technicians for employment, the courses are also useful in industry for updating employees in company-sponsored…

  8. Hardware Evolution of Analog Speed Controllers for a DC Motor

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; Ferguson, Michael I.

    2003-01-01

    Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a Field Programmable Transistor Array (FPTA). The performance of these evolved controllers is compared to that of a conventional proportional-integral (PI) controller.

  9. Development and characteristics of the hardware for Skylab experiment S015

    NASA Technical Reports Server (NTRS)

    Thirolf, R. G.

    1975-01-01

    Details are given regarding the hardware for the Skylab S015 experiment, which was designed to detect the effects of zero gravity on cell growth rates. Experience gained in hardware-related considerations is presented for use of researchers concerned with future research of this type and further study of the S015 results. Brief descriptions are given of the experiment hardware, the hardware configuration for the critical design review, the major configuration changes, the final configuration, and the postflight review and analysis. An appendix describes pertinent documentation, film, and hardware that are available to qualified researchers; sources for additional or special information are given.

  10. Configuration management for hardware-software codesign

    SciTech Connect

    Kobialka, H.U.; Gnedina, A.; Wilberg, J.

    1996-12-31

    Configuration Management (CM) has a long tradition in the area of software development. In other areas CM is still more a promise than a product to be used. During HW/SW codesign a large design space has to be explored in order to find the optimal combination of software and hardware. This is an optimization process where many variants (> 1000) and associated analysis results have to be maintained for later exploration. Each variant consists of hundreds of files. This paper describes the CM requirements we encountered when introducing CM in a HW/SW codesign project. CM support for HW/SW codesign has been implemented in the ADDD development environment.

  11. Workmanship Challenges for NASA Mission Hardware

    NASA Technical Reports Server (NTRS)

    Plante, Jeannette

    2010-01-01

    This slide presentation reviews several challenges in workmanship for NASA mission hardware development. Several standards for NASA workmanship exist, that are required for all programs, projects, contracts and subcontracts. These Standards contain our best known methods for avoiding past assembly problems and defects. These best practices may not be available if suppliers are used who are not compliant with them. Compliance includes having certified operators and inspectors. Some examples of problems that have occured from the lack of requirements flow-down to contractors are reviewed. The presentation contains a detailed example of the challenge in regards to The Packaging "Design" Dilemma.

  12. Hardware Counter Multiplexing V1.2

    Energy Science and Technology Software Center (ESTSC)

    2000-10-13

    The Hardware Counter Multiplexer works with the built-in counter registers on computer processors. These counters record varius low-level events as software runs, but they can cannot record all possible events at the same time. This software helps work around that limitation by counting a series of different events in sequence over a period of time. This in turn allows programmers to measure interesting combinations of events, rather than single events. The software is designed tomore » work with multithreaded or single-threaded programs.« less

  13. Orbiter CIU/IUS communications hardware evaluation

    NASA Technical Reports Server (NTRS)

    Huth, G. K.

    1979-01-01

    The DOD and NASA inertial upper stage communication system design, hardware specifications and interfaces were analyzed to determine their compatibility with the Orbiter payload communications equipment (Payload Interrogator, Payload Signal Processors, Communications Interface Unit, and the Orbiter operational communications equipment (the S-Band and Ku-band systems). Topics covered include (1) IUS/shuttle Orbiter communications interface definition; (2) Orbiter avionics equipment serving the IUS; (3) IUS communication equipment; (4) IUS/shuttle Orbiter RF links; (5) STDN/TDRS S-band related activities; and (6) communication interface unit/Orbiter interface issues. A test requirement plan overview is included.

  14. INTEGRATED MONITORING HARDWARE DEVELOPMENTS AT LOS ALAMOS

    SciTech Connect

    R. PARKER; J. HALBIG; ET AL

    1999-09-01

    The hardware of the integrated monitoring system supports a family of instruments having a common internal architecture and firmware. Instruments can be easily configured from application-specific personality boards combined with common master-processor and high- and low-voltage power supply boards, and basic operating firmware. The instruments are designed to function autonomously to survive power and communication outages and to adapt to changing conditions. The personality boards allow measurement of gross gammas and neutrons, neutron coincidence and multiplicity, and gamma spectra. In addition, the Intelligent Local Node (ILON) provides a moderate-bandwidth network to tie together instruments, sensors, and computers.

  15. Open Hardware for CERN's accelerator control systems

    NASA Astrophysics Data System (ADS)

    van der Bij, E.; Serrano, J.; Wlostowski, T.; Cattin, M.; Gousiou, E.; Alvarez Sanchez, P.; Boccardi, A.; Voumard, N.; Penacoba, G.

    2012-01-01

    The accelerator control systems at CERN will be upgraded and many electronics modules such as analog and digital I/O, level converters and repeaters, serial links and timing modules are being redesigned. The new developments are based on the FPGA Mezzanine Card, PCI Express and VME64x standards while the Wishbone specification is used as a system on a chip bus. To attract partners, the projects are developed in an `Open' fashion. Within this Open Hardware project new ways of working with industry are being evaluated and it has been proven that industry can be involved at all stages, from design to production and support.

  16. CASIS Fact Sheet: Hardware and Facilities

    NASA Technical Reports Server (NTRS)

    Solomon, Michael R.; Romero, Vergel

    2016-01-01

    Vencore is a proven information solutions, engineering, and analytics company that helps our customers solve their most complex challenges. For more than 40 years, we have designed, developed and delivered mission-critical solutions as our customers' trusted partner. The Engineering Services Contract, or ESC, provides engineering and design services to the NASA organizations engaged in development of new technologies at the Kennedy Space Center. Vencore is the ESC prime contractor, with teammates that include Stinger Ghaffarian Technologies, Sierra Lobo, Nelson Engineering, EASi, and Craig Technologies. The Vencore team designs and develops systems and equipment to be used for the processing of space launch vehicles, spacecraft, and payloads. We perform flight systems engineering for spaceflight hardware and software; develop technologies that serve NASA's mission requirements and operations needs for the future. Our Flight Payload Support (FPS) team at Kennedy Space Center (KSC) provides engineering, development, and certification services as well as payload integration and management services to NASA and commercial customers. Our main objective is to assist principal investigators (PIs) integrate their science experiments into payload hardware for research aboard the International Space Station (ISS), commercial spacecraft, suborbital vehicles, parabolic flight aircrafts, and ground-based studies. Vencore's FPS team is AS9100 certified and a recognized implementation partner for the Center for Advancement of Science in Space (CASIS

  17. Hardware Development Process for Human Research Facility Applications

    NASA Technical Reports Server (NTRS)

    Bauer, Liz

    2000-01-01

    The simple goal of the Human Research Facility (HRF) is to conduct human research experiments on the International Space Station (ISS) astronauts during long-duration missions. This is accomplished by providing integration and operation of the necessary hardware and software capabilities. A typical hardware development flow consists of five stages: functional inputs and requirements definition, market research, design life cycle through hardware delivery, crew training, and mission support. The purpose of this presentation is to guide the audience through the early hardware development process: requirement definition through selecting a development path. Specific HRF equipment is used to illustrate the hardware development paths. The source of hardware requirements is the science community and HRF program. The HRF Science Working Group, consisting of SCientists from various medical disciplines, defined a basic set of equipment with functional requirements. This established the performance requirements of the hardware. HRF program requirements focus on making the hardware safe and operational in a space environment. This includes structural, thermal, human factors, and material requirements. Science and HRF program requirements are defined in a hardware requirements document which includes verification methods. Once the hardware is fabricated, requirements are verified by inspection, test, analysis, or demonstration. All data is compiled and reviewed to certify the hardware for flight. Obviously, the basis for all hardware development activities is requirement definition. Full and complete requirement definition is ideal prior to initiating the hardware development. However, this is generally not the case, but the hardware team typically has functional inputs as a guide. The first step is for engineers to conduct market research based on the functional inputs provided by scientists. CommerCially available products are evaluated against the science requirements as

  18. Mapping of topological quantum circuits to physical hardware.

    PubMed

    Paler, Alexandru; Devitt, Simon J; Nemoto, Kae; Polian, Ilia

    2014-01-01

    Topological quantum computation is a promising technique to achieve large-scale, error-corrected computation. Quantum hardware is used to create a large, 3-dimensional lattice of entangled qubits while performing computation requires strategic measurement in accordance with a topological circuit specification. The specification is a geometric structure that defines encoded information and fault-tolerant operations. The compilation of a topological circuit is one important aspect of programming a quantum computer, another is the mapping of the topological circuit into the operations performed by the hardware. Each qubit has to be controlled, and measurement results are needed to propagate encoded quantum information from input to output. In this work, we introduce an algorithm for mapping an topological circuit to the operations needed by the physical hardware. We determine the control commands for each qubit in the computer and the relevant measurements that are needed to track information as it moves through the circuit. PMID:24722360

  19. Mapping of Topological Quantum Circuits to Physical Hardware

    NASA Astrophysics Data System (ADS)

    Paler, Alexandru; Devitt, Simon J.; Nemoto, Kae; Polian, Ilia

    2014-04-01

    Topological quantum computation is a promising technique to achieve large-scale, error-corrected computation. Quantum hardware is used to create a large, 3-dimensional lattice of entangled qubits while performing computation requires strategic measurement in accordance with a topological circuit specification. The specification is a geometric structure that defines encoded information and fault-tolerant operations. The compilation of a topological circuit is one important aspect of programming a quantum computer, another is the mapping of the topological circuit into the operations performed by the hardware. Each qubit has to be controlled, and measurement results are needed to propagate encoded quantum information from input to output. In this work, we introduce an algorithm for mapping an topological circuit to the operations needed by the physical hardware. We determine the control commands for each qubit in the computer and the relevant measurements that are needed to track information as it moves through the circuit.

  20. Open Source Hardware for DIY Environmental Sensing

    NASA Astrophysics Data System (ADS)

    Aufdenkampe, A. K.; Hicks, S. D.; Damiano, S. G.; Montgomery, D. S.

    2014-12-01

    The Arduino open source electronics platform has been very popular within the DIY (Do It Yourself) community for several years, and it is now providing environmental science researchers with an inexpensive alternative to commercial data logging and transmission hardware. Here we present the designs for our latest series of custom Arduino-based dataloggers, which include wireless communication options like self-meshing radio networks and cellular phone modules. The main Arduino board uses a custom interface board to connect to various research-grade sensors to take readings of turbidity, dissolved oxygen, water depth and conductivity, soil moisture, solar radiation, and other parameters. Sensors with SDI-12 communications can be directly interfaced to the logger using our open Arduino-SDI-12 software library (https://github.com/StroudCenter/Arduino-SDI-12). Different deployment options are shown, like rugged enclosures to house the loggers and rigs for mounting the sensors in both fresh water and marine environments. After the data has been collected and transmitted by the logger, the data is received by a mySQL-PHP stack running on a web server that can be accessed from anywhere in the world. Once there, the data can be visualized on web pages or served though REST requests and Water One Flow (WOF) services. Since one of the main benefits of using open source hardware is the easy collaboration between users, we are introducing a new web platform for discussion and sharing of ideas and plans for hardware and software designs used with DIY environmental sensors and data loggers.

  1. Hardware acceleration of image recognition through a visual cortex model

    NASA Astrophysics Data System (ADS)

    Rice, Kenneth L.; Taha, Tarek M.; Vutsinas, Christopher N.

    2008-09-01

    Recent findings in neuroscience have led to the development of several new models describing the processes in the neocortex. These models excel at cognitive applications such as image analysis and movement control. This paper presents a hardware architecture to speed up image content recognition through a recently proposed model of the visual cortex. The system is based on a set of parallel computation nodes implemented in an FPGA. The design was optimized for hardware by reducing the data storage requirements, and removing the need for multiplies and divides. The reconfigurable logic hardware implementation running at 121 MHz provided a speedup of 148 times over a 2 GHz AMD Opteron processor. The results indicate the feasibility of specialized hardware to accelerate larger biological scale implementations of the model.

  2. Human-machine interface hardware: The next decade

    NASA Technical Reports Server (NTRS)

    Marcus, Elizabeth A.

    1991-01-01

    In order to understand where human-machine interface hardware is headed, it is important to understand where we are today, how we got there, and what our goals for the future are. As computers become more capable, faster, and programs become more sophisticated, it becomes apparent that the interface hardware is the key to an exciting future in computing. How can a user interact and control a seemingly limitless array of parameters effectively? Today, the answer is most often a limitless array of controls. The link between these controls and human sensory motor capabilities does not utilize existing human capabilities to their full extent. Interface hardware for teleoperation and virtual environments is now facing a crossroad in design. Therefore, we as developers need to explore how the combination of interface hardware, human capabilities, and user experience can be blended to get the best performance today and in the future.

  3. Hardware Fault Simulator for Microprocessors

    NASA Technical Reports Server (NTRS)

    Hess, L. M.; Timoc, C. C.

    1983-01-01

    Breadboarded circuit is faster and more thorough than software simulator. Elementary fault simulator for AND gate uses three gates and shaft register to simulate stuck-at-one or stuck-at-zero conditions at inputs and output. Experimental results showed hardware fault simulator for microprocessor gave faster results than software simulator, by two orders of magnitude, with one test being applied every 4 microseconds.

  4. Hunting for hardware changes in data centres

    NASA Astrophysics Data System (ADS)

    Coelho dos Santos, M.; Steers, I.; Szebenyi, I.; Xafi, A.; Barring, O.; Bonfillou, E.

    2012-12-01

    With many servers and server parts the environment of warehouse sized data centres is increasingly complex. Server life-cycle management and hardware failures are responsible for frequent changes that need to be managed. To manage these changes better a project codenamed “hardware hound” focusing on hardware failure trending and hardware inventory has been started at CERN. By creating and using a hardware oriented data set - the inventory - with detailed information on servers and their parts as well as tracking changes to this inventory, the project aims at, for example, being able to discover trends in hardware failure rates.

  5. Color science demonstration kit from open source hardware and software

    NASA Astrophysics Data System (ADS)

    Zollers, Michael W.

    2014-09-01

    Color science is perhaps the most universally tangible discipline within the optical sciences for people of all ages. Excepting a small and relatively well-understood minority, we can see that the world around us consists of a multitude of colors; yet, describing the "what", "why", and "how" of these colors is not an easy task, especially without some sort of equally colorful visual aids. While static displays (e.g., poster boards, etc.) serve their purpose, there is a growing trend, aided by the recent permeation of small interactive devices into our society, for interactive and immersive learning. However, for the uninitiated, designing software and hardware for this purpose may not be within the purview of all optical scientists and engineers. Enter open source. Open source "anything" are those tools and designs -- hardware or software -- that are available and free to use, often without any restrictive licensing. Open source software may be familiar to some, but the open source hardware movement is relatively new. These are electronic circuit board designs that are provided for free and can be implemented in physical hardware by anyone. This movement has led to the availability of some relatively inexpensive, but quite capable, computing power for the creation of small devices. This paper will showcase the design and implementation of the software and hardware that was used to create an interactive demonstration kit for color. Its purpose is to introduce and demonstrate the concepts of color spectra, additive color, color rendering, and metamers.

  6. Extensible Hardware Architecture for Mobile Robots

    NASA Technical Reports Server (NTRS)

    Park, Eric; Kobayashi, Linda; Lee, Susan Y.

    2005-01-01

    The Intelligent Robotics Group at NASA Ames Research Center has developed a new mobile robot hardware architecture designed for extensibility and reconfigurability. Currently implemented on the k9 rover. and won to be integrated onto the K10 series of human-robot collaboration research robots, this architecture allows for rapid changes in instrumentation configuration and provides a high degree of modularity through a synergistic mix of off-the-shelf and custom designed components, allowing eased transplantation into a wide vane6 of mobile robot platforms. A component level overview of this architecture is presented along with a description of the changes required for implementation on K10 , followed by plans for future work.

  7. Efficient hardware-software co-implementation of a digital dental x-ray system

    NASA Astrophysics Data System (ADS)

    Kim, Jong D.; Kim, Seo-Gyoo; Kim, Jongwon

    2001-05-01

    In this paper the design considerations for a digital dental x-ray system is discussed where a commercial CCD sensor is adopted. Especially the system should be able to work with several x-ray machines even with them for the classical film. The hardware-software co-design methodology is employed to optimize the system. The full digital implementation is assumed for the reliability of the system. The considered functions cover the pre-processing such as the exposure detection, clamping and the dark level correction and the post-processing such as gray level compensation. It is analyzed with some other constraints in order to make the final partition. The entire system based on the partition will be described.

  8. Correction of a skeletal Class II malocclusion with severe crowding by a specially designed rapid maxillary expander.

    PubMed

    Wang, Honghong; Feng, Jing; Lu, Peijun; Shen, Gang

    2015-02-01

    To correct an Angle Class II malocclusion or to create spaces in the maxillary arch by nonextraction treatment, distal movement of the maxillary molars is required. Various modalities for distalizing the buccal segment have been reported. Conventional extraoral appliances can be used to obtain maximum anchorage. However, many patients reject headgear wear because of social and esthetic concerns, and the success of this treatment depends on patient compliance. Intraoral appliances, such as repelling magnets, nickel-titanium coils, pendulum appliance, Jones jig appliance, distal jet appliance, and modified Nance appliance, have been introduced to distalize the molars with little or no patient cooperation. However, intraoral appliances can result in anchorage loss of the anterior teeth and distal tipping of the maxillary molars. In this case report, we introduce a diversified rapid maxillary expansion appliance that was custom designed and fabricated for the treatment of a growing girl with a skeletal Class II malocclusion and severe crowding from a totally lingually positioned lateral incisor. The appliance concomitantly expanded the maxilla transversely and retracted the buccal segment sagittally, distalizing the maxillary molars to reach a Class I relationship and creating the spaces to displace the malpositioned lateral incisor. The uniqueness of this special diversified rapid maxillary expansion appliance was highlighted by a series of reconstructions and modifications at different stages of the treatment to reinforce the anchorage. PMID:25636559

  9. Hardware and software reliability estimation using simulations

    NASA Technical Reports Server (NTRS)

    Swern, Frederic L.

    1994-01-01

    The simulation technique is used to explore the validation of both hardware and software. It was concluded that simulation is a viable means for validating both hardware and software and associating a reliability number with each. This is useful in determining the overall probability of system failure of an embedded processor unit, and improving both the code and the hardware where necessary to meet reliability requirements. The methodologies were proved using some simple programs, and simple hardware models.

  10. On the use of inexact, pruned hardware in atmospheric modelling

    PubMed Central

    Düben, Peter D.; Joven, Jaume; Lingamneni, Avinash; McNamara, Hugh; De Micheli, Giovanni; Palem, Krishna V.; Palmer, T. N.

    2014-01-01

    Inexact hardware design, which advocates trading the accuracy of computations in exchange for significant savings in area, power and/or performance of computing hardware, has received increasing prominence in several error-tolerant application domains, particularly those involving perceptual or statistical end-users. In this paper, we evaluate inexact hardware for its applicability in weather and climate modelling. We expand previous studies on inexact techniques, in particular probabilistic pruning, to floating point arithmetic units and derive several simulated set-ups of pruned hardware with reasonable levels of error for applications in atmospheric modelling. The set-up is tested on the Lorenz ‘96 model, a toy model for atmospheric dynamics, using software emulation for the proposed hardware. The results show that large parts of the computation tolerate the use of pruned hardware blocks without major changes in the quality of short- and long-time diagnostics, such as forecast errors and probability density functions. This could open the door to significant savings in computational cost and to higher resolution simulations with weather and climate models. PMID:24842031

  11. Evaluation of next generation hardware for lithography processing

    NASA Astrophysics Data System (ADS)

    Shimoaoki, T.; Enomoto, M.; Nafus, K.; Marumoto, H.; Kosugi, H.; Mallmann, J.; Maas, R.; Verspaget, C.; van der Heijden, E.; Wang, S.

    2010-04-01

    This work is the summary of improvements in processing capability implemented and tested on the LITHIUS ProTM -i / TWINSCANTM XT:1950Hi litho cluster installed at ASML's development clean room at Veldhoven, the Netherlands. Process performance with regards to CD uniformity (CDU) and defectivity are investigated to confirm adherence to ITRS roadmaps specifications. Specifically, imaging capabilities are tested for 40nm line 80nm pitch with the new bake plate hardware for below hp 3Xnm generation. For defectivity, the combination of Coater/Developer defect reduction hardware with the novel immersion hood design will be tested. For CDU improvements, the enhanced Post Exposure Bake (PEB) plate hardware was verified versus performance of the previous technology plate. Additionally, after the PEB improvement, a remaining across wafer signature was reduced with an optimized develop process. The total CDU budget was analyzed and compared to previous results. Finally the optimized process was applied to a non top coat resist process. For defectivity improvements, the effectiveness of ASML's new immersion hood and TEL's defect reduction hardware were evaluated. The new immersion hood performance was optimal on very hydrophobic materials, which requires optimization of the track hardware and process. The high contact angle materials could be shown to be successfully processed by using TEL's Advanced Defect Reduction (ADR) for residues related to the high contact angle and optimized bevel cut strategy with new bevel rinse hardware. Finally all the optimized processes were combined to obtain defect counts on a highly hydrophobic resist well within manufacturing specifications.

  12. Apollo Guidance, Navigation, and Control (GNC) Hardware Overview

    NASA Technical Reports Server (NTRS)

    Interbartolo, Michael

    2009-01-01

    This viewgraph presentation reviews basic guidance, navigation and control (GNC) concepts, examines the Command and Service Module (CSM) and Lunar Module (LM) GNC organization and discusses the primary GNC and the CSM Stabilization and Control System (SCS), as well as other CSM-specific hardware. The LM Abort Guidance System (AGS), Control Electronics System (CES) and other LM-specific hardware are also addressed. Three subsystems exist on each vehicle: the computer subsystem (CSS), the inertial subsystem (ISS) and the optical subsystem (OSS). The CSS and ISS are almost identical between CSM and LM and each is designed to operate independently. CSM SCS hardware are highlighted, including translation control, rotation controls, gyro assemblies, a gyro display coupler and flight director attitude indicators. The LM AGS hardware are also highlighted and include the abort electronics assembly and the abort sensor assembly; while the LM CES hardware includes the attitude controller assembly, thrust/translation controller assemblies and the ascent engine arming assemble. Other common hardware including the Orbital Rate Display - Earth and Lunar (ORDEAL) and the Crewman Optical Alignment Sight (COAS), a docking aid, are also highlighted.

  13. Stretched Lens Array (SLA) Photovoltaic Concentrator Hardware Development and Testing

    NASA Technical Reports Server (NTRS)

    Piszczor, Michael; O'Neill, Mark J.; Eskenazi, Michael

    2003-01-01

    Over the past two years, the Stretched Lens Array (SLA) photovoltaic concentrator has evolved, under a NASA contract, from a concept with small component demonstrators to operational array hardware that is ready for space validation testing. A fully-functional four panel SLA solar array has been designed, built and tested. This paper will summarize the focus of the hardware development effort, discuss the results of recent testing conducted under this program and present the expected performance of a full size 7kW array designed to meet the requirements of future space missions.

  14. Carbonate fuel cell endurance: Hardware corrosion and electrolyte management status

    SciTech Connect

    Yuh, C.; Johnsen, R.; Farooque, M.; Maru, H.

    1993-05-01

    Endurance tests of carbonate fuel cell stacks (up to 10,000 hours) have shown that hardware corrosion and electrolyte losses can be reasonably controlled by proper material selection and cell design. Corrosion of stainless steel current collector hardware, nickel clad bipolar plate and aluminized wet seal show rates within acceptable limits. Electrolyte loss rate to current collector surface has been minimized by reducing exposed current collector surface area. Electrolyte evaporation loss appears tolerable. Electrolyte redistribution has been restrained by proper design of manifold seals.

  15. Carbonate fuel cell endurance: Hardware corrosion and electrolyte management status

    SciTech Connect

    Yuh, C.; Johnsen, R.; Farooque, M.; Maru, H.

    1993-01-01

    Endurance tests of carbonate fuel cell stacks (up to 10,000 hours) have shown that hardware corrosion and electrolyte losses can be reasonably controlled by proper material selection and cell design. Corrosion of stainless steel current collector hardware, nickel clad bipolar plate and aluminized wet seal show rates within acceptable limits. Electrolyte loss rate to current collector surface has been minimized by reducing exposed current collector surface area. Electrolyte evaporation loss appears tolerable. Electrolyte redistribution has been restrained by proper design of manifold seals.

  16. GENI: Grid Hardware and Software

    SciTech Connect

    2012-01-09

    GENI Project: The 15 projects in ARPA-E’s GENI program, short for “Green Electricity Network Integration,” aim to modernize the way electricity is transmitted in the U.S. through advances in hardware and software for the electric grid. These advances will improve the efficiency and reliability of electricity transmission, increase the amount of renewable energy the grid can utilize, and provide energy suppliers and consumers with greater control over their power flows in order to better manage peak power demand and cost.

  17. Automated Hardware-Identification System

    NASA Technical Reports Server (NTRS)

    Schramm, Harry F., Jr.; Roxby, Donald L.

    1995-01-01

    "Compressed symbology" emerging technology involving one- and two-dimensional arrays of surface depressions to form optically readable dots. Patterns more durable and denser than common bar codes. Convey identification data in binary form and read by optoelectric sensors. Computers and compressed-symbology engraving machines they control constitute subsystems of "paperless" hardware-tracking and -identification systems coordinating flows of both identifying information and identified parts themselves, along with ancillary information like work orders. Modifications of software expected to accelerate marking operations, eliminate need for trial or practice marking, and reduce incidence of errors.

  18. 16 CFR 1509.7 - Hardware.

    Code of Federal Regulations, 2011 CFR

    2011-01-01

    ... 16 Commercial Practices 2 2011-01-01 2011-01-01 false Hardware. 1509.7 Section 1509.7 Commercial Practices CONSUMER PRODUCT SAFETY COMMISSION FEDERAL HAZARDOUS SUBSTANCES ACT REGULATIONS REQUIREMENTS FOR NON-FULL-SIZE BABY CRIBS § 1509.7 Hardware. (a) The hardware in a non-full-size baby crib shall...

  19. Evaluating Interactive Video: Software and Hardware.

    ERIC Educational Resources Information Center

    Sorge, Dennis H.; And Others

    1993-01-01

    Discusses selection criteria for evaluating software and hardware used in interactive video based on experiences from the Purdue Academic Learning Opportunity System Project at Purdue University. Highlights include checklists for evaluating software and selecting hardware, including peripheral equipment; videodisc players; hardware compatibility;…

  20. Design study of Software-Implemented Fault-Tolerance (SIFT) computer

    NASA Technical Reports Server (NTRS)

    Wensley, J. H.; Goldberg, J.; Green, M. W.; Kutz, W. H.; Levitt, K. N.; Mills, M. E.; Shostak, R. E.; Whiting-Okeefe, P. M.; Zeidler, H. M.

    1982-01-01

    Software-implemented fault tolerant (SIFT) computer design for commercial aviation is reported. A SIFT design concept is addressed. Alternate strategies for physical implementation are considered. Hardware and software design correctness is addressed. System modeling and effectiveness evaluation are considered from a fault-tolerant point of view.

  1. Cooling tower hardware corrosion studies

    SciTech Connect

    Blue, S.C.

    1983-01-31

    The data presented in this report are interim results of a continuing investigation into the corrosion resistance of metals in the environment of a large cooling tower. Some of the significant observations are as follows: the corrosion of susceptible metals occurs most rapidly in the warm fog conditions between the deck and mist filters; the application of stainless steel must be made on the basis of alloy chemistry and processing history. Some corrosion resistant alloys may develop cracking problems after improper heat treating or welding; combinations of aluminum bronze, stainless steel, and silicon bronze hardware were not susceptible to galvanic corrosion; the service life of structural steel is extended by coal tar epoxy coatings; aluminum coatings appear to protect structural steel on the tower deck and below the distribution nozzles. The corrosion of cooling tower hardware can be easily controlled through the use of 316 stainless steel and silicon bronze. The use of other materials which exhibit general resistance should be specified only after they have been tested in the form of structural assemblies such as weldments and bolted joints in each of the different tower zones.

  2. The Initial Blood Storage Experiment - The spaceflight hardware program

    NASA Technical Reports Server (NTRS)

    Almgren, David W.; Csigi, Katinka I.; Glaser, Peter E.; Lucas, Robert M.; Spencer, Richard H.

    1989-01-01

    The Initial Blood Storage Experiment (IBSE) was conceived to investigate the effects of microgravity on the formed elements of human blood. The experiment flew on the January 1986, 61-C mission of the Space Shuttle Columbia. The experiment hardware was designed to provide a closely controlled temperature and air flow environment for all blood samples. During the mission, two IBSE modules were on board the orbiter and an identical set of hardware and blood samples were maintained on earth as a control. This paper describes the development and performance of the IBSE hardware which was converted from a conceptual design to an on-orbit, man-rated, mid-deck locker experiment in 17 months.

  3. Design for the correction system of the real time nonuniformity of large area-array CCD image

    NASA Astrophysics Data System (ADS)

    Wang, Yan; Li, Chunmei; Lei, Ning

    2012-10-01

    With the robust thriving of aviation cameras and remote sensing technology, the linear-array CCD (charge-coupled device) and area CCD have developed toward large area CCD, which has a broad coverage and avoids the difficulty in jointing small area CCDs in addition to improving time resolution. However, due to the high amount of pixels and channels of large area CCD, photo-response non-uniformity (PRNU) is severe. In this paper, a real time non-uniformity correction system is introduced for a sort of large area full frame transfer CCD. First, the correction algorithm is elaborated according to CCD's working principle. Secondly, due to the high number of pixels and correction coefficient, ordinary chip memory cannot meet the requirement. The combination of external flash memory and DDR described in the paper satisfies large capacity memory and rapid real time correction. The methods and measurement steps for obtaining correction factors are provided simultaneously. At the end, an imaging test is made. The non-uniformity of the image is reduced to 0.38 % from the pre-correction 2.96 %, achieving an obvious reduction of non-uniformity. The result shows that the real time non-uniformity correction system can meet the demands of large area-array CCD.

  4. Electronic processing and control system with programmable hardware

    NASA Technical Reports Server (NTRS)

    Alkalaj, Leon (Inventor); Fang, Wai-Chi (Inventor); Newell, Michael A. (Inventor)

    1998-01-01

    A computer system with reprogrammable hardware allowing dynamically allocating hardware resources for different functions and adaptability for different processors and different operating platforms. All hardware resources are physically partitioned into system-user hardware and application-user hardware depending on the specific operation requirements. A reprogrammable interface preferably interconnects the system-user hardware and application-user hardware.

  5. Product Assurance for Spaceflight Hardware

    NASA Technical Reports Server (NTRS)

    Monroe, Mike

    1995-01-01

    This report contains information about the tasks I have completed and the valuable experience I have gained at NASA. The report is divided into two different sections followed by a program summary sheet. The first section describes the two reports I have completed for the Office of Mission Assurance (OMA). I describe the approach and the resources and facilities used to complete each report. The second section describes my experience working in the Receipt Inspection/Quality Assurance Lab (RI/QA). The first report described is a Product Assurance Plan for the Gas Permeable Polymer Materials (GPPM) mission. The purpose of the Product Assurance Plan is to define the various requirements which are to be met through completion of the GPPM mission. The GPPM experiment is a space payload which will be flown in the shuttle's SPACEHAB module. The experiment will use microgravity to enable production of complex polymeric gas permeable materials. The second report described in the first section is a Fracture Analysis for the Mir Environmental Effects Payload (MEEP). The Fracture Analysis report is a summary of the fracture control classifications for all structural elements of the MEEP. The MEEP hardware consists of four experiment carriers, each of which contains an experiment container holding a passive experiment. The MEEP hardware will be attached to the cargo bay of the space shuttle. It will be transferred by Extravehicular Activity and mounted on the Mir space station. The second section of this report describes my experiences in the RVQA lab. I listed the different equipment I used at the lab and their functions. I described the extensive inspection process that must be completed for spaceflight hardware. Included, at the end of this section, are pictures of most of the equipment used in the lab. There is a summary sheet located at the end of this report. It briefly describes the valuable experience I have gained at NASA this summer and what I will be able to take

  6. An IOMMU for hardware-assisted full virtualization of heterogeneous multi-core SoCs

    NASA Astrophysics Data System (ADS)

    Kornaros, G.; Harteros, K.; Astrinaki, M.; Christoforakis, I.; Coppola, M.; Grammatikakis, M. D.

    2013-05-01

    Hardware virtualization is a major challenge in embedded virtualization. The key to improving resource utilization in a virtualized system is to allow maximum possible resource access operations to perform natively with minimal intervention by the virtual machine monitor, while at the same time ensuring protected operation among different virtual machines' address space. An innovative I/O Memory Management Unit component (IOMMU) is architected to enable mapping of virtual addresses from multiple devices to the correct VM's physical memory locations, offering enhanced protection, scatter-gather functions on distributed memory organizations, high performance supported by a configurable TLB and an integrated lightweight hardware monitoring unit to facilitate dynamic system optimizations. This new IOMMU is designed in a modular way supporting address translation along with protection and security extensions. The principal objective is to ensure device isolation by safely mapping a device to a particular guest without risking the integrity of other guests. Additionally, the IOMMU is designed to provide an increased level of security in scenarios without virtualization; with the aid of the IOMMU, the operating system is able to protect itself from malicious device drivers by limiting a device's memory accesses and managing the permissions of peripheral devices.

  7. Hardware-efficient low-power image processing system for wireless capsule endoscopy.

    PubMed

    Turcza, Pawel; Duplaga, Mariusz

    2013-11-01

    This paper presents the design of a hardware-efficient, low-power image processing system for next-generation wireless endoscopy. The presented system is composed of a custom CMOS image sensor, a dedicated image compressor, a forward error correction (FEC) encoder protecting radio transmitted data against random and burst errors, a radio data transmitter, and a controller supervising all operations of the system. The most significant part of the system is the image compressor. It is based on an integer version of a discrete cosine transform and a novel, low complexity yet efficient, entropy encoder making use of an adaptive Golomb-Rice algorithm instead of Huffman tables. The novel hardware-efficient architecture designed for the presented system enables on-the-fly compression of the acquired image. Instant compression, together with elimination of the necessity of retransmitting erroneously received data by their prior FEC encoding, significantly reduces the size of the required memory in comparison to previous systems. The presented system was prototyped in a single, low-power, 65-nm field programmable gate arrays (FPGA) chip. Its power consumption is low and comparable to other application-specific-integrated-circuits-based systems, despite FPGA-based implementation. PMID:24240723

  8. Comparing codes for error corrected quantum annealing

    NASA Astrophysics Data System (ADS)

    Mishra, Anurag; Albash, Tameem; Paz, Gerardo; Lidar, Daniel

    2015-03-01

    Previous work on the D-Wave Two (DW2) device has demonstrated the effectiveness of using error correction and suppression for quantum annealers. As the size of a quantum annealer increases, error correction becomes crucial for improved performance. We introduce a new type of code for error correction tailored to the hardware graph of the DW2, discuss the result of benchmarking this code on qubit chains, discuss various new decoding methods, and compare the performance to previous quantum annealing correction schemes.

  9. Computer and information technology: hardware.

    PubMed

    O'Brien, D

    1998-02-01

    Computers open the door to an ever-expanding arena of knowledge and technology. Most nurses practicing in perianesthesia setting were educated before the computer era, and many fear computers and the associated technology. Frequently, the greatest difficulty is finding the resources and knowing what questions to ask. The following is the first in a series of articles on computers and information technology. This article discusses computer hardware to get the novice started or the experienced user upgraded to access new technologies and the Internet. Future articles will discuss start up and usual software applications, getting up to speed on the information superhighway, and other technologies that will broaden our knowledge and expand our personal and professional world. PMID:9543967

  10. Review of Maxillofacial Hardware Complications and Indications for Salvage.

    PubMed

    Hernandez Rosa, Jonatan; Villanueva, Nathaniel L; Sanati-Mehrizy, Paymon; Factor, Stephanie H; Taub, Peter J

    2016-06-01

    From 2002 to 2006, more than 117,000 facial fractures were recorded in the U.S. National Trauma Database. These fractures are commonly treated with open reduction and internal fixation. While in place, the hardware facilitates successful bony union. However, when postoperative complications occur, the plates may require removal before bony union. Indications for salvage versus removal of the maxillofacial hardware are not well defined. A literature review was performed to identify instances when hardware may be salvaged. Articles considered for inclusion were found in the PubMed and Web of Science databases in August 2014 with the keywords maxillofacial trauma AND hardware complications OR indications for hardware removal. Included studies looked at human patients with only facial trauma and miniplate fixation, and presented data on complications and/or hardware removal. Fifteen articles were included. None were clinical trials. Complication data were presented by patient, fractures, and/or plate without consistency. The data described 1,075 fractures, 2,961 patients, and 2,592 plates, nonexclusive. Complication rates varied from 6 to 8% by fracture and 6 to 13% by patient. When their data were combined, 50% of complications were treated with plate removal; this was consistent across the mandible, midface, and upper face. All complications caused by loosening, nonunion, broken hardware, and severe/prolonged pain were treated with removal. Some complications caused by exposures, deformities, and infections were treated with salvage. Exposed plates were treated with flaps, plates with deformities were treated with secondary procedures including hardware revision, and hardware infections were treated with antibiotics alone or in conjunction with soft-tissue debridement and/or tooth extraction. Well-designed clinical trials evaluating hardware removal versus salvage are lacking. Some postoperative complications caused by exposure, deformity, and/or infection may be

  11. Fastener Retention Requirements and Practices in Spaceflight Hardware

    NASA Technical Reports Server (NTRS)

    Dasgupta, Rajib

    2004-01-01

    This presentation reviews the requirements for safety critical fasteners in spaceflight hardware. Included in the presentation are design guidelines and information for Locking Helicoils, key locked inserts and thinwalled inserts, self locking screws and bolts. locknuts, and a locking adhesives, Loctite and Vibratite.

  12. Neural Networks Based Approach to Enhance Space Hardware Reliability

    NASA Technical Reports Server (NTRS)

    Zebulum, Ricardo S.; Thakoor, Anilkumar; Lu, Thomas; Franco, Lauro; Lin, Tsung Han; McClure, S. S.

    2011-01-01

    This paper demonstrates the use of Neural Networks as a device modeling tool to increase the reliability analysis accuracy of circuits targeted for space applications. The paper tackles a number of case studies of relevance to the design of Flight hardware. The results show that the proposed technique generates more accurate models than the ones regularly used to model circuits.

  13. Combine Security and Safety with the Right Door Hardware.

    ERIC Educational Resources Information Center

    Olmstead, Patrick R.

    1999-01-01

    Discusses how door design and construction can add safety and security to educational facilities. Exit device variations, and electromagnetic locks and access control are explored. Also discussed are inexpensive ways to improve the safety and security profiles of a building using door hardware. (GR)

  14. Nios II hardware acceleration of the epsilon quadratic sieve algorithm

    NASA Astrophysics Data System (ADS)

    Meyer-Bäse, Uwe; Botella, Guillermo; Castillo, Encarnacion; García, Antonio

    2010-04-01

    The quadratic sieve (QS) algorithm is one of the most powerful algorithms to factor large composite primes used to break RSA cryptographic systems. The hardware structure of the QS algorithm seems to be a good fit for FPGA acceleration. Our new ɛ-QS algorithm further simplifies the hardware architecture making it an even better candidate for C2H acceleration. This paper shows our design results in FPGA resource and performance when implementing very long arithmetic on the Nios microprocessor platform with C2H acceleration for different libraries (GMP, LIP, FLINT, NRMP) and QS architecture choices for factoring 32-2048 bit RSA numbers.

  15. Surface moisture measurement system hardware acceptance test report

    SciTech Connect

    Ritter, G.A., Westinghouse Hanford

    1996-05-28

    This document summarizes the results of the hardware acceptance test for the Surface Moisture Measurement System (SMMS). This test verified that the mechanical and electrical features of the SMMS functioned as designed and that the unit is ready for field service. The bulk of hardware testing was performed at the 306E Facility in the 300 Area and the Fuels and Materials Examination Facility in the 400 Area. The SMMS was developed primarily in support of Tank Waste Remediation System (TWRS) Safety Programs for moisture measurement in organic and ferrocyanide watch list tanks.

  16. Space biology initiative program definition review. Trade study 3: Hardware miniaturization versus cost

    NASA Technical Reports Server (NTRS)

    Jackson, L. Neal; Crenshaw, John, Sr.; Davidson, William L.; Herbert, Frank J.; Bilodeau, James W.; Stoval, J. Michael; Sutton, Terry

    1989-01-01

    The optimum hardware miniaturization level with the lowest cost impact for space biology hardware was determined. Space biology hardware and/or components/subassemblies/assemblies which are the most likely candidates for application of miniaturization are to be defined and relative cost impacts of such miniaturization are to be analyzed. A mathematical or statistical analysis method with the capability to support development of parametric cost analysis impacts for levels of production design miniaturization are provided.

  17. GSTAMIDS ground-penetrating radar: hardware description

    NASA Astrophysics Data System (ADS)

    Sower, Gary D.; Eberly, John; Christy, Ed

    2001-10-01

    The Ground Standoff Mine Detection System (GSTAMIDS) is now in the Engineering, Manufacturing and Development (EMD) Block 0 phase for USA CECOM. The Mine Detection Subsystem (MDS) presently utilizes three different sensor technologies to detect buried anti-tank (AT) land mines; Ground Penetrating Radar (GPR), Pulsed Magnetic Induction (PMI), and passive infrared (IR). The GSTAMIDS hardware and software architectures are designed so that other technologies can readily be incorporated when and if they prove viable. Each sensor suite is designed to detect the buried mines and to discriminate against various clutter and background objects. Sensor data fusion of the outputs of the individual sensor suites then enhances the detection probability while reducing the false alarm rate from clutter objects. The metal detector is an essential tool for buried mine detection, as metal land mines still account for a large percentage of land mines. Technologies such as nuclear quadrupole resonance (NQR or QR) are presently being developed to detect or confirm the presence of explosive material in buried land mines, particularly the so-called plastic mines; unfortunately, the radio frequency signals required cannot penetrate into a metal land mine. The limitation of the metal detector is not in detection of the metal mines, but in the additional detection of metal clutter. A metal detector has been developed using singular value decomposition (SVD) extraction techniques to discriminate the mines from the clutter, thereby greatly reducing false alarm rates. This mine detector is designed to characterize the impulse response function of the metal objects, based on a parametric three-pole model of the response, and to use pattern recognition to determine the match of the responses to known mines. In addition to discrimination against clutter, the system can also generally tell one mine type from another. This paper describes the PMI sensor suite hardware and its physical incorporation

  18. DAQ hardware and software development for the ATLAS Pixel Detector

    NASA Astrophysics Data System (ADS)

    Stramaglia, Maria Elena

    2016-07-01

    In 2014, the Pixel Detector of the ATLAS experiment has been extended by about 12 million pixels thanks to the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented along with newly designed readout hardware to support high bandwidth for data readout and calibration. The hardware is supported by an embedded software stack running on the readout boards. The same boards will be used to upgrade the readout bandwidth for the two outermost barrel layers of the ATLAS Pixel Detector. We present the IBL readout hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel Detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  19. Development of Enhanced Avionics Flight Hardware Selection Process

    NASA Technical Reports Server (NTRS)

    Smith, K.; Watson, G. L.

    2003-01-01

    The primary objective of this research was to determine the processes and feasibility of using commercial off-the-shelf PC104 hardware for flight applications. This would lead to a faster, better, and cheaper approach to low-budget programs as opposed to the design, procurement. and fabrication of space flight hardware. This effort will provide experimental evaluation with results of flight environmental testing. Also, a method and/or suggestion used to bring test hardware up to flight standards will be given. Several microgravity programs, such as the Equiaxed Dendritic Solidification Experiment, Self-Diffusion in Liquid Elements, and various other programs, are interested in PC104 environmental testing to establish the limits of this technology.

  20. High-Speed Isolation Board for Flight Hardware Testing

    NASA Technical Reports Server (NTRS)

    Yamamoto, Clifford K.; Goodpasture, Richard L.

    2011-01-01

    There is a need to provide a portable and cost-effective galvanic isolation between ground support equipment and flight hardware such that any unforeseen voltage differential between ground and power supplies is eliminated. An interface board was designed for use between the ground support equipment and the flight hardware that electrically isolates all input and output signals and faithfully reproduces them on each side of the interface. It utilizes highly integrated multi-channel isolating devices to minimize size and reduce assembly time. This single-board solution provides appropriate connector hardware and breakout of required flight signals to individual connectors as needed for various ground support equipment. The board utilizes multi-channel integrated circuits that contain transformer coupling, thereby allowing input and output signals to be isolated from one another while still providing high-fidelity reproduction of the signal up to 90 MHz. The board also takes in a single-voltage power supply input from the ground support equipment and in turn provides a transformer-derived isolated voltage supply to power the portion of the circuitry that is electrically connected to the flight hardware. Prior designs used expensive opto-isolated couplers that were required for each signal to isolate and were time-consuming to assemble. In addition, these earlier designs were bulky and required a 2U rack-mount enclosure. The new design is smaller than a piece of 8.5 11-in. (.22 28-mm) paper and can be easily hand-carried where needed. The flight hardware in question is based on a lineage of existing software-defined radios (SDRs) that utilize a common interface connector with many similar input-output signals present. There are currently four to five variations of this SDR, and more upcoming versions are planned based on the more recent design.

  1. Hardware Implementation of Singular Value Decomposition

    NASA Astrophysics Data System (ADS)

    Majumder, Swanirbhar; Shaw, Anil Kumar; Sarkar, Subir Kumar

    2016-06-01

    Singular value decomposition (SVD) is a useful decomposition technique which has important role in various engineering fields such as image compression, watermarking, signal processing, and numerous others. SVD does not involve convolution operation, which make it more suitable for hardware implementation, unlike the most popular transforms. This paper reviews the various methods of hardware implementation for SVD computation. This paper also studies the time complexity and hardware complexity in various methods of SVD computation.

  2. Electronic hardware implementations of neutral networks

    NASA Technical Reports Server (NTRS)

    Thakoor, A. P.; Moopenn, A.; Lambe, John; Khanna, S. K.

    1987-01-01

    This paper examines some of the present work on the development of electronic neural network hardware. In particular, the investigations currently under way at JPL on neural network hardware implementations based on custom VLSI technology, novel thin film materials, and an analog-digital hybrid architecture are reviewed. The availability of such hardware will greatly benefit and enhance the present intense research effort on the potential computational capabilities of highly parallel systems based on neural network models.

  3. Life Sciences Division Spaceflight Hardware

    NASA Technical Reports Server (NTRS)

    Yost, B.

    1999-01-01

    The Ames Research Center (ARC) is responsible for the development, integration, and operation of non-human life sciences payloads in support of NASA's Gravitational Biology and Ecology (GB&E) program. To help stimulate discussion and interest in the development and application of novel technologies for incorporation within non-human life sciences experiment systems, three hardware system models will be displayed with associated graphics/text explanations. First, an Animal Enclosure Model (AEM) will be shown to communicate the nature and types of constraints physiological researchers must deal with during manned space flight experiments using rodent specimens. Second, a model of the Modular Cultivation System (MCS) under development by ESA will be presented to highlight technologies that may benefit cell-based research, including advanced imaging technologies. Finally, subsystems of the Cell Culture Unit (CCU) in development by ARC will also be shown. A discussion will be provided on candidate technology requirements in the areas of specimen environmental control, biotelemetry, telescience and telerobotics, and in situ analytical techniques and imaging. In addition, an overview of the Center for Gravitational Biology Research facilities will be provided.

  4. Environmental testing for new SOFIA flight hardware

    NASA Astrophysics Data System (ADS)

    Lachenmann, Michael; Wolf, Jürgen; Strecker, Rainer; Weckenmann, Benedikt; Trimpe, Fritz; Hall, Helen J.

    2014-07-01

    New flight hardware for the Stratospheric Observatory for Infrared Astronomy (SOFIA) has to be tested to prove its safety and functionality and to measure its performance under flight conditions. Although it is not expected to experience critical issues inside the pressurized cabin with close-to-normal conditions, all equipment has to be tested for safety margins in case of a decompression event and/or for unusual high temperatures, e.g. inside an electronic unit caused by a malfunction as well as unusual high ambient temperatures inside the cabin, when the aircraft is parked in a desert. For equipment mounted on the cavity side of the telescope, stratospheric conditions apply, i.e., temperatures from -40 °C to -60°C and an air pressure of about 0.1 bar. Besides safety aspects as not to endanger personnel or equipment, new hardware inside the cavity has to function and to perform to specifications under such conditions. To perform these tests, an environmental test laboratory was set up at the SOFIA Science Center at the NASA Ames Research Center, including a thermal vacuum chamber, temperature measurement equipment, and a control and data logging workstation. This paper gives an overview of the test and measurement equipment, shows results from the commissioning and characterization of the thermal vacuum chamber, and presents examples of the component tests that were performed so far. To test the focus position stability of optics when cooling them to stratospheric temperatures, an auto-collimation device has been developed. We will present its design and results from measurements on commercial off-the-shelf optics as candidates for the new Wide Field Imager for SOFIA as an example.

  5. The Application of Acoustic Measurements and Audio Recordings for Diagnosis of In-Flight Hardware Anomalies

    NASA Technical Reports Server (NTRS)

    Welsh, David; Denham, Samuel; Allen, Christopher

    2011-01-01

    In many cases, an initial symptom of hardware malfunction is unusual or unexpected acoustic noise. Many industries such as automotive, heating and air conditioning, and petro-chemical processing use noise and vibration data along with rotating machinery analysis techniques to identify noise sources and correct hardware defects. The NASA/Johnson Space Center Acoustics Office monitors the acoustic environment of the International Space Station (ISS) through periodic sound level measurement surveys. Trending of the sound level measurement survey results can identify in-flight hardware anomalies. The crew of the ISS also serves as a "detection tool" in identifying unusual hardware noises; in these cases the spectral analysis of audio recordings made on orbit can be used to identify hardware defects that are related to rotating components such as fans, pumps, and compressors. In this paper, three examples of the use of sound level measurements and audio recordings for the diagnosis of in-flight hardware anomalies are discussed: identification of blocked inter-module ventilation (IMV) ducts, diagnosis of abnormal ISS Crew Quarters rack exhaust fan noise, and the identification and replacement of a defective flywheel assembly in the Treadmill with Vibration Isolation (TVIS) hardware. In each of these examples, crew time was saved by identifying the off nominal component or condition that existed and in directing in-flight maintenance activities to address and correct each of these problems.

  6. Real-time orthorectification by FPGA-based hardware acceleration

    NASA Astrophysics Data System (ADS)

    Kuo, David; Gordon, Don

    2010-10-01

    Orthorectification that corrects the perspective distortion of remote sensing imagery, providing accurate geolocation and ease of correlation to other images is a valuable first-step in image processing for information extraction. However, the large amount of metadata and the floating-point matrix transformations required to operate on each pixel make this a computation and I/O (Input/Output) intensive process. As result much imagery is either left unprocessed or loses timesensitive value in the long processing cycle. However, the computation on each pixel can be reduced substantially by using computational results of the neighboring pixels and accelerated by special pipelined hardware architecture in one to two orders of magnitude. A specialized coprocessor that is implemented inside an FPGA (Field Programmable Gate Array) chip and surrounded by vendorsupported hardware IP (Intellectual Property) shares the computation workload with CPU through PCI-Express interface. The ultimate speed of one pixel per clock (125 MHz) is achieved by the pipelined systolic array architecture. The optimal partition between software and hardware, the timing profile among image I/O and computation, and the highly automated GUI (Graphical User Interface) that fully exploits this speed increase to maximize overall image production throughput will also be discussed. The software that runs on a workstation with the acceleration hardware orthorectifies 16 Megapixels per second, which is 16 times faster than without the hardware. It turns the production time from months to days. A real-life successful story of an imaging satellite company that adopted such workstations for their orthorectified imagery production will be presented. The potential candidacy of the image processing computation that can be accelerated more efficiently by the same approach will also be analyzed.

  7. Rapid space hardware development through computer-automated testing

    SciTech Connect

    Masters, D.S.; Ruud, K.K.

    1997-10-01

    FORTE, the Fast On-Orbit Recording of Transient Events small satellite designed and built by Los Alamos and Sandia National Laboratories, is scheduled for launch in August, 1997. In the spirit of {open_quotes}better, cheaper, faster{close_quotes} satellites, the RF experiment hardware (receiver and trigger sub-systems) necessitated rapid prototype testing and characterization in the development of space-flight components. This was accomplished with the assembly of engineering model hardware prior to construction of flight hardware and the design of component-specific, PC-based software control libraries. Using the LabVIEW{reg_sign} graphical programming language, together with off-the-shelf PC digital I/O and GPIB interface cards, hardware control and complete automation of test equipment was possible from one PC. Because the receiver and trigger sub-systems employed complex functions for signal discrimination and transient detection, thorough validation of all functions and illumination of any faults were priorities. These methods were successful in accelerating the development and characterization of space-flight components prior to integration and allowed more complete data to be gathered than could have been accomplished without automation. Additionally, automated control of input signal sources was carried over from bench-level to system-level with the use of networked Linux workstation utilizing a GPIB interface.

  8. Solar array shuttle flight experiment - hardware development and testing

    SciTech Connect

    Elms, R.V.; Hill, H.C.; Young, L.E.

    1982-09-01

    This paper reports on the fabrication and ground testing of a large area, light-weight, flexible substrate developmental solar array wing that has been built for NASA-MSFC (Contract NAS8-31352) and of the supporting structure and data acquisition system (DAS) which, with the wing will be flown in the shuttle as an experiment in 1984. The experiment will verify the dynamics, thermodynamic, and electrical performance predictions of the array wing and will demonstrate the structural capability of the array wing for Orbiter launch and re-entry environments. The accomodation of the Shuttle payload requirements has resulted in several array wing and operation modifications since the ground demonstration of the array wing in the technology development program. The experiment hardware verification program was designed to minimize costs and risk of experiment performance degradation while maintaining shuttle and crew safety. The previous full-scale wing hardware tests included an extension mast water table test and wing testing for random vibration, thermal vacuum, and acoustic environments. The results of these tests were used to define wing design modifications and to scope the test program for the experiment hardware. The experiment hardware acceptance test program will be completed in October 1982.

  9. Tinker's Toys: Lessons from Bank Street: Hardware.

    ERIC Educational Resources Information Center

    Tinker, Robert

    1985-01-01

    Bank Street Laboratory (a set of hardware/software tools for measuring temperature, light, and sound) consists of a board that plugs into Apple microcomputers, cabling, software, and six probes. Discusses the laboratory's hardware, including the analog-to-digital converter, multiplier chip, and modular connectors. Circuit diagrams of components…

  10. Properly Matching Microcomputer Hardware, Software Minimizes "Glitches."

    ERIC Educational Resources Information Center

    Fredenburg, Philip B.

    1986-01-01

    Microcomputer systems for school districts are best obtained by selecting the software, and matching it with hardware. Discusses criteria for software and hardware, monitors, input/output devices, backup devices, and printers. Components of two basic microcomputer systems for the business office are proposed. (MLF)

  11. Returned Solar Max hardware degradation study results

    NASA Technical Reports Server (NTRS)

    Triolo, Jack J.; Ousley, Gilbert W.

    1989-01-01

    The Solar Maximum Repair Mission returned with the replaced hardware that had been in low Earth orbit for over four years. The materials of this returned hardware gave the aerospace community an opportunity to study the realtime effects of atomic oxygen, solar radiation, impact particles, charged particle radiation, and molecular contamination. The results of these studies are summarized.

  12. 16 CFR 1509.7 - Hardware.

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... NON-FULL-SIZE BABY CRIBS § 1509.7 Hardware. (a) The hardware in a non-full-size baby crib shall be... abuse. (b) Non-full-size baby cribs shall incorporate locking or latching devices for dropsides or... non-full-size baby crib....

  13. Dynamic testing of docking system hardware

    NASA Technical Reports Server (NTRS)

    Dorland, W. D.

    1972-01-01

    Extensive dynamic testing was conducted to verify the flight readiness of the Apollo docking hardware. Testing was performed on a unique six degree-of-freedom motion simulator controlled by a computer that calculated the associated spacecraft motions. The test system and the results obtained by subjecting flight-type docking hardware to actual impact loads and resultant spacecraft dynamics are described.

  14. A Survey of Display Hardware and Software.

    ERIC Educational Resources Information Center

    Poore, Jesse H., Jr.; And Others

    Reported are two papers which deal with the fundamentals of display hardware and software in computer systems. The first report presents the basic principles of display hardware in terms of image generation from buffers presumed to be loaded and controlled by a digital computer. The concepts surrounding the electrostatic tube, the electromagnetic…

  15. Hardware verification at Computational Logic, Inc.

    NASA Technical Reports Server (NTRS)

    Brock, Bishop C.; Hunt, Warren A., Jr.

    1990-01-01

    The following topics are covered in viewgraph form: (1) hardware verification; (2) Boyer-Moore logic; (3) core RISC; (4) the FM8502 fabrication, implementation specification, and pinout; (5) hardware description language; (6) arithmetic logic generator; (7) near term expected results; (8) present trends; (9) future directions; (10) collaborations and technology transfer; and (11) technology enablers.

  16. Hardware and software fault tolerance - A unified architectural approach

    NASA Technical Reports Server (NTRS)

    Lala, Jaynarayan H.; Alger, Linda S.

    1988-01-01

    The loss of hardware fault tolerance which often arises when design diversity is used to improve the fault tolerance of computer software is considered analytically, and a unified design approach is proposed to avoid the problem. The fundamental theory of fault-tolerant (FT) architectures is reviewed; the current status of design-diversity software development is surveyed; and the FT-processor/attached-processor (FTP/AP) architecture developed by Lala et al. (1986) is described in detail and illustrated with diagrams. FTP/AP is shown to permit efficient implementation of N-version FT software while still tolerating random hardware failures with very high coverage; the reliability is found to be significantly higher than that of conventional majority-vote N-version software.

  17. An evaluation of Skylab habitability hardware

    NASA Technical Reports Server (NTRS)

    Stokes, J.

    1974-01-01

    For effective mission performance, participants in space missions lasting 30-60 days or longer must be provided with hardware to accommodate their personal needs. Such habitability hardware was provided on Skylab. Equipment defined as habitability hardware was that equipment composing the food system, water system, sleep system, waste management system, personal hygiene system, trash management system, and entertainment equipment. Equipment not specifically defined as habitability hardware but which served that function were the Wardroom window, the exercise equipment, and the intercom system, which was occasionally used for private communications. All Skylab habitability hardware generally functioned as intended for the three missions, and most items could be considered as adequate concepts for future flights of similar duration. Specific components were criticized for their shortcomings.

  18. Wavefront curvature sensing in a 2.5m wide-field telescope: design, analysis, and implementation for real-time correction of telescope alignment

    NASA Astrophysics Data System (ADS)

    Lousberg, Gregory P.; Moreau, Vincent; Pirnay, Olivier; Gloesener, Pierre; Flebus, Carlo

    2015-09-01

    In the framework of the design and manufacturing of a wide-field 2.5m telescope for the Observatorio Astrofisica de Javalambre (OAJ), AMOS has developed a novel wavefront sensing system that allows for real time correction of the alignment of the telescope without perturbing the acquisition of science images. The system is based on the wavefront curvature sensing (WCS) technique in which two out-of-focus images of a star are used for reconstructing the telescope wavefront error. Any deviations from the nominal wavefront error that is obtained after telescope final alignment are tracked and corrective actions can be implemented so as to optimize the telescope optical quality. The wavefront reconstruction technique and the associated corrections of the telescope alignment have been modelled and analyzed so as to validate the proposed approach before implementation in the telescope. To this aim, a bespoke coupled Zemax-Matlab model has been developed by AMOS. The model incorporates the algorithm for the telescope wavefront error reconstruction from out-of-focus images and computation of the alignment corrections in the telescope model. The justification of the wavefront sensing approach, its robustness against several sources of errors, as well as the selection of the appropriate equipment for its implementation in the telescope are discussed on the basis of this combined model.

  19. Benchmarking hypercube hardware and software

    NASA Technical Reports Server (NTRS)

    Grunwald, Dirk C.; Reed, Daniel A.

    1986-01-01

    It was long a truism in computer systems design that balanced systems achieve the best performance. Message passing parallel processors are no different. To quantify the balance of a hypercube design, an experimental methodology was developed and the associated suite of benchmarks was applied to several existing hypercubes. The benchmark suite includes tests of both processor speed in the absence of internode communication and message transmission speed as a function of communication patterns.

  20. Evolvable Hardware for Space Applications

    NASA Technical Reports Server (NTRS)

    Lohn, Jason; Globus, Al; Hornby, Gregory; Larchev, Gregory; Kraus, William

    2004-01-01

    This article surveys the research of the Evolvable Systems Group at NASA Ames Research Center. Over the past few years, our group has developed the ability to use evolutionary algorithms in a variety of NASA applications ranging from spacecraft antenna design, fault tolerance for programmable logic chips, atomic force field parameter fitting, analog circuit design, and earth observing satellite scheduling. In some of these applications, evolutionary algorithms match or improve on human performance.

  1. Flight Hardware Development and Research at MSFC for Optimizing Success on the International Space Station

    NASA Technical Reports Server (NTRS)

    2003-01-01

    To optimize biological crystallization success in microgravity in-house personnel at the MSFC are working on the development of innovative flight hardware such as Delta-L and the Iterative Biological Crystallization (IBC) apparatus as well as troubleshooting the performance of existing hardware. Delta-L will provide a diagnostic hardware to examine the relationship between crystal growth characteristics and crystal quality improvement in microgravity. IBC is a new hardware being designed to allow iteration of crystal growth experiments in microgravity using innovative lab on a chip technology. While being built to obtain scientific data of benefit to the scientific community, the design methods involved in the development of these hardware have directly benefited other groups within NASA and keep NASA at the forefront of innovation.

  2. FPS-RAM: Fast Prefix Search RAM-Based Hardware for Forwarding Engine

    NASA Astrophysics Data System (ADS)

    Zaitsu, Kazuya; Yamamoto, Koji; Kuroda, Yasuto; Inoue, Kazunari; Ata, Shingo; Oka, Ikuo

    Ternary content addressable memory (TCAM) is becoming very popular for designing high-throughput forwarding engines on routers. However, TCAM has potential problems in terms of hardware and power costs, which limits its ability to deploy large amounts of capacity in IP routers. In this paper, we propose new hardware architecture for fast forwarding engines, called fast prefix search RAM-based hardware (FPS-RAM). We designed FPS-RAM hardware with the intent of maintaining the same search performance and physical user interface as TCAM because our objective is to replace the TCAM in the market. Our RAM-based hardware architecture is completely different from that of TCAM and has dramatically reduced the costs and power consumption to 62% and 52%, respectively. We implemented FPS-RAM on an FPGA to examine its lookup operation.

  3. Optical Properties of Nanosatellite Hardware

    NASA Technical Reports Server (NTRS)

    Finckenor, M. M.; Coker, R. F.

    2014-01-01

    Over the last decade, a number of very small satellites have been launched into space. These have been called nanosatellites (generally of a weight between 1 and 10 kg) or picosatellites (weight <1 kg). This also includes CubeSats, which are based on 10-cm cube units. With the addition of the Japanese Experiment Module (JEM) Small Satellite Orbital Deployer (J-SSOD) to the International Space Station (ISS), CubeSats are easily cycled through the JEM airlock and deployed into space (fig. 1). The number of CubeSats launched since 2003 was approaching 100 at the time of publication, and the authors expect this trend in research to continue, particularly for high school and college flight experiments. Because these spacecraft are so small, there is usually no allowance for shielding or active heating or cooling of the avionics and other hardware. Parts that are usually ignored in the thermal analysis of larger spacecraft may contribute significantly to the heat load of a tiny satellite. In addition, many small satellites have commercial-off-the-shelf (COTS) components. To reduce costs, many providers of COTS components do not include the optical and physical parameters necessary for accurate thermal analysis. Marshall Space Flight Center participated in the development and analysis of the Space Missile Defense Command-Operational Nanosatellite Effect (SMDC-ONE) and the Edison Demonstration of Smallsat Networks (EDSN) nanosatellites. These optical property measurements are documented here in hopes that they may benefit future nanosatellite and picosatellite programs and aid thermal analysis to ensure project goals are met, with the understanding that material properties may vary by vendor, batch, manufacturing process, and preflight handling. Where possible, complementary data are provided from ground simulations of the space environment and flight experiments, such as the Materials on International Space Station Experiment (MISSE) series. NASA gives no recommendation

  4. SUMC-DV hardware manual

    NASA Technical Reports Server (NTRS)

    Feller, A.

    1972-01-01

    The assembly, the physical and electrical characteristics, and the basic electrical tests of the Space Ultrareliable Modular Computer Demonstration Vehicle (SUMC-DV), are described. The descriptions include: (1) the packaging concepts, physical assembly, design and fabrication using design automation techniques of 10 different types of custom CMOS LSI arrays; (2) the fabrication and testing of the various components including the LSI arrays; (3) the hierarchy of the memory complement and the clock generation and distribution system; (4) system testing techniques; and (5) the procedure employed in the electrical checkout of the system.

  5. Tomographic image reconstruction and rendering with texture-mapping hardware

    SciTech Connect

    Azevedo, S.G.; Cabral, B.K.; Foran, J.

    1994-07-01

    The image reconstruction problem, also known as the inverse Radon transform, for x-ray computed tomography (CT) is found in numerous applications in medicine and industry. The most common algorithm used in these cases is filtered backprojection (FBP), which, while a simple procedure, is time-consuming for large images on any type of computational engine. Specially-designed, dedicated parallel processors are commonly used in medical CT scanners, whose results are then passed to graphics workstation for rendering and analysis. However, a fast direct FBP algorithm can be implemented on modern texture-mapping hardware in current high-end workstation platforms. This is done by casting the FBP algorithm as an image warping operation with summing. Texture-mapping hardware, such as that on the Silicon Graphics Reality Engine (TM), shows around 600 times speedup of backprojection over a CPU-based implementation (a 100 Mhz R4400 in this case). This technique has the further advantages of flexibility and rapid programming. In addition, the same hardware can be used for both image reconstruction and for volumetric rendering. The techniques can also be used to accelerate iterative reconstruction algorithms. The hardware architecture also allows more complex operations than straight-ray backprojection if they are required, including fan-beam, cone-beam, and curved ray paths, with little or no speed penalties.

  6. Tomographic image reconstruction and rendering with texture-mapping hardware

    NASA Astrophysics Data System (ADS)

    Azevedo, Stephen G.; Cabral, Brian K.; Foran, Jim

    1994-07-01

    The image reconstruction problem, also known as the inverse Radon transform, for x-ray computed tomography (CT) is found in numerous applications in medicine and industry. The most common algorithm used in these cases is filtered backprojection (FBP), which, while a simple procedure, is time-consuming for large images on any type of computational engine. Specially designed, dedicated parallel processors are commonly used in medical CT scanners, whose results are then passed to a graphics workstation for rendering and analysis. However, a fast direct FBP algorithm can be implemented on modern texture-mapping hardware in current high-end workstation platforms. This is done by casting the FBP algorithm as an image warping operation with summing. Texture- mapping hardware, such as that on the silicon Graphics Reality Engine, shows around 600 times speedup of backprojection over a CPU-based implementation (a 100 Mhz R4400 in our case). This technique has the further advantages of flexibility and rapid programming. In addition, the same hardware can be used for both image reconstruction and for volumetric rendering. Our technique can also be used to accelerate iterative reconstruction algorithms. The hardware architecture also allows more complex operations than straight-ray backprojection if they are required, including fan-beam, cone-beam, and curved ray paths, with little or no speed penalties.

  7. Use of Heritage Hardware on MPCV Exploration Flight Test One

    NASA Technical Reports Server (NTRS)

    Rains, George Edward; Cross, Cynthia D.

    2011-01-01

    Due to an aggressive schedule for the first orbital test flight of an unmanned Orion capsule, known as Exploration Flight Test One (EFT1), combined with severe programmatic funding constraints, an effort was made to identify heritage hardware, i.e., already existing, flight-certified components from previous manned space programs, which might be available for use on EFT1. With the end of the Space Shuttle Program, no current means exists to launch Multi Purpose Logistics Modules (MPLMs) to the International Space Station (ISS), and so the inventory of many flight-certified Shuttle and MPLM components are available for other purposes. Two of these items are the Shuttle Ground Support Equipment Heat Exchanger (GSE Hx) and the MPLM cabin Positive Pressure Relief Assembly (PPRA). In preparation for the utilization of these components by the Orion Program, analyses and testing of the hardware were performed. The PPRA had to be analyzed to determine its susceptibility to pyrotechnic shock, and vibration testing had to be performed, since those environments are predicted to be significantly more severe during an Orion mission than those the hardware was originally designed to accommodate. The GSE Hx had to be tested for performance with the Orion thermal working fluids, which are different from those used by the Space Shuttle. This paper summarizes the certification of the use of heritage hardware for EFT1.

  8. Measuring Auroral and Arctic Ozone Using Student Made Hardware

    NASA Astrophysics Data System (ADS)

    Pina, M.

    2015-12-01

    This project is twofold to test the feasibility of student made hardware and teach students more about atmospheric instrumentation by providing students with education and materials, instructing them in design and building of hardware, and testing the hardware against commercial models in terms of weight, cost, and features. The Gaseous Compounds team of the University of Houston Undergraduate Student Instrument Project (USIP) selected the parts and the students of the team are assembling the payload. The payload will launch on a latex balloon in Houston and Fairbanks, Alaska. The instrument will gather data on the concentration of certain gases in the atmosphere as well as a meteorological profile of the atmosphere. The students plan to have the instrument collect and transmit data on carbon monoxide, nitric oxide, nitrogen dioxide, and ozone, as well as temperature, humidity, and barometric pressure. The data will also be stored on an SD card as a backup in case transmission fails. These payloads will fly at night and day to get an accurate vertical profile of the atmosphere and these results will be tested against the results of commercial hardware with the same capabilities.

  9. Hardware Testing for the Optical PAyload for Lasercomm Science (OPALS)

    NASA Technical Reports Server (NTRS)

    Slagle, Amanda

    2011-01-01

    Hardware for several subsystems of the proposed Optical PAyload for Lasercomm Science (OPALS), including the gimbal and avionics, was tested. Microswitches installed on the gimbal were evaluated to verify that their point of actuation would remain within the acceptable range even if the switches themselves move slightly during launch. An inspection of the power board was conducted to ensure that all power and ground signals were isolated, that polarized components were correctly oriented, and that all components were intact and securely soldered. Initial testing on the power board revealed several minor problems, but once they were fixed the power board was shown to function correctly. All tests and inspections were documented for future use in verifying launch requirements.

  10. Optical design of a novel instrument that uses the Hartmann-Shack sensor and Zernike polynomials to measure and simulate customized refraction correction surgery outcomes and patient satisfaction

    NASA Astrophysics Data System (ADS)

    Yasuoka, Fatima M. M.; Matos, Luciana; Cremasco, Antonio; Numajiri, Mirian; Marcato, Rafael; Oliveira, Otavio G.; Sabino, Luis G.; Castro N., Jarbas C.; Bagnato, Vanderlei S.; Carvalho, Luis A. V.

    2016-03-01

    An optical system that conjugates the patient's pupil to the plane of a Hartmann-Shack (HS) wavefront sensor has been simulated using optical design software. And an optical bench prototype is mounted using mechanical eye device, beam splitter, illumination system, lenses, mirrors, mirrored prism, movable mirror, wavefront sensor and camera CCD. The mechanical eye device is used to simulate aberrations of the eye. From this device the rays are emitted and travelled by the beam splitter to the optical system. Some rays fall on the camera CCD and others pass in the optical system and finally reach the sensor. The eye models based on typical in vivo eye aberrations is constructed using the optical design software Zemax. The computer-aided outcomes of each HS images for each case are acquired, and these images are processed using customized techniques. The simulated and real images for low order aberrations are compared using centroid coordinates to assure that the optical system is constructed precisely in order to match the simulated system. Afterwards a simulated version of retinal images is constructed to show how these typical eyes would perceive an optotype positioned 20 ft away. Certain personalized corrections are allowed by eye doctors based on different Zernike polynomial values and the optical images are rendered to the new parameters. Optical images of how that eye would see with or without corrections of certain aberrations are generated in order to allow which aberrations can be corrected and in which degree. The patient can then "personalize" the correction to their own satisfaction. This new approach to wavefront sensing is a promising change in paradigm towards the betterment of the patient-physician relationship.

  11. Advances in SPECT and PET Hardware.

    PubMed

    Slomka, Piotr J; Pan, Tinsu; Berman, Daniel S; Germano, Guido

    2015-01-01

    There have been significant recent advances in single photon emission computed tomography (SPECT) and positron emission tomography (PET) hardware. Novel collimator designs, such as multi-pinhole and locally focusing collimators arranged in geometries that are optimized for cardiac imaging have been implemented to reduce imaging time and radiation dose. These new collimators have been coupled with solid state photon detectors to further improve image quality and reduce scanner size. The new SPECT scanners demonstrate up to a 7-fold increase in photon sensitivity and up to 2 times improvement in image resolution. Although PET scanners are used primarily for oncological imaging, cardiac imaging can benefit from the improved PET sensitivity of 3D systems without inter-plane septa and implementation of the time-of-flight reconstruction. Additionally, resolution recovery techniques are now implemented by all major PET vendors. These new methods improve image contrast, image resolution, and reduce image noise. Simultaneous PET/magnetic resonance (MR) hybrid systems have been developed. Solid state detectors with avalanche photodiodes or digital silicon photomultipliers have also been utilized in PET. These new detectors allow improved image resolution, higher count rate, as well as a reduced sensitivity to electromagnetic MR fields. PMID:25721706

  12. 77 FR 42500 - Designation of a Class of Employees for Addition to the Special Exposure Cohort; Correction

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-07-19

    ... HUMAN SERVICES Designation of a Class of Employees for Addition to the Special Exposure Cohort... addition to the Special Exposure Cohort (SEC) under the Energy Employees Occupational Illness Compensation... more other classes of employees included in the Special Exposure Cohort. The designation published...

  13. 78 FR 43853 - Designation for the Champaign-Danville, IL Area; Correction to Geographic Area for Champaign...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-07-22

    ..., 2012 Federal Register Notice (77 FR 76452), GIPSA requested applications for designation to provide... Federal Register Notice published on December 28, 2012 in FR Doc. 2012-76452, in the third column, the... Grain Inspection, Packers and Stockyards Administration Designation for the Champaign-Danville, IL...

  14. Microcomputer basics. Hardware. Part I.

    PubMed

    Siguel, E N

    1983-12-01

    Microcomputers are invading every aspect of life including the practice of pathology. This first in a series of articles is designed to help neophytes make effective use of these new tools. A list of references, intended to provide readers with more information on the subject of microcomputers and their applications to pathology, will be furnished at the conclusion of the series. PMID:10264428

  15. Design of Post-Wall Feed Waveguide for a Parallel Plate Slot Array by an Analysis Model with Corrected Solid-Walls

    NASA Astrophysics Data System (ADS)

    Hashimoto, Koh; Hirokawa, Jiro; Ando, Makoto

    A novel analysis model for post-wall waveguide T-junctions is proposed. Equivalent solid-walls for the post-walls to have equal guided wavelength are corrected in the analysis model so that the wall thickness for the coupling windows is set to the difference in the width between the post-wall and the solid-wall waveguides. The accuracy of the proposed model is confirmed by comparing it to an HFSS analysis for the real structure of the post-wall waveguide T-junction including the post surfaces. 61.25GHz model antennas are fabricated for experimental verification. The reflection of the antenna designed by the modified analysis model is suppressed to below -15dB over a 5.6GHz bandwidth, while that in the antenna designed by the conventional model is larger than -15dB around the design frequency.

  16. Multi-frequency EIT hardware system based on DSP.

    PubMed

    Zhang, Shuai; Xu, Guizhi; Wu, Huanli; Geng, Duyan; Yan, Weili

    2006-01-01

    Electrical impedance tomography (EIT) is a new functional imaging technique in the biomedical engineering. A multi-frequency hardware EIT system based on digital signal processor (DSP) has been developed, and the system also has been designed using modular structure. Some experiments in vitro tissue are done and their images are generated with the filtered back-projection algorithm using this system in real time. The results show that this system is feasible, stable, convenient and extended. PMID:17959484

  17. A new hardware-efficient algorithm and reconfigurable architecture for image contrast enhancement.

    PubMed

    Huang, Shih-Chia; Chen, Wen-Chieh

    2014-10-01

    Contrast enhancement is crucial when generating high quality images for image processing applications, such as digital image or video photography, liquid crystal display processing, and medical image analysis. In order to achieve real-time performance for high-definition video applications, it is necessary to design efficient contrast enhancement hardware architecture to meet the needs of real-time processing. In this paper, we propose a novel hardware-oriented contrast enhancement algorithm which can be implemented effectively for hardware design. In order to be considered for hardware implementation, approximation techniques are proposed to reduce these complex computations during performance of the contrast enhancement algorithm. The proposed hardware-oriented contrast enhancement algorithm achieves good image quality by measuring the results of qualitative and quantitative analyzes. To decrease hardware cost and improve hardware utilization for real-time performance, a reduction in circuit area is proposed through use of parameter-controlled reconfigurable architecture. The experiment results show that the proposed hardware-oriented contrast enhancement algorithm can provide an average frame rate of 48.23 frames/s at high definition resolution 1920 × 1080. PMID:25148665

  18. Programmable hardware for reconfigurable computing systems

    NASA Astrophysics Data System (ADS)

    Smith, Stephen

    1996-10-01

    In 1945 the work of J. von Neumann and H. Goldstein created the principal architecture for electronic computation that has now lasted fifty years. Nevertheless alternative architectures have been created that have computational capability, for special tasks, far beyond that feasible with von Neumann machines. The emergence of high capacity programmable logic devices has made the realization of these architectures practical. The original ENIAC and EDVAC machines were conceived to solve special mathematical problems that were far from today's concept of 'killer applications.' In a similar vein programmable hardware computation is being used today to solve unique mathematical problems. Our programmable hardware activity is focused on the research and development of novel computational systems based upon the reconfigurability of our programmable logic devices. We explore our programmable logic architectures and their implications for programmable hardware. One programmable hardware board implementation is detailed.

  19. Rapid Production of Composite Prototype Hardware

    NASA Technical Reports Server (NTRS)

    DeLay, T. K.

    2000-01-01

    The objective of this research was to provide a mechanism to cost-effectively produce composite hardware prototypes. The task was to take a hands-on approach to developing new technologies that could benefit multiple future programs.

  20. Hardware device binding and mutual authentication

    SciTech Connect

    Hamlet, Jason R; Pierson, Lyndon G

    2014-03-04

    Detection and deterrence of device tampering and subversion by substitution may be achieved by including a cryptographic unit within a computing device for binding multiple hardware devices and mutually authenticating the devices. The cryptographic unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a binding PUF value. The cryptographic unit uses the binding PUF value during an enrollment phase and subsequent authentication phases. During a subsequent authentication phase, the cryptographic unit uses the binding PUF values of the multiple hardware devices to generate a challenge to send to the other device, and to verify a challenge received from the other device to mutually authenticate the hardware devices.

  1. Using Verbal Protocol Methodology in the Evaluation of Software and Hardware.

    ERIC Educational Resources Information Center

    Mathison, Sandra; Meyer, Tricia R.; Vargas, Juan D.

    1999-01-01

    Describes verbal protocols as a useful tool for evaluating computer hardware and software, especially if informed by activity theory. Such protocols cannot, however, stand alone in a thorough evaluation design. (Author/SLD)

  2. Aberration-corrected aspheric grating designs for the Lyman/Far-Ultraviolet Spectroscopic Explorer high-resolution spectrograph - A comparison

    NASA Technical Reports Server (NTRS)

    Trout, Catherine; Content, David; Davila, Pam

    1992-01-01

    Two approaches to reducing the optical aberrations of concave diffraction gratings have been studied to obtain candidate grating designs for the Lyman/Far-Ultraviolet Spectroscopic Explorer mission. The first approach involves shaping the grating substrate while using straight and equally spaced grooves. The second approach involves using a gating substrate with a relatively simple figure and holographically controlling the groove curvature and spacing. Specific designs derived from both approaches are analyzed and compared.

  3. IDD Archival Hardware Architecture and Workflow

    SciTech Connect

    Mendonsa, D; Nekoogar, F; Martz, H

    2008-10-09

    This document describes the functionality of every component in the DHS/IDD archival and storage hardware system shown in Fig. 1. The document describes steps by step process of image data being received at LLNL then being processed and made available to authorized personnel and collaborators. Throughout this document references will be made to one of two figures, Fig. 1 describing the elements of the architecture and the Fig. 2 describing the workflow and how the project utilizes the available hardware.

  4. A comprehensive comparison of spectral scatterometry hardware

    NASA Astrophysics Data System (ADS)

    Lensing, Kevin; Stirton, Broc; Starnes, Brian; Synoradzki, Joseph; Swain, Bryan; Lane, Lawrence

    2005-05-01

    In this paper, three different types of spectral scatterometry hardware are compared using Timbre Technologies' Optical Digital Profiler (ODP) as a common software platform. The hardware under consideration includes a spectroscopic reflectometer (R), polarizing spectroscopic reflectometer (RP) and a spectroscopic ellipsometer (SE). Four advanced lithographic applications are evaluated-two from Spansion's 110-nm Flash memory technology line, and two from AMD's 90-nm logic process. ODP models are developed and optimized for each application and each type of hardware. Results include static and dynamic repeatability, throughput, correlation to incumbent metrology and correlation to cross-section. For each application, the authors also attempt to determine the level of model complexity supported by each hardware type, with special attention paid to the relative sensitivity of each system to changes in critical dimension (CD) and resist profile. The results generally indicate that the SE is the most sensitive hardware type while the R is the most stable. The RP occupies some form of middle ground on both counts. These generalizations are largely application dependent and clear differentiations do not always exist. Selecting the right spectral scatterometry hardware, therefore, is a function of one"s application complexity and control objectives.

  5. Software for Managing Inventory of Flight Hardware

    NASA Technical Reports Server (NTRS)

    Salisbury, John; Savage, Scott; Thomas, Shirman

    2003-01-01

    The Flight Hardware Support Request System (FHSRS) is a computer program that relieves engineers at Marshall Space Flight Center (MSFC) of most of the non-engineering administrative burden of managing an inventory of flight hardware. The FHSRS can also be adapted to perform similar functions for other organizations. The FHSRS affords a combination of capabilities, including those formerly provided by three separate programs in purchasing, inventorying, and inspecting hardware. The FHSRS provides a Web-based interface with a server computer that supports a relational database of inventory; electronic routing of requests and approvals; and electronic documentation from initial request through implementation of quality criteria, acquisition, receipt, inspection, storage, and final issue of flight materials and components. The database lists both hardware acquired for current projects and residual hardware from previous projects. The increased visibility of residual flight components provided by the FHSRS has dramatically improved the re-utilization of materials in lieu of new procurements, resulting in a cost savings of over $1.7 million. The FHSRS includes subprograms for manipulating the data in the database, informing of the status of a request or an item of hardware, and searching the database on any physical or other technical characteristic of a component or material. The software structure forces normalization of the data to facilitate inquiries and searches for which users have entered mixed or inconsistent values.

  6. FHAST: FPGA-Based Acceleration of Bowtie in Hardware.

    PubMed

    Fernandez, Edward B; Villarreal, Jason; Lonardi, Stefano; Najjar, Walid A

    2015-01-01

    While the sequencing capability of modern instruments continues to increase exponentially, the computational problem of mapping short sequenced reads to a reference genome still constitutes a bottleneck in the analysis pipeline. A variety of mapping tools (e.g., Bowtie, BWA) is available for general-purpose computer architectures. These tools can take many hours or even days to deliver mapping results, depending on the number of input reads, the size of the reference genome and the number of allowed mismatches or insertion/deletions, making the mapping problem an ideal candidate for hardware acceleration. In this paper, we present FHAST (FPGA hardware accelerated sequence-matching tool), a drop-in replacement for Bowtie that uses a hardware design based on field programmable gate arrays (FPGA). Our architecture masks memory latency by executing multiple concurrent hardware threads accessing memory simultaneously. FHAST is composed by multiple parallel engines to exploit the parallelism available to us on an FPGA. We have implemented and tested FHAST on the Convey HC-1 and later ported on the Convey HC-2ex, taking advantage of the large memory bandwidth available to these systems and the shared memory image between hardware and software. A preliminary version of FHAST running on the Convey HC-1 achieved up to 70x speedup compared to Bowtie (single-threaded). An improved version of FHAST running on the Convey HC-2ex FPGAs achieved up to 12x fold speed gain compared to Bowtie running eight threads on an eight-core conventional architecture, while maintaining almost identical mapping accuracy. FHAST is a drop-in replacement for Bowtie, so it can be incorporated in any analysis pipeline that uses Bowtie (e.g., TopHat). PMID:26451812

  7. Digital Smile Design concept delineates the final potential result of crown lengthening and porcelain veneers to correct a gummy smile.

    PubMed

    Trushkowsky, Richard; Arias, David Montalvo; David, Steven

    2016-01-01

    Prior to initiating any treatment, it is necessary to visualize the desired outcomes. It then becomes possible to formulate the steps required to achieve this result. Digital Smile Design (DSD) utilizes patient input and information gathered through diagnostic procedures to create an esthetic treatment scheme. In the case presented here, the NYUCD Esthetic Evaluation Form, intraoral and extraoral photographs, mounted diagnostic casts, physical examination, and radiographs were the diagnostic modalities. The gathered information served as a starting point for a wax-up and intraoral mock-up. This case report demonstrates how the DSD served as a template for crown lengthening procedures and design of the final porcelain veneer restorations. PMID:27433549

  8. Considerations in Selecting Microcomputers for Instructional Design.

    ERIC Educational Resources Information Center

    Matthews, John I.

    1981-01-01

    Suggestions are made for choosing microcomputers for instructional design. Elements discussed include hardware (system components, selection procedures, operations and hardware); equipment suppliers; software development (database management, simulation); and implementation (acquisition of hardware, probable difficulties). (CT)

  9. Scaling Retro-Commissioning to Small Commercial Buildings: A Turnkey Automated Hardware-Software Solution

    SciTech Connect

    Lin, Guanjing; Granderson, J.; Brambley, Michael R.

    2015-07-01

    In the United States, small commercial buildings represent 51% of total floor space of all commercial buildings and consume nearly 3 quadrillion Btu (3.2 quintillion joule) of site energy annually, presenting an enormous opportunity for energy savings. Retro-commissioning (RCx), the process through which professional energy service providers identify and correct operational problems, has proven to be a cost-effective means to achieve median energy savings of 16%. However, retro-commissioning is not typically conducted at scale throughout the commercial stock. Very few small commercial buildings are retro-commissioned because utility expenses are relatively modest, margins are tighter, and capital for improvements is limited. In addition, small buildings do not have in-house staff with the expertise to identify improvement opportunities. In response, a turnkey hardware-software solution was developed to enable cost-effective, monitoring-based RCx of small commercial buildings. This highly tailored solution enables non-commissioning providers to identify energy and comfort problems, as well as associated cost impacts and remedies. It also facilitates scale by offering energy service providers the means to streamline their existing processes and reduce costs by more than half. The turnkey RCx sensor suitcase consists of two primary components: a suitcase of sensors for short-term building data collection that guides users through the process of deploying and retrieving their data and a software application that automates analysis of sensor data, identifies problems and generates recommendations. This paper presents the design and testing of prototype models, including descriptions of the hardware design, analysis algorithms, performance testing, and plans for dissemination.

  10. Onboard utilization of ground control points for image correction. Volume 3: Ground control point simulation software design

    NASA Technical Reports Server (NTRS)

    1981-01-01

    The software developed to simulate the ground control point navigation system is described. The Ground Control Point Simulation Program (GCPSIM) is designed as an analysis tool to predict the performance of the navigation system. The system consists of two star trackers, a global positioning system receiver, a gyro package, and a landmark tracker.

  11. 34 CFR 403.100 - What are the requirements for designating a State corrections educational agency to administer...

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... Education Regulations of the Offices of the Department of Education (Continued) OFFICE OF VOCATIONAL AND ADULT EDUCATION, DEPARTMENT OF EDUCATION STATE VOCATIONAL AND APPLIED TECHNOLOGY EDUCATION PROGRAM What... 34 Education 3 2010-07-01 2010-07-01 false What are the requirements for designating a...

  12. Introduction to co-simulation of software and hardware in embedded processor systems

    SciTech Connect

    Dreike, P.L.; McCoy, J.A.

    1996-09-01

    From the dawn of the first use of microprocessors and microcontrollers in embedded systems, the software has been blamed for products being late to market, This is due to software being developed after hardware is fabricated. During the past few years, the use of Hardware Description (or Design) Languages (HDLs) and digital simulation have advanced to a point where the concurrent development of software and hardware can be contemplated using simulation environments. This offers the potential of 50% or greater reductions in time-to-market for embedded systems. This paper is a tutorial on the technical issues that underlie software-hardware (swhw) co-simulation, and the current state of the art. We review the traditional sequential hardware-software design paradigm, and suggest a paradigm for concurrent design, which is supported by co-simulation of software and hardware. This is followed by sections on HDLs modeling and simulation;hardware assisted approaches to simulation; microprocessor modeling methods; brief descriptions of four commercial products for sw-hw co-simulation and a description of our own experiments to develop a co-simulation environment.

  13. VEG-01: Veggie Hardware Verification Testing

    NASA Technical Reports Server (NTRS)

    Massa, Gioia; Newsham, Gary; Hummerick, Mary; Morrow, Robert; Wheeler, Raymond

    2013-01-01

    The Veggie plant/vegetable production system is scheduled to fly on ISS at the end of2013. Since much of the technology associated with Veggie has not been previously tested in microgravity, a hardware validation flight was initiated. This test will allow data to be collected about Veggie hardware functionality on ISS, allow crew interactions to be vetted for future improvements, validate the ability of the hardware to grow and sustain plants, and collect data that will be helpful to future Veggie investigators as they develop their payloads. Additionally, food safety data on the lettuce plants grown will be collected to help support the development of a pathway for the crew to safely consume produce grown on orbit. Significant background research has been performed on the Veggie plant growth system, with early tests focusing on the development of the rooting pillow concept, and the selection of fertilizer, rooting medium and plant species. More recent testing has been conducted to integrate the pillow concept into the Veggie hardware and to ensure that adequate water is provided throughout the growth cycle. Seed sanitation protocols have been established for flight, and hardware sanitation between experiments has been studied. Methods for shipping and storage of rooting pillows and the development of crew procedures and crew training videos for plant activities on-orbit have been established. Science verification testing was conducted and lettuce plants were successfully grown in prototype Veggie hardware, microbial samples were taken, plant were harvested, frozen, stored and later analyzed for microbial growth, nutrients, and A TP levels. An additional verification test, prior to the final payload verification testing, is desired to demonstrate similar growth in the flight hardware and also to test a second set of pillows containing zinnia seeds. Issues with root mat water supply are being resolved, with final testing and flight scheduled for later in 2013.

  14. Symptomatic Hardware Removal After First Tarsometatarsal Arthrodesis.

    PubMed

    Peterson, Kyle S; McAlister, Jeffrey E; Hyer, Christopher F; Thompson, John

    2016-01-01

    Severe hallux valgus deformity with proximal instability creates pain and deformity in the forefoot. First tarsometatarsal joint arthrodesis is performed to reduce the intermetatarsal angle and stabilize the joint. Dorsomedial locking plate fixation with adjunctive lag screw fixation is used because of its superior construct strength and healing rate. Despite this, questions remain regarding whether this hardware is more prominent and more likely to need removal. The purpose of the present study was to determine the incidence of symptomatic hardware at the first tarsometatarsal joint and to determine the incidence of hardware removal resulting from prominence and/or discomfort. A review of 165 medical records of consecutive patients who had undergone first tarsometatarsal joint arthrodesis with plate fixation was conducted. The outcome of interest was the incidence of symptomatic hardware removal in patients with clinical union. The mean age was 55 (range 18.4 to 78.8) years. The mean follow-up duration was 65.9 ± 34.0 (range 7.0 to 369.0) weeks. In our cohort, 25 patients (15.2%) had undergone hardware removed because of pain and irritation. Of these patients, 18 (72.0%) had a locking plate and lag screw removed, and 7 (28.0%) had crossing lag screws removed. The fixation of a first tarsometatarsal joint fusion poses a difficult situation owing to minimal soft tissue coverage and the inherent need for robust fixation to promote fusion. Hardware can become prominent postoperatively and can become painful and/or induce cutaneous compromise. The results of the present observational investigation imply that surgeons can reasonably inform patients that the incidence of symptomatic hardware removal after first tarsometatarsal arthrodesis is approximately 15% within a median duration of 9.0 months after surgery. PMID:26215552

  15. Hardware simulator of Caliste-SO detectors for STIX instrument

    NASA Astrophysics Data System (ADS)

    Podgórski, P.; Ścisłowski, D.; Kowaliński, M.; Mrozek, T.; Steślicki, M.; Barylak, J.; Barylak, A.; Sylwester, J.; Krucker, S.; Hurford, G. J.; Arnold, N. G.; Orleański, P.; Meuris, A.; Limousin, O.; Gevin, O.; Grimm, O.; Etesi, L.; Hochmuth, N.; Battaglia, M.; Csillaghy, A.; Kienreich, I. W.; Veronig, A.; Bloomfield, D. Shaun; Byrne, M.; Massone, A. M.; Piana, M.; Giordano, S.; Skup, K. R.; Graczyk, R.; Michalska, M.; Nowosielski, W.; Cichocki, A.; Mosdorf, M.

    2013-10-01

    The Spectrometer Telescope for Imaging X-rays (STIX) is one of 10 instruments on-board Solar Orbiter mission of the European Space Agency (ESA) scheduled to be launched in 2017. STIX is aimed to provide imaging spectroscopy of solar thermal and non-thermal hard X-ray emissions from 4 keV to 150 keV using a Fourier-imaging technique. The instrument employs a set of tungsten grids in front of 32 pixelized CdTe detectors. These detectors are source of data collected and analyzed in real time by Instrument Data Processing Unit (IDPU). In order to support development and implementation of on-board algorithms a dedicated detector hardware simulator is designed and manufactured as a part of Electrical Ground Support Equipment (EGSE) for STIX instrument. Complementary to the hardware simulator is data analysis software which is used to generate input data and to analyze output data. The simulator will allow sending strictly defined data from all detectors' pixels at the input of the IDPU for further analysis of instrument response. Particular emphasis is given here to the simulator hardware design.

  16. Hardware demonstration of high-speed networks for satellite applications.

    SciTech Connect

    Donaldson, Jonathon W.; Lee, David S.

    2008-09-01

    This report documents the implementation results of a hardware demonstration utilizing the Serial RapidIO{trademark} and SpaceWire protocols that was funded by Sandia National Laboratories (SNL's) Laboratory Directed Research and Development (LDRD) office. This demonstration was one of the activities in the Modeling and Design of High-Speed Networks for Satellite Applications LDRD. This effort has demonstrated the transport of application layer packets across both RapidIO and SpaceWire networks to a common downlink destination using small topologies comprised of commercial-off-the-shelf and custom devices. The RapidFET and NEX-SRIO debug and verification tools were instrumental in the successful implementation of the RapidIO hardware demonstration. The SpaceWire hardware demonstration successfully demonstrated the transfer and routing of application data packets between multiple nodes and also was able reprogram remote nodes using configuration bitfiles transmitted over the network, a key feature proposed in node-based architectures (NBAs). Although a much larger network (at least 18 to 27 nodes) would be required to fully verify the design for use in a real-world application, this demonstration has shown that both RapidIO and SpaceWire are capable of routing application packets across a network to a common downlink node, illustrating their potential use in real-world NBAs.

  17. Overlapped checkpointing with hardware assist

    SciTech Connect

    Mitchell, Christopher J; Nunez, James A; Wang, Jun

    2009-01-01

    We present a new approach to handling the demanding I/O workload incurred during checkpoint writes encountered in High Performance Computing. Prior efforts to improve performance have been primarily bound by mechanical limitations of the hard drive. Our research surpasses this limitation by providing a method to: (1) write checkpoint data to a high-speed, non-volatile buffer, and (2) asynchronously write this data to permanent storage while resuming computation. This removes the hard drive from the critical data path because our I/O node based buffers isolate the compute nodes from the storage servers. This solution is feasible because of industry declines in cost for high-capacity, non-volatile storage technologies. Testing was conducted on a small-scale cluster to prove the design, and then scaled at Los Alamos National Laboratory. Results show a definitive speedup factor for select workloads over writing directly to a typical global parallel file system; the Panasas ActiveScale File System.

  18. Outline of a fast hardware implementation of Winograd's DFT algorithm

    NASA Technical Reports Server (NTRS)

    Zohar, S.

    1980-01-01

    The main characteristics of the discrete Fourier transform (DFT) algorithm considered by Winograd (1976) is a significant reduction in the number of multiplications. Its primary disadvantage is a higher structural complexity. It is, therefore, difficult to translate the reduced number of multiplications into faster execution of the DFT by means of a software implementation of the algorithm. For this reason, a hardware implementation is considered in the current study, taking into account a design based on the algorithm prescription discussed by Zohar (1979). The hardware implementation of a FORTRAN subroutine is proposed, giving attention to a pipelining scheme in which 5 consecutive data batches are being operated on simultaneously, each batch undergoing one of 5 processing phases.

  19. Object oriented hardware-software test bench for OMTF diagnosis

    NASA Astrophysics Data System (ADS)

    Drabik, Pawel; Pozniak, Krzysztof T.; Bunkowski, Karol; Zawistowski, Krystian; Byszuk, Adrian; Bluj, Michał; Doroba, Krzysztof; Górski, Maciej; Kalinowski, Artur; Kierzkowski, Krzysztof; Konecki, Marcin; Królikowski, Jan; Oklinski, Wojciech; Olszewski, Michał; Skala, Aleksander; Zabołotny, Wojciech M.

    2015-09-01

    In this paper the object oriented hardware-software model and its sample implementation of diagnostics for the Overlap Muon Track Finder trigger for the CMS experiment in CERN is described. It presents realization of test-bench for control and diagnosis class of multichannel, distributed measurement systems based on FPGA chips. The test-bench fulfills requirements for system's rapid changes, configurability and efficiency. This ability is very significant and desirable by expanded electronic systems. The solution described is a software model based on a method of address space management called the Component Internal Interface (CII). Establishment of stable link between hardware and software, as a purpose of designed and realized programming environment, is presented. The test-bench implementation and example of OMTF algorithm test is presented.

  20. Summary of multi-core hardware and programming model investigations

    SciTech Connect

    Kelly, Suzanne Marie; Pedretti, Kevin Thomas Tauke; Levenhagen, Michael J.

    2008-05-01

    This report summarizes our investigations into multi-core processors and programming models for parallel scientific applications. The motivation for this study was to better understand the landscape of multi-core hardware, future trends, and the implications on system software for capability supercomputers. The results of this study are being used as input into the design of a new open-source light-weight kernel operating system being targeted at future capability supercomputers made up of multi-core processors. A goal of this effort is to create an agile system that is able to adapt to and efficiently support whatever multi-core hardware and programming models gain acceptance by the community.

  1. Method Designed to Respect Molecular Heterogeneity Can Profoundly Correct Present Data Interpretations for Genome-Wide Expression Analysis

    PubMed Central

    Chen, Chih-Hao; Hsu, Chueh-Lin; Huang, Shih-Hao; Chen, Shih-Yuan; Hung, Yi-Lin; Chen, Hsiao-Rong; Wu, Yu-Chung

    2015-01-01

    Although genome-wide expression analysis has become a routine tool for gaining insight into molecular mechanisms, extraction of information remains a major challenge. It has been unclear why standard statistical methods, such as the t-test and ANOVA, often lead to low levels of reproducibility, how likely applying fold-change cutoffs to enhance reproducibility is to miss key signals, and how adversely using such methods has affected data interpretations. We broadly examined expression data to investigate the reproducibility problem and discovered that molecular heterogeneity, a biological property of genetically different samples, has been improperly handled by the statistical methods. Here we give a mathematical description of the discovery and report the development of a statistical method, named HTA, for better handling molecular heterogeneity. We broadly demonstrate the improved sensitivity and specificity of HTA over the conventional methods and show that using fold-change cutoffs has lost much information. We illustrate the especial usefulness of HTA for heterogeneous diseases, by applying it to existing data sets of schizophrenia, bipolar disorder and Parkinson’s disease, and show it can abundantly and reproducibly uncover disease signatures not previously detectable. Based on 156 biological data sets, we estimate that the methodological issue has affected over 96% of expression studies and that HTA can profoundly correct 86% of the affected data interpretations. The methodological advancement can better facilitate systems understandings of biological processes, render biological inferences that are more reliable than they have hitherto been and engender translational medical applications, such as identifying diagnostic biomarkers and drug prediction, which are more robust. PMID:25793610

  2. Low-power hardware implementation of movement decoding for brain computer interface with reduced-resolution discrete cosine transform.

    PubMed

    Minho Won; Albalawi, Hassan; Xin Li; Thomas, Donald E

    2014-01-01

    This paper describes a low-power hardware implementation for movement decoding of brain computer interface. Our proposed hardware design is facilitated by two novel ideas: (i) an efficient feature extraction method based on reduced-resolution discrete cosine transform (DCT), and (ii) a new hardware architecture of dual look-up table to perform discrete cosine transform without explicit multiplication. The proposed hardware implementation has been validated for movement decoding of electrocorticography (ECoG) signal by using a Xilinx FPGA Zynq-7000 board. It achieves more than 56× energy reduction over a reference design using band-pass filters for feature extraction. PMID:25570284

  3. Use of CCSDS Packets Over SpaceWire to Control Hardware

    NASA Technical Reports Server (NTRS)

    Haddad, Omar; Blau, Michael; Haghani, Noosha; Yuknis, William; Albaijes, Dennis

    2012-01-01

    For the Lunar Reconnaissance Orbiter, the Command and Data Handling subsystem consisted of several electronic hardware assemblies that were connected with SpaceWire serial links. Electronic hardware would be commanded/controlled and telemetry data was obtained using the SpaceWire links. Prior art focused on parallel data buses and other types of serial buses, which were not compatible with the SpaceWire and the core flight executive (CFE) software bus. This innovation applies to anything that utilizes both SpaceWire networks and the CFE software. The CCSDS (Consultative Committee for Space Data Systems) packet contains predetermined values in its payload fields that electronic hardware attached at the terminus of the SpaceWire node would decode, interpret, and execute. The hardware s interpretation of the packet data would enable the hardware to change its state/configuration (command) or generate status (telemetry). The primary purpose is to provide an interface that is compatible with the hardware and the CFE software bus. By specifying the format of the CCSDS packet, it is possible to specify how the resulting hardware is to be built (in terms of digital logic) that results in a hardware design that can be controlled by the CFE software bus in the final application

  4. Hardware Prototyping of Neural Network based Fetal Electrocardiogram Extraction

    NASA Astrophysics Data System (ADS)

    Hasan, M. A.; Reaz, M. B. I.

    2012-01-01

    The aim of this paper is to model the algorithm for Fetal ECG (FECG) extraction from composite abdominal ECG (AECG) using VHDL (Very High Speed Integrated Circuit Hardware Description Language) for FPGA (Field Programmable Gate Array) implementation. Artificial Neural Network that provides efficient and effective ways of separating FECG signal from composite AECG signal has been designed. The proposed method gives an accuracy of 93.7% for R-peak detection in FHR monitoring. The designed VHDL model is synthesized and fitted into Altera's Stratix II EP2S15F484C3 using the Quartus II version 8.0 Web Edition for FPGA implementation.

  5. Environmental Conditions for Space Flight Hardware: A Survey

    NASA Technical Reports Server (NTRS)

    Plante, Jeannette; Lee, Brandon

    2005-01-01

    Interest in generalization of the physical environment experienced by NASA hardware from the natural Earth environment (on the launch pad), man-made environment on Earth (storage acceptance an d qualification testing), the launch environment, and the space environment, is ed to find commonality among our hardware in an effort to reduce cost and complexity. NASA is entering a period of increase in its number of planetary missions and it is important to understand how our qualification requirements will evolve with and track these new environments. Environmental conditions are described for NASA projects in several ways for the different periods of the mission life cycle. At the beginning, the mission manager defines survivability requirements based on the mission length, orbit, launch date, launch vehicle, and other factors . such as the use of reactor engines. Margins are then applied to these values (temperature extremes, vibration extremes, radiation tolerances, etc,) and a new set of conditions is generalized for design requirements. Mission assurance documents will then assign an additional margin for reliability, and a third set of values is provided for during testing. A fourth set of environmental condition values may evolve intermittently from heritage hardware that has been tested to a level beyond the actual mission requirement. These various sets of environment figures can make it quite confusing and difficult to capture common hardware environmental requirements. Environmental requirement information can be found in a wide variety of places. The most obvious is with the individual projects. We can easily get answers to questions about temperature extremes being used and radiation tolerance goals, but it is more difficult to map the answers to the process that created these requirements: for design, for qualification, and for actual environment with no margin applied. Not everyone assigned to a NASA project may have that kind of insight, as many have

  6. Regolith simulant preparation methods for hardware testing

    NASA Astrophysics Data System (ADS)

    Gouache, Thibault P.; Brunskill, Christopher; Scott, Gregory P.; Gao, Yang; Coste, Pierre; Gourinat, Yves

    2010-12-01

    To qualify hardware for space flight, great care is taken to replicate the environment encountered in space. Emphasis is focused on presenting the hardware with the most extreme conditions it might encounter during its mission lifetime. The same care should be taken when regolith simulants are prepared to test space system performance. Indeed, the manner a granular material is prepared can have a very high influence on its mechanical properties and on the performance of the system interacting with it. Three regolith simulant preparation methods have been tested and are presented here (rain, pour, vibrate). They should enable researchers and hardware developers to test their prototypes in controlled and repeatable conditions. The pour and vibrate techniques are robust but only allow reaching a given relative density. The rain technique allows reaching a variety of relative densities but can be less robust if manually controlled.

  7. Multimode guidance project low frequency ECM simulator: Hardware description

    NASA Astrophysics Data System (ADS)

    Kaye, H. M.

    1982-10-01

    The Multimode Guidance(MMG) Project, part of the Army/Navy Area Defense SAM Technology Prototyping Program, was established to conduct a feasibility demonstration of multimode guidance concepts. Prototype guidance units for advanced, long range missiles are being built and tested under MMG Project sponsorship. The Johns Hopkins University Applied Physics Laboratory has been designated as Government Agent for countermeasures for this project. In support of this effort, a family of computer-controlled ECM simulators is being developed for validation of contractor's multimode guidance prototype designs. The design of the Low Frequency ECM Simulator is documented in two volumes. This report, Volume A, describes the hardware design of the simulator; Volume B describes the software design. This computer-controlled simulator can simulate up to six surveillance frequency jammers in B through F bands and will be used to evaluate the performance of home-on-jamming guidance modes in multiple jammer environments.

  8. No-hardware-signature cybersecurity-crypto-module: a resilient cyber defense agent

    NASA Astrophysics Data System (ADS)

    Zaghloul, A. R. M.; Zaghloul, Y. A.

    2014-06-01

    We present an optical cybersecurity-crypto-module as a resilient cyber defense agent. It has no hardware signature since it is bitstream reconfigurable, where single hardware architecture functions as any selected device of all possible ones of the same number of inputs. For a two-input digital device, a 4-digit bitstream of 0s and 1s determines which device, of a total of 16 devices, the hardware performs as. Accordingly, the hardware itself is not physically reconfigured, but its performance is. Such a defense agent allows the attack to take place, rendering it harmless. On the other hand, if the system is already infected with malware sending out information, the defense agent allows the information to go out, rendering it meaningless. The hardware architecture is immune to side attacks since such an attack would reveal information on the attack itself and not on the hardware. This cyber defense agent can be used to secure a point-to-point, point-to-multipoint, a whole network, and/or a single entity in the cyberspace. Therefore, ensuring trust between cyber resources. It can provide secure communication in an insecure network. We provide the hardware design and explain how it works. Scalability of the design is briefly discussed. (Protected by United States Patents No.: US 8,004,734; US 8,325,404; and other National Patents worldwide.)

  9. Which total knee replacement implant should I pick? Correcting the pathology: the role of knee bearing designs.

    PubMed

    Berend, K R; Lombardi, A V; Adams, J B

    2013-11-01

    Debate has raged over whether a cruciate retaining (CR) or a posterior stabilised (PS) total knee replacement (TKR) provides a better range of movement (ROM) for patients. Various sub-sets of CR design are frequently lumped together when comparing outcomes. Additionally, multiple factors have been proven to influence the rate of manipulation under anaesthetic (MUA) following TKR. The purpose of this study was to determine whether different CR bearing insert designs provide better ROM or different MUA rates. All primary TKRs performed by two surgeons between March 2006 and March 2009 were reviewed and 2449 CR-TKRs were identified. The same CR femoral component, instrumentation, and tibial base plate were consistently used. In 1334 TKRs a CR tibial insert with 3° posterior slope and no posterior lip was used (CR-S). In 803 there was an insert with no slope and a small posterior lip (CR-L) and in 312 knees the posterior cruciate ligament (PCL) was either resected or lax and a deep-dish, anterior stabilised insert was used (CR-AS). More CR-AS inserts were used in patients with less pre-operative ROM and greater pre-operative tibiofemoral deformity and flexion contracture (p < 0.05). The mean improvement in ROM was highest for the CR-AS inserts (5.9° (-40° to 55°) vs CR-S 3.1° (-45° to 70°) vs CR-L 3.0° (-45° to 65°); p = 0.004). There was a significantly higher MUA rate with the CR-S and CR-L inserts than CR-AS (Pearson rank 6.51; p = 0.04). Despite sacrificing or not substituting for the PCL, ROM improvement was highest, and the MUA rate was lowest in TKRs with a deep-dish, anterior-stabilised insert. Substitution for the posterior cruciate ligament (PCL) in the form of a PS design may not be necessary even when the PCL is deficient. PMID:24187370

  10. Pressure Sensor Calibration using VIPA Hardware

    SciTech Connect

    Suarez, Reynold; Heimbigner, Tom R.; Forrester, Joel B.; Hayes, James C.; Lidey, Lance S.

    2008-10-08

    The VIPA hardware uses a series of modules to control the system. One of the modules that the VIPA hardware uses is a 16-bit analog input module. The main purpose of this module is to read in a voltage. The inputs of these modules are connected directly to the voltage outputs of all the pressure sensors in the system. Because the sensors have different pressure and voltage output ranges, it is necessary to calibrate and scale the sensors so that the values make sense to the operator of the system.

  11. Management of a CFD organization in support of space hardware development

    NASA Technical Reports Server (NTRS)

    Schutzenhofer, L. A.; Mcconnaughey, P. K.; Mcconnaughey, H. V.; Wang, T. S.

    1991-01-01

    The management strategy of NASA-Marshall's CFD branch in support of space hardware development and code validation implements various elements of total quality management. The strategy encompasses (1) a teaming strategy which focuses on the most pertinent problem, (2) quick-turnaround analysis, (3) the evaluation of retrofittable design options through sensitivity analysis, and (4) coordination between the chief engineer and the hardware contractors. Advanced-technology concepts are being addressed via the definition of technology-development projects whose products are transferable to hardware programs and the integration of research activities with industry, government agencies, and universities, on the basis of the 'consortium' concept.

  12. Programming time-multiplexed reconfigurable hardware using a scalable neuromorphic compiler.

    PubMed

    Minkovich, Kirill; Srinivasa, Narayan; Cruz-Albrecht, Jose M; Cho, Youngkwan; Nogin, Aleksey

    2012-06-01

    Scalability and connectivity are two key challenges in designing neuromorphic hardware that can match biological levels. In this paper, we describe a neuromorphic system architecture design that addresses an approach to meet these challenges using traditional complementary metal-oxide-semiconductor (CMOS) hardware. A key requirement in realizing such neural architectures in hardware is the ability to automatically configure the hardware to emulate any neural architecture or model. The focus for this paper is to describe the details of such a programmable front-end. This programmable front-end is composed of a neuromorphic compiler and a digital memory, and is designed based on the concept of synaptic time-multiplexing (STM). The neuromorphic compiler automatically translates any given neural architecture to hardware switch states and these states are stored in digital memory to enable desired neural architectures. STM enables our proposed architecture to address scalability and connectivity using traditional CMOS hardware. We describe the details of the proposed design and the programmable front-end, and provide examples to illustrate its capabilities. We also provide perspectives for future extensions and potential applications. PMID:24806761

  13. Advances in metered dose inhaler technology: hardware development.

    PubMed

    Stein, Stephen W; Sheth, Poonam; Hodson, P David; Myrdal, Paul B

    2014-04-01

    Pressurized metered dose inhalers (MDIs) were first introduced in the 1950s and they are currently widely prescribed as portable systems to treat pulmonary conditions. MDIs consist of a formulation containing dissolved or suspended drug and hardware needed to contain the formulation and enable efficient and consistent dose delivery to the patient. The device hardware includes a canister that is appropriately sized to contain sufficient formulation for the required number of doses, a metering valve capable of delivering a consistent amount of drug with each dose delivered, an actuator mouthpiece that atomizes the formulation and serves as a conduit to deliver the aerosol to the patient, and often an indicating mechanism that provides information to the patient on the number of doses remaining. This review focuses on the current state-of-the-art of MDI hardware and includes discussion of enhancements made to the device's core subsystems. In addition, technologies that aid the correct use of MDIs will be discussed. These include spacers, valved holding chambers, and breath-actuated devices. Many of the improvements discussed in this article increase the ability of MDI systems to meet regulatory specifications. Innovations that enhance the functionality of MDIs continue to be balanced by the fact that a key advantage of MDI systems is their low cost per dose. The expansion of the health care market in developing countries and the increased focus on health care costs in many developed countries will ensure that MDIs remain a cost-effective crucial delivery system for treating pulmonary conditions for many years to come. PMID:24357110

  14. Weight and the Future of Space Flight Hardware Cost Modeling

    NASA Technical Reports Server (NTRS)

    Prince, Frank A.

    2003-01-01

    Weight has been used as the primary input variable for cost estimating almost as long as there have been parametric cost models. While there are good reasons for using weight, serious limitations exist. These limitations have been addressed by multi-variable equations and trend analysis in models such as NAFCOM, PRICE, and SEER; however, these models have not be able to address the significant time lags that can occur between the development of similar space flight hardware systems. These time lags make the cost analyst's job difficult because insufficient data exists to perform trend analysis, and the current set of parametric models are not well suited to accommodating process improvements in space flight hardware design, development, build and test. As a result, people of good faith can have serious disagreement over the cost for new systems. To address these shortcomings, new cost modeling approaches are needed. The most promising approach is process based (sometimes called activity) costing. Developing process based models will require a detailed understanding of the functions required to produce space flight hardware combined with innovative approaches to estimating the necessary resources. Particularly challenging will be the lack of data at the process level. One method for developing a model is to combine notional algorithms with a discrete event simulation and model changes to the total cost as perturbations to the program are introduced. Despite these challenges, the potential benefits are such that efforts should be focused on developing process based cost models.

  15. Hardware architecture for full analytical Fraunhofer computer-generated holograms

    NASA Astrophysics Data System (ADS)

    Pang, Zhi-Yong; Xu, Zong-Xi; Xiong, Yi; Chen, Biao; Dai, Hui-Min; Jiang, Shao-Ji; Dong, Jian-Wen

    2015-09-01

    Hardware architecture of parallel computation is proposed for generating Fraunhofer computer-generated holograms (CGHs). A pipeline-based integrated circuit architecture is realized by employing the modified Fraunhofer analytical formulism, which is large scale and enables all components to be concurrently operated. The architecture of the CGH contains five modules to calculate initial parameters of amplitude, amplitude compensation, phases, and phase compensation, respectively. The precalculator of amplitude is fully adopted considering the "reusable design" concept. Each complex operation type (such as square arithmetic) is reused only once by means of a multichannel selector. The implemented hardware calculates an 800×600 pixels hologram in parallel using 39,319 logic elements, 21,074 registers, and 12,651 memory bits in an Altera field-programmable gate array environment with stable operation at 50 MHz. Experimental results demonstrate that the quality of the images reconstructed from the hardware-generated hologram can be comparable to that of a software implementation. Moreover, the calculation speed is approximately 100 times faster than that of a personal computer with an Intel i5-3230M 2.6 GHz CPU for a triangular object.

  16. Using Innovative Technologies for Manufacturing and Evaluating Rocket Engine Hardware

    NASA Technical Reports Server (NTRS)

    Betts, Erin M.; Hardin, Andy

    2011-01-01

    Many of the manufacturing and evaluation techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As we enter into a new space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt new and innovative techniques for manufacturing and evaluating hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, manufacturing techniques such as Direct Metal Laser Sintering (DMLS) and white light scanning are being adopted and evaluated for their use on J-2X, with hopes of employing both technologies on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powdered metal manufacturing process in order to produce complex part geometries. The white light technique is a non-invasive method that can be used to inspect for geometric feature alignment. Both the DMLS manufacturing method and the white light scanning technique have proven to be viable options for manufacturing and evaluating rocket engine hardware, and further development and use of these techniques is recommended.

  17. Efficient Execution of Recursive Programs on Commodity Vector Hardware

    SciTech Connect

    Ren, Bin; Jo, Youngjoon; Krishnamoorthy, Sriram; Agrawal, Kunal; Kulkarni, Milind

    2015-06-13

    The pursuit of computational efficiency has led to the proliferation of throughput-oriented hardware, from GPUs to increasingly-wide vector units on commodity processors and accelerators. This hardware is designed to efficiently execute data-parallel computations in a vectorized manner. However, many algorithms are more naturally expressed as divide-and-conquer, recursive, task-parallel computations; in the absence of data parallelism, it seems that such algorithms are not well-suited to throughput-oriented architectures. This paper presents a set of novel code transformations that expose the data-parallelism latent in recursive, task-parallel programs. These transformations facilitate straightforward vectorization of task-parallel programs on commodity hardware. We also present scheduling policies that maintain high utilization of vector resources while limiting space usage. Across several task-parallel benchmarks, we demonstrate both efficient vector resource utilization and substantial speedup on chips using Intel's SSE4.2 vector units as well as accelerators using Intel's AVX512 units.

  18. High-performance reconfigurable hardware architecture for restricted Boltzmann machines.

    PubMed

    Ly, Daniel Le; Chow, Paul

    2010-11-01

    Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications has been limited. A primary cause for this lack of adoption is that neural networks are usually implemented as software running on general-purpose processors. Hence, a hardware implementation that can exploit the inherent parallelism in neural networks is desired. This paper investigates how the restricted Boltzmann machine (RBM), which is a popular type of neural network, can be mapped to a high-performance hardware architecture on field-programmable gate array (FPGA) platforms. The proposed modular framework is designed to reduce the time complexity of the computations through heavily customized hardware engines. A method to partition large RBMs into smaller congruent components is also presented, allowing the distribution of one RBM across multiple FPGA resources. The framework is tested on a platform of four Xilinx Virtex II-Pro XC2VP70 FPGAs running at 100 MHz through a variety of different configurations. The maximum performance was obtained by instantiating an RBM of 256 × 256 nodes distributed across four FPGAs, which resulted in a computational speed of 3.13 billion connection-updates-per-second and a speedup of 145-fold over an optimized C program running on a 2.8-GHz Intel processor. PMID:20858578

  19. Space Station Freedom biomedical monitoring and countermeasures: Biomedical facility hardware catalog

    NASA Technical Reports Server (NTRS)

    1990-01-01

    This hardware catalog covers that hardware proposed under the Biomedical Monitoring and Countermeasures Development Program supported by the Johnson Space Center. The hardware items are listed separately by item, and are in alphabetical order. Each hardware item specification consists of four pages. The first page describes background information with an illustration, definition and a history/design status. The second page identifies the general specifications, performance, rack interface requirements, problems, issues, concerns, physical description, and functional description. The level of hardware design reliability is also identified under the maintainability and reliability category. The third page specifies the mechanical design guidelines and assumptions. Described are the material types and weights, modules, and construction methods. Also described is an estimation of percentage of construction which utilizes a particular method, and the percentage of required new mechanical design is documented. The fourth page analyzes the electronics, the scope of design effort, and the software requirements. Electronics are described by percentages of component types and new design. The design effort, as well as, the software requirements are identified and categorized.

  20. Ocean Temperature and Humidity Sensor Design Based on SHT75 Module

    NASA Astrophysics Data System (ADS)

    Zhao, Jie; Yang, Li; Gai, Zhigang; Yang, Junxian; Yang, Ying

    SHT75 is a temperature and humidity module with high precision, low power consumption, two line output. An intelligent output temperature and humidity sensor is developed based on this module. The hardware and software design are introduced in detail in this paper. In addition, temperature and humidity correction parameters can be calculated by polynomial curve fitting. Experimental results show that the polynomial curve fitting after correction for temperature and humidity sensor can reach to more accurate measurement accuracy.

  1. Use of heat pipes in electronic hardware

    NASA Technical Reports Server (NTRS)

    Graves, J. R.

    1977-01-01

    A modular, multiple output power converter was developed in order to reduce costs of space hardware in future missions. The converter is of reduced size and weight, and utilizes advanced heat removal techniques, in the form of heat pipes which remove internally generated heat more effectively than conventional methods.

  2. Super Heavy-Duty Door Hardware.

    ERIC Educational Resources Information Center

    Fickes, Michael

    2000-01-01

    Discusses the new generation of durable school-door hardware and innovations that can resist everyday abuse. Concluding comments address cross-corridor door innovations that can help doorways more easily accommodate the passage of oversized items, and classroom door locking systems. (GR)

  3. Image Interpolation With Dedicated Digital Hardware

    NASA Technical Reports Server (NTRS)

    Hartenstein, R.; Wagner, G.; Simons, D.; Coulson, J.

    1986-01-01

    Algorithm for interpolating two-dimensional image data to change picture-element spacing implemented in dedicated digital hardware for high-speed execution. System interpolates 100 times as fast as generalpurpose computer. Image resampling occurs first along one image axis and then along other, using two interpolation devices implemented in series.

  4. Postflight hardware evaluation (RSRM-29, STS-54)

    NASA Technical Reports Server (NTRS)

    1993-01-01

    This document is the final report for the Clearfield disassembly evaluation and a continuation of the KSC postflight assessment for the RSRM-29 flight set. All observed hardware conditions were documented on PFOR's and are included in Appendices A, B, and C. Appendices D and E contain the measurements and safety factor data for the nozzle and insulation components. This report, along with the KSC Ten-Day Postflight Hardware Evaluation Report (TWR-64221), represents a summary of the RSRM-29 hardware evaluation. Disassembly evaluation photograph numbers are logged in TWA-1990. The RSRM-29 flight set disassembly evaluations described in this document were performed at the RSRM Refurbishment Facility in Clearfield, Utah. The final factory joint demate occurred on September 9, 1993. Detailed evaluations were performed in accordance with the Clearfield PEEP, TWR-50051, Revision A. All observations were compared against limits that are also defined in the PEEP. These limits outline the criteria for categorizing the observations as acceptable, reportable, or critical. Hardware conditions that were unexpected and/or determined to be reportable or critical were evaluated by the applicable CPT and tracked through the PFAR system.

  5. Postflight hardware evaluation (RSRM-29, STS-54)

    NASA Astrophysics Data System (ADS)

    1993-09-01

    This document is the final report for the Clearfield disassembly evaluation and a continuation of the KSC postflight assessment for the RSRM-29 flight set. All observed hardware conditions were documented on PFOR's and are included in Appendices A, B, and C. Appendices D and E contain the measurements and safety factor data for the nozzle and insulation components. This report, along with the KSC Ten-Day Postflight Hardware Evaluation Report (TWR-64221), represents a summary of the RSRM-29 hardware evaluation. Disassembly evaluation photograph numbers are logged in TWA-1990. The RSRM-29 flight set disassembly evaluations described in this document were performed at the RSRM Refurbishment Facility in Clearfield, Utah. The final factory joint demate occurred on September 9, 1993. Detailed evaluations were performed in accordance with the Clearfield PEEP, TWR-50051, Revision A. All observations were compared against limits that are also defined in the PEEP. These limits outline the criteria for categorizing the observations as acceptable, reportable, or critical. Hardware conditions that were unexpected and/or determined to be reportable or critical were evaluated by the applicable CPT and tracked through the PFAR system.

  6. Clinically-Relevant Design Features of a Three-Dimensional Correct Molar Crown and Related Maximum Principal Stress. A Finite Element Model Study

    PubMed Central

    Rafferty, Brian T.; Janal, Malvin N.; Zavanelli, Ricardo A.; Silva, Nelson R. F. A.; Rekow, E. Dianne; Thompson, Van P.; Coelho, Paulo G.

    2009-01-01

    Objective To evaluate the effects of clinically relevant variables on the maximum principal stress (MPS) in the veneer layer of an anatomically correct veneer-core-cement-tooth model. Methods The average dimensions of a mandibular first molar crown were imported into CAD software; a tooth preparation was modeled by reducing the proximal walls by 1.5 mm and the occlusal surface by 2.0 mm. ‘Crown systems’ were composed by varying characteristics of a cement layer, structural core, and veneer solid, all designed to fit the tooth preparation. The main and interacting effects of proximal wall height reduction, core material, core thickness, cement modulus, cement thickness, and load position on the maximum stress distribution were derived from a series of nite element models and analyzed in a factorial analysis of variance. Results The average MPS in the veneer layer over the 64 models was 488 MPa (range= 248 to 840 MPa). MPS increased significantly with the addition of horizontal load components and with increasing cement thickness. In addition, MPS levels varied as a function of interactions between: proximal wall height reduction and load position; load position and cement thickness; core thickness and cement thickness; cement thickness and proximal wall height reduction; and core thickness, cement thickness and proximal wall height reduction. Conclusion Rational design of veneered structural ceramics must consider the complex geometry of the crown-tooth system and integrate the in uence of both the main effects and interactions among design parameters. PMID:19857888

  7. Nonuniformity correction of a resistor array infrared scene projector

    NASA Astrophysics Data System (ADS)

    Olson, Eric M.; Murrer, Robert Lee, Jr.

    1999-07-01

    At the Kinetic-kill vehicle Hardware-in-the-Loop Simulator (KHILS) facility located at Eglin AFB, Florida, a technology has been developed for the projection of scenes to support hardware-in-the-loop testing of infrared seekers. The Wideband Infrared Scene Projector program is based on a 512 X 512 VLSI array of 2 mil pitch resistors. A characteristic associated with these projectors is each resistor emits measurably different in-band radiance when the same voltage is applied. Therefore, since it is desirable to have each resistor emit the same for a commanded radiance, each resistor requires a Non-Uniformity Correction (NUC). Though this NUC task may seem simple to a casual observer, it is, however, quite complicated. A high quality infrared camera and well-designed optical system are prerequisites to measuring each resistor's output accurately for correction. A technique for performing a NUC on a resistor array has been developed and implemented at KHILS that achieves a NUC (standard deviation output/mean output) of less than 1 percent. This paper presents details pertaining to the NUC system, procedures, and results.

  8. Hardware Implementation of Serially Concatenated PPM Decoder

    NASA Technical Reports Server (NTRS)

    Moision, Bruce; Hamkins, Jon; Barsoum, Maged; Cheng, Michael; Nakashima, Michael

    2009-01-01

    A prototype decoder for a serially concatenated pulse position modulation (SCPPM) code has been implemented in a field-programmable gate array (FPGA). At the time of this reporting, this is the first known hardware SCPPM decoder. The SCPPM coding scheme, conceived for free-space optical communications with both deep-space and terrestrial applications in mind, is an improvement of several dB over the conventional Reed-Solomon PPM scheme. The design of the FPGA SCPPM decoder is based on a turbo decoding algorithm that requires relatively low computational complexity while delivering error-rate performance within approximately 1 dB of channel capacity. The SCPPM encoder consists of an outer convolutional encoder, an interleaver, an accumulator, and an inner modulation encoder (more precisely, a mapping of bits to PPM symbols). Each code is describable by a trellis (a finite directed graph). The SCPPM decoder consists of an inner soft-in-soft-out (SISO) module, a de-interleaver, an outer SISO module, and an interleaver connected in a loop (see figure). Each SISO module applies the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm to compute a-posteriori bit log-likelihood ratios (LLRs) from apriori LLRs by traversing the code trellis in forward and backward directions. The SISO modules iteratively refine the LLRs by passing the estimates between one another much like the working of a turbine engine. Extrinsic information (the difference between the a-posteriori and a-priori LLRs) is exchanged rather than the a-posteriori LLRs to minimize undesired feedback. All computations are performed in the logarithmic domain, wherein multiplications are translated into additions, thereby reducing complexity and sensitivity to fixed-point implementation roundoff errors. To lower the required memory for storing channel likelihood data and the amounts of data transfer between the decoder and the receiver, one can discard the majority of channel likelihoods, using only the remainder in

  9. Cumulative Measurement Errors for Dynamic Testing of Space Flight Hardware

    NASA Technical Reports Server (NTRS)

    Winnitoy, Susan

    2012-01-01

    Located at the NASA Johnson Space Center in Houston, TX, the Six-Degree-of-Freedom Dynamic Test System (SDTS) is a real-time, six degree-of-freedom, short range motion base simulator originally designed to simulate the relative dynamics of two bodies in space mating together (i.e., docking or berthing). The SDTS has the capability to test full scale docking and berthing systems utilizing a two body dynamic docking simulation for docking operations and a Space Station Remote Manipulator System (SSRMS) simulation for berthing operations. The SDTS can also be used for nonmating applications such as sensors and instruments evaluations requiring proximity or short range motion operations. The motion base is a hydraulic powered Stewart platform, capable of supporting a 3,500 lb payload with a positional accuracy of 0.03 inches. The SDTS is currently being used for the NASA Docking System testing and has been also used by other government agencies. The SDTS is also under consideration for use by commercial companies. Examples of tests include the verification of on-orbit robotic inspection systems, space vehicle assembly procedures and docking/berthing systems. The facility integrates a dynamic simulation of on-orbit spacecraft mating or de-mating using flight-like mechanical interface hardware. A force moment sensor is used for input during the contact phase, thus simulating the contact dynamics. While the verification of flight hardware presents unique challenges, one particular area of interest involves the use of external measurement systems to ensure accurate feedback of dynamic contact. The measurement systems for the test facility have two separate functions. The first is to take static measurements of facility and test hardware to determine both the static and moving frames used in the simulation and control system. The test hardware must be measured after each configuration change to determine both sets of reference frames. The second function is to take dynamic

  10. Aircraft Reply and Interference Environment Simulator (ARIES) hardware principles of operation, volume 1

    NASA Astrophysics Data System (ADS)

    Mancus, Edward

    1989-10-01

    The Aircraft Reply and Interference Environment Simulator (ARIES) makes possible the performance assessment of the Mode Select (Mode S) sensor under its specific maximum aircraft load. To do this, ARIES operates upon disk files for traffic model and interference to generate simulated aircraft replies and fruit, feeding them to the sensor at radio frequency. Support documentation for ARIES consists of: (1) the ARIES Hardware Maintenance Manual: Volume 1 (DOT/FAA/CT-TN88/3); (2) Appendixes of the Hardware Maintenance Manual: Volume 2; (3) the ARIES Hardware Principles of Operation: Volume 1 (DOT/FAA/CT-TN88/4-1); (4) Appendixes of the Hardware Principles of Operation: Volume 2; (5) ARIES Software Principles of Operation (DOT/FAA/CT-TN87/16); and (6) ARIES Software User's Manual (DOT/FAA/CT-TN88/15). This document, the ARIES Hardware Principles of Operation, Volume 1, explains the theory of operation of the ARIES special purpose hardware designed and fabricated at the Federal Aviation Administration Technical Center. Each hardware device is discussed. Functional block diagrams, signal timing diagrams, and state timing diagrams are included where appropriate.

  11. Parallel Processing with Digital Signal Processing Hardware and Software

    NASA Technical Reports Server (NTRS)

    Swenson, Cory V.

    1995-01-01

    The assembling and testing of a parallel processing system is described which will allow a user to move a Digital Signal Processing (DSP) application from the design stage to the execution/analysis stage through the use of several software tools and hardware devices. The system will be used to demonstrate the feasibility of the Algorithm To Architecture Mapping Model (ATAMM) dataflow paradigm for static multiprocessor solutions of DSP applications. The individual components comprising the system are described followed by the installation procedure, research topics, and initial program development.

  12. Hardware proofs using EHDM and the RSRE verification methodology

    NASA Technical Reports Server (NTRS)

    Butler, Ricky W.; Sjogren, Jon A.

    1988-01-01

    Examined is a methodology for hardware verification developed by Royal Signals and Radar Establishment (RSRE) in the context of the SRI International's Enhanced Hierarchical Design Methodology (EHDM) specification/verification system. The methodology utilizes a four-level specification hierarchy with the following levels: functional level, finite automata model, block model, and circuit level. The properties of a level are proved as theorems in the level below it. This methodology is applied to a 6-bit counter problem and is critically examined. The specifications are written in EHDM's specification language, Extended Special, and the proofs are improving both the RSRE methodology and the EHDM system.

  13. Dynamic Stability Instrumentation System (DSIS). Volume 1: Hardware description

    NASA Technical Reports Server (NTRS)

    Jordan, T. L.; Daniels, T. S.; Hare, D. A.; Boyden, R. P.; Dress, D. A.

    1994-01-01

    This paper is a hardware description manual for the Dynamic Stability Instrumentation System that is used in specific NASA Langley wind tunnels. The instrumentation system performs either a synchronous demodulation or a fast Fourier transform on dynamic balance strain gage signals, and ultimately computes aerodynamic coefficients. The DSIS consists of a double rack of instruments, a remote motor-generator set, two special stings each with motor driven shafts, and specially designed balances. The major components in the instrumentation rack include a personal computer, digital signal processor microcomputers, computer-controlled signal conditioners, function generator, digital multimeter, and an optional fast Fourier transform analyzer.

  14. Jitter Correction

    NASA Technical Reports Server (NTRS)

    Waegell, Mordecai J.; Palacios, David M.

    2011-01-01

    Jitter_Correct.m is a MATLAB function that automatically measures and corrects inter-frame jitter in an image sequence to a user-specified precision. In addition, the algorithm dynamically adjusts the image sample size to increase the accuracy of the measurement. The Jitter_Correct.m function takes an image sequence with unknown frame-to-frame jitter and computes the translations of each frame (column and row, in pixels) relative to a chosen reference frame with sub-pixel accuracy. The translations are measured using a Cross Correlation Fourier transformation method in which the relative phase of the two transformed images is fit to a plane. The measured translations are then used to correct the inter-frame jitter of the image sequence. The function also dynamically expands the image sample size over which the cross-correlation is measured to increase the accuracy of the measurement. This increases the robustness of the measurement to variable magnitudes of inter-frame jitter

  15. Hardware-in-the-loop simulation and energy optimization of cardiac pacemakers.

    PubMed

    Barker, Chris; Kwiatkowska, Marta; Mereacre, Alexandru; Paoletti, Nicola; Patane, Andrea

    2015-08-01

    Implantable cardiac pacemakers are medical devices that can monitor and correct abnormal heart rhythms. To provide the necessary safety assurance for pacemaker software, both testing and verification of the code, as well as testing the entire pacemaker hardware in the loop, is necessary. In this paper, we present a hardware testbed that enables detailed hardware-in-the-loop simulation and energy optimisation of pacemaker algorithms with respect to a heart model. Both the heart and the pacemaker models are encoded in Simulink/Stateflow™ and translated into executable code, with the pacemaker executed directly on the microcontroller. We evaluate the usefulness of the testbed by developing a parameter synthesis algorithm which optimises the timing parameters based on power measurements acquired in real-time. The experiments performed on real measurements successfully demonstrate that the testbed is capable of energy minimisation in real-time and obtains safe pacemaker timing parameters. PMID:26737950

  16. The corrections for significant wave height and attitude effects in the TOPEX radar altimeter

    NASA Astrophysics Data System (ADS)

    Hayne, G. S.; Hancock, D. W.; Purdy, C. L.; Callahan, P. S.

    1994-12-01

    The routine ground processing of data from the NASA radar altimeter of TOPEX/POSEIDON includes instrument corrections for the effects of significant wave height and attitude angle changes on the altimeter's estimates of range, backscattered power, and significant wave height. This paper describes how these instrument corrections were generated and how they are applied. Detailed waveform fitting to telemetered waveform samples is use to assess the effectiveness of the corrections. There are several altimeter hardware-caused small waveform departures from the model waveforms and these departures, designated waveform 'features', are described in detailed. A consequence of the waveform features, and their positioning relationship to range rate, is that range data for ground tracks moving toward the equator may differ systematically by about a centimeter compared to range data for ground tracks moving away from the equator. The results and discussion are limited to side A of the redundant altimeter, as only side A has been operated on orbit.

  17. Hardware for a real-time multiprocessor simulator

    NASA Technical Reports Server (NTRS)

    Blech, R. A.; Arpasi, D. J.

    1984-01-01

    The hardware for a real time multiprocessor simulator (RTMPS) developed at the NASA Lewis Research Center is described. The RTMPS is a multiple microprocessor system used to investigate the application of parallel processing concepts to real time simulation. It is designed to provide flexible data exchange paths between processors by using off the shelf microcomputer boards and minimal customized interfacing. A dedicated operator interface allows easy setup of the simulator and quick interpreting of simulation data. Simulations for the RTMPS are coded in a NASA designed real time multiprocessor language (RTMPL). This language is high level and geared to the multiprocessor environment. A real time multiprocessor operating system (RTMPOS) has also been developed that provides a user friendly operator interface. The RTMPS and supporting software are currently operational and are being evaluated at Lewis. The results of this evaluation will be used to specify the design of an optimized parallel processing system for real time simulation of dynamic systems.

  18. Reconfigurable hardware for an augmented reality application

    NASA Astrophysics Data System (ADS)

    Toledo Moreo, F. Javier; Martinez Alvarez, J. Javier; Garrigos Guerrero, F. Javier; Ferrandez Vicente, J. Manuel

    2005-06-01

    An FPGA-based approach is proposed to build an augmented reality system in order to aid people affected by a visual disorder known as tunnel vision. The aim is to increase the user's knowledge of his environment by superimposing on his own view useful information obtained with image processing. Two different alternatives have been explored to perform the required image processing: a specific purpose algorithm to extract edge detection information, and a cellular neural network with the suitable template. Their implementations in reconfigurable hardware pursue to take advantage of the performance and flexibility that show modern FPGAs. This paper describes the hardware implementation of both the Canny algorithm and the cellular neural network, and the overall system architecture. Results of the implementations and examples of the system functionality are presented.

  19. An update on SCARLET hardware development and flight programs

    NASA Technical Reports Server (NTRS)

    Jones, P. Alan; Murphy, David M.; Piszczor, Michael F.; Allen, Douglas M.

    1995-01-01

    Solar Concentrator Array with Refractive Linear Element Technology (SCARLET) is one of the first practical photovoltaic concentrator array technologies that offers a number of benefits for space applications (i.e. high array efficiency, protection from space radiation effects, a relatively light weight system, minimized plasma interactions, etc.) The line-focus concentrator concept, however, also offers two very important advantages: (1) low-cost mass production potential of the lens material; and (2) relaxation of precise array tracking requirements to only a single axis. These benefits offer unique capabilities to both commercial and government spacecraft users, specifically those interested in high radiation missions, such as MEO orbits, and electric-powered propulsion LEO-to-GEO orbit raising applications. SCARLET is an aggressive hardware development and flight validation program sponsored by the Ballistic Missile Defense Organization (BMDO) and NASA Lewis Research Center. Its intent is to bring technology to the level of performance and validation necessary for use by various government and commercial programs. The first phase of the SCARLET program culminated with the design, development and fabrication of a small concentrator array for flight on the METEOR satellite. This hardware will be the first in-space demonstration of concentrator technology at the 'array level' and will provide valuable in-orbit performance measurements. The METEOR satellite is currently planned for a September/October 1995 launch. The next phase of the program is the development of large array for use by one of the NASA New Millenium Program missions. This hardware will incorporate a number of the significant improvements over the basic METEOR design. This presentation will address the basic SCARLET technology, examine its benefits to users, and describe the expected improvements for future missions.

  20. An update on SCARLET hardware development and flight programs

    SciTech Connect

    Jones, P.A.; Murphy, D.M.; Piszczor, M.F.; Allen, D.M. |

    1995-10-01

    Solar Concentrator Array with Refractive Linear Element Technology (SCARLET) is one of the first practical photovoltaic concentrator array technologies that offers a number of benefits for space applications (i.e. high array efficiency, protection from space radiation effects, a relatively light weight system, minimized plasma interactions, etc.) The line-focus concentrator concept, however, also offers two very important advantages: (1) low-cost mass production potential of the lens material; and (2) relaxation of precise array tracking requirements to only a single axis. These benefits offer unique capabilities to both commercial and government spacecraft users, specifically those interested in high radiation missions, such as MEO orbits, and electric-powered propulsion LEO-to-GEO orbit raising applications. SCARLET is an aggressive hardware development and flight validation program sponsored by the Ballistic Missile Defense Organization (BMDO) and NASA Lewis Research Center. Its intent is to bring technology to the level of performance and validation necessary for use by various government and commercial programs. The first phase of the SCARLET program culminated with the design, development and fabrication of a small concentrator array for flight on the METEOR satellite. This hardware will be the first in-space demonstration of concentrator technology at the `array level` and will provide valuable in-orbit performance measurements. The METEOR satellite is currently planned for a September/October 1995 launch. The next phase of the program is the development of large array for use by one of the NASA New Millenium Program missions. This hardware will incorporate a number of the significant improvements over the basic METEOR design. This presentation will address the basic SCARLET technology, examine its benefits to users, and describe the expected improvements for future missions.

  1. An update on SCARLET hardware development and flight programs

    NASA Astrophysics Data System (ADS)

    Jones, P. Alan; Murphy, David M.; Piszczor, Michael F.; Allen, Douglas M.

    1995-10-01

    Solar Concentrator Array with Refractive Linear Element Technology (SCARLET) is one of the first practical photovoltaic concentrator array technologies that offers a number of benefits for space applications (i.e. high array efficiency, protection from space radiation effects, a relatively light weight system, minimized plasma interactions, etc.) The line-focus concentrator concept, however, also offers two very important advantages: (1) low-cost mass production potential of the lens material; and (2) relaxation of precise array tracking requirements to only a single axis. These benefits offer unique capabilities to both commercial and government spacecraft users, specifically those interested in high radiation missions, such as MEO orbits, and electric-powered propulsion LEO-to-GEO orbit raising applications. SCARLET is an aggressive hardware development and flight validation program sponsored by the Ballistic Missile Defense Organization (BMDO) and NASA Lewis Research Center. Its intent is to bring technology to the level of performance and validation necessary for use by various government and commercial programs. The first phase of the SCARLET program culminated with the design, development and fabrication of a small concentrator array for flight on the METEOR satellite. This hardware will be the first in-space demonstration of concentrator technology at the 'array level' and will provide valuable in-orbit performance measurements. The METEOR satellite is currently planned for a September/October 1995 launch. The next phase of the program is the development of large array for use by one of the NASA New Millenium Program missions. This hardware will incorporate a number of the significant improvements over the basic METEOR design. This presentation will address the basic SCARLET technology, examine its benefits to users, and describe the expected improvements for future missions.

  2. A configurable-hardware document-similarity classifier to detect web attacks.

    SciTech Connect

    Ulmer, Craig D.; Gokhale, Maya

    2010-04-01

    This paper describes our approach to adapting a text document similarity classifier based on the Term Frequency Inverse Document Frequency (TFIDF) metric to reconfigurable hardware. The TFIDF classifier is used to detect web attacks in HTTP data. In our reconfigurable hardware approach, we design a streaming, real-time classifier by simplifying an existing sequential algorithm and manipulating the classifier's model to allow decision information to be represented compactly. We have developed a set of software tools to help automate the process of converting training data to synthesizable hardware and to provide a means of trading off between accuracy and resource utilization. The Xilinx Virtex 5-LX implementation requires two orders of magnitude less memory than the original algorithm. At 166MB/s (80X the software) the hardware implementation is able to achieve Gigabit network throughput at the same accuracy as the original algorithm.

  3. Open source hardware and software platform for robotics and artificial intelligence applications

    NASA Astrophysics Data System (ADS)

    Liang, S. Ng; Tan, K. O.; Lai Clement, T. H.; Ng, S. K.; Mohammed, A. H. Ali; Mailah, Musa; Azhar Yussof, Wan; Hamedon, Zamzuri; Yussof, Zulkifli

    2016-02-01

    Recent developments in open source hardware and software platforms (Android, Arduino, Linux, OpenCV etc.) have enabled rapid development of previously expensive and sophisticated system within a lower budget and flatter learning curves for developers. Using these platform, we designed and developed a Java-based 3D robotic simulation system, with graph database, which is integrated in online and offline modes with an Android-Arduino based rubbish picking remote control car. The combination of the open source hardware and software system created a flexible and expandable platform for further developments in the future, both in the software and hardware areas, in particular in combination with graph database for artificial intelligence, as well as more sophisticated hardware, such as legged or humanoid robots.

  4. Design and experimental testing of air slab caps which convert commercial electron diodes into dual purpose, correction-free diodes for small field dosimetry

    SciTech Connect

    Charles, P. H.; Cranmer-Sargison, G.; Thwaites, D. I.; Kairn, T.; Crowe, S. B.; Langton, C. M.; Trapp, J. V.; Pedrazzini, G.; Aland, T.; Kenny, J.

    2014-10-15

    Purpose: Two diodes which do not require correction factors for small field relative output measurements are designed and validated using experimental methodology. This was achieved by adding an air layer above the active volume of the diode detectors, which canceled out the increase in response of the diodes in small fields relative to standard field sizes. Methods: Due to the increased density of silicon and other components within a diode, additional electrons are created. In very small fields, a very small air gap acts as an effective filter of electrons with a high angle of incidence. The aim was to design a diode that balanced these perturbations to give a response similar to a water-only geometry. Three thicknesses of air were placed at the proximal end of a PTW 60017 electron diode (PTWe) using an adjustable “air cap”. A set of output ratios (OR{sub Det}{sup f{sub c}{sub l}{sub i}{sub n}}) for square field sizes of side length down to 5 mm was measured using each air thickness and compared to OR{sub Det}{sup f{sub c}{sub l}{sub i}{sub n}} measured using an IBA stereotactic field diode (SFD). k{sub Q{sub c{sub l{sub i{sub n,Q{sub m{sub s{sub r}{sup f{sub c}{sub l}{sub i}{sub n},f{sub m}{sub s}{sub r}}}}}}}}} was transferred from the SFD to the PTWe diode and plotted as a function of air gap thickness for each field size. This enabled the optimal air gap thickness to be obtained by observing which thickness of air was required such that k{sub Q{sub c{sub l{sub i{sub n,Q{sub m{sub s{sub r}{sup f{sub c}{sub l}{sub i}{sub n},f{sub m}{sub s}{sub r}}}}}}}}} was equal to 1.00 at all field sizes. A similar procedure was used to find the optimal air thickness required to make a modified Sun Nuclear EDGE detector (EDGEe) which is “correction-free” in small field relative dosimetry. In addition, the feasibility of experimentally transferring k{sub Q{sub c{sub l{sub i{sub n,Q{sub m{sub s{sub r}{sup f{sub c}{sub l}{sub i}{sub n},f{sub m}{sub s}{sub r

  5. Hardware-Independent Proofs of Numerical Programs

    NASA Technical Reports Server (NTRS)

    Boldo, Sylvie; Nguyen, Thi Minh Tuyen

    2010-01-01

    On recent architectures, a numerical program may give different answers depending on the execution hardware and the compilation. Our goal is to formally prove properties about numerical programs that are true for multiple architectures and compilers. We propose an approach that states the rounding error of each floating-point computation whatever the environment. This approach is implemented in the Frama-C platform for static analysis of C code. Small case studies using this approach are entirely and automatically proved

  6. Verifying Dissolution Of Wax From Hardware Surfaces

    NASA Technical Reports Server (NTRS)

    Montoya, Benjamina G.

    1995-01-01

    Wax removed by cleaning solvent revealed by cooling solution with liquid nitrogen. Such improved procedure and test needed in case of hardware that must be protected by wax during machining or plating but required to be free of wax during subsequent use. Improved cleaning procedure and test take less than 5 minutes. Does not require special skill or equipment and performs at cleaning site. In addition, enables recovery of all cleaning solvent.

  7. Testing Microshutter Arrays Using Commercial FPGA Hardware

    NASA Technical Reports Server (NTRS)

    Rapchun, David

    2008-01-01

    NASA is developing micro-shutter arrays for the Near Infrared Spectrometer (NIRSpec) instrument on the James Webb Space Telescope (JWST). These micro-shutter arrays allow NIRspec to do Multi Object Spectroscopy, a key part of the mission. Each array consists of 62414 individual 100 x 200 micron shutters. These shutters are magnetically opened and held electrostatically. Individual shutters are then programmatically closed using a simple row/column addressing technique. A common approach to provide these data/clock patterns is to use a Field Programmable Gate Array (FPGA). Such devices require complex VHSIC Hardware Description Language (VHDL) programming and custom electronic hardware. Due to JWST's rapid schedule on the development of the micro-shutters, rapid changes were required to the FPGA code to facilitate new approaches being discovered to optimize the array performance. Such rapid changes simply could not be made using conventional VHDL programming. Subsequently, National Instruments introduced an FPGA product that could be programmed through a Labview interface. Because Labview programming is considerably easier than VHDL programming, this method was adopted and brought success. The software/hardware allowed the rapid change the FPGA code and timely results of new micro-shutter array performance data. As a result, numerous labor hours and money to the project were conserved.

  8. Trends in computer hardware and software.

    PubMed

    Frankenfeld, F M

    1993-04-01

    Previously identified and current trends in the development of computer systems and in the use of computers for health care applications are reviewed. Trends identified in a 1982 article were increasing miniaturization and archival ability, increasing software costs, increasing software independence, user empowerment through new software technologies, shorter computer-system life cycles, and more rapid development and support of pharmaceutical services. Most of these trends continue today. Current trends in hardware and software include the increasing use of reduced instruction-set computing, migration to the UNIX operating system, the development of large software libraries, microprocessor-based smart terminals that allow remote validation of data, speech synthesis and recognition, application generators, fourth-generation languages, computer-aided software engineering, object-oriented technologies, and artificial intelligence. Current trends specific to pharmacy and hospitals are the withdrawal of vendors of hospital information systems from the pharmacy market, improved linkage of information systems within hospitals, and increased regulation by government. The computer industry and its products continue to undergo dynamic change. Software development continues to lag behind hardware, and its high cost is offsetting the savings provided by hardware. PMID:8470690

  9. "Greenbook Algorithms and Hardware Needs Analysis"

    SciTech Connect

    De Jong, Wibe A.; Oehmen, Chris S.; Baxter, Douglas J.

    2007-01-09

    "This document describes the algorithms, and hardware balance requirements needed to enable the solution of real scientific problems in the DOE core mission areas of environmental and subsurface chemistry, computational and systems biology, and climate science. The MSCF scientific drivers have been outlined in the Greenbook, which is available online at http://mscf.emsl.pnl.gov/docs/greenbook_for_web.pdf . Historically, the primary science driver has been the chemical and the molecular dynamics of the biological science area, whereas the remaining applications in the biological and environmental systems science areas have been occupying a smaller segment of the available hardware resources. To go from science drivers to hardware balance requirements, the major applications were identified. Major applications on the MSCF resources are low- to high-accuracy electronic structure methods, molecular dynamics, regional climate modeling, subsurface transport, and computational biology. The algorithms of these applications were analyzed to identify the computational kernels in both sequential and parallel execution. This analysis shows that a balanced architecture is needed with respect to processor speed, peak flop rate, peak integer operation rate, and memory hierarchy, interprocessor communication, and disk access and storage. A single architecture can satisfy the needs of all of the science areas, although some areas may take greater advantage of certain aspects of the architecture. "

  10. Quantum annealing correction with minor embedding

    NASA Astrophysics Data System (ADS)

    Vinci, Walter; Albash, Tameem; Paz-Silva, Gerardo; Hen, Itay; Lidar, Daniel A.

    2015-10-01

    Quantum annealing provides a promising route for the development of quantum optimization devices, but the usefulness of such devices will be limited in part by the range of implementable problems as dictated by hardware constraints. To overcome constraints imposed by restricted connectivity between qubits, a larger set of interactions can be approximated using minor embedding techniques whereby several physical qubits are used to represent a single logical qubit. However, minor embedding introduces new types of errors due to its approximate nature. We introduce and study quantum annealing correction schemes designed to improve the performance of quantum annealers in conjunction with minor embedding, thus leading to a hybrid scheme defined over an encoded graph. We argue that this scheme can be efficiently decoded using an energy minimization technique provided the density of errors does not exceed the per-site percolation threshold of the encoded graph. We test the hybrid scheme using a D-Wave Two processor on problems for which the encoded graph is a two-level grid and the Ising model is known to be NP-hard. The problems we consider are frustrated Ising model problem instances with "planted" (a priori known) solutions. Applied in conjunction with optimized energy penalties and decoding techniques, we find that this approach enables the quantum annealer to solve minor embedded instances with significantly higher success probability than it would without error correction. Our work demonstrates that quantum annealing correction can and should be used to improve the robustness of quantum annealing not only for natively embeddable problems but also when minor embedding is used to extend the connectivity of physical devices.

  11. Integrating reconfigurable hardware-based grid for high performance computing.

    PubMed

    Dondo Gazzano, Julio; Sanchez Molina, Francisco; Rincon, Fernando; López, Juan Carlos

    2015-01-01

    FPGAs have shown several characteristics that make them very attractive for high performance computing (HPC). The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use. However, there are still some difficulties when using reconfigurable platforms as accelerator that need to be addressed: the need of an in-depth application study to identify potential acceleration, the lack of tools for the deployment of computational problems in distributed hardware platforms, and the low portability of components, among others. This work proposes a complete grid infrastructure for distributed high performance computing based on dynamically reconfigurable FPGAs. Besides, a set of services designed to facilitate the application deployment is described. An example application and a comparison with other hardware and software implementations are shown. Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process. PMID:25874241

  12. The Unified Floating Point Vector Coprocessor for Reconfigurable Hardware

    NASA Astrophysics Data System (ADS)

    Kathiara, Jainik

    There has been an increased interest recently in using embedded cores on FPGAs. Many of the applications that make use of these cores have floating point operations. Due to the complexity and expense of floating point hardware, these algorithms are usually converted to fixed point operations or implemented using floating-point emulation in software. As the technology advances, more and more homogeneous computational resources and fixed function embedded blocks are added to FPGAs and hence implementation of floating point hardware becomes a feasible option. In this research we have implemented a high performance, autonomous floating point vector Coprocessor (FPVC) that works independently within an embedded processor system. We have presented a unified approach to vector and scalar computation, using a single register file for both scalar operands and vector elements. The Hybrid vector/SIMD computational model of FPVC results in greater overall performance for most applications along with improved peak performance compared to other approaches. By parameterizing vector length and the number of vector lanes, we can design an application specific FPVC and take optimal advantage of the FPGA fabric. For this research we have also initiated designing a software library for various computational kernels, each of which adapts FPVC's configuration and provide maximal performance. The kernels implemented are from the area of linear algebra and include matrix multiplication and QR and Cholesky decomposition. We have demonstrated the operation of FPVC on a Xilinx Virtex 5 using the embedded PowerPC.

  13. Integrating Reconfigurable Hardware-Based Grid for High Performance Computing

    PubMed Central

    Dondo Gazzano, Julio; Sanchez Molina, Francisco; Rincon, Fernando; López, Juan Carlos

    2015-01-01

    FPGAs have shown several characteristics that make them very attractive for high performance computing (HPC). The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use. However, there are still some difficulties when using reconfigurable platforms as accelerator that need to be addressed: the need of an in-depth application study to identify potential acceleration, the lack of tools for the deployment of computational problems in distributed hardware platforms, and the low portability of components, among others. This work proposes a complete grid infrastructure for distributed high performance computing based on dynamically reconfigurable FPGAs. Besides, a set of services designed to facilitate the application deployment is described. An example application and a comparison with other hardware and software implementations are shown. Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process. PMID:25874241

  14. A hardware overview of the RHIC LLRF platform

    SciTech Connect

    Hayes, T.; Smith, K.S.

    2011-03-28

    The RHIC Low Level RF (LLRF) platform is a flexible, modular system designed around a carrier board with six XMC daughter sites. The carrier board features a Xilinx FPGA with an embedded, hard core Power PC that is remotely reconfigurable. It serves as a front end computer (FEC) that interfaces with the RHIC control system. The carrier provides high speed serial data paths to each daughter site and between daughter sites as well as four generic external fiber optic links. It also distributes low noise clocks and serial data links to all daughter sites and monitors temperature, voltage and current. To date, two XMC cards have been designed: a four channel high speed ADC and a four channel high speed DAC. The new LLRF hardware was used to replace the old RHIC LLRF system for the 2009 run. For the 2010 run, the RHIC RF system operation was dramatically changed with the introduction of accelerating both beams in a new, common cavity instead of each ring having independent cavities. The flexibility of the new system was beneficial in allowing the low level system to be adapted to support this new configuration. This hardware was also used in 2009 to provide LLRF for the newly commissioned Electron Beam Ion Source.

  15. Optimized hardware and software for fast full-chip simulation

    NASA Astrophysics Data System (ADS)

    Cao, Yu; Lu, Yen-Wen; Chen, Luoqi; Ye, Jun

    2005-05-01

    Lithography simulation is an increasingly important part of semiconductor manufacturing due to the decreasing k1 value. It is not only required in lithography process development, but also in RET design, RET verification, and process latitude analysis, from library cells to full-chip. As the design complexity grows exponentially, pure software based simulation tools running on general-purpose computer clusters are facing increasing challenges in meeting today"s requirements for cycle time, coverage, and modeling accuracy. We have developed a new lithography simulation platform (TachyonTM) which achieves orders of magnitude speedup as compared to traditional pure software simulation tools. The platform combines innovations in all levels of the system: algorithm, software architecture, cluster-level architecture, and proprietary acceleration hardware using application specific integrated circuits. The algorithm approach is based on image processing, fundamentally different from conventional edge-based analysis. The system achieves superior model accuracy than conventional full-chip simulation methods, owing to its ability to handle hundreds of TCC kernels, using either vector or scalar optical model, without impacting throughput. Thus first-principle aerial image simulation at the full-chip level can be carried out within minutes. We will describe the hardware, algorithms and models used in the system and demonstrate its applications of the full chip verification purposes.

  16. Ground target infrared signature model validation for real-time hardware-in-the-loop simulations

    NASA Astrophysics Data System (ADS)

    Sanders, Jeffrey S.; Rodgers, Jeremy B.; Siddique, Ahmed A.

    1998-07-01

    Techniques and tools for validation of real-time infrared target signature models are presented. The model validation techniques presented in this paper were developed for hardware-in-the-loop (HWIL) simulations at the U.S. Army Missile Command's Research, Development, and Engineering Center. Real-time target model validation is a required deliverable to the customer of a HWIL simulation facility and is a critical part of ensuring the fidelity of a HWIL simulation. There are two levels of real-time target model validation. The first level is comparison of the target model to some baseline or measured data which answers the question 'are the simulation inputs correct?' The second level of validation is a simulation validation which answers the question 'for a given target model input are the simulation hardware and software generating the correct output?' This paper deals primarily with the first level of target model validation.

  17. Real-Time Hardware-in-the-Loop Simulation of Ares I Launch Vehicle

    NASA Technical Reports Server (NTRS)

    Tobbe, Patrick; Matras, Alex; Walker, David; Wilson, Heath; Fulton, Chris; Alday, Nathan; Betts, Kevin; Hughes, Ryan; Turbe, Michael

    2009-01-01

    The Ares Real-Time Environment for Modeling, Integration, and Simulation (ARTEMIS) has been developed for use by the Ares I launch vehicle System Integration Laboratory at the Marshall Space Flight Center. The primary purpose of the Ares System Integration Laboratory is to test the vehicle avionics hardware and software in a hardware - in-the-loop environment to certify that the integrated system is prepared for flight. ARTEMIS has been designed to be the real-time simulation backbone to stimulate all required Ares components for verification testing. ARTE_VIIS provides high -fidelity dynamics, actuator, and sensor models to simulate an accurate flight trajectory in order to ensure realistic test conditions. ARTEMIS has been designed to take advantage of the advances in underlying computational power now available to support hardware-in-the-loop testing to achieve real-time simulation with unprecedented model fidelity. A modular realtime design relying on a fully distributed computing architecture has been implemented.

  18. Hardware Implementation of a Bilateral Subtraction Filter

    NASA Technical Reports Server (NTRS)

    Huertas, Andres; Watson, Robert; Villalpando, Carlos; Goldberg, Steven

    2009-01-01

    A bilateral subtraction filter has been implemented as a hardware module in the form of a field-programmable gate array (FPGA). In general, a bilateral subtraction filter is a key subsystem of a high-quality stereoscopic machine vision system that utilizes images that are large and/or dense. Bilateral subtraction filters have been implemented in software on general-purpose computers, but the processing speeds attainable in this way even on computers containing the fastest processors are insufficient for real-time applications. The present FPGA bilateral subtraction filter is intended to accelerate processing to real-time speed and to be a prototype of a link in a stereoscopic-machine- vision processing chain, now under development, that would process large and/or dense images in real time and would be implemented in an FPGA. In terms that are necessarily oversimplified for the sake of brevity, a bilateral subtraction filter is a smoothing, edge-preserving filter for suppressing low-frequency noise. The filter operation amounts to replacing the value for each pixel with a weighted average of the values of that pixel and the neighboring pixels in a predefined neighborhood or window (e.g., a 9 9 window). The filter weights depend partly on pixel values and partly on the window size. The present FPGA implementation of a bilateral subtraction filter utilizes a 9 9 window. This implementation was designed to take advantage of the ability to do many of the component computations in parallel pipelines to enable processing of image data at the rate at which they are generated. The filter can be considered to be divided into the following parts (see figure): a) An image pixel pipeline with a 9 9- pixel window generator, b) An array of processing elements; c) An adder tree; d) A smoothing-and-delaying unit; and e) A subtraction unit. After each 9 9 window is created, the affected pixel data are fed to the processing elements. Each processing element is fed the pixel value for

  19. Ultra-low noise miniaturized neural amplifier with hardware averaging

    NASA Astrophysics Data System (ADS)

    Dweiri, Yazan M.; Eggers, Thomas; McCallum, Grant; Durand, Dominique M.

    2015-08-01

    Objective. Peripheral nerves carry neural signals that could be used to control hybrid bionic systems. Cuff electrodes provide a robust and stable interface but the recorded signal amplitude is small (<3 μVrms 700 Hz-7 kHz), thereby requiring a baseline noise of less than 1 μVrms for a useful signal-to-noise ratio (SNR). Flat interface nerve electrode (FINE) contacts alone generate thermal noise of at least 0.5 μVrms therefore the amplifier should add as little noise as possible. Since mainstream neural amplifiers have a baseline noise of 2 μVrms or higher, novel designs are required. Approach. Here we apply the concept of hardware averaging to nerve recordings obtained with cuff electrodes. An optimization procedure is developed to minimize noise and power simultaneously. The novel design was based on existing neural amplifiers (Intan Technologies, LLC) and is validated with signals obtained from the FINE in chronic dog experiments. Main results. We showed that hardware averaging leads to a reduction in the total recording noise by a factor of 1/√N or less depending on the source resistance. Chronic recording of physiological activity with FINE using the presented design showed significant improvement on the recorded baseline noise with at least two parallel operation transconductance amplifiers leading to a 46.1% reduction at N = 8. The functionality of these recordings was quantified by the SNR improvement and shown to be significant for N = 3 or more. The present design was shown to be capable of generating <1.5 μVrms total recording baseline noise when connected to a FINE placed on the sciatic nerve of an awake animal. An algorithm was introduced to find the value of N that can minimize both the power consumption and the noise in order to design a miniaturized ultralow-noise neural amplifier. Significance. These results demonstrate the efficacy of hardware averaging on noise improvement for neural recording with cuff electrodes, and can accommodate the

  20. Pre-Hardware Optimization of Spacecraft Image Processing Software Algorithms and Hardware Implementation

    NASA Technical Reports Server (NTRS)

    Kizhner, Semion; Flatley, Thomas P.; Hestnes, Phyllis; Jentoft-Nilsen, Marit; Petrick, David J.; Day, John H. (Technical Monitor)

    2001-01-01

    Spacecraft telemetry rates have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image processing application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms and re-configurable computing hardware technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processing (DSP). It has been shown in [1] and [2] that this configuration can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft. However, since this technology is still maturing, intensive pre-hardware steps are necessary to achieve the benefits of hardware implementation. This paper describes these steps for the GOES-8 application, a software project developed using Interactive Data Language (IDL) (Trademark of Research Systems, Inc.) on a Workstation/UNIX platform. The solution involves converting the application to a PC/Windows/RC platform, selected mainly by the availability of low cost, adaptable high-speed RC hardware. In order for the hybrid system to run, the IDL software was modified to account for platform differences. It was interesting to examine the gains and losses in performance on the new platform, as well as unexpected observations before implementing hardware. After substantial pre-hardware optimization steps, the necessity of hardware implementation for bottleneck code in the PC environment became evident and solvable beginning with the methodology described in [1], [2], and implementing a novel methodology for this specific application [6]. The PC-RC interface bandwidth problem for the