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Sample records for correct hardware design

  1. A hardware implementation of a provably correct design of a fault-tolerant clock synchronization circuit

    NASA Technical Reports Server (NTRS)

    Torres-Pomales, Wilfredo

    1993-01-01

    A fault-tolerant clock synchronization system was designed to a proven correct formal specification. Formal methods were used in the development of this specification. A description of the system and an analysis of the tests performed are presented. Plots of typical experimental results are included.

  2. Design of an IRFPA nonuniformity correction algorithm to be implemented as a real-time hardware prototype

    NASA Astrophysics Data System (ADS)

    Fenner, Jonathan W.; Simon, Solomon H.; Eden, Dayton D.

    1994-07-01

    As new IR focal plane array (IRFPA) technologies become available, improved methods for coping with array errors must be developed. Traditional methods of nonuniformity correction using simple calibration mode are not adequate to compensate for the inherent nonuniformity and 1/f noise in some arrays. In an effort to compensate for nonuniformity in a HgCdTe IRFPA, and to reduce the effects of 1/f noise over a time interval, a new dynamic neural network (NN) based algorithm was implemented. The algorithm compensates for nonuniformities, and corrects for 1/f noise. A gradient descent algorithm is used with nearest neighbor feedback for training, creating a dynamic model of the IRFPA's gains and offsets, then updating and correcting them continuously. Improvements to the NN include implementation on a IBM 486 computer system, and a close examination of simulated scenes to test the algorithms boundaries. Preliminary designs for a real-time hardware prototype have been developed as well. Simulations were implemented to test the algorithm's ability to correct under a variety of conditions. A wide range of background noise, 1/f noise, object intensities, and background intensities were used. Results indicate that this algorithm can correct efficiently down to the background noise. Our conclusions are that NN based adaptive algorithms will supplement the effectiveness of IRFPA's.

  3. Resampling in hyperspectral cameras as an alternative to correcting keystone in hardware, with focus on benefits for optical design and data quality

    NASA Astrophysics Data System (ADS)

    Fridman, Andrei; Høye, Gudrun; Løke, Trond

    2014-05-01

    Current high-resolution hyperspectral cameras attempt to correct misregistration errors in hardware. This severely limits other specifications of the hyperspectral camera, such as spatial resolution and light gathering capacity. If resampling is used to correct keystone in software instead of in hardware, then these stringent requirements could be lifted. Preliminary designs show that a resampling camera should be able to resolve at least 3000-5000 pixels, while at the same time collecting up to four times more light than the majority of current high spatial resolution cameras. A virtual camera software, specifically developed for this purpose, was used to compare the performance of resampling and hardware corrected cameras. Different criteria are suggested for quantifying the camera performance. The simulations showed that the performance of a resampling camera is comparable to that of a hardware corrected camera with 0.1 pixel residual keystone, and that the use of a more advanced resampling method than the commonly used linear interpolation, such as high-resolution cubic splines, is highly beneficial for the data quality of the resampled image. Our findings suggest that if high-resolution sensors are available, it would be better to use resampling instead of trying to correct keystone in hardware.

  4. Resampling in hyperspectral cameras as an alternative to correcting keystone in hardware, with focus on benefits for the optical design and data quality

    NASA Astrophysics Data System (ADS)

    Fridman, Andrei; Høye, Gudrun; Løke, Trond

    2013-06-01

    Current high-resolution hyperspectral cameras attempt to correct misregistration errors in hardware. Usually, it is required that aberrations in the optical system must be controlled with precision 0.1 pixel or smaller. This severely limits other specifications of the hyperspectral camera, such as spatial resolution and light gathering capacity, and often requires very tight tolerances. If resampling is used to correct keystone in software instead of in hardware, then these stringent requirements could be lifted. Preliminary designs show that a resampling camera should be able to resolve at least 3000-5000 pixels, while at the same time collecting up to four times more light than the majority of current high spatial resolution cameras that correct keystone in hardware (HW corrected cameras). A Virtual Camera software, specifically developed for this purpose, was used to compare the performance of resampling cameras and HW corrected cameras. For the cameras where a large keystone is corrected by resampling, different resampling methods are investigated. Different criteria are suggested for quantifying performance, and the tested cameras are compared according to these criteria. The simulations showed that the performance of a resampling camera is comparable to that of a HW corrected camera with 0.1 pixel residual keystone, and that the use of a more advanced resampling method than the commonly used linear interpolation - such as for instance high-resolution cubic splines - is highly beneficial for the data quality of the resampled image. Our findings suggest that if high-resolution sensors are available, it would be better to use resampling instead of trying to correct keystone in hardware.

  5. Correctness properties for iterated hardware structures

    NASA Technical Reports Server (NTRS)

    Windley, Phillip J.

    1993-01-01

    Iterated structures occur frequently in hardware. This paper describes properties required of mathematical relations that can be implemented iteratively and demonstrates the use of these properties on a generalized class of adders. This work provides a theoretical basis for the correct synthesis of iterated arithmetic structures.

  6. Fundamental Hardware Design in PVS

    NASA Technical Reports Server (NTRS)

    Leathrum, James F., Jr.

    1997-01-01

    The development of Programmable Logic Devices (PLDs) has introduced programming as a primary tool in the development of digital circuits. This work attempts to create a generic verification environment in which designs can be specified and verified using the Prototype Verification System (PVS). This is accomplished by providing library support for general hardware constructs. The environment is intended for use with any PLD and any PLD programming language. The goal of the environment is to allow the easy translation of digital designs to PVS and provide sufficient support to make verification possible without a great deal of effort.

  7. X-15 Hardware Design Challenges

    NASA Technical Reports Server (NTRS)

    Storms, Harrison A., Jr.

    1991-01-01

    Historical events in the development of the X-15 hardware design are presented. Some of the topics covered include: (1) drivers that led to the development of the X-15; (2) X-15 space research objectives; (3) original performance targets; (4) the X-15 typical mission; (5) X-15 dimensions and weight; (5) the propulsion system; (6) X-15 development milestones; (7) engineering and manufacturing challenges; (8) the X-15 structure; (9) ballistic flight control; (10) landing gear; (11) nose gear; and (12) an X-15 program recap.

  8. Comparative Modal Analysis of Sieve Hardware Designs

    NASA Technical Reports Server (NTRS)

    Thompson, Nathaniel

    2012-01-01

    The CMTB Thwacker hardware operates as a testbed analogue for the Flight Thwacker and Sieve components of CHIMRA, a device on the Curiosity Rover. The sieve separates particles with a diameter smaller than 150 microns for delivery to onboard science instruments. The sieving behavior of the testbed hardware should be similar to the Flight hardware for the results to be meaningful. The elastodynamic behavior of both sieves was studied analytically using the Rayleigh Ritz method in conjunction with classical plate theory. Finite element models were used to determine the mode shapes of both designs, and comparisons between the natural frequencies and mode shapes were made. The analysis predicts that the performance of the CMTB Thwacker will closely resemble the performance of the Flight Thwacker within the expected steady state operating regime. Excitations of the testbed hardware that will mimic the flight hardware were recommended, as were those that will improve the efficiency of the sieving process.

  9. Hardware

    NASA Technical Reports Server (NTRS)

    1999-01-01

    The full complement of EDOMP investigations called for a broad spectrum of flight hardware ranging from commercial items, modified for spaceflight, to custom designed hardware made to meet the unique requirements of testing in the space environment. In addition, baseline data collection before and after spaceflight required numerous items of ground-based hardware. Two basic categories of ground-based hardware were used in EDOMP testing before and after flight: (1) hardware used for medical baseline testing and analysis, and (2) flight-like hardware used both for astronaut training and medical testing. To ensure post-landing data collection, hardware was required at both the Kennedy Space Center (KSC) and the Dryden Flight Research Center (DFRC) landing sites. Items that were very large or sensitive to the rigors of shipping were housed permanently at the landing site test facilities. Therefore, multiple sets of hardware were required to adequately support the prime and backup landing sites plus the Johnson Space Center (JSC) laboratories. Development of flight hardware was a major element of the EDOMP. The challenges included obtaining or developing equipment that met the following criteria: (1) compact (small size and light weight), (2) battery-operated or requiring minimal spacecraft power, (3) sturdy enough to survive the rigors of spaceflight, (4) quiet enough to pass acoustics limitations, (5) shielded and filtered adequately to assure electromagnetic compatibility with spacecraft systems, (6) user-friendly in a microgravity environment, and (7) accurate and efficient operation to meet medical investigative requirements.

  10. Space hardware designs, volume 1

    NASA Technical Reports Server (NTRS)

    Meyer, Rudolf X.; Cribbs, Richard; Honda, Mark; Ma, Christina; Robson, Christopher

    1994-01-01

    The design of a solar sail space vehicle with a novel sail deployment mechanism is described. The sail is triangular in shape and is deployed and stabilized by three miniature spacecraft, one at each corner of the triangle. A concept demonstrator for a spherical microrover for the exploration of a planetary surface is described. Lastly, laboratory experiments have been conducted to study the migration of thin oil films on metal surfaces in the presence of a thermal gradient.

  11. Digital Hardware Design Teaching: An Alternative Approach

    ERIC Educational Resources Information Center

    Benkrid, Khaled; Clayton, Thomas

    2012-01-01

    This article presents the design and implementation of a complete review of undergraduate digital hardware design teaching in the School of Engineering at the University of Edinburgh. Four guiding principles have been used in this exercise: learning-outcome driven teaching, deep learning, affordability, and flexibility. This has identified…

  12. Design considerations for space flight hardware

    NASA Technical Reports Server (NTRS)

    Glover, Daniel

    1990-01-01

    The environmental and design constraints are reviewed along with some insight into the established design and quality assurance practices that apply to low earth orbit (LEO) space flight hardware. It is intended as an introduction for people unfamiliar with space flight considerations. Some basic data and a bibliography are included.

  13. Shuttle mission simulator hardware conceptual design report

    NASA Technical Reports Server (NTRS)

    Burke, J. F.

    1973-01-01

    The detailed shuttle mission simulator hardware requirements are discussed. The conceptual design methods, or existing technology, whereby those requirements will be fulfilled are described. Information of a general nature on the total design problem plus specific details on how these requirements are to be satisfied are reported. The configuration of the simulator is described and the capabilities for various types of training are identified.

  14. Access flight hardware design and development

    NASA Technical Reports Server (NTRS)

    Rogers, John F.; Tutterow, Robin D.

    1987-01-01

    Several items were found to be of immense value in the design and development of the Assembly Concept for Construction of Erectable Space Structures (ACCESS) hardware. The early availability of mock-up and engineering test hardware helped to develop the concept and prove the feasibility of the experiment. The extensive neutral buoyancy testing was invaluable in developing the procedures and timelines, proving that the hardware functioned as intended, and effectively trained the astronauts. The early involvement of the crew systems/astronaut personnel was extremely beneficial in shaping the design to meet the EVA compatibility requirements. Also, the early definition of coupled loads and on-orbit dynamic responses can not be overemphasized due to the relative uncertainty in the magnitude of these loads and their impact on the design.

  15. Microprocessor Design Using Hardware Description Language

    ERIC Educational Resources Information Center

    Mita, Rosario; Palumbo, Gaetano

    2008-01-01

    The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

  16. Design guidelines for robotically serviceable hardware

    NASA Technical Reports Server (NTRS)

    Gordon, Scott A.

    1988-01-01

    Research being conducted at the Goddard Space Flight Center into the development of guidelines for the design of robotically serviceable spaceflight hardware is described. A mock-up was built based on an existing spaceflight system demonstrating how these guidelines can be applied to actual hardware. The report examines the basic servicing philosophy being studied and how this philosophy is reflected in the formulation of design guidelines for robotic servicing. A description of the mock-up is presented with emphasis on the design features that make it robot friendly. Three robotic servicing schemes fulfilling the design guidelines were developed for the mock-up. These servicing schemes are examined as to how their implementation was affected by the constraints of the spacecraft system on which the mock-up is based.

  17. SuperCDMS Cold Hardware Design

    SciTech Connect

    Al Kenany, S.; Rolla, Julie A.; Godfrey, Gary; Brink, Paul L.; Seitz, Dennis N.; Figueroa-Feliciano, Enectali; Huber, Martin E.; Hines, Bruce A.; Irwin, Kent D.; /NIST, Boulder

    2012-06-13

    We discuss the current design of the cold hardware and cold electronics to be used in the upcoming SuperCDMS Soudan deployment. Engineering challenges associated with such concerns as thermal isolation, microphonics, radiopurity, and power dissipation are discussed, along with identifying the design changes necessary for SuperCDMS SNOLAB. The Cryogenic Dark Matter Search (CDMS) employs ultrapure 1-inch thick, 3-inch diameter germanium crystals operating below 50 mK in a dilution cryostat. These detectors give an ionization and phonon signal, which gives us rejection capabilities regarding background events versus dark matter signals.

  18. Design Space Issues for Intrinsic Evolvable Hardware

    NASA Technical Reports Server (NTRS)

    Hereford, James; Gwaltney, David

    2004-01-01

    This paper discusses the problem of increased programming time for intrinsic evolvable hardware (EM) as the complexity of the circuit grows. As the circuit becomes more complex, then more components will be required and a longer programming string, L, is required. We develop equations for the size of the population, n, and the number of generations required for the population to converge, based on L. Our analytical results show that even though the design search space grows as 2L (assuming a binary programming string), the number of circuit evaluations, n*ngen, only grows as O(Lg3), or slightly less than O(L). This makes evolvable techniques a good tool for exploring large design spaces. The major hurdle for intrinsic EHW is evaluation time for each possible circuit. The evaluation time involves downloading the bit string to the device, updating the device configuration, measuring the output and then transferring the output data to the control processor. Each of these steps must be done for each member of the population. The processing time of the computer becomes negligible since the selection/crossover/mutation steps are only done once per generation. Evaluation time presently limits intrinsic evolvable hardware techniques to designing only small or medium-sized circuits. To evolve large or complicated circuits, several researchers have proposed using hierarchical design or reuse techniques where submodules are combined together to form complex circuits. However, these practical approaches limit the search space of available designs and preclude utilizing parasitic coupling or other effects within the programmable device. The practical approaches also raise the issue of why intrinsic EHW techniques do not easily apply to large design spaces, since the analytical results show only an O(L) complexity growth.

  19. Theorem Proving in Intel Hardware Design

    NASA Technical Reports Server (NTRS)

    O'Leary, John

    2009-01-01

    For the past decade, a framework combining model checking (symbolic trajectory evaluation) and higher-order logic theorem proving has been in production use at Intel. Our tools and methodology have been used to formally verify execution cluster functionality (including floating-point operations) for a number of Intel products, including the Pentium(Registered TradeMark)4 and Core(TradeMark)i7 processors. Hardware verification in 2009 is much more challenging than it was in 1999 - today s CPU chip designs contain many processor cores and significant firmware content. This talk will attempt to distill the lessons learned over the past ten years, discuss how they apply to today s problems, outline some future directions.

  20. Employing ISRU Models to Improve Hardware Design

    NASA Technical Reports Server (NTRS)

    Linne, Diane L.

    2010-01-01

    An analytical model for hydrogen reduction of regolith was used to investigate the effects of several key variables on the energy and mass performance of reactors for a lunar in-situ resource utilization oxygen production plant. Reactor geometry, reaction time, number of reactors, heat recuperation, heat loss, and operating pressure were all studied to guide hardware designers who are developing future prototype reactors. The effects of heat recuperation where the incoming regolith is pre-heated by the hot spent regolith before transfer was also investigated for the first time. In general, longer reaction times per batch provide a lower overall energy, but also result in larger and heavier reactors. Three reactors with long heat-up times results in similar energy requirements as a two-reactor system with all other parameters the same. Three reactors with heat recuperation results in energy reductions of 20 to 40 percent compared to a three-reactor system with no heat recuperation. Increasing operating pressure can provide similar energy reductions as heat recuperation for the same reaction times.

  1. The Art of Space Flight Exercise Hardware: Design and Implementation

    NASA Technical Reports Server (NTRS)

    Beyene, Nahom M.

    2004-01-01

    The design of space flight exercise hardware depends on experience with crew health maintenance in a microgravity environment, history in development of flight-quality exercise hardware, and a foundation for certifying proper project management and design methodology. Developed over the past 40 years, the expertise in designing exercise countermeasures hardware at the Johnson Space Center stems from these three aspects of design. The medical community has steadily pursued an understanding of physiological changes in humans in a weightless environment and methods of counteracting negative effects on the cardiovascular and musculoskeletal system. The effects of weightlessness extend to the pulmonary and neurovestibular system as well with conditions ranging from motion sickness to loss of bone density. Results have shown losses in water weight and muscle mass in antigravity muscle groups. With the support of university-based research groups and partner space agencies, NASA has identified exercise to be the primary countermeasure for long-duration space flight. The history of exercise hardware began during the Apollo Era and leads directly to the present hardware on the International Space Station. Under the classifications of aerobic and resistive exercise, there is a clear line of development from the early devices to the countermeasures hardware used today. In support of all engineering projects, the engineering directorate has created a structured framework for project management. Engineers have identified standards and "best practices" to promote efficient and elegant design of space exercise hardware. The quality of space exercise hardware depends on how well hardware requirements are justified by exercise performance guidelines and crew health indicators. When considering the microgravity environment of the device, designers must consider performance of hardware separately from the combined human-in-hardware system. Astronauts are the caretakers of the hardware

  2. Automated Hardware Design via Evolutionary Search

    NASA Technical Reports Server (NTRS)

    Lohn, Jason D.; Colombano, Silvano P.

    2000-01-01

    The goal of this research is to investigate the application of evolutionary search to the process of automated engineering design. Evolutionary search techniques involve the simulation of Darwinian mechanisms by computer algorithms. In recent years, such techniques have attracted much attention because they are able to tackle a wide variety of difficult problems and frequently produce acceptable solutions. The results obtained are usually functional, often surprising, and typically "messy" because the algorithms are told to concentrate on the overriding objective and not elegance or simplicity. advantages. First, faster design cycles translate into time and, hence, cost savings. Second, automated design techniques can be made to scale well and hence better deal with increasing amounts of design complexity. Third, design quality can increase because design properties can be specified a priori. For example, size and weight specifications of a device, smaller and lighter than the best known design, might be optimized by the automated design technique. The domain of electronic circuit design is an advantageous platform in which to study automated design techniques because it is a rich design space that is well understood, permitting human-created designs to be compared to machine- generated designs. developed for circuit design was to automatically produce high-level integrated electronic circuit designs whose properties permit physical implementation in silicon. This process entailed designing an effective evolutionary algorithm and solving a difficult multiobjective optimization problem. FY 99 saw many accomplishments in this effort.

  3. The monarch parallel processor hardware design

    SciTech Connect

    Rettberg, R.D.; Crowther, W.R.; Carvey, P.P.; Tomlinson, R.S. )

    1990-04-01

    The authors report on their development of the Monarch parallel processor. Today, the Monarch's design is largely done and well into implementation. The high-speed interconnection network has been tested with two-micron switch chips, logging more than 30,000 device hours of operation at 125 mega bits per second passing over 10{sup 16} bits. The processor's logic design is almost complete and simulated. The memory controller and concentrator remain to be designed. The authors have analyzed the software in detail with the use of hand-coded examples, a simulator, and a rudimentary compiler. The authors are currently seeking support to finish the implementation.

  4. Magnetic resonance elastography hardware design: a survey.

    PubMed

    Tse, Z T H; Janssen, H; Hamed, A; Ristic, M; Young, I; Lamperth, M

    2009-05-01

    Magnetic resonance elastography (MRE) is an emerging technique capable of measuring the shear modulus of tissue. A suspected tumour can be identified by comparing its properties with those of tissues surrounding it; this can be achieved even in deep-lying areas as long as mechanical excitation is possible. This would allow non-invasive methods for cancer-related diagnosis in areas not accessible with conventional palpation. An actuating mechanism is required to generate the necessary tissue displacements directly on the patient in the scanner and three different approaches, in terms of actuator action and position, exist to derive stiffness measurements. However, the magnetic resonance (MR) environment places considerable constraints on the design of such devices, such as the possibility of mutual interference between electrical components, the scanner field, and radio frequency pulses, and the physical space restrictions of the scanner bore. This paper presents a review of the current solutions that have been developed for MRE devices giving particular consideration to the design criteria including the required vibration frequency and amplitude in different applications, the issue of MR compatibility, actuation principles, design complexity, and scanner synchronization issues. The future challenges in this field are also described. PMID:19499839

  5. Flight Hardware Packaging Design for Stringent EMC Radiated Emission Requirements

    NASA Technical Reports Server (NTRS)

    Lortz, Charlene L.; Huang, Chi-Chien N.; Ravich, Joshua A.; Steiner, Carl N.

    2013-01-01

    This packaging design approach can help heritage hardware meet a flight project's stringent EMC radiated emissions requirement. The approach requires only minor modifications to a hardware's chassis and mainly concentrates on its connector interfaces. The solution is to raise the surface area where the connector is mounted by a few millimeters using a pedestal, and then wrapping with conductive tape from the cable backshell down to the surface-mounted connector. This design approach has been applied to JPL flight project subsystems. The EMC radiated emissions requirements for flight projects can vary from benign to mission critical. If the project's EMC requirements are stringent, the best approach to meet EMC requirements would be to design an EMC control program for the project early on and implement EMC design techniques starting with the circuit board layout. This is the ideal scenario for hardware that is built from scratch. Implementation of EMC radiated emissions mitigation techniques can mature as the design progresses, with minimal impact to the design cycle. The real challenge exists for hardware that is planned to be flown following a built-to-print approach, in which heritage hardware from a past project with a different set of requirements is expected to perform satisfactorily for a new project. With acceptance of heritage, the design would already be established (circuit board layout and components have already been pre-determined), and hence any radiated emissions mitigation techniques would only be applicable at the packaging level. The key is to take a heritage design with its known radiated emissions spectrum and repackage, or modify its chassis design so that it would have a better chance of meeting the new project s radiated emissions requirements.

  6. Design Tools for Reconfigurable Hardware in Orbit (RHinO)

    NASA Technical Reports Server (NTRS)

    French, Mathew; Graham, Paul; Wirthlin, Michael; Larchev, Gregory; Bellows, Peter; Schott, Brian

    2004-01-01

    The Reconfigurable Hardware in Orbit (RHinO) project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. These tools leverage an established FPGA design environment and focus primarily on space effects mitigation and power optimization. The project is creating software to automatically test and evaluate the single-event-upsets (SEUs) sensitivities of an FPGA design and insert mitigation techniques. Extensions into the tool suite will also allow evolvable algorithm techniques to reconfigure around single-event-latchup (SEL) events. In the power domain, tools are being created for dynamic power visualiization and optimization. Thus, this technology seeks to enable the use of Reconfigurable Hardware in Orbit, via an integrated design tool-suite aiming to reduce risk, cost, and design time of multimission reconfigurable space processors using SRAM-based FPGAs.

  7. Lab at Home: Hardware Kits for a Digital Design Lab

    ERIC Educational Resources Information Center

    Oliver, J. P.; Haim, F.

    2009-01-01

    An innovative laboratory methodology for an introductory digital design course is presented. Instead of having traditional lab experiences, where students have to come to school classrooms, a "lab at home" concept is proposed. Students perform real experiments in their own homes, using hardware kits specially developed for this purpose. They…

  8. Temporal high-pass non-uniformity correction algorithm based on grayscale mapping and hardware implementation

    NASA Astrophysics Data System (ADS)

    Jin, Minglei; Jin, Weiqi; Li, Yiyang; Li, Shuo

    2015-08-01

    In this paper, we propose a novel scene-based non-uniformity correction algorithm for infrared image processing-temporal high-pass non-uniformity correction algorithm based on grayscale mapping (THP and GM). The main sources of non-uniformity are: (1) detector fabrication inaccuracies; (2) non-linearity and variations in the read-out electronics and (3) optical path effects. The non-uniformity will be reduced by non-uniformity correction (NUC) algorithms. The NUC algorithms are often divided into calibration-based non-uniformity correction (CBNUC) algorithms and scene-based non-uniformity correction (SBNUC) algorithms. As non-uniformity drifts temporally, CBNUC algorithms must be repeated by inserting a uniform radiation source which SBNUC algorithms do not need into the view, so the SBNUC algorithm becomes an essential part of infrared imaging system. The SBNUC algorithms' poor robustness often leads two defects: artifacts and over-correction, meanwhile due to complicated calculation process and large storage consumption, hardware implementation of the SBNUC algorithms is difficult, especially in Field Programmable Gate Array (FPGA) platform. The THP and GM algorithm proposed in this paper can eliminate the non-uniformity without causing defects. The hardware implementation of the algorithm only based on FPGA has two advantages: (1) low resources consumption, and (2) small hardware delay: less than 20 lines, it can be transplanted to a variety of infrared detectors equipped with FPGA image processing module, it can reduce the stripe non-uniformity and the ripple non-uniformity.

  9. Energy Efficient Engine combustor test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Burrus, D. L.; Chahrour, C. A.; Foltz, H. L.; Sabla, P. E.; Seto, S. P.; Taylor, J. R.

    1984-01-01

    The Energy Efficient Engine (E3) Combustor Development effort was conducted as part of the overall NASA/GE E3 Program. This effort included the selection of an advanced double-annular combustion system design. The primary intent was to evolve a design which meets the stringent emissions and life goals of the E3 as well as all of the usual performance requirements of combustion systems for modern turbofan engines. Numerous detailed design studies were conducted to define the features of the combustion system design. Development test hardware was fabricated, and an extensive testing effort was undertaken to evaluate the combustion system subcomponents in order to verify and refine the design. Technology derived from this development effort will be incorporated into the engine combustion system hardware design. This advanced engine combustion system will then be evaluated in component testing to verify the design intent. What is evolving from this development effort is an advanced combustion system capable of satisfying all of the combustion system design objectives and requirements of the E3. Fuel nozzle, diffuser, starting, and emissions design studies are discussed.

  10. Hardware Design of the Energy Efficient Fall Detection Device

    NASA Astrophysics Data System (ADS)

    Skorodumovs, A.; Avots, E.; Hofmanis, J.; Korāts, G.

    2016-04-01

    Health issues for elderly people may lead to different injuries obtained during simple activities of daily living. Potentially the most dangerous are unintentional falls that may be critical or even lethal to some patients due to the heavy injury risk. In the project "Wireless Sensor Systems in Telecare Application for Elderly People", we have developed a robust fall detection algorithm for a wearable wireless sensor. To optimise the algorithm for hardware performance and test it in field, we have designed an accelerometer based wireless fall detector. Our main considerations were: a) functionality - so that the algorithm can be applied to the chosen hardware, and b) power efficiency - so that it can run for a very long time. We have picked and tested the parts, built a prototype, optimised the firmware for lowest consumption, tested the performance and measured the consumption parameters. In this paper, we discuss our design choices and present the results of our work.

  11. Hardware Design Improvements to the Major Constituent Analyzer

    NASA Technical Reports Server (NTRS)

    Combs, Scott; Schwietert, Daniel; Anaya, Marcial; DeWolf, Shannon; Merrill, Dave; Gardner, Ben D.; Thoresen, Souzan; Granahan, John; Belcher, Paul; Matty, Chris

    2011-01-01

    The Major Constituent Analyzer (MCA) onboard the International Space Station (ISS) is designed to monitor the major constituents of the ISS's internal atmosphere. This mass spectrometer based system is an integral part of the Environmental Control and Life Support System (ECLSS) and is a primary tool for the management of ISS atmosphere composition. As a part of NASA Change Request CR10773A, several alterations to the hardware have been made to accommodate improved MCA logistics. First, the ORU 08 verification gas assembly has been modified to allow the verification gas cylinder to be installed on orbit. The verification gas is an essential MCA consumable that requires periodic replenishment. Designing the cylinder for subassembly transport reduces the size and weight of the maintained item for launch. The redesign of the ORU 08 assembly includes a redesigned housing, cylinder mounting apparatus, and pneumatic connection. The second hardware change is a redesigned wiring harness for the ORU 02 analyzer. The ORU 02 electrical connector interface was damaged in a previous on-orbit installation, and this necessitated the development of a temporary fix while a more permanent solution was developed. The new wiring harness design includes flexible cable as well as indexing fasteners and guide-pins, and provides better accessibility during the on-orbit maintenance operation. This presentation will describe the hardware improvements being implemented for MCA as well as the expected improvement to logistics and maintenance.

  12. HSCT Sector Combustor Hardware Modifications for Improved Combustor Design

    NASA Technical Reports Server (NTRS)

    Greenfield, Stuart C.; Heberling, Paul V.; Moertle, George E.

    2005-01-01

    An alternative to the stepped-dome design for the lean premixed prevaporized (LPP) combustor has been developed. The new design uses the same premixer types as the stepped-dome design: integrated mixer flameholder (IMFH) tubes and a cyclone swirler pilot. The IMFH fuel system has been taken to a new level of development. Although the IMFH fuel system design developed in this Task is not intended to be engine-like hardware, it does have certain characteristics of engine hardware, including separate fuel circuits for each of the fuel stages. The four main stage fuel circuits are integrated into a single system which can be withdrawn from the combustor as a unit. Additionally, two new types of liner cooling have been designed. The resulting lean blowout data was found to correlate well with the Lefebvre parameter. As expected, CO and unburned hydrocarbons emissions were shown to have an approximately linear relationship, even though some scatter was present in the data, and the CO versus flame temperature data showed the typical cupped shape. Finally, the NOx emissions data was shown to agree well with a previously developed correlation based on emissions data from Configuration 3 tests performed at GEAE. The design variations of the cyclone swirler pilot that were investigated in this study did not significantly change the NOx emissions from the baseline design (GEAE Configuration 3) at supersonic cruise conditions.

  13. IDEAS and App Development Internship in Hardware and Software Design

    NASA Technical Reports Server (NTRS)

    Alrayes, Rabab D.

    2016-01-01

    In this report, I will discuss the tasks and projects I have completed while working as an electrical engineering intern during the spring semester of 2016 at NASA Kennedy Space Center. In the field of software development, I completed tasks for the G-O Caching Mobile App and the Asbestos Management Information System (AMIS) Web App. The G-O Caching Mobile App was written in HTML, CSS, and JavaScript on the Cordova framework, while the AMIS Web App is written in HTML, CSS, JavaScript, and C# on the AngularJS framework. My goals and objectives on these two projects were to produce an app with an eye-catching and intuitive User Interface (UI), which will attract more employees to participate; to produce a fully-tested, fully functional app which supports workforce engagement and exploration; to produce a fully-tested, fully functional web app that assists technicians working in asbestos management. I also worked in hardware development on the Integrated Display and Environmental Awareness System (IDEAS) wearable technology project. My tasks on this project were focused in PCB design and camera integration. My goals and objectives for this project were to successfully integrate fully functioning custom hardware extenders on the wearable technology headset to minimize the size of hardware on the smart glasses headset for maximum user comfort; to successfully integrate fully functioning camera onto the headset. By the end of this semester, I was able to successfully develop four extender boards to minimize hardware on the headset, and assisted in integrating a fully-functioning camera into the system.

  14. Design-to-fabricate: maker hardware requires maker software.

    PubMed

    Schmidt, Ryan; Ratto, Matt

    2013-01-01

    As a result of consumer-level 3D printers' increasing availability and affordability, the audience for 3D-design tools has grown considerably. However, current tools are ill-suited for these users. They have steep learning curves and don't take into account that the end goal is a physical object, not a digital model. A new class of "maker"-level design tools is needed to accompany this new commodity hardware. However, recent examples of such tools achieve accessibility primarily by constraining functionality. In contrast, the meshmixer project is building tools that provide accessibility and expressive power by leveraging recent computer graphics research in geometry processing. The project members have had positive experiences with several 3D-design-to-print workshops and are exploring several design-to-fabricate problems. This article is part of a special issue on 3D printing. PMID:24808128

  15. Towards improved hardware component attenuation correction in PET/MR hybrid imaging

    NASA Astrophysics Data System (ADS)

    Paulus, D. H.; Tellmann, L.; Quick, H. H.

    2013-11-01

    In positron emission tomography/computed tomography (PET/CT) hybrid imaging attenuation correction (AC) of the patient tissue and patient table is performed by converting the CT-based Hounsfield units (HU) to linear attenuation coefficients (LAC) of PET. When applied to the new field of hardware component AC in PET/magnetic resonance (MR) hybrid imaging, this conversion method may result in local overcorrection of PET activity values. The aim of this study thus was to optimize the conversion parameters for CT-based AC of hardware components in PET/MR. Systematic evaluation and optimization of the HU to LAC conversion parameters has been performed for the hardware component attenuation map (µ-map) of a flexible radiofrequency (RF) coil used in PET/MR imaging. Furthermore, spatial misregistration of this RF coil to its µ-map was simulated by shifting the µ-map in different directions and the effect on PET quantification was evaluated. Measurements of a PET NEMA standard emission phantom were performed on an integrated hybrid PET/MR system. Various CT parameters were used to calculate different µ-maps for the flexible RF coil and to evaluate the impact on the PET activity concentration. A 511 keV transmission scan of the local RF coil was used as standard of reference to adapt the slope of the conversion from HUs to LACs at 511 keV. The average underestimation of the PET activity concentration due to the non-attenuation corrected RF coil in place was calculated to be 5.0% in the overall phantom. When considering attenuation only in the upper volume of the phantom, the average difference to the reference scan without RF coil is 11.0%. When the PET/CT conversion is applied, an average overestimation of 3.1% (without extended CT scale) and 4.2% (with extended CT scale) is observed in the top volume of the NEMA phantom. Using the adapted conversion resulting from this study, the deviation in the top volume of the phantom is reduced to -0.5% and shows the lowest

  16. Health Maintenance System (HMS) Hardware Research, Design, and Collaboration

    NASA Technical Reports Server (NTRS)

    Gonzalez, Stefanie M.

    2010-01-01

    The Space Life Sciences division (SLSD) concentrates on optimizing a crew member's health. Developments are translated into innovative engineering solutions, research growth, and community awareness. This internship incorporates all those areas by targeting various projects. The main project focuses on integrating clinical and biomedical engineering principles to design, develop, and test new medical kits scheduled for launch in the Spring of 2011. Additionally, items will be tagged with Radio Frequency Interference Devices (RFID) to keep track of the inventory. The tags will then be tested to optimize Radio Frequency feed and feed placement. Research growth will occur with ground based experiments designed to measure calcium encrusted deposits in the International Space Station (ISS). The tests will assess the urine calcium levels with Portable Clinical Blood Analyzer (PCBA) technology. If effective then a model for urine calcium will be developed and expanded to microgravity environments. To support collaboration amongst the subdivisions of SLSD the architecture of the Crew Healthcare Systems (CHeCS) SharePoint site has been redesigned for maximum efficiency. Community collaboration has also been established with the University of Southern California, Dept. of Aeronautical Engineering and the Food and Drug Administration (FDA). Hardware disbursements will transpire within these communities to support planetary surface exploration and to serve as an educational tool demonstrating how ground based medicine influenced the technological development of space hardware.

  17. Hardware accelerator design for tracking in smart camera

    NASA Astrophysics Data System (ADS)

    Singh, Sanjay; Dunga, Srinivasa Murali; Saini, Ravi; Mandal, A. S.; Shekhar, Chandra; Vohra, Anil

    2011-10-01

    Smart Cameras are important components in video analysis. For video analysis, smart cameras needs to detect interesting moving objects, track such objects from frame to frame, and perform analysis of object track in real time. Therefore, the use of real-time tracking is prominent in smart cameras. The software implementation of tracking algorithm on a general purpose processor (like PowerPC) could achieve low frame rate far from real-time requirements. This paper presents the SIMD approach based hardware accelerator designed for real-time tracking of objects in a scene. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA. Resulted frame rate is 30 frames per second for 250x200 resolution video in gray scale.

  18. Modular implementation of a digital hardware design automation system

    NASA Astrophysics Data System (ADS)

    Masud, M.

    An automation system based on AHPL (A Hardware Programming Language) was developed. The project may be divided into three distinct phases: (1) Upgrading of AHPL to make it more universally applicable; (2) Implementation of a compiler for the language; and (3) illustration of how the compiler may be used to support several phases of design activities. Several new features were added to AHPL. These include: application-dependent parameters, mutliple clocks, asynchronous results, functional registers and primitive functions. The new language, called Universal AHPL, has been defined rigorously. The compiler design is modular. The parsing is done by an automatic parser generated from the SLR(1)BNF grammar of the language. The compiler produces two data bases from the AHPL description of a circuit. The first one is a tabular representation of the circuit, and the second one is a detailed interconnection linked list. The two data bases provide a means to interface the compiler to application-dependent CAD systems.

  19. Design and test hardware for a solar array switching unit

    NASA Technical Reports Server (NTRS)

    Patil, A. R.; Cho, B. H.; Sable, D.; Lee, F. C.

    1992-01-01

    This paper describes the control of a pulse width modulated (PWM) type sequential shunt switching unit (SSU) for spacecraft applications. It is found that the solar cell output capacitance has a significant impact on SSU design. Shorting of this cell capacitance by the PWM switch causes input current surges. These surges are minimized by the use of a series filter inductor. The system with a filter is analyzed for ripple and the control to output-voltage transfer function. Stable closed loop design considerations are discussed. The results are supported by modeling and measurements of loop gain and of closed-loop bus impedance on test hardware for NASA's 120 V Earth Observation System (EOS). The analysis and modeling are also applicable to NASA's 160 V Space Station power system.

  20. Process of videotape making: presentation design, software, and hardware

    NASA Astrophysics Data System (ADS)

    Dickinson, Robert R.; Brady, Dan R.; Bennison, Tim; Burns, Thomas; Pines, Sheldon

    1991-06-01

    The use of technical video tape presentations for communicating abstractions of complex data is now becoming commonplace. While the use of video tapes in the day-to-day work of scientists and engineers is still in its infancy, their use as applications oriented conferences is now growing rapidly. Despite these advancements, there is still very little that is written down about the process of making technical videotapes. For printed media, different presentation styles are well known for categories such as results reports, executive summary reports, and technical papers and articles. In this paper, the authors present ideas on the topic of technical videotape presentation design in a format that is worth referring to. They have started to document the ways in which the experience of media specialist, teaching professionals, and character animators can be applied to scientific animation. Software and hardware considerations are also discussed. For this portion, distinctions are drawn between the software and hardware required for computer animation (frame at a time) productions, and live recorded interaction with a computer graphics display.

  1. Design time optimization for hardware watermarking protection of HDL designs.

    PubMed

    Castillo, E; Morales, D P; García, A; Parrilla, L; Todorovich, E; Meyer-Baese, U

    2015-01-01

    HDL-level design offers important advantages for the application of watermarking to IP cores, but its complexity also requires tools automating these watermarking algorithms. A new tool for signature distribution through combinational logic is proposed in this work. IPP@HDL, a previously proposed high-level watermarking technique, has been employed for evaluating the tool. IPP@HDL relies on spreading the bits of a digital signature at the HDL design level using combinational logic included within the original system. The development of this new tool for the signature distribution has not only extended and eased the applicability of this IPP technique, but it has also improved the signature hosting process itself. Three algorithms were studied in order to develop this automated tool. The selection of a cost function determines the best hosting solutions in terms of area and performance penalties on the IP core to protect. An 1D-DWT core and MD5 and SHA1 digital signatures were used in order to illustrate the benefits of the new tool and its optimization related to the extraction logic resources. Among the proposed algorithms, the alternative based on simulated annealing reduces the additional resources while maintaining an acceptable computation time and also saving designer effort and time. PMID:25861681

  2. Design Time Optimization for Hardware Watermarking Protection of HDL Designs

    PubMed Central

    Castillo, E.; Morales, D. P.; García, A.; Parrilla, L.; Todorovich, E.; Meyer-Baese, U.

    2015-01-01

    HDL-level design offers important advantages for the application of watermarking to IP cores, but its complexity also requires tools automating these watermarking algorithms. A new tool for signature distribution through combinational logic is proposed in this work. IPP@HDL, a previously proposed high-level watermarking technique, has been employed for evaluating the tool. IPP@HDL relies on spreading the bits of a digital signature at the HDL design level using combinational logic included within the original system. The development of this new tool for the signature distribution has not only extended and eased the applicability of this IPP technique, but it has also improved the signature hosting process itself. Three algorithms were studied in order to develop this automated tool. The selection of a cost function determines the best hosting solutions in terms of area and performance penalties on the IP core to protect. An 1D-DWT core and MD5 and SHA1 digital signatures were used in order to illustrate the benefits of the new tool and its optimization related to the extraction logic resources. Among the proposed algorithms, the alternative based on simulated annealing reduces the additional resources while maintaining an acceptable computation time and also saving designer effort and time. PMID:25861681

  3. INO340 telescope control system: hardware design and development

    NASA Astrophysics Data System (ADS)

    Jafarzadeh, Asghar; Ravanmehr, Reza

    2014-07-01

    In order to meet high image quality requirements of the INO340 telescope, one of the significant issues is the design and development of the Telescope Control System (TCS) architecture. The architecture of TCS is designed based on distributed control system configuration, which consists of four major subsystems: Telescope Control System supervisor (TCSS), Dome Control System (DCS), Mount Control System (MCS), and Active Optic System (AOS). Another system which plays important role in the hardware architecture is Interlock System (ILS), which is responsible for safety of staff, telescope and data. ILS architecture is also designed, using distributed system method based on the fail-safe PLCs. All subsystems of TCS are designed with an adequate safety subsystem, which are responsible for the safety of the subsystem and communicates through reliable lines with the main controller, placed in control room. In this paper, we explain the innovative architecture of Telescope Control System together with Interlock System and in brief show the interface control issues between different subsystems.

  4. Hardware synthesis from DDL. [Digital Design Language for computer aided design and test of LSI

    NASA Technical Reports Server (NTRS)

    Shah, A. M.; Shiva, S. G.

    1981-01-01

    The details of the digital systems can be conveniently input into the design automation system by means of Hardware Description Languages (HDL). The Computer Aided Design and Test (CADAT) system at NASA MSFC is used for the LSI design. The Digital Design Language (DDL) has been selected as HDL for the CADAT System. DDL translator output can be used for the hardware implementation of the digital design. This paper addresses problems of selecting the standard cells from the CADAT standard cell library to realize the logic implied by the DDL description of the system.

  5. Hardware design and implementation of the closed-orbit feedback system at APS

    SciTech Connect

    Barr, D.; Chung, Youngjoo

    1996-10-01

    The Advanced Photon Source (APS) storage ring will utilize a closed-orbit feedback system in order to produce a more stable beam. The specified orbit measurement resolution is 25 microns for global feedback and 1 micron for local feedback. The system will sample at 4 kHz and provide a correction bandwidth of 100 Hz. At this bandwidth, standard rf BPMs will provide a resolution of 0.7 micron, while specialized miniature BPMs positioned on either side of the insertion devices for local feedback will provide a resolution of 0.2 micron (1). The measured BPM noise floor for standard BPMs is 0.06 micron per root hertz mA. Such a system has been designed, simulated, and tested on a small scale (2). This paper covers the actual hardware design and layout of the entire closed-loop system. This includes commercial hardware components, in addition to many components designed and built in-house. The paper will investigate the large-scale workings of all these devices, as well as an overall view of each piece of hardware used.

  6. Towards improved hardware component attenuation correction in PET/MR hybrid imaging.

    PubMed

    Paulus, D H; Tellmann, L; Quick, H H

    2013-11-21

    In positron emission tomography/computed tomography (PET/CT) hybrid imaging attenuation correction (AC) of the patient tissue and patient table is performed by converting the CT-based Hounsfield units (HU) to linear attenuation coefficients (LAC) of PET. When applied to the new field of hardware component AC in PET/magnetic resonance (MR) hybrid imaging, this conversion method may result in local overcorrection of PET activity values. The aim of this study thus was to optimize the conversion parameters for CT-based AC of hardware components in PET/MR. Systematic evaluation and optimization of the HU to LAC conversion parameters has been performed for the hardware component attenuation map (µ-map) of a flexible radiofrequency (RF) coil used in PET/MR imaging. Furthermore, spatial misregistration of this RF coil to its µ-map was simulated by shifting the µ-map in different directions and the effect on PET quantification was evaluated. Measurements of a PET NEMA standard emission phantom were performed on an integrated hybrid PET/MR system. Various CT parameters were used to calculate different µ-maps for the flexible RF coil and to evaluate the impact on the PET activity concentration. A 511 keV transmission scan of the local RF coil was used as standard of reference to adapt the slope of the conversion from HUs to LACs at 511 keV. The average underestimation of the PET activity concentration due to the non-attenuation corrected RF coil in place was calculated to be 5.0% in the overall phantom. When considering attenuation only in the upper volume of the phantom, the average difference to the reference scan without RF coil is 11.0%. When the PET/CT conversion is applied, an average overestimation of 3.1% (without extended CT scale) and 4.2% (with extended CT scale) is observed in the top volume of the NEMA phantom. Using the adapted conversion resulting from this study, the deviation in the top volume of the phantom is reduced to -0.5% and shows the lowest

  7. Hardware design of a spherical mini-rover

    NASA Technical Reports Server (NTRS)

    Tarlton, John

    1992-01-01

    In this hardware project the students designed the prototype of a novel mini-rover for the exploration of a planetary surface. In an actual application, a large number of such miniature roving devices would be released from a landing craft. Each rover would be equipped with a Cd 109 radio-isotope source (a gamma ray emitter) irradiating the planetary surface below the rover, and an x-ray fluorescence detector for a quantitative assay of high atomic weight elements in the planet's surface. (Similar, miniaturized, hand-held devices have recently been developed for use in gold mines). The device developed by the students was limited to demonstrating the mechanical and electrical drive. The geometric external shape is a sphere; hence there is no danger of the rover being turned on its back and stopped. Propulsion is by means of an interior mass, eccentric to the sphere and driven by an electric motor. In an inter-disciplinary effort in mechanical and electrical engineering, the students designed the mechanical parts, built the transistorized circuit board, and tested the device.

  8. Scalability, Timing, and System Design Issues for Intrinsic Evolvable Hardware

    NASA Technical Reports Server (NTRS)

    Hereford, James; Gwaltney, David

    2004-01-01

    In this paper we address several issues pertinent to intrinsic evolvable hardware (EHW). The first issue is scalability; namely, how the design space scales as the programming string for the programmable device gets longer. We develop a model for population size and the number of generations as a function of the programming string length, L, and show that the number of circuit evaluations is an O(L2) process. We compare our model to several successful intrinsic EHW experiments and discuss the many implications of our model. The second issue that we address is the timing of intrinsic EHW experiments. We show that the processing time is a small part of the overall time to derive or evolve a circuit and that major improvements in processor speed alone will have only a minimal impact on improving the scalability of intrinsic EHW. The third issue we consider is the system-level design of intrinsic EHW experiments. We review what other researchers have done to break the scalability barrier and contend that the type of reconfigurable platform and the evolutionary algorithm are tied together and impose limits on each other.

  9. Simplified method for the hardware implementation of nonuniformity correction on a resistor-array infrared scene projector

    NASA Astrophysics Data System (ADS)

    Jones, Lawrence E.; Olson, Eric M.; Murrer, Robert Lee, Jr.; Andrews, Allen R.

    1997-07-01

    Ever increasing developments in imaging infrared (IR) seekers that are being designed for Ballistic Missile Defense Office guided interceptor programs have amplified the necessity for robust hardware-in-the-loop (HWIL) testing to reduce program risk. Successful IR HWIL testing requires a high fidelity spatial, spectral, and temporal IR projector. Recent characterization measurements of a 512 X 512 metal-oxide semiconductor field-effect transistor (MOSFET) resistor array show that resistor array technology is a leading contender for the IR projector. As with any array device, nonuniform performance between individual elements of the array is a concern. This paper addresses a simplified approach to accomplishing the nonuniformity correction of a resistor array in real-time. The first step in this process is to obtain a nominal output curve typical of the resistors' MOSFET output. The key feature of this simplified process is that all output curves specific to individual resistors can be related to this typical curve with a simple gain and offset correction. In practice, the inverse of the typical output curve is stored in a look-up table in order to obtain the required command for a desired output and then a correcting gain and offset are applied. Results from this process show great promise.

  10. Energy efficient engine: Fan test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Sullivan, T. J.

    1980-01-01

    A single stage fan and quarter stage booster were designed for the energy efficient engine. The fan has an inlet radius ratio of 0.342 and a specific flow rate of 208.9 Kg/S sq m (42.8 lbm/sec sq ft). The fan rotor has 32 medium aspect ratio (2.597) titanium blades with a partspan shroud at 55% blade height. The design corrected fan tip speed is 411.5 M/S (1350 ft/sec). The quarter stage island splits the total fan flow with approximately 22% of the flow being supercharged by the quarter stage rotor. The fan bypass ratio is 6.8. The core flow total pressure ratio is 1.67 and the fan bypass pressure ratio is 1.65. The design details of the fan and booster blading, and the fan frame and static structure for the fan configuration are presented.

  11. [Design of an FPGA-based image guided surgery hardware platform].

    PubMed

    Zou, Fa-Dong; Qin, Bin-Jie

    2008-07-01

    An FPGA-Based Image Guided Surgery Hardware Platform has been designed and implemented in this paper. The hardware platform can provide hardware acceleration for image guided surgery. It is completed with a video decoder interface, a DDR memory controller, a 12C bus controller, an interrupt controller and so on. It is able to perform real time video endoscopy image capturing in the surgery and to preserve the hardware interface for image guided surgery algorithm module. PMID:18973036

  12. Hardware architecture design of a fast global motion estimation method

    NASA Astrophysics Data System (ADS)

    Liang, Chaobing; Sang, Hongshi; Shen, Xubang

    2015-12-01

    VLSI implementation of gradient-based global motion estimation (GME) faces two main challenges: irregular data access and high off-chip memory bandwidth requirement. We previously proposed a fast GME method that reduces computational complexity by choosing certain number of small patches containing corners and using them in a gradient-based framework. A hardware architecture is designed to implement this method and further reduce off-chip memory bandwidth requirement. On-chip memories are used to store coordinates of the corners and template patches, while the Gaussian pyramids of both the template and reference frame are stored in off-chip SDRAMs. By performing geometric transform only on the coordinates of the center pixel of a 3-by-3 patch in the template image, a 5-by-5 area containing the warped 3-by-3 patch in the reference image is extracted from the SDRAMs by burst read. Patched-based and burst mode data access helps to keep the off-chip memory bandwidth requirement at the minimum. Although patch size varies at different pyramid level, all patches are processed in term of 3x3 patches, so the utilization of the patch-processing circuit reaches 100%. FPGA implementation results show that the design utilizes 24,080 bits on-chip memory and for a sequence with resolution of 352x288 and frequency of 60Hz, the off-chip bandwidth requirement is only 3.96Mbyte/s, compared with 243.84Mbyte/s of the original gradient-based GME method. This design can be used in applications like video codec, video stabilization, and super-resolution, where real-time GME is a necessity and minimum memory bandwidth requirement is appreciated.

  13. Electronic hardware design of electrical capacitance tomography systems.

    PubMed

    Saied, I; Meribout, M

    2016-06-28

    Electrical tomography techniques for process imaging are very prominent for industrial applications, such as the oil and gas industry and chemical refineries, owing to their ability to provide the flow regime of a flowing fluid within a relatively high throughput. Among the various techniques, electrical capacitance tomography (ECT) is gaining popularity due to its non-invasive nature and its capability to differentiate between different phases based on their permittivity distribution. In recent years, several hardware designs have been provided for ECT systems that have improved its resolution of measurements to be around attofarads (aF, 10(-18) F), or the number of channels, that is required to be large for some applications that require a significant amount of data. In terms of image acquisition time, some recent systems could achieve a throughput of a few hundred frames per second, while data processing time could be achieved in only a few milliseconds per frame. This paper outlines the concept and main features of the most recent front-end and back-end electronic circuits dedicated for ECT systems. In this paper, multiple-excitation capacitance polling, a front-end electronic technique, shows promising results for ECT systems to acquire fast data acquisition speeds. A highly parallel field-programmable gate array (FPGA) based architecture for a fast reconstruction algorithm is also described. This article is part of the themed issue 'Supersensing through industrial process tomography'. PMID:27185964

  14. RF control hardware design for CYCIAE-100 cyclotron

    NASA Astrophysics Data System (ADS)

    Yin, Zhiguo; Fu, Xiaoliang; Ji, Bin; Zhao, Zhenlu; Zhang, Tianjue; Li, Pengzhan; Wei, Junyi; Xing, Jiansheng; Wang, Chuan

    2015-11-01

    The Beijing Radioactive Ion-beam Facility project is being constructed by BRIF division of China Institute of Atomic Energy. In this project, a 100 MeV high intensity compact proton cyclotron is built for multiple applications. The first successful beam extraction of CYCIAE-100 cyclotron was done in the middle of 2014. The extracted proton beam energy is 100 MeV and the beam current is more than 20 μA. The RF system of the CYCIAE-100 cyclotron includes two half-wavelength cavities, two 100 kW tetrode amplifiers and power transmission line systems (all above are independent from each other) and two sets of Low Level RF control crates. Each set of LLRF control includes an amplitude control unit, a tuning control unit, a phase control unit, a local Digital Signal Process control unit and an Advanced RISC Machines based EPICS IOC unit. These two identical LLRF control crates share one common reference clock and take advantages of modern digital technologies (e.g. DSP and Direct Digital Synthesizer) to achieve closed loop voltage and phase regulations of the dee-voltage. In the beam commission, the measured dee-voltage stability of RF system is better than 0.1% and phase stability is better than 0.03°. The hardware design of the LLRF system will be reviewed in this paper.

  15. Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques

    PubMed Central

    Rincon, Fernando; Vaderrama, Carlos; Villanueva, Felix; Caba, Julian; Lopez, Juan Carlos

    2014-01-01

    In FPGA-based control system design, partial reconfiguration is especially well suited to implement preemptive systems. In real-time systems, the deadline for critical task can compel the preemption of noncritical one. Besides, an asynchronous event can demand immediate attention and, then, force launching a reconfiguration process for high-priority task implementation. If the asynchronous event is previously scheduled, an explicit activation of the reconfiguration process is performed. If the event cannot be previously programmed, such as in dynamically scheduled systems, an implicit activation to the reconfiguration process is demanded. This paper provides a hardware-based approach to explicit and implicit activation of the partial reconfiguration process in dynamically reconfigurable SoCs and includes all the necessary tasks to cope with this issue. Furthermore, the reconfiguration service introduced in this work allows remote invocation of the reconfiguration process and then the remote integration of off-chip components. A model that offers component location transparency is also presented to enhance and facilitate system integration. PMID:24672292

  16. Design of Test Support Hardware for Advanced Space Suits

    NASA Technical Reports Server (NTRS)

    Watters, Jeffrey A.; Rhodes, Richard

    2013-01-01

    As a member of the Space Suit Assembly Development Engineering Team, I designed and built test equipment systems to support the development of the next generation of advanced space suits. During space suit testing it is critical to supply the subject with two functions: (1) cooling to remove metabolic heat, and (2) breathing air to pressurize the space suit. The objective of my first project was to design, build, and certify an improved Space Suit Cooling System for manned testing in a 1-G environment. This design had to be portable and supply a minimum cooling rate of 2500 BTU/hr. The Space Suit Cooling System is a robust, portable system that supports very high metabolic rates. It has a highly adjustable cool rate and is equipped with digital instrumentation to monitor the flowrate and critical temperatures. It can supply a variable water temperature down to 34 deg., and it can generate a maximum water flowrate of 2.5 LPM. My next project was to design and build a Breathing Air System that was capable of supply facility air to subjects wearing the Z-2 space suit. The system intakes 150 PSIG breathing air and regulates it to two operating pressures: 4.3 and 8.3 PSIG. It can also provide structural capabilities at 1.5x operating pressure: 6.6 and 13.2 PSIG, respectively. It has instrumentation to monitor flowrate, as well as inlet and outlet pressures. The system has a series of relief valves to fully protect itself in case of regulator failure. Both projects followed a similar design methodology. The first task was to perform research on existing concepts to develop a sufficient background knowledge. Then mathematical models were developed to size components and simulate system performance. Next, mechanical and electrical schematics were generated and presented at Design Reviews. After the systems were approved by the suit team, all the hardware components were specified and procured. The systems were then packaged, fabricated, and thoroughly tested. The next step

  17. Hardware Evolution of Closed-Loop Controller Designs

    NASA Technical Reports Server (NTRS)

    Gwaltney, David; Ferguson, Ian

    2002-01-01

    Poster presentation will outline on-going efforts at NASA, MSFC to employ various Evolvable Hardware experimental platforms in the evolution of digital and analog circuitry for application to automatic control. Included will be information concerning the application of commercially available hardware and software along with the use of the JPL developed FPTA2 integrated circuit and supporting JPL developed software. Results to date will be presented.

  18. Hardware-software partitioning for the design of system on chip by neural network optimization method

    NASA Astrophysics Data System (ADS)

    Pan, Zhongliang; Li, Wei; Shao, Qingyi; Chen, Ling

    2011-12-01

    In the design procedure of system on chip (SoC), it is needed to make use of hardware-software co-design technique owing to the great complexity of SoC. One of main steps in hardware-software co-design is how to carry out the partitioning of a system into hardware and software components. The efficient approaches for hardware-software partitioning can achieve good system performance, which is superior to the techniques that use software only or use hardware only. In this paper, a method based on neural networks is presented for the hardware-software partitioning of system on chip. The discrete Hopfield neural networks corresponding to the problem of hardware-software partitioning is built, the states of neural neurons are able to represent whether the required components or functionalities are to be implemented in hardware or software. An algorithm based on the principle of simulated annealing is designed, which can be used to compute the minimal energy states of neural networks, therefore the optimal partitioning schemes are obtained. The experimental results show that the hardware-software partitioning method proposed in this paper can obtain the near optimal partitioning for a lot of example circuits.

  19. Pyroshock Simulation Systems: Are We Correctly Qualifying Flight Hardware for Pyroshock Environments?

    NASA Technical Reports Server (NTRS)

    Kolaini, Ali R.; Nayeri, Reza; Kern, Dennis L.

    2009-01-01

    There are several methods of shock testing that are commonly used by the aerospace industry to qualify flight hardware to pyroshock environments. In some cases the shock results and in particular the shock response spectra computed from these tests were interpreted in such a way as to satisfy the testing requirements and were often considered successful for flight hardware qualification. However, close scrutiny of these acquired shock data suggest gross violation of the pyroshock qualification requirements. There are several issues, both in terms of the shock generation mechanisms and the shock signature acquisition and analysis that have led to improper qualification of flight hardware. In this paper some factors contributing to the misinterpretation of the shock data are reviewed. First, issues with the hardware fixturing and instrumentation that may lead to incorrect shock testing are discussed. Second, issues facing the shock simulation systems and pyrotechnic testing are reviewed. Finally, issues pertaining to the data acquisition and analysis are briefly discussed.

  20. Interim Service ISDN Satellite (ISIS) hardware experiment design for advanced ISDN satellite design and experiments

    NASA Technical Reports Server (NTRS)

    Pepin, Gerard R.

    1992-01-01

    The Interim Service Integrated Services Digital Network (ISDN) Satellite (ISIS) Hardware Experiment Design for Advanced Satellite Designs describes the design of the ISDN Satellite Terminal Adapter (ISTA) capable of translating ISDN protocol traffic into time division multiple access (TDMA) signals for use by a communications satellite. The ISTA connects the Type 1 Network Termination (NT1) via the U-interface on the line termination side of the CPE to the V.35 interface for satellite uplink. The same ISTA converts in the opposite direction the V.35 to U-interface data with a simple switch setting.

  1. Functional design specification for Stowage List And Hardware Tracking System (SLAHTS). [space shuttles

    NASA Technical Reports Server (NTRS)

    Keltner, D. J.

    1975-01-01

    This functional design specification defines the total systems approach to meeting the requirements stated in the Detailed Requirements Document for Stowage List and Hardware Tracking System for the space shuttle program. The stowage list and hardware tracking system is identified at the system and subsystem level with each subsystem defined as a function of the total system.

  2. Cognon Neural Model Software Verification and Hardware Implementation Design

    NASA Astrophysics Data System (ADS)

    Haro Negre, Pau

    Little is known yet about how the brain can recognize arbitrary sensory patterns within milliseconds using neural spikes to communicate information between neurons. In a typical brain there are several layers of neurons, with each neuron axon connecting to ˜104 synapses of neurons in an adjacent layer. The information necessary for cognition is contained in theses synapses, which strengthen during the learning phase in response to newly presented spike patterns. Continuing on the model proposed in "Models for Neural Spike Computation and Cognition" by David H. Staelin and Carl H. Staelin, this study seeks to understand cognition from an information theoretic perspective and develop potential models for artificial implementation of cognition based on neuronal models. To do so we focus on the mathematical properties and limitations of spike-based cognition consistent with existing neurological observations. We validate the cognon model through software simulation and develop concepts for an optical hardware implementation of a network of artificial neural cognons.

  3. Design of digital hardware system for pulse signals.

    PubMed

    Lee, J; Kim, J; Lee, M

    2001-12-01

    In this study, we have developed the digital hardware system which performs signal processing necessary for the filtering to eliminate noises by inputting pulse wave signals from the sensor group. With a view to obtain clinically effective information, we analyzed structural elements of pulse waveform and, thus, conducted a systematic classification. What is more, we performed the modeling of the digital filter by using the Steiglitz-McBride iteration method in order to get the same results with output signals coming out of an galvanometer of analog type of existing Pulse diagnosis system with input signals entering into galvanometer and coming out of the amp group of the Pulse diagnosis system. PMID:11708398

  4. Verifying the "correctness" of your optical proximity correction designs

    NASA Astrophysics Data System (ADS)

    Malhotra, Vinod K.; Chang, Fang C.

    1999-07-01

    The emerging demand for smaller and smaller IC features, undiminished by the delay of next generation stepper technologies, has increased the need for OPC and PSM designs that are becoming critical for leading-edge IC manufacturing. However, modifications made to the original layout by OPC or PSM deign tools in general, exclude the use of conventional design verification tools to verify the modified designs. Therefore, the question of design 'correctness' often goes unanswered until after the wafers have been printed. This is extremely costly in terms of time and money. In this paper, we address the critical issue that has thus far remained open, the development of methods for physical verification of OPC designs. Our approach uses fast lithography simulation to map the modified mask design to the final patterns produced on the wafer. The simulated wafer pattern is matched against the specified tolerances and the problem areas are reported. It is a hierarchical verification tool. The hierarchical processing of the data makes it a high performance tool and keeps the data volume in check. We validate this technology by comparing the simulation results with the experimental data. In addition, performance measurements indicate that it is an effective and practical solution to the problem of verifying correctness of full-chip OPC designs.

  5. Intrinsic Hardware Evolution for the Design and Reconfiguration of Analog Speed Controllers for a DC Motor

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; Ferguson, Michael I.

    2003-01-01

    Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a second generation Field Programmable Transistor Array (FPTA2). The performance of an evolved controller is compared to that of a conventional proportional-integral (PI) controller. It is shown that hardware evolution is able to create a compact design that provides good performance, while using considerably less functional electronic components than the conventional design. Additionally, the use of hardware evolution to provide fault tolerance by reconfiguring the design is explored. Experimental results are presented showing that significant recovery of capability can be made in the face of damaging induced faults.

  6. Biomolecular Design of an Integrated Software and Hardware System for Cryptography

    NASA Astrophysics Data System (ADS)

    Hirabayashi, Miki; Kojima, Hiroaki; Oiwa, Kazuhiro

    In the DNA-based molecular computation, calculation procedures described by the hardware design can provide an effective physical random source for the theoretically unbreakable encryption system. To realize its practical application, we present a new information processing idea.

  7. Energy efficient engine low-pressure compressor component test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Michael, C. J.; Halle, J. E.

    1981-01-01

    The aerodynamic and mechanical design description of the low pressure compressor component of the Energy Efficient Engine were used. The component was designed to meet the requirements of the Flight Propulsion System while maintaining a low cost approach in providing a low pressure compressor design for the Integrated Core/Low Spool test required in the Energy Efficient Engine Program. The resulting low pressure compressor component design meets or exceeds all design goals with the exception of surge margin. In addition, the expense of hardware fabrication for the Integrated Core/Low Spool test has been minimized through the use of existing minor part hardware.

  8. Multiple IMU system hardware interface design, volume 2

    NASA Technical Reports Server (NTRS)

    Landey, M.; Brown, D.

    1975-01-01

    The design of each system component is described. Emphasis is placed on functional requirements unique in this system, including data bus communication, data bus transmitters and receivers, and ternary-to-binary torquing decision logic. Mechanization drawings are presented.

  9. Savannah River Site reactor hardware design modification study

    SciTech Connect

    Fisher, J.E.

    1990-03-01

    A study was undertaken to assess the merits of proposed design modifications to the SRS reactors. The evaluation was based on the responses calculated by the RELAP5 systems code to double-ended guillotine break loss-of-coolant-accidents (DEGB LOCAs). The three concepts evaluated were (a) elevated plenum inlet piping with a guard vessel and clamshell enclosures, (b) closure of both rotovalves in the affected loop, and (c) closure of the pump suction valve in the affected loop. Each concept included a fast reactor shutdown (to 65% power in 100 ms) and a 2-s ac pump trip. For the elevated piping design, system recovery was predicted for breaks in the plenum inlet or pump suction piping; response to the pump discharge break location did not show improvement compared to the present system configuration. The rotovalve closure design improved system response to plenum inlet or pump discharge breaks; recovery was not predicted for pump suction breaks. The pump suction valve closure design demonstrated system recovery for all break locations downstream of the valve. A combination of features is recommended to ensure liquid inventory recovery for all break locations. The elevated piping design performance during pump discharge breaks would be improved with addition of a dc pump trip in the affected loop. Valve closure design performance for a break location in the short section of piping between the reactor concrete shield and the pump suction valve would benefit from the clamshell enclosing that section of piping. 12 refs., 10 figs., 2 tabs.

  10. Hardware design document for the Infrasound Prototype for a CTBT IMS station

    SciTech Connect

    Breding, D.R.; Kromer, R.P.; Whitaker, R.W.; Sandoval, T.

    1997-11-01

    The Hardware Design Document (HDD) describes the various hardware components used in the Comprehensive Test Ban Treaty (CTBT) Infrasound Prototype and their interrelationships. It divides the infrasound prototype into hardware configurations items (HWCIs). The HDD uses techniques such as block diagrams and parts lists to present this information. The level of detail provided in the following sections should be sufficient to allow potential users to procure and install the infrasound system. Infrasonic monitoring is a low cost, robust, and effective technology for detecting atmospheric explosions. Low frequencies from explosion signals propagate to long ranges (few thousand kilometers) where they can be detected with an array of sensors.

  11. Hardware removal - extremity

    MedlinePlus

    Surgeons use hardware such as pins, plates, or screws to help fix a broken bone or to correct an abnormality in ... of pain or other problems related to the hardware, you may have surgery to remove the hardware. ...

  12. Energy efficient engine combustor test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Zeisser, M. H.; Greene, W.; Dubiel, D. J.

    1982-01-01

    The combustor for the Energy Efficient Engine is an annular, two-zone component. As designed, it either meets or exceeds all program goals for performance, safety, durability, and emissions, with the exception of oxides of nitrogen. When compared to the configuration investigated under the NASA-sponsored Experimental Clean Combustor Program, which was used as a basis for design, the Energy Efficient Engine combustor component has several technology advancements. The prediffuser section is designed with short, strutless, curved-walls to provide a uniform inlet airflow profile. Emissions control is achieved by a two-zone combustor that utilizes two types of fuel injectors to improve fuel atomization for more complete combustion. The combustor liners are a segmented configuration to meet the durability requirements at the high combustor operating pressures and temperatures. Liner cooling is accomplished with a counter-parallel FINWALL technique, which provides more effective heat transfer with less coolant.

  13. Hardware acceleration of a Monte Carlo simulation for photodynamic therapy [corrected] treatment planning.

    PubMed

    Lo, William Chun Yip; Redmond, Keith; Luu, Jason; Chow, Paul; Rose, Jonathan; Lilge, Lothar

    2009-01-01

    Monte Carlo (MC) simulations are being used extensively in the field of medical biophysics, particularly for modeling light propagation in tissues. The high computation time for MC limits its use to solving only the forward solutions for a given source geometry, emission profile, and optical interaction coefficients of the tissue. However, applications such as photodynamic therapy treatment planning or image reconstruction in diffuse optical tomography require solving the inverse problem given a desired dose distribution or absorber distribution, respectively. A faster means for performing MC simulations would enable the use of MC-based models for accomplishing such tasks. To explore this possibility, a digital hardware implementation of a MC simulation based on the Monte Carlo for Multi-Layered media (MCML) software was implemented on a development platform with multiple field-programmable gate arrays (FPGAs). The hardware performed the MC simulation on average 80 times faster and was 45 times more energy efficient than the MCML software executed on a 3-GHz Intel Xeon processor. The resulting isofluence lines closely matched those produced by MCML in software, diverging by only less than 0.1 mm for fluence levels as low as 0.00001 cm(-2) in a skin model. PMID:19256707

  14. Performance/price estimates for cortex-scale hardware: a design space exploration.

    PubMed

    Zaveri, Mazad S; Hammerstrom, Dan

    2011-04-01

    In this paper, we revisit the concept of virtualization. Virtualization is useful for understanding and investigating the performance/price and other trade-offs related to the hardware design space. Moreover, it is perhaps the most important aspect of a hardware design space exploration. Such a design space exploration is a necessary part of the study of hardware architectures for large-scale computational models for intelligent computing, including AI, Bayesian, bio-inspired and neural models. A methodical exploration is needed to identify potentially interesting regions in the design space, and to assess the relative performance/price points of these implementations. As an example, in this paper we investigate the performance/price of (digital and mixed-signal) CMOS and hypothetical CMOL (nanogrid) technology based hardware implementations of human cortex-scale spiking neural systems. Through this analysis, and the resulting performance/price points, we demonstrate, in general, the importance of virtualization, and of doing these kinds of design space explorations. The specific results suggest that hybrid nanotechnology such as CMOL is a promising candidate to implement very large-scale spiking neural systems, providing a more efficient utilization of the density and storage benefits of emerging nano-scale technologies. In general, we believe that the study of such hypothetical designs/architectures will guide the neuromorphic hardware community towards building large-scale systems, and help guide research trends in intelligent computing, and computer engineering. PMID:21232918

  15. Hardware Design and Testing of SUPERball, A Modular Tensegrity Robot

    NASA Technical Reports Server (NTRS)

    Sabelhaus, Andrew P.; Bruce, Jonathan; Caluwaerts, Ken; Chen, Yangxin; Lu, Dizhou; Liu, Yuejia; Agogino, Adrian K.; SunSpiral, Vytas; Agogino, Alice M.

    2014-01-01

    We are developing a system of modular, autonomous "tensegrity end-caps" to enable the rapid exploration of untethered tensegrity robot morphologies and functions. By adopting a self-contained modular approach, different end-caps with various capabilities (such as peak torques, or motor speeds), can be easily combined into new tensegrity robots composed of rods, cables, and actuators of different scale (such as in length, mass, peak loads, etc). As a first step in developing this concept, we are in the process of designing and testing the end-caps for SUPERball (Spherical Underactuated Planetary Exploration Robot), a project at the Dynamic Tensegrity Robotics Lab (DTRL) within NASA Ames's Intelligent Robotics Group. This work discusses the evolving design concepts and test results that have gone into the structural, mechanical, and sensing aspects of SUPERball. This representative tensegrity end-cap design supports robust and repeatable untethered mobility tests of the SUPERball, while providing high force, high displacement actuation, with a low-friction, compliant cabling system.

  16. Internet-based hardware/software co-design framework for embedded 3D graphics applications

    NASA Astrophysics Data System (ADS)

    Yeh, Chi-Tsai; Wang, Chun-Hao; Huang, Ing-Jer; Wong, Weng-Fai

    2011-12-01

    Advances in technology are making it possible to run three-dimensional (3D) graphics applications on embedded and handheld devices. In this article, we propose a hardware/software co-design environment for 3D graphics application development that includes the 3D graphics software, OpenGL ES application programming interface (API), device driver, and 3D graphics hardware simulators. We developed a 3D graphics system-on-a-chip (SoC) accelerator using transaction-level modeling (TLM). This gives software designers early access to the hardware even before it is ready. On the other hand, hardware designers also stand to gain from the more complex test benches made available in the software for verification. A unique aspect of our framework is that it allows hardware and software designers from geographically dispersed areas to cooperate and work on the same framework. Designs can be entered and executed from anywhere in the world without full access to the entire framework, which may include proprietary components. This results in controlled and secure transparency and reproducibility, granting leveled access to users of various roles.

  17. Savannah River Site reactor hardware design modification study

    SciTech Connect

    Fisher, J.E.

    1990-01-01

    A study was undertaken to assess the merits of proposed design modifications to the Savannah River Site (SRS) reactors. The evaluation was based on the responses calculated by the RELAP5 systems code to double-ended guillotine break loss-of-coolant-accidents (DEGB LOCAs). The three concepts evaluated were (a) elevated plenum inlet piping with a guard vessel and clamshell enclosures, (b) closure of both rotovalves in the affected loop, and (c) closure of the pump suction valve in the affected loop. Each concept included a fast reactor shutdown (to 65% power in 100 ms) and a 2-s ac pump trip. System recovery potential was evaluated for break locations at the pump suction, the pump discharge, and the plenum inlet. The code version used was RELAP5/MOD2.5 version 3d3, a preliminary version of RELAP5/MOD3. The model was a three-dimensional representation of the K-Reactor water plenum and moderator tank. It included explicit representations of all six loops, which were based on the configuration of L-Reactor. A combination of features is recommended to ensure liquid inventory recovery for all break locations. Valve closure design performance for a break location in the short section of piping between the reactor concrete shield and the pump suction valve would benefit from the clamshell enclosing that section of piping. 7 refs., 10 figs., 2 tabs.

  18. An FPGA hardware/software co-design towards evolvable spiking neural networks for robotics application.

    PubMed

    Johnston, S P; Prasad, G; Maguire, L; McGinnity, T M

    2010-12-01

    This paper presents an approach that permits the effective hardware realization of a novel Evolvable Spiking Neural Network (ESNN) paradigm on Field Programmable Gate Arrays (FPGAs). The ESNN possesses a hybrid learning algorithm that consists of a Spike Timing Dependent Plasticity (STDP) mechanism fused with a Genetic Algorithm (GA). The design and implementation direction utilizes the latest advancements in FPGA technology to provide a partitioned hardware/software co-design solution. The approach achieves the maximum FPGA flexibility obtainable for the ESNN paradigm. The algorithm was applied as an embedded intelligent system robotic controller to solve an autonomous navigation and obstacle avoidance problem. PMID:21117269

  19. Study of the adaptability of existing hardware designs to a Pioneer Saturn/Uranus probe

    NASA Technical Reports Server (NTRS)

    1973-01-01

    The basic concept of designing a scientific entry probe for the expected range of environments at Saturn or Uranus and making the probe compatible with the interface constraints of the Pioneer spacecraft was investigated for launches in the early 1980's. It was found that the amount of hardware commonality between that used in the Pioneer Venus program and that for the Saturn/Uranus probe was approximately 85%. It is recommended that additional development studies be conducted to improve the hardware definitions of the probe design for the following: heat shield, battery, nose cap jettisoning, and thermal control insulation.

  20. Full chip correction of EUV design

    NASA Astrophysics Data System (ADS)

    Lorusso, G. F.; Hendrickx, E.; Fenger, G. L.; Niroomand, A.

    2010-04-01

    Extreme Ultraviolet Lithography (EUVL) is currently the most promising technology for advanced manufacturing nodes: it recently demonstrated the feasibility of 32nm and 22nm node devices, and pre-production tools are expected to be delivered by 2010. Generally speaking, EUVL is less in need of Optical Proximity Correction (OPC) as compared to 193nm lithography, and the device feasibility studies were indeed carried out with limited or no correction. However, a rigorous optical correction strategy and an appropriate Electronic Design Automation (EDA) infrastructure is critical to face the challenges of the 22nm node and beyond, and EUV-specific effects such as flare and shadowing have to be fully integrated in the correction flow and properly tested. This study aims to assess in detail the quality of a full chip optical correction for a EUV design, as well to discuss the available approaches to compensate for EUV-specific effects. Extensive data sets have been collected on the ASML EUV Alpha-Demo Tool (ADT) using the latest IMEC baseline resist Shin-Etsu SEVR59. In total about 1300 CD measurements at wafer level and 700 at mask level were used as input for model calibration and validation. The smallest feature size in the data set was 32nm. Both one-dimensional and two-dimensional structures through CD and pitch were measured. The mask used in this calibration exercise allowed the authors to modulate flare by varying tiling densities within the range expected in the final design. The OPC model was fitted and validated against the CD data collected on the EUV ADT. The shadowing effect was modeled by means of a single bias correction throughout the design. Horizontal and vertical features of different type through pitch and CD were used to calibrate the shadowing correction, and the extent of the validity of the single bias approach is discussed. In addition, the quality of the generated full-chip flare maps has been tested against experimental results, and the model

  1. Hardware-Efficient and Fully Autonomous Quantum Error Correction in Superconducting Circuits

    NASA Astrophysics Data System (ADS)

    Kapit, Eliot

    2016-04-01

    Superconducting qubits are among the most promising platforms for building a quantum computer. However, individual qubit coherence times are not far past the scalability threshold for quantum error correction, meaning that millions of physical devices would be required to construct a useful quantum computer. Consequently, further increases in coherence time are very desirable. In this Letter, we blueprint a simple circuit consisting of two transmon qubits and two additional lossy qubits or resonators, which is passively protected against all single-qubit quantum error channels through a combination of continuous driving and engineered dissipation. Photon losses are rapidly corrected through two-photon drive fields implemented with driven superconducting quantum interference device couplings, and dephasing from random potential fluctuations is heavily suppressed by the drive fields used to implement the multiqubit Hamiltonian. Comparing our theoretical model to published noise estimates from recent experiments on flux and transmon qubits, we find that logical state coherence could be improved by a factor of 40 or more compared to the individual qubit T1 and T2 using this technique. We thus demonstrate that there is substantial headroom for improving the coherence of modern superconducting qubits with a fairly modest increase in device complexity.

  2. Hardware-Efficient and Fully Autonomous Quantum Error Correction in Superconducting Circuits.

    PubMed

    Kapit, Eliot

    2016-04-15

    Superconducting qubits are among the most promising platforms for building a quantum computer. However, individual qubit coherence times are not far past the scalability threshold for quantum error correction, meaning that millions of physical devices would be required to construct a useful quantum computer. Consequently, further increases in coherence time are very desirable. In this Letter, we blueprint a simple circuit consisting of two transmon qubits and two additional lossy qubits or resonators, which is passively protected against all single-qubit quantum error channels through a combination of continuous driving and engineered dissipation. Photon losses are rapidly corrected through two-photon drive fields implemented with driven superconducting quantum interference device couplings, and dephasing from random potential fluctuations is heavily suppressed by the drive fields used to implement the multiqubit Hamiltonian. Comparing our theoretical model to published noise estimates from recent experiments on flux and transmon qubits, we find that logical state coherence could be improved by a factor of 40 or more compared to the individual qubit T_{1} and T_{2} using this technique. We thus demonstrate that there is substantial headroom for improving the coherence of modern superconducting qubits with a fairly modest increase in device complexity. PMID:27127945

  3. When "Less is More": The Optimal Design of Language Laboratory Hardware.

    ERIC Educational Resources Information Center

    Kershaw, Gary; Boyd, Gary

    1980-01-01

    The results of a process of designing, building, and "de-bugging" two replacement language laboratory hardware systems at Concordia University (Montreal) are described. Because commercially available systems did not meet specifications within budgetary constraints, the systems were built by the university technical department. The systems replaced…

  4. The design of flight hardware: Organizational and technical ideas from the MITRE/WPI Shuttle Program

    NASA Technical Reports Server (NTRS)

    Looft, F. J.

    1986-01-01

    The Mitre Corporation of Bedford Mass. and the Worcester Polytechnic Institute are developing several experiments for a future Shuttle flight. Several design practices for the development of the electrical equipment for the flight hardware have been standardized. Some of the ideas are presented, not as hard and fast rules but rather in the interest of stimulating discussions for sharing such ideas.

  5. Design Considerations in Development of Minicomputer-Based Computer Aided Instructional Hardware Systems.

    ERIC Educational Resources Information Center

    Wells, C. H.

    A minicomputer-based computer-assisted instructional (CAI) system was designed at the University of Texas Medical Branch in an attempt to lower both the excessive hardware costs and the inordinate amount of time required for the preparation of each hour of instructional material associated with traditional CAI systems. A prototype system with an…

  6. A Design of the Signal Processing Hardware Platform for Communication Systems

    NASA Astrophysics Data System (ADS)

    Lee, Byung Wook; Cho, Sung Ho

    In this letter, an efficient hardware platform for the digital signal processing for OFDM communication systems is presented. The hardware platform consists of a single FPGA having 900K gates, two DSPs with maximum 8,000 MIPS at 1GHz clock, 2-channel ADC and DAC supporting maximum 125MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16d software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.

  7. Test Hardware Design for Flight-Like Operation of Advanced Stirling Convertors

    NASA Technical Reports Server (NTRS)

    Oriti, Salvatore M.

    2012-01-01

    NASA Glenn Research Center (GRC) has been supporting development of the Advanced Stirling Radioisotope Generator (ASRG) since 2006. A key element of the ASRG project is providing life, reliability, and performance testing of the Advanced Stirling Convertor (ASC). For this purpose, the Thermal Energy Conversion branch at GRC has been conducting extended operation of a multitude of free-piston Stirling convertors. The goal of this effort is to generate long-term performance data (tens of thousands of hours) simultaneously on multiple units to build a life and reliability database. The test hardware for operation of these convertors was designed to permit in-air investigative testing, such as performance mapping over a range of environmental conditions. With this, there was no requirement to accurately emulate the flight hardware. For the upcoming ASC-E3 units, the decision has been made to assemble the convertors into a flight-like configuration. This means the convertors will be arranged in the dual-opposed configuration in a housing that represents the fit, form, and thermal function of the ASRG. The goal of this effort is to enable system level tests that could not be performed with the traditional test hardware at GRC. This offers the opportunity to perform these system-level tests much earlier in the ASRG flight development, as they would normally not be performed until fabrication of the qualification unit. This paper discusses the requirements, process, and results of this flight-like hardware design activity.

  8. Test Hardware Design for Flightlike Operation of Advanced Stirling Convertors (ASC-E3)

    NASA Technical Reports Server (NTRS)

    Oriti, Salvatore M.

    2012-01-01

    NASA Glenn Research Center (GRC) has been supporting development of the Advanced Stirling Radioisotope Generator (ASRG) since 2006. A key element of the ASRG project is providing life, reliability, and performance testing of the Advanced Stirling Convertor (ASC). For this purpose, the Thermal Energy Conversion branch at GRC has been conducting extended operation of a multitude of free-piston Stirling convertors. The goal of this effort is to generate long-term performance data (tens of thousands of hours) simultaneously on multiple units to build a life and reliability database. The test hardware for operation of these convertors was designed to permit in-air investigative testing, such as performance mapping over a range of environmental conditions. With this, there was no requirement to accurately emulate the flight hardware. For the upcoming ASC-E3 units, the decision has been made to assemble the convertors into a flight-like configuration. This means the convertors will be arranged in the dual-opposed configuration in a housing that represents the fit, form, and thermal function of the ASRG. The goal of this effort is to enable system level tests that could not be performed with the traditional test hardware at GRC. This offers the opportunity to perform these system-level tests much earlier in the ASRG flight development, as they would normally not be performed until fabrication of the qualification unit. This paper discusses the requirements, process, and results of this flight-like hardware design activity.

  9. A Comprehensive Reliability Methodology for Assessing Risk of Reusing Failed Hardware Without Corrective Actions with and Without Redundancy

    NASA Technical Reports Server (NTRS)

    Putcha, Chandra S.; Mikula, D. F. Kip; Dueease, Robert A.; Dang, Lan; Peercy, Robert L.

    1997-01-01

    This paper deals with the development of a reliability methodology to assess the consequences of using hardware, without failure analysis or corrective action, that has previously demonstrated that it did not perform per specification. The subject of this paper arose from the need to provide a detailed probabilistic analysis to calculate the change in probability of failures with respect to the base or non-failed hardware. The methodology used for the analysis is primarily based on principles of Monte Carlo simulation. The random variables in the analysis are: Maximum Time of Operation (MTO) and operation Time of each Unit (OTU) The failure of a unit is considered to happen if (OTU) is less than MTO for the Normal Operational Period (NOP) in which this unit is used. NOP as a whole uses a total of 4 units. Two cases are considered. in the first specialized scenario, the failure of any operation or system failure is considered to happen if any of the units used during the NOP fail. in the second specialized scenario, the failure of any operation or system failure is considered to happen only if any two of the units used during the MOP fail together. The probability of failure of the units and the system as a whole is determined for 3 kinds of systems - Perfect System, Imperfect System 1 and Imperfect System 2. in a Perfect System, the operation time of the failed unit is the same as that of the MTO. In an Imperfect System 1, the operation time of the failed unit is assumed as 1 percent of the MTO. In an Imperfect System 2, the operation time of the failed unit is assumed as zero. in addition, simulated operation time of failed units is assumed as 10 percent of the corresponding units before zero value. Monte Carlo simulation analysis is used for this study. Necessary software has been developed as part of this study to perform the reliability calculations. The results of the analysis showed that the predicted change in failure probability (P(sub F)) for the

  10. Object oriented design (OOD) in real-time hardware-in-the-loop (HWIL) simulations

    NASA Astrophysics Data System (ADS)

    Morris, Joe; Richard, Henri; Lowman, Alan; Youngren, Rob

    2006-05-01

    Using Object Oriented Design (OOD) concepts in AMRDEC's Hardware-in-the Loop (HWIL) real-time simulations allows the user to interchange parts of the simulation to meet test requirements. A large-scale three-spectral band simulator connected via a high speed reflective memory ring for time-critical data transfers to PC controllers connected by non real-time Ethernet protocols is used to separate software objects from logical entities close to their respective controlled hardware. Each standalone object does its own dynamic initialization, real-time processing, and end of run processing; therefore it can be easily maintained and updated. A Resource Allocation Program (RAP) is also utilized along with a device table to allocate, organize, and document the communication protocol between the software and hardware components. A GUI display program lists all allocations and deallocations of HWIL memory and hardware resources. This interactive program is also used to clean up defunct allocations of dead processes. Three examples are presented using the OOD and RAP concepts. The first is the control of an ACUTRONICS built three-axis flight table using the same control for calibration and real-time functions. The second is the transportability of a six-degree-of-freedom (6-DOF) simulation from an Onyx residence to a Linux-PC. The third is the replacement of the 6-DOF simulation with a replay program to drive the facility with archived run data for demonstration or analysis purposes.

  11. The design and hardware implementation of a low-power real-time seizure detection algorithm

    NASA Astrophysics Data System (ADS)

    Raghunathan, Shriram; Gupta, Sumeet K.; Ward, Matthew P.; Worth, Robert M.; Roy, Kaushik; Irazoqui, Pedro P.

    2009-10-01

    Epilepsy affects more than 1% of the world's population. Responsive neurostimulation is emerging as an alternative therapy for the 30% of the epileptic patient population that does not benefit from pharmacological treatment. Efficient seizure detection algorithms will enable closed-loop epilepsy prostheses by stimulating the epileptogenic focus within an early onset window. Critically, this is expected to reduce neuronal desensitization over time and lead to longer-term device efficacy. This work presents a novel event-based seizure detection algorithm along with a low-power digital circuit implementation. Hippocampal depth-electrode recordings from six kainate-treated rats are used to validate the algorithm and hardware performance in this preliminary study. The design process illustrates crucial trade-offs in translating mathematical models into hardware implementations and validates statistical optimizations made with empirical data analyses on results obtained using a real-time functioning hardware prototype. Using quantitatively predicted thresholds from the depth-electrode recordings, the auto-updating algorithm performs with an average sensitivity and selectivity of 95.3 ± 0.02% and 88.9 ± 0.01% (mean ± SEα = 0.05), respectively, on untrained data with a detection delay of 8.5 s [5.97, 11.04] from electrographic onset. The hardware implementation is shown feasible using CMOS circuits consuming under 350 nW of power from a 250 mV supply voltage from simulations on the MIT 180 nm SOI process.

  12. Skylab SO71/SO72 circadian periodicity experiment. [experimental design and checkout of hardware

    NASA Technical Reports Server (NTRS)

    Fairchild, M. K.; Hartmann, R. A.

    1973-01-01

    The circadian rhythm hardware activities from 1965 through 1973 are considered. A brief history of the programs leading to the development of the combined Skylab SO71/SO72 Circadian Periodicity Experiment (CPE) is given. SO71 is the Skylab experiment number designating the pocket mouse circadian experiment, and SO72 designates the vinegar gnat circadian experiment. Final design modifications and checkout of the CPE, integration testing with the Apollo service module CSM 117 and the launch preparation and support tasks at Kennedy Space Center are reported.

  13. Accelerating a MPEG-4 video decoder through custom software/hardware co-design

    NASA Astrophysics Data System (ADS)

    Díaz, Jorge L.; Barreto, Dacil; García, Luz; Marrero, Gustavo; Carballo, Pedro P.; Núñez, Antonio

    2007-05-01

    In this paper we present a novel methodology to accelerate an MPEG-4 video decoder using software/hardware co-design for wireless DAB/DMB networks. Software support includes the services provided by the embedded kernel μC/OS-II, and the application tasks mapped to software. Hardware support includes several custom co-processors and a communication architecture with bridges to the main system bus and with a dual port SRAM. Synchronization among tasks is achieved at two levels, by a hardware protocol and by kernel level scheduling services. Our reference application is an MPEG-4 video decoder composed of several software functions and written using a special C++ library named CASSE. Profiling and space exploration techniques were used previously over the Advanced Simple Profile (ASP) MPEG-4 decoder to determinate the best HW/SW partition developed here. This research is part of the ARTEMI project and its main goal is the establishment of methodologies for the design of real-time complex digital systems using Programmable Logic Devices with embedded microprocessors as target technology and the design of multimedia systems for broadcasting networks as reference application.

  14. A Principled Kernel Testbed for Hardware/Software Co-Design Research

    SciTech Connect

    Kaiser, Alex; Williams, Samuel; Madduri, Kamesh; Ibrahim, Khaled; Bailey, David; Demmel, James; Strohmaier, Erich

    2010-04-01

    Recently, advances in processor architecture have become the driving force for new programming models in the computing industry, as ever newer multicore processor designs with increasing number of cores are introduced on schedules regimented by marketing demands. As a result, collaborative parallel (rather than simply concurrent) implementations of important applications, programming languages, models, and even algorithms have been forced to adapt to these architectures to exploit the available raw performance. We believe that this optimization regime is flawed. In this paper, we present an alternate approach that, rather than starting with an existing hardware/software solution laced with hidden assumptions, defines the computational problems of interest and invites architects, researchers and programmers to implement novel hardware/software co-designed solutions. Our work builds on the previous ideas of computational dwarfs, motifs, and parallel patterns by selecting a representative set of essential problems for which we provide: An algorithmic description; scalable problem definition; illustrative reference implementations; verification schemes. This testbed will enable comparative research in areas such as parallel programming models, languages, auto-tuning, and hardware/software codesign. For simplicity, we focus initially on the computational problems of interest to the scientific computing community but proclaim the methodology (and perhaps a subset of the problems) as applicable to other communities. We intend to broaden the coverage of this problem space through stronger community involvement.

  15. Hardware design to accelerate PNG encoder for binary mask compression on FPGA

    NASA Astrophysics Data System (ADS)

    Kachouri, Rostom; Akil, Mohamed

    2015-02-01

    PNG (Portable Network Graphics) is a lossless compression method for real-world pictures. Since its specification, it continues to attract the interest of the image processing community. Indeed, PNG is an extensible file format for portable and well-compressed storage of raster images. In addition, it supports all of Black and White (binary mask), grayscale, indexed-color, and truecolor images. Within the framework of the Demat+ project which intend to propose a complete solution for storage and retrieval of scanned documents, we address in this paper a hardware design to accelerate the PNG encoder for binary mask compression on FPGA. For this, an optimized architecture is proposed as part of an hybrid software and hardware co-operating system. For its evaluation, the new designed PNG IP has been implemented on the ALTERA Arria II GX EP2AGX125EF35" FPGA. The experimental results show a good match between the achieved compression ratio, the computational cost and the used hardware resources.

  16. Thermal Performance of a Customized Multilayer Insulation (MLI). Design and Fabrication of Test Facility Hardware

    NASA Technical Reports Server (NTRS)

    Leonhard, K. E.

    1975-01-01

    The design, fabrication, and assembly of hardware for testing the performance of a customized multilayer insulation are discussed. System components described include the thermal payload simulator, the modified cryoshroud, and a tank back pressure control device designed to maintain a constant liquid boiling point during the thermal evaluation of the multilayer insulation. The thermal payload simulator will provide a constant temperature surface in the range of 20.5 to 417K (37 to 750R) for the insulated tank to view. The cryoshroud was modified to establish a low temperature black body cavity while limiting liquid hydrogen usage to a minimum feasible rate.

  17. Design and Control of Compliant Tensegrity Robots Through Simulation and Hardware Validation

    NASA Technical Reports Server (NTRS)

    Caluwaerts, Ken; Despraz, Jeremie; Iscen, Atil; Sabelhaus, Andrew P.; Bruce, Jonathan; Schrauwen, Benjamin; Sunspiral, Vytas

    2014-01-01

    To better understand the role of tensegrity structures in biological systems and their application to robotics, the Dynamic Tensegrity Robotics Lab at NASA Ames Research Center has developed and validated two different software environments for the analysis, simulation, and design of tensegrity robots. These tools, along with new control methodologies and the modular hardware components developed to validate them, are presented as a system for the design of actuated tensegrity structures. As evidenced from their appearance in many biological systems, tensegrity ("tensile-integrity") structures have unique physical properties which make them ideal for interaction with uncertain environments. Yet these characteristics, such as variable structural compliance, and global multi-path load distribution through the tension network, make design and control of bio-inspired tensegrity robots extremely challenging. This work presents the progress in using these two tools in tackling the design and control challenges. The results of this analysis includes multiple novel control approaches for mobility and terrain interaction of spherical tensegrity structures. The current hardware prototype of a six-bar tensegrity, code-named ReCTeR, is presented in the context of this validation.

  18. Design and control of compliant tensegrity robots through simulation and hardware validation

    PubMed Central

    Caluwaerts, Ken; Despraz, Jérémie; Işçen, Atıl; Sabelhaus, Andrew P.; Bruce, Jonathan; Schrauwen, Benjamin; SunSpiral, Vytas

    2014-01-01

    To better understand the role of tensegrity structures in biological systems and their application to robotics, the Dynamic Tensegrity Robotics Lab at NASA Ames Research Center, Moffett Field, CA, USA, has developed and validated two software environments for the analysis, simulation and design of tensegrity robots. These tools, along with new control methodologies and the modular hardware components developed to validate them, are presented as a system for the design of actuated tensegrity structures. As evidenced from their appearance in many biological systems, tensegrity (‘tensile–integrity’) structures have unique physical properties that make them ideal for interaction with uncertain environments. Yet, these characteristics make design and control of bioinspired tensegrity robots extremely challenging. This work presents the progress our tools have made in tackling the design and control challenges of spherical tensegrity structures. We focus on this shape since it lends itself to rolling locomotion. The results of our analyses include multiple novel control approaches for mobility and terrain interaction of spherical tensegrity structures that have been tested in simulation. A hardware prototype of a spherical six-bar tensegrity, the Reservoir Compliant Tensegrity Robot, is used to empirically validate the accuracy of simulation. PMID:24990292

  19. Design and control of compliant tensegrity robots through simulation and hardware validation.

    PubMed

    Caluwaerts, Ken; Despraz, Jérémie; Işçen, Atıl; Sabelhaus, Andrew P; Bruce, Jonathan; Schrauwen, Benjamin; SunSpiral, Vytas

    2014-09-01

    To better understand the role of tensegrity structures in biological systems and their application to robotics, the Dynamic Tensegrity Robotics Lab at NASA Ames Research Center, Moffett Field, CA, USA, has developed and validated two software environments for the analysis, simulation and design of tensegrity robots. These tools, along with new control methodologies and the modular hardware components developed to validate them, are presented as a system for the design of actuated tensegrity structures. As evidenced from their appearance in many biological systems, tensegrity ('tensile-integrity') structures have unique physical properties that make them ideal for interaction with uncertain environments. Yet, these characteristics make design and control of bioinspired tensegrity robots extremely challenging. This work presents the progress our tools have made in tackling the design and control challenges of spherical tensegrity structures. We focus on this shape since it lends itself to rolling locomotion. The results of our analyses include multiple novel control approaches for mobility and terrain interaction of spherical tensegrity structures that have been tested in simulation. A hardware prototype of a spherical six-bar tensegrity, the Reservoir Compliant Tensegrity Robot, is used to empirically validate the accuracy of simulation. PMID:24990292

  20. Radiation Mitigation and Power Optimization Design Tools for Reconfigurable Hardware in Orbit

    NASA Technical Reports Server (NTRS)

    French, Matthew; Graham, Paul; Wirthlin, Michael; Wang, Li; Larchev, Gregory

    2005-01-01

    The Reconfigurable Hardware in Orbit (RHinO)project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. In the second year of the project, design tools that leverage an established FPGA design environment have been created to visualize and analyze an FPGA circuit for radiation weaknesses and power inefficiencies. For radiation, a single event Upset (SEU) emulator, persistence analysis tool, and a half-latch removal tool for Xilinx/Virtex-II devices have been created. Research is underway on a persistence mitigation tool and multiple bit upsets (MBU) studies. For power, synthesis level dynamic power visualization and analysis tools have been completed. Power optimization tools are under development and preliminary test results are positive.

  1. Combined Cycle Engine Large-Scale Inlet for Mode Transition Experiments: System Identification Rack Hardware Design

    NASA Technical Reports Server (NTRS)

    Thomas, Randy; Stueber, Thomas J.

    2013-01-01

    The System Identification (SysID) Rack is a real-time hardware-in-the-loop data acquisition (DAQ) and control instrument rack that was designed and built to support inlet testing in the NASA Glenn Research Center 10- by 10-Foot Supersonic Wind Tunnel. This instrument rack is used to support experiments on the Combined-Cycle Engine Large-Scale Inlet for Mode Transition Experiment (CCE? LIMX). The CCE?LIMX is a testbed for an integrated dual flow-path inlet configuration with the two flow paths in an over-and-under arrangement such that the high-speed flow path is located below the lowspeed flow path. The CCE?LIMX includes multiple actuators that are designed to redirect airflow from one flow path to the other; this action is referred to as "inlet mode transition." Multiple phases of experiments have been planned to support research that investigates inlet mode transition: inlet characterization (Phase-1) and system identification (Phase-2). The SysID Rack hardware design met the following requirements to support Phase-1 and Phase-2 experiments: safely and effectively move multiple actuators individually or synchronously; sample and save effector control and position sensor feedback signals; automate control of actuator positioning based on a mode transition schedule; sample and save pressure sensor signals; and perform DAQ and control processes operating at 2.5 KHz. This document describes the hardware components used to build the SysID Rack including their function, specifications, and system interface. Furthermore, provided in this document are a SysID Rack effectors signal list (signal flow); system identification experiment setup; illustrations indicating a typical SysID Rack experiment; and a SysID Rack performance overview for Phase-1 and Phase-2 experiments. The SysID Rack described in this document was a useful tool to meet the project objectives.

  2. Interim Service ISDN Satellite (ISIS) hardware experiment development for advanced ISDN satellite designs and experiments

    NASA Technical Reports Server (NTRS)

    Pepin, Gerard R.

    1992-01-01

    The Interim Service Integrated Service Digital Network (ISDN) Satellite (ISIS) Hardware Experiment Development for Advanced Satellite Designs describes the development of the ISDN Satellite Terminal Adapter (ISTA) capable of translating ISDN protocol traffic into Time Division Multiple Access (TDMA) signals for use by a communications satellite. The ISTA connects the Type 1 Network Termination (NT1) via the U-interface on the line termination side of the CPE to the RS-499 interface for satellite uplink. The same ISTA converts in the opposite direction the RS-499 to U-interface data with a simple switch setting.

  3. Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology

    NASA Astrophysics Data System (ADS)

    Lata Murotiya, Sneh; Gupta, Anu

    2016-05-01

    This paper proposes a hardware-efficient low-power 2-bit ternary arithmetic logic unit (TALU) design in carbon nano tube field effect transistor technology. The proposed TALU architecture combines adder-subtractor and Ex-OR cell in one cell, thereby reducing the number of transistors by 71% in comparison with other TALU architecture. Further, the proposed TALU is optimised at transistor level with a new pass-transistor logic-based encoder circuit. Hspice simulation results show that the proposed design attains great advantages in power and power-delay product for addition and multiplication operations than reported designs. For instant, at power supply of 0.9 V, the proposed TALU consumes on average 91% and 95% less energy compared to their existing counterparts, for addition and multiplication operations, respectively.

  4. Color correction strategies in optical design

    NASA Astrophysics Data System (ADS)

    Pfisterer, Richard N.; Vorndran, Shelby D.

    2014-12-01

    An overview of color correction strategies is presented. Starting with basic first-order aberration theory, we identify known color corrected solutions for doublets and triplets. Reviewing the modern approaches of Robb-Mercado, Rayces-Aguilar, and C. de Albuquerque et al, we find that they confirm the existence of glass combinations for doublets and triplets that yield color corrected solutions that we already know exist. Finally we explore the use of the y, ӯ diagram in conjunction with aberration theory to identify the solution space of glasses capable of leading to color corrected solutions in arbitrary optical systems.

  5. A processor for MPEG decoder SOC: a software/hardware co-design approach

    NASA Astrophysics Data System (ADS)

    Yu, Guojun; Yao, Qingdong; Liu, Peng; Jiang, Zhidi; Li, Fuping

    2005-03-01

    Media processing such as real-time compression and decompression of video signal is now expected to be the driving force in the evolution of media processor. In this paper, a hardware and software co-design approach is introduced for a 32-bit media processor: MediaDsp3201 (briefly, MD32), which is realized in 0.18μm TSMC, 200MHz and can achieve 200 million multiply-accumulate (MAC) operations per second. In our design, we have emerged RISC and DSP into one processor (RISC/DSP). Based on the analysis of inherent characteristics of video processing algorithms, media enhancement instructions are adopted into MD32"instruction set. The media extension instructions are physically realized in the processor core, and improves video processing performance effectively with negligible additional hardware cost (2.7%). Considering the high complexity of the operation for media instructions, technology named scalable super pipeline is used to resolve problem of the time delay of pipeline stage (mainly EX stage). Simulation results show that our method can reduce more than 31% and 23% instructions for IDCT compared to MMX and SSE"s implementation and 40% for MC compared to MMX"s implementation.

  6. VLSI realization of learning vector quantization with hardware/software co-design for different applications

    NASA Astrophysics Data System (ADS)

    An, Fengwei; Akazawa, Toshinobu; Yamasaki, Shogo; Chen, Lei; Jürgen Mattausch, Hans

    2015-04-01

    This paper reports a VLSI realization of learning vector quantization (LVQ) with high flexibility for different applications. It is based on a hardware/software (HW/SW) co-design concept for on-chip learning and recognition and designed as a SoC in 180 nm CMOS. The time consuming nearest Euclidean distance search in the LVQ algorithm’s competition layer is efficiently implemented as a pipeline with parallel p-word input. Since neuron number in the competition layer, weight values, input and output number are scalable, the requirements of many different applications can be satisfied without hardware changes. Classification of a d-dimensional input vector is completed in n × \\lceil d/p \\rceil + R clock cycles, where R is the pipeline depth, and n is the number of reference feature vectors (FVs). Adjustment of stored reference FVs during learning is done by the embedded 32-bit RISC CPU, because this operation is not time critical. The high flexibility is verified by the application of human detection with different numbers for the dimensionality of the FVs.

  7. A hardware-software co-design approach to a JPEG encoder design for a planetary micro-rover application

    NASA Astrophysics Data System (ADS)

    Sarma, S.; Udupa, S.; Bhardwaj, K. M.; Parameswaran, K.; Malik, N. K.

    2011-01-01

    Micro-rovers aimed with the objective of planetary exploration of moons and heavenly bodies are becoming focus of many space missions. These micro-rover missions face hard challenges of harsh environment and resource constraints such as power and transmission bandwidth. The image data collected by the on-board cameras are often not possible to transmit to ground due to low bandwidth or adequate transmission duration. The JPEG image compression standard that is developed by the Joint Photographic Experts Group committee for use in compressing digital images and full color photographic images is ubiquitous and is a useful solution to the problem. In this paper, a hardware-software based co-design approach is presented with the aim to implement a JPEG encoder for reducing the transmission bandwidth requirement of a planetary micro-rover. A pipelined hardware architecture of the JPEG encoder requiring reduced hardware resources and power is designed for PowerPC and MIL-1750 processor interface and its performance and resource utilization using standard images of various sizes and quality settings for both these processor architecture is compared. Results are substantiated using extensive simulation and RTL implementation in FPGA. Based on these studies an efficient architecture is arrived at for use in a planetary microrover for future exploration by an Indian moon mission.

  8. Preliminary design of flight hardware for two-phase fluid research

    NASA Technical Reports Server (NTRS)

    Hustvedt, D. C.; Oonk, R. L.

    1982-01-01

    This study defined the preliminary designs of flight software for the Space Shuttle Orbiter for three two-phase fluid research experiments: (1) liquid reorientation - to study the motion of liquid in tanks subjected to small accelerations; (2) pool boiling - to study low-gravity boiling from horizontal cylinders; and (3) flow boiling - to study low-gravity forced flow boiling heat transfer and flow phenomena in a heated horizontal tube. The study consisted of eight major tasks: reassessment of the existing experiment designs, assessment of the Spacelab facility approach, assessment of the individual carry-on approach, selection of the preferred approach, preliminary design of flight hardware, safety analysis, preparation of a development plan, estimates of detailed design, fabrication and ground testing costs. The most cost effective design approach for the experiments is individual carry-ons in the Orbiter middeck. The experiments were designed to fit into one or two middeck lockers. Development schedules for the detailed design, fabrication and ground testing ranged from 15 1/2 to 18 months. Minimum costs (in 1981 dollars) ranged from $463K for the liquid reorientation experiment to $998K for the pool boiling experiment.

  9. Design of OLED gamma correction system based on the LUT

    NASA Astrophysics Data System (ADS)

    Tai, Yonghang; Yun, Lijun; Shi, Junsheng; Chen, Zaiqing; Li, Qiong

    2011-11-01

    Gamma correction is an important processing in reproduce images information realizing of video source. In order to improve the image sharpness of the OLED micro-display, a Gamma correction system was established to compensate for the gray scale distortion of the micro-display which is caused by the difference between the optical and electrical characteristic property. Based on the North OLEiD Company's 0.5 inch OLED, We proposed a Gamma correction system to converts 8 bits input signal into 9 bits displayed on the OLED. It used Microchip as the MCU and the master of the I2C serial bus, Development of the hardware system measurement verified the correction of VGA and CVBS video input and the picture quality also apparently improved.

  10. SensoTube: A Scalable Hardware Design Architecture for Wireless Sensors and Actuators Networks Nodes in the Agricultural Domain.

    PubMed

    Piromalis, Dimitrios; Arvanitis, Konstantinos

    2016-01-01

    Wireless Sensor and Actuators Networks (WSANs) constitute one of the most challenging technologies with tremendous socio-economic impact for the next decade. Functionally and energy optimized hardware systems and development tools maybe is the most critical facet of this technology for the achievement of such prospects. Especially, in the area of agriculture, where the hostile operating environment comes to add to the general technological and technical issues, reliable and robust WSAN systems are mandatory. This paper focuses on the hardware design architectures of the WSANs for real-world agricultural applications. It presents the available alternatives in hardware design and identifies their difficulties and problems for real-life implementations. The paper introduces SensoTube, a new WSAN hardware architecture, which is proposed as a solution to the various existing design constraints of WSANs. The establishment of the proposed architecture is based, firstly on an abstraction approach in the functional requirements context, and secondly, on the standardization of the subsystems connectivity, in order to allow for an open, expandable, flexible, reconfigurable, energy optimized, reliable and robust hardware system. The SensoTube implementation reference model together with its encapsulation design and installation are analyzed and presented in details. Furthermore, as a proof of concept, certain use cases have been studied in order to demonstrate the benefits of migrating existing designs based on the available open-source hardware platforms to SensoTube architecture. PMID:27527180

  11. Hardware synthesis from DDL description. [simulating a digital system for computerized design of large scale integrated circuits

    NASA Technical Reports Server (NTRS)

    Shiva, S. G.; Shah, A. M.

    1980-01-01

    The details of digital systems can be conveniently input into the design automation system by means of hardware description language (HDL). The computer aided design and test (CADAT) system at NASA MSFC is used for the LSI design. The digital design language (DDL) was selected as HDL for the CADAT System. DDL translator output can be used for the hardware implementation of the digital design. Problems of selecting the standard cells from the CADAT standard cell library to realize the logic implied by the DDL description of the system are addressed.

  12. Acoustical Testing Laboratory Developed to Support the Low-Noise Design of Microgravity Space Flight Hardware

    NASA Technical Reports Server (NTRS)

    Cooper, Beth A.

    2001-01-01

    The NASA John H. Glenn Research Center at Lewis Field has designed and constructed an Acoustical Testing Laboratory to support the low-noise design of microgravity space flight hardware. This new laboratory will provide acoustic emissions testing and noise control services for a variety of customers, particularly for microgravity space flight hardware that must meet International Space Station limits on noise emissions. These limits have been imposed by the space station to support hearing conservation, speech communication, and safety goals as well as to prevent noise-induced vibrations that could impact microgravity research data. The Acoustical Testing Laboratory consists of a 23 by 27 by 20 ft (height) convertible hemi/anechoic chamber and separate sound-attenuating test support enclosure. Absorptive 34-in. fiberglass wedges in the test chamber provide an anechoic environment down to 100 Hz. A spring-isolated floor system affords vibration isolation above 3 Hz. These criteria, along with very low design background levels, will enable the acquisition of accurate and repeatable acoustical measurements on test articles, up to a full space station rack in size, that produce very little noise. Removable floor wedges will allow the test chamber to operate in either a hemi/anechoic or anechoic configuration, depending on the size of the test article and the specific test being conducted. The test support enclosure functions as a control room during normal operations but, alternatively, may be used as a noise-control enclosure for test articles that require the operation of noise-generating test support equipment.

  13. Hybrid Modeling for Scenario-Based Evaluation of Failure Effects in Advanced Hardware-Software Designs

    NASA Technical Reports Server (NTRS)

    Malin, Jane T.; Fleming, Land; Throop, David

    2001-01-01

    This paper describes an incremental scenario-based simulation approach to evaluation of intelligent software for control and management of hardware systems. A hybrid continuous/discrete event simulation of the hardware dynamically interacts with the intelligent software in operations scenarios. Embedded anomalous conditions and failures in simulated hardware can lead to emergent software behavior and identification of missing or faulty software or hardware requirements. An approach is described for extending simulation-based automated incremental failure modes and effects analysis, to support concurrent evaluation of intelligent software and the hardware controlled by the software

  14. Design and Development of Multi-Purpose CCD Camera System with Thermoelectric Cooling: Hardware

    NASA Astrophysics Data System (ADS)

    Kang, Y.-W.; Byun, Y. I.; Rhee, J. H.; Oh, S. H.; Kim, D. K.

    2007-12-01

    We designed and developed a multi-purpose CCD camera system for three kinds of CCDs; KAF-0401E(768×512), KAF-1602E(1536×1024), KAF-3200E(2184×1472) made by KODAK Co.. The system supports fast USB port as well as parallel port for data I/O and control signal. The packing is based on two stage circuit boards for size reduction and contains built-in filter wheel. Basic hardware components include clock pattern circuit, A/D conversion circuit, CCD data flow control circuit, and CCD temperature control unit. The CCD temperature can be controlled with accuracy of approximately 0.4° C in the max. range of temperature, Δ 33° C. This CCD camera system has with readout noise 6 e^{-}, and system gain 5 e^{-}/ADU. A total of 10 CCD camera systems were produced and our tests show that all of them show passable performance.

  15. Structural Design Requirements and Factors of Safety for Spaceflight Hardware: For Human Spaceflight. Revision A

    NASA Technical Reports Server (NTRS)

    Bernstein, Karen S.; Kujala, Rod; Fogt, Vince; Romine, Paul

    2011-01-01

    This document establishes the structural requirements for human-rated spaceflight hardware including launch vehicles, spacecraft and payloads. These requirements are applicable to Government Furnished Equipment activities as well as all related contractor, subcontractor and commercial efforts. These requirements are not imposed on systems other than human-rated spacecraft, such as ground test articles, but may be tailored for use in specific cases where it is prudent to do so such as for personnel safety or when assets are at risk. The requirements in this document are focused on design rather than verification. Implementation of the requirements is expected to be described in a Structural Verification Plan (SVP), which should describe the verification of each structural item for the applicable requirements. The SVP may also document unique verifications that meet or exceed these requirements with NASA Technical Authority approval.

  16. Final Scientific/Technical Report for "Enabling Exascale Hardware and Software Design through Scalable System Virtualization"

    SciTech Connect

    Dinda, Peter August

    2015-03-17

    This report describes the activities, findings, and products of the Northwestern University component of the "Enabling Exascale Hardware and Software Design through Scalable System Virtualization" project. The purpose of this project has been to extend the state of the art of systems software for high-end computing (HEC) platforms, and to use systems software to better enable the evaluation of potential future HEC platforms, for example exascale platforms. Such platforms, and their systems software, have the goal of providing scientific computation at new scales, thus enabling new research in the physical sciences and engineering. Over time, the innovations in systems software for such platforms also become applicable to more widely used computing clusters, data centers, and clouds. This was a five-institution project, centered on the Palacios virtual machine monitor (VMM) systems software, a project begun at Northwestern, and originally developed in a previous collaboration between Northwestern University and the University of New Mexico. In this project, Northwestern (including via our subcontract to the University of Pittsburgh) contributed to the continued development of Palacios, along with other team members. We took the leadership role in (1) continued extension of support for emerging Intel and AMD hardware, (2) integration and performance enhancement of overlay networking, (3) connectivity with architectural simulation, (4) binary translation, and (5) support for modern Non-Uniform Memory Access (NUMA) hosts and guests. We also took a supporting role in support for specialized hardware for I/O virtualization, profiling, configurability, and integration with configuration tools. The efforts we led (1-5) were largely successful and executed as expected, with code and papers resulting from them. The project demonstrated the feasibility of a virtualization layer for HEC computing, similar to such layers for cloud or datacenter computing. For effort (3

  17. Hardware/software co-design of global cloud system resolving models

    NASA Astrophysics Data System (ADS)

    Wehner, Michael F.; Oliker, Leonid; Shalf, John; Donofrio, David; Drummond, Leroy A.; Heikes, Ross; Kamil, Shoaib; Kono, Celal; Miller, Norman; Miura, Hiroaki; Mohiyuddin, Marghoob; Randall, David; Yang, Woo-Sun

    2011-04-01

    We present an analysis of the performance aspects of an atmospheric general circulation model at the ultra-high resolution required to resolve individual cloud systems and describe alternative technological paths to realize the integration of such a model in the relatively near future. Due to a superlinear scaling of the computational burden dictated by the Courant stability criterion, the solution of the equations of motion dominate the calculation at these ultra-high resolutions. From this extrapolation, it is estimated that a credible kilometer scale atmospheric model would require a sustained computational rate of at least 28 Petaflop/s to provide scientifically useful climate simulations. Our design study portends an alternate strategy for practical power-efficient implementations of next-generation ultra-scale systems. We demonstrate that hardware/software co-design of low-power embedded processor technology could be exploited to design a custom machine tailored to ultra-high resolution climate model specifications at relatively affordable cost and power considerations. A strawman machine design is presented consisting of in excess of 20 million processing elements that effectively exploits forthcoming many-core chips. The system pushes the limits of domain decomposition to increase explicit parallelism, and suggests that functional partitioning of sub-components of the climate code (much like the coarse-grained partitioning of computation between the atmospheric, ocean, land, and ice components of current coupled models) may be necessary for future performance scaling.

  18. Real-time multi-dimensional processing hardware designs research activities

    SciTech Connect

    Current, W. . Dept. of Electrical Engineering and Computer Science)

    1990-10-31

    In this final report, we summarize some of our results from September 1989 to October 1990. The design, construction, and testing of a four-processor prototype multi-processor (RTP) board using TI TMS320C25 DSP chips has been completed and is reported upon in our separately submitted Final Report on the RADON TRANSFORM COMPUTER'' Project.'' The design of our fully custom CMOS VLSI chip has been completed. The chip has been designed, the layout completed, and the chip is now going through its final pre-fabrication simulations. We are now finishing the extensive detailed final documentation of the R/Bchip. This extensive documentation will be provided to Steve Azevedo when we have submitted the chip for fabrication. The present status of the custom chip design activity is summarized in Section II. Evaluations of the hardware requirements for fast filtering of data for filtered backprojection (item 3) have been completed and are summarized in our separately submitted Final Report on the RADON TRANSFORM COMPUTER'' Project.'' We briefly summarize the new custom CMOS VLSI unified Radon transform/backprojection IC architecture, layout, and simulated performance.

  19. Design and fabrication of an autonomous rendezvous and docking sensor using off-the-shelf hardware

    NASA Technical Reports Server (NTRS)

    Grimm, Gary E.; Bryan, Thomas C.; Howard, Richard T.; Book, Michael L.

    1991-01-01

    NASA Marshall Space Flight Center (MSFC) has developed and tested an engineering model of an automated rendezvous and docking sensor system composed of a video camera ringed with laser diodes at two wavelengths and a standard remote manipulator system target that has been modified with retro-reflective tape and 830 and 780 mm optical filters. TRW has provided additional engineering analysis, design, and manufacturing support, resulting in a robust, low cost, automated rendezvous and docking sensor design. We have addressed the issue of space qualification using off-the-shelf hardware components. We have also addressed the performance problems of increased signal to noise ratio, increased range, increased frame rate, graceful degradation through component redundancy, and improved range calibration. Next year, we will build a breadboard of this sensor. The phenomenology of the background scene of a target vehicle as viewed against earth and space backgrounds under various lighting conditions will be simulated using the TRW Dynamic Scene Generator Facility (DSGF). Solar illumination angles of the target vehicle and candidate docking target ranging from eclipse to full sun will be explored. The sensor will be transportable for testing at the MSFC Flight Robotics Laboratory (EB24) using the Dynamic Overhead Telerobotic Simulator (DOTS).

  20. Streamlined design and self reliant hardware for active control of precision space structures

    NASA Technical Reports Server (NTRS)

    Hyland, David C.; King, James A.; Phillips, Douglas J.

    1994-01-01

    Precision space structures may require active vibration control to satisfy critical performance requirements relating to line-of-sight pointing accuracy and the maintenance of precise, internal alignments. In order for vibration control concepts to become operational, it is necessary that their benefits be practically demonstrated in large scale ground-based experiments. A unique opportunity to carry out such demonstrations on a wide variety of experimental testbeds was provided by the NASA Control-Structure Integration (CSI) Guest Investigator (GI) Program. This report surveys the experimental results achieved by the Harris Corporation GI team on both Phases 1 and 2 of the program and provides a detailed description of Phase 2 activities. The Phase 1 results illustrated the effectiveness of active vibration control for space structures and demonstrated a systematic methodology for control design, implementation test. In Phase 2, this methodology was significantly streamlined to yield an on-site, single session design/test capability. Moreover, the Phase 2 research on adaptive neural control techniques made significant progress toward fully automated, self-reliant space structure control systems. As a further thrust toward productized, self-contained vibration control systems, the Harris Phase II activity concluded with experimental demonstration of new vibration isolation hardware suitable for a wide range of space-flight and ground-based commercial applications.The CSI GI Program Phase 1 activity was conducted under contract NASA1-18872, and the Phase 2 activity was conducted under NASA1-19372.

  1. Space Technology 5: Changing the Mission Design without Changing the Hardware

    NASA Technical Reports Server (NTRS)

    Carlisle, Candace C.; Webb, Evan H.; Slavin, James A.

    2005-01-01

    The Space Technology 5 (ST-5) Project is part of NASA's New Millennium Program. The validation objectives are to demonstrate the research-quality science capability of the ST-5 spacecraft; to operate the three spacecraft as a constellation; and to design, develop, test and flight-validate three capable micro-satellites with new technologies. A three-month flight demonstration phase is planned, beginning in March 2006. This year, the mission was re-planned for a Pegasus XL dedicated launch into an elliptical polar orbit (instead of the Originally-planned Geosynchronous Transfer Orbit.) The re-plan allows the mission to achieve the same high-level technology validation objectives with a different launch vehicle. The new mission design involves a revised science validation strategy, a new orbit and different communication strategy, while minimizing changes to the ST-5 spacecraft itself. The constellation operations concepts have also been refined. While the system engineers, orbit analysts, and operations teams were re-planning the mission, the implementation team continued to make progress on the flight hardware. Most components have been delivered, and the first spacecraft is well into integration and test.

  2. Hardware Design and Implementation of a Wavelet De-Noising Procedure for Medical Signal Preprocessing

    PubMed Central

    Chen, Szi-Wen; Chen, Yuan-Ho

    2015-01-01

    In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz. PMID:26501290

  3. Hardware design and implementation of a wavelet de-noising procedure for medical signal preprocessing.

    PubMed

    Chen, Szi-Wen; Chen, Yuan-Ho

    2015-01-01

    In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz. PMID:26501290

  4. Simulation verification techniques study: Simulation self test hardware design and techniques report

    NASA Technical Reports Server (NTRS)

    1974-01-01

    The final results are presented of the hardware verification task. The basic objectives of the various subtasks are reviewed along with the ground rules under which the overall task was conducted and which impacted the approach taken in deriving techniques for hardware self test. The results of the first subtask and the definition of simulation hardware are presented. The hardware definition is based primarily on a brief review of the simulator configurations anticipated for the shuttle training program. The results of the survey of current self test techniques are presented. The data sources that were considered in the search for current techniques are reviewed, and results of the survey are presented in terms of the specific types of tests that are of interest for training simulator applications. Specifically, these types of tests are readiness tests, fault isolation tests and incipient fault detection techniques. The most applicable techniques were structured into software flows that are then referenced in discussions of techniques for specific subsystems.

  5. Energy Efficient Engine: High-pressure compressor test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Howe, David C.; Marchant, R. D.

    1988-01-01

    The objective of the NASA Energy Efficient Engine program is to identify and verify the technology required to achieve significant reductions in fuel consumption and operating cost for future commercial gas turbine engines. The design and analysis is documented of the high pressure compressor which was tested as part of the Pratt and Whitney effort under the Energy Efficient Engine program. This compressor was designed to produce a 14:1 pressure ratio in ten stages with an adiabatic efficiency of 88.2 percent in the flight propulsion system. The corresponding expected efficiency for the compressor component test rig is 86.5 percent. Other performance goals are a surge margin of 20 percent, a corrected flow rate of 35.2 kg/sec (77.5 lb/sec), and a life of 20,000 missions and 30,000 hours. Low loss, highly loaded airfoils are used to increase efficiency while reducing the parts count. Active clearance control and case trenches in abradable strips over the blade tips are included in the compressor component design to further increase the efficiency potential. The test rig incorporates variable geometry stator vanes in all stages to permit maximum flexibility in developing stage-to-stage matching. This provision precluded active clearance control on the rear case of the test rig. Both the component and rig designs meet or exceed design requirements with the exception of life goals, which will be achievable with planned advances in materials technology.

  6. A parallel algorithm for error correction in high-throughput short-read data on CUDA-enabled graphics hardware.

    PubMed

    Shi, Haixiang; Schmidt, Bertil; Liu, Weiguo; Müller-Wittig, Wolfgang

    2010-04-01

    Emerging DNA sequencing technologies open up exciting new opportunities for genome sequencing by generating read data with a massive throughput. However, produced reads are significantly shorter and more error-prone compared to the traditional Sanger shotgun sequencing method. This poses challenges for de novo DNA fragment assembly algorithms in terms of both accuracy (to deal with short, error-prone reads) and scalability (to deal with very large input data sets). In this article, we present a scalable parallel algorithm for correcting sequencing errors in high-throughput short-read data so that error-free reads can be available before DNA fragment assembly, which is of high importance to many graph-based short-read assembly tools. The algorithm is based on spectral alignment and uses the Compute Unified Device Architecture (CUDA) programming model. To gain efficiency we are taking advantage of the CUDA texture memory using a space-efficient Bloom filter data structure for spectrum membership queries. We have tested the runtime and accuracy of our algorithm using real and simulated Illumina data for different read lengths, error rates, input sizes, and algorithmic parameters. Using a CUDA-enabled mass-produced GPU (available for less than US$400 at any local computer outlet), this results in speedups of 12-84 times for the parallelized error correction, and speedups of 3-63 times for both sequential preprocessing and parallelized error correction compared to the publicly available Euler-SR program. Our implementation is freely available for download from http://cuda-ec.sourceforge.net . PMID:20426693

  7. The design of a hardware testing system for the D Zero Detector

    SciTech Connect

    Angstadt, R.; Johnson, M.; Martin, M.; Matulik, M.; Utes, M.

    1991-11-01

    Testing a system as large as the D Zero data acquisition system is difficult. This paper describes the use of IBM compatible personal computers in a hardware test system that can run on any size system from an engineer`s test bench to the entire subsystem in the D Zero Detector. The test system uses a PC to VME bus interface for the local testing and the Token Ring network for more global testing. This system has been implemented for several different hardware systems in D Zero.

  8. Designing multifocal corneal models to correct presbyopia by laser ablation

    NASA Astrophysics Data System (ADS)

    Alarcón, Aixa; Anera, Rosario G.; Del Barco, Luis Jiménez; Jiménez, José R.

    2012-01-01

    Two multifocal corneal models and an aspheric model designed to correct presbyopia by corneal photoablation were evaluated. The design of each model was optimized to achieve the best visual quality possible for both near and distance vision. In addition, we evaluated the effect of myosis and pupil decentration on visual quality. The corrected model with the central zone for near vision provides better results since it requires less ablated corneal surface area, permits higher addition values, presents stabler visual quality with pupil-size variations and lower high-order aberrations.

  9. [Design and implementation of real-time processing platform for movement error correction of hyperspectrual imaging].

    PubMed

    Yu, Tao; Hu, Bing-liang; Gao, Xiao-hui; Wei, Ru-yi; Jing, Juan-juan

    2012-08-01

    The approach that deals with compressed and packed image data transmitted from satellite to the ground is too slow for real-time application occasion, it also has huge image, multi-processing step and complexity recovery arithmetic synchronously, so it is urgent to build accurate and fast data processing platform for real-time processing. For the moment, the platform for data recovery and error correction is much less, the so-called successful platform may directly affect the effect of target detection and identification because of processing speed, precision, flexibility, configuration and upgrade. The platform we build is to set spatial modulation spectrometer as the research goal, We design and implement a hardware platform based on Xilinx Virtex-5 FPGA, It is combined with ISE IP soft-core resources which is configurable, high-precision and flexible by focusing on analyzing key aspects of the hardware platform. And the relevant test data were drawn, then a good way for spectrum recovery and error correction was explored. PMID:23156797

  10. Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Biagioni, A.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Rossetti, D.; Simula, F.; Tosoratto, L.; Vicini, P.

    2015-12-01

    In the attempt to develop an interconnection architecture optimized for hybrid HPC systems dedicated to scientific computing, we designed APEnet+, a point-to-point, low-latency and high-performance network controller supporting 6 fully bidirectional off-board links over a 3D torus topology. The first release of APEnet+ (named V4) was a board based on a 40 nm Altera FPGA, integrating 6 channels at 34 Gbps of raw bandwidth per direction and a PCIe Gen2 x8 host interface. It has been the first-of-its-kind device to implement an RDMA protocol to directly read/write data from/to Fermi and Kepler NVIDIA GPUs using NVIDIA peer-to-peer and GPUDirect RDMA protocols, obtaining real zero-copy GPU-to-GPU transfers over the network. The latest generation of APEnet+ systems (now named V5) implements a PCIe Gen3 x8 host interface on a 28 nm Altera Stratix V FPGA, with multi-standard fast transceivers (up to 14.4 Gbps) and an increased amount of configurable internal resources and hardware IP cores to support main interconnection standard protocols. Herein we present the APEnet+ V5 architecture, the status of its hardware and its system software design. Both its Linux Device Driver and the low-level libraries have been redeveloped to support the PCIe Gen3 protocol, introducing optimizations and solutions based on hardware/software co-design.

  11. Design of Application-Specific Instructions and Hardware Accelerator for Reed-Solomon Codecs

    NASA Astrophysics Data System (ADS)

    Lee, Jung H.; Lee, Jaesung; Sunwoo, Myung H.

    2003-12-01

    This paper presents new application-specific digital signal processor (ASDSP) instructions and their hardware accelerator to efficiently implement Reed-Solomon (RS) encoding and decoding, which is one of the most widely used forward error control (FEC) algorithms. The proposed ASDSP architecture can implement various programmable primitive polynomials, and thus, hardwired RS codecs can be replaced. The new instructions and their hardware accelerator perform Galois field (GF) operations using the proposed GF multiplier and adder. Therefore, the proposed digital signal processor (DSP) architecture can significantly reduce the number of clock cycles compared with existing DSP chips. The proposed GF multiplier was implemented using the Faraday 0.25[InlineEquation not available: see fulltext.]m standard cell library and it can perform RS decoding at a rate up to 228.1 Mbps at 130 MHz.

  12. Design of the high-speed framing, FEC, and interleaving hardware used in a 5.4km free-space optical communication experiment

    NASA Astrophysics Data System (ADS)

    Greco, Joseph A.

    2009-08-01

    The forward error correction (FEC) and interleaver realizations used in a 5.4 km horizontal-path link experiment incorporated several unique elements that were specifically tailored to address turbulence-induced fading. To facilitate optimization studies, this hardware was designed to afford a high degree of flexibility in the FEC code structure and interleaver length. An essential aspect of this structure was the standards-compliant client interface, which provided seamless connectivity to fiber-based terrestrial networks. Through the use of an OTU1 (2.667 Gbaud) architecture with nonstandard interleaving, error-free transmission was achieved in the presence of strong scintillation that produced fade events that frequently exceeded 10 ms in duration. This work was sponsored by the Department of Defense, RRCO DDR&E, under Air Force Contract FA8721-05-C-0002. Opinions, interpretations, conclusions and recommendations are those of the authors and are not necessarily endorsed by the United States Government.

  13. Hardware Controller DNA Synthesizer

    Energy Science and Technology Software Center (ESTSC)

    1995-07-27

    The program controls the operation of various hardware components of an automatic 12-channel parrallel oligosynthesizer. This involves accepting information regarding the DNA sequence to be generated and converting this into a series of instructions to I/O ports to actuate the appropriate hardware components. The design and function of the software is specific to a particular hardware platform and has no utility for controlling other configurations.

  14. Study of orbit correction for eRHIC FFAG design

    SciTech Connect

    Liu, C.; Hao, Y.; Litvinenko, V.; Meot, F.; Minty, M.; Ptitsyn, V.; Trbojevic, D.

    2015-05-03

    The unique feature of the orbits in the eRHIC Fixed Field Alternating Gradient (FFAG) design is that multiple accelerating and decelerating bunches pass through the same magnets with different horizontal offsets. Therefore, it is critical for the eRHIC FFAG to correct multiple orbits in the same vacuum pipe for better spin transmission and alignment of colliding beams. In this report, the effects on orbits from multiple error sources will be studied. The orbit correction method will be described and results will be presented.

  15. Design and hardware-in-loop implementation of collision avoidance algorithms for heavy commercial road vehicles

    NASA Astrophysics Data System (ADS)

    Rajaram, Vignesh; Subramanian, Shankar C.

    2016-07-01

    An important aspect from the perspective of operational safety of heavy road vehicles is the detection and avoidance of collisions, particularly at high speeds. The development of a collision avoidance system is the overall focus of the research presented in this paper. The collision avoidance algorithm was developed using a sliding mode controller (SMC) and compared to one developed using linear full state feedback in terms of performance and controller effort. Important dynamic characteristics such as load transfer during braking, tyre-road interaction, dynamic brake force distribution and pneumatic brake system response were considered. The effect of aerodynamic drag on the controller performance was also studied. The developed control algorithms have been implemented on a Hardware-in-Loop experimental set-up equipped with the vehicle dynamic simulation software, IPG/TruckMaker®. The evaluation has been performed for realistic traffic scenarios with different loading and road conditions. The Hardware-in-Loop experimental results showed that the SMC and full state feedback controller were able to prevent the collision. However, when the discrepancies in the form of parametric variations were included, the SMC provided better results in terms of reduced stopping distance and lower controller effort compared to the full state feedback controller.

  16. Groundwater modeling in RCRA assessment, corrective action design and evaluation

    SciTech Connect

    Rybak, I.; Henley, W.

    1995-12-31

    Groundwater modeling was conducted to design, implement, modify, and terminate corrective action at several RCRA sites in EPA Region 4. Groundwater flow, contaminant transport and unsaturated zone air flow models were used depending on the complexity of the site and the corrective action objectives. Software used included Modflow, Modpath, Quickflow, Bioplume 2, and AIR3D. Site assessment data, such as aquifer properties, site description, and surface water characteristics for each facility were used in constructing the models and designing the remedial systems. Modeling, in turn, specified additional site assessment data requirements for the remedial system design. The specific purpose of computer modeling is discussed with several case studies. These consist, among others, of the following: evaluation of the mechanism of the aquifer system and selection of a cost effective remedial option, evaluation of the capture zone of a pumping system, prediction of the system performance for different and difficult hydrogeologic settings, evaluation of the system performance, and trouble-shooting for the remedial system operation. Modeling is presented as a useful tool for corrective action system design, performance, evaluation, and trouble-shooting. The case studies exemplified the integration of diverse data sources, understanding the mechanism of the aquifer system, and evaluation of the performance of alternative remediation systems in a cost-effective manner. Pollutants of concern include metals and PAHs.

  17. SIMPL Systems, or: Can We Design Cryptographic Hardware without Secret Key Information?

    NASA Astrophysics Data System (ADS)

    Rührmair, Ulrich

    This paper discusses a new cryptographic primitive termed SIMPL system. Roughly speaking, a SIMPL system is a special type of Physical Unclonable Function (PUF) which possesses a binary description that allows its (slow) public simulation and prediction. Besides this public key like functionality, SIMPL systems have another advantage: No secret information is, or needs to be, contained in SIMPL systems in order to enable cryptographic protocols - neither in the form of a standard binary key, nor as secret information hidden in random, analog features, as it is the case for PUFs. The cryptographic security of SIMPLs instead rests on (i) a physical assumption on their unclonability, and (ii) a computational assumption regarding the complexity of simulating their output. This novel property makes SIMPL systems potentially immune against many known hardware and software attacks, including malware, side channel, invasive, or modeling attacks.

  18. Design of a hardware track finder (Fast Tracker) for the ATLAS trigger

    NASA Astrophysics Data System (ADS)

    Cavaliere, V.; Adelman, J.; Albicocco, P.; Alison, J.; Ancu, L. S.; Anderson, J.; Andari, N.; Andreani, A.; Andreazza, A.; Annovi, A.; Antonelli, M.; Asbah, N.; Atkinson, M.; Baines, J.; Barberio, E.; Beccherle, R.; Beretta, M.; Bertolucci, F.; Biesuz, N. V.; Blair, R.; Bogdan, M.; Boveia, A.; Britzger, D.; Bryant, P.; Burghgrave, B.; Calderini, G.; Camplani, A.; Cavasinni, V.; Chakraborty, D.; Chang, P.; Cheng, Y.; Citraro, S.; Citterio, M.; Crescioli, F.; Dawe, N.; Dell'Orso, M.; Donati, S.; Dondero, P.; Drake, G.; Gadomski, S.; Gatta, M.; Gentsos, C.; Giannetti, P.; Gkaitatzis, S.; Gramling, J.; Howarth, J. W.; Iizawa, T.; Ilic, N.; Jiang, Z.; Kaji, T.; Kasten, M.; Kawaguchi, Y.; Kim, Y. K.; Kimura, N.; Klimkovich, T.; Kolb, M.; Kordas, K.; Krizka, K.; Kubota, T.; Lanza, A.; Li, H. L.; Liberali, V.; Lisovyi, M.; Liu, L.; Love, J.; Luciano, P.; Luongo, C.; Magalotti, D.; Maznas, I.; Meroni, C.; Mitani, T.; Nasimi, H.; Negri, A.; Neroutsos, P.; Neubauer, M.; Nikolaidis, S.; Okumura, Y.; Pandini, C.; Petridou, C.; Piendibene, M.; Proudfoot, J.; Rados, P.; Roda, C.; Rossi, E.; Sakurai, Y.; Sampsonidis, D.; Saxon, J.; Schmitt, S.; Schoening, A.; Shochet, M.; Shojaii, S.; Soltveit, H.; Sotiropoulou, C. L.; Stabile, A.; Swiatlowski, M.; Tang, F.; Taylor, P. T.; Testa, M.; Tompkins, L.; Vercesi, V.; Volpi, G.; Wang, R.; Watari, R.; Webster, J.; Wu, X.; Yorita, K.; Yurkewicz, A.; Zeng, J. C.; Zhang, J.; Zou, R.

    2016-02-01

    The use of tracking information at the trigger level in the LHC Run II period is crucial for the trigger and data acquisition system and will be even more so as contemporary collisions that occur at every bunch crossing will increase in Run III. The Fast TracKer is part of the ATLAS trigger upgrade project; it is a hardware processor that will provide every Level-1 accepted event (100 kHz) and within 100μs, full tracking information for tracks with momentum as low as 1 GeV . Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance.

  19. Hardware description languages

    NASA Technical Reports Server (NTRS)

    Tucker, Jerry H.

    1994-01-01

    Hardware description languages are special purpose programming languages. They are primarily used to specify the behavior of digital systems and are rapidly replacing traditional digital system design techniques. This is because they allow the designer to concentrate on how the system should operate rather than on implementation details. Hardware description languages allow a digital system to be described with a wide range of abstraction, and they support top down design techniques. A key feature of any hardware description language environment is its ability to simulate the modeled system. The two most important hardware description languages are Verilog and VHDL. Verilog has been the dominant language for the design of application specific integrated circuits (ASIC's). However, VHDL is rapidly gaining in popularity.

  20. Design of an integrated hardware interface for AOSLO image capture and cone-targeted stimulus delivery

    PubMed Central

    Yang, Qiang; Arathorn, David W.; Tiruveedhula, Pavan; Vogel, Curtis R.; Roorda, Austin

    2010-01-01

    We demonstrate an integrated FPGA solution to project highly stabilized, aberration-corrected stimuli directly onto the retina by means of real-time retinal image motion signals in combination with high speed modulation of a scanning laser. By reducing the latency between target location prediction and stimulus delivery, the stimulus location accuracy, in a subject with good fixation, is improved to 0.15 arcminutes from 0.26 arcminutes in our earlier solution. We also demonstrate the new FPGA solution is capable of delivering stabilized large stimulus pattern (up to 256x256 pixels) to the retina. PMID:20721171

  1. An introduction to the BANNING design automation system for shuttle microelectronic hardware development

    NASA Technical Reports Server (NTRS)

    Mcgrady, W. J.

    1979-01-01

    The BANNING MOS design system is presented. It complements rather than supplant the normal design activities associated with the design and fabrication of low-power digital electronic equipment. BANNING is user-oriented and requires no programming experience to use effectively. It provides the user a simulation capability to aid in his circuit design and it eliminates most of the manual operations involved in the layout and artwork generation of integrated circuits. An example of its operation is given and some additional background reading is provided.

  2. A Student Experiment Method for Learning the Basics of Embedded Software Technologies Including Hardware/Software Co-design

    NASA Astrophysics Data System (ADS)

    Kambe, Hidetoshi; Mitsui, Hiroyasu; Endo, Satoshi; Koizumi, Hisao

    The applications of embedded system technologies have spread widely in various products, such as home appliances, cellular phones, automobiles, industrial machines and so on. Due to intensified competition, embedded software has expanded its role in realizing sophisticated functions, and new development methods like a hardware/software (HW/SW) co-design for uniting HW and SW development have been researched. The shortfall of embedded SW engineers was estimated to be approximately 99,000 in the year 2006, in Japan. Embedded SW engineers should understand HW technologies and system architecture design as well as SW technologies. However, a few universities offer this kind of education systematically. We propose a student experiment method for learning the basics of embedded system development, which includes a set of experiments for developing embedded SW, developing embedded HW and experiencing HW/SW co-design. The co-design experiment helps students learn about the basics of embedded system architecture design and the flow of designing actual HW and SW modules. We developed these experiments and evaluated them.

  3. Software algorithm and hardware design for real-time implementation of new spectral estimator

    PubMed Central

    2014-01-01

    Background Real-time spectral analyzers can be difficult to implement for PC computer-based systems because of the potential for high computational cost, and algorithm complexity. In this work a new spectral estimator (NSE) is developed for real-time analysis, and compared with the discrete Fourier transform (DFT). Method Clinical data in the form of 216 fractionated atrial electrogram sequences were used as inputs. The sample rate for acquisition was 977 Hz, or approximately 1 millisecond between digital samples. Real-time NSE power spectra were generated for 16,384 consecutive data points. The same data sequences were used for spectral calculation using a radix-2 implementation of the DFT. The NSE algorithm was also developed for implementation as a real-time spectral analyzer electronic circuit board. Results The average interval for a single real-time spectral calculation in software was 3.29 μs for NSE versus 504.5 μs for DFT. Thus for real-time spectral analysis, the NSE algorithm is approximately 150× faster than the DFT. Over a 1 millisecond sampling period, the NSE algorithm had the capability to spectrally analyze a maximum of 303 data channels, while the DFT algorithm could only analyze a single channel. Moreover, for the 8 second sequences, the NSE spectral resolution in the 3-12 Hz range was 0.037 Hz while the DFT spectral resolution was only 0.122 Hz. The NSE was also found to be implementable as a standalone spectral analyzer board using approximately 26 integrated circuits at a cost of approximately $500. The software files used for analysis are included as a supplement, please see the Additional files 1 and 2. Conclusions The NSE real-time algorithm has low computational cost and complexity, and is implementable in both software and hardware for 1 millisecond updates of multichannel spectra. The algorithm may be helpful to guide radiofrequency catheter ablation in real time. PMID:24886214

  4. FPGA-Based Efficient Hardware/Software Co-Design for Industrial Systems with Consideration of Output Selection

    NASA Astrophysics Data System (ADS)

    Deliparaschos, Kyriakos M.; Michail, Konstantinos; Zolotas, Argyrios C.; Tzafestas, Spyros G.

    2016-05-01

    This work presents a field programmable gate array (FPGA)-based embedded software platform coupled with a software-based plant, forming a hardware-in-the-loop (HIL) that is used to validate a systematic sensor selection framework. The systematic sensor selection framework combines multi-objective optimization, linear-quadratic-Gaussian (LQG)-type control, and the nonlinear model of a maglev suspension. A robustness analysis of the closed-loop is followed (prior to implementation) supporting the appropriateness of the solution under parametric variation. The analysis also shows that quantization is robust under different controller gains. While the LQG controller is implemented on an FPGA, the physical process is realized in a high-level system modeling environment. FPGA technology enables rapid evaluation of the algorithms and test designs under realistic scenarios avoiding heavy time penalty associated with hardware description language (HDL) simulators. The HIL technique facilitates significant speed-up in the required execution time when compared to its software-based counterpart model.

  5. Design requirements for SRB production control system. Volume 3: Package evaluation, modification and hardware

    NASA Technical Reports Server (NTRS)

    1981-01-01

    The software package evaluation was designed to analyze commercially available, field-proven, production control or manufacturing resource planning management technology and software package. The analysis was conducted by comparing SRB production control software requirements and conceptual system design to software package capabilities. The methodology of evaluation and the findings at each stage of evaluation are described. Topics covered include: vendor listing; request for information (RFI) document; RFI response rate and quality; RFI evaluation process; and capabilities versus requirements.

  6. Acoustic Treatment Design Scaling Methods. Volume 3; Test Plans, Hardware, Results, and Evaluation

    NASA Technical Reports Server (NTRS)

    Yu, J.; Kwan, H. W.; Echternach, D. K.; Kraft, R. E.; Syed, A. A.

    1999-01-01

    The ability to design, build, and test miniaturized acoustic treatment panels on scale-model fan rigs representative of the full-scale engine provides not only a cost-savings, but an opportunity to optimize the treatment by allowing tests of different designs. To be able to use scale model treatment as a full-scale design tool, it is necessary that the designer be able to reliably translate the scale model design and performance to an equivalent full-scale design. The primary objective of the study presented in this volume of the final report was to conduct laboratory tests to evaluate liner acoustic properties and validate advanced treatment impedance models. These laboratory tests include DC flow resistance measurements, normal incidence impedance measurements, DC flow and impedance measurements in the presence of grazing flow, and in-duct liner attenuation as well as modal measurements. Test panels were fabricated at three different scale factors (i.e., full-scale, half-scale, and one-fifth scale) to support laboratory acoustic testing. The panel configurations include single-degree-of-freedom (SDOF) perforated sandwich panels, SDOF linear (wire mesh) liners, and double-degree-of-freedom (DDOF) linear acoustic panels.

  7. Hardware and software design for a National Instrument-based magnetic induction tomography system for prospective biomedical applications.

    PubMed

    Wei, Hsin-Yu; Soleimani, Manuchehr

    2012-05-01

    Magnetic induction tomography (MIT) is a new and emerging type of tomography technique that is able to map the passive electromagnetic properties (in particular conductivity) of an object. Excitation coils are used to induce eddy currents in the medium, and the magnetic field produced by the induced eddy current is then sensed by the receiver coils. Because of its non-invasive and contactless feature, it becomes an attractive technique for many applications (especially in biomedical area) compared to traditional contact electrode-based electrical impedance tomography. Due to the low contrast in conductivity between biological tissues, an accurate and stable hardware system is necessary. Most MIT systems in the literature employ external signal generators, power amplifiers and highly stable down-conversion electronics to obtain a satisfactory phase measurement. However, this would increase design complexity substantially. In this paper, a National Instrument-based MIT system is developed at the University of Bath, aiming for biomedical applications. The system utilizes National Instrument products to accomplish all signal driving, switching and data acquisition tasks, which ease the system design whilst providing satisfactory performance. This paper presents a full-scaled medical MIT system, from the sensor and system hardware design, eddy current model verification to the image reconstruction software: the performance of this MIT instrumentation system is characterized in detail, including the system accuracy and system stability. The methods of solving eddy current problem are presented. The reconstructed images of detecting the presence of saline solutions are also included in this paper, which show the capability of national instrument products to be developed into a full-scaled biomedical MIT system, by demonstrating the practical experimental results. PMID:22531316

  8. ACTIVE FILTER HARDWARE DESIGN & PERFORMANCE FOR THE DIII-D PLASMA CONTROL SYSTEM

    SciTech Connect

    SELLERS,D; FERRON,J.R; WALKER,M.L; BROESCH,J.D

    2003-10-01

    OAK-B135 The digital plasma control system (PCS), currently in operation on the DIII-D tokamak, requires inputs from a large number of sensors. Due to the nature of the digitizers and the relative noisy environment from which these signals are derived, each of the 32 signals must be conditioned via an active filter. Two different types of filters, Chebyshev and Bessel with fixed frequencies: 100 Hz Bessel was used for filtering the motional Stark effect diagnostic data. 800 Hz Bessel was designed to filter plasma control data and 1200 Hz Chebyshev is used with closed loop control of choppers. The performance of the plasma control system is greatly influenced by how well the actual filter responses match the software model used in the control system algorithms. This paper addresses the various issues facing the designer in matching the electrical design with the theoretical.

  9. Blackcomb: Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems

    SciTech Connect

    Schreiber, Robert

    2014-11-26

    Summary of technical results of Blackcomb Memory Devices We explored various different memory technologies (STTRAM, PCRAM, FeRAM, and ReRAM). The progress can be classified into three categories, below. Modeling and Tool Releases Various modeling tools have been developed over the last decade to help in the design of SRAM or DRAM-based memory hierarchies. To explore new design opportunities that NVM technologies can bring to the designers, we have developed similar high-level models for NVM, including PCRAMsim [Dong 2009], NVSim [Dong 2012], and NVMain [Poremba 2012]. NVSim is a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies. On the other side, NVMain is a cycle accurate main memory simulator designed to simulate emerging nonvolatile memories at the architectural level. We have released these models as open source tools and provided contiguous support to them. We also proposed PS3-RAM, which is a fast, portable and scalable statistical STT-RAM reliability analysis model [Wen 2012]. Design Space Exploration and Optimization With the support of these models, we explore different device/circuit optimization techniques. For example, in [Niu 2012a] we studied the power reduction technique for the application of ECC scheme in ReRAM designs and proposed to use ECC code to relax the BER (Bit Error Rate) requirement of a single memory to improve the write energy consumption and latency for both 1T1R and cross-point ReRAM designs. In [Xu 2011], we proposed a methodology to design STT-RAM for different optimization goals such as read performance, write performance and write energy by leveraging the trade-off between write current and write time of MTJ. We also studied the tradeoffs in building a reliable crosspoint Re

  10. The J-2X Upper Stage Engine: From Design to Hardware

    NASA Technical Reports Server (NTRS)

    Byrd, Thomas

    2010-01-01

    NASA is well on its way toward developing a new generation of launch vehicles to support of national space policy to retire the Space Shuttle fleet, complete the International Space Station, and return to the Moon as the first step in resuming this nation s exploration of deep space. The Constellation Program is developing the launch vehicles, spacecraft, surface systems, and ground systems to support those plans. Two launch vehicles will support those ambitious plans the Ares I and Ares V. (Figure 1) The J-2X Upper Stage Engine is a critical element of both of these new launchers. This paper will provide an overview of the J-2X design background, progress to date in design, testing, and manufacturing. The Ares I crew launch vehicle will lift the Orion crew exploration vehicle and up to four astronauts into low Earth orbit (LEO) to rendezvous with the space station or the first leg of mission to the Moon. The Ares V cargo launch vehicle is designed to lift a lunar lander into Earth orbit where it will be docked with the Orion spacecraft, and provide the thrust for the trans-lunar journey. While these vehicles bear some visual resemblance to the 1960s-era Saturn vehicles that carried astronauts to the Moon, the Ares vehicles are designed to carry more crew and more cargo to more places to carry out more ambitious tasks than the vehicles they succeed. The government/industry team designing the Ares rockets is mining a rich history of technology and expertise from the Shuttle, Saturn and other programs and seeking commonality where feasible between the Ares crew and cargo rockets as a way to minimize risk, shorten development times, and live within the budget constraints of its original guidance.

  11. Design of a hardware/software FPGA-based driver system for a large area high resolution CCD image sensor

    NASA Astrophysics Data System (ADS)

    Chen, Ying; Xu, Wanpeng; Zhao, Rongsheng; Chen, Xiangning

    2014-09-01

    A hardware/software field programmable gate array (FPGA)-based driver system was proposed and demonstrated for the KAF-39000 large area high resolution charge coupled device (CCD). The requirements of the KAF-39000 driver system were analyzed. The structure of "microprocessor with application specific integrated circuit (ASIC) chips" was implemented to design the driver system. The system test results showed that dual channels of imaging analog data were obtained with a frame rate of 0.87 frame/s. The frequencies of horizontal timing and vertical timing were 22.9 MHz and 28.7 kHz, respectively, which almost reached the theoretical value of 24 MHz and 30 kHz, respectively.

  12. Toward a Performance/Resilience Tool for Hardware/Software Co-Design of High-Performance Computing Systems

    SciTech Connect

    Engelmann, Christian; Naughton, III, Thomas J

    2013-01-01

    xSim is a simulation-based performance investigation toolkit that permits running high-performance computing (HPC) applications in a controlled environment with millions of concurrent execution threads, while observing application performance in a simulated extreme-scale system for hardware/software co-design. The presented work details newly developed features for xSim that permit the injection of MPI process failures, the propagation/detection/notification of such failures within the simulation, and their handling using application-level checkpoint/restart. These new capabilities enable the observation of application behavior and performance under failure within a simulated future-generation HPC system using the most common fault handling technique.

  13. Hardware and software design for an electromagnetic induction tomography (EMT) system for high contrast metal process applications

    NASA Astrophysics Data System (ADS)

    Ma, X.; Peyton, A. J.; Higson, S. R.; Lyons, A.; Dickinson, S. J.

    2006-01-01

    This paper presents the latest development of an EMT system designed for use in the metal production industry such as imaging molten steel flow profiles during continuous casting. The system that has been developed is based on a commercial data acquisition board residing in a PC host computer and programmed in the LabView graphical language. The paper reviews the new EMT hardware electronics and software. The noise effects and the detectability limits of the system are given in the paper followed by the system sensitivity map analysis. Optimal image reconstructions, including the simultaneous iterative reconstruction technique (SIRT) and non-iterative Tikhonov regularization, truncated singular value decomposition (TSVD), are also discussed and applied for the system. The system has been demonstrated in real time (10 frames s-1 for 5 kHz excitation) with test phantoms that represent typical metal flow profiles such as central, annular stream and multiple streams.

  14. Design and implementation of a new real-time frequency sensor used as hardware countermeasure.

    PubMed

    Jiménez-Naharro, Raúl; Gómez-Galán, Juan Antonio; Sánchez-Raya, Manuel; Gómez-Bravo, Fernando; Pedro-Carrasco, Manuel

    2013-01-01

    A new digital countermeasure against attacks related to the clock frequency is presented. This countermeasure, known as frequency sensor, consists of a local oscillator, a transition detector, a measurement element and an output block. The countermeasure has been designed using a full-custom technique implemented in an Application-Specific Integrated Circuit (ASIC), and the implementation has been verified and characterized with an integrated design using a 0.35 mm standard Complementary Metal Oxide Semiconductor (CMOS) technology (Very Large Scale Implementation-VLSI implementation). The proposed solution is configurable in resolution time and allowed range of period, achieving a minimum resolution time of only 1.91 ns and an initialization time of 5.84 ns. The proposed VLSI implementation shows better results than other solutions, such as digital ones based on semi-custom techniques and analog ones based on band pass filters, all design parameters considered. Finally, a counter has been used to verify the good performance of the countermeasure in avoiding the success of an attack. PMID:24008285

  15. The Effect of Predicted Vehicle Displacement on Ground Crew Task Performance and Hardware Design

    NASA Technical Reports Server (NTRS)

    Atencio, Laura Ashley; Reynolds, David W.

    2011-01-01

    NASA continues to explore new launch vehicle concepts that will carry astronauts to low- Earth orbit to replace the soon-to-be retired Space Transportation System (STS) shuttle. A tall vertically stacked launch vehicle (> or =300 ft) is exposed to the natural environment while positioned on the launch pad. Varying directional winds and vortex shedding cause the vehicle to sway in an oscillating motion. Ground crews working high on the tower and inside the vehicle during launch preparations will be subjected to this motion while conducting critical closeout tasks such as mating fluid and electrical connectors and carrying heavy objects. NASA has not experienced performing these tasks in such environments since the Saturn V, which was serviced from a movable (but rigid) service structure; commercial launchers are likewise attended by a service structure that moves away from the vehicle for launch. There is concern that vehicle displacement may hinder ground crew operations, impact the ground system designs, and ultimately affect launch availability. The vehicle sway assessment objective is to replicate predicted frequencies and displacements of these tall vehicles, examine typical ground crew tasks, and provide insight into potential vehicle design considerations and ground crew performance guidelines. This paper outlines the methodology, configurations, and motion testing performed while conducting the vehicle displacement assessment that will be used as a Technical Memorandum for future vertically stacked vehicle designs.

  16. Energy efficient engine high pressure turbine test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Halila, E. E.; Lenahan, D. T.; Thomas, T. T.

    1982-01-01

    The high pressure turbine configuration for the Energy Efficient Engine is built around a two-stage design system. Moderate aerodynamic loading for both stages is used to achieve the high level of turbine efficiency. Flowpath components are designed for 18,000 hours of life, while the static and rotating structures are designed for 36,000 hours of engine operation. Both stages of turbine blades and vanes are air-cooled incorporating advanced state of the art in cooling technology. Direct solidification (DS) alloys are used for blades and one stage of vanes, and an oxide dispersion system (ODS) alloy is used for the Stage 1 nozzle airfoils. Ceramic shrouds are used as the material composition for the Stage 1 shroud. An active clearance control (ACC) system is used to control the blade tip to shroud clearances for both stages. Fan air is used to impinge on the shroud casing support rings, thereby controlling the growth rate of the shroud. This procedure allows close clearance control while minimizing blade tip to shroud rubs.

  17. Preliminary control law and hardware designs for a ride quality augmentation system for commuter aircraft. Phase 2

    NASA Technical Reports Server (NTRS)

    Davis, D. J.; Linse, D. J.; Suikat, R.; Entz, D. P.

    1986-01-01

    The continued investigation of the design of Ride Quality Augmentation Systems (RQAS) for commuter aircraft is described. The purpose of these RQAS is the reduction of the vertical and lateral acceleration response of the aircraft due to atmospheric turbulence by the application of active control. The current investigations include the refinement of the sample data feedback control laws based on the control-rate-weighting and output-weighting optimal control design techniqes. These control designs were evaluated using aircraft time simulations driven by Dryden spectra turbulence. Fixed gain controllers were tested throughout the aircrft operating envelope. The preliminary design of the hardware modifications necessary to implement and test the RQAS on a commuter aircraft is included. These include a separate surface elevator and the flap modifications to provide both direct lift and roll control. A preliminary failure mode investigation was made for the proposed configuration. The results indicate that vertical acceleration reductions of 45% and lateral reductions of more than 50% are possible. A fixed gain controller appears to be feasible with only minor response degradation.

  18. Design and Implementation of a Hardware Channel Board for Holographic Data Storage

    NASA Astrophysics Data System (ADS)

    Yoon, Pilsang; Kim, Haksun; Park, Jooyoun; Jung, Heungsang; Park, Gwitae

    2009-03-01

    A channel board has been designed, manufactured, and used for real-time recording and reading processes. The channel coding and decoding algorithms were implemented on Xilinx field-programmable gate array (FPGA) devices. For fast data transmission between the channel board and personal computer (PC), a universal serial bus (USB) 2.0 interface is installed in the channel board. The firmware and device driver for USB interface achieved a transfer rate of 34 Mbyte/s. A holographic data storage system records a video stream, which was successfully retrieved and reconstructed without error.

  19. Hardware-Based Non-Optimum Factors for Launch Vehicle Structural Design

    NASA Technical Reports Server (NTRS)

    Wu, K. Chauncey; Cerro, Jeffrey A.

    2010-01-01

    During aerospace vehicle conceptual and preliminary design, empirical non-optimum factors are typically applied to predicted structural component weights to account for undefined manufacturing and design details. Non-optimum factors are developed here for 32 aluminum-lithium 2195 orthogrid panels comprising the liquid hydrogen tank barrel of the Space Shuttle External Tank using measured panel weights and manufacturing drawings. Minimum values for skin thickness, axial and circumferential blade stiffener thickness and spacing, and overall panel thickness are used to estimate individual panel weights. Panel non-optimum factors computed using a coarse weights model range from 1.21 to 1.77, and a refined weights model (including weld lands and skin and stiffener transition details) yields non-optimum factors of between 1.02 and 1.54. Acreage panels have an average 1.24 non-optimum factor using the coarse model, and 1.03 with the refined version. The observed consistency of these acreage non-optimum factors suggests that relatively simple models can be used to accurately predict large structural component weights for future launch vehicles.

  20. The design and fabrication of the Centaur neutral buoyancy trainer and related hardware

    NASA Technical Reports Server (NTRS)

    Ware, Alan S.; Hollingsworth, Michael

    1986-01-01

    Two full scale mockups of the Centaur upper stage were designed, fabricated and delivered to NASA. One was the Centaur Weightless Environment Training Facility (WETF) trainer and the other was the Centaur 1-G mockup. The Centaur upper stage booster is designed to carry the spacecraft Galileo to Jupiter, and the spacecraft Ulysses to an orbit around the Sun after launch from the Space Shuttle. The flight vehicle has several Extravehicular Activity (EVA) contingency tasks that require crew training. This need for crew training generated the requirement for the Centaur WETF crew trainer, which is high fidelity in areas of expected crew interface. During the production of the Centaur WETF crew trainer, the need for a jumper cable from Centaur to the Orbiter was identified. This EVA contingency task would be the installation of a cable from the Orbiter cargo bay sill to various command data boxes on Centaur to allow crew control deployment should a failure occur. This task required the upgrading of volumetric boxes on the trainer to a high fidelity configuration including electrical connector installation and cable routing.

  1. Designing an Ergonomically Correct CNC Workstation on a Shoe String Budget.

    ERIC Educational Resources Information Center

    Lightner, Stan

    2001-01-01

    Describes research to design and construct ergonomically correct work stations for Computer Numerical Control machine tools. By designing ergonomically correct work stations, industrial technology teachers help protect students from repetitive motion injuries. (Contains 12 references.) (JOW)

  2. Hardly Hardware

    ERIC Educational Resources Information Center

    Lott, Debra

    2007-01-01

    In a never-ending search for new and inspirational still-life objects, the author discovered that home improvement retailers make great resources for art teachers. Hardware and building materials are inexpensive and have interesting and variable shapes. She especially liked the dryer-vent coils and the electrical conduit. These items can be…

  3. Final Report: Enabling Exascale Hardware and Software Design through Scalable System Virtualization

    SciTech Connect

    Bridges, Patrick G.

    2015-02-01

    In this grant, we enhanced the Palacios virtual machine monitor to increase its scalability and suitability for addressing exascale system software design issues. This included a wide range of research on core Palacios features, large-scale system emulation, fault injection, perfomrance monitoring, and VMM extensibility. This research resulted in large number of high-impact publications in well-known venues, the support of a number of students, and the graduation of two Ph.D. students and one M.S. student. In addition, our enhanced version of the Palacios virtual machine monitor has been adopted as a core element of the Hobbes operating system under active DOE-funded research and development.

  4. [The hardware design of a portable gastrointestinal wireless endoscope image receiver].

    PubMed

    Zhang, Si-jie; Zeng, Xiao-ping; Zheng, Xiao-lin; Xie, Li-ying; Peng, Cheng-lin

    2006-05-01

    The portable gastrointestinal wireless endoscope image receiver is developed and based on TMS320C6211 DSP. It can receive and demodulate the modulated signal which is transmitted from the camera-capsule, and then output the video signal. The synchronizing signals offered by SAA7114H are made best of and are used to design the time logic circuit. The fitful video signal can be collected under the control of the time logic circuit. The circuit can automatically get rid of useless blank data and only collect effective and good-quality video signals, and storage them in CF card. In addition, the image signal can be processed and compressed by DSP, and thus the data storage space and the data- analyzing time can be saved. PMID:16929775

  5. Design of software and hardware components for a six-degrees of freedom optical position sensor

    SciTech Connect

    Garcia, F.N.

    1997-06-01

    This report summarizes the evaluation of a fully compatible and operational data acquisition system for a six-degrees of freedom optical sensor (SixDOF). The SixDOF, developed at Lawrence Livermore National Laboratory by Charles Vann, is capable of tracking an object`s position in all its six degrees of freedom without any datum specification by means of two reflective surfaces mounted on the object. To make the SixDOF operational and thus validate its underlying physics, a signal processing system has been designed so that information from the sensor is transferred accurately and efficiently to a computer. In addition, a six-degrees of freedom positioning stage has been built in efforts to calibrate the sensor in real time. A crucial design constraint is the necessity to build the complete data acquisition system so that it be small and most importantly portable. The prototype of the SixDOF system proved to be capable of crudely detecting changes in the position of an object in all six spatial degrees of freedom. An accuracy of around 0.5 mm is estimated presently even though the position of the two reflectors on the object is seen to significantly influence the accuracy of the sensor. The resolution of the sensor is not quite understood yet because of uncertainties in the actual spot size of the laser, however, field of the view has been seen to increase as the resolution decreases. The decoupling (calibration) of the sensor data proved to be rather successful although some coupling still exists. This coupling, however, is almost certain to come from the crudeness in the alignment of the optics within the sensor.

  6. Correction.

    PubMed

    2015-11-01

    In the article by Heuslein et al, which published online ahead of print on September 3, 2015 (DOI: 10.1161/ATVBAHA.115.305775), a correction was needed. Brett R. Blackman was added as the penultimate author of the article. The article has been corrected for publication in the November 2015 issue. PMID:26490278

  7. Design and implementation of coating hardware for the Hobby-Eberly Telescope wide-field corrector

    NASA Astrophysics Data System (ADS)

    Good, John; Lee, Hanshin; Hill, Gary J.; Vattiat, Brian; Perry, David; Kriel, Herman; Savage, Richard

    2014-07-01

    A major upgrade of the HET is in progress that will substantially increase the pupil size to 10 meters and the field of view to 22 arc-minutes by replacing the spherical aberration corrector. The new Wide Field Corrector is a 4-element assembly weighing 750kg and measuring 1.34 meters diameter by 2.1 meter in length. Special fixtures were required in order to support the mirrors of the Wide-Field Corrector and adapt them to the coaters chamber, during the vacuum coating process. For the 1 meter-class mirrors, the only suitable support interface was located on a 80mm wide cylindrical surface on the periphery of each mirror. The vacuum compatible system had to support the mirrors with the surface facing downward, and accommodate thermal ranges from ambient to 100C without inducing stresses in the substrate. The fixture also had to accommodate washing, as well as support of witness samples during testing and production runs, and provide masking for alignment fixtures in the center apertures of each mirror. Design principles, materials, implementation details, as well as lessons learned are covered*.

  8. Reducing NPR 7120.5D to Practice: Transitioning from Design Reviews to the SIR Hardware Review

    NASA Technical Reports Server (NTRS)

    Taylor, Randall

    2011-01-01

    The Gravity Recovery And Interior Laboratory (GRAIL) mission was the first Jet Propulsion Laboratory (JPL) project initiated under NASA's revised rules for space flight project management, NPR 7120.5D, "NASA Space Flight Program and Project Management Requirements." NASA selected GRAIL through a competitive Announcement of Opportunity process and funded its Phase B Preliminary Design effort. The team's first major milestone was a JPL institutional milestone, the Project Mission System Review (PMSR), which proved an excellent tune-up for the end-of-Phase-B NASA life-cycle review, the Preliminary Design Review (PDR). Building on JPL experience on the Prometheus and Juno projects, the team successfully organized for and conducted these reviews on an aggressive schedule. For the Project Critical Design Review (CDR), lessons learned from the PDR and updated Standing Review Board (SRB) practices from the Agency were factored into the review preparation effort. Additionally, the review was held at the Principal Investigator's institution, the Massachusetts Institute of Technology, rather than at the project management center (JPL), which necessitated additional cross-country coordination steps. The PMSR, PDR, and CDR were design reviews and largely paper-oriented. For the System Integration Review (SIR), the project needed to transition to a hardware review and deal with paper in a very different manner. While many of the practices employed for the design reviews were modified and retained (e.g., review preparation team, gate products management, pre-reviews, SRB coordination), the review agenda, presentation style, and slide templates were significantly changed. A key success factor concerned the handling of project open paper, which was succinctly and effectively communicated to the SRB in presentations.This paper provides a brief overview of the GRAIL mission and its project management challenges, provides a detailed description of project SIR preparation and execution

  9. Design of Improved Error Correction Decoder Using Error Detecting Information of Modulation Code in Digital Versatile Disc Systems

    NASA Astrophysics Data System (ADS)

    Lee, Joohyun; Lee, Jaejin

    2006-02-01

    We present a powerful error control decoder which can be used in all kinds of digital versatile disk (DVD) systems. The decoder exploits the error information from the modulation decoder in order to increase the error correcting capability. We can identify that the modulation decoder in DVD system can detect errors more than 60% of total errors when burst errors are occurred. In results, for a decoded block, error correcting capability of the proposed scheme is improved up to 25% more than that of the original error control decoder. Also, a pipeline-balanced Reed-Solomon Product Code (RSPC) decoder with a low hardware complexity is designed to maximize the throughput. The maximum throughput of the RSPC decoder is 740 Mbps at 100 MHz and the number of gate counts is 20.3 K for RS(182,172,11) decoder and 30.7 K for RS(208,192,17) decoder, respectively.

  10. Correction.

    PubMed

    2015-12-01

    In the article by Narayan et al (Narayan O, Davies JE, Hughes AD, Dart AM, Parker KH, Reid C, Cameron JD. Central aortic reservoir-wave analysis improves prediction of cardiovascular events in elderly hypertensives. Hypertension. 2015;65:629–635. doi: 10.1161/HYPERTENSIONAHA.114.04824), which published online ahead of print December 22, 2014, and appeared in the March 2015 issue of the journal, some corrections were needed.On page 632, Figure, panel A, the label PRI has been corrected to read RPI. In panel B, the text by the upward arrow, "10% increase in kd,” has been corrected to read, "10% decrease in kd." The corrected figure is shown below.The authors apologize for these errors. PMID:26558821

  11. Standard gas hardware

    NASA Technical Reports Server (NTRS)

    Spencer, Stan

    1995-01-01

    The Sierra College Space Technology Program is currently building their third GAS payload in addition to a small satellite. The project is supported by an ARPA/TRP grant. One aspect of the grant is the design of standard hardware for Get Away Specials (GAS) payloads. A standard structure has been designed and work is progressing on a standard battery box and computer.

  12. Correction

    NASA Astrophysics Data System (ADS)

    1995-04-01

    Seismic images of the Brooks Range, Arctic Alaska, reveal crustal-scale duplexing: Correction Geology, v. 23, p. 65 68 (January 1995) The correct Figure 4A, for the loose insert, is given here. See Figure 4A below. Corrected inserts will be available to those requesting copies of the article from the senior author, Gary S. Fuis, U.S. Geological Survey, 345 Middlefield Road, Menlo Park, CA 94025. Figure 4A. P-wave velocity model of Brooks Range region (thin gray contours) with migrated wide-angle reflections (heavy red lines) and migreated vertical-incidence reflections (short black lines) superimposed. Velocity contour interval is 0.25 km/s; 4,5, and 6 km/s contours are labeled. Estimated error in velocities is one contour interval. Symbols on faults shown at top are as in Figure 2 caption.

  13. Correction.

    PubMed

    2016-02-01

    Neogi T, Jansen TLTA, Dalbeth N, et al. 2015 Gout classification criteria: an American College of Rheumatology/European League Against Rheumatism collaborative initiative. Ann Rheum Dis 2015;74:1789–98. The name of the 20th author was misspelled. The correct spelling is Janitzia Vazquez-Mellado. We regret the error. PMID:26881284

  14. On two new trends in evolvable hardware: employment of HDL-based structuring, and design of multi-functional circuits

    NASA Technical Reports Server (NTRS)

    Stoica, A.; Keymeulen, D.; Zebulum, R. S.; Ferguson, M. I.; Guo, X.

    2002-01-01

    This paper comments on some directions of growth for evolvable hardware, proposes research directions that address the scalability problem and gives examples of results in novel areas approached by EHW.

  15. Correction.

    PubMed

    2016-02-01

    In the article by Guessous et al (Guessous I, Pruijm M, Ponte B, Ackermann D, Ehret G, Ansermot N, Vuistiner P, Staessen J, Gu Y, Paccaud F, Mohaupt M, Vogt B, Pechère-Bertschi A, Martin PY, Burnier M, Eap CB, Bochud M. Associations of ambulatory blood pressure with urinary caffeine and caffeine metabolite excretions. Hypertension. 2015;65:691–696. doi: 10.1161/HYPERTENSIONAHA.114.04512), which published online ahead of print December 8, 2014, and appeared in the March 2015 issue of the journal, a correction was needed.One of the author surnames was misspelled. Antoinette Pechère-Berstchi has been corrected to read Antoinette Pechère-Bertschi.The authors apologize for this error. PMID:26763012

  16. Hardware-software-co-design of parallel and distributed systems using a behavioural programming and multi-process model with high-level synthesis

    NASA Astrophysics Data System (ADS)

    Bosse, Stefan

    2011-05-01

    A new design methodology for parallel and distributed embedded systems is presented using the behavioural hardware compiler ConPro providing an imperative programming model based on concurrently communicating sequential processes (CSP) with an extensive set of interprocess-communication primitives and guarded atomic actions. The programming language and the compiler-based synthesis process enables the design of constrained power- and resourceaware embedded systems with pure Register-Transfer-Logic (RTL) efficiently mapped to FPGA and ASIC technologies. Concurrency is modelled explicitly on control- and datapath level. Additionally, concurrency on data-path level can be automatically explored and optimized by different schedulers. The CSP programming model can be synthesized to hardware (SoC) and software (C,ML) models and targets. A common source for both hardware and software implementation with identical functional behaviour is used. Processes and objects of the entire design can be distributed on different hardware and software platforms, for example, several FPGA components and software executed on several microprocessors, providing a parallel and distributed system. Intersystem-, interprocess-, and object communication is automatically implemented with serial links, not visible on programming level. The presented design methodology has the benefit of high modularity, freedom of choice of target technologies, and system architecture. Algorithms can be well matched to and distributed on different suitable execution platforms and implementation technologies, using a unique programming model, providing a balance of concurrency and resource complexity. An extended case study of a communication protocol used in high-density sensor-actuator networks should demonstrate and compare the design of a hardware and software target. The communication protocol is suited for high-density intra-and interchip networks.

  17. A framework for the design and specification of hard real-time, hardware-in-the-loop simulations of large, avionic systems

    NASA Astrophysics Data System (ADS)

    Ricks, Kenneth Gerald

    High-level design tools for the design and specification of avionic systems and real-time systems currently exist. However, real-time, hardware-in-the-loop simulations of avionic systems are based upon principles fundamentally different than those used to design avionic systems and represent a specialized case of real-time systems. As a result, the high-level software tools used to design avionic systems and real-time systems cannot be applied to the design of real-time, hardware-in-the-loop simulations of avionic systems. For this reason, such simulations of avionic systems should not be considered part of the domain containing avionic systems or general-purpose real-time systems and should be considered as an application domain unto itself for which design tools are unavailable. To fill this void, this dissertation proposes a framework for the design and specification of real-time, hardware-in-the-loop simulations of avionic systems. This framework is based upon a new specification language called the Simulation Architecture Description Language. This specification language is a graphical language with constructs and semantics defined to provide the user with the capability to completely define the simulation and its software execution characteristics at various levels of abstraction. The language includes a new method for combining precedence constraints for a single software process. These semantics provide a more accurate description of the behavior of software systems having a dynamic job structure than existing semantics. An environment that supports the execution of simulation software having the semantics defined within this language is also described. A toolset that interfaces to the language and provides additional functionality such as design analysis, schedulability analysis, and simulation file generation is also discussed. This framework provides a complete design and specification environment for real-time, hardware-in-the-loop simulations of

  18. Correction.

    PubMed

    2015-05-22

    The Circulation Research article by Keith and Bolli (“String Theory” of c-kitpos Cardiac Cells: A New Paradigm Regarding the Nature of These Cells That May Reconcile Apparently Discrepant Results. Circ Res. 2015:116:1216-1230. doi: 10.1161/CIRCRESAHA.116.305557) states that van Berlo et al (2014) observed that large numbers of fibroblasts and adventitial cells, some smooth muscle and endothelial cells, and rare cardiomyocytes originated from c-kit positive progenitors. However, van Berlo et al reported that only occasional fibroblasts and adventitial cells derived from c-kit positive progenitors in their studies. Accordingly, the review has been corrected to indicate that van Berlo et al (2014) observed that large numbers of endothelial cells, with some smooth muscle cells and fibroblasts, and more rarely cardiomyocytes, originated from c-kit positive progenitors in their murine model. The authors apologize for this error, and the error has been noted and corrected in the online version of the article, which is available at http://circres.ahajournals.org/content/116/7/1216.full ( PMID:25999426

  19. Correction

    NASA Astrophysics Data System (ADS)

    1998-12-01

    Alleged mosasaur bite marks on Late Cretaceous ammonites are limpet (patellogastropod) home scars Geology, v. 26, p. 947 950 (October 1998) This article had the following printing errors: p. 947, Abstract, line 11, “sepia” should be “septa” p. 947, 1st paragraph under Introduction, line 2, “creep” should be “deep” p. 948, column 1, 2nd paragraph, line 7, “creep” should be “deep” p. 949, column 1, 1st paragraph, line 1, “creep” should be “deep” p. 949, column 1, 1st paragraph, line 5, “19774” should be “1977)” p. 949, column 1, 4th paragraph, line 7, “in particular” should be “In particular” CORRECTION Mammalian community response to the latest Paleocene thermal maximum: An isotaphonomic study in the northern Bighorn Basin, Wyoming Geology, v. 26, p. 1011 1014 (November 1998) An error appeared in the References Cited. The correct reference appears below: Fricke, H. C., Clyde, W. C., O'Neil, J. R., and Gingerich, P. D., 1998, Evidence for rapid climate change in North America during the latest Paleocene thermal maximum: Oxygen isotope compositions of biogenic phosphate from the Bighorn Basin (Wyoming): Earth and Planetary Science Letters, v. 160, p. 193 208.

  20. NASA HUNCH Hardware

    NASA Technical Reports Server (NTRS)

    Hall, Nancy R.; Wagner, James; Phelps, Amanda

    2014-01-01

    What is NASA HUNCH? High School Students United with NASA to Create Hardware-HUNCH is an instructional partnership between NASA and educational institutions. This partnership benefits both NASA and students. NASA receives cost-effective hardware and soft goods, while students receive real-world hands-on experiences. The 2014-2015 was the 12th year of the HUNCH Program. NASA Glenn Research Center joined the program that already included the NASA Johnson Space Flight Center, Marshall Space Flight Center, Langley Research Center and Goddard Space Flight Center. The program included 76 schools in 24 states and NASA Glenn worked with the following five schools in the HUNCH Build to Print Hardware Program: Medina Career Center, Medina, OH; Cattaraugus Allegheny-BOCES, Olean, NY; Orleans Niagara-BOCES, Medina, NY; Apollo Career Center, Lima, OH; Romeo Engineering and Tech Center, Washington, MI. The schools built various parts of an International Space Station (ISS) middeck stowage locker and learned about manufacturing process and how best to build these components to NASA specifications. For the 2015-2016 school year the schools will be part of a larger group of schools building flight hardware consisting of 20 ISS middeck stowage lockers for the ISS Program. The HUNCH Program consists of: Build to Print Hardware; Build to Print Soft Goods; Design and Prototyping; Culinary Challenge; Implementation: Web Page and Video Production.

  1. Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description

    NASA Astrophysics Data System (ADS)

    Algredo-Badillo, Ignacio; Feregrino-Uribe, Claudia; Cumplido, René; Morales-Sandoval, Miguel

    MD5 is a cryptographic algorithm used for authentication. When implemented in hardware, the performance is affected by the data dependency of the iterative compression function. In this paper, a new functional description is proposed with the aim of achieving higher throughput by mean of reducing the critical path and latency. This description can be used in similar structures of other hash algorithms, such as SHA-1, SHA-2 and RIPEMD-160, which have comparable data dependence. The proposed MD5 hardware architecture achieves a high throughput/area ratio, results of implementation in an FPGA are presented and discussed, as well as comparisons against related works.

  2. A novel visual hardware behavioral language

    NASA Technical Reports Server (NTRS)

    Li, Xueqin; Cheng, H. D.

    1992-01-01

    Most hardware behavioral languages just use texts to describe the behavior of the desired hardware design. This is inconvenient for VLSI designers who enjoy using the schematic approach. The proposed visual hardware behavioral language has the ability to graphically express design information using visual parallel models (blocks), visual sequential models (processes) and visual data flow graphs (which consist of primitive operational icons, control icons, and Data and Synchro links). Thus, the proposed visual hardware behavioral language can not only specify hardware concurrent and sequential functionality, but can also visually expose parallelism, sequentiality, and disjointness (mutually exclusive operations) for the hardware designers. That would make the hardware designers capture the design ideas easily and explicitly using this visual hardware behavioral language.

  3. New Designs for Correctional Education and Training Programs.

    ERIC Educational Resources Information Center

    McCollum, Sylvia G.

    1973-01-01

    The challenge confronting creative educators concerned with using the correctional experience in positive ways is to structure an educational delivery system which takes into account the wide range of individual differences among people whose only common denominator is "serving time." Inherent is the problem of staff and public resistance to…

  4. 78 FR 32988 - Core Principles and Other Requirements for Designated Contract Markets; Correction

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-06-03

    ... and Other Requirements for Designated Contract Markets (77 FR 36612, June 19, 2012). The final rule... Markets; Correction AGENCY: Commodity Futures Trading Commission. ACTION: Final rule; correction. SUMMARY... Other Requirements for Designated Contract Markets by inserting a missing instruction to add Appendix...

  5. Characterization of a Solid Oxide Fuel Cell Gas Turbine Hybrid System Based on a Factorial Design of Experiments Using Hardware Simulation

    SciTech Connect

    Restrepo, Bernardo; Banta, Larry E.; Tucker, David

    2012-10-01

    A full factorial experimental design and a replicated fractional factorial design were carried out using the Hybrid Performance (HyPer) project facility installed at the National Energy Technology Laboratory (NETL), U.S. Department of Energy to simulate gasifer/fuel cell/turbine hybrid power systems. The HyPer facility uses hardware in the loop (HIL) technology that couples a modified recuperated gas turbine cycle with hardware driven by a solid oxide fuel cell model. A 34 full factorial design (FFD) was selected to study the effects of four factors: cold-air, hot-air, bleed-air bypass valves, and the electric load on different parameters such as cathode and turbine inlet temperatures, pressure and mass flow. The results obtained, compared with former results where the experiments were made using one-factor-at-a-time (OFAT), show that no strong interactions between the factors are present in the different parameters of the system. This work also presents a fractional factorial design (ffd) 34-2 in order to analyze replication of the experiments. In addition, a new envelope is described based on the results of the design of experiments (DoE), compared with OFAT experiments, and analyzed in an off-design integrated fuel cell/gas turbine framework. This paper describes the methodology, strategy, and results of these experiments that bring new knowledge concerning the operating state space for this kind of power generation system.

  6. Coding design for error correcting output codes based on perceptron

    NASA Astrophysics Data System (ADS)

    Zhou, Jin-Deng; Wang, Xiao-Dan; Zhou, Hong-Jian; Cui, Yong-Hua; Jing, Sun

    2012-05-01

    It is known that error-correcting output codes (ECOC) is a common way to model multiclass classification problems, in which the research of encoding based on data is attracting more and more attention. We propose a method for learning ECOC with the help of a single-layered perception neural network. To achieve this goal, the code elements of ECOC are mapped to the weights of network for the given decoding strategy, and an object function with the constrained weights is used as a cost function of network. After the training, we can obtain a coding matrix including lots of subgroups of class. Experimental results on artificial data and University of California Irvine with logistic linear classifier and support vector machine as the binary learner show that our scheme provides better performance of classification with shorter length of coding matrix than other state-of-the-art encoding strategies.

  7. Sterilization of space hardware.

    NASA Technical Reports Server (NTRS)

    Pflug, I. J.

    1971-01-01

    Discussion of various techniques of sterilization of space flight hardware using either destructive heating or the action of chemicals. Factors considered in the dry-heat destruction of microorganisms include the effects of microbial water content, temperature, the physicochemical properties of the microorganism and adjacent support, and nature of the surrounding gas atmosphere. Dry-heat destruction rates of microorganisms on the surface, between mated surface areas, or buried in the solid material of space vehicle hardware are reviewed, along with alternative dry-heat sterilization cycles, thermodynamic considerations, and considerations of final sterilization-process design. Discussed sterilization chemicals include ethylene oxide, formaldehyde, methyl bromide, dimethyl sulfoxide, peracetic acid, and beta-propiolactone.

  8. Hardware Accelerated Simulated Radiography

    SciTech Connect

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-04-12

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32 bit floating point texture capabilities to obtain validated solutions to the radiative transport equation for X-rays. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedra that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester. We show that the hardware accelerated solution is faster than the current technique used by scientists.

  9. Factors Influencing the Design, Establishment, Administration, and Governance of Correctional Education for Females

    ERIC Educational Resources Information Center

    Ellis, Johnica; McFadden, Cheryl; Colaric, Susan

    2008-01-01

    This article summarizes the results of a study conducted to investigate factors influencing the organizational design, establishment, administration, and governance of correctional education for females. The research involved interviews with correctional and community college administrators and practitioners representing North Carolina female…

  10. The use of real-time, hardware-in-the-loop simulation in the design and development of the new Hughes HS601 spacecraft attitude control system

    NASA Technical Reports Server (NTRS)

    Slafer, Loren I.

    1989-01-01

    Realtime simulation and hardware-in-the-loop testing is being used extensively in all phases of the design, development, and testing of the attitude control system (ACS) for the new Hughes HS601 satellite bus. Realtime, hardware-in-the-loop simulation, integrated with traditional analysis and pure simulation activities is shown to provide a highly efficient and productive overall development program. Implementation of high fidelity simulations of the satellite dynamics and control system algorithms, capable of real-time execution (using applied Dynamics International's System 100), provides a tool which is capable of being integrated with the critical flight microprocessor to create a mixed simulation test (MST). The MST creates a highly accurate, detailed simulated on-orbit test environment, capable of open and closed loop ACS testing, in which the ACS design can be validated. The MST is shown to provide a valuable extension of traditional test methods. A description of the MST configuration is presented, including the spacecraft dynamics simulation model, sensor and actuator emulators, and the test support system. Overall system performance parameters are presented. MST applications are discussed; supporting ACS design, developing on-orbit system performance predictions, flight software development and qualification testing (augmenting the traditional software-based testing), mission planning, and a cost-effective subsystem-level acceptance test. The MST is shown to provide an ideal tool in which the ACS designer can fly the spacecraft on the ground.

  11. 16 CFR 1508.6 - Hardware.

    Code of Federal Regulations, 2011 CFR

    2011-01-01

    ... 16 Commercial Practices 2 2011-01-01 2011-01-01 false Hardware. 1508.6 Section 1508.6 Commercial... FULL-SIZE BABY CRIBS § 1508.6 Hardware. (a) A crib shall be designed and constructed in a manner that eliminates from any hardware accessible to a child within the crib the possibility of the...

  12. Door Hardware and Installations; Carpentry: 901894.

    ERIC Educational Resources Information Center

    Dade County Public Schools, Miami, FL.

    The curriculum guide outlines a course designed to provide instruction in the selection, preparation, and installation of hardware for door assemblies. The course is divided into five blocks of instruction (introduction to doors and hardware, door hardware, exterior doors and jambs, interior doors and jambs, and a quinmester post-test) totaling…

  13. The telescope control of the ASTRI SST-2M prototype for the Cherenkov telescope Array: hardware and software design architecture

    NASA Astrophysics Data System (ADS)

    Antolini, Elisa; Cascone, Enrico; Schwarz, Joseph; Stringhetti, Luca; Tanci, Claudio; Tosti, Gino; Aisa, Damiano; Aisa, Simone; Bagaglia, Marco; Busatta, Andrea; Campeggi, Carlo; Cefala, Marco; Farnesini, Lucio; Giacomel, Stefano; Marchiori, Gianpiero; Marcuzzi, Enrico; Nucciarelli, Giuliano; Piluso, Antonfranco

    2014-07-01

    ASTRI (Astrofisica con Specchi a Tecnologia Replicante Italiana) is a flagship project of the Italian Ministry of Research and led by the Italian National Institute of Astrophysics (INAF). One of its aims is to develop, within the Cherenkov Telescope Array (CTA) framework, an end-to-end small-sized telescope prototype in a dual-mirror configuration (SST-2M) in order to investigate the energy range E ~ 1-100 TeV. A long-term goal of the ASTRI program is the production of an ASTRI/CTA mini-array composed of seven SST-2M telescopes. The prototype, named ASTRI SST-2M, is seen as a standalone system that needs only network and power connections to work. The software system that is being developed to control the prototype is the base for the Mini-Array Software System (MASS), which has the task to make possible the operation of both the ASTRI SST-2M prototype and the ASTRI/CTA mini-array. The scope of this contribution is to give an overview of the hardware and software architecture adopted for the ASTRI SST- 2M prototype, showing how to apply state of the art industrial technologies to telescope control and monitoring systems.

  14. The Space Operations Simulation Center (SOSC) and Closed-loop Hardware Testing for Orion Rendezvous System Design

    NASA Technical Reports Server (NTRS)

    D'Souza, Christopher; Milenkovich, Zoran; Wilson, Zachary; Huich, David; Bendle, John; Kibler, Angela

    2011-01-01

    The Space Operations Simulation Center (SOSC) at the Lockheed Martin (LM) Waterton Campus in Littleton, Colorado is a dynamic test environment focused on Autonomous Rendezvous and Docking (AR&D) development testing and risk reduction activities. The SOSC supports multiple program pursuits and accommodates testing Guidance, Navigation, and Control (GN&C) algorithms for relative navigation, hardware testing and characterization, as well as software and test process development. The SOSC consists of a high bay (60 meters long by 15.2 meters wide by 15.2 meters tall) with dual six degree-of-freedom (6DOF) motion simulators and a single fixed base 6DOF robot. The large testing area (maximum sensor-to-target effective range of 60 meters) allows for large-scale, flight-like simulations of proximity maneuvers and docking events. The facility also has two apertures for access to external extended-range outdoor target test operations. In addition, the facility contains four Mission Operations Centers (MOCs) with connectivity to dual high bay control rooms and a data/video interface room. The high bay is rated at Class 300,000 (. 0.5 m maximum particles/m3) cleanliness and includes orbital lighting simulation capabilities.

  15. Hardware Counter Multiplexing

    Energy Science and Technology Software Center (ESTSC)

    2000-10-13

    The Hardware Counter Multiplexer works with the built-in counter registers on computer processors. These counters record various low-level events as software runs, but they can not record all possible events at the same time. This software helps work around that limitation by counting a series of different events in sequence over a period of time. This in turn allows programmers to measure interesting combinations of events, rather than single events. The software is designed tomore » work with multithreaded or single-threaded programs.« less

  16. Energy efficient engine: Turbine intermediate case and low-pressure turbine component test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Leach, K.; Thulin, R. D.; Howe, D. C.

    1982-01-01

    A four stage, low pressure turbine component has been designed to power the fan and low pressure compressor system in the Energy Efficient Engine. Designs for a turbine intermediate case and an exit guide vane assembly also have been established. The components incorporate numerous technology features to enhance efficiency, durability, and performance retention. These designs reflect a positive step towards improving engine fuel efficiency on a component level. The aerodynamic and thermal/mechanical designs of the intermediate case and low pressure turbine components are presented and described. An overview of the predicted performance of the various component designs is given.

  17. Growth and development of Arabidopsis in the Advanced Biological Research System (ABRS) hardware designed for the International Space Station

    NASA Astrophysics Data System (ADS)

    Savidge, Rodney

    Wild type (Col 0) Arabidopsis thaliana were grown in a growth chamber within the single mid-deck sized Advanced Biological Research System (ABRS) spaceflight hardware developed by NASA Kennedy Space Center. Before beginning this experiment, the plants, each rooted in individual transferable tubes containing nutrients, were cultivated hydroponically on halfstrength Hoagland's solution beneath either LED lighting similar to that provided by the ABRS growth chamber or white fluorescent lighting. The leaves of the basal whorl of plants pre-grown in ABRS lighting were small and purplish at the start of the experiment, whereas those under fluorescent lighting were larger and green. The plants were transferred to the ABRS soon after their inflorescence axes had started to elongate, and thereafter they were maintained under preset conditions (22 o C, approximately 1500 ppm CO2 , predominantly 125 µmol m-2 s-1 PAR) with pulses of water provided at 1-3 d intervals (as needed) to the module into which the root tubes were inserted. That module was pre-treated with half-strength Hoagland's nutrient solution on day 0, but no additional nutrients were provided the plants thereafter. Strong primary growth of all inflorescence stems occurred soon after initiating the ABRS experiment, and the plants began forming an overarching canopy of flowering stems beneath the LED lighting module within two weeks. After 38 days the root module was littered with seeds, siliques and abscised leaves, but all plants remained alive. Plants pre-grown in ABRS lighting were more advanced toward senescence, and leaves and stems of plants pre-grown in fluorescent lighting although greener were also acquiring a purplish hue. Microscopy revealed that the flowering stems achieved no secondary growth; however, progressive inward conversion of pith parenchyma into sclerenchyma cells did occur resulting in the inflorescence stems becoming abnormally woody.

  18. 78 FR 15755 - Proposed Revision to Design of Structures, Components, Equipment and Systems; Correction

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-03-12

    ... March 1, 2013 (41 FR 13911), that announced the solicitation for comments of the proposed revision in Chapter 3, ``Design of Structures, Components, Equipment, and Systems'' and is soliciting public comment... COMMISSION Proposed Revision to Design of Structures, Components, Equipment and Systems; Correction...

  19. 75 FR 38129 - Freescale Semiconductor, Inc., Hardware/Software Design and Manufacturing A Including On-Site...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-07-01

    ... published in the Federal Register on May 28, 2010 (75 FR 30070). At the request of the State Agency, the... Manufacturing A Including On-Site Leased Workers From TAC Worldwide, GDA Technologies, Inc., Manpower, Ion..., GDA Technologies, Inc., Manpower, Ion Design, Design Solutions, Inc., Veriseo, SilconElite and...

  20. Design and development of a wireless sensor network to monitor snow depth in multiple catchments in the American River basin, California: hardware selection and sensor placement techniques

    NASA Astrophysics Data System (ADS)

    Kerkez, B.; Rice, R.; Glaser, S. D.; Bales, R. C.; Saksa, P. C.

    2010-12-01

    A 100-node wireless sensor network (WSN) was designed for the purpose of monitoring snow depth in two watersheds, spanning 3 km2 in the American River basin, in the central Sierra Nevada of California. The network will be deployed as a prototype project that will become a core element of a larger water information system for the Sierra Nevada. The site conditions range from mid-elevation forested areas to sub-alpine terrain with light forest cover. Extreme temperature and humidity fluctuations, along with heavy rain and snowfall events, create particularly challenging conditions for wireless communications. We show how statistics gathered from a previously deployed 60-node WSN, located in the Southern Sierra Critical Zone Observatory, were used to inform design. We adapted robust network hardware, manufactured by Dust Networks for highly demanding industrial monitoring, and added linear amplifiers to the radios to improve transmission distances. We also designed a custom data-logging board to interface the WSN hardware with snow-depth sensors. Due to the large distance between sensing locations, and complexity of terrain, we analyzed network statistics to select the location of repeater nodes, to create a redundant and reliable mesh. This optimized network topology will maximize transmission distances, while ensuring power-efficient network operations throughout harsh winter conditions. At least 30 of the 100 nodes will actively sense snow depth, while the remainder will act as sensor-ready repeaters in the mesh. Data from a previously conducted snow survey was used to create a Gaussian Process model of snow depth; variance estimates produced by this model were used to suggest near-optimal locations for snow-depth sensors to measure the variability across a 1 km2 grid. We compare the locations selected by the sensor placement algorithm to those made through expert opinion, and offer explanations for differences resulting from each approach.

  1. Open-source hardware for medical devices

    PubMed Central

    2016-01-01

    Open-source hardware is hardware whose design is made publicly available so anyone can study, modify, distribute, make and sell the design or the hardware based on that design. Some open-source hardware projects can potentially be used as active medical devices. The open-source approach offers a unique combination of advantages, including reducing costs and faster innovation. This article compares 10 of open-source healthcare projects in terms of how easy it is to obtain the required components and build the device. PMID:27158528

  2. Constructing Hardware in a Scale Embedded Language

    SciTech Connect

    Bachan, John

    2014-08-21

    Chisel is a new open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. Chisel is embedded in the Scala programming language, which raises the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. From the same source, Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to pass on to standard ASIC or FPGA tools for synthesis and place and route.

  3. Constructing Hardware in a Scale Embedded Language

    Energy Science and Technology Software Center (ESTSC)

    2014-08-21

    Chisel is a new open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. Chisel is embedded in the Scala programming language, which raises the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. From the same source, Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to pass onmore » to standard ASIC or FPGA tools for synthesis and place and route.« less

  4. Hardware removal - extremity

    MedlinePlus

    ... this page: //medlineplus.gov/ency/article/007644.htm Hardware removal - extremity To use the sharing features on this page, please enable JavaScript. Surgeons use hardware such as pins, plates, or screws to help ...

  5. Engineering aspects and hardware verification of a volume producable solid oxide fuel cell stack design for diesel auxiliary power units

    NASA Astrophysics Data System (ADS)

    Stelter, Michael; Reinert, Andreas; Mai, Björn Erik; Kuznecov, Mihail

    A solid oxide fuel cell (SOFC) stack module is presented that is designed for operation on diesel reformate in an auxiliary power unit (APU). The stack was designed using a top-down approach, based on a specification of an APU system that is installed on board of vehicles. The stack design is planar, modular and scalable with stamped sheet metal interconnectors. It features thin membrane electrode assemblies (MEAs), such as electrolyte supported cells (ESC) and operates at elevated temperatures around 800 °C. The stack has a low pressure drop in both the anode and the cathode to facilitate a simple system layout. An overview of the technical targets met so far is given. A stack power density of 0.2 kW l -1 has been demonstrated in a fully integrated, thermally self-sustaining APU prototype running with diesel and without an external water supply.

  6. Modular hardware synthesis using an HDL. [Hardware Description Language

    NASA Technical Reports Server (NTRS)

    Covington, J. A.; Shiva, S. G.

    1981-01-01

    Although hardware description languages (HDL) are becoming more and more necessary to automated design systems, their application is complicated due to the difficulty in translating the HDL description into an implementable format, nonfamiliarity of hardware designers with high-level language programming, nonuniform design methodologies and the time and costs involved in transfering HDL design software. Digital design language (DDL) suffers from all of the above problems and in addition can only by synthesized on a complete system and not on its subparts, making it unsuitable for synthesis using standard modules or prefabricated chips such as those required in LSI or VLSI circuits. The present paper presents a method by which the DDL translator can be made to generate modular equations that will allow the system to be synthesized as an interconnection of lower-level modules. The method involves the introduction of a new language construct called a Module which provides for the separate translation of all equations bounded by it.

  7. The Space Operations Simulation Center (SOSC) and Closed-Loop Hardware Testing for Orion Rendezvous System Design

    NASA Technical Reports Server (NTRS)

    Milenkovic, Zoran; DSouza, Christopher; Huish, David; Bendle, John; Kibler, Angela

    2012-01-01

    The exploration goals of Orion / MPCV Project will require a mature Rendezvous, Proximity Operations and Docking (RPOD) capability. Ground testing autonomous docking with a next-generation sensor such as the Vision Navigation Sensor (VNS) is a critical step along the path of ensuring successful execution of autonomous RPOD for Orion. This paper will discuss the testing rationale, the test configuration, the test limitations and the results obtained from tests that have been performed at the Lockheed Martin Space Operations Simulation Center (SOSC) to evaluate and mature the Orion RPOD system. We will show that these tests have greatly increased the confidence in the maturity of the Orion RPOD design, reduced some of the latent risks and in doing so validated the design philosophy of the Orion RPOD system. This paper is organized as follows: first, the objectives of the test are given. Descriptions of the SOSC facility, and the Orion RPOD system and associated components follow. The details of the test configuration of the components in question are presented prior to discussing preliminary results of the tests. The paper concludes with closing comments.

  8. Designedly Incomplete Utterances: A Pedagogical Practice for Eliciting Knowledge Displays in Error Correction Sequences.

    ERIC Educational Resources Information Center

    Koshik, Irene

    2002-01-01

    Uses a conversation analytic framework to analyze a practice used by teachers in 1-0-1, second language writing conferences when eliciting self-correction of students' written language errors. This type of turn used to elicit a knowledge display from the student is labeled designedly incomplete utterance (DIU). Teachers use DIUs made up of…

  9. Bias Corrections for Standardized Effect Size Estimates Used with Single-Subject Experimental Designs

    ERIC Educational Resources Information Center

    Ugille, Maaike; Moeyaert, Mariola; Beretvas, S. Natasha; Ferron, John M.; Van den Noortgate, Wim

    2014-01-01

    A multilevel meta-analysis can combine the results of several single-subject experimental design studies. However, the estimated effects are biased if the effect sizes are standardized and the number of measurement occasions is small. In this study, the authors investigated 4 approaches to correct for this bias. First, the standardized effect…

  10. 78 FR 28291 - Unblocking of 1 Individual Designated Pursuant to Executive Order 13572; Correction

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-05-14

    ... Persons with Respect to Human Rights Abuses in Syria'' from the list of Specially Designated Nationals and... President issued Executive Order 13572, ``Blocking Property of Certain Persons with Respect to Human Rights.../622-0077. Correction In the notice published in the Federal Register on April 25, 2013 at 78 FR...

  11. Visualizing the Future of Research on Post Secondary Correctional Education: Designs, Data, and Deliverables

    ERIC Educational Resources Information Center

    Wheeldon, J.

    2011-01-01

    Providing post-secondary education in correctional settings has emerged as one of the best ways to reduce recidivism, save taxpayer dollars, and promote post release employment and community reintegration. While a number of studies exist, this paper argues persistent challenges connected to research design, data collection, and the communication…

  12. The APACHE survey hardware and software design: Tools for an automatic search of small-size transiting exoplanets

    NASA Astrophysics Data System (ADS)

    Christille, Jean-Marc; Bernagozzi, A.; Bertolini, E.; Calcidese, P.; Carbognani, A.; Cenadelli, D.; Damasso, M.; Giacobbe, P.; Lanteri, L.; Lattanzi, M. G.; Sozzetti, A.; Smart, R.

    2013-04-01

    Small-size ground-based telescopes can effectively be used to look for transiting rocky planets around nearby low-mass M stars using the photometric transit method, as recently demonstrated for example by the MEarth project. Since 2008 at the Astronomical Observatory of the Autonomous Region of Aosta Valley (OAVdA), we have been preparing for the long-term photometric survey APACHE, aimed at finding transiting small-size planets around thousands of nearby early and mid-M dwarfs. APACHE (A PAthway toward the Characterization of Habitable Earths) is designed to use an array of five dedicated and identical 40-cm Ritchey-Chretien telescopes and its observations started at the beginning of summer 2012. The main characteristics of the survey final set up and the preliminary results from the first weeks of observations will be discussed.

  13. Hardware description ADSP-21020 40-bit floating point DSP as designed in a remotely controlled digital CW Doppler radar

    SciTech Connect

    Morrison, R.E.; Robinson, S.H.

    1991-01-01

    A continuous wave Doppler radar system has been designed which is portable, easily deployed, and remotely controlled. The heart of this system is a DSP/control board using Analog Devices ADSP-21020 40-bit floating point digital signal processor (DSP) microprocessor. Two 18-bit audio A/D converters provide digital input to the DSP/controller board for near real time target detection. Program memory for the DSP is dual ported with an Intel 87C51 microcontroller allowing DSP code to be up-loaded or down-loaded from a central controlling computer. The 87C51 provides overall system control for the remote radar and includes a time-of-day/day-of-year real time clock, system identification (ID) switches, and input/output (I/O) expansion by an Intel 82C55 I/O expander. 5 refs., 8 figs., 2 tabs.

  14. Open-loop correction of horizontal turbulence: system design and result.

    PubMed

    Mu, Quanquan; Cao, Zhaoliang; Li, Dayu; Hu, Lifa; Xuan, Li

    2008-08-10

    Adaptive optics systems often work in a closed-loop configuration due to the hysteretic and nonlinearity properties of conventional deformable mirrors. Because of the high-precision wavefront generation and nonhysteretic properties of liquid-crystal devices, the open-loop control becomes possible. Open-loop control is a requirement for advanced adaptive optics concepts. We designed an open-loop adaptive optics system with a liquid-crystal-on-silicon wavefront corrector. This system is simple, fast, and can save much more light compared to conventional liquid-crystal-based closed-loop systems. The detailed principle, construction, and operation are discussed. The 500 m horizontal turbulence correction experiment was done using a 250 mm telescope in the laboratory. The whole system can reach a 60 Hz correction frequency. Evaluation of the correction precision was done at closed-loop configuration, which is 0.2 lambda (lambda=0.633 microm) in peak to valley. The dynamic image under open-loop correction got the same resolution compared to closed-loop correction. The whole system reached 0.68 arc sec resolution capability at open-loop correction, which is slightly larger than the system's diffraction-limited resolution of 0.65 arc sec. PMID:18690274

  15. Electrical Safety for Human Space Flight Payload Hardware

    NASA Astrophysics Data System (ADS)

    Runnells, James A.

    2010-09-01

    Human Space Flight payload hardware designs must address both mission success and safety requirements for flight on the Space Shuttle, International Space Station(ISS), or International Partner(IP) Launch Vehicles. Flight hardware generally can be considered either Government Furnished Equipment(GFE) or Payload hardware, although some Commercial-off-the-shelf(COTS) hardware is also flown. In this case we will use the payload flight hardware system safety perspective, which closely resembles the GFE system safety process with a few exceptions. Why is Human space flight hardware treated differently than ground hardware? The key reason flight hardware is treated more conservatively than ground hardware is the relative impact to crew and vehicle, and the relative inability to provide immediate recovery of a disabled space vehicle or crewmember on-orbit. One aspect of safe payload flight hardware design is Electrical Power Systems(EPS), including the safe design and operations of electrical power systems for payloads.

  16. Broadband astigmatism-corrected spectrometer design using a toroidal lens and a special filter

    NASA Astrophysics Data System (ADS)

    Ge, Xianying; Chen, Siying; Zhang, Yinchao; Chen, He; Guo, Pan; Mu, Taotao; Yang, Jian; Bu, Zhichao

    2015-01-01

    In the paper, a method to obtain a broadband, astigmatism-corrected spectrometer based on the existing Czerny-Turner spectrometer is proposed. The theories of astigmatism correction using a toroidal lens and a special filter are described in detail. Performance comparisons of the modified spectrometer and the traditional spectrometer are also presented. Results show that with the new design the RMS spot radius in sagittal view is one-eightieth of that in the traditional spectrometer over a broadband spectral range from 300 to 700 nm, without changing or moving any optical elements in the traditional spectrometer.

  17. Fault tolerant VLSI (Very Large-Scale Integration) design using error correcting codes

    NASA Astrophysics Data System (ADS)

    Hartmann, C. R.; Lala, P. K.; Ali, A. M.; Ganguly, S.; Visweswaran, G. S.

    1989-02-01

    Very Large-Scale Integration (VLSI) provides the opportunity to design fault tolerant, self-checking circuits with on-chip, concurrent error correction. This study determines the applicability of a variety of error-detecting, error-correcting codes (EDAC) in high speed digital data processors and buses. In considering both microcircuit faults and bus faults, some of the codes examined are: Berger, repetition, parity, residue, and Modified Reflected Binary codes. The report describes the improvement in fault tolerance obtained as a result of implementing these EDAC schemes and the associated penalties in circuit area.

  18. Correction of magnetooptic device phase errors in optical correlators through filter design modifications

    NASA Technical Reports Server (NTRS)

    Downie, John D.; Reid, Max B.; Hine, Butler P.

    1991-01-01

    We address the problem of optical phase errors in an optical correlator introduced by the input and filter plane spatial light modulators. Specifically, we study a laboratory correlator with magnetooptic spatial light modulator (MOSLM) devices. We measure and characterize the phase errors, analyze their effects on the correlation process, and discuss a means of correction through a design modification of the binary phase-only optical filter function. The phase correction technique is found to produce correlation results close to those of an error-free correlator.

  19. Novel Principles and Techniques to Create a Natural Design in Female Hairline Correction Surgery

    PubMed Central

    2015-01-01

    Abstract Background: Female hairline correction surgery is becoming increasingly popular. However, no guidelines or methods of female hairline design have been introduced to date. Methods: The purpose of this study was to create an initial framework based on the novel principles of female hairline design and then use artistic ability and experience to fine tune this framework. An understanding of the concept of 5 areas (frontal area, frontotemporal recess area, temporal peak, infratemple area, and sideburns) and 5 points (C, A, B, T, and S) is required for female hairline correction surgery (the 5A5P principle). The general concepts of female hairline correction surgery and natural design methods are, herein, explained with a focus on the correlations between these 5 areas and 5 points. Results: A natural and aesthetic female hairline can be created with application of the above-mentioned concepts. Conclusion: The 5A5P principle of forming the female hairline is very useful in female hairline correction surgery. PMID:26894014

  20. Towards composition of verified hardware devices

    NASA Technical Reports Server (NTRS)

    Schubert, E. Thomas; Levitt, K.; Cohen, G. C.

    1991-01-01

    Computers are being used where no affordable level of testing is adequate. Safety and life critical systems must find a replacement for exhaustive testing to guarantee their correctness. Through a mathematical proof, hardware verification research has focused on device verification and has largely ignored system composition verification. To address these deficiencies, we examine how the current hardware verification methodology can be extended to verify complete systems.

  1. Viscous microstructural dampers with aligned holes: design procedure including the edge correction.

    PubMed

    Homentcovschi, Dorel; Miles, Ronald N

    2007-09-01

    The paper is a continuation of the works "Modelling of viscous damping of perforated planar micromechanical structures. Applications in acoustics" [Homentcovschi and Miles, J. Acoust. Soc. Am. 116, 2939-2947 (2004)] and "Viscous Damping of Perforated Planar Micromechanical Structures" [Homentcovschi and Miles, Sensors Actuators, A119, 544-552 (2005)] where design formulas for the case of an offset (staggered) system of holes was provided. The present work contains design formulas for perforated planar microstructures used in MEMS devices (such as proof-masses in accelerometers, backplates in microphones, micromechanical switches, resonators, tunable microoptical interferometers, etc.) in the case of aligned (nonstaggered) holes of circular and square section. The given formulas assure a minimum total damping coefficient (including the squeeze film damping and the direct and indirect resistance of the holes) for an assigned open area. The paper also gives a simple edge correction, making it possible to consider real (finite) perforated planar microstructures. The proposed edge correction is validated by comparison with the results obtained by FEM simulations: the relative error is found to be smaller than 0.04%. By putting together the design formulas with the edge correction a simple integrated design procedure for obtaining viscous perforated dampers with assigned properties is obtained. PMID:17927414

  2. Thermal Hardware for the Thermal Analyst

    NASA Technical Reports Server (NTRS)

    Steinfeld, David

    2015-01-01

    The presentation will be given at the 26th Annual Thermal Fluids Analysis Workshop (TFAWS 2015) hosted by the Goddard Space Flight Center (GSFC) Thermal Engineering Branch (Code 545). NCTS 21070-1. Most Thermal analysts do not have a good background into the hardware which thermally controls the spacecraft they design. SINDA and Thermal Desktop models are nice, but knowing how this applies to the actual thermal hardware (heaters, thermostats, thermistors, MLI blanketing, optical coatings, etc...) is just as important. The course will delve into the thermal hardware and their application techniques on actual spacecraft. Knowledge of how thermal hardware is used and applied will make a thermal analyst a better engineer.

  3. Computer hardware description languages - A tutorial

    NASA Technical Reports Server (NTRS)

    Shiva, S. G.

    1979-01-01

    The paper introduces hardware description languages (HDL) as useful tools for hardware design and documentation. The capabilities and limitations of HDLs are discussed along with the guidelines needed in selecting an appropriate HDL. The directions for future work are provided and attention is given to the implementation of HDLs in microcomputers.

  4. 16 CFR 1508.6 - Hardware.

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... 16 Commercial Practices 2 2010-01-01 2010-01-01 false Hardware. 1508.6 Section 1508.6 Commercial Practices CONSUMER PRODUCT SAFETY COMMISSION FEDERAL HAZARDOUS SUBSTANCES ACT REGULATIONS REQUIREMENTS FOR FULL-SIZE BABY CRIBS § 1508.6 Hardware. (a) A crib shall be designed and constructed in a manner...

  5. Research on bottlenecks of RAID controller hardware

    NASA Astrophysics Data System (ADS)

    Tan, Zhihu; Chen, Jie; Hu, Huaixiang

    2008-12-01

    RAID systems provide both improved capacity and performance as compared to single disk by striping data to multiple disks, and improve reliability efficiently by redundancy techniques, now RAID becomes key storage device for massive storage system. There are two ways to implement the RAID system: the first is to implement as a software subsystem under PC platform, the second is to implement as a hardware controller. The second one is more common. We have designed and implemented a RAID hardware controller, which called DSDM-FC2000. This paper discusses three kinds of bottlenecks of the DSDM-FC2000 RAID hardware controller: PCI transmission bottleneck, memory access bottleneck and CPU computation bottleneck, and then presents an optimized hardware XOR algorithm which can improve the RAID performance efficiently. Finally this paper gives some advises on designing new generation RAID controller hardware.

  6. Commercial Aircraft Maintenance Experience Relating to Engine External Hardware

    NASA Technical Reports Server (NTRS)

    Soditus, Sharon M.

    2006-01-01

    Airlines are extremely sensitive to the amount of dollars spent on maintaining the external engine hardware in the field. Analysis reveals that many problems revolve around a central issue, reliability. Fuel and oil leakage due to seal failure and electrical fault messages due to wire harness failures play a major role in aircraft delays and cancellations (D&C's) and scheduled maintenance. Correcting these items on the line requires a large investment of engineering resources and manpower after the fact. The smartest and most cost effective philosophy is to build the best hardware the first time. The only way to do that is to completely understand and model the operating environment, study the field experience of similar designs and to perform extensive testing.

  7. Hardware-Accelerated Simulated Radiography

    SciTech Connect

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-08-04

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32-bit floating point texture capabilities to obtain solutions to the radiative transport equation for X-rays. The hardware accelerated solutions are accurate enough to enable scientists to explore the experimental design space with greater efficiency than the methods currently in use. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedral meshes that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester.

  8. Design and analysis of site-specific single-strand nicking endonucleases for gene correction.

    PubMed

    Metzger, Michael J; Certo, Michael T

    2014-01-01

    Single-strand nicking endonucleases ("nickases") have been shown to induce homology-mediated gene correction with reduced toxicity of DNA double-strand break-producing enzymes, and nickases have been engineered from both homing endonuclease and FokI-based scaffolds. We describe the strategies used to engineer these site-specific nickases as well as the in vitro methods used to confirm their activity and specificity. Additionally, we describe the Traffic Light Reporter system, which uses a flow cytometric assay to simultaneously detect both gene repair and mutagenic nonhomologous end-joining outcomes at a single targeted site in mammalian cells. With these methods, novel nickases can be designed and tested for use in gene correction with novel target sites. PMID:24557907

  9. Hardware Testing and System Evaluation: Procedures to Evaluate Commodity Hardware for Production Clusters

    SciTech Connect

    Goebel, J

    2004-02-27

    Without stable hardware any program will fail. The frustration and expense of supporting bad hardware can drain an organization, delay progress, and frustrate everyone involved. At Stanford Linear Accelerator Center (SLAC), we have created a testing method that helps our group, SLAC Computer Services (SCS), weed out potentially bad hardware and purchase the best hardware at the best possible cost. Commodity hardware changes often, so new evaluations happen periodically each time we purchase systems and minor re-evaluations happen for revised systems for our clusters, about twice a year. This general framework helps SCS perform correct, efficient evaluations. This article outlines SCS's computer testing methods and our system acceptance criteria. We expanded the basic ideas to other evaluations such as storage, and we think the methods outlined in this article has helped us choose hardware that is much more stable and supportable than our previous purchases. We have found that commodity hardware ranges in quality, so systematic method and tools for hardware evaluation were necessary. This article is based on one instance of a hardware purchase, but the guidelines apply to the general problem of purchasing commodity computer systems for production computational work.

  10. Effective safety measures with tests followed by design correction for aerospace structures

    NASA Astrophysics Data System (ADS)

    Matsumura, Taiki

    Analytical and computational prediction tools enable us to design aircraft and spacecraft components with high degree of confidence. While the accuracy of such predictions has been improved over the years, uncertainty continues to be added by new materials and new technology introduced in order to improve performance. This requires us to have reality checks, such as tests, in order to make sure that the prediction tools are reliable enough to ensure safety. While tests can reveal unsafe designs and lead to design correction, these tests are very costly. Therefore, it is important to manage such a design-test-correction cycle effectively. In this dissertation, we consider three important test stages in the lifecycle of an aviation system. First, we dealt with characterization tests that reveal failure modes of new materials or new geometrical arrangements. We investigated the challenge associated with getting the best characterization with a limited number of tests. We have found that replicating tests to attenuate the effect of noise in observation is not necessary because some surrogate models can serve as a noise filter without having replicated data. Instead, we should focus on exploring the design space with different structural configurations in order to discover unknown failure modes. Next, we examined post-design tests for design acceptance followed by possible redesign. We looked at the question of how to balance the desire for better performance achieved by redesign against the cost of redesign. We proposed a design optimization framework that provides tradeoff information between the expected performance improvement by redesign and the probability of redesign, equivalent to the cost of redesign. We also demonstrated that the proposed method can reduce the performance loss due to a conservative reliability estimate. The ultimate test, finally, is whether the structures do not fail in flight. Once an accident occurs, an accident investigation takes place

  11. Mechanically verified hardware implementing an 8-bit parallel IO Byzantine agreement processor

    NASA Technical Reports Server (NTRS)

    Moore, J. Strother

    1992-01-01

    Consider a network of four processors that use the Oral Messages (Byzantine Generals) Algorithm of Pease, Shostak, and Lamport to achieve agreement in the presence of faults. Bevier and Young have published a functional description of a single processor that, when interconnected appropriately with three identical others, implements this network under the assumption that the four processors step in synchrony. By formalizing the original Pease, et al work, Bevier and Young mechanically proved that such a network achieves fault tolerance. We develop, formalize, and discuss a hardware design that has been mechanically proven to implement their processor. In particular, we formally define mapping functions from the abstract state space of the Bevier-Young processor to a concrete state space of a hardware module and state a theorem that expresses the claim that the hardware correctly implements the processor. We briefly discuss the Brock-Hunt Formal Hardware Description Language which permits designs both to be proved correct with the Boyer-Moore theorem prover and to be expressed in a commercially supported hardware description language for additional electrical analysis and layout. We briefly describe our implementation.

  12. Initial Hardware Development Schedule

    NASA Technical Reports Server (NTRS)

    Culpepper, William X.

    1991-01-01

    The hardware development schedule for the Common Lunar Lander's (CLLs) tracking system is presented. Among the topics covered are the following: historical perspective, solution options, industry contacts, and the rationale for selection.

  13. Orbiter CIU/IUS communications hardware evaluation

    NASA Technical Reports Server (NTRS)

    Huth, G. K.

    1979-01-01

    Inertial Upper Stage (IUS) and DoD Communication Interface Unit (CIU) communication system design, hardware specifications, and interfaces were evaluated to determine their compatibility with the Orbiter payload communication and data handling equipment and the Orbiter network communication equipment.

  14. Prime focus wide-field corrector designs with lossless atmospheric dispersion correction

    SciTech Connect

    Saunders, Will; Gillingham, Peter; Smith, Greg; Kent, Steve; Doel, Peter

    2014-07-18

    Wide-Field Corrector designs are presented for the Blanco and Mayall telescopes, the CFHT and the AAT. The designs are Terezibh-style, with 5 or 6 lenses, and modest negative optical power. They have 2.2-3 degree fields of view, with curved and telecentric focal surfaces suitable for fiber spectroscopy. Some variants also allow wide-field imaging, by changing the last WFC element. Apart from the adaptation of the Terebizh design for spectroscopy, the key feature is a new concept for a 'Compensating Lateral Atmospheric Dispersion Corrector', with two of the lenses being movable laterally by small amounts. This provides excellent atmospheric dispersion correction, without any additional surfaces or absorption. A novel and simple mechanism for providing the required lens motions is proposed, which requires just 3 linear actuators for each of the two moving lenses.

  15. Bion 11 mission hardware.

    PubMed

    Golov, V K; Magedov, V S; Skidmore, M G; Hines, J W; Kozlovskaya, I B; Korolkov, V I

    2000-01-01

    The mission hardware provided for Bion 11 shared primate experiments included the launch vehicle, biosatellite, spaceflight operational systems, spacecraft recovery systems, life support systems, bioinstrumentation, and data collection systems. Under the unique Russia/US bilateral contract, the sides worked together to ensure the reliability and quality of hardware supporting the primate experiments. Parameters recorded inflight covered biophysical, biochemical, biopotential, environmental, and system operational status. PMID:11543453

  16. Applying a Genetic Algorithm to Reconfigurable Hardware

    NASA Technical Reports Server (NTRS)

    Wells, B. Earl; Weir, John; Trevino, Luis; Patrick, Clint; Steincamp, Jim

    2004-01-01

    This paper investigates the feasibility of applying genetic algorithms to solve optimization problems that are implemented entirely in reconfgurable hardware. The paper highlights the pe$ormance/design space trade-offs that must be understood to effectively implement a standard genetic algorithm within a modem Field Programmable Gate Array, FPGA, reconfgurable hardware environment and presents a case-study where this stochastic search technique is applied to standard test-case problems taken from the technical literature. In this research, the targeted FPGA-based platform and high-level design environment was the Starbridge Hypercomputing platform, which incorporates multiple Xilinx Virtex II FPGAs, and the Viva TM graphical hardware description language.

  17. Design and progress toward a multi-conjugate adaptive optics system for distributed aberration correction

    SciTech Connect

    Baker, K; Olivier, S; Tucker, J; Silva, D; Gavel, D; Lim, R; Gratrix, E

    2004-08-17

    This article investigates the use of a multi-conjugate adaptive optics system to improve the field-of-view for the system. The emphasis of this research is to develop techniques to improve the performance of optical systems with applications to horizontal imaging. The design and wave optics simulations of the proposed system are given. Preliminary results from the multi-conjugate adaptive optics system are also presented. The experimental system utilizes a liquid-crystal spatial light modulator and an interferometric wave-front sensor for correction and sensing of the phase aberrations, respectively.

  18. Formal hardware verification of digital circuits

    NASA Technical Reports Server (NTRS)

    Joyce, J.; Seger, C.-J.

    1991-01-01

    The use of formal methods to verify the correctness of digital circuits is less constrained by the growing complexity of digital circuits than conventional methods based on exhaustive simulation. This paper briefly outlines three main approaches to formal hardware verification: symbolic simulation, state machine analysis, and theorem-proving.

  19. The correct lens mount lightweighting design and thermal stress OPD analysis in Cassegrain telescope

    NASA Astrophysics Data System (ADS)

    Hsu, Ming-Ying; Chan, Chia-Yen; Lin, Wei-Cheng; Chang, Shenq-Tsong; Huang, Ting-Ming

    2013-09-01

    This study is trying to evaluate different lens barrel material, caused lens stress OPD (Optical Path Different) in different temperature condition. The Cassegrain telescope's correct lens assembly are including as correct lens, lens mount, spacer, mount barrel and retainer. The lens barrel initial design is made by invar, but system mass limit is need to lightweighting to meet requirement. Therefore, the lens barrel material is tried to replace to lower density material, such as aluminum and titanium alloy. Meanwhile, the aluminum or titanium alloy material properties CTE (Coefficient of Thermal Expansion) are larger then invar. Thus, the high CTE material will introduce larger thermal stress into the optical system in different temperature condition. This article is analysis the correct lens assembly thermal stress and optical performance in different lens mount material. From above conditions, using FEM (Finite Element Method) and optical software, simulation and optimization the lens mount to achieve system mass requirement.

  20. Microbiologic assay of space hardware.

    NASA Technical Reports Server (NTRS)

    Favero, M. S.

    1971-01-01

    Review of the procedures used in the microbiological examination of space hardware. The general procedure for enumerating aerobic and anaerobic microorganisms and spores is outlined. Culture media and temperature-time cycles used for incubation are reviewed, along with assay systems designed for the enumeration of aerobic and anaerobic spores. The special problems which are discussed are involved in the precise and accurate enumeration of microorganisms on surfaces and in the neutralization of viable organisms buried inside solid materials that could be released to a planet's surface if the solid should be fractured. Special attention is given to sampling procedures including also the indirect techniques of surface assays of space hardware such as those using detachable or fallout strips. Some data on comparative levels of microbial contamination on lunar and planetary spacecraft are presented.

  1. Decoding: Codes and hardware implementation

    NASA Technical Reports Server (NTRS)

    Sulzer, M. P.; Woodman, R. F.

    1983-01-01

    The MST radars vary considerably from one installation to the next in the type of hardware, operating schedule and associated personnel. Most such systems do not have the computing power to decode in software when the decoding must be performed for each received pulse, as is required for certain sets of phase codes. These sets provide the best signal to sidelobe ratio when operating at the minimum band length allowed by the bandwidth of the transmitter. The development of the hardware phase decoder, and the applicability of each to decoding MST radar signals are discussed. A new design for a decoder which is very inexpensive to build, easy to add to an existing system and is capable of decoding on each received pulse using codes with a band length as short as one microsecond is presented.

  2. DESIGN OF TWO-DIMENSIONAL SUPERSONIC TURBINE ROTOR BLADES WITH BOUNDARY-LAYER CORRECTION

    NASA Technical Reports Server (NTRS)

    Goldman, L. J.

    1994-01-01

    A computer program has been developed for the design of supersonic rotor blades where losses are accounted for by correcting the ideal blade geometry for boundary layer displacement thickness. The ideal blade passage is designed by the method of characteristics and is based on establishing vortex flow within the passage. Boundary-layer parameters (displacement and momentum thicknesses) are calculated for the ideal passage, and the final blade geometry is obtained by adding the displacement thicknesses to the ideal nozzle coordinates. The boundary-layer parameters are also used to calculate the aftermixing conditions downstream of the rotor blades assuming the flow mixes to a uniform state. The computer program input consists essentially of the rotor inlet and outlet Mach numbers, upper- and lower-surface Mach numbers, inlet flow angle, specific heat ratio, and total flow conditions. The program gas properties are set up for air. Additional gases require changes to be made to the program. The computer output consists of the corrected rotor blade coordinates, the principal boundary-layer parameters, and the aftermixing conditions. This program is written in FORTRAN IV for batch execution and has been implemented on an IBM 7094. This program was developed in 1971.

  3. Computer hardware fault administration

    DOEpatents

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-09-14

    Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

  4. Space shuttle main engine hardware simulation

    NASA Technical Reports Server (NTRS)

    Vick, H. G.; Hampton, P. W.

    1985-01-01

    The Huntsville Simulation Laboratory (HSL) provides a simulation facility to test and verify the space shuttle main engine (SSME) avionics and software system using a maximum complement of flight type hardware. The HSL permits evaluations and analyses of the SSME avionics hardware, software, control system, and mathematical models. The laboratory has performed a wide spectrum of tests and verified operational procedures to ensure system component compatibility under all operating conditions. It is a test bed for integration of hardware/software/hydraulics. The HSL is and has been an invaluable tool in the design and development of the SSME.

  5. The design of flux-corrected transport (FCT) algorithms on structured grids

    NASA Astrophysics Data System (ADS)

    Zalesak, Steven T.

    2005-12-01

    A given flux-corrected transport (FCT) algorithm consists of three components: (1) a high order algorithm to which it reduces in smooth parts of the flow field; (2) a low order algorithm to which it reduces in parts of the flow devoid of smoothness; and (3) a flux limiter which calculates the weights assigned to the high and low order algorithms, in flux form, in the various regions of the flow field. In this dissertation, we describe a set of design principles that significantly enhance the accuracy and robustness of FCT algorithms by enhancing the accuracy and robustness of each of the three components individually. These principles include the use of very high order spatial operators in the design of the high order fluxes, the use of non-clipping flux limiters, the appropriate choice of constraint variables in the critical flux-limiting step, and the implementation of a "failsafe" flux-limiting strategy. We show via standard test problems the kind of algorithm performance one can expect if these design principles are adhered to. We give examples of applications of these design principles in several areas of physics. Finally, we compare the performance of these enhanced algorithms with that of other recent front-capturing methods.

  6. Testing of hardware implementation of infrared image enhancing algorithm

    NASA Astrophysics Data System (ADS)

    Dulski, R.; Sosnowski, T.; PiÄ tkowski, T.; Trzaskawka, P.; Kastek, M.; Kucharz, J.

    2012-10-01

    The interpretation of IR images depends on radiative properties of observed objects and surrounding scenery. Skills and experience of an observer itself are also of great importance. The solution to improve the effectiveness of observation is utilization of algorithm of image enhancing capable to improve the image quality and the same effectiveness of object detection. The paper presents results of testing the hardware implementation of IR image enhancing algorithm based on histogram processing. Main issue in hardware implementation of complex procedures for image enhancing algorithms is high computational cost. As a result implementation of complex algorithms using general purpose processors and software usually does not bring satisfactory results. Because of high efficiency requirements and the need of parallel operation, the ALTERA's EP2C35F672 FPGA device was used. It provides sufficient processing speed combined with relatively low power consumption. A digital image processing and control module was designed and constructed around two main integrated circuits: a FPGA device and a microcontroller. Programmable FPGA device performs image data processing operations which requires considerable computing power. It also generates the control signals for array readout, performs NUC correction and bad pixel mapping, generates the control signals for display module and finally executes complex image processing algorithms. Implemented adaptive algorithm is based on plateau histogram equalization. Tests were performed on real IR images of different types of objects registered in different spectral bands. The simulations and laboratory experiments proved the correct operation of the designed system in executing the sophisticated image enhancement.

  7. Development of robotics facility docking test hardware

    NASA Technical Reports Server (NTRS)

    Loughead, T. E.; Winkler, R. V.

    1984-01-01

    Design and fabricate test hardware for NASA's George C. Marshall Space Flight Center (MSFC) are reported. A docking device conceptually developed was fabricated, and two docking targets which provide high and low mass docking loads were required and were represented by an aft 61.0 cm section of a Hubble space telescope (ST) mockup and an upgrading of an existing multimission modular spacecraft (MSS) mockup respectively. A test plan is developed for testing the hardware.

  8. Removal of broken hardware.

    PubMed

    Hak, David J; McElvany, Matthew

    2008-02-01

    Despite advances in metallurgy, fatigue failure of hardware is common when a fracture fails to heal. Revision procedures can be difficult, usually requiring removal of intact or broken hardware. Several different methods may need to be attempted to successfully remove intact or broken hardware. Broken intramedullary nail cross-locking screws may be advanced out by impacting with a Steinmann pin. Broken open-section (Küntscher type) intramedullary nails may be removed using a hook. Closed-section cannulated intramedullary nails require additional techniques, such as the use of guidewires or commercially available extraction tools. Removal of broken solid nails requires use of a commercial ratchet grip extractor or a bone window to directly impact the broken segment. Screw extractors, trephines, and extraction bolts are useful for removing stripped or broken screws. Cold-welded screws and plates can complicate removal of locked implants and require the use of carbide drills or high-speed metal cutting tools. Hardware removal can be a time-consuming process, and no single technique is uniformly successful. PMID:18252842

  9. The Hardware Dilemma.

    ERIC Educational Resources Information Center

    ELECTRONIC Learning, 1983

    1983-01-01

    Profiles 24 microcomputers used by educators in elementary and secondary schools, presenting information from manufacturers (price, memory, languages, keyboard, screen display, graphics, sound, color, networking, compatible machine) and teacher commentary. Four micro-guides dealing with understanding specifications, finding hardware reviews,…

  10. Design and real time implementation of single phase boost power factor correction converter.

    PubMed

    Bouafassa, Amar; Rahmani, Lazhar; Mekhilef, Saad

    2015-03-01

    This paper presents a real time implementation of the single-phase power factor correction (PFC) AC-DC boost converter. A combination of higher order sliding mode controller based on super twisting algorithm and predictive control techniques are implemented to improve the performance of the boost converter. Due to the chattering effects, the higher order sliding mode control (HOSMC) is designed. Also, the predictive technique is modified taking into account the large computational delays. The robustness of the controller is verified conducting simulation in MATLAB, the results show good performances in both steady and transient states. An experiment is conducted through a test bench based on dSPACE 1104. The experimental results proved that the proposed controller enhanced the performance of the converter under different parameters variations. PMID:25457043