Science.gov

Sample records for gate oxide reliability

  1. A Unified Functional Reliability Model for N-channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub 2 nm Gate Oxide

    NASA Astrophysics Data System (ADS)

    Lee, Hai-Ming; Du, Long-Jye; Liang, Mong-Song; King, Ya-Ching; Hsu, Charles Ching-Hsiang

    2002-09-01

    Reliability tests of N-channel metal-oxide-semiconductor field-effect transistors (NMOSFET’s) with oxide thickness ranging from 3.3 nm to 1.7 nm are performed and analyzed in this work. New device failure mechanism due to gate-to-drain leakage path formation is observed, and it severely degrades the off-state performance of devices with sub 2 nm gate oxides. Among the device parameters monitored, on-state conduction current and off-state drain leakage are the two most decisive parameters which dominate NMOSFET’s functional reliability. A new unified functional reliability model is proposed, and lifetime predictions due to respective device parameters can be achieved.

  2. Degradation of Gate Oxide Reliability due to Plasma-Deposited Silicon Nitride

    NASA Astrophysics Data System (ADS)

    Ogino, Masaaki; Sugahara, Yoshiyuki; Kuribayashi, Hitoshi; Yamabe, Kikuo

    2004-03-01

    The effects of plasma-enhanced chemical vapor deposition (PE-CVD) silicon nitride (p-SiN) passivation films on time dependent dielectric breakdown (TDDB) of gate oxide were studied. It was found that degradation of TDDB characteristics with p-SiN films was suppressed by the change in p-SiN deposition conditions. The correlation between trapped electron density and TDDB characteristics varied, depending on the p-SiN films. The degradation of TDDB characteristics was also enhanced with phosphosilicate glass (PSG) under the p-SiN passivation film.

  3. Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET

    NASA Astrophysics Data System (ADS)

    Pradhan, K. P.; Sahu, P. K.; Singh, D.; Artola, L.; Mohapatra, S. K.

    2015-09-01

    A novel device named charge plasma based doping less double material gate oxide (DMGO) silicon-germanium on insulator (SGOI) double gate (DG) MOSFET is proposed for the first time. The fundamental objective in this work is to modify the channel potential, electric field and electron velocity for improving leakage current, transconductance (gm) and transconductance generation factor (TGF). Using 2-D simulation, we exhibit that the DMGO-SGOI MOSFET shows higher electron velocity at source side and lower electric field at drain side as compare to ultra-thin body (UTB) DG MOSFET. On the other hand DMGO-SGOI MOSFET demonstrates a significant improvement in gm and TGF in comparison to UTB-DG MOSFET. This work also evaluates the existence of a biasing point i.e. zero temperature coefficient (ZTC) bias point, where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performance metrics are also subjected to extensive analysis. This further validates the reliability of charge plasma DMGO SGOI MOSFET and its application opportunities involved in designing analog/RF circuits for a wide range of temperature applications.

  4. Improvement in reliability of amorphous indium-gallium-zinc oxide thin-film transistors with Teflon/SiO2 bilayer passivation under gate bias stress

    NASA Astrophysics Data System (ADS)

    Fan, Ching-Lin; Tseng, Fan-Ping; Li, Bo-Jyun; Lin, Yu-Zuo; Wang, Shea-Jue; Lee, Win-Der; Huang, Bohr-Ran

    2016-02-01

    The reliability of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with Teflon/SiO2 bilayer passivation prepared under positive and negative gate bias stresses (PGBS and NGBS, respectively) was investigated. Heavier electrical degradation was observed under PGBS than under NGBS, indicating that the environmental effects under PGBS are more evident than those under NGBS. The device with bilayer passivation under PGBS shows two-step degradation. The positive threshold voltage shifts during the initial stressing period (before 500 s), owing to the charges trapped in the gate insulator or at the gate insulator/a-IGZO active layer interface. The negative threshold voltage shift accompanies the increase in subthreshold swing (SS) for the continuous stressing period (after 500 s) owing to H2O molecules from ambience diffused within the a-IGZO TFTs. It is believed that Teflon/SiO2 bilayer passivation can effectively improve the reliability of the a-IGZO TFTs without passivation even though the devices are stressed under gate bias.

  5. Effects of N and F passivation on the reliability and interface structure of 700 °C grown ultrathin silicon oxide/Si(100) gate films

    NASA Astrophysics Data System (ADS)

    Yamada, Hiroshi

    2008-01-01

    Correlations between reliability and interfacial structure changes of ultrathin silicon oxide gate films grown at 700 °C with in situ pyrolytic-gas passivation (PGP) were investigated. PGP uses a little pyrolytic N2O and NF3 during ultradry oxidation with pure O2 at less than 1 ppb humidity and has a potential for application to future low-temperature device fabrication processes due to the reliability retention of the films. It was found that the reliability for the 700 °C grown PGP films is much like that of the 800-900 °C grown ones, with an interface state density of less than 1-3×1010/eV cm2 maintained. Quantitative analyses of N, F, and O indicated that this is probably due to microscopic, interfacial structure changes, that is, N and F passivation effectively contributes to compensate inconsistent-state bonding sites and to generate a high-density structure with few dangling bonds.

  6. Reliability assessment of germanium gate stacks with promising initial characteristics

    NASA Astrophysics Data System (ADS)

    Lu, Cimang; Lee, Choong Hyun; Nishimura, Tomonori; Nagashio, Kosuke; Toriumi, Akira

    2015-02-01

    This work reports on the reliability assessment of germanium (Ge) gate stacks with promising initial electrical properties, with focus on trap generation under a constant electric stress field (Estress). Initial Ge gate stack properties do not necessarily mean highly robust reliability when it is considered that traps are newly generated under high Estress. A small amount of yttrium- or scandium oxide-doped GeO2 (Y-GeO2 or Sc-GeO2, respectively) significantly reduces trap generation in Ge gate stacks without deterioration of the interface. This is explained by the increase in the average coordination number (Nav) of the modified GeO2 network that results from the doping.

  7. Reliability study of refractory gate gallium arsenide MESFETS

    NASA Technical Reports Server (NTRS)

    Yin, J. C. W.; Portnoy, W. M.

    1981-01-01

    Refractory gate MESFET's were fabricated as an alternative to aluminum gate devices, which have been found to be unreliable as RF power amplifiers. In order to determine the reliability of the new structures, statistics of failure and information about mechanisms of failure in refractory gate MESFET's are given. Test transistors were stressed under conditions of high temperature and forward gate current to enhance failure. Results of work at 150 C and 275 C are reported.

  8. Single event gate rupture in thin gate oxides

    SciTech Connect

    Sexton, F.W.; Fleetwood, D.M.; Shaneyfelt, M.R.; Dodd, P.E.; Hash, G.L.

    1997-06-01

    As integrated circuit densities increase with each new technology generation, both the lateral and vertical dimensions shrink. Operating voltages, however, have not scaled as aggressively as feature size, with a resultant increase in the electric fields within advanced geometry devices. Oxide electric fields are in fact increasing to greater than 5 MV/cm as feature size approaches 0.1 {micro}m. This trend raises the concern that single event gate rupture (SEGR) may limit the scaling of advanced integrated circuits (ICs) for space applications. The dependence of single event gate rupture (SEGR) critical field on oxide thickness is examined for thin gate oxides. Critical field for SEGR increases with decreasing oxide thickness, consistent with an increasing intrinsic breakdown field.

  9. Crystalline ZrTiO{sub 4} gated p-metal–oxide–semiconductor field effect transistors with sub-nm equivalent oxide thickness featuring good electrical characteristics and reliability

    SciTech Connect

    Wu, Chao-Yi; Hsieh, Ching-Heng; Lee, Ching-Wei; Wu, Yung-Hsien

    2015-02-02

    ZrTiO{sub 4} crystallized in orthorhombic (o-) phase was stacked with an amorphous Yb{sub 2}O{sub 3} interfacial layer as the gate dielectric for Si-based p-MOSFETs. With thermal annealing after gate electrode, the gate stack with equivalent oxide thickness (EOT) of 0.82 nm achieves high dielectric quality by showing a low interface trap density (D{sub it}) of 2.75 × 10{sup 11 }cm{sup −2}eV{sup −1} near the midgap and low oxide traps. Crystallization of ZrTiO{sub 4} and post metal annealing are also proven to introduce very limited amount of metal induced gap states or interfacial dipole. The p-MOSFETs exhibit good sub-threshold swing of 75 mV/dec which is ascribed to the low D{sub it} value and small EOT. Owing to the Y{sub 2}O{sub 3} interfacial layer and smooth interface with Si substrate that, respectively, suppress phonon and surface roughness scattering, the p-MOSFETs also display high hole mobility of 49 cm{sup 2}/V-s at 1 MV/cm. In addition, I{sub on}/I{sub off} ratio larger than 10{sup 6} is also observed. From the reliability evaluation by negative bias temperature instability test, after stressing with an electric field of −10 MV/cm at 85 °C for 1000 s, satisfactory threshold voltage shift of 12 mV and sub-threshold swing degradation of 3% were obtained. With these promising characteristics, the Yb{sub 2}O{sub 3}/o-ZrTiO{sub 4} gate stack holds the great potential for next-generation electronics.

  10. Improved linearity and reliability in GaN metal-oxide-semiconductor high-electron-mobility transistors using nanolaminate La2O3/SiO2 gate dielectric

    NASA Astrophysics Data System (ADS)

    Hsu, Ching-Hsiang; Shih, Wang-Cheng; Lin, Yueh-Chin; Hsu, Heng-Tung; Hsu, Hisang-Hua; Huang, Yu-Xiang; Lin, Tai-Wei; Wu, Chia-Hsun; Wu, Wen-Hao; Maa, Jer-Shen; Iwai, Hiroshi; Kakushima, Kuniyuki; Chang, Edward Yi

    2016-04-01

    Improved device performance to enable high-linearity power applications has been discussed in this study. We have compared the La2O3/SiO2 AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with other La2O3-based (La2O3/HfO2, La2O3/CeO2 and single La2O3) MOS-HEMTs. It was found that forming lanthanum silicate films can not only improve the dielectric quality but also can improve the device characteristics. The improved gate insulation, reliability, and linearity of the 8 nm La2O3/SiO2 MOS-HEMT were demonstrated.

  11. Performance and reliability improvement of HfSiON gate dielectrics using chlorine plasma treatment

    SciTech Connect

    Park, Hong Bae; Ju, Byongsun; Kang, Chang Yong; Park, Chanro; Park, Chang Seo; Lee, Byoung Hun; Kim, Tea Wan; Kim, Beom Seok; Choi, Rino

    2009-01-26

    The effects of chlorine plasma treatment on HfSiON gate dielectrics were investigated with respect to device performance and reliability characteristics. The chlorine plasma treatment was performed on atomic layer deposited HfSiON films to remove the residual carbon content. The optimal chlorine plasma treatment is shown to lower gate leakage current density without increasing equivalent oxide thickness of the gate stack. Secondary ion mass spectroscopy depth profiling showed that the carbon residue in HfSiON was reduced by the chlorine plasma treatment. It is demonstrated that an optimized chlorine plasma treatment improves the transistor I{sub on}-I{sub off} characteristics and reduces negative-bias temperature instability.

  12. Deuterium-incorporated gate oxide of MOS devices fabricated by using deuterium ion implantation

    NASA Astrophysics Data System (ADS)

    Lee, Jae-Sung; Lear, Kevin L.

    2012-04-01

    In the aspect of metal-oxide-semiconductor (MOS) device reliability, deuterium-incorporated gate oxide could be utilized to suppress the wear-out that is combined with oxide trap generation. An alternative deuterium process for the passivation of oxide traps or defects in the gate oxide of MOS devices has been suggested in this study. The deuterium ion is delivered to the location where the gate oxide resides by using an implantation process and subsequent N2 annealing process at the back-end of metallization process. A conventional MOS field-effect transistor (MOSFET) with a 3-nm-thick gate oxide and poly-to-ploy capacitor sandwiched with 20-nm-thick SiO2 were fabricated in order to demonstrate the deuterium effect in our process. An optimum condition of ion implantation was necessary to account for the topography of the overlaying layers in the device structure and to minimize the physical damage due to the energy of the implanted ion. Device parameter variations, the gate leakage current, and the dielectric breakdown phenomenon were investigated in the deuterium-ion-implanted devices. We found the isotope effect between hydrogen- and deuterium-implanted devices and an improved electrical reliability in the deuterated gate oxide. This implies that deuterium bonds are generated effectively at the Si/SiO2 interface and in the SiO2 bulk.

  13. Process Design for Preventing the Gate Oxide Thinning in the Integration of Dual Gate Oxide Transistor

    NASA Astrophysics Data System (ADS)

    Kim, Seong-Ho; Kim, Sung-Hoan; Kim, Sung-Eun; Kim, Myung-Soo; Park, Joo-Han; Kim, Eun-Soo; Kim, Jin-Tae

    2002-04-01

    In this study, a method is proposed to alleviate a gate oxide (GOX) thinning problem at the edge of shallow trench isolation (STI), when STI is adopted in the dual gate oxide process (DGOX). It is well known that the DGOX process is usually used for realizing both low and high voltage operating parts in one chip. However, it is found that severe GOX thinning occurs from 320 Å (in active area) to 79 Å (at STI top edge) and a dent profile exists at the top edge of STI, when conventional DGOX and STI processes are adopted. In order to solve these problems, a new DGOX process is used in this study. The GOX thinning is prevented mainly by a combination of a thick sidewall oxide with SiN pullback. Therefore, good subthreshold characteristics without a so-called double hump are obtained by the prevention of GOX thinning and a deep dent profile.

  14. Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement

    NASA Astrophysics Data System (ADS)

    Raad, Bhagwan Ram; Nigam, Kaushal; Sharma, Dheeraj; Kondekar, P. N.

    2016-06-01

    This script features a study of bandgap, gate material work function and gate dielectric engineering for enhancement of DC and Analog/RF performance, reduction in the hot carriers effect (HCEs) and drain induced barrier lowering (DIBL) for better device reliability. In this concern, the use of band gap and gate material work function engineering improves the device performance in terms of the ON-state current and suppressed ambipolar behaviour with maintaining the low OFF-state current. With these advantages, the use of gate material work function engineering imposes restriction on the high frequency performance due to increment in the parasitic capacitances and also introduces the hot carrier effects. Hence, the gate dielectric engineering with bandgap and gate material work function engineering are used in this paper to overcome the cons of the gate material work function engineering by obtaining a superior performance in terms of the current driving capability, ambipolar conduction, HCEs, DIBL and high frequency parameters of the device for ultra-low power applications. Finally, the optimization of length for different work function is performed to get the best out of this.

  15. Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

    PubMed

    Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

    2016-08-24

    Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing. PMID:27471861

  16. Mechanisms of heavy-ion induced gate rupture in thin oxides

    SciTech Connect

    Sexton, F.W.; Fleetwood, D.M.; Krisch, K.S.

    1998-08-01

    Single event gate rupture (SEGR) is a catastrophic failure mode that occurs in dielectric materials that are struck by energetic heavy ions while biased under a high electric field condition. SEGR can reduce the critical electric field to breakdown to less than half the value observed in normal voltage ramp reliability tests. As electric fields in gate oxides increase to greater than 5 MV/cm in advanced MOS technologies, the impact of SEGR on the reliability of space based electronics must be assessed. In this summary, the authors explore the nature of SEGR in oxides with thickness from 7 nm to less than 5 nm, where soft breakdown is often observed during traditional reliability tests. They discuss the possible connection between the present understanding of SEGR and voltage stress breakdown models.

  17. Effect of gate oxide thickness on the radiation hardness of silicon-gate CMOS

    SciTech Connect

    Nordstrom, T.V.; Gibbon, C.F.

    1981-01-01

    Significant improvements have been made in the radiation hardness of silicon-gate CMOS by reducing the gate oxide thickness. The device studied is an 8-bit arithmetic logic unit designed with Sandia's Expanded Linear Array (ELA) standard cells. Devices with gate oxide thicknesses of 400, 570 (standard), and 700 A were fabricated. Irradiations were done at a dose rate of 2 x 10/sup 6/ rads (Si) per hour. N- and P-channel maximum threshold shifts were reduced by 0.3 and 1.2 volts, respectively, for the thinnest oxide. Approximately, a linear relationship is found for threshold shift versus thickness. The functional radiation hardness of the full integrated circuit was also measured.

  18. Oxidative Modulation of Voltage-Gated Potassium Channels

    PubMed Central

    Sahoo, Nirakar; Hoshi, Toshinori

    2014-01-01

    Abstract Significance: Voltage-gated K+ channels are a large family of K+-selective ion channel protein complexes that open on membrane depolarization. These K+ channels are expressed in diverse tissues and their function is vital for numerous physiological processes, in particular of neurons and muscle cells. Potentially reversible oxidative regulation of voltage-gated K+ channels by reactive species such as reactive oxygen species (ROS) represents a contributing mechanism of normal cellular plasticity and may play important roles in diverse pathologies including neurodegenerative diseases. Recent Advances: Studies using various protocols of oxidative modification, site-directed mutagenesis, and structural and kinetic modeling provide a broader phenomenology and emerging mechanistic insights. Critical Issues: Physicochemical mechanisms of the functional consequences of oxidative modifications of voltage-gated K+ channels are only beginning to be revealed. In vivo documentation of oxidative modifications of specific amino-acid residues of various voltage-gated K+ channel proteins, including the target specificity issue, is largely absent. Future Directions: High-resolution chemical and proteomic analysis of ion channel proteins with respect to oxidative modification combined with ongoing studies on channel structure and function will provide a better understanding of how the function of voltage-gated K+ channels is tuned by ROS and the corresponding reducing enzymes to meet cellular needs. Antioxid. Redox Signal. 21, 933–952. PMID:24040918

  19. AlN and Al oxy-nitride gate dielectrics for reliable gate stacks on Ge and InGaAs channels

    NASA Astrophysics Data System (ADS)

    Guo, Y.; Li, H.; Robertson, J.

    2016-05-01

    AlN and Al oxy-nitride dielectric layers are proposed instead of Al2O3 as a component of the gate dielectric stacks on higher mobility channels in metal oxide field effect transistors to improve their positive bias stress instability reliability. It is calculated that the gap states of nitrogen vacancies in AlN lie further away in energy from the semiconductor band gap than those of oxygen vacancies in Al2O3, and thus AlN might be less susceptible to charge trapping and have a better reliability performance. The unfavourable defect energy level distribution in amorphous Al2O3 is attributed to its larger coordination disorder compared to the more symmetrically bonded AlN. Al oxy-nitride is also predicted to have less tendency for charge trapping.

  20. The understanding on the evolution of stress-induced gate leakage in high-k dielectric metal-oxide-field-effect transistor by random-telegraph-noise measurement

    NASA Astrophysics Data System (ADS)

    Hsieh, E. R.; Chung, Steve S.

    2015-12-01

    The evolution of gate-current leakage path has been observed and depicted by RTN signals on metal-oxide-silicon field effect transistor with high-k gate dielectric. An experimental method based on gate-current random telegraph noise (Ig-RTN) technique was developed to observe the formation of gate-leakage path for the device under certain electrical stress, such as Bias Temperature Instability. The results show that the evolution of gate-current path consists of three stages. In the beginning, only direct-tunnelling gate current and discrete traps inducing Ig-RTN are observed; in the middle stage, interaction between traps and the percolation paths presents a multi-level gate-current variation, and finally two different patterns of the hard or soft breakdown path can be identified. These observations provide us a better understanding of the gate-leakage and its impact on the device reliability.

  1. High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

    PubMed Central

    Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

    2015-01-01

    The use of indium–gallium–zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic–inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic–inorganic hybrid devices. PMID:26677773

  2. High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric.

    PubMed

    Fujii, Mami N; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

    2015-01-01

    The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices. PMID:26677773

  3. High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

    NASA Astrophysics Data System (ADS)

    Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

    2015-12-01

    The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

  4. High-κ oxide nanoribbons as gate dielectrics for high mobility top-gated graphene transistors

    PubMed Central

    Liao, Lei; Bai, Jingwei; Qu, Yongquan; Lin, Yung-chen; Li, Yujing; Huang, Yu; Duan, Xiangfeng

    2010-01-01

    Deposition of high-κ dielectrics onto graphene is of significant challenge due to the difficulties of nucleating high quality oxide on pristine graphene without introducing defects into the monolayer of carbon lattice. Previous efforts to deposit high-κ dielectrics on graphene often resulted in significant degradation in carrier mobility. Here we report an entirely new strategy to integrate high quality high-κ dielectrics with graphene by first synthesizing freestanding high-κ oxide nanoribbons at high temperature and then transferring them onto graphene at room temperature. We show that single crystalline Al2O3 nanoribbons can be synthesized with excellent dielectric properties. Using such nanoribbons as the gate dielectrics, we have demonstrated top-gated graphene transistors with the highest carrier mobility (up to 23,600 cm2/V·s) reported to date, and a more than 10-fold increase in transconductance compared to the back-gated devices. This method opens a new avenue to integrate high-κ dielectrics on graphene with the preservation of the pristine nature of graphene and high carrier mobility, representing an important step forward to high-performance graphene electronics. PMID:20308584

  5. Chemical gating of epitaxial graphene through ultrathin oxide layers

    NASA Astrophysics Data System (ADS)

    Larciprete, Rosanna; Lacovig, Paolo; Orlando, Fabrizio; Dalmiglio, Matteo; Omiciuolo, Luca; Baraldi, Alessandro; Lizzit, Silvano

    2015-07-01

    We achieved a controllable chemical gating of epitaxial graphene grown on metal substrates by exploiting the electrostatic polarization of ultrathin SiO2 layers synthesized below it. Intercalated oxygen diffusing through the SiO2 layer modifies the metal-oxide work function and hole dopes graphene. The graphene/oxide/metal heterostructure behaves as a gated plane capacitor with the in situ grown SiO2 layer acting as a homogeneous dielectric spacer, whose high capacity allows the Fermi level of graphene to be shifted by a few hundreds of meV when the oxygen coverage at the metal substrate is of the order of 0.5 monolayers. The hole doping can be finely tuned by controlling the amount of interfacial oxygen, as well as by adjusting the thickness of the oxide layer. After complete thermal desorption of oxygen the intrinsic doping of SiO2 supported graphene is evaluated in the absence of contaminants and adventitious adsorbates. The demonstration that the charge state of graphene can be changed by chemically modifying the buried oxide/metal interface hints at the possibility of tuning the level and sign of doping by the use of other intercalants capable of diffusing through the ultrathin porous dielectric and reach the interface with the metal.We achieved a controllable chemical gating of epitaxial graphene grown on metal substrates by exploiting the electrostatic polarization of ultrathin SiO2 layers synthesized below it. Intercalated oxygen diffusing through the SiO2 layer modifies the metal-oxide work function and hole dopes graphene. The graphene/oxide/metal heterostructure behaves as a gated plane capacitor with the in situ grown SiO2 layer acting as a homogeneous dielectric spacer, whose high capacity allows the Fermi level of graphene to be shifted by a few hundreds of meV when the oxygen coverage at the metal substrate is of the order of 0.5 monolayers. The hole doping can be finely tuned by controlling the amount of interfacial oxygen, as well as by adjusting

  6. Chemical gating of epitaxial graphene through ultrathin oxide layers.

    PubMed

    Larciprete, Rosanna; Lacovig, Paolo; Orlando, Fabrizio; Dalmiglio, Matteo; Omiciuolo, Luca; Baraldi, Alessandro; Lizzit, Silvano

    2015-08-01

    We achieved a controllable chemical gating of epitaxial graphene grown on metal substrates by exploiting the electrostatic polarization of ultrathin SiO2 layers synthesized below it. Intercalated oxygen diffusing through the SiO2 layer modifies the metal-oxide work function and hole dopes graphene. The graphene/oxide/metal heterostructure behaves as a gated plane capacitor with the in situ grown SiO2 layer acting as a homogeneous dielectric spacer, whose high capacity allows the Fermi level of graphene to be shifted by a few hundreds of meV when the oxygen coverage at the metal substrate is of the order of 0.5 monolayers. The hole doping can be finely tuned by controlling the amount of interfacial oxygen, as well as by adjusting the thickness of the oxide layer. After complete thermal desorption of oxygen the intrinsic doping of SiO2 supported graphene is evaluated in the absence of contaminants and adventitious adsorbates. The demonstration that the charge state of graphene can be changed by chemically modifying the buried oxide/metal interface hints at the possibility of tuning the level and sign of doping by the use of other intercalants capable of diffusing through the ultrathin porous dielectric and reach the interface with the metal. PMID:26148485

  7. Polysilicon Gate Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations in Sub-100 nm MOSFET's with Ultrathin Gate Oxide

    NASA Technical Reports Server (NTRS)

    Asenov, Asen; Saini, Subhash

    2000-01-01

    In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFET's with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3-D) "atomistic" simulation technique described else-where. MOSFET's with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled-in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide-thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect or the polysilicon grain boundaries on the threshold voltage variation are also presented.

  8. Enhanced Breakdown Reliability and Spatial Uniformity of Atomic Layer Deposited High-k Gate Dielectrics on Graphene via Organic Seeding Layers

    NASA Astrophysics Data System (ADS)

    Sangwan, Vinod; Jariwala, Deep; Filippone, Stephen; Karmel, Hunter; Johns, James; Alaboson, Justice; Marks, Tobin; Lauhon, Lincoln; Hersam, Mark

    2013-03-01

    Ultra-thin high- κ top-gate dielectrics are essential for high-speed graphene-based nanoelectronic circuits. Motivated by the need for high reliability and spatial uniformity, we report here the first statistical analysis of the breakdown characteristics of dielectrics grown on graphene. Based on these measurements, a rational approach is devised that simultaneously optimizes the gate capacitance and the key parameters of large-area uniformity and dielectric strength. In particular, vertically heterogeneous oxide stacks grown via atomic-layer deposition (ALD) seeded by a molecularly thin perylene-3,4,9,10-tetracarboxylic dianhydride (PTCDA) organic monolayer result in improved reliability (Weibull shape parameter β > 25) compared to the control dielectric directly grown on graphene without PTCDA (β < 1). The optimized sample also showed a large breakdown strength (Weibull scale parameter, EBD > 7 MV/cm) that is comparable to that of the control dielectric grown on Si substrates.

  9. Precursor ion damage and single event gate rupture in thin oxides

    SciTech Connect

    Sexton, F.W.; Fleetwood, D.M.; Shaneyfelt, M.R.; Dodd, P.E.; Hash, G.L.; Schanwald, L.P.; Krisch, K.S.

    1998-02-01

    Gate oxide electric fields are expected to increase to greater than 5 MV/cm as feature size approaches 0.1 micrometers in advanced integrated circuit (IC) technologies. Work by Johnston, et al. raised the concern that single event gate rupture (SEGR) may limit the scaling of advanced ICs for space applications. SEGR has also been observed in field programmable gate arrays, which rely on thin dielectrics for electrical programming at very high electric fields. The focus of this effort is to further explore the mechanisms for SEGR in thin gate oxides. The authors examine the characteristics of heavy ion induced breakdown and compare them to ion induced damage in thin gate oxides. Further, the authors study the impact of precursor damage in oxides on SEGR threshold. Finally, they compare thermal and nitrided oxides to see if SEGR is improved by incorporating nitrogen in the oxide.

  10. Surface photovoltage analysis of iron contamination in silicon processing and the relation to gate oxide integrity

    NASA Astrophysics Data System (ADS)

    Henley, Worth B.

    1995-09-01

    Surface photovoltage (SPV), a contactless optical technique for measuring minority carrier lifetime, is used to quantify the relationship between silicon iron contamination level and thin gate oxide integrity. Iron concentration levels in the range of 1 X 1010 cm-3 to 5 X 1013 cm-3 are evaluated for oxide thicknesses of 8 to 20 nm. Ramp voltage electrical breakdown and time dependant dielectric breakdown measurement on the iron contaminated gate oxide capacitors are reported. Distinct iron contamination threshold limits based on defect density and gate oxide integrity evaluate cleaning efficiencies and metallic cross contamination effects during thermal processing contamination. Iron-silicide precipitation kinetics are investigated by the lifetime analysis procedure.

  11. Vox/Eox-Driven Breakdown of Ultrathin SiON Gate Dielectrics in p-Type Metal Oxide Semiconductor Field Effect Transistors under Low-Voltage Inversion Stress

    NASA Astrophysics Data System (ADS)

    Tsujikawa, Shimpei; Shiga, Katsuya; Umeda, Hiroshi; Yugami, Jiro

    2007-01-01

    The breakdown mechanism of ultrathin SiON gate dielectrics in p-type metal oxide semiconductor field effect transistors having p+gates (p+gate-pMOSFETs) has been studied. Systematic study with varying gate doping concentrations has revealed that, in the case of p+gate-pMOSFET in inversion mode, gate dielectric breakdown under stress voltage lower than -4 V is driven by oxide voltage (Vox) or oxide field (Eox), while the breakdown under stress voltage higher than -4 V is driven by gate voltage (Vg). The Vox/Eox-driven breakdown observed under low stress voltage is quite important to the reliability of low-voltage complementary metal oxide semiconductor (CMOS). By studying the mechanism of the breakdown, it has been clarified that the breakdown is not induced by electron current. The concept that the breakdown is due to same mechanism as the negative bias temperature instability (NBTI), namely the interfacial hydrogen release driven by Eox, has been shown to be possible. However, direct tunneling of holes driven by Vox has also been found to be a possible driving force of the breakdown. Although a decisive conclusion concerning the mechanism issue has not yet been obtained, the key factor that governs the breakdown has been shown to be Vox or Eox.

  12. Room-temperature phosphorescence logic gates developed from nucleic acid functionalized carbon dots and graphene oxide.

    PubMed

    Gui, Rijun; Jin, Hui; Wang, Zonghua; Zhang, Feifei; Xia, Jianfei; Yang, Min; Bi, Sai; Xia, Yanzhi

    2015-05-14

    Room-temperature phosphorescence (RTP) logic gates were developed using capture ssDNA (cDNA) modified carbon dots and graphene oxide (GO). The experimental results suggested the feasibility of these developed RTP-based "OR", "INHIBIT" and "OR-INHIBIT" logic gate operations, using Hg(2+), target ssDNA (tDNA) and doxorubicin (DOX) as inputs. PMID:25882250

  13. Mesostructured HfxAlyO2 Thin Films as Reliable and Robust Gate Dielectrics with Tunable Dielectric Constants for High-Performance Graphene-Based Transistors.

    PubMed

    Lee, Yunseong; Jeon, Woojin; Cho, Yeonchoo; Lee, Min-Hyun; Jeong, Seong-Jun; Park, Jongsun; Park, Seongjun

    2016-07-26

    We introduce a reliable and robust gate dielectric material with tunable dielectric constants based on a mesostructured HfxAlyO2 film. The ultrathin mesostructured HfxAlyO2 film is deposited on graphene via a physisorbed-precursor-assisted atomic layer deposition process and consists of an intermediate state with small crystallized parts in an amorphous matrix. Crystal phase engineering using Al dopant is employed to achieve HfO2 phase transitions, which produce the crystallized part of the mesostructured HfxAlyO2 film. The effects of various Al doping concentrations are examined, and an enhanced dielectric constant of ∼25 is obtained. Further, the leakage current is suppressed (∼10(-8) A/cm(2)) and the dielectric breakdown properties are enhanced (breakdown field: ∼7 MV/cm) by the partially remaining amorphous matrix. We believe that this contribution is theoretically and practically relevant because excellent gate dielectric performance is obtained. In addition, an array of top-gated metal-insulator-graphene field-effect transistors is fabricated on a 6 in. wafer, yielding a capacitance equivalent oxide thickness of less than 1 nm (0.78 nm). This low capacitance equivalent oxide thickness has important implications for the incorporation of graphene into high-performance silicon-based nanoelectronics. PMID:27355098

  14. Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

    NASA Astrophysics Data System (ADS)

    Kim, Young-Hee

    Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is

  15. Automated Coronary Artery Calcification Scoring in Non-Gated Chest CT: Agreement and Reliability

    PubMed Central

    Takx, Richard A. P.; de Jong, Pim A.; Leiner, Tim; Oudkerk, Matthijs; de Koning, Harry J.; Mol, Christian P.; Viergever, Max A.; Išgum, Ivana

    2014-01-01

    Objective To determine the agreement and reliability of fully automated coronary artery calcium (CAC) scoring in a lung cancer screening population. Materials and Methods 1793 low-dose chest CT scans were analyzed (non-contrast-enhanced, non-gated). To establish the reference standard for CAC, first automated calcium scoring was performed using a preliminary version of a method employing coronary calcium atlas and machine learning approach. Thereafter, each scan was inspected by one of four trained raters. When needed, the raters corrected initially automaticity-identified results. In addition, an independent observer subsequently inspected manually corrected results and discarded scans with gross segmentation errors. Subsequently, fully automatic coronary calcium scoring was performed. Agatston score, CAC volume and number of calcifications were computed. Agreement was determined by calculating proportion of agreement and examining Bland-Altman plots. Reliability was determined by calculating linearly weighted kappa (κ) for Agatston strata and intraclass correlation coefficient (ICC) for continuous values. Results 44 (2.5%) scans were excluded due to metal artifacts or gross segmentation errors. In the remaining 1749 scans, median Agatston score was 39.6 (P25–P75∶0–345.9), median volume score was 60.4 mm3 (P25–P75∶0–361.4) and median number of calcifications was 2 (P25–P75∶0–4) for the automated scores. The κ demonstrated very good reliability (0.85) for Agatston risk categories between the automated and reference scores. The Bland-Altman plots showed underestimation of calcium score values by automated quantification. Median difference was 2.5 (p25–p75∶0.0–53.2) for Agatston score, 7.6 (p25–p75∶0.0–94.4) for CAC volume and 1 (p25–p75∶0–5) for number of calcifications. The ICC was very good for Agatston score (0.90), very good for calcium volume (0.88) and good for number of calcifications (0.64). Discussion Fully automated

  16. Influence of the Polysilicon Gate on the Random Dopant Induced Threshold Voltage Fluctuations in Sub 100 nm MOSFETS with Thin Gate Oxides

    NASA Technical Reports Server (NTRS)

    Asenov, Asen; Saini, S.

    2000-01-01

    In this paper for the first time we study the influence of the polysilicon gate on the random dopant induced threshold voltage fluctuations in sub 100 nm MOSFETs with tunnelling gate oxides. This is done by using an efficient 3D 'atomistic' simulation technique described elsewhere. Devices with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveale that the polysilicon gate is responsible for a substantial fraction of the threshold voltage fluctuations in both devices when the gate oxide is scaled to tunnelling thickness in the range of 1 - 2 nm.

  17. Reliability tests of gated silicon field emitters for use in space

    NASA Astrophysics Data System (ADS)

    Aplin, K. L.; Collingwood, C. M.; Kent, B. J.

    2004-07-01

    Neutralizers are required to prevent spacecraft charging from satellite ion propulsion. This paper discusses the development of a gated silicon tip field emitter (FE) neutralizer, specified to deliver 6 mA, with each tip emitting a mean current of 7 nA. It is important to investigate factors affecting the lifetime of field emitter arrays for a space application, as longevity and reliability are both critical requirements. Semi-automated procedures to prepare 400 arrays, each consisting of 765 FEs, for life tests are described with failure conditions strictly defined by mission constraints. Results of 25 life tests on 72 arrays driven to failure at constant emission current are summarized, and a case study of one test is presented. Two of the three failure mechanisms identified are consistent with thermal failure and damage by ion bombardment. Reduced field enhancement from tip erosion caused by ion bombardment is a common explanation for FE failure. However, scanning electron microscope examination of tip apex diameters showed no significant relationship between array failure and apex geometry. The third failure mechanism was associated with short-lived arrays and may be caused by manufacturing defects. Substantial intrinsic variability was observed in the arrays tested, even with the rigorous production standards required for space applications. Arrays without manufacturing defects had lifetimes of thousands of hours.

  18. A Low-Leakage Epitaxial High-κ Gate Oxide for Germanium Metal-Oxide-Semiconductor Devices.

    PubMed

    Hu, Chengqing; McDaniel, Martin D; Jiang, Aiting; Posadas, Agham; Demkov, Alexander A; Ekerdt, John G; Yu, Edward T

    2016-03-01

    Germanium (Ge)-based metal-oxide-semiconductor field-effect transistors are a promising candidate for high performance, low power electronics at the 7 nm technology node and beyond. However, the availability of high quality gate oxide/Ge interfaces that provide low leakage current density and equivalent oxide thickness (EOT), robust scalability, and acceptable interface state density (Dit) has emerged as one of the most challenging hurdles in the development of such devices. Here we demonstrate and present detailed electrical characterization of a high-κ epitaxial oxide gate stack based on crystalline SrHfO3 grown on Ge (001) by atomic layer deposition. Metal-oxide-Ge capacitor structures show extremely low gate leakage, small and scalable EOT, and good and reducible Dit. Detailed growth strategies and postgrowth annealing schemes are demonstrated to reduce Dit. The physical mechanisms behind these phenomena are studied and suggest approaches for further reduction of Dit. PMID:26859048

  19. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

    DOE PAGESBeta

    Leng, X.; Bozovic, I.; Bollinger, A. T.

    2016-08-10

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a puremore » electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.« less

  20. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

    NASA Astrophysics Data System (ADS)

    Leng, X.; Bollinger, A. T.; Božović, I.

    2016-08-01

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.

  1. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

    PubMed Central

    Leng, X.; Bollinger, A. T.; Božović, I.

    2016-01-01

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices. PMID:27506371

  2. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films.

    PubMed

    Leng, X; Bollinger, A T; Božović, I

    2016-01-01

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices. PMID:27506371

  3. Gate stack dielectric degradation of rare-earth oxides grown on high mobility Ge substrates

    NASA Astrophysics Data System (ADS)

    Shahinur Rahman, Md.; Evangelou, E. K.; Konofaos, N.; Dimoulas, A.

    2012-11-01

    We report on the reliability characteristics and their analysis, of rare-earth oxides (REOs) dielectric degradation, when used as interfacial buffer layers together with HfO2 high-k films (REOs/HfO2) on high mobility Ge substrates. Metal-oxide-semiconductor (MOS) devices with these stacks, show dissimilar charge trapping phenomena under varying levels of constant-voltage-stress (CVS) conditions, influencing the measured densities of the interface (Nit) and border (NBT) traps. In the present study, we report on C-Vg hysteresis curves related to both Nit and NBT. We propose a new model based on the Maxwell-Wagner mechanism, and this model explains the current decay transient observed under CVS bias from low to higher fields of MOS gate stack devices grown on Ge substrates. The proposed model is unlike to those used for other MOS devices. Finally, CVS measurements for very long times at moderate fields reveal an initial current decay due to relaxation, followed by charge trapping and generation of stress-induced leakage which eventually lead to hard breakdown.

  4. Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET

    NASA Astrophysics Data System (ADS)

    Pradhan, K. P.; Priyanka; Sahu, P. K.

    2016-01-01

    Symmetric Dual-k Spacer (SDS) Trigate Wavy FinFET is a novel hybrid device that combines three significant and advanced technologies i.e., ultra-thin-body (UTB), FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. This innovative architecture promises to enhance the device performance as compared to conventional FinFET without increasing the chip area. For the first time, we have incorporated two different dielectric materials (SiO2, and HfO2) as gate oxide to analyze the effect on various performance metrics of SDS wavy FinFET. This work evaluates the response of double material gate oxide (DMGO) on parameters like mobility, on current (Ion), transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) in SDS wavy FinFET. This work also reveals the presence of biasing point i.e., zero temperature coefficient (ZTC) bias point. The ZTC bias point is that point where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performances are also subjected to extensive analysis. This further validates the reliability of DMGO-SDS FinFET and its application opportunities involved in modeling analog/RF circuits for a broad range of temperature applications. From extensive 3-D device simulation, we have determined that the inclusion of DMGO in SDS wavy FinFET is superior in performance.

  5. Transient characteristics for proton gating in laterally coupled indium-zinc-oxide transistors.

    PubMed

    Liu, Ning; Zhu, Li Qiang; Xiao, Hui; Wan, Chang Jin; Liu, Yang Hui; Chao, Jin Yu

    2015-03-25

    The control and detection over processing, transport and delivery of chemical species is of great importance in sensors and biological systems. The transient characteristics of the migration of chemical species reflect the basic properties in the processings of chemical species. Here, we observed the field-configurable proton effects in a laterally coupled transistor gated by phosphorosilicate glass (PSG). The bias on the lateral gate would modulate the interplay between protons and electrons at the PSG/indium-zinc-oxide (IZO) channel interface. Due to the modulation of protons flux within the PSG films, the IZO channel current would be modified correspondingly. The characteristic time for the proton gating is estimated to be on the order of 20 ms. Such laterally coupled oxide based transistors with proton gating are promising for low-cost portable biosensors and neuromorphic system applications. PMID:25741771

  6. Room-temperature phosphorescence logic gates developed from nucleic acid functionalized carbon dots and graphene oxide

    NASA Astrophysics Data System (ADS)

    Gui, Rijun; Jin, Hui; Wang, Zonghua; Zhang, Feifei; Xia, Jianfei; Yang, Min; Bi, Sai; Xia, Yanzhi

    2015-04-01

    Room-temperature phosphorescence (RTP) logic gates were developed using capture ssDNA (cDNA) modified carbon dots and graphene oxide (GO). The experimental results suggested the feasibility of these developed RTP-based ``OR'', ``INHIBIT'' and ``OR-INHIBIT'' logic gate operations, using Hg2+, target ssDNA (tDNA) and doxorubicin (DOX) as inputs.Room-temperature phosphorescence (RTP) logic gates were developed using capture ssDNA (cDNA) modified carbon dots and graphene oxide (GO). The experimental results suggested the feasibility of these developed RTP-based ``OR'', ``INHIBIT'' and ``OR-INHIBIT'' logic gate operations, using Hg2+, target ssDNA (tDNA) and doxorubicin (DOX) as inputs. Electronic supplementary information (ESI) available: All experimental details, Part S1-3, Fig. S1-6 and Table S1. See DOI: 10.1039/c4nr07620f

  7. Investigation of metal oxide dielectrics for non-volatile floating gate and resistance switching memory applications

    NASA Astrophysics Data System (ADS)

    Chakrabarti, Bhaswar

    Floating gate transistor based flash memories have seen more than a decade of continuous growth as the prominent non-volatile memory technology. However, the recent trends indicate that the scaling of flash memory is expected to saturate in the near future. Several alternative technologies are being considered for the replacement of flash in the near future. The basic motivation for this work is to investigate the material properties of metal oxide based high-k dielectrics for potential applications in floating gate and resistance switching memory applications. This dissertation can be divided into two main sections. In the first section, the tunneling characteristics of the SiO2/HfO 2 stacks were investigated. Previous theoretical studies for thin SiO 2/ thick high-k stacks predict an increase in tunneling current in the high-bias regime (better programming) and a decrease in the low-bias regime (better retention) in comparison to pure SiO2 of same equivalent oxide thickness (EOT). However, our studies indicated that the performance improvement in SiO2/HfO2 stacks with thick HfO2 layer is difficult due to significant amount of charge traps in thick HfO2 layers. Oxygen anneal on the stacks did not improve the programming current and retention. X-ray photoelectron spectroscopy (XPS) studies indicated that this was due to formation of an interfacial oxide layer. The second part of the dissertation deals with the investigation of resistive switching in metal oxides. Although promising, practical applications of resistive random access memories (RRAM) require addressing several issues including high forming voltage, large operating currents and reliability. We first investigated resistive switching in HfTiOx nanolaminate with conventional TiN electrodes. The forming-free switching observed in the structures could be described by the quantum point contact model. The modelling results indicated that the forming-free characteristics can be due to a higher number of

  8. Analytical Model for Direct Tunneling Gate Current in Long-Channel Undoped Cylindrical Surrounding Gate Metal-Oxide-Semiconductor Field Effect Transistors

    NASA Astrophysics Data System (ADS)

    Han, Ru; Li, Cong

    2013-02-01

    In this study, an analytical direct tunneling gate current model for long-channel undoped cylindrical surrounding gate (CSG) MOSFETs is developed. On the basis of an analytical model, the direct tunneling gate current in CSG MOSFETs is investigated. It is found that direct tunneling gate current is a strong function of gate oxide thickness, but less affected by the change in channel radius. It is also revealed that considering the influence of the source and drain, as the length of the underlap region decreases to zero, the direct tunneling gate current drastically increases. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.

  9. Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

    NASA Astrophysics Data System (ADS)

    Chun, Minkyu; Um, Jae Gwang; Park, Min Sang; Chowdhury, Md Delwar Hossain; Jang, Jin

    2016-07-01

    We report the abnormal behavior of the threshold voltage (VTH) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (VTG), while bottom gate bias (VBG) is less effect than VTG. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of In metal diffusion to the top SiO2/a-IGZO and also the existence of large amount of In+ under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH- at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of VTG both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.

  10. Oxide thinning percolation statistical model for soft breakdown in ultrathin gate oxides

    NASA Astrophysics Data System (ADS)

    Chen, Ming-Jer; Kang, Ting-Kuo; Liu, Chuan-Hsi; Chang, Yih J.; Fu, Kuan-Yu

    2000-07-01

    An existing cell-based percolation model with parameter correlation can find its potential applications in assessing soft-breakdown (BD) statistics as long as the oxide thinning due to the localized physical damage near the SiO2/Si interface is accounted for. The resulting model is expressed explicitly with the critical trap number per cell nBD and the remaining oxide thickness tox' both as parameters. Reproduction of time-to-bimodal (soft- and hard-) breakdown statistical data from 3.3-nm-thick gate-oxide samples yields nBD of 3 and 4 for soft and hard breakdown, respectively. The extracted tox' of 1.0 nm for soft breakdown, plus the transition layer thickness of 0.5 nm in the model, is fairly comparable with literature values from current-voltage fitting. The dimension and area of the localized physically damaged region or percolation path (cell) are quantified as well. Based on the work, the origins of soft and hard breakdown are clarified in the following: (i) soft breakdown behaves intrinsically as hard breakdown, that is, they share the same defect (neutral trap) generation process and follow Poisson random statistics; (ii) both are independent events corresponding to different tox' requirements; and (iii) hard breakdown takes place in a certain path located differently from that for the first soft breakdown.

  11. Chemical Gated Field Effect Transistor by Hybrid Integration of One-Dimensional Silicon Nanowire and Two-Dimensional Tin Oxide Thin Film for Low Power Gas Sensor.

    PubMed

    Han, Jin-Woo; Rim, Taiuk; Baek, Chang-Ki; Meyyappan, M

    2015-09-30

    Gas sensors based on metal-oxide-semiconductor transistor with the polysilicon gate replaced by a gas sensitive thin film have been around for over 50 years. These are not suitable for the emerging mobile and wearable sensor platforms due to operating voltages and powers far exceeding the supply capability of batteries. Here we present a novel approach to decouple the chemically sensitive region from the conducting channel for reducing the drive voltage and increasing reliability. This chemically gated field effect transistor uses silicon nanowire for the current conduction channel with a tin oxide film on top of the nanowire serving as the gas sensitive medium. The potential change induced by the molecular adsorption and desorption allows the electrically floating tin oxide film to gate the silicon channel. As the device is designed to be normally off, the power is consumed only during the gas sensing event. This feature is attractive for the battery operated sensor and wearable electronics. In addition, the decoupling of the chemical reaction and the current conduction regions allows the gas sensitive material to be free from electrical stress, thus increasing reliability. The device shows excellent gas sensitivity to the tested analytes relative to conventional metal oxide transistors and resistive sensors. PMID:26381613

  12. Electrical control of Co/Ni magnetism adjacent to gate oxides with low oxygen ion mobility

    SciTech Connect

    Yan, Y. N.; Zhou, X. J.; Li, F.; Cui, B.; Wang, Y. Y.; Wang, G. Y.; Pan, F.; Song, C.

    2015-09-21

    We investigate the electrical manipulation of Co/Ni magnetization through a combination of ionic liquid and oxide gating, where HfO{sub 2} with a low O{sup 2−} ion mobility is employed. A limited oxidation-reduction process at the metal/HfO{sub 2} interface can be induced by large electric field, which can greatly affect the saturated magnetization and Curie temperature of Co/Ni bilayer. Besides the oxidation/reduction process, first-principles calculations show that the variation of d electrons is also responsible for the magnetization variation. Our work discloses the role of gate oxides with a relatively low O{sup 2−} ion mobility in electrical control of magnetism, and might pave the way for the magneto-ionic memory with low power consumption and high endurance performance.

  13. Mechanically reliable surface oxides for high-temperature corrosion resistance

    SciTech Connect

    Natesan, K.; Veal, B.W.; Grimsditch, M.; Renusch, D.; Paulikas, A.P.

    1995-05-01

    Corrosion is widely recognized as being important, but an understanding of the underlying phenomena involves factors such as the chemistry and physics of early stages of oxidation, chemistry and bonding at the substrate/oxide interface, role of segregants on the strength of that bond, transport processes through scale, mechanisms of residual stress generation and relief, and fracture behavior at the oxide/substrate interface. Because of this complexity a multilaboratory program has been initiated under the auspices of the DOE Center of Excellence for the Synthesis and Processing of Advanced Materials, with strong interactions and cross-leveraging with DOE Fossil Energy and US industry. Objective is to systematically generate the knowledge required to establish a scientific basis for designing and synthesizing improved protective oxide scales/coatings (slow-growing, adherent, sound) on high-temperature materials without compromising the requisite properties of the bulk materials. The objectives of program work at Argonne are to (1) correlate actual corrosion performance with stresses, voids, segregants, interface roughness, initial stages of oxidation, and microstructures; (2) study such behavior in growing or as-grown films; and (3) define prescriptive design and synthesis routes to mechanically reliable surface oxides. Several techniques, such as Auger electron spectroscopy, X-ray diffraction, X-ray grazing incidence reflectance, grazing-angle X-ray fluorescence, optical fluorescence, and Raman spectroscopy, are used in the studies. Tne project has selected Fe-25 wt.% Cr-20 wt.% Ni and Fe-Cr-Al alloys, which are chromia- and alumina-formers respectively, for the studies. This paper presents some of the results on early stages of oxidation and on surface segregation of elements.

  14. Reliability characterizations and failure mechanism of ultra-thin oxides for MOS devices

    NASA Astrophysics Data System (ADS)

    Wang, Bin

    The aggressive scaling of smaller/faster logic and memory devices demands accurate reliability characterization and knowledge of the failure mechanisms of ultra-thin (<30 A) silicon dioxide (SiO 2) layers in the gates of metal-oxide semiconductor (MOS) structures. The increased occurrence of soft breakdown in ultra-thin oxide films necessitates the development of more sophisticated techniques to detect breakdown. One such technique is by interrupting stress and monitoring stress-induced leakage current (SILC) or interface state density (Dit). The effect of interrupting stress was carefully studied and determined not to affect device lifetime. A comprehensive time-dependent dielectric breakdown (TDDB) study was conducted on ultra-thin oxide over a temperature ranging from 220°C to 350°C to study temperature acceleration. The results of the study showed that both hard and soft breakdown modes exhibit the same temperature dependence. The choice of a failure model for time/charge to breakdown (tBD /QBD) is critical for accurate reliability extrapolation. In this work, two more experiments were carried out to clarify the current physical mechanisms responsible to dielectric wear-out. The first experiment investigated the effects of pulsed biased stress on device lifetime. A lifetime enhancement under bipolar pulse stress was observed. The results suggest that previously proposed mechanism of hole de-trapping in thick oxide may not be responsible for the lifetime increase observed here for ultra-thin oxides. The second experiment studied the effects of heavy ion on the reliability of ultra-thin SiO2. Annealing and electron injection experiments on irradiated devices with heavy ion implied that holes were significantly created and trapped inside SiO2 without causing the SiO2 to breakdown. The results from these two studies suggest that breakdown of ultra-thin oxides is not caused by holes and that the anode hole injection (AHI) model for constant voltage stress (CVS) is

  15. Highly Reliable Liquid-Phase-Deposited SiO2 with Nitrous Oxide Plasma Post-Treatment for Low-Temperature-Processed Polysilicon Thin Film Transistors

    NASA Astrophysics Data System (ADS)

    Yeh, Ching-Fa; Chen, Darren Chi-Hsiang; Lu, Cheng-Yu; Liu, Chung; Lee, Su-Tseng; Liu, Cheng-Hong; Chen, Tai-Ju

    2002-10-01

    Low-temperature (˜300°C) N2O-plasma post-treatment for liquid-phase-deposited (LPD) gate oxide has been proposed for the first time. This treatment successfully takes the place of conventional furnace annealing in O2 ambient. Results of physicochemical and electrical characteristics show that N2O-plasma post-treated LPD-SiO2 has a high electrical breakdown field and low interface state density. In addition, N2O-plasma treatment also improves the Si-rich phenomenon of LPD-SiO2. From the comparison with pure N2O-plasma oxidation film, LPD-SiO2 with its short re-oxidation time in N2O plasma plays an important role in relieving interfacial stress. Finally, the novel technology is applied to the gate oxide of low-temperature-processed (LTP) polysilicon thin film transistors (poly-Si TFTs). The device performance reveals excellent electrical characteristics, and the reliability shows a satisfactory result, as well as the gate oxide reliability. It is believed that the N2O-plasma post-treatment not only improves the oxide quality, but also effectively passivates the trap states of poly-Si TFTs.

  16. Dual Gate Thin Film Transistors Based on Indium Oxide Active Layers

    SciTech Connect

    Kekuda, Dhananjaya; Rao, K. Mohan; Tolpadi, Amita; Chu, C. W.

    2011-07-15

    Polycrystalline Indium Oxide (In{sub 2}O{sub 3}) thin films were employed as an active channel layer for the fabrication of bottom and top gate thin film transistors. While conventional SiO{sub 2} served as a bottom gate dielectric, cross-linked poly-4-vinylphenol (PVP) was used a top gate dielectric. These nano-crystalline TFTs exhibited n-channel behavior with their transport behavior highly dependent on the thickness of the channel. The correlation between the thickness of the active layer and TFT parameters such as on/off ratio, field-effect mobility, threshold voltage were carried out. The optical spectra revealed a high transmittance in the entire visible region, thus making them promising candidates for the display technology.

  17. Direct deposition of aluminum oxide gate dielectric on graphene channel using nitrogen plasma treatment

    SciTech Connect

    Lim, Taekyung; Kim, Dongchool; Ju, Sanghyun

    2013-07-01

    Deposition of high-quality dielectric on a graphene channel is an essential technology to overcome structural constraints for the development of nano-electronic devices. In this study, we investigated a method for directly depositing aluminum oxide (Al{sub 2}O{sub 3}) on a graphene channel through nitrogen plasma treatment. The deposited Al{sub 2}O{sub 3} thin film on graphene demonstrated excellent dielectric properties with negligible charge trapping and de-trapping in the gate insulator. A top-gate-structural graphene transistor was fabricated using Al{sub 2}O{sub 3} as the gate dielectric with nitrogen plasma treatment on graphene channel region, and exhibited p-type transistor characteristics.

  18. Characterization of reliability of printed indium tin oxide thin films.

    PubMed

    Hong, Sung-Jei; Kim, Jong-Woong; Jung, Seung-Boo

    2013-11-01

    Recently, decreasing the amount of indium (In) element in the indium tin oxide (ITO) used for transparent conductive oxide (TCO) thin film has become necessary for cost reduction. One possible approach to this problem is using printed ITO thin film instead of sputtered. Previous studies showed potential for printed ITO thin films as the TCO layer. However, nothing has been reported on the reliability of printed ITO thin films. Therefore, in this study, the reliability of printed ITO thin films was characterized. ITO nanoparticle ink was fabricated and printed onto a glass substrate followed by heating at 400 degrees C. After measurement of the initial values of sheet resistance and optical transmittance of the printed ITO thin films, their reliabilities were characterized with an isothermal-isohumidity test for 500 hours at 85 degrees C and 85% RH, a thermal shock test for 1,000 cycles between 125 degrees C and -40 degrees C, and a high temperature storage test for 500 hours at 125 degrees C. The same properties were investigated after the tests. Printed ITO thin films showed stable properties despite extremely thermal and humid conditions. Sheet resistances of the printed ITO thin films changed slightly from 435 omega/square to 735 omega/square 507 omega/square and 442 omega/square after the tests, respectively. Optical transmittances of the printed ITO thin films were slightly changed from 84.74% to 81.86%, 88.03% and 88.26% after the tests, respectively. These test results suggest the stability of printed ITO thin film despite extreme environments. PMID:24245331

  19. Note: Design and construction of a simple and reliable printed circuit board-substrate Bradbury-Nielsen gate for ion mobility spectrometry

    NASA Astrophysics Data System (ADS)

    Du, Yongzhai; Cang, Huaiwen; Wang, Weiguo; Han, Fenglei; Chen, Chuang; Li, Lin; Hou, Keyong; Li, Haiyang

    2011-08-01

    A less laborious, structure-simple, and performance-reliable printed circuit board (PCB) based Bradbury-Nielsen gate for high-resolution ion mobility spectrometry was introduced and investigated. The gate substrate was manufactured using a PCB etching process with small holes (Φ 0.1 mm) drilled along the gold-plated copper lines. Two interdigitated sets of rigid stainless steel spring wire (Φ 0.1 mm) that stands high temperature and guarantees performance stability were threaded through the holes. Our homebuilt ion mobility spectrometer mounted with the gate gave results of about 40 for resolution while keeping a signal intensity of over 0.5 nano-amperes.

  20. Effect of reverse body bias on hot-electron-induced punchthrough reliability of pMOSFETs with thin gate dielectric at high temperatures

    NASA Astrophysics Data System (ADS)

    Kang, YongHa; Kim, JongKyun; Lee, NamHyun; Oh, MinGeon; Hwang, YuChul; Moon, ByungMoo

    2016-06-01

    The effect of the reverse body bias V SB on the hot-electron-induced punch-through (HEIP) reliability of pMOSFETs with a thin gate dielectric at high temperatures was investigated for the first time. Experimental results indicate that the reverse V SB increased the HEIP degradation for a thin pMOSFET because of the increase in the maximum electric field E m due to the increase in the threshold voltage V th. The sensitivity of HEIP degradation to V SB increased with increasing body effect coefficient γ at a given oxide thickness T ox. However, a thin device (22 Å) showed a much stronger dependence of HEIP degradation on V SB due to the decrease in the velocity saturation length l, although it had a smaller γ than a thick device (60 Å). These new observations suggest that the body bias technique for improving circuit performance can cause a reliability problem of nanoscale pMOSFETs at high temperatures and impose a significant limitation on CMOS device scaling.

  1. In-line 90 nm Technology Gate Oxide Nitrogen Monitoring With Non-Contact Electrical Technique

    NASA Astrophysics Data System (ADS)

    Pic, Nicolas; Polisski, Gennadi; Paire, Emmanuel; Rizzo, Véronique; Grosjean, Catherine; Bortolotti, Benjamin; D'Amico, John; Cabuil, Nicolas

    2009-09-01

    The continuous race to reduce the dimensions of IC components has lead to the introduction of Nitrogen in the thin gate oxide layer in order to increase the dielectric constant and to improve the gate dielectric properties. It is mandatory to apply in-line monitoring to control the amount of Nitrogen to ensure that electrical behavior is correct over time. Historically, this monitoring was performed by measuring the delay to reoxidation (D2R) with an ellipsometer. But, this method is not suitable in production as it is depending on both initial oxidation and reoxidation reproducibility, which implies implementing dedicated Statistical Process Control (SPC) monitoring at these two specific processing steps. We are here presenting an alternative method to D2R for 90 nm Technology gate oxide grown by Rapid Thermal Process (RTP). Applying a non-contact Metrology technique, which couples Kelvin probe surface voltage measurement with surface Corona deposition, directly after the nitridation step, the interface trapped charge (QIT) is obtained by integration of the interface state density over the space charge region. In summary, this electrical non-contact monitoring is more sensitive to the Nitrogen content compared to ellipsometer measurement after nitridation or after D2R, less sensitive compared to D2R to any initial oxide variation, and it allows simplification of the qualification procedure at this process step by skipping the reoxidation.

  2. Band offsets of a ruthenium gate on ultrathin high-{kappa} oxide films on silicon

    SciTech Connect

    Rangan, Sylvie; Bersch, Eric; Bartynski, Robert Allen; Garfunkel, Eric; Vescovo, Elio

    2009-02-15

    Valence-band and conduction-band edges of ultrathin oxides (SiO{sub 2}, HfO{sub 2}, Hf{sub 0.7}Si{sub 0.3}O{sub 2}, and Al{sub 2}O{sub 3} grown on silicon) and their shifts upon sequential metallization with ruthenium have been measured using synchrotron-radiation-excited x-ray, ultraviolet, and inverse photoemissions. From these techniques, the offsets between the valence-band and conduction-band edges of the oxides, and the ruthenium metal gate Fermi edge have been directly measured. In addition the core levels of the oxides and the ruthenium have been characterized. Upon deposition, Ru remains metallic and no chemical alteration of the underlying oxide gates, or interfacial SiO{sub 2} in the case of the high-{kappa} thin films, can be detected. However a clear shift of the band edges is measured for all samples due to the creation of an interface dipole at the ruthenium-oxide interface. Using the energy gap, the electron affinity of the oxides, and the ruthenium work function that have been directly measured on these samples, the experimental band offsets are compared to those predicted by the induced gap states model.

  3. Band Offsets of a Ruthenium Gate on Ultrathin High-k Oxide Films on Silicon

    SciTech Connect

    Rangan, S.; Bersch, W; Bartynski, R; Garfunkel, E; Vescovo, E

    2009-01-01

    Valence-band and conduction-band edges of ultrathin oxides and their shifts upon sequential metallization with ruthenium have been measured using synchrotron-radiation-excited x-ray, ultraviolet, and inverse photoemissions. From these techniques, the offsets between the valence-band and conduction-band edges of the oxides, and the ruthenium metal gate Fermi edge have been directly measured. In addition the core levels of the oxides and the ruthenium have been characterized. Upon deposition, Ru remains metallic and no chemical alteration of the underlying oxide gates, or interfacial SiO{sub 2} in the case of the high-? thin films, can be detected. However a clear shift of the band edges is measured for all samples due to the creation of an interface dipole at the ruthenium-oxide interface. Using the energy gap, the electron affinity of the oxides, and the ruthenium work function that have been directly measured on these samples, the experimental band offsets are compared to those predicted by the induced gap states model.

  4. Total-dose and charge-trapping effects in gate oxides for CMOS LSI devices

    SciTech Connect

    Singh, R.S.; Kaputa, D.J.; Korman, C.S.; Surowiec, E.P.

    1984-12-01

    The effect of gamma irradiation on CMOS devices fabricated using 3 Micron CMOS BULK process has been studied as a function of gate oxide processing and subsequent annealing. Threshold shifts, speed degradation, and power supply currents were measured as a function of total dose up to 10/sup 6/ Rad (Si). Using hot electron injection techniques, trapping densities and capture cross-sections of the traps in each oxide type have been determined at pre- and post-irradiation levels. Power supply leakage and speed performance of the devices were recovered within three to five hours by annealing them at 125/sup 0/C, +10 V bias.

  5. Effect of low and high temperature anneal on process-induced damage of gate oxide

    SciTech Connect

    King, J.C.; Hu, C. . Dept. of Electrical Engineering and Computer Sciences)

    1994-11-01

    The authors have investigated the ability of high and low temperature anneals to repair the gate oxide damage due to simulated electrical stress caused by wafer charging resulting from plasma etching, etc. Even 800 C anneal cannot restore the stability in interface trap generation. Even 900 C anneal cannot repair the deteriorated charge-to-breakdown and oxide charge trapping. As a small consolation, the ineffectiveness of anneal in repairing the process-induced damage allows them to monitor the damages even at the end of the fabrication process.

  6. The interfaces of lanthanum oxide-based subnanometer EOT gate dielectrics

    PubMed Central

    2014-01-01

    When pushing the gate dielectric thickness of metal-oxide-semiconductor (MOS) devices down to the subnanometer scale, the most challenging issue is the interface. The interfacial transition layers between the high-k dielectric/Si and between the high-k dielectric/gate metal become the critical constraints for the smallest achievable film thickness. This work presents a detailed study on the interface bonding structures of the tungsten/lanthanum oxide/silicon (W/La2O3/Si) MOS structure. We found that both W/La2O3 and La2O3/Si are thermally unstable. Thermal annealing can lead to W oxidation and the forming of a complex oxide layer at the W/La2O3 interface. For the La2O3/Si interface, thermal annealing leads to a thick low-k silicate layer. These interface layers do not only cause significant device performance degradation, but also impose a limit on the thinnest equivalent oxide thickness (EOT) to be achievable which may be well above the requirements of our future technology nodes. PMID:25246873

  7. Direct Imaging of Nanoscale Conductance Evolution in Ion-Gel-Gated Oxide Transistors.

    PubMed

    Ren, Yuan; Yuan, Hongtao; Wu, Xiaoyu; Chen, Zhuoyu; Iwasa, Yoshihiro; Cui, Yi; Hwang, Harold Y; Lai, Keji

    2015-07-01

    Electrostatic modification of functional materials by electrolytic gating has demonstrated a remarkably wide range of density modulation, a condition crucial for developing novel electronic phases in systems ranging from complex oxides to layered chalcogenides. Yet little is known microscopically when carriers are modulated in electrolyte-gated electric double-layer transistors (EDLTs) due to the technical challenge of imaging the buried electrolyte-semiconductor interface. Here, we demonstrate the real-space mapping of the channel conductance in ZnO EDLTs using a cryogenic microwave impedance microscope. A spin-coated ionic gel layer with typical thicknesses below 50 nm allows us to perform high resolution (on the order of 100 nm) subsurface imaging, while maintaining the capability of inducing the metal-insulator transition under a gate bias. The microwave images vividly show the spatial evolution of channel conductance and its local fluctuations through the transition as well as the uneven conductance distribution established by a large source-drain bias. The unique combination of ultrathin ion-gel gating and microwave imaging offers a new opportunity to study the local transport and mesoscopic electronic properties in EDLTs. PMID:26061780

  8. High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

    PubMed

    Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

    2015-07-01

    A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications. PMID:26039187

  9. Gate controllable resistive random access memory devices using reduced graphene oxide

    NASA Astrophysics Data System (ADS)

    Hazra, Preetam; Resmi, A. N.; Jinesh, K. B.

    2016-04-01

    The biggest challenge in the resistive random access memory (ReRAM) technology is that the basic operational parameters, such as the set and reset voltages, the current on-off ratios (hence the power), and their operational speeds, strongly depend on the active and electrode materials and their processing methods. Therefore, for its actual technological implementations, the unification of the operational parameters of the ReRAM devices appears to be a difficult task. In this letter, we show that by fabricating a resistive memory device in a thin film transistor configuration and thus applying an external gate bias, we can control the switching voltage very accurately. Taking partially reduced graphene oxide, the gate controllable switching is demonstrated, and the possible mechanisms are discussed.

  10. New Trap-Assisted Band-to-Band Tunneling Induced Gate Current Model for P-Channel Metal-Oxide-Semiconductor Field Effect Transistors with Sub-3 nm Oxides

    NASA Astrophysics Data System (ADS)

    Lee, Hai-Ming; Liu, Cheng-Jye; Hsu, Chih-Wei; Liang, Mong-Song; King, Ya-Chin; Hsu, Charles Ching-Hsiang

    2001-03-01

    A new trap-assisted band-to-band tunneling (TAB) gate current model is proposed to describe the new observed band-to-band tunneling (BBT) induced gate current characteristics of p-channel metal-oxide-semiconductor field effect transistors (PMOSFET’s) with ultra-thin gate oxide. Based on this new TAB gate current model, the off-state gate currents of PMOSFET’s with various sub-3 nm gate oxides can be well characterized, while the conventional BBT current model is no longer applicable in this regime.

  11. Random Interface-Traps-Induced Electrical Characteristic Fluctuation in 16-nm-Gate High-κ/Metal Gate Complementary Metal-Oxide-Semiconductor Device and Inverter Circuit

    NASA Astrophysics Data System (ADS)

    Li, Yiming; Cheng, Hui-Wen

    2012-04-01

    This work estimates electrical and transfer-characteristic fluctuations in 16-nm-gate high-κ/metal gate (HKMG) metal-oxide-semiconductor field effect transistor (MOSFET) devices and inverter circuit induced by random interface traps (ITs) at high-κ/silicon interface. Randomly generated devices with two-dimensional (2D) ITs at HfO2/Si interface are incorporated into quantum-mechanically corrected 3D device simulation. Device characteristics, as influenced by different degrees of fluctuation, are discussed in relation to random ITs near source and drain ends. Owing to a decreasing penetration of electric field from drain to source, the drain induced barrier lowering (DIBL) of the edvice decreases when the number of ITs increases. In contrast to random-dopant fluctuation, the screening effect of device's inversion layer cannot effectively screen potential's variation; thus, devices still have noticeable fluctuation of gate capacitance (CG) under high gate bias. The cutoff frequency decreases as increasing the number of ITs owing to the decreasing transconductance and increasing CG. Decreasing on-state current and increasing CG further result in increasing intrinsic gate delay time (τ) when the number of ITs increases. The fluctuation magnitude of DIBL, cutoff frequency, and τ above is increased as the number of ITs increases. Even for cases with the same number of random ITs, noise margins (NMs) of the 16-nm-gate complementary metal-oxide-semiconductor inverter circuit are still quite different due to the different distribution of random ITs. The NMs of inverter circuit increase as the number of random ITs increases; however, the NMs' fluctuations are increased due to the more sources of fluctuation at HfO2/Si interface of HKMG devices.

  12. Quantum-Mechanical Simulation of Gate Tunneling Current in Accumulated n-Channel Metal-Oxide-Semiconductor Devices with n+-Polysilicon Gates

    NASA Astrophysics Data System (ADS)

    Iwata, Hideyuki; Matsuda, Toshihiro; Ohzone, Takashi

    2002-08-01

    The gate tunneling current in n+-polysilicon gate n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) in accumulation regime has been simulated quantum-mechanically. The two current components, due to hole tunneling from the accumulation layer on the p-silicon surface and due to electron tunneling from the accumulation layer on the n+-polysilicon gate, have been investigated for bulk and silicon-on-insulator (SOI) MOSFETs with various SOI layer thicknesses. For bulk MOSFETs, the electron current from the gate becomes much larger than the hole current from the silicon surface. On the other hand, as the SOI layer thickness (tSOI) decreases, the hole current increases, but the electron current decreases, and thus the hole current exceeds the electron current at a certain tSOI. The total gate current increases with decreasing tSOI (>2 nm). For extremely thin tSOI, the contribution of the electron current almost disappears. Moreover, the quantum-mechanical effects on the tunneling current in accumulated SOI MOSFETs have been discussed in detail.

  13. Al and Ge simultaneous oxidation using neutral beam post-oxidation for formation of gate stack structures

    SciTech Connect

    Ohno, Takeo; Nakayama, Daiki; Samukawa, Seiji

    2015-09-28

    To obtain a high-quality Germanium (Ge) metal–oxide–semiconductor structure, a Ge gate stacked structure was fabricated using neutral beam post-oxidation. After deposition of a 1-nm-thick Al metal film on a Ge substrate, simultaneous oxidation of Al and Ge was carried out at 300 °C, and a Ge oxide film with 29% GeO{sub 2} content was obtained by controlling the acceleration bias power of the neutral oxygen beam. In addition, the fabricated AlO{sub x}/GeO{sub x}/Ge structure achieved a low interface state density of less than 1 × 10{sup 11 }cm{sup −2 }eV{sup −1} near the midgap.

  14. Top-gate zinc tin oxide thin-film transistors with high bias and environmental stress stability

    NASA Astrophysics Data System (ADS)

    Fakhri, M.; Theisen, M.; Behrendt, A.; Görrn, P.; Riedl, T.

    2014-06-01

    Top gated metal-oxide thin-film transistors (TFTs) provide two benefits compared to their conventional bottom-gate counterparts: (i) The gate dielectric may concomitantly serve as encapsulation layer for the TFT channel. (ii) Damage of the dielectric due to high-energetic particles during channel deposition can be avoided. In our work, the top-gate dielectric is prepared by ozone based atomic layer deposition at low temperatures. For ultra-low gas permeation rates, we introduce nano-laminates of Al2O3/ZrO2 as dielectrics. The resulting TFTs show a superior environmental stability even at elevated temperatures. Their outstanding stability vs. bias stress is benchmarked against bottom-gate devices with encapsulation.

  15. Top-gate zinc tin oxide thin-film transistors with high bias and environmental stress stability

    SciTech Connect

    Fakhri, M.; Theisen, M.; Behrendt, A.; Görrn, P.; Riedl, T.

    2014-06-23

    Top gated metal-oxide thin-film transistors (TFTs) provide two benefits compared to their conventional bottom-gate counterparts: (i) The gate dielectric may concomitantly serve as encapsulation layer for the TFT channel. (ii) Damage of the dielectric due to high-energetic particles during channel deposition can be avoided. In our work, the top-gate dielectric is prepared by ozone based atomic layer deposition at low temperatures. For ultra-low gas permeation rates, we introduce nano-laminates of Al{sub 2}O{sub 3}/ZrO{sub 2} as dielectrics. The resulting TFTs show a superior environmental stability even at elevated temperatures. Their outstanding stability vs. bias stress is benchmarked against bottom-gate devices with encapsulation.

  16. Control of interfacial properties of Pr-oxide/Ge gate stack structure by introduction of nitrogen

    NASA Astrophysics Data System (ADS)

    Kato, Kimihiko; Kondo, Hiroki; Sakashita, Mitsuo; Nakatsuka, Osamu; Zaima, Shigeaki

    2011-06-01

    We have demonstrated the control of interfacial properties of Pr-oxide/Ge gate stack structure by the introduction of nitrogen. From C- V characteristics of Al/Pr-oxide/Ge 3N 4/Ge MOS capacitors, the interface state density decreases without the change of the accumulation capacitance after annealing. The TEM and TED measurements reveal that the crystallization of Pr-oxide is enhanced with annealing and the columnar structure of cubic-Pr 2O 3 is formed after annealing. From the depth profiles measured using XPS with Ar sputtering for the Pr-oxide/Ge 3N 4/Ge stack structure, the increase in the Ge component is not observed in a Pr-oxide film and near the interface between a Pr-oxide film and a Ge substrate. In addition, the N component segregates near the interface region, amorphous Pr-oxynitride (PrON) is formed at the interface. As a result, Pr-oxide/PrON/Ge stacked structure without the Ge-oxynitride interlayer is formed.

  17. Study of charge control and gate tunneling in a ferroelectric-oxide-silicon field effect transistor: Comparison with a conventional metal-oxide-silicon structure

    NASA Astrophysics Data System (ADS)

    Lin, Yih-Yin; Zhang, Yifei; Singh, Jasprit; York, Robert; Mishra, Umesh

    2001-02-01

    It is known that conventional metal-oxide-silicon (MOS) devices will have gate tunneling related problems at very thin oxide thicknesses. Various high-dielectric-constant materials are being examined to suppress the gate currents. In this article we present theoretical results of a charge control and gate tunneling model for a ferroelectric-oxide-silicon field effect transistor and compare them to results for a conventional MOS device. The potential of high polarization charge to induce inversion without doping and high dielectric constant to suppress tunneling current is explored. The model is based on a self-consistent solution of the quantum problem and includes the ferroelectric hysteresis response self-consistently. We show that the polarization charge associated with ferroelectrics can allow greater controllability of the inversion layer charge density. Also the high dielectric constant of ferroelectrics results in greatly suppressed gate current.

  18. Trap Profiling Based on Frequency Varied Charge Pumping Method for Hot Carrier Stressed Thin Gate Oxide Metal Oxide Semiconductors Field Effect Transistors.

    PubMed

    Choi, Pyungho; Kim, Hyunjin; Kim, Sangsub; Kim, Soonkon; Javadi, Reza; Park, Hyoungsun; Choi, Byoungdeog

    2016-05-01

    In this study, pulse frequency and reverse bias voltage is modified in charge pumping and advanced technique is presented to extract oxide trap profile in hot carrier stressed thin gate oxide metal oxide semiconductor field effect transistors (MOSFETs). Carrier trapping-detrapping in a gate oxide was analyzed after hot carrier stress and the relationship between trapping depth and frequency was investigated. Hot carrier induced interface traps appears in whole channel area but induced border traps mainly appears in above pinch-off region near drain and gradually decreases toward center of the channel. Thus, hot carrier stress causes interface trap generation in whole channel area while most border trap generation occurs in the drain region under the gate. Ultimately, modified charge pumping method was performed to get trap density distribution of hot carrier stressed MOSFET devices, and the trapping-detrapping mechanism is also analyzed. PMID:27483833

  19. Lanthanide-based oxides and silicates for high-kappa gate dielectric applications

    NASA Astrophysics Data System (ADS)

    Jur, Jesse Stephen

    The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high current leakage between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high-kappa dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-kappa dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. In this work, lanthanum oxide films have been deposited by thermal evaporation on to a pre-grown chemical oxide layer on silicon. It is observed that the SiO2 interfacial layer can be consumed by a low-temperature reaction with lanthanum oxide to produce a high-quality silicate. This is opposed to depositing lanthanum oxide directly on silicon, which can possibly favor silicide formation. The importance of oxygen regulation in the surrounding environment of the La2O3-SiO2 reaction-anneal is observed. By controlling the oxygen available during the reaction, SiO2 growth can be limited to achieve high stoichiometric ratios of La2O 3 to SiO2. As a result, MOS devices with an equivalent oxide thickness (EOT) of 5 A and a leakage current density of 5.0 A/cm 2 are attained. This data equals the best value achieved in this field and is a

  20. Lateral-coupling coplanar-gate oxide-based thin-film transistors on bare paper substrates

    NASA Astrophysics Data System (ADS)

    Wu, Guodong; Wan, Xiang; Yang, Yi; Jiang, Shuanghe

    2014-11-01

    For conventional thin-film transistors (TFTs), bottom-gate or top-gate configuration is always adopted because the channel current is generally controlled by vertical capacitive coupling. In this article, depending on huge lateral electric-double-layer (EDL) capacitor induced by spatial movement of protons in phosphosilicate glass (PSG) solid electrolyte dielectrics, coplanar-gate indium-zinc-oxide (IZO)-TFTs based on the lateral capacitive coupling were fabricated on bare paper substrates. The PSG solid electrolyte films here were used at the same time as gate dielectrics and smooth buffer layers. These TFTs showed a low-voltage operation of only 1 V with a large field-effect mobility of 13.4 cm2 V-1·s, a high current on/off ratio of 6  ×  106 and a small subthreshold swing of 75 mV/decade. Furthermore, with introducing another coplanar gate, AND logic operation was also demonstrated on the coplanar dual-gate TFTs. These simple lateral-coupling coplanar-gate IZO-TFTs on bare paper substrates are very promising for low-cost portable sensors and bio-electronics.

  1. Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

    SciTech Connect

    Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

    2009-11-30

    We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgO{sub x} and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgO{sub x} gate operates under low voltage write-erase (WR-ER) pulse of {+-}20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of {+-}70 V for WR and ER states. Both devices stably operated under visible illuminations.

  2. Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics.

    PubMed

    Park, Sungjun; Lee, SeYeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

    2015-01-01

    Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 10(7), and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo. PMID:26271456

  3. Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics

    NASA Astrophysics Data System (ADS)

    Park, Sungjun; Lee, Seyeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

    2015-08-01

    Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 107, and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo.

  4. Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics

    PubMed Central

    Park, Sungjun; Lee, SeYeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

    2015-01-01

    Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 107, and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo. PMID:26271456

  5. Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

    NASA Astrophysics Data System (ADS)

    Inaba, Masafumi; Muta, Tsubasa; Kobayashi, Mikinori; Saito, Toshiki; Shibata, Masanobu; Matsumura, Daisuke; Kudo, Takuya; Hiraiwa, Atsushi; Kawarada, Hiroshi

    2016-07-01

    The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al2O3. Using Al2O3 as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

  6. Multiplexed aptasensors and amplified DNA sensors using functionalized graphene oxide: application for logic gate operations.

    PubMed

    Liu, Xiaoqing; Aizen, Ruth; Freeman, Ronit; Yehezkeli, Omer; Willner, Itamar

    2012-04-24

    Graphene oxide (GO) is implemented as a functional matrix for developing fluorescent sensors for the amplified multiplexed detection of DNA, aptamer-substrate complexes, and for the integration of predesigned DNA constructs that activate logic gate operations. Fluorophore-labeled DNA strands acting as probes for two different DNA targets are adsorbed onto GO, leading to the quenching of the luminescence of the fluorophores. Desorption of the probes from the GO, through hybridization with the target DNAs, leads to the fluorescence of the respective label. By coupling exonuclease III, Exo III, to the system, the recycling of the target DNAs is demonstrated, and this leads to the amplified detection of the DNA targets (detection limit 5 × 10(-12) M). Similarly, adsorption of fluorophore-functionalized aptamers against thrombin or ATP onto the GO leads to the desorption of the aptamer-substrate complexes from GO and to the triggering of the luminescence corresponding to the respective fluorophore, thus, allowing the multiplexed analysis of the aptamer-substrate complexes. By designing functional fluorophore-labeled DNA constructs and their interaction with GO, in the presence (or absence) of nucleic acids, or two different substrates for aptamers, as inputs, the activation of the "OR" and "AND" logic gates is demonstrated. PMID:22404375

  7. Evolution of Insulator-Metal Phase Transitions in Epitaxial Tungsten Oxide Films during Electrolyte-Gating.

    PubMed

    Nishihaya, Shinichi; Uchida, Masaki; Kozuka, Yusuke; Iwasa, Yoshihiro; Kawasaki, Masashi; Nishihaya, S; Uchida, M; Kozuka, Y; Iwasa, Y; Kawasaki, M; Iwasa, Y; Kawasaki, M

    2016-08-31

    An interface between an oxide and an electrolyte gives rise to various processes as exemplified by electrostatic charge accumulation/depletion and electrochemical reactions such as intercalation/decalation under electric field. Here we directly compare typical device operations of those in electric double layer transistor geometry by adopting A-site vacant perovskite WO3 epitaxial thin films as a channel material and two different electrolytes as gating agent. In situ measurements of X-ray diffraction and channel resistance performed during the gating revealed that in both the cases WO3 thin film reaches a new metallic state through multiple phase transitions, accompanied by the change in out-of-plane lattice constant. Electrons are electrostatically accumulated from the interface side with an ionic liquid, while alkaline metal ions are more uniformly intercalated into the film with a polymer electrolyte. We systematically demonstrate this difference in the electrostatic and electrochemical processes, by comparing doped carrier density, lattice deformation behavior, and time constant of the phase transitions. PMID:27502546

  8. High performance high-κ/metal gate complementary metal oxide semiconductor circuit element on flexible silicon

    NASA Astrophysics Data System (ADS)

    Torres Sevilla, G. A.; Almuslem, A. S.; Gumus, A.; Hussain, A. M.; Cruz, M. E.; Hussain, M. M.

    2016-02-01

    Thinned silicon based complementary metal oxide semiconductor (CMOS) electronics can be physically flexible. To overcome challenges of limited thinning and damaging of devices originated from back grinding process, we show sequential reactive ion etching of silicon with the assistance from soft polymeric materials to efficiently achieve thinned (40 μm) and flexible (1.5 cm bending radius) silicon based functional CMOS inverters with high-κ/metal gate transistors. Notable advances through this study shows large area of silicon thinning with pre-fabricated high performance elements with ultra-large-scale-integration density (using 90 nm node technology) and then dicing of such large and thinned (seemingly fragile) pieces into smaller pieces using excimer laser. The impact of various mechanical bending and bending cycles show undeterred high performance of flexible silicon CMOS inverters. Future work will include transfer of diced silicon chips to destination site, interconnects, and packaging to obtain fully flexible electronic systems in CMOS compatible way.

  9. Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

    NASA Astrophysics Data System (ADS)

    Lee, Eunji; Chowdhury, Md Delwar Hossain; Park, Min Sang; Jang, Jin

    2015-12-01

    We have studied the effect of top gate bias (VTG) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm2 intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the VTG from -15 to +15 V. By changing VTG from negative to positive, the Fermi level (EF) shifts toward conduction band edge (EC), which substantially controls the conversion of neutral vacancy to charged one (VO → VO+/VO2+ + e-/2e-), peroxide (O22-) formation or conversion of ionized interstitial (Oi2-) to neutral interstitial (Oi), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows -2.7 V shift at VTG = -15 V, which gradually decreases to -0.42 V shift at VTG = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (VO+/VO2+/O22-/Oi) and/or hole trapping in the a-IGZO /interfaces.

  10. Thermally stable, sub-nanometer equivalent oxide thickness gate stack for gate-first In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors

    NASA Astrophysics Data System (ADS)

    El Kazzi, M.; Czornomaz, L.; Rossel, C.; Gerl, C.; Caimi, D.; Siegwart, H.; Fompeyrine, J.; Marchiori, C.

    2012-02-01

    Metal-oxide-semiconductor (MOS) capacitors were fabricated by depositing composite 2 nm HfO2/1 nm Al2O3/1 nm a-Si gate stacks on p-In0.53Ga0.47As/InP (001) substrates. Thanks to the presence of the Al2O3 barrier layer, a minimum amount of the a-Si passivating layer is oxidized during the whole fabrication process. The capacitors exhibit excellent electrical characteristics with scaled equivalent oxide thickness (EOT) of 0.89 nm and mid-gap interface state density of 5 × 1011 eV-1 cm-2 upon post-metallization anneal up to 550 °C. Gate-first, self-aligned MOS field-effect-transistors were fabricated with a similar 5 nm HfO2/1 nm Al2O3/1 nm a-Si gate stack and raised source and drain (600 °C for 30 min). Owing to the excellent thermal stability of the stack, no degradation of the gate stack/semiconductor interface is observed, as demonstrated by the excellent capacitance vs voltage characteristics and the good mobility values (peak at 1030 cm2 V-1 s-1 and 740 cm2 V-1 s-1 at carrier density of 6.5 × 1012 cm-2) for a 1.3 nm EOT.

  11. Characterization of high-k gate dielectrics based on hafnium oxide and titanium oxide for CMOS application

    NASA Astrophysics Data System (ADS)

    Lee, Sanghyun

    Hafnium oxide, Titanium oxide, and ternary alloys with nitrided films of each of the above on Silicon and Germanium substrate were investigated in effort of understanding origins and various factors governing intrinsic band edge defects and interface trapped charges which are crucial to implent the high-k dielectrics into CMOS device below Electrical Equivalent Thickness (EOT) < 1nm. Novel design of atomic scale molecule was applied to achieve superb quality guided by the bond constrain theory. Tetrahedral bonding of Hf and Ti oxide in each Hf/Ti Silicon oxynitride gave the chemical stability upon annealing up to 1100°C. From the spectroscopic and electrical measurements, defect states were suppressed by reducing oxygen vacancy related defect states in Hf/Ti Silicon oxynitride. Conduction and valence band edge defect states were detected and reduced by limiting the thickness of HfO2 to 2 nm which is critical length for forming coherent inter-primitive pi bonding between Hf dpi-O ppi orbitals. As a result, Jahn-Teller d state term splittings were suppressed. The application of ultrathin Hf oxide and Hf Si oxynitride films onto Ge (100) and Ge (111) substrates resulted in the elimination of interfacial transition layer by removing Ge-N and possibly Ge-O bond after 800°C anneal. This could afford re-grown Ge epitaxial layer on top of Ge substrate which dramatically reduced the defect states between Hf Silicon oxynitride and Ge substrate. The gate leakage current for Hf Silicon oxynitride was lower than that on Si substrate.

  12. A stable ATP binding to the nucleotide binding domain is important for reliable gating cycle in an ABC transporter CFTR.

    PubMed

    Shimizu, Hiroyasu; Yu, Ying-Chun; Kono, Koichi; Kubota, Takahiro; Yasui, Masato; Li, Min; Hwang, Tzyh-Chang; Sohma, Yoshiro

    2010-09-01

    Cystic fibrosis transmembrane conductance regulator (CFTR) anion channel, a member of ABC transporter superfamily, gates following ATP-dependent conformational changes of the nucleotide binding domains (NBD). Reflecting the hundreds of milliseconds duration of the channel open state corresponding to the dimerization of two NBDs, macroscopic WT-CFTR currents usually showed a fast, single exponential relaxation upon removal of cytoplasmic ATP. Mutations of tyrosine1219, a residue critical for ATP binding in second NBD (NBD2), induced a significant slow phase in the current relaxation, suggesting that weakening ATP binding affinity at NBD2 increases the probability of the stable open state. The slow phase was effectively diminished by a higher affinity ATP analogue. These data suggest that a stable binding of ATP to NBD2 is required for normal CFTR gating cycle, andthat the instability of ATP binding frequently halts the gating cycle in the open state presumably through a failure of ATP hydrolysis at NBD2. PMID:20628841

  13. A stable ATP binding to the nucleotide binding domain is important for reliable gating cycle in an ABC transporter CFTR

    PubMed Central

    Shimizu, Hiroyasu; Yu, Ying-Chun; Kono, Koichi; Kubota, Takahiro; Yasui, Masato; Li, Min

    2016-01-01

    Cystic fibrosis transmembrane conductance regulator (CFTR) anion channel, a member of ABC transporter superfamily, gates following ATP-dependent conformational changes of the nucleotide binding domains (NBD). Reflecting the hundreds of milliseconds duration of the channel open state corresponding to the dimerization of two NBDs, macroscopic WT-CFTR currents usually showed a fast, single exponential relaxation upon removal of cytoplasmic ATP. Mutations of tyrosine1219, a residue critical for ATP binding in second NBD (NBD2), induced a significant slow phase in the current relaxation, suggesting that weakening ATP binding affinity at NBD2 increases the probability of the stable open state. The slow phase was effectively diminished by a higher affinity ATP analogue. These data suggest that a stable binding of ATP to NBD2 is required for normal CFTR gating cycle, andthat the instability of ATP binding frequently halts the gating cycle in the open state presumably through a failure of ATP hydrolysis at NBD2. PMID:20628841

  14. Electronic States of Hafnium and Vanadium oxide in Silicon Gate Stack Structure

    NASA Astrophysics Data System (ADS)

    Zhu, Chiyu; Tang, Fu; Liu, Xin; Yang, Jialing; Nemanich, Robert

    2010-03-01

    Vanadium oxide (VO2) is a narrow band gap material with a metal-insulator transition (MIT) at less than 100C. Hafnium oxide (HfO2) is currently the preferred high-k material for gate dielectrics. To utilize VO2 in a charge storage device, it is necessary to understand the band relationships between VO2, HfO2, and Si substrate. In this study, a 2nm thick VO2 layer is embedded in a dielectric stack structure between an oxidized n-type Si(100) surface and a 2nm HfO2 layer. The in situ experiments are carried out in an UHV multi-chamber system. After each growth step, the surface is characterized using XPS and UPS. After the initial plasma cleaning and oxidation treatment the Si substrate displayed essentially flat bands at the surface. After deposition of the VO2 layer, the Si 2p peak shifted to lower binding energy, and the Si 2p associated with the SiO2 layer also was shifted, indicating an internal field in the SiO2. The VO2 valence band maximum (VBM) was identified at 0.6 eV below the Fermi level (EF). This ultra thin VO2 exhibits the metal-insulator transition at a temperature higher than thicker films. As a comparison, a 100nm thick film of VO2 on Si showed a MIT at 60C. After the HfO2 deposition, the Si 2p substrate feature returned to the initial value indicating a return to flat band conditions. The UPS indicated the VBM of HfO2 at 4.0 eV below EF. This work is supported by the NSF (DMR-0805353).

  15. Electron mobility in ultra-thin InGaAs channels: Impact of surface orientation and different gate oxide materials

    NASA Astrophysics Data System (ADS)

    Krivec, Sabina; Poljak, Mirko; Suligoj, Tomislav

    2016-01-01

    Electron mobility is investigated in sub-20 nm-thick InGaAs channels, sandwiched between different gate oxides (SiO2, Al2O3, HfO2) and InP as substrate, using physics-based numerical modeling. Effects of body thickness downscaling to 2 nm, different gate oxides, and surface orientation [(1 0 0) and (1 1 1)] are examined by including all electron valleys and all relevant scattering mechanisms. We report that ultra-thin (1 1 1) Al2O3-InGaAs-InP devices offer greater electron mobility than (1 0 0) devices even in the extremely-thin channels. Furthermore, ultra-thin (1 0 0) InGaAs devices outperform SOI in terms of electron mobility for body thicknesses above ∼4 nm, while (1 1 1) InGaAs channels are superior to SOI for all body thickness values above ∼3 nm. The study of different gate oxides indicates that HfO2 is the optimum gate dielectric regardless of device orientation, offering a mobility improvement of up to 124% for (1 1 1) and 149% for (1 0 0) surface orientation, when compared to the initial Al2O3-InGaAs-InP structure. The (1 1 1) orientation offers improvement over (1 0 0) device irrespective of the body thickness and gate oxide material, with the highest difference reported for SiO2, followed by Al2O3 and HfO2.

  16. Analytical model for an asymmetric double-gate MOSFET with gate-oxide thickness and flat-band voltage variations in the subthreshold region

    NASA Astrophysics Data System (ADS)

    Shin, Yong Hyeon; Yun, Ilgu

    2016-06-01

    This paper proposes an analytical model for an asymmetric double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) with varying gate-oxide thickness (tox) and flat-band voltage (Vfb) in the subthreshold region. Since such variations cannot be completely avoided, the modeling of their behaviors is essential. The analytical model is developed by solving a 2D Poisson equation with a varying channel doping concentration (NA). To solve the 2D Poisson equation of the asymmetric DG MOSFET, a perturbation method is used to separate the solution of the channel potential into basic and perturbed terms. Since the basic terms can be regarded as the equations derived from a general symmetric doped DG MOSFET, the conventional analytical model is adopted. In addition, a solution related to the perturbed terms for the asymmetric structures is obtained using Fourier series. Based on the obtained channel potential, the electrical characteristics of the drive current (IDS) are expressed in the analytical model. The prediction of the electrical characteristics by the analytical model shows excellent agreement when compared with commercially available 2D numerical device simulation results with respect to not only tox and Vfb variations but also channel length and NA variations.

  17. GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistor Fabricated with Novel Wet Etching

    NASA Astrophysics Data System (ADS)

    Kodama, Masahito; Sugimoto, Masahiro; Hayashi, Eiko; Soejima, Narumasa; Ishiguro, Osamu; Kanechika, Masakazu; Itoh, Kenji; Ueda, Hiroyuki; Uesugi, Tsutomu; Kachi, Tetsu

    2008-02-01

    A novel method for fabricating trench structures on GaN was developed. A smooth non-polar (1100) plane was obtained by wet etching using tetramethylammonium hydroxide (TMAH) as the etchant. A U-shape trench with the (1100) plane side walls was formed with dry etching and the TMAH wet etching. A U-shape trench gate metal oxide semiconductor field-effect transistor (MOSFET) was also fabricated using the novel etching technology. This device has the excellent normally-off operation of drain current-gate voltage characteristics with the threshold voltage of 10 V. The drain breakdown voltage of 180 V was obtained. The results indicate that the trench gate structure can be applied to GaN-based transistors.

  18. Improvement in performance of solution-processed indium-zinc-tin oxide thin-film transistors by UV/O3 treatment on zirconium oxide gate insulator

    NASA Astrophysics Data System (ADS)

    Naik, Bukke Ravindra; Avis, Christophe; Delwar Hossain Chowdhury, Md; Kim, Taehun; Lin, Tengda; Jang, Jin

    2016-03-01

    We studied solution-processed amorphous indium-zinc-tin oxide (a-IZTO) thin-film transistors (TFTs) with spin-coated zirconium oxide (ZrOx) as the gate insulator. The ZrOx gate insulator was used without and with UV/O3 treatment. The TFTs with an untreated ZrOx gate dielectric showed a saturation mobility (μsat) of 0.91 ± 0.29 cm2 V-1 s-1, a threshold voltage (Vth) of 0.28 ± 0.36 V, a subthreshold swing (SS) of 199 ± 37.17 mV/dec, and a current ratio (ION/IOFF) of ˜107. The TFTs with a UV/O3-treated ZrOx gate insulator exhibited μsat of 2.65 ± 0.43 cm2 V-1 s-1, Vth of 0.44 ± 0.35 V, SS of 133 ± 24.81 mV/dec, and ION/IOFF of ˜108. Hysteresis was 0.32 V in the untreated TFTs and was eliminated by UV/O3 treatment. Also, the leakage current decreased significantly when the IZTO TFT was coated onto a UV/O3-treated ZrOx gate insulator.

  19. Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

    SciTech Connect

    Chun, Minkyu; Chowdhury, Md Delwar Hossain; Jang, Jin

    2015-05-15

    We investigated the effects of top gate voltage (V{sub TG}) and temperature (in the range of 25 to 70 {sup o}C) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The increment of V{sub TG} from -20V to +20V, decreases the threshold voltage (V{sub TH}) from 19.6V to 3.8V and increases the electron density to 8.8 x 10{sup 18}cm{sup −3}. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on V{sub TG}. At V{sub TG} of 20V, the mobility decreases from 19.1 to 15.4 cm{sup 2}/V ⋅ s with increasing temperature, showing a metallic conduction. On the other hand, at V{sub TG} of - 20V, the mobility increases from 6.4 to 7.5cm{sup 2}/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.

  20. Gate dielectric development for flexible electronics

    SciTech Connect

    Joshi, P. C.; Voutsas, A. T.; Hartzell, J. W.

    2007-07-15

    Thin film transistors integrated on flexible substrates are becoming increasingly attractive for low cost displays, sensors, and rf communication applications. The successful development of the flexible devices will be dictated by the enhancement in the thermal stability of the substrates and the low temperature (<300 deg. C) processing of the gate dielectric. The plasma-enhanced chemical-vapor deposition (PECVD) technique has successfully met the demands of the gate dielectric for display devices at processing temperatures lower than 600 deg. C. However, a further reduction in the processing temperatures below 300 deg. C is essential to realize low cost, highly functional devices on flexible substrates. The low temperature processing of gate dielectric films necessitates the development of processes and techniques with plasma controlled reaction kinetics dominating the thin film growth rather than the thermal state of the substrate. In the present work, the authors report on the processing of high quality gate dielectric films by high density PECVD technique at process temperatures lower than 300 deg. C. The bulk and interfacial electrical quality and reliability of the metal-oxide-semiconductor capacitors as a function of process temperature are discussed in this article. A comparison with the high temperature gate oxide films deposited by PECVD technique employing capacitively coupled plasma source has been made to establish the film quality and reliability. The films processed at low temperatures have shown good electrical performance and reliability as evaluated in terms of the leakage current, flatband voltage, midgap interface trap concentration, and bias temperature stress reliability characteristics.

  1. Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

    SciTech Connect

    Lee, Eunji; Chowdhury, Md Delwar Hossain; Park, Min Sang; Jang, Jin

    2015-12-07

    We have studied the effect of top gate bias (V{sub TG}) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm{sup 2} intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the V{sub TG} from −15 to +15 V. By changing V{sub TG} from negative to positive, the Fermi level (E{sub F}) shifts toward conduction band edge (E{sub C}), which substantially controls the conversion of neutral vacancy to charged one (V{sub O} → V{sub O}{sup +}/V{sub O}{sup 2+} + e{sup −}/2e{sup −}), peroxide (O{sub 2}{sup 2−}) formation or conversion of ionized interstitial (O{sub i}{sup 2−}) to neutral interstitial (O{sub i}), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows −2.7 V shift at V{sub TG} = −15 V, which gradually decreases to −0.42 V shift at V{sub TG} = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (V{sub O}{sup +}/V{sub O}{sup 2+}/O{sub 2}{sup 2−}/O{sub i}) and/or hole trapping in the a-IGZO /interfaces.

  2. Self-aligned graphene field-effect transistors on SiC (0001) substrates with self-oxidized gate dielectric

    NASA Astrophysics Data System (ADS)

    Jia, Li; Cui, Yu; Li, Wang; Qingbin, Liu; Zezhao, He; Shujun, Cai; Zhihong, Feng

    2014-07-01

    A scalable self-aligned approach is employed to fabricate monolayer graphene field-effect transistors on semi-insulated 4H-SiC (0001) substrates. The self-aligned process minimized access resistance and parasitic capacitance. Self-oxidized Al2O3, formed by deposition of 2 nm Al followed by exposure in air to be oxidized, is used as gate dielectric and shows excellent insulation. An intrinsic cutoff frequency of 34 GHz and maximum oscillation frequency of 36.4 GHz are realized for the monolayer graphene field-effect transistor with a gate length of 0.2 μm. These studies show a pathway to fabricate graphene transistors for future applications in ultra-high frequency circuits.

  3. Short-Term Synaptic Plasticity Regulation in Solution-Gated Indium-Gallium-Zinc-Oxide Electric-Double-Layer Transistors.

    PubMed

    Wan, Chang Jin; Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

    2016-04-20

    In the biological nervous system, synaptic plasticity regulation is based on the modulation of ionic fluxes, and such regulation was regarded as the fundamental mechanism underlying memory and learning. Inspired by such biological strategies, indium-gallium-zinc-oxide (IGZO) electric-double-layer (EDL) transistors gated by aqueous solutions were proposed for synaptic behavior emulations. Short-term synaptic plasticity, such as paired-pulse facilitation, high-pass filtering, and orientation tuning, was experimentally emulated in these EDL transistors. Most importantly, we found that such short-term synaptic plasticity can be effectively regulated by alcohol (ethyl alcohol) and salt (potassium chloride) additives. Our results suggest that solution gated oxide-based EDL transistors could act as the platforms for short-term synaptic plasticity emulation. PMID:27007748

  4. A Novel Sub-20 V Contact Gate Metal Oxide Semiconductor Field Effect Transistor with Fully Complementary Metal Oxide Semiconductor Compatible Process

    NASA Astrophysics Data System (ADS)

    Lee, Te Liang; Tsang Tsai, Ming; King, Ya Chin; Lin, Chrong Jung

    2013-04-01

    In this paper, a novel sub-20 V device which is called contact gate MOSFET (CGMOS) with fully CMOS logic compatible process is proposed and demonstrated. Comparing with lateral double diffusion MOSFET (LDMOS), CGMOS uses P substrate instead of N minus layer as drift region in logic process, and a contact on resistance protection oxide (RPO) layers to form an extra gate on the drain side of the channel region to provide a better gate control and reduce the surface field. This new device significantly rises up the breakdown voltage to 18 V with specific on-resistance 8.8 mΩ.mm2 in a small high voltage (HV) MOSFET area. Since there is no extra mask for creating the drift region or additional step for the wire bonding, CGMOS makes the integration of high voltage and logic circuits much simpler and area-saving.

  5. Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

    NASA Astrophysics Data System (ADS)

    Asahara, Ryohei; Hideshima, Iori; Oka, Hiroshi; Minoura, Yuya; Ogawa, Shingo; Yoshigoe, Akitaka; Teraoka, Yuden; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2015-06-01

    Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlOx) interlayers. A step-by-step in situ procedure by deposition of AlOx and hafnium oxide (HfOx) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO2/AlOx/GeOx/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlOx interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56 nm and very low interface state density of 2.4 × 1011 cm-2eV-1 with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

  6. Low-temperature formation of high-quality gate oxide by ultraviolet irradiation on spin-on-glass

    NASA Astrophysics Data System (ADS)

    Usuda, R.; Uchida, K.; Nozaki, S.

    2015-11-01

    Although a UV cure was found to effectively convert a perhydropolysilazane (PHPS) spin-on-glass film into a dense SiOx film at low temperature, the electrical characteristics were never reported in order to recommend the use of PHPS as a gate-oxide material that can be formed at low temperature. We have formed a high-quality gate oxide by UV irradiation on the PHPS film, and obtained an interface midgap trap density of 3.4 × 1011 cm-2 eV-1 by the UV wet oxidation and UV post-metallization annealing (PMA), at a temperature as low as 160 °C. In contrast to the UV irradiation using short-wavelength UV light, which is well known to enhance oxidation by the production of the excited states of oxygen, the UV irradiation was carried out using longer-wavelength UV light from a metal halide lamp. The UV irradiation during the wet oxidation of the PHPS film generates electron-hole pairs. The electrons ionize the H2O molecules and facilitate dissociation of the molecules into H and OH-. The OH- ions are highly reactive with Si and improve the stoichiometry of the oxide. The UV irradiation during the PMA excites the electrons from the accumulation layer, and the built-in electric field makes the electron injection into the oxide much easier. The electrons injected into the oxide recombine with the trapped holes, which have caused a large negative flat band voltage shift after the UV wet oxidation, and also ionize the H2O molecules. The ionization results in the electron stimulated dissociation of H2O molecules and the decreased interface trap density.

  7. Low-temperature formation of high-quality gate oxide by ultraviolet irradiation on spin-on-glass

    SciTech Connect

    Usuda, R.; Uchida, K.; Nozaki, S.

    2015-11-02

    Although a UV cure was found to effectively convert a perhydropolysilazane (PHPS) spin-on-glass film into a dense SiO{sub x} film at low temperature, the electrical characteristics were never reported in order to recommend the use of PHPS as a gate-oxide material that can be formed at low temperature. We have formed a high-quality gate oxide by UV irradiation on the PHPS film, and obtained an interface midgap trap density of 3.4 × 10{sup 11 }cm{sup −2} eV{sup −1} by the UV wet oxidation and UV post-metallization annealing (PMA), at a temperature as low as 160 °C. In contrast to the UV irradiation using short-wavelength UV light, which is well known to enhance oxidation by the production of the excited states of oxygen, the UV irradiation was carried out using longer-wavelength UV light from a metal halide lamp. The UV irradiation during the wet oxidation of the PHPS film generates electron-hole pairs. The electrons ionize the H{sub 2}O molecules and facilitate dissociation of the molecules into H and OH{sup −}. The OH{sup −} ions are highly reactive with Si and improve the stoichiometry of the oxide. The UV irradiation during the PMA excites the electrons from the accumulation layer, and the built-in electric field makes the electron injection into the oxide much easier. The electrons injected into the oxide recombine with the trapped holes, which have caused a large negative flat band voltage shift after the UV wet oxidation, and also ionize the H{sub 2}O molecules. The ionization results in the electron stimulated dissociation of H{sub 2}O molecules and the decreased interface trap density.

  8. Structural and thermodynamic consideration of metal oxide doped GeO{sub 2} for gate stack formation on germanium

    SciTech Connect

    Lu, Cimang Lee, Choong Hyun; Zhang, Wenfeng; Nishimura, Tomonori; Nagashio, Kosuke; Toriumi, Akira

    2014-11-07

    A systematic investigation was carried out on the material and electrical properties of metal oxide doped germanium dioxide (M-GeO{sub 2}) on Ge. We propose two criteria on the selection of desirable M-GeO{sub 2} for gate stack formation on Ge. First, metal oxides with larger cation radii show stronger ability in modifying GeO{sub 2} network, benefiting the thermal stability and water resistance in M-GeO{sub 2}/Ge stacks. Second, metal oxides with a positive Gibbs free energy for germanidation are required for good interface properties of M-GeO{sub 2}/Ge stacks in terms of preventing the Ge-M metallic bond formation. Aggressive equivalent oxide thickness scaling to 0.5 nm is also demonstrated based on these understandings.

  9. Impact of the crystallization of the high-k dielectric gate oxide on the positive bias temperature instability of the n-channel metal-oxide-semiconductor field emission transistor

    NASA Astrophysics Data System (ADS)

    Lim, Han Jin; Kim, Youngkuk; Sang Jeon, In; Yeo, Jaehyun; Im, Badro; Hong, Soojin; Kim, Bong-Hyun; Nam, Seok-Woo; Kang, Ho-kyu; Jung, E. S.

    2013-06-01

    The positive bias temperature instability (PBTI) characteristics of the n-channel metal-oxide-semiconductor field emission transistors which had different kinds of high-k dielectric gate oxides were studied with the different stress-relaxation times. The degradation in the threshold voltage followed a power-law on the stress times. In particular, we found that their PBTI behaviors were closely related to the structural phase of the high-k dielectric gate oxide. In an amorphous gate oxide, the negative charges were trapped into the stress-induced defects of which energy level was so deep that the trapped charges were de-trapped slowly. Meanwhile, in a crystalline gate oxide, the negative charges were trapped mostly in the pre-existing defects in the crystallized films during early stage of the stress time and de-trapped quickly due to the shallow energy level of the defects.

  10. Understanding the Structure of High-K Gate Oxides - Oral Presentation

    SciTech Connect

    Miranda, Andre

    2015-08-25

    Hafnium Oxide (HfO2) amorphous thin films are being used as gate oxides in transistors because of their high dielectric constant (κ) over Silicon Dioxide. The present study looks to find the atomic structure of HfO2 thin films which hasn’t been done with the technique of this study. In this study, two HfO2 samples were studied. One sample was made with thermal atomic layer deposition (ALD) on top of a Chromium and Gold layer on a silicon wafer. The second sample was made with plasma ALD on top of a Chromium and Gold layer on a Silicon wafer. Both films were deposited at a thickness of 50nm. To obtain atomic structure information, Grazing Incidence X-ray diffraction (GIXRD) was carried out on the HfO2 samples. Because of this, absorption, footprint, polarization, and dead time corrections were applied to the scattering intensity data collected. The scattering curves displayed a difference in structure between the ALD processes. The plasma ALD sample showed the broad peak characteristic of an amorphous structure whereas the thermal ALD sample showed an amorphous structure with characteristics of crystalline materials. This appears to suggest that the thermal process results in a mostly amorphous material with crystallites within. Further, the scattering intensity data was used to calculate a pair distribution function (PDF) to show more atomic structure. The PDF showed atom distances in the plasma ALD sample had structure up to 10 Å, while the thermal ALD sample showed the same structure below 10 Å. This structure that shows up below 10 Å matches the bond distances of HfO2 published in literature. The PDF for the thermal ALD sample also showed peaks up to 20 Å, suggesting repeating atomic spacing outside the HfO2 molecule in the sample. This appears to suggest that there is some crystalline structure within the thermal ALD sample.

  11. The physical origin of dispersion in accumulation in InGaAs based metal oxide semiconductor gate stacks

    NASA Astrophysics Data System (ADS)

    Krylov, Igor; Ritter, Dan; Eizenberg, Moshe

    2015-05-01

    Dispersion in accumulation is a widely observed phenomenon in technologically important InGaAs gate stacks. Two principal different interface defects were proposed as the physical origin of this phenomenon—disorder induced gap states and border traps. While the gap states are located at the semiconductor side of the interface, the border traps are related to the dielectric side. The study of Al2O3, HfO2, and an intermediate composition of HfxAlyO deposited on InGaAs enabled us to find a correlation between the dispersion and the dielectric/InGaAs band offset. At the same time, no change in the dispersion was observed after applying an effective pre-deposition treatment which results in significant reduction of the interface states. Both observations prove that border traps are the physical origin of the dispersion in accumulation in InGaAs based metal-oxide-semiconductor gate stacks.

  12. Metal-oxide thin-film transistor-based pH sensor with a silver nanowire top gate electrode

    NASA Astrophysics Data System (ADS)

    Yoo, Tae-Hee; Sang, Byoung-In; Wang, Byung-Yong; Lim, Dae-Soon; Kang, Hyun Wook; Choi, Won Kook; Lee, Young Tack; Oh, Young-Jei; Hwang, Do Kyung

    2016-04-01

    Amorphous InGaZnO (IGZO) metal-oxide-semiconductor thin-film transistors (TFTs) are one of the most promising technologies to replace amorphous and polycrystalline Si TFTs. Recently, TFT-based sensing platforms have been gaining significant interests. Here, we report on IGZO transistor-based pH sensors in aqueous medium. In order to achieve stable operation in aqueous environment and enhance sensitivity, we used Al2O3 grown by using atomic layer deposition (ALD) and a porous Ag nanowire (NW) mesh as the top gate dielectric and electrode layers, respectively. Such devices with a Ag NW mesh at the top gate electrode rapidly respond to the pH of solutions by shifting the turn-on voltage. Furthermore, the output voltage signals induced by the voltage shifts can be directly extracted by implantation of a resistive load inverter.

  13. A compact quantum correction model for symmetric double gate metal-oxide-semiconductor field-effect transistor

    SciTech Connect

    Cho, Edward Namkyu; Shin, Yong Hyeon; Yun, Ilgu

    2014-11-07

    A compact quantum correction model for a symmetric double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. The compact quantum correction model is proposed from the concepts of the threshold voltage shift (ΔV{sub TH}{sup QM}) and the gate capacitance (C{sub g}) degradation. First of all, ΔV{sub TH}{sup QM} induced by quantum mechanical (QM) effects is modeled. The C{sub g} degradation is then modeled by introducing the inversion layer centroid. With ΔV{sub TH}{sup QM} and the C{sub g} degradation, the QM effects are implemented in previously reported classical model and a comparison between the proposed quantum correction model and numerical simulation results is presented. Based on the results, the proposed quantum correction model can be applicable to the compact model of DG MOSFET.

  14. Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme

    NASA Astrophysics Data System (ADS)

    Veloso, Anabela; Boccardi, Guillaume; Ragnarsson, Lars-Åke; Higuchi, Yuichi; Arimura, Hiroaki; Lee, Jae Woo; Simoen, Eddy; Cho, Moon Ju; Roussel, Philippe J.; Paraschiv, Vasile; Shi, Xiaoping; Schram, Tom; Aik Chew, Soon; Brus, Stephan; Dangol, Anish; Vecchio, Emma; Sebaai, Farid; Kellens, Kristof; Heylen, Nancy; Devriendt, Katia; Dekkers, Harold; Van Ammel, Annemie; Witters, Thomas; Conard, Thierry; Vaesen, Inge; Richard, Olivier; Bender, Hugo; Athimulam, Raja; Chiarella, Thomas; Thean, Aaron; Horiguchi, Naoto

    2014-01-01

    We report on aggressively scaled replacement metal gate, high-k last (RMG-HKL) planar and multi-gate fin field-effect transistor (FinFET) devices, systematically investigating the impact of post high-k deposition thermal (PDA) and plasma (SF6) treatments on device characteristics, and providing a deeper insight into underlying degradation mechanisms. We demonstrate that: 1) substantially reduced gate leakage (JG) and noise can be obtained for both type of devices with PDA and F incorporation in the gate stack by SF6, without equivalent oxide thickness (EOT) penalty; 2) SF6 enables improved mobility and reduced interface trapped charge density (Nit) down to narrower fin devices [fin width (WFin) ≥ 5 nm], mitigating the impact of fin patterning and fin sidewall crystal orientations, while allowing a simplified dual-effective work function (EWF) CMOS scheme suitable for both device architectures; 3) PDA yields smaller, in absolute values, PMOS threshold voltage |VT|, and substantially improved reliability behavior due to reduction of bulk defects.

  15. Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors

    NASA Astrophysics Data System (ADS)

    Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

    2013-10-01

    In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements. Electronic supplementary information (ESI) available. See DOI: 10.1039/c3nr02987e

  16. Extraction of Distance Between Interface Trap and Oxide Trap from Random Telegraph Noise in Gate-Induced Drain Leakage.

    PubMed

    Seo, Youngsoo; Yoo, Sungwon; Shin, Joonha; Kim, Hyunsoo; Kim, Hyunsuk; Jeon, Sangbin; Shin, Hyungcheol

    2016-05-01

    This paper presents an analysis of the Random Telegraph Noise (RTN) of the Gate-Induced Drain Leakage (GIDL) of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The RTN data that was measured and analytical equations are used to extract the values of the parameters for the vertical distance of the oxide trap from the interface and of the energy level of the interface trap. These values and equations allow for the distance r between the interface trap and the oxide trap to be extracted. For the first time, the accurate field enhancement factor γ(F), which depends on the magnitude of the electric field at the Si/SiO2 interface, was used to calculate the current ratio before and after the electron trapping, and the value extracted for r is completely different depending on the enhancement factor that is used. PMID:27483908

  17. Performance enhancement of multiple-gate ZnO metal-oxide-semiconductor field-effect transistors fabricated using self-aligned and laser interference photolithography techniques

    PubMed Central

    2014-01-01

    The simple self-aligned photolithography technique and laser interference photolithography technique were proposed and utilized to fabricate multiple-gate ZnO metal-oxide-semiconductor field-effect transistors (MOSFETs). Since the multiple-gate structure could improve the electrical field distribution along the ZnO channel, the performance of the ZnO MOSFETs could be enhanced. The performance of the multiple-gate ZnO MOSFETs was better than that of the conventional single-gate ZnO MOSFETs. The higher the drain-source saturation current (12.41 mA/mm), the higher the transconductance (5.35 mS/mm) and the lower the anomalous off-current (5.7 μA/mm) for the multiple-gate ZnO MOSFETs were obtained. PMID:24948884

  18. Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

    PubMed Central

    Hussin, H.; Soin, N.; Bukhori, M. F.; Wan Muhamad Hatta, S.; Abdul Wahab, Y.

    2014-01-01

    We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2 are increased but is reduced by 11% when the SiO2 interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2 interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated. PMID:25221784

  19. Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors

    NASA Astrophysics Data System (ADS)

    Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

    2016-04-01

    In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade-1 and 3.62 × 1011 eV-1 cm-2, respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

  20. Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.

    PubMed

    Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

    2016-12-01

    In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade(-1) and 3.62 × 10(11) eV(-1) cm(-2), respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT. PMID:27129687

  1. Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature

    NASA Astrophysics Data System (ADS)

    Liuan, Li; Jiaqi, Zhang; Yang, Liu; Jin-Ping, Ao

    2016-03-01

    In this paper, TiN/AlOx gated AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600 °C with the contact resistance approximately 1.6 Ω·mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/AlOx gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate AlGaN/GaN MOS-HFETs. Project supported by the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260).

  2. Improvement of Ron under AC Operation of Floating Island and Thick Bottom Oxide Trench Gate MOSFET (FITMOS)

    NASA Astrophysics Data System (ADS)

    Takaya, Hidefumi; Miyagi, Kyosuke; Hamada, Kimimori

    A MOSFET structure called a FITMOS (Floating Island and Thick Bottom Oxide Trench Gate MOSFET) that exhibits a record low loss in the 60V breakdown voltage (BVdss) range has been successfully developed. The following improvements achieved progress in the characteristic of FITMOS. (1) At the time of AC operation, the charges in the floating P islands that are a feature of the floating type device become greater, thereby increasing the on-resistance (Ron) due to the JFET effect. This issue was solved by forming passive hole gates in the end walls of the trenches. The Ron under AC operation is equivalent to the Ron under DC operation. This paper clarified the influence of the passive hole gate diffusion layer shape and the impurity concentration to BVdss and AC operation. (2) The trade-off of BVdss and Ron has been improved by making the floating island into an elliptical form. A BVdss of 83V and a specific on-resistance (RonA) of 36mΩmm2 were obtained.

  3. Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

    SciTech Connect

    Chao, Jin Yu; Zhu, Li Qiang Xiao, Hui; Yuan, Zhi Guo

    2015-12-21

    Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ∼1.0 V such as on/off ratio of ∼3 × 10{sup 7}, subthreshold swing of ∼65 mV/dec, threshold voltage of ∼0.3 V, and mobility of ∼7 cm{sup 2}/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor in series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.

  4. Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

    NASA Astrophysics Data System (ADS)

    Chao, Jin Yu; Zhu, Li Qiang; Xiao, Hui; Yuan, Zhi Guo

    2015-12-01

    Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ˜1.0 V such as on/off ratio of ˜3 × 107, subthreshold swing of ˜65 mV/dec, threshold voltage of ˜0.3 V, and mobility of ˜7 cm2/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor in series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.

  5. High-performance GaAs-based metal-oxide-semiconductor heterostructure field-effect transistors with atomic-layer-deposited Al2O3 gate oxide and in situ AlN passivation by metalorganic chemical vapor deposition

    NASA Astrophysics Data System (ADS)

    Aoki, Takeshi; Fukuhara, Noboru; Osada, Takenori; Sazawa, Hiroyuki; Hata, Masahiko; Inoue, Takayuki

    2014-10-01

    GaAs-based metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with Al2O3 gate oxide and in situ AlN passivation were investigated. Passivation with AlN improved the quality of the MOS interfaces, leading to good control of the gate. The devices had a sufficiently small subthreshold swing of 84 mV decade-1 in the drain current vs gate voltage curves, as well as negligible frequency dispersions and nearly zero hysteresis in the gate capacitance vs gate voltage curves. A maximum drain current of 630 mA/mm and a peak effective mobility of 6720 cm2 V-1 s-1 at a sheet carrier density of 3 × 1012 cm-2 were achieved.

  6. A high-mobility electronic system at an electrolyte-gated oxide surface

    PubMed Central

    Gallagher, Patrick; Lee, Menyoung; Petach, Trevor A.; Stanwyck, Sam W.; Williams, James R.; Watanabe, Kenji; Taniguchi, Takashi; Goldhaber-Gordon, David

    2015-01-01

    Electrolyte gating is a powerful technique for accumulating large carrier densities at a surface. Yet this approach suffers from significant sources of disorder: electrochemical reactions can damage or alter the sample, and the ions of the electrolyte and various dissolved contaminants sit Angstroms from the electron system. Accordingly, electrolyte gating is well suited to studies of superconductivity and other phenomena robust to disorder, but of limited use when reactions or disorder must be avoided. Here we demonstrate that these limitations can be overcome by protecting the sample with a chemically inert, atomically smooth sheet of hexagonal boron nitride. We illustrate our technique with electrolyte-gated strontium titanate, whose mobility when protected with boron nitride improves more than 10-fold while achieving carrier densities nearing 1014 cm−2. Our technique is portable to other materials, and should enable future studies where high carrier density modulation is required but electrochemical reactions and surface disorder must be minimized. PMID:25762485

  7. A Back-Gated Ferroelectric Field-Effect Transistor with an Al-Doped Zinc Oxide Channel

    NASA Astrophysics Data System (ADS)

    Jia, Ze; Xu, Jian-Long; Wu, Xiao; Zhang, Ming-Ming; Liou, Juin-J.

    2015-02-01

    We report a back-gated metal-oxide-ferroelectric-metal (MOFM) field-effect transistor (FET) with lead zirconate titanate (PZT) material, in which an Al doped zinc oxide (AZO) channel layer with an optimized doping concentration of 1% is applied to reduce the channel resistance of the channel layer, thus guaranteeing a large enough load capacity of the transistor. The hysteresis loops of the Pt/PZT/AZO/Ti/Pt capacitor are measured and compared with a Pt/PZT/Pt capacitor, indicating that the remnant polarization is almost 40 μC/cm2 and the polarization is saturated at 20 V. The measured capacitance-voltage properties are analyzed as a result of the electron depletion and accumulation switching operation conducted by the modulation of PZT on AZO channel resistance caused by the switchable remnant polarization of PZT. The switching properties of the AZO channel layer are also proved by the current-voltage transfer curves measured in the back-gated MOFM ferroelectric FET, which also show a drain current switching ratio up to about 100 times.

  8. Reduction method of gate-to-drain capacitance by oxide spacer formation in tunnel field-effect transistor with elevated drain

    NASA Astrophysics Data System (ADS)

    Kwon, Dae Woong; Kim, Jang Hyun; Park, Euyhwan; Lee, Junil; Park, Taehyung; Lee, Ryoongbin; Kim, Sihyun; Park, Byung-Gook

    2016-06-01

    A novel fabrication method is proposed to reduce large gate-to-drain capacitance (C GD) and to improve AC switching characteristics in tunnel field-effect transistor (TFETs) with elevated drain (TFETED). In the proposed method, gate oxide at drain region (GDOX) is selectively formed through oxide deposition and spacer-etch process. Furthermore, the thicknesses of the GDOX are simply controlled by the amount of the oxide deposition and etch. Mixed-mode device and circuit technology computer aided design (TCAD) simulations are performed to verify the effects of the GDOX thickness on DC and AC switching characteristics of a TFETED inverter. As a result, it is found that AC switching characteristics such as output voltage pre-shoot and falling/rising delay are improved with nearly unchanged DC characteristics by thicker GDOX. This improvement is explained successfully by reduced C GD and positive shifted gate voltage (V G) versus C GD curves with the thicker GDOX.

  9. Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

    SciTech Connect

    Asahara, Ryohei; Hideshima, Iori; Oka, Hiroshi; Minoura, Yuya; Hosoi, Takuji Shimura, Takayoshi; Watanabe, Heiji; Ogawa, Shingo; Yoshigoe, Akitaka; Teraoka, Yuden

    2015-06-08

    Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlO{sub x}) interlayers. A step-by-step in situ procedure by deposition of AlO{sub x} and hafnium oxide (HfO{sub x}) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO{sub 2}/AlO{sub x}/GeO{sub x}/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlO{sub x} interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56 nm and very low interface state density of 2.4 × 10{sup 11 }cm{sup −2}eV{sup −1} with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

  10. A New Two-Dimensional Analytical Model for Short-Channel Symmetrical Dual-Material Double-Gate Metal-Oxide-Semiconductor Field Effect Transistors

    NASA Astrophysics Data System (ADS)

    Chiang, Te-Kuang; Chen, Mei-Li

    2007-06-01

    Based on resultant solution of a two-dimensional (2D) Poisson’s equation in the silicon region, a new analytical model for short-channel fully depleted, symmetrical dual-material double-gate (SDMDG) metal-oxide-semiconductor field effect transistors (MOSFETs) has been developed. The SDMDG MOSFET exhibits significantly reduced short-channel effects (SCEs) when compared with the symmetrical double-gate (SDG) MOSFET due to the step potential profile at the interface between different gate materials. It is found that the threshold voltage roll-off can be effectively reduced using both the thin Si film and thin gate oxide. A considerable portion of the large workfunction of metal gate 1 (M1) when laterally merged with the small workfunction of metal gate 2 (M2) can efficiently suppress drain-induced barrier lowering (DIBL) and maintain the low threshold voltage degradation. In this work, not only a precise 2D analytical model of the surface potential and threshold voltage is presented, but also the minimum surface potential in M1 of the shorter channel device that brings about subthreshold swing degradation for the SDMDG MOSFET is discussed. The new model is verified to be in good agreement with numerical simulation results over a wide range of device parameters.

  11. Simulation of Nanoscale Two-Bit Not-And-type Silicon-Oxide-Nitride-Oxide-Silicon Nonvolatile Memory Devices with a Separated Double-Gate Fin Field Effect Transistor Structure Containing Different Tunneling Oxide Thicknesses

    NASA Astrophysics Data System (ADS)

    Oh, Se Woong; Park, Sang Su; Kim, Dong Hun; Kim, Hyun Woo; Kim, Tae Whan

    2009-06-01

    Not-and (NAND)-type silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory (NVM) devices with a separated double-gate (SDG) Fin field effect transistor structure were proposed to reduce the unit cell size of such memory devices and increase their memory density in comparison with that of conventional NVM devices. The proposed memory device consisted of a pair of control gates separated along the length of the Fin channel direction. Each SDG had a different thickness of the tunneling oxide to operate the proposed memory device as a two-bit/cell device. A technology computer-aided design simulation was performed to investigate the program/erase and two-bit characteristics. The simulation results show that the proposed devices can be used to increase the scaling down capability and charge storage density of NAND-type SONOS NVM devices.

  12. The n-type metal-oxide semiconductor field-effect transistor bias impact on the modelling of the gate-induced drain leakage current

    NASA Astrophysics Data System (ADS)

    Touhami, A.; Bouhdada, A.

    2002-12-01

    The band-to-band tunnelling (BBT) effect in an n-type metal-oxide semiconductor field-effect transistor (n-MOSFET) is attributed not only to the transverse electric field ET but also to the lateral electric field EL in the gate-to-drain overlap region. The main sources of these electric fields are the gate-source (Vgs) and drain-source (Vds) voltages. The modelling of the gate-induced drain leakage current, Igidl, associated with BBT remains always dependent on the drain-gate voltage, Vdg, whatever the applied values of Vgs and Vds, which cannot describe accurately the evolution of the Igidl current according to biases. Therefore, it is necessary to clarify the impact of Vgs and Vds separately. In this paper, we propose a new model of the Igidl current, which can describe the BBT effect in n-MOSFETs under various Vgs and Vds biases.

  13. Indium-zinc-oxide electric-double-layer thin-film transistors gated by silane coupling agents 3-triethoxysilylpropylamine-graphene oxide solid electrolyte

    NASA Astrophysics Data System (ADS)

    Guo, Liqiang; Huang, Yukai; Shi, Yangyang; Cheng, Guanggui; Ding, Jianning

    2015-07-01

    Silane coupling agents 3-triethoxysilylpropyla-mine-graphene oxide (KH550-GO) solid electrolyte are prepared by spin coating process. A high proton conductivity of ~1.2   ×   10-3 Scm-1 is obtained at room temperature. A strong electric-double-layer (EDL) effect is observed due to the accumulation of protons at KH550-GO/IZO interface. Indium-Zinc-Oxide thin film transistors gated by KH550-GO solid electrolyte are self-assembled on ITO glass substrates. Good electrical performances are obtained, such as a low subthreshold swing of ~140 mV/dec., a high current on/off ratio of ~2.9   ×   107 and a high field-effect mobility of ~13.2 cm2 V-1 S-1, respectively.

  14. Comparison between chemical vapor deposited and physical vapor deposited WSi2 metal gate for InGaAs n-metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Ong, B. S.; Pey, K. L.; Ong, C. Y.; Tan, C. S.; Antoniadis, D. A.; Fitzgerald, E. A.

    2011-05-01

    We compare chemical vapor deposition (CVD) and physical vapor deposition (PVD) WSi2 metal gate process for In0.53Ga0.47As n-metal-oxide-semiconductor field-effect transistors using 10 and 6.5 nm Al2O3 as dielectric layer. The CVD-processed metal gate device with 6.5 nm Al2O3 shows enhanced transistor performance such as drive current, maximum transconductance and maximum effective mobility. These values are relatively better than the PVD-processed counterpart device with improvement of 51.8%, 46.4%, and 47.8%, respectively. The improvement for the performance of the CVD-processed metal gate device is due to the fluorine passivation at the oxide/semiconductor interface and a nondestructive deposition process.

  15. Improvement in gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors using microwave irradiation

    SciTech Connect

    Jo, Kwang-Won; Cho, Won-Ju

    2014-11-24

    In this study, we evaluated the effects of microwave irradiation (MWI) post-deposition-annealing (PDA) treatment on the gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) and compared the results with a conventional thermal annealing PDA treatment. The MWI-PDA-treated a-IGZO TFTs exhibited enhanced electrical performance as well as improved long-term stability with increasing microwave power. The positive turn-on voltage shift (ΔV{sub ON}) as a function of stress time with positive bias and varying temperature was precisely modeled on a stretched-exponential equation, suggesting that charge trapping is a dominant mechanism in the instability of MWI-PDA-treated a-IGZO TFTs. The characteristic trapping time and average effective barrier height for electron transport indicate that the MWI-PDA treatment effectively reduces the defects in a-IGZO TFTs, resulting in a superior resistance against gate bias stress.

  16. Liquid-Gated High Mobility and Quantum Oscillation of the Two-Dimensional Electron Gas at an Oxide Interface.

    PubMed

    Zeng, Shengwei; Lü, Weiming; Huang, Zhen; Liu, Zhiqi; Han, Kun; Gopinadhan, Kalon; Li, Changjian; Guo, Rui; Zhou, Wenxiong; Ma, Haijiao Harsan; Jian, Linke; Venkatesan, Thirumalai; Ariando

    2016-04-26

    Electric field effect in electronic double layer transistor (EDLT) configuration with ionic liquids as the dielectric materials is a powerful means of exploring various properties in different materials. Here, we demonstrate the modulation of electrical transport properties and extremely high mobility of two-dimensional electron gas at LaAlO3/SrTiO3 (LAO/STO) interface through ionic liquid-assisted electric field effect. With a change of the gate voltages, the depletion of charge carrier and the resultant enhancement of electron mobility up to 19 380 cm(2)/(V s) are realized, leading to quantum oscillations of the conductivity at the LAO/STO interface. The present results suggest that high-mobility oxide interfaces, which exhibit quantum phenomena, could be obtained by ionic liquid-assisted field effect. PMID:26974812

  17. Atomic layer etching of ultra-thin HfO2 film for gate oxide in MOSFET devices

    NASA Astrophysics Data System (ADS)

    Park, Jae Beom; Lim, Woong Sun; Park, Byoung Jae; Park, Ih Ho; Kim, Young Woon; Yeom, Geun Young

    2009-03-01

    Precise etch depth control of ultra-thin HfO2 (3.5 nm) films applied as a gate oxide material was investigated by using atomic layer etching (ALET) with an energetic Ar beam and BCl3 gas. A monolayer etching condition of 1.2 Å/cycle with a low surface roughness and an unchanged surface composition was observed for ultra-thin, ALET-etched HfO2 by supplying BCl3 gas and an Ar beam at higher levels than the critical pressure and dose, respectively. When HfO2-nMOSFET devices were fabricated by ALET, a 70% increase in the drain current and a lower leakage current were observed compared with the device fabricated by conventional reactive ion etching, which was attributed to the decreased structural and electrical damage.

  18. Recovery from ultraviolet-induced threshold voltage shift in indium gallium zinc oxide thin film transistors by positive gate bias

    SciTech Connect

    Liu, P.; Chen, T. P.; Li, X. D.; Wong, J. I.; Liu, Z.; Liu, Y.; Leong, K. C.

    2013-11-11

    The effect of short-duration ultraviolet (UV) exposure on the threshold voltage (V{sub th}) of amorphous indium gallium zinc oxide thin film transistors (TFTs) and its recovery characteristics were investigated. The V{sub th} exhibited a significant negative shift after UV exposure. The V{sub th} instability caused by UV illumination is attributed to the positive charge trapping in the dielectric layer and/or at the channel/dielectric interface. The illuminated devices showed a slow recovery in threshold voltage without external bias. However, an instant recovery can be achieved by the application of positive gate pulses, which is due to the elimination of the positive trapped charges as a result of the presence of a large amount of field-induced electrons in the interface region.

  19. Lateral protonic/electronic hybrid oxide thin-film transistor gated by SiO{sub 2} nanogranular films

    SciTech Connect

    Zhu, Li Qiang Chao, Jin Yu; Xiao, Hui

    2014-12-15

    Ionic/electronic interaction offers an additional dimension in the recent advancements of condensed materials. Here, lateral gate control of conductivities of indium-zinc-oxide (IZO) films is reported. An electric-double-layer (EDL) transistor configuration was utilized with a phosphorous-doped SiO{sub 2} nanogranular film to provide a strong lateral electric field. Due to the strong lateral protonic/electronic interfacial coupling effect, the IZO EDL transistor could operate at a low-voltage of 1 V. A resistor-loaded inverter is built, showing a high voltage gain of ∼8 at a low supply voltage of 1 V. The lateral ionic/electronic coupling effects are interesting for bioelectronics and portable electronics.

  20. Lateral protonic/electronic hybrid oxide thin-film transistor gated by SiO2 nanogranular films

    NASA Astrophysics Data System (ADS)

    Zhu, Li Qiang; Chao, Jin Yu; Xiao, Hui

    2014-12-01

    Ionic/electronic interaction offers an additional dimension in the recent advancements of condensed materials. Here, lateral gate control of conductivities of indium-zinc-oxide (IZO) films is reported. An electric-double-layer (EDL) transistor configuration was utilized with a phosphorous-doped SiO2 nanogranular film to provide a strong lateral electric field. Due to the strong lateral protonic/electronic interfacial coupling effect, the IZO EDL transistor could operate at a low-voltage of 1 V. A resistor-loaded inverter is built, showing a high voltage gain of ˜8 at a low supply voltage of 1 V. The lateral ionic/electronic coupling effects are interesting for bioelectronics and portable electronics.

  1. Model for the field effect from layers of biological macromolecules on the gates of metal-oxide-semiconductor transistors

    NASA Astrophysics Data System (ADS)

    Landheer, D.; Aers, G.; McKinnon, W. R.; Deen, M. J.; Ranuarez, J. C.

    2005-08-01

    The potential diagram for field-effect transistors used to detect charged biological macromolecules in an electrolyte is presented for the case where an insulating cover layer is used over a conventional eletrolyte-insulator metal-oxide-semiconductor (EIMOS) structure to tether or bind the biological molecules to a floating gate. The layer of macromolecules is modeled using the Poisson-Boltzmann equation for an ion-permeable membrane. Expressions are derived for the charges and potentials in the EIMOS and electrolyte-insulator-semiconductor structures, including the membrane and electrolyte. Exact solutions for the potentials and charges are calculated using numerical algorithms. Simple expressions for the response are presented for low solution potentials when the Donnan potential is approached in the bulk of the membrane. The implications of the model for the small-signal equivalent circuit and the noise analysis of these structures are discussed.

  2. Use of nonpolar BaHfO3 gate oxide for field effect on the high mobility BaSnO3

    NASA Astrophysics Data System (ADS)

    Park, Chulkwon; Kim, Useong; Kim, Young Mo; Ju, Chanjong; Char, Kookrin

    2015-03-01

    Recently, BaSnO3 (BSO) has attracted attentions as a transparent conducting oxide and/or a transparent oxide semiconductor due to its novel properties: the excellent oxygen stability even at high temperature and the high electrical mobility at room temperature. We fabricated field effect transistors using La-doped BSO as the semiconducting channel on undoped BSO buffer layers on SrTiO3 substrates. A non-polar perovskite BaHfO3 was used as the gate insulator, and 4% La-doped BSO as the source, the drain, and the gate electrodes grown by pulsed laser deposition. We have measured the optical and the dielectric properties of the epitaxial BaHfO3 gate oxide layer, namely the optical band gap, the dielectric constant, and the breakdown field. Using such BaHfO3 gate oxide, we observed carrier modulation in the active layer by field effect. In this presentation, we will report on the performance of such field effect transistors: the output and the transfer characteristics, the field effect mobility, the Ion/Ioff ratio, and the subthreshold swing.

  3. Aqueous combustion synthesis of aluminum oxide thin films and application as gate dielectric in GZTO solution-based TFTs.

    PubMed

    Branquinho, Rita; Salgueiro, Daniela; Santos, Lídia; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

    2014-11-26

    Solution processing has been recently considered as an option when trying to reduce the costs associated with deposition under vacuum. In this context, most of the research efforts have been centered in the development of the semiconductors processes nevertheless the development of the most suitable dielectrics for oxide based transistors is as relevant as the semiconductor layer itself. In this work we explore the solution combustion synthesis and report on a completely new and green route for the preparation of amorphous aluminum oxide thin films; introducing water as solvent. Optimized dielectric layers were obtained for a water based precursor solution with 0.1 M concentration and demonstrated high capacitance, 625 nF cm(-2) at 10 kHz, and a permittivity of 7.1. These thin films were successfully applied as gate dielectric in solution processed gallium-zinc-tin oxide (GZTO) thin film transistors (TFTs) yielding good electrical performance such as subthreshold slope of about 0.3 V dec(-1) and mobility above 1.3 cm2 V(-1) s(-1). PMID:25354332

  4. Solution processed lanthanum aluminate gate dielectrics for use in metal oxide-based thin film transistors

    SciTech Connect

    Esro, M.; Adamopoulos, G.; Mazzocco, R.; Kolosov, O.; Krier, A.; Vourlias, G.; Milne, W. I.

    2015-05-18

    We report on ZnO-based thin-film transistors (TFTs) employing lanthanum aluminate gate dielectrics (La{sub x}Al{sub 1−x}O{sub y}) grown by spray pyrolysis in ambient atmosphere at 440 °C. The structural, electronic, optical, morphological, and electrical properties of the La{sub x}Al{sub 1−x}O{sub y} films and devices as a function of the lanthanum to aluminium atomic ratio were investigated using a wide range of characterization techniques such as UV-visible absorption spectroscopy, impedance spectroscopy, spectroscopic ellipsometry, atomic force microscopy, x-ray diffraction, and field-effect measurements. As-deposited LaAlO{sub y} dielectrics exhibit a wide band gap (∼6.18 eV), high dielectric constant (k ∼ 16), low roughness (∼1.9 nm), and very low leakage currents (<3 nA/cm{sup 2}). TFTs employing solution processed LaAlO{sub y} gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with hysteresis-free operation, low operation voltages (∼10 V), high on/off current modulation ratio of >10{sup 6}, subthreshold swing of ∼650 mV dec{sup −1}, and electron mobility of ∼12 cm{sup 2} V{sup −1} s{sup −1}.

  5. Solution processed lanthanum aluminate gate dielectrics for use in metal oxide-based thin film transistors

    NASA Astrophysics Data System (ADS)

    Esro, M.; Mazzocco, R.; Vourlias, G.; Kolosov, O.; Krier, A.; Milne, W. I.; Adamopoulos, G.

    2015-05-01

    We report on ZnO-based thin-film transistors (TFTs) employing lanthanum aluminate gate dielectrics (LaxAl1-xOy) grown by spray pyrolysis in ambient atmosphere at 440 °C. The structural, electronic, optical, morphological, and electrical properties of the LaxAl1-xOy films and devices as a function of the lanthanum to aluminium atomic ratio were investigated using a wide range of characterization techniques such as UV-visible absorption spectroscopy, impedance spectroscopy, spectroscopic ellipsometry, atomic force microscopy, x-ray diffraction, and field-effect measurements. As-deposited LaAlOy dielectrics exhibit a wide band gap (˜6.18 eV), high dielectric constant (k ˜ 16), low roughness (˜1.9 nm), and very low leakage currents (<3 nA/cm2). TFTs employing solution processed LaAlOy gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with hysteresis-free operation, low operation voltages (˜10 V), high on/off current modulation ratio of >106, subthreshold swing of ˜650 mV dec-1, and electron mobility of ˜12 cm2 V-1 s-1.

  6. Reliability and fatigue failure modes of implant-supported aluminum-oxide fixed dental prostheses

    PubMed Central

    Stappert, Christian F. J.; Baldassarri, Marta; Zhang, Yu; Hänssler, Felix; Rekow, Elizabeth D.; Thompson, Van P.

    2012-01-01

    Objectives To investigate failure modes and reliability of implant-supported aluminum-oxide three-unit fixed-dental-prostheses (FDPs) using two different veneering porcelains. Material and methods Thirty-six aluminum-oxide FDP-frameworks were CAD/CAM fabricated and either hand-veneered(n=18) or over-pressed(n=18). All FDPs were adhesively luted to custom-made zirconium-oxide-abutments attached to dental implant fixtures (RP-4×13mm). Specimens were stored in water prior to mechanical testing. A Step-Stress-Accelerated-Life-Test (SSALT) with three load/cycles varying profiles was developed based on initial single-load-to-failure testing. Failure was defined by veneer chipping or chipping in combination with framework fracture. SSALT was performed on each FDP inclined 30° with respect to the applied load direction. For all specimens, failure modes were analyzed using polarized-reflected-light-microscopy and scanning-electron-microscopy (SEM). Reliability was computed using Weibull analysis software (Reliasoft). Results The dominant failure mode for the over-pressed FDPs was buccal chipping of the porcelain in the loading area of the pontic, while hand-veneered specimens failed mainly by combined failure modes in the veneering porcelain, framework and abutments. Chipping of the porcelain occurred earlier in the over-pressed specimens (350 N/85k, load/cycles) than in the hand-veneered (600 N/110k)(profile I). Given a mission at 300 N load and 100k or 200 K cycles the computed Weibull reliability (2-sided at 90.0 % confidence bounds) was 0.99(1/0.98) and 0.99(1/0.98) for hand-veneered FDPs, and 0.45(0.76/0.10) and 0.05(0.63/0) for over-pressed FDPs, respectively. Conclusions In the range of average clinical loads (300–700 N), hand-veneered aluminum-oxide FDPs showed significantly less failure by chipping of the veneer than the over-pressed. Hand-veneered FDPs under fatigue loading failed at loads ≥ 600N. PMID:22093019

  7. The Integration of Sub-10 nm Gate Oxide on MoS2 with Ultra Low Leakage and Enhanced Mobility

    PubMed Central

    Yang, Wen; Sun, Qing-Qing; Geng, Yang; Chen, Lin; Zhou, Peng; Ding, Shi-Jin; Zhang, David Wei

    2015-01-01

    The integration of ultra-thin gate oxide, especially at sub-10 nm region, is one of the principle problems in MoS2 based transistors. In this work, we demonstrate sub-10 nm uniform deposition of Al2O3 on MoS2 basal plane by applying ultra-low energy remote oxygen plasma pretreatment prior to atomic layer deposition. It is demonstrated that oxygen species in ultra-low energy plasma are physically adsorbed on MoS2 surfaces without making the flakes oxidized, and is capable of benefiting the mobility of MoS2 flake. Based on this method, top-gated MoS2 transistor with ultrathin Al2O3 dielectric is fabricated. With 6.6 nm Al2O3 as gate dielectric, the device shows gate leakage about 0.1 pA/μm2 at 4.5 MV/cm which is much lower than previous reports. Besides, the top-gated device shows great on/off ratio of over 108, subthreshold swing (SS) of 101 mV/dec and a mobility of 28 cm2/Vs. With further investigations and careful optimizations, this method can play an important role in future nanoelectronics. PMID:26146017

  8. Reliability in Short-Channel p-Type Polycrystalline Silicon Thin-Film Transistor under High Gate and Drain Bias Stress

    NASA Astrophysics Data System (ADS)

    Choi, Sung-Hwan; Kim, Sun-Jae; Mo, Yeon-Gon; Kim, Hye-Dong; Han, Min-Koo

    2010-03-01

    We have investigated the electrical characteristics of short-channel p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under high gate and drain bias stress. We found that the threshold voltage of short-channel TFTs was significantly shifted in the negative direction owing to high gate and drain bias stress (ΔVTH = -2.08 V), whereas that of long-channel TFTs was rarely shifted in the negative direction (ΔVTH = -0.10 V). This negative shift of threshold voltage in the short-channel TFT may be attributed to interface state generation near the source junction and deep trap state creation near the drain junction between the poly-Si film and the gate insulator layer. It was also found that the gate-to-drain capacitance (CGD) characteristic of the stressed TFT severely stretched for the gate voltage below the flat band voltage VFB. The effects of high gate and drain bias stress are related to hot-hole-induced donor like interface state generation. The transfer characteristics of the forward and reverse modes after the high gate and drain bias stress also indicate that the interface state generation at the gate insulator/channel interface occurred near the source junction region.

  9. Reliability in Short-Channel p-Type Polycrystalline Silicon Thin-Film Transistor under High Gate and Drain Bias Stress

    NASA Astrophysics Data System (ADS)

    Sung-Hwan Choi,; Sun-Jae Kim,; Yeon-Gon Mo,; Hye-Dong Kim,; Min-Koo Han,

    2010-03-01

    We have investigated the electrical characteristics of short-channel p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under high gate and drain bias stress. We found that the threshold voltage of short-channel TFTs was significantly shifted in the negative direction owing to high gate and drain bias stress (Δ VTH = -2.08 V), whereas that of long-channel TFTs was rarely shifted in the negative direction (Δ VTH = -0.10 V). This negative shift of threshold voltage in the short-channel TFT may be attributed to interface state generation near the source junction and deep trap state creation near the drain junction between the poly-Si film and the gate insulator layer. It was also found that the gate-to-drain capacitance (CGD) characteristic of the stressed TFT severely stretched for the gate voltage below the flat band voltage VFB. The effects of high gate and drain bias stress are related to hot-hole-induced donor like interface state generation. The transfer characteristics of the forward and reverse modes after the high gate and drain bias stress also indicate that the interface state generation at the gate insulator/channel interface occurred near the source junction region.

  10. Highly Conductive and Reliable Copper-Filled Isotropically Conductive Adhesives Using Organic Acids for Oxidation Prevention

    NASA Astrophysics Data System (ADS)

    Chen, Wenjun; Deng, Dunying; Cheng, Yuanrong; Xiao, Fei

    2015-07-01

    The easy oxidation of copper is one critical obstacle to high-performance copper-filled isotropically conductive adhesives (ICAs). In this paper, a facile method to prepare highly reliable, highly conductive, and low-cost ICAs is reported. The copper fillers were treated by organic acids for oxidation prevention. Compared with ICA filled with untreated copper flakes, the ICA filled with copper flakes treated by different organic acids exhibited much lower bulk resistivity. The lowest bulk resistivity achieved was 4.5 × 10-5 Ω cm, which is comparable to that of commercially available Ag-filled ICA. After 500 h of 85°C/85% relative humidity (RH) aging, the treated ICAs showed quite stable bulk resistivity and relatively stable contact resistance. Through analyzing the results of x-ray diffraction, x-ray photoelectron spectroscopy, and thermogravimetric analysis, we found that, with the assistance of organic acids, the treated copper flakes exhibited resistance to oxidation, thus guaranteeing good performance.

  11. Reliability of potassium ion electret in silicon oxide for vibrational energy harvester applications

    NASA Astrophysics Data System (ADS)

    Misawa, Kensuke; Sugiyama, Tatsuhiko; Hashiguchi, Gen; Toshiyoshi, Hiroshi

    2015-06-01

    In this paper, we report on the long-term reliability of potassium ion electret included in a thermally grown silicon oxide. The electret in this work is used in a microelectromechanical systems (MEMS) energy harvester to generate electrical current from mechanical vibration. A spring-mass system similar to a comb-drive electrostatic actuator is developed by silicon micromachining, and the surface is oxidized by wet-oxidation through a potassium hydroxide bubbler, thereby including potassium atoms at a high concentration. The potassium is then electrically polarized by an applied voltage of 150 V at 650 °C for 5 min. Degradation of the stored polarization potential is monitored in a vacuum of 1 × 10-3 Pa at elevated temperatures of 350, 400, and 450 °C. The time needed to cause a -1 dB decay of the potential is used as the lifetime of the electret, and the Arrhenius extrapolation plot suggested a life time of more than 400 years at 25 °C.

  12. Oxygen Defect-Induced Metastability in Oxide Semiconductors Probed by Gate Pulse Spectroscopy

    PubMed Central

    Lee, Sungsik; Nathan, Arokia; Jeon, Sanghun; Robertson, John

    2015-01-01

    We investigate instability mechanisms in amorphous In-Ga-Zn-O transistors based on bias and illumination stress-recovery experiments coupled with analysis using stretched exponentials and inverse Laplace transform to retrieve the distribution of activation energies associated with metastable oxygen defects. Results show that the recovery process after illumination stress is persistently slow by virtue of defect states with a broad range, 0.85 eV to 1.38 eV, suggesting the presence of ionized oxygen vacancies and interstitials. We also rule out charge trapping/detrapping events since this requires a much smaller activation energy ~0.53 eV, and which tends to be much quicker. These arguments are supported by measurements using a novel gate-pulse spectroscopy probing technique that reveals the post-stress ionized oxygen defect profile, including anti-bonding states within the conduction band. PMID:26446400

  13. A hot oxidant, 3-NO2Y122 radical, unmasks conformational gating in ribonucleotide reductase

    PubMed Central

    Yokoyama, Kenichi; Uhlin, Ulla; Stubbe, JoAnne

    2010-01-01

    Escherichia coli ribonucleotide reductase is an α2β2 complex that catalyzes the conversion of nucleotides to deoxynucleotides and requires a diferric-tyrosyl radical (Y•) cofactor to initiate catalysis. The initiation process requires long range proton-coupled electron transfer (PCET) over 35 Å between the two subunits by a specific pathway (Y122• → W48 → Y356 within β to Y731 → Y730 → C439 within α). The rate-limiting step in nucleotide reduction is the conformational gating of the PCET process, which masks the chemistry of radical propagation. 3-Nitrotyrosine (NO2Y) has recently been incorporated site-specifically in place of Y122 in β2. The protein as isolated contained a diferric cluster, but no nitrotyrosyl radical (NO2Y•) and was inactive. In the present paper we show that incubation of apo-Y122NO2Y-β2 with Fe2+ and O2 generates a diferric-NO2Y• that has a half-life of 40 s at 25 °C. Sequential mixing experiments, in which the cofactor is assembled to 1.2 NO2Y•/β2 and then mixed with α2, CDP, and ATP, have been analyzed by stopped flow spectroscopy, rapid freeze quench EPR spectroscopy and rapid chemical quench methods. These studies have for the first time unmasked the conformational gating. They reveal that the NO2Y• is reduced to the nitrotyrosinate with biphasic kinetics (283 and 67 s-1), that dCDP is produced at 107 s-1, and that a new Y• is produced at 97 s-1. Studies with pathway mutants suggest that the new Y• is predominantly located at 356 in β2. In conjunction with the crystal structure of Y122NO2Y-β2, a mechanism for PCET uncoupling in NO2Y•-RNR is proposed. PMID:20929229

  14. Oxidation of Phe454 in the Gating Segment Inactivates Trametes multicolor Pyranose Oxidase during Substrate Turnover

    PubMed Central

    Volc, Jindrich; Peterbauer, Clemens K.; Leitner, Christian; Haltrich, Dietmar

    2016-01-01

    The flavin-dependent enzyme pyranose oxidase catalyses the oxidation of several pyranose sugars at position C-2. In a second reaction step, oxygen is reduced to hydrogen peroxide. POx is of interest for biocatalytic carbohydrate oxidations, yet it was found that the enzyme is rapidly inactivated under turnover conditions. We studied pyranose oxidase from Trametes multicolor (TmPOx) inactivated either during glucose oxidation or by exogenous hydrogen peroxide using mass spectrometry. MALDI-MS experiments of proteolytic fragments of inactivated TmPOx showed several peptides with a mass increase of 16 or 32 Da indicating oxidation of certain amino acids. Most of these fragments contain at least one methionine residue, which most likely is oxidised by hydrogen peroxide. One peptide fragment that did not contain any amino acid residue that is likely to be oxidised by hydrogen peroxide (DAFSYGAVQQSIDSR) was studied in detail by LC-ESI-MS/MS, which showed a +16 Da mass increase for Phe454. We propose that oxidation of Phe454, which is located at the flexible active-site loop of TmPOx, is the first and main step in the inactivation of TmPOx by hydrogen peroxide. Oxidation of methionine residues might then further contribute to the complete inactivation of the enzyme. PMID:26828796

  15. Design and control of Ge-based metal-oxide-semiconductor interfaces for high-mobility field-effect transistors with ultrathin oxynitride gate dielectrics

    NASA Astrophysics Data System (ADS)

    Minoura, Yuya; Kasuya, Atsushi; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2013-07-01

    High-quality Ge-based metal-oxide-semiconductor (MOS) stacks were achieved with ultrathin oxynitride (GeON) gate dielectrics. An in situ process based on plasma nitridation of the base germanium oxide (GeO2) surface and subsequent metal electrode deposition was proven to be effective for suppressing electrical deterioration induced by the reaction at the metal/insulator interface. The electrical properties of the bottom GeON/Ge interface were further improved by both low-temperature oxidation for base GeO2 formation and high-temperature in situ vacuum annealing after plasma nitridation of the base oxide. Based on the optimized in situ gate stack fabrication process, very high inversion carrier mobility (μhole: 445 cm2/Vs, μelectron: 1114 cm2/Vs) was demonstrated for p- and n-channel Ge MOSFETs with Al/GeON/Ge gate stacks at scaled equivalent oxide thickness down to 1.4 nm.

  16. Phospho-silicate glass gated 4H-SiC metal-oxide-semiconductor devices: Phosphorus concentration dependence

    NASA Astrophysics Data System (ADS)

    Jiao, C.; Ahyi, A. C.; Xu, C.; Morisette, D.; Feldman, L. C.; Dhar, S.

    2016-04-01

    The correlation between phosphorus concentration in phospho-silicate glass (PSG) gate dielectrics and electrical properties of 4H-SiC MOS devices has been investigated. Varying P uptake in PSG is achieved by changing the POCl3 post-oxidation annealing temperature. The density of interface traps (Dit) at the PSG/4H-SiC interface decreases as the amount of interfacial P increases. Most significantly, the MOSFET channel mobility does not correlate with Dit for all samples, which is highly unusual for SiC MOSFETs. Further analysis reveals two types of field-effect mobility (μfe) behavior, depending on the annealing temperature. Annealing at 1000 °C improves the channel mobility most effectively, with a peak value ˜105 cm2 V-1 s-1, and results in a surface phonon scattering limited mobility at high oxide field. On the other hand, PSG annealed at other temperatures results in a surface roughness scattering limited mobility at similar field.

  17. A hot oxidant, 3-NO2Y122 radical, unmasks conformational gating in ribonucleotide reductase.

    PubMed

    Yokoyama, Kenichi; Uhlin, Ulla; Stubbe, JoAnne

    2010-11-01

    Escherichia coli ribonucleotide reductase is an α2β2 complex that catalyzes the conversion of nucleotides to deoxynucleotides and requires a diferric-tyrosyl radical (Y(•)) cofactor to initiate catalysis. The initiation process requires long-range proton-coupled electron transfer (PCET) over 35 Å between the two subunits by a specific pathway (Y(122)(•)→W(48)→Y(356) within β to Y(731)→Y(730)→C(439) within α). The rate-limiting step in nucleotide reduction is the conformational gating of the PCET process, which masks the chemistry of radical propagation. 3-Nitrotyrosine (NO(2)Y) has recently been incorporated site-specifically in place of Y(122) in β2. The protein as isolated contained a diferric cluster but no nitrotyrosyl radical (NO(2)Y(•)) and was inactive. In the present paper we show that incubation of apo-Y(122)NO(2)Y-β2 with Fe(2+) and O(2) generates a diferric-NO(2)Y(•) that has a half-life of 40 s at 25 °C. Sequential mixing experiments, in which the cofactor is assembled to 1.2 NO(2)Y(•)/β2 and then mixed with α2, CDP, and ATP, have been analyzed by stopped-flow absorption spectroscopy, rapid freeze quench EPR spectroscopy, and rapid chemical quench methods. These studies have, for the first time, unmasked the conformational gating. They reveal that the NO(2)Y(•) is reduced to the nitrotyrosinate with biphasic kinetics (283 and 67 s(-1)), that dCDP is produced at 107 s(-1), and that a new Y(•) is produced at 97 s(-1). Studies with pathway mutants suggest that the new Y(•) is predominantly located at 356 in β2. In consideration of these data and the crystal structure of Y(122)NO(2)Y-β2, a mechanism for PCET uncoupling in NO(2)Y(•)-RNR is proposed. PMID:20929229

  18. Bulk and interface trapping in the gate dielectric of GaN based metal-oxide-semiconductor high-electron-mobility transistors

    NASA Astrophysics Data System (ADS)

    Ťapajna, M.; Jurkovič, M.; Válik, L.; Haščík, Š.; Gregušová, D.; Brunner, F.; Cho, E.-M.; Kuzmík, J.

    2013-06-01

    The trapping phenomena in GaN metal-oxide-semiconductor high-electron mobility transistor structures with 10 and 20-nm thick Al2O3 gate dielectric grown by metal-organic chemical vapor deposition were deeply investigated using comprehensive capacitance-voltage measurements. By controlling the interface traps population, substantial electron trapping in the dielectric bulk was identified. Separation between the trapping process and the interface traps emission allowed us to determine distribution of interface trap density in a wide energy range. Temperature dependence of the trapping process indicates thermionic field emission of electrons from the gate into traps with a sheet density of ~1013 cm-2, located a few nm below the gate.

  19. Bulk and interface trapping in the gate dielectric of GaN based metal-oxide-semiconductor high-electron-mobility transistors

    NASA Astrophysics Data System (ADS)

    Ťapajna, M.; Jurkovič, M.; Válik, L.; Haščík, Š.; Gregušová, D.; Brunner, F.; Cho, E.-M.; Kuzmík, J.

    2013-06-01

    The trapping phenomena in GaN metal-oxide-semiconductor high-electron mobility transistor structures with 10 and 20-nm thick Al2O3 gate dielectric grown by metal-organic chemical vapor deposition were deeply investigated using comprehensive capacitance-voltage measurements. By controlling the interface traps population, substantial electron trapping in the dielectric bulk was identified. Separation between the trapping process and the interface traps emission allowed us to determine distribution of interface trap density in a wide energy range. Temperature dependence of the trapping process indicates thermionic field emission of electrons from the gate into traps with a sheet density of ˜1013 cm-2, located a few nm below the gate.

  20. The Impacts of Contact Etch Stop Layer Thickness and Gate Height on Channel Stress in Strained N-Metal Oxide Semiconductor Field Effect Transistors.

    PubMed

    Lin, K C; Twu, M J; Deng, R H; Liu, C H

    2015-04-01

    The stress induced by strain in the channel of metal oxide semiconductor field effect transistors (MOSFET) is an effective method to boost the device performance. The geometric dimensions of spacer, gate height, and the contact etch stop layer (CESL) are important factors among the feasible booster. This study utilized the mismatch of the thermal expansion coefficients of stressors to simulate the process-induced stress in the N-MOSFET. Different temperatures are applied to different region of the device to generate the required strain. The analysis was performed by well-developed finite element package. The composite spacers with variant width of inserted silicon nitride (SiO2/SiN/SiO2, ONO) were proposed and their impacts on channel stress were compared. Two aspects of the impacts of those factors on the channel stress in the longitudinal direction for N-MOSFET with variant channel length were investigated. Firstly, the channel stresses of device without CESL for different gate heights were studied. Secondly, with stress applied to CESL and ONO spacers, the induced stresses in the channel were analyzed for long/short gate length. Two conclusions were drawn from the results of simulation. The N-MOSFET device without CESL shows that the stressed spacer alone generates compressive stress and the magnitude increases along with higher gate height. The channel stress becomes tensile for device with CESL and increases when the thickness of CESL and the height of gate increase, especially for device with shorter gate length. The gate height plays more significant role in inducing channel stress compared with the thickness of CESL. The channel stress can be used to quantify the mobility of electron/hole for strained MOSFET device. Therefore, with the guideline disclosed in this study, better device performance can be expected for N-MOSFET. PMID:26353480

  1. The impact of implantation sequence on the characterization of n-MOSFET's with gate oxide grown on nitrogen-implanted Si substrate

    NASA Astrophysics Data System (ADS)

    Wu, You-Lin

    2002-08-01

    Both of the nitrogen implantation and threshold-voltage adjustment implantation introduce dopant atoms near the SiO 2/Si interface during the fabrication of n-channel metal-oxide-semiconductor field-effect transistor (n-MOSFET's) with gate oxide grown on nitrogen implanted silicon substrate. This work examined the impact of implantation sequence on the characterization of n-MOSFET's with gate oxide grown on nitrogen implanted silicon substrate. It is found that the sequence of nitrogen implantation and boron implantation affects both the electrical characteristics and hot-carrier properties of n-MOSFET's. It is found that no channel mobility degradation, less interface state density, lower subthreshold leakage current and better hot-carrier resistance can be achieved in the n-MOSFET's if the threshold-voltage adjustment implantation is performed after the nitrogen implantation during the gate oxide preparation. However lower channel mobility, higher interface state density, higher subthreshold leakage current and less hot-carrier resistance were observed if the implantation sequence was reversed.

  2. Near-IR squaraine dye–loaded gated periodic mesoporous organosilica for photo-oxidation of phenol in a continuous-flow device

    PubMed Central

    Borah, Parijat; Sreejith, Sivaramapanicker; Anees, Palapuravan; Menon, Nishanth Venugopal; Kang, Yuejun; Ajayaghosh, Ayyappanpillai; Zhao, Yanli

    2015-01-01

    Periodic mesoporous organosilica (PMO) has been widely used for the fabrication of a variety of catalytically active materials. We report the preparation of novel photo-responsive PMO with azobenzene-gated pores. Upon activation, the azobenzene gate undergoes trans-cis isomerization, which allows an unsymmetrical near-infrared squaraine dye (Sq) to enter into the pores. The gate closure by cis-trans isomerization of the azobenzene unit leads to the safe loading of the monomeric dye inside the pores. The dye-loaded and azobenzene-gated PMO (Sq-azo@PMO) exhibits excellent generation of reactive oxygen species upon excitation at 664 nm, which can be effectively used for the oxidation of phenol into benzoquinone in aqueous solution. Furthermore, Sq-azo@PMO as the catalyst was placed inside a custom-built, continuous-flow device to carry out the photo-oxidation of phenol to benzoquinone in the presence of 664-nm light. By using the device, about 23% production of benzoquinone with 100% selectivity was achieved. The current research presents a prototype of transforming heterogeneous catalysts toward practical use. PMID:26601266

  3. Near-IR squaraine dye-loaded gated periodic mesoporous organosilica for photo-oxidation of phenol in a continuous-flow device.

    PubMed

    Borah, Parijat; Sreejith, Sivaramapanicker; Anees, Palapuravan; Menon, Nishanth Venugopal; Kang, Yuejun; Ajayaghosh, Ayyappanpillai; Zhao, Yanli

    2015-09-01

    Periodic mesoporous organosilica (PMO) has been widely used for the fabrication of a variety of catalytically active materials. We report the preparation of novel photo-responsive PMO with azobenzene-gated pores. Upon activation, the azobenzene gate undergoes trans-cis isomerization, which allows an unsymmetrical near-infrared squaraine dye (Sq) to enter into the pores. The gate closure by cis-trans isomerization of the azobenzene unit leads to the safe loading of the monomeric dye inside the pores. The dye-loaded and azobenzene-gated PMO (Sq-azo@PMO) exhibits excellent generation of reactive oxygen species upon excitation at 664 nm, which can be effectively used for the oxidation of phenol into benzoquinone in aqueous solution. Furthermore, Sq-azo@PMO as the catalyst was placed inside a custom-built, continuous-flow device to carry out the photo-oxidation of phenol to benzoquinone in the presence of 664-nm light. By using the device, about 23% production of benzoquinone with 100% selectivity was achieved. The current research presents a prototype of transforming heterogeneous catalysts toward practical use. PMID:26601266

  4. Electrical Properties and Reliability Analysis of Solution-Processed Indium Tin Zinc Oxide Thin Film Transistors with O2-Plasma Treatment.

    PubMed

    Ko, Sun Wook; Kim, Soon Kon; Kim, Jong Min; Cho, Jae Hee; Park, Hyoung Sun; Choi, Byoung Deog

    2015-10-01

    In this paper, we report the effects of O2-plasma treatment on the reliability and electrical properties of indium tin zinc oxide (ITZO) films. Excellent electrical properties, including a saturation mobility (μsat) of ~20.2 cm2/V · s, a threshold voltage (VTH) of ~-6.8 V, a sub-threshold swing (S.S) of ~0.956 V/decade, and an on/off current ratio (ION/OFF) of ~10(5) can be found with a molarity of 0.4 M and ratio of In:Zn:Sn = 2:1:2. Following O2-plasma treatment, it was confirmed that the electrical properties of the ITZO films are improved when compared to the untreated films. The devices showed a decreased S.S of ~0.51 V/decade, while the VTH and ION/OFF tended to increase. To determine the reliability of a-ITZO TFTs, we analyzed the electrical characteristics according to gate bias stress, VG,stress = 10 V for 4000 s. Improved reliability was confirmed when compared with the variation in threshold voltage prior to O2-plasma treatment, most likely stemming from a smooth surface on the active layer as a result of O2-plasma treatment. We were able to obtain a solution a-ITZO film transmittance of 92% in the visible light region (400~700 nm). These results show that a-ITZO TFTs fabricated via solution process with optimized molar ratio exhibit good electrical properties. a-ITZO films fabricated via spin-coating are a visible alternative to those fabricated via high-cost sputtering methods, and are applicable in flexible and transparent electronics. PMID:26726354

  5. Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

    SciTech Connect

    Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A.

    2015-07-28

    Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

  6. Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

    NASA Astrophysics Data System (ADS)

    Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A.

    2015-07-01

    Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

  7. Modeling of n-InAs metal oxide semiconductor capacitors with high-κ gate dielectric

    NASA Astrophysics Data System (ADS)

    Babadi, A. S.; Lind, E.; Wernersson, L. E.

    2014-12-01

    A qualitative analysis on capacitance-voltage and conductance data for high-κ/InAs capacitors is presented. Our measured data were evaluated with a full equivalent circuit model, including both majority and minority carriers, as well as interface and border traps, formulated for narrow band gap metal-oxide-semiconductor capacitors. By careful determination of interface trap densities, distribution of border traps across the oxide thickness, and taking into account the bulk semiconductor response, it is shown that the trap response has a strong effect on the measured capacitances. Due to the narrow bandgap of InAs, there can be a large surface concentration of electrons and holes even in depletion, so a full charge treatment is necessary.

  8. Modeling of n-InAs metal oxide semiconductor capacitors with high-κ gate dielectric

    SciTech Connect

    Babadi, A. S. Lind, E.; Wernersson, L. E.

    2014-12-07

    A qualitative analysis on capacitance-voltage and conductance data for high-κ/InAs capacitors is presented. Our measured data were evaluated with a full equivalent circuit model, including both majority and minority carriers, as well as interface and border traps, formulated for narrow band gap metal-oxide-semiconductor capacitors. By careful determination of interface trap densities, distribution of border traps across the oxide thickness, and taking into account the bulk semiconductor response, it is shown that the trap response has a strong effect on the measured capacitances. Due to the narrow bandgap of InAs, there can be a large surface concentration of electrons and holes even in depletion, so a full charge treatment is necessary.

  9. Band alignment of vanadium oxide as an interlayer in a hafnium oxide-silicon gate stack structure

    NASA Astrophysics Data System (ADS)

    Zhu, Chiyu; Kaur, Manpuneet; Tang, Fu; Liu, Xin; Smith, David J.; Nemanich, Robert J.

    2012-10-01

    Vanadium oxide (VO2) is a narrow band gap material (Eg = 0.7 eV) with a thermally induced insulator-metal phase transition at ˜343 K and evidence of an electric field induced transition at T < 343 K. To explore the electronic properties of VO2, a sandwich structure was prepared with a 2 nm VO2 layer embedded between an oxidized Si(100) surface and a 2 nm hafnium oxide (HfO2) layer. The layer structure was confirmed with high resolution transmission electron microscopy. The electronic properties were characterized with x-ray and ultraviolet photoemission spectroscopy, and the band alignment was deduced on both n-type and p-type Si substrates. The valence band offset between VO2 and SiO2 is measured to be 4.0 eV. The valence band offset between HfO2 and VO2 is measured to be ˜3.4 eV. The band relation developed from these results demonstrates the potential for charge storage and switching for the embedded VO2 layer.

  10. Study of Novel Floating-Gate Oxide Semiconductor Memory Using Indium-Gallium-Zinc Oxide for Low-Power System-on-Panel Applications

    NASA Astrophysics Data System (ADS)

    Yamauchi, Yoshimitsu; Kamakura, Yoshinari; Isagi, Yousuke; Matsuoka, Toshimasa; Malotaux, Satoshi

    2013-09-01

    A novel floating-gate oxide semiconductor (FLOTOS) memory using a wide-band-gap indium-gallium-zinc oxide (IGZO) is presented for low-power system-on-panel applications. An IGZO thin-film-transistor (TFT) is used as a memory transistor for controlling read current as well as a switching transistor for storing charges in a storage capacitor (Cs). The FLOTOS memory is fabricated using a standard IGZO TFT process without any additional process or mask steps. The proposed precharge-assisted threshold voltage compensation technique makes it possible to realize an infinite number of write cycles and a low-power write operation with a bit-line voltage of 5 V. Furthermore, excellent data retention longer than 10 h is obtained at 60 °C even under the worst bias-stress condition of read operation with the ultra low off-state leakage (2.8×10-20 A/µm) of the IGZO TFTs, which is estimated to be smaller by more than 7 orders of magnitude than that of polycrystalline silicon TFTs.

  11. INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Quantum-Mechanical Study on Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Hu, Guang-Xi; Wang, Ling-Li; Liu, Ran; Tang, Ting-Ao; Qiu, Zhi-Jun

    2010-10-01

    As the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) scales into the nanometer regime, quantum mechanical effects are becoming more and more significant. In this work, a model for the surrounding-gate (SG) nMOSFET is developed. The Schrödinger equation is solved analytically. Some of the solutions are verified via results obtained from simulations. It is found that the percentage of the electrons with lighter conductivity mass increases as the silicon body radius decreases, or as the gate voltage reduces, or as the temperature decreases. The centroid of inversion-layer is driven away from the silicon-oxide interface towards the silicon body, therefore the carriers will suffer less scattering from the interface and the electrons effective mobility of the SG nMOSFETs will be enhanced.

  12. The effect of post oxide deposition annealing on the effective work function in metal/Al{sub 2}O{sub 3}/InGaAs gate stack

    SciTech Connect

    Winter, R.; Krylov, I.; Eizenberg, M.; Ahn, J.; McIntyre, P. C.

    2014-05-19

    The effect of post oxide deposition annealing on the effective work function in metal/Al{sub 2}O{sub 3}/ InGaAs gate stacks was investigated. Using a systematic method for effective work function extraction, a shift of 0.3 ± 0.1 eV was found between the effective work function of forming gas annealed samples and vacuum annealed samples. The electrical measurements enabled us to obtain the band alignment of the metal/Al{sub 2}O{sub 3}/InGaAs gate stack. This band alignment was confirmed by X-ray photoelectron spectroscopy. The measured shift in the effective work function between different annealing ambient may be attributed to indium out-diffusion during post oxide deposition annealing that is observed in forming gas anneal to a much larger extent than in vacuum.

  13. Quantum Mechanical Effects on the Threshold Voltage of Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Hu, Guang-Xi; Liu, Ran; Qiu, Zhi-Jun; Wang, Ling-Li; Tang, Ting-Ao

    2010-03-01

    A model for a metal-oxide-semiconductor field-effect transistor (MOSFET) with a double gate (DG) is developed. Quantum mechanical effects on the threshold voltage (VTH) are modeled and investigated analytically. The analytic model shows how VTH is increased with quantum mechanical effect. The model is applicable to both symmetric DG (SDG) and asymmetric DG (ADG) nMOSFETs, and is also applicable to both doped and undoped DG nMOSFETs. The analytic results are verified by comparing with the results obtained from simulations using Schred, and good agreement is observed. The VTH of an ADG nMOSFET will shift more than that of an SDG nMOSFET, and the VTH of a DG transistor with (110)-silicon (Si) orientation will shift more than that of a DG transistor with (100)-Si orientation. When the silicon thickness tsi < 3 nm, the VTH shift will be significant, and one should be careful in the use of an extremely thin silicon body. When the body doping density (NA) is not high (<1018 cm-3), the VTH shift is almost the same for different NA. When NA > 1018 cm-3, the higher the NA, the more the VTH shift.

  14. Theoretical Study of Triboelectric-Potential Gated/Driven Metal-Oxide-Semiconductor Field-Effect Transistor.

    PubMed

    Peng, Wenbo; Yu, Ruomeng; He, Yongning; Wang, Zhong Lin

    2016-04-26

    Triboelectric nanogenerator has drawn considerable attentions as a potential candidate for harvesting mechanical energies in our daily life. By utilizing the triboelectric potential generated through the coupling of contact electrification and electrostatic induction, the "tribotronics" has been introduced to tune/control the charge carrier transport behavior of silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET). Here, we perform a theoretical study of the performances of tribotronic MOSFET gated by triboelectric potential in two working modes through finite element analysis. The drain-source current dependence on contact-electrification generated triboelectric charges, gap separation distance, and externally applied bias are investigated. The in-depth physical mechanism of the tribotronic MOSFET operations is thoroughly illustrated by calculating and analyzing the charge transfer process, voltage relationship to gap separation distance, and electric potential distribution. Moreover, a tribotronic MOSFET working concept is proposed, simulated and studied for performing self-powered FET and logic operations. This work provides a deep understanding of working mechanisms and design guidance of tribotronic MOSFET for potential applications in micro/nanoelectromechanical systems (MEMS/NEMS), human-machine interface, flexible electronics, and self-powered active sensors. PMID:27077327

  15. Effect of size and position of gold nanocrystals embedded in gate oxide of SiO2/Si MOS structures

    NASA Astrophysics Data System (ADS)

    Chakraborty, Chaitali; Bose, Chayanika

    2016-02-01

    The influence of single and double layered gold (Au) nanocrystals (NC), embedded in SiO2 matrix, on the electrical characteristics of metal-oxide-semiconductor (MOS) structures is reported in this communication. The size and position of the NCs are varied and study is made using Sentaurus TCAD simulation tools. In a single NC-layered MOS structure, the role of NCs is more prominent when they are placed closer to SiO2/Si‑substrate interface than to SiO2/Al-gate interface. In MOS structures with larger NC dots and double layered NCs, the charge storage capacity is increased due to charging of the dielectric in the presence of NCs. Higher breakdown voltage and smaller leakage current are also obtained in the case of dual NC-layered MOS device. A new phenomenon of smearing out of the capacitance-voltage curve is observed in the presence of dual NC layer indicating generation of interface traps. An internal electric field developed between these two charged NC layers is expected to generate such interface traps at the SiO2/Si interface.

  16. Reliability investigation of high-k/metal gate in nMOSFETs by three-dimensional kinetic Monte-Carlo simulation with multiple trap interactions

    NASA Astrophysics Data System (ADS)

    Li, Yun; Jiang, Hai; Lun, Zhiyuan; Wang, Yijiao; Huang, Peng; Hao, Hao; Du, Gang; Zhang, Xing; Liu, Xiaoyan

    2016-04-01

    Degradation behaviors in the high-k/metal gate stacks of nMOSFETs are investigated by three-dimensional (3D) kinetic Monte-Carlo (KMC) simulation with multiple trap coupling. Novel microscopic mechanisms are simultaneously considered in a compound system: (1) trapping/detrapping from/to substrate/gate; (2) trapping/detrapping to other traps; (3) trap generation and recombination. Interacting traps can contribute to random telegraph noise (RTN), bias temperature instability (BTI), and trap-assisted tunneling (TAT). Simulation results show that trap interaction induces higher probability and greater complexity in trapping/detrapping processes and greatly affects the characteristics of RTN and BTI. Different types of trap distribution cause largely different behaviors of RTN, BTI, and TAT. TAT currents caused by multiple trap coupling are sensitive to the gate voltage. Moreover, trap generation and recombination have great effects on the degradation of HfO2-based nMOSFETs under a large stress.

  17. The development of non-uniform deposition of holes in gate oxides

    SciTech Connect

    Freitag, R.K.; Dozier, C.M.; Brown, D.B.; Burke, E.A.

    1988-12-01

    The subthreshold technique was used to study irradiated MOS transistors at 80 K. Stretchout of the subthreshold curve demonstrated production of lateral non-uniformities (LNUs) in the hole distribution. The LNUs were analyzed in terms of (a) a parallel transistor model, and (b) the statistics of the non-uniform distribution of dose deposition in the SiO/sub 2/. The results confirm the hypothesis that at 80 K the principal source of LNUs is the granularity in dose deposition. The relative standard deviation for the deposited dose is larger for thin oxides, for 10 kev x-rays (as opposed to Co-60), and at low doses. These physical phenomena are predicted to have a significant effect at room temperature also.

  18. Enhanced Total Ionizing Dose Hardness of Deep Sub-Micron Partially Depleted Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Field Effect Transistors by Applying Larger Back-Gate Voltage Stress

    NASA Astrophysics Data System (ADS)

    Zheng, Qi-Wen; Cui, Jiang-Wei; Yu, Xue-Feng; Guo, Qi; Zhou, Hang; Ren, Di-Yuan

    2014-12-01

    The larger back-gate voltage stress is applied on 130 nm partially depleted silicon-on-insulator n-type metal-oxide-semiconductor field-effect transistors isolated by shallow trench isolation. The experimental results show that the back-gate sub-threshold hump of the device is eliminated by stress. This observed behavior is caused by the high electric field in the oxide near the bottom corner of the silicon island. The total ionizing dose hardness of devices with pre back-gate stress is enhanced by the interface states induced by stress.

  19. Role of PheE15 Gate in Ligand Entry and Nitric Oxide Detoxification Function of Mycobacterium tuberculosis Truncated Hemoglobin N

    PubMed Central

    Bidon-Chanal, Axel; Forti, Flavio; Martí, Marcelo A.; Boechi, Leonardo; Estrin, Dario A.; Dikshit, Kanak L.; Luque, F. Javier

    2012-01-01

    The truncated hemoglobin N, HbN, of Mycobacterium tuberculosis is endowed with a potent nitric oxide dioxygenase (NOD) activity that allows it to relieve nitrosative stress and enhance in vivo survival of its host. Despite its small size, the protein matrix of HbN hosts a two-branched tunnel, consisting of orthogonal short and long channels, that connects the heme active site to the protein surface. A novel dual-path mechanism has been suggested to drive migration of O2 and NO to the distal heme cavity. While oxygen migrates mainly by the short path, a ligand-induced conformational change regulates opening of the long tunnel branch for NO, via a phenylalanine (PheE15) residue that acts as a gate. Site-directed mutagenesis and molecular simulations have been used to examine the gating role played by PheE15 in modulating the NOD function of HbN. Mutants carrying replacement of PheE15 with alanine, isoleucine, tyrosine and tryptophan have similar O2/CO association kinetics, but display significant reduction in their NOD function. Molecular simulations substantiated that mutation at the PheE15 gate confers significant changes in the long tunnel, and therefore may affect the migration of ligands. These results support the pivotal role of PheE15 gate in modulating the diffusion of NO via the long tunnel branch in the oxygenated protein, and hence the NOD function of HbN. PMID:23145144

  20. Impacts of Ti on electrical properties of Ge metal-oxide-semiconductor capacitors with ultrathin high- k LaTiON gate dielectric

    NASA Astrophysics Data System (ADS)

    Xu, H. X.; Xu, J. P.; Li, C. X.; Chan, C. L.; Lai, P. T.

    2010-06-01

    Ge Metal-Oxide-Semiconductor (MOS) capacitors with LaON gate dielectric incorporating different Ti contents are fabricated and their electrical properties are measured and compared. It is found that Ti incorporation can increase the dielectric permittivity, and the higher the Ti content, the larger is the permittivity. However, the interfacial and gate-leakage properties become poorer as the Ti content increases. Therefore, optimization of Ti content is important in order to obtain a good trade-off among the electrical properties of the device. For the studied range of the Ti/La2O3 ratio, a suitable Ti/La2O3 ratio of 14.7% results in a high relative permittivity of 24.6, low interface-state density of 3.1×1011 eV-1 cm-2, and relatively low gate-leakage current density of 2.0×10-3 A cm-2 at a gate voltage of 1 V.

  1. Metal-Oxide-Semiconductor Field-Effect-Transistors Possessing Step Functional I-V Curves Caused by the Punch Through between Drain and Inversion Layer of the Gate

    NASA Astrophysics Data System (ADS)

    Karasawa, Shinji; Yamanouchi, Kazuhiko; Tachibana, Yukio

    1992-02-01

    Through measurements of an Al gate p-channel Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) with a gap between the gate and drain, the behavior of the minority carrier in the depletion layer is clarified. The turn-on drain voltage depends upon the length and the density of impurity on the punch-through area. That is, Vd{=}-4 V for Lgap{=}0.5 μm in 3˜5 Ω\\cdotcm n-Si wafer and Vd{=}-3 V for Lgap{=}2.0 μm in 120˜200 Ω\\cdotcm n-Si wafer. The abrupt step functional I-V curve is revealed under the condition of low gate voltage. There are surface effects by which the higher the gate voltage, the lower the turn-on voltage of the drain becomes. The hole mobility in the depletion layer made from lightly doped < 111> wafer abruptly decreases when the temperature is lowered to below 20 K and the turn-on voltage on the step function MOSFET increases remarkably at 4.2 K.

  2. Hole trapping in thermal oxides grown under various oxidation conditions using avalanche injection in poly-silicon gate structures

    NASA Astrophysics Data System (ADS)

    Anand, K. V.; Cairns, B. R.; Strain, R. J.

    1985-03-01

    I/v data (where I is the dc current and v is the maximum value of the ac applied voltage across the device) was analyzed with respect to the theory and it was shown that the hole temperature not only depends on the substrate doping density and the electric field as measured by the Delta V subscript FB is not only a characteristic of the way that an oxide is grown and annealed, but it also depends on the quality of the substrate and its detailed thermal history. This substrate effect shows itself in the I/v characteristic of a particular device. If the dc current Idc was kept constant at a particular level (as was the case for our experiments), then the v value would represent the temperature of the hot carriers. Since the evidence suggests that the hot carriers generate trap levels, then any change in carrier temperature would reflect in Delta V subscript FB. These substrate related effects were found to be significant.

  3. Chemical Bonding, Interfaces and Defects in Hafnium Oxide/Germanium Oxynitride Gate Stacks on Ge (100)

    SciTech Connect

    Oshima, Yasuhiro; Sun, Yun; Kuzum, Duygu; Sugawara, Takuya; Saraswat, Krishna C.; Pianetta, Piero; McIntyre, Paul C.; /Stanford U., Materials Sci. Dept.

    2008-10-31

    Correlations among interface properties and chemical bonding characteristics in HfO{sub 2}/GeO{sub x}N{sub y}/Ge MIS stacks were investigated using in-situ remote nitridation of the Ge (100) surface prior to HfO{sub 2} atomic layer deposition (ALD). Ultra thin ({approx}1.1 nm), thermally stable and aqueous etch-resistant GeO{sub x}N{sub y} interfaces layers that exhibited Ge core level photoelectron spectra (PES) similar to stoichiometric Ge{sub 3}N{sub 4} were synthesized. To evaluate GeO{sub x}N{sub y}/Ge interface defects, the density of interface states (D{sub it}) was extracted by the conductance method across the band gap. Forming gas annealed (FGA) samples exhibited substantially lower D{sub it} ({approx} 1 x 10{sup 12} cm{sup -2} eV{sup -1}) than did high vacuum annealed (HVA) and inert gas anneal (IGA) samples ({approx} 1x 10{sup 13} cm{sup -2} eV{sup -1}). Germanium core level photoelectron spectra from similar FGA-treated samples detected out-diffusion of germanium oxide to the HfO{sub 2} film surface and apparent modification of chemical bonding at the GeO{sub x}N{sub y}/Ge interface, which is related to the reduced D{sub it}.

  4. Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating

    PubMed Central

    Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S.; Takeuchi, Ichiro; Greene, Richard. L.

    2016-01-01

    The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2−xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of −2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected. PMID:27221198

  5. Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating

    NASA Astrophysics Data System (ADS)

    Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S.; Takeuchi, Ichiro; Greene, Richard. L.

    2016-05-01

    The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2‑xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of ‑2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected.

  6. Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating.

    PubMed

    Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S; Takeuchi, Ichiro; Greene, Richard L

    2016-01-01

    The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2-xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of -2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected. PMID:27221198

  7. Universal Superreplication of Unitary Gates

    NASA Astrophysics Data System (ADS)

    Chiribella, G.; Yang, Y.; Huang, C.

    2015-03-01

    Quantum states obey an asymptotic no-cloning theorem, stating that no deterministic machine can reliably replicate generic sequences of identically prepared pure states. In stark contrast, we show that generic sequences of unitary gates can be replicated deterministically at nearly quadratic rates, with an error vanishing on most inputs except for an exponentially small fraction. The result is not in contradiction with the no-cloning theorem, since the impossibility of deterministically transforming pure states into unitary gates prevents the application of the gate replication protocol to states. In addition to gate replication, we show that N parallel uses of a completely unknown unitary gate can be compressed into a single gate acting on O (log2N ) qubits, leading to an exponential reduction of the amount of quantum communication needed to implement the gate remotely.

  8. Universal superreplication of unitary gates.

    PubMed

    Chiribella, G; Yang, Y; Huang, C

    2015-03-27

    Quantum states obey an asymptotic no-cloning theorem, stating that no deterministic machine can reliably replicate generic sequences of identically prepared pure states. In stark contrast, we show that generic sequences of unitary gates can be replicated deterministically at nearly quadratic rates, with an error vanishing on most inputs except for an exponentially small fraction. The result is not in contradiction with the no-cloning theorem, since the impossibility of deterministically transforming pure states into unitary gates prevents the application of the gate replication protocol to states. In addition to gate replication, we show that N parallel uses of a completely unknown unitary gate can be compressed into a single gate acting on O(log_{2}N) qubits, leading to an exponential reduction of the amount of quantum communication needed to implement the gate remotely. PMID:25860728

  9. Effect of proton irradiation dose on InAlN/GaN metal-oxide semiconductor high electron mobility transistors with Al2O3 gate oxide

    DOE PAGESBeta

    Ahn, Shihyun; Kim, Byung -Jae; Lin, Yi -Hsuan; Ren, Fan; Pearton, Stephen J.; Yang, Gwangseok; Kim, Jihyun; Kravchenko, Ivan I.

    2016-07-26

    The effects of proton irradiation on the dc performance of InAlN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) with Al2O3 as the gate oxide were investigated. The InAlN/GaN MOSHEMTs were irradiated with doses ranging from 1×1013 to 1×1015cm–2 at a fixed energy of 5MeV. There was minimal damage induced in the two dimensional electron gas at the lowest irradiation dose with no measurable increase in sheet resistance, whereas a 9.7% increase of the sheet resistance was observed at the highest irradiation dose. By sharp contrast, all irradiation doses created more severe degradation in the Ohmic metal contacts, with increases of specificmore » contact resistance from 54% to 114% over the range of doses investigated. These resulted in source-drain current–voltage decreases ranging from 96 to 242 mA/mm over this dose range. The trap density determined from temperature dependent drain current subthreshold swing measurements increased from 1.6 × 1013 cm–2 V–1 for the reference MOSHEMTs to 6.7 × 1013 cm–2 V–1 for devices irradiated with the highest dose. In conclusion, the carrier removal rate was 1287 ± 64 cm–1, higher than the authors previously observed in AlGaN/GaN MOSHEMTs for the same proton energy and consistent with the lower average bond energy of the InAlN.« less

  10. Near interface traps in SiO2/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

    NASA Astrophysics Data System (ADS)

    Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena; Roccaforte, Fabrizio

    2016-07-01

    This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO2/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in "gate-controlled-diode" configuration. The measurements revealed an anomalous non-steady conduction under negative bias (VG > |20 V|) through the SiO2/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (Ntrap ˜ 2 × 1011 cm-2).

  11. High mobility field effect transistor based on BaSnO{sub 3} with Al{sub 2}O{sub 3} gate oxide

    SciTech Connect

    Park, Chulkwon; Kim, Useong; Ju, Chan Jong; Park, Ji Sung; Kim, Young Mo; Char, Kookrin

    2014-11-17

    We fabricated an n-type accumulation-mode field effect transistor based on BaSnO{sub 3} transparent perovskite semiconductor, taking advantage of its high mobility and oxygen stability. We used the conventional metal-insulator-semiconductor structures: (In,Sn){sub 2}O{sub 3} as the source, drain, and gate electrodes, Al{sub 2}O{sub 3} as the gate insulator, and La-doped BaSnO{sub 3} as the semiconducting channel. The Al{sub 2}O{sub 3} gate oxide was deposited by atomic layer deposition technique. At room temperature, we achieved the field effect mobility value of 17.8 cm{sup 2}/Vs and the I{sub on}/I{sub off} ratio value higher than 10{sup 5} for V{sub DS} = 1 V. These values are higher than those previously reported on other perovskite oxides, in spite of the large density of threading dislocations in the BaSnO{sub 3} on SrTiO{sub 3} substrates. However, a relatively large subthreshold swing value was found, which we attribute to the large density of charge traps in the Al{sub 2}O{sub 3} as well as the threading dislocations.

  12. Gate protective device for insulated gate field-effect transistors

    NASA Technical Reports Server (NTRS)

    Sunshine, R. A.

    1972-01-01

    Device, which protects insulated gate field-effect transistors, improves reliability through utilization of layers of conductive material on top of each alternating semiconductor material region. Separation of layers is necessary to prevent shorting out junctions between alternating regions.

  13. Effect of Pr Valence State on Interfacial Structure and Electrical Properties of Pr Oxide/PrON/Ge Gate Stack Structure

    NASA Astrophysics Data System (ADS)

    Kato, Kimihiko; Sakashita, Mitsuo; Takeuchi, Wakana; Kondo, Hiroki; Nakatsuka, Osamu; Zaima, Shigeaki

    2011-04-01

    In this study, we investigated the valence state and chemical bonding state of Pr in a Pr oxide/PrON/Ge structure. We clarified the relationship between the valence state of Pr and the Pr oxide/Ge interfacial reaction using Pr oxide/Ge and Pr oxide/PrON/Ge samples. We found the formation of three Pr oxide phases in Pr oxide films; hexagonal Pr2O3 (h-Pr2O3) (Pr3+), cubic Pr2O3 (c-Pr2O3) (Pr3+), and c-PrO2 (Pr4+). We also investigated the effect of a nitride interlayer on the interfacial reaction in Pr oxide/Ge gate stacks. In a sample with a nitride interlayer (Pr oxide/PrON/Ge), metallic Pr-Pr bonds are also formed in the c-Pr2O3 film. After annealing in H2 ambient, the diffusion of Ge into Pr oxide is not observed in this sample. Pr-Pr bonds probably prevent the interfacial reaction and Ge oxide formation, considering that the oxygen chemical potential of this film is lower than that of a GeO2/Ge system. On the other hand, the rapid thermal oxidation (RTO) treatment terminates the O vacancies and defects in c-Pr2O3. As a result, c-PrO2 with tetravalent Pr is formed in the Pr oxide/PrON/Ge sample with RTO. In this sample, the leakage current density is effectively decreased in comparison with the sample without RTO. Hydrogen termination works effectively in Pr oxide/PrON/Ge samples with and without RTO, and we can achieve an interface state density of as low as 4 ×1011 eV-1·cm-2.

  14. GaN metal-oxide-semiconductor field-effect transistors on AlGaN/GaN heterostructure with recessed gate

    NASA Astrophysics Data System (ADS)

    Wang, Qingpeng; Ao, Jin-Ping; Wang, Pangpang; Jiang, Ying; Li, Liuan; Kawaharada, Kazuya; Liu, Yang

    2015-04-01

    GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure with a recess gate were fabricated and characterized. The device showed good pinch-off characteristics and a maximum field-effect mobility of 145.2 cm2·V-1·s-1. The effects of etching gas of Cl2 and SiCl4 were investigated in the gate recess process. SiCl4-etched devices showed higher channel mobility and lower threshold voltage. Atomic force microscope measurement was done to investigate the etching profile with different etching protection mask. Compared with photoresist, SiO2-masked sample showed lower surface roughness and better profile with stepper sidewall and weaker trenching effect resulting in higher channel mobility in the MOSFET.

  15. A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stress

    NASA Astrophysics Data System (ADS)

    Niang, K. M.; Barquinha, P. M. C.; Martins, R. F. P.; Cobb, B.; Powell, M. J.; Flewitt, A. J.

    2016-02-01

    Thin film transistors (TFTs) employing an amorphous indium gallium zinc oxide (a-IGZO) channel layer exhibit a positive shift in the threshold voltage under the application of positive gate bias stress (PBS). The time and temperature dependence of the threshold voltage shift was measured and analysed using the thermalization energy concept. The peak energy barrier to defect conversion is extracted to be 0.75 eV and the attempt-to-escape frequency is extracted to be 107 s-1. These values are in remarkable agreement with measurements in a-IGZO TFTs under negative gate bias illumination stress (NBIS) reported recently (Flewitt and Powell, J. Appl. Phys. 115, 134501 (2014)). This suggests that the same physical process is responsible for both PBS and NBIS, and supports the oxygen vacancy defect migration model that the authors have previously proposed.

  16. Interface trap density and mobility extraction in InGaAs buried quantum well metal-oxide-semiconductor field-effect-transistors by gated Hall method

    SciTech Connect

    Chidambaram, Thenappan; Madisetti, Shailesh; Greene, Andrew; Yakimov, Michael; Tokranov, Vadim; Oktyabrsky, Serge; Veksler, Dmitry; Hill, Richard

    2014-03-31

    In this work, we are using a gated Hall method for measurement of free carrier density and electron mobility in buried InGaAs quantum well metal-oxide-semiconductor field-effect-transistor channels. At room temperature, mobility over 8000 cm{sup 2}/Vs is observed at ∼1.4 × 10{sup 12} cm{sup −2}. Temperature dependence of the electron mobility gives the evidence that remote Coulomb scattering dominates at electron density <2 × 10{sup 11} cm{sup −2}. Spectrum of the interface/border traps is quantified from comparison of Hall data with capacitance-voltage measurements or electrostatic modeling. Above the threshold voltage, gate control is strongly limited by fast traps that cannot be distinguished from free channel carriers just by capacitance-based methods and can be the reason for significant overestimation of channel density and underestimation of carrier mobility from transistor measurements.

  17. Amorphous Indium Gallium Zinc Oxide Thin-Film Transistors with a Low-Temperature Polymeric Gate Dielectric on a Flexible Substrate

    NASA Astrophysics Data System (ADS)

    Hyung, Gun Woo; Park, Jaehoon; Wang, Jian-Xun; Lee, Ho Won; Li, Zhao-Hui; Koo, Ja-Ryong; Kwon, Sang Jik; Cho, Eou-Sik; Kim, Woo Young; Kim, Young Kwan

    2013-07-01

    Amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with a solution-processed polymeric gate dielectric of cross-linked poly(4-vinylphenol) (c-PVP) film were fabricated on a poly(ethylene terephthalate) (PET) substrate on which an a-IGZO film, as the active channel layer, was deposited by radio frequency (RF) sputtering. The entire TFT fabrication process was carried out at a temperature below 110 °C. The device exhibited an on/off ratio of 1.5×106 and a high field-effect mobility of 10.2 cm2 V-1 s-1, which is, to our knowledge, the best result ever achieved among a-IGZO TFTs with polymeric gate dielectrics on a plastic substrate.

  18. Reliability and failure modes of implant-supported zirconium-oxide fixed dental prostheses related to veneering techniques

    PubMed Central

    Baldassarri, Marta; Zhang, Yu; Thompson, Van P.; Rekow, Elizabeth D.; Stappert, Christian F. J.

    2011-01-01

    Summary Objectives To compare fatigue failure modes and reliability of hand-veneered and over-pressed implant-supported three-unit zirconium-oxide fixed-dental-prostheses(FDPs). Methods Sixty-four custom-made zirconium-oxide abutments (n=32/group) and thirty-two zirconium-oxide FDP-frameworks were CAD/CAM manufactured. Frameworks were veneered with hand-built up or over-pressed porcelain (n=16/group). Step-stress-accelerated-life-testing (SSALT) was performed in water applying a distributed contact load at the buccal cusp-pontic-area. Post failure examinations were carried out using optical (polarized-reflected-light) and scanning electron microscopy (SEM) to visualize crack propagation and failure modes. Reliability was compared using cumulative-damage step-stress analysis (Alta-7-Pro, Reliasoft). Results Crack propagation was observed in the veneering porcelain during fatigue. The majority of zirconium-oxide FDPs demonstrated porcelain chipping as the dominant failure mode. Nevertheless, fracture of the zirconium-oxide frameworks was also observed. Over-pressed FDPs failed earlier at a mean failure load of 696 ± 149 N relative to hand-veneered at 882 ± 61 N (profile I). Weibull-stress-number of cycles-unreliability-curves were generated. The reliability (2-sided at 90% confidence bounds) for a 400N load at 100K cycles indicated values of 0.84 (0.98-0.24) for the hand-veneered FDPs and 0.50 (0.82-0.09) for their over-pressed counterparts. Conclusions Both zirconium-oxide FDP systems were resistant under accelerated-life-time-testing. Over-pressed specimens were more susceptible to fatigue loading with earlier veneer chipping. PMID:21557985

  19. Theoretical comparison of Si, Ge, and GaAs ultrathin p-type double-gate metal oxide semiconductor transistors

    NASA Astrophysics Data System (ADS)

    Dib, Elias; Bescond, Marc; Cavassilas, Nicolas; Michelini, Fabienne; Raymond, Laurent; Lannoo, Michel

    2013-08-01

    Based on a self-consistent multi-band quantum transport code including hole-phonon scattering, we compare current characteristics of Si, Ge, and GaAs p-type double-gate transistors. Electronic properties are analyzed as a function of (i) transport orientation, (ii) channel material, and (iii) gate length. We first show that ⟨100⟩-oriented devices offer better characteristics than their ⟨110⟩-counterparts independently of the material choice. Our results also point out that the weaker impact of scattering in Ge produces better electrical performances in long devices, while the moderate tunneling effect makes Si more advantageous in ultimately scaled transistors. Moreover, GaAs-based devices are less advantageous for shorter lengths and do not offer a high enough ON current for longer gate lengths. According to our simulations, the performance switching between Si and Ge occurs for a gate length of 12 nm. The conclusions of the study invite then to consider ⟨100⟩-oriented double-gate devices with Si for gate length shorter than 12 nm and Ge otherwise.

  20. Drift region doping effects on characteristics and reliability of high-voltage n-type metal-oxide-semiconductor transistors

    NASA Astrophysics Data System (ADS)

    Chen, Jone F.; Chang, Chun-Po; Liu, Yu Ming; Tsai, Yan-Lin; Hsu, Hao-Tang; Chen, Chih-Yuan; Hwang, Hann-Ping

    2016-01-01

    In this study, off-state breakdown voltage (VBD) and hot-carrier-induced degradation in high-voltage n-type metal-oxide-semiconductor transistors with various BF2 implantation doses in the n- drift region are investigated. Results show that a higher BF2 implantation dose results in a higher VBD but leads to a greater hot-carrier-induced device degradation. Experimental data and technology computer-aided design simulations suggest that the higher VBD is due to the suppression of gate-induced drain current. On the other hand, the greater hot-carrier-induced device degradation can be explained by a lower net donor concentration and a different current-flow path, which is closer to the Si-SiO2 interface.

  1. Effect of electrical stress on Au/Pb (Zr0.52Ti0.48) O3/TiOxNy/Si gate stack for reliability analysis of ferroelectric field effect transistors

    NASA Astrophysics Data System (ADS)

    Khosla, Robin; Sharma, Deepak K.; Mondal, Kunal; Sharma, Satinder K.

    2014-10-01

    Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure with 20 nm thin lead zirconate titanate (PZT) ferroelectric film and 6 nm ultrathin high-κ titanium oxynitride (TiOxNy) insulator layer on p-Si substrate were fabricated. Effect of constant voltage stress (CVS) on electrical characteristics of MFIS structure was investigated to study the reliability of fabricated devices. The experimental results showed trivial variation in memory window (ΔW) from 1.05 to 1 V under CVS of 0 to 15 V (5.76 MV/cm) at sweep voltage of ±5 V. Also, leakage current density (J) reduced from 5.57 to 1.94 μA/cm2 under CVS of 5.76 MV/cm, supported by energy band diagram. It signifies highly reliable TiOxNy buffer layer for Ferroelectric Random Access Memory. After programming at ±5 V, the high (CH) and low (CL) capacitances reliability remains distinguishable for 5000 s even if we extrapolate measured data to 15 years. Microstructures analysis of XRD reveals the formation of (100) and (111) orientation of PZT and TiOxNy, respectively. Thus, Au/PZT/TiOxNy/Si, MFIS gate stacks can be potential candidate for next generation reliable Ferroelectric Field Effect Transistors.

  2. The impact of tunnel oxide nitridation to reliability performance of charge storage non-volatile memory devices.

    PubMed

    Lee, Meng Chuan; Wong, Hin Yong

    2014-02-01

    This paper is written to review the development of critical research on the overall impact of tunnel oxide nitridation (TON) with the aim to mitigate reliability issues due to incessant technology scaling of charge storage NVM devices. For more than 30 years, charge storage non-volatile memory (NVM) has been critical in the evolution of intelligent electronic devices and continuous development of integrated technologies. Technology scaling is the primary strategy implemented throughout the semiconductor industry to increase NVM density and drive down average cost per bit. In this paper, critical reliability challenges and key innovative technical mitigation methods are reviewed. TON is one of the major candidates to replace conventional oxide layer for its superior quality and reliability performance. Major advantages and caveats of key TON process techniques are discussed. The impact of TON on quality and reliability performance of charge storage NVM devices is carefully reviewed with emphasis on major advantages and drawbacks of top and bottom nitridation. Physical mechanisms attributed to charge retention and V(t) instability phenomenon are also reviewed in this paper. PMID:24749438

  3. Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

    NASA Astrophysics Data System (ADS)

    Liu, Hsi-Wen; Chang, Ting-Chang; Tsai, Jyun-Yu; Chen, Ching-En; Liu, Kuan-Ju; Lu, Ying-Hsin; Lin, Chien-Yu; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Ye, Yi-Han

    2016-04-01

    This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

  4. Femtosecond all-optical parallel logic gates based on tunable saturable to reverse saturable absorption in graphene-oxide thin films

    SciTech Connect

    Roy, Sukhdev Yadav, Chandresh

    2013-12-09

    A detailed theoretical analysis of ultrafast transition from saturable absorption (SA) to reverse saturable absorption (RSA) has been presented in graphene-oxide thin films with femtosecond laser pulses at 800 nm. Increase in pulse intensity leads to switching from SA to RSA with increased contrast due to two-photon absorption induced excited-state absorption. Theoretical results are in good agreement with reported experimental results. Interestingly, it is also shown that increase in concentration results in RSA to SA transition. The switching has been optimized to design parallel all-optical femtosecond NOT, AND, OR, XOR, and the universal NAND and NOR logic gates.

  5. Electric field-induced transport modulation in VO2 FETs with high-k oxide/organic parylene-C hybrid gate dielectric

    NASA Astrophysics Data System (ADS)

    Wei, Tingting; Kanki, Teruo; Fujiwara, Kohei; Chikanari, Masashi; Tanaka, Hidekazu

    2016-02-01

    We report on the observation of reversible and immediate resistance switching by high-k oxide Ta2O5/organic parylene-C hybrid dielectric-gated VO2 thin films. Resistance change ratios at various temperatures in the insulating regime were demonstrated to occur in the vicinity of phase transition temperature. We also found an asymmetric hole-electron carrier modulation related to the suppression of phase transition temperature. The results in this research provide a possibility for clarifying the origin of metal-insulator transition in VO2 through the electrostatic field-induced transport modulation.

  6. Measurement of conduction band deformation potential constants using gate direct tunneling current in n-type metal oxide semiconductor field effect transistors under mechanical stress

    NASA Astrophysics Data System (ADS)

    Lim, Ji-Song; Yang, Xiaodong; Nishida, Toshikazu; Thompson, Scott E.

    2006-08-01

    An experimental method to determine both the hydrostatic and shear deformation potential constants is introduced. The technique is based on the change in the gate tunneling currents of Si-metal oxide semiconductor field effect transistors (MOSFETs) under externally applied mechanical stress and has been applied to industrial n-type MOSFETs. The conduction band hydrostatic and shear deformation potential constants (Ξd and Ξu) are extracted to be 1.0±0.1 and 9.6±1.0eV, respectively, which is consistent with recent theoretical works.

  7. Positive bias temperature instability in p-type metal-oxide-semiconductor devices with HfSiON/SiO{sub 2} gate dielectrics

    SciTech Connect

    Samanta, Piyas; Huang, Heng-Sheng; Chen, Shuang-Yuan; Liu, Chuan-Hsi; Cheng, Li-Wei

    2014-02-21

    We present a detailed investigation on positive-bias temperature stress (PBTS) induced degradation of nitrided hafnium silicate (HfSiON)/SiO{sub 2} gate stack in n{sup +}-poly crystalline silicon (polySi) gate p-type metal-oxide-semiconductor (pMOS) devices. The measurement results indicate that gate dielectric degradation is a composite effect of electron trapping in as-fabricated as well as newly generated neutral traps, resulting a significant amount of stress-induced leakage current and generation of surface states at the Si/SiO{sub 2} interface. Although, a significant amount of interface states are created during PBTS, the threshold voltage (V{sub T}) instability of the HfSiON based pMOS devices is primarily caused by electron trapping and detrapping. It is also shown that PBTS creates both acceptor- and donor-like interface traps via different depassivation mechanisms of the Si{sub 3} ≡ SiH bonds at the Si/SiO{sub 2} interface in pMOS devices. However, the number of donor-like interface traps ΔN{sub it}{sup D} is significantly greater than that of acceptor-like interface traps ΔN{sup A}{sub it}, resulting the PBTS induced net interface traps as donor-like.

  8. Gate length and temperature dependence of negative differential transconductance in silicon quantum well metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Naquin, Clint; Lee, Mark; Edwards, Hal; Mathur, Guru; Chatterjee, Tathagata; Maggio, Ken

    2015-09-28

    Introducing quantum transport into silicon transistors in a manner compatible with industrial fabrication has the potential to transform the performance horizons of large scale integrated silicon devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) transistors fabricated using industrial silicon complementary metal-oxide-semiconductor processing. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (V{sub G}) spacing between NDTCs. The V{sub G} spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background.

  9. 17. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    17. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ARMS, PIERS AND DAM BRIDGE, WITH ROLLER GATE HEADHOUSE IN BACKGROUND, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  10. 20. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    20. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ARM, TRUNNION PIN, PIER AND GATE GAUGE, LOOKING WEST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  11. 20. DETAIL VIEW OF SUBMERSIBLE GATE, SHOWING GATE ARMS, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    20. DETAIL VIEW OF SUBMERSIBLE GATE, SHOWING GATE ARMS, GATE PIERS, TRUNNION PIN AND GATE GAUGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  12. 21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ARM, TRUNNION PIN, PIER AND GATE GAUGE, LOOKING EAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  13. Phosphorus and boron diffusion paths in polycrystalline silicon gate of a trench-type three-dimensional metal-oxide-semiconductor field effect transistor investigated by atom probe tomography

    SciTech Connect

    Han, Bin Takamizawa, Hisashi Shimizu, Yasuo; Inoue, Koji; Nagai, Yasuyoshi; Yano, Fumiko; Kunimune, Yorinobu; Inoue, Masao; Nishida, Akio

    2015-07-13

    The dopant (P and B) diffusion path in n- and p-types polycrystalline-Si gates of trench-type three-dimensional (3D) metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated using atom probe tomography, based on the annealing time dependence of the dopant distribution at 900 °C. Remarkable differences were observed between P and B diffusion behavior. In the initial stage of diffusion, P atoms diffuse into deeper regions from the implanted region along grain boundaries in the n-type polycrystalline-Si gate. With longer annealing times, segregation of P on the grain boundaries was observed; however, few P atoms were observed within the large grains or on the gate/gate oxide interface distant from grain boundaries. These results indicate that P atoms diffuse along grain boundaries much faster than through the bulk or along the gate/gate oxide interface. On the other hand, in the p-type polycrystalline-Si gate, segregation of B was observed only at the initial stage of diffusion. After further annealing, the B atoms became uniformly distributed, and no clear segregation of B was observed. Therefore, B atoms diffuse not only along the grain boundary but also through the bulk. Furthermore, B atoms diffused deeper than P atoms along the grain boundaries under the same annealing conditions. This information on the diffusion behavior of P and B is essential for optimizing annealing conditions in order to control the P and B distributions in the polycrystalline-Si gates of trench-type 3D MOSFETs.

  14. Oxidization of squalene, a human skin lipid: a new and reliable marker of environmental pollution studies.

    PubMed

    Pham, D-M; Boussouira, B; Moyal, D; Nguyen, Q L

    2015-08-01

    A review of the oxidization of squalene, a specific human compound produced by the sebaceous gland, is proposed. Such chemical transformation induces important consequences at various levels. Squalene by-products, mostly under peroxidized forms, lead to comedogenesis, contribute to the development of inflammatory acne and possibly modify the skin relief (wrinkling). Experimental conditions of oxidation and/or photo-oxidation mechanisms are exposed, suggesting that they could possibly be bio-markers of atmospheric pollution upon skin. Ozone, long UVA rays, cigarette smoke… are shown powerful oxidizing agents of squalene. Some in vitro, ex vivo and in vivo testings are proposed as examples, aiming at studying ingredients or products capable of boosting or counteracting such chemical changes that, globally, bring adverse effects to various cutaneous compartments. PMID:25656265

  15. Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

    NASA Astrophysics Data System (ADS)

    Tari, Alireza; Lee, Czang-Ho; Wong, William S.

    2015-07-01

    Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO2, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiNx, and (3) a PECVD SiOx/SiNx dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the Vo concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiNx (high Vo) and SiO2 (low Vo) had the highest and lowest conductivity, respectively. A PECVD SiOx/SiNx dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer into the IGZO and resulted in higher resistivity films.

  16. Resonant gate driver with efficient gate energy recovery and switching loss reduction

    NASA Astrophysics Data System (ADS)

    Kim, I.-G.; Kwak, S.-S.

    2016-04-01

    This article describes a novel resonant gate driver for charging the gate capacitor of power metal-oxide semiconductor field-effect-transistors (MOSFETs) that operate at a high switching frequency in power converters. The proposed resonant gate driver is designed with three small MOSFETs to build up the inductor current in addition to an inductor for temporary energy storage. The proposed resonant gate driver recovers the CV2 gate loss, which is the largest loss dissipated in the gate resistance in conventional gate drivers. In addition, the switching loss is reduced at the instants of turn on and turn off in the power MOSFETs of power converters by using the proposed gate driver. Mathematical analyses of the total loss appearing in the gate driver circuit and the switching loss reduction in the power switch of power converters are discussed. Finally, the proposed resonant gate driver is verified with experimental results at a switching frequency of 1 MHz.

  17. Surface cleaning effects on reliability for devices with ultrathin oxides or oxynitrides

    NASA Astrophysics Data System (ADS)

    Lai, Kafai; Hao, Ming-Yin; Chen, Wei-Ming; Lee, Jack C.

    1994-09-01

    A new wafer cleaning procedure has been developed for ultra-thin thermal oxidation process (oxides (48 angstrom) and oxynitrides grown in N2O (42 angstrom) were prepared using this new cleaning and other commonly used cleaning methods to investigate the effects of surface preparation on dielectric integrity. It has been found that this two-dip method produces dielectrics with reduced leakage current and stress-induced leakage current, which are believed to be the critical parameters for ultrathin oxides. Furthermore, this new cleaning procedure improves both intrinsic and defect-related breakdown as well as the uniformity of the current- voltage characteristics across a 4-inch wafer. The methanol/HF dip time has also been optimized. The improvement is believed to be due to enhanced silicon surface passivation by hydrogen, the reduced surface micro-roughness and the absence of native oxide.

  18. Nucleation and growth of atomic layer deposited HfO2 gate dielectric layers on chemical oxide (Si-O-H) and thermal oxide (SiO2 or Si-O-N) underlayers

    NASA Astrophysics Data System (ADS)

    Green, M. L.; Ho, M.-Y.; Busch, B.; Wilk, G. D.; Sorsch, T.; Conard, T.; Brijs, B.; Vandervorst, W.; Räisänen, P. I.; Muller, D.; Bude, M.; Grazul, J.

    2002-12-01

    A study was undertaken to determine the efficacy of various underlayers for the nucleation and growth of atomic layer deposited HfO2 films. These were compared to films grown on hydrogen terminated Si. The use of a chemical oxide underlayer results in almost no barrier to film nucleation, enables linear and predictable growth at constant film density, and the most two-dimensionally continuous HfO2 films. The ease of nucleation is due to the large concentration of OH groups in the hydrous, chemical oxide. HfO2 grows on chemical oxide at a coverage rate of about 14% of a monolayer per cycle, and films are about 90% of the theoretical density of crystalline HfO2. Growth on hydrogen terminated Si is characterized by a large barrier to nucleation and growth, resulting in three-dimensional, rough, and nonlinear growth. Thermal oxide/oxynitride underlayers result in a small nucleation barrier, and nonlinear growth at low HfO2 coverages. The use of chemical oxide underlayers clearly results in the best HfO2 layers. Further, the potential to minimize the chemical oxide thickness provides an important research opportunity for high-κ gate dielectric scaling below 1.0 nm effective oxide thickness.

  19. Comparison between chemical vapor deposited and physical vapor deposited WSi{sub 2} metal gate for InGaAs n-metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Ong, B. S.; Pey, K. L.; Ong, C. Y.; Tan, C. S.; Antoniadis, D. A.; Fitzgerald, E. A.

    2011-05-02

    We compare chemical vapor deposition (CVD) and physical vapor deposition (PVD) WSi{sub 2} metal gate process for In{sub 0.53}Ga{sub 0.47}As n-metal-oxide-semiconductor field-effect transistors using 10 and 6.5 nm Al{sub 2}O{sub 3} as dielectric layer. The CVD-processed metal gate device with 6.5 nm Al{sub 2}O{sub 3} shows enhanced transistor performance such as drive current, maximum transconductance and maximum effective mobility. These values are relatively better than the PVD-processed counterpart device with improvement of 51.8%, 46.4%, and 47.8%, respectively. The improvement for the performance of the CVD-processed metal gate device is due to the fluorine passivation at the oxide/semiconductor interface and a nondestructive deposition process.

  20. AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor with Polarized P(VDF-TrFE) Ferroelectric Polymer Gating.

    PubMed

    Liu, Xinke; Lu, Youming; Yu, Wenjie; Wu, Jing; He, Jiazhu; Tang, Dan; Liu, Zhihong; Somasuntharam, Pannirselvam; Zhu, Deliang; Liu, Wenjun; Cao, Peijiang; Han, Sun; Chen, Shaojun; Tan, Leng Seow

    2015-01-01

    Effect of a polarized P(VDF-TrFE) ferroelectric polymer gating on AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) was investigated. The P(VDF-TrFE) gating in the source/drain access regions of AlGaN/GaN MOS-HEMTs was positively polarized (i.e., partially positively charged hydrogen were aligned to the AlGaN surface) by an applied electric field, resulting in a shift-down of the conduction band at the AlGaN/GaN interface. This increases the 2-dimensional electron gas (2-DEG) density in the source/drain access region of the AlGaN/GaN heterostructure, and thereby reduces the source/drain series resistance. Detailed material characterization of the P(VDF-TrFE) ferroelectric film was also carried out using the atomic force microscopy (AFM), X-ray Diffraction (XRD), and ferroelectric hysteresis loop measurement. PMID:26364872

  1. AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor with Polarized P(VDF-TrFE) Ferroelectric Polymer Gating

    PubMed Central

    Liu, Xinke; Lu, Youming; Yu, Wenjie; Wu, Jing; He, Jiazhu; Tang, Dan; Liu, Zhihong; Somasuntharam, Pannirselvam; Zhu, Deliang; Liu, Wenjun; Cao, Peijiang; Han, Sun; Chen, Shaojun; Seow Tan, Leng

    2015-01-01

    Effect of a polarized P(VDF-TrFE) ferroelectric polymer gating on AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) was investigated. The P(VDF-TrFE) gating in the source/drain access regions of AlGaN/GaN MOS-HEMTs was positively polarized (i.e., partially positively charged hydrogen were aligned to the AlGaN surface) by an applied electric field, resulting in a shift-down of the conduction band at the AlGaN/GaN interface. This increases the 2-dimensional electron gas (2-DEG) density in the source/drain access region of the AlGaN/GaN heterostructure, and thereby reduces the source/drain series resistance. Detailed material characterization of the P(VDF-TrFE) ferroelectric film was also carried out using the atomic force microscopy (AFM), X-ray Diffraction (XRD), and ferroelectric hysteresis loop measurement. PMID:26364872

  2. AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor with Polarized P(VDF-TrFE) Ferroelectric Polymer Gating

    NASA Astrophysics Data System (ADS)

    Liu, Xinke; Lu, Youming; Yu, Wenjie; Wu, Jing; He, Jiazhu; Tang, Dan; Liu, Zhihong; Somasuntharam, Pannirselvam; Zhu, Deliang; Liu, Wenjun; Cao, Peijiang; Han, Sun; Chen, Shaojun; Seow Tan, Leng

    2015-09-01

    Effect of a polarized P(VDF-TrFE) ferroelectric polymer gating on AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) was investigated. The P(VDF-TrFE) gating in the source/drain access regions of AlGaN/GaN MOS-HEMTs was positively polarized (i.e., partially positively charged hydrogen were aligned to the AlGaN surface) by an applied electric field, resulting in a shift-down of the conduction band at the AlGaN/GaN interface. This increases the 2-dimensional electron gas (2-DEG) density in the source/drain access region of the AlGaN/GaN heterostructure, and thereby reduces the source/drain series resistance. Detailed material characterization of the P(VDF-TrFE) ferroelectric film was also carried out using the atomic force microscopy (AFM), X-ray Diffraction (XRD), and ferroelectric hysteresis loop measurement.

  3. Optimization of a Solution-Processed SiO2 Gate Insulator by Plasma Treatment for Zinc Oxide Thin Film Transistors.

    PubMed

    Jeong, Yesul; Pearson, Christopher; Kim, Hyun-Gwan; Park, Man-Young; Kim, Hongdoo; Do, Lee-Mi; Petty, Michael C

    2016-01-27

    We report on the optimization of the plasma treatment conditions for a solution-processed silicon dioxide gate insulator for application in zinc oxide thin film transistors (TFTs). The SiO2 layer was formed by spin coating a perhydropolysilazane (PHPS) precursor. This thin film was subsequently thermally annealed, followed by exposure to an oxygen plasma, to form an insulating (leakage current density of ∼10(-7) A/cm(2)) SiO2 layer. Optimized ZnO TFTs (40 W plasma treatment of the gate insulator for 10 s) possessed a carrier mobility of 3.2 cm(2)/(V s), an on/off ratio of ∼10(7), a threshold voltage of -1.3 V, and a subthreshold swing of 0.2 V/decade. In addition, long-term exposure (150 min) of the pre-annealed PHPS to the oxygen plasma enabled the maximum processing temperature to be reduced from 180 to 150 °C. The resulting ZnO TFT exhibited a carrier mobility of 1.3 cm(2)/(V s) and on/off ratio of ∼10(7). PMID:26704352

  4. Properties of c-axis-aligned crystalline indium-gallium-zinc oxide field-effect transistors fabricated through a tapered-trench gate process

    NASA Astrophysics Data System (ADS)

    Asami, Yoshinobu; Kurata, Motomu; Okazaki, Yutaka; Higa, Eiji; Matsubayashi, Daisuke; Okamoto, Satoru; Sasagawa, Shinya; Moriwaka, Tomoaki; Kakehata, Tetsuya; Yakubo, Yuto; Kato, Kiyoshi; Hamada, Takashi; Sakakura, Masayuki; Hayakawa, Masahiko; Yamazaki, Shunpei

    2016-04-01

    To achieve both low power consumption and high-speed operation, we fabricated c-axis-aligned crystalline indium-gallium-zinc oxide (CAAC-IGZO) field-effect transistors (FETs) with In-rich IGZO and common IGZO (\\text{In}:\\text{Ga}:\\text{Zn} = 1:1:1 in atomic ratio) active layers through a simple process using trench gates, and evaluated their characteristics. The results confirm that 60-nm-node IGZO FETs fabricated through a 450 °C process show an extremely low off-state current below the detection limit (at most 2 × 10-16 A) even at a measurement temperature of 150 °C. The results also reveal that the FETs with the In-rich IGZO active layer show a higher on-state current than those with the common IGZO active layer and have excellent frequency characteristics with a cutoff frequency and a maximum oscillation frequency of up to 20 and 6 GHz, respectively. Thus, we demonstrated that CAAC-IGZO FETs with trench gates are promising for achieving both low power consumption and high-speed operation.

  5. The role of the substrate on the dispersion in accumulation in III-V compound semiconductor based metal-oxide-semiconductor gate stacks

    SciTech Connect

    Krylov, Igor; Ritter, Dan; Eizenberg, Moshe

    2015-09-07

    Dispersion in accumulation is a widely observed phenomenon in metal-oxide-semiconductor gate stacks based on III-V compound semiconductors. The physical origin of this phenomenon is attributed to border traps located in the dielectric material adjacent to the semiconductor. Here, we study the role of the semiconductor substrate on the electrical quality of the first layers at atomic layer deposited (ALD) dielectrics. For this purpose, either Al{sub 2}O{sub 3} or HfO{sub 2} dielectrics with variable thicknesses were deposited simultaneously on two technology important semiconductors—InGaAs and InP. Significantly larger dispersion was observed in InP based gate stacks compared to those based on InGaAs. The observed difference is attributed to a higher border trap density in dielectrics deposited on InP compared to those deposited on InGaAs. We therefore conclude that the substrate plays an important role in the determination of the electrical quality of the first dielectric monolayers deposited by ALD. An additional observation is that larger dispersion was obtained in HfO{sub 2} based capacitors compared to Al{sub 2}O{sub 3} based capacitors, deposited on the same semiconductor. This phenomenon is attributed to the lower conduction band offset rather than to a higher border trap density.

  6. Al{sub 2}O{sub 3}/GeO{sub x} gate stack on germanium substrate fabricated by in situ cycling ozone oxidation method

    SciTech Connect

    Yang, Xu; Zeng, Zhen-Hua; Wang, Sheng-Kai E-mail: xzhang62@aliyun.com Sun, Bing; Zhao, Wei; Chang, Hu-Dong; Liu, Honggang E-mail: xzhang62@aliyun.com; Zhang, Xiong E-mail: xzhang62@aliyun.com

    2014-09-01

    Al{sub 2}O{sub 3}/GeO{sub x}/Ge gate stack fabricated by an in situ cycling ozone oxidation (COO) method in the atomic layer deposition (ALD) system at low temperature is systematically investigated. Excellent electrical characteristics such as minimum interface trap density as low as 1.9 × 10{sup 11 }cm{sup −2 }eV{sup −1} have been obtained by COO treatment. The impact of COO treatment against the band alignment of Al{sub 2}O{sub 3} with respect to Ge is studied by x-ray photoelectron spectroscopy (XPS) and spectroscopic ellipsometry (SE). Based on both XPS and SE studies, the origin of gate leakage in the ALD-Al{sub 2}O{sub 3} is attributed to the sub-gap states, which may be correlated to the OH-related groups in Al{sub 2}O{sub 3} network. It is demonstrated that the COO method is effective in repairing the OH-related defects in high-k dielectrics as well as forming superior high-k/Ge interface for high performance Ge MOS devices.

  7. The role of the substrate on the dispersion in accumulation in III-V compound semiconductor based metal-oxide-semiconductor gate stacks

    NASA Astrophysics Data System (ADS)

    Krylov, Igor; Ritter, Dan; Eizenberg, Moshe

    2015-09-01

    Dispersion in accumulation is a widely observed phenomenon in metal-oxide-semiconductor gate stacks based on III-V compound semiconductors. The physical origin of this phenomenon is attributed to border traps located in the dielectric material adjacent to the semiconductor. Here, we study the role of the semiconductor substrate on the electrical quality of the first layers at atomic layer deposited (ALD) dielectrics. For this purpose, either Al2O3 or HfO2 dielectrics with variable thicknesses were deposited simultaneously on two technology important semiconductors—InGaAs and InP. Significantly larger dispersion was observed in InP based gate stacks compared to those based on InGaAs. The observed difference is attributed to a higher border trap density in dielectrics deposited on InP compared to those deposited on InGaAs. We therefore conclude that the substrate plays an important role in the determination of the electrical quality of the first dielectric monolayers deposited by ALD. An additional observation is that larger dispersion was obtained in HfO2 based capacitors compared to Al2O3 based capacitors, deposited on the same semiconductor. This phenomenon is attributed to the lower conduction band offset rather than to a higher border trap density.

  8. Resistive switching memories based on metal oxides: mechanisms, reliability and scaling

    NASA Astrophysics Data System (ADS)

    Ielmini, Daniele

    2016-06-01

    With the explosive growth of digital data in the era of the Internet of Things (IoT), fast and scalable memory technologies are being researched for data storage and data-driven computation. Among the emerging memories, resistive switching memory (RRAM) raises strong interest due to its high speed, high density as a result of its simple two-terminal structure, and low cost of fabrication. The scaling projection of RRAM, however, requires a detailed understanding of switching mechanisms and there are potential reliability concerns regarding small device sizes. This work provides an overview of the current understanding of bipolar-switching RRAM operation, reliability and scaling. After reviewing the phenomenological and microscopic descriptions of the switching processes, the stability of the low- and high-resistance states will be discussed in terms of conductance fluctuations and evolution in 1D filaments containing only a few atoms. The scaling potential of RRAM will finally be addressed by reviewing the recent breakthroughs in multilevel operation and 3D architecture, making RRAM a strong competitor among future high-density memory solutions.

  9. Modification of electronic properties of top-gated graphene devices by ultrathin yttrium-oxide dielectric layers.

    PubMed

    Wang, Lin; Chen, Xiaolong; Wang, Yang; Wu, Zefei; Li, Wei; Han, Yu; Zhang, Mingwei; He, Yuheng; Zhu, Chao; Fung, Kwok Kwong; Wang, Ning

    2013-02-01

    We report the structure characterization and electronic property modification of single layer graphene (SLG) field-effect transistor (FET) devices top-gated using ultrathin Y(2)O(3) as dielectric layers. Based on the Boltzmann transport theory within variant screening, Coulomb scattering is confirmed quantitatively to be dominant in Y(2)O(3)-covered SLG and a very few short-range impurities have been introduced by Y(2)O(3). Both DC transport and AC capacitance measurements carried out at cryogenic temperatures demonstrate that the broadening of Landau levels is mainly due to the additional charged impurities and inhomogeneity of carriers induced by Y(2)O(3) layers. PMID:23263255

  10. A novel optical gating method for laser gated imaging

    NASA Astrophysics Data System (ADS)

    Ginat, Ran; Schneider, Ron; Zohar, Eyal; Nesher, Ofer

    2013-06-01

    For the past 15 years, Elbit Systems is developing time-resolved active laser-gated imaging (LGI) systems for various applications. Traditional LGI systems are based on high sensitive gated sensors, synchronized to pulsed laser sources. Elbit propriety multi-pulse per frame method, which is being implemented in LGI systems, improves significantly the imaging quality. A significant characteristic of the LGI is its ability to penetrate a disturbing media, such as rain, haze and some fog types. Current LGI systems are based on image intensifier (II) sensors, limiting the system in spectral response, image quality, reliability and cost. A novel propriety optical gating module was developed in Elbit, untying the dependency of LGI system on II. The optical gating module is not bounded to the radiance wavelength and positioned between the system optics and the sensor. This optical gating method supports the use of conventional solid state sensors. By selecting the appropriate solid state sensor, the new LGI systems can operate at any desired wavelength. In this paper we present the new gating method characteristics, performance and its advantages over the II gating method. The use of the gated imaging systems is described in a variety of applications, including results from latest field experiments.

  11. Reliability of different blood indices to explore the oxidative stress in response to maximal cycling and static exercises.

    PubMed

    Steinberg, Jean Guillaume; Delliaux, Stéphane; Jammes, Yves

    2006-03-01

    This study compares the changes in four blood markers of exercise-induced oxidative stress in response to exercise protocols commonly used to explore the global muscle performance at work (maximal incremental cycle) and endurance to fatigue of selected muscles (static handgrip and thumb adduction). Cycling and static exercises allow the muscle to work in aerobic and anaerobic conditions, respectively. Healthy adults performed an incremental cycling exercise until volitional exhaustion and, on separated days, executed infra-maximal static thumb adduction and handgrip until exhaustion. Exercise-induced oxidative stress was assessed by the increased plasma concentration of thiobarbituric acid reactive substances (TBARS), the consumption of plasma reduced ascorbic acid (RAA), and erythrocyte reduced glutathione (GSH) antioxidants, and the changes in the total antioxidant status (TAS) of plasma. Five minutes after the end of the incremental cycling exercise, we measured a peak increase in TBARS level, maximal consumption of GSH and RAA, and a modest but significant decrease in TAS concentration. In response to both static thumb adduction and handgrip, significant variations of TBARS, GSH and RAA occurred but we did not measure any significant change in TAS level throughout the 20-min recovery period of both exercise bouts. The present study shows that only the changes in TBARS, GSH and RAA explore both dynamic and static exercises. In addition, TAS measurement does not seem to represent a reliable and unique tool to explore exercise-induced oxidative stress, at least during isometric efforts that allow the muscle to work under anaerobic condition. PMID:16494601

  12. Recent progress in high performance and reliable n-type transition metal oxide-based thin film transistors

    NASA Astrophysics Data System (ADS)

    Kwon, Jang Yeon; Kyeong Jeong, Jae

    2015-02-01

    This review gives an overview of the recent progress in vacuum-based n-type transition metal oxide (TMO) thin film transistors (TFTs). Several excellent review papers regarding metal oxide TFTs in terms of fundamental electron structure, device process and reliability have been published. In particular, the required field-effect mobility of TMO TFTs has been increasing rapidly to meet the demands of the ultra-high-resolution, large panel size and three dimensional visual effects as a megatrend of flat panel displays, such as liquid crystal displays, organic light emitting diodes and flexible displays. In this regard, the effects of the TMO composition on the performance of the resulting oxide TFTs has been reviewed, and classified into binary, ternary and quaternary composition systems. In addition, the new strategic approaches including zinc oxynitride materials, double channel structures, and composite structures have been proposed recently, and were not covered in detail in previous review papers. Special attention is given to the advanced device architecture of TMO TFTs, such as back-channel-etch and self-aligned coplanar structure, which is a key technology because of their advantages including low cost fabrication, high driving speed and unwanted visual artifact-free high quality imaging. The integration process and related issues, such as etching, post treatment, low ohmic contact and Cu interconnection, required for realizing these advanced architectures are also discussed.

  13. Memory characteristics of metal-oxide-semiconductor capacitor with high density cobalt nanodots floating gate and HfO2 blocking dielectric

    NASA Astrophysics Data System (ADS)

    Pei, Yanli; Yin, Chengkuan; Kojima, Toshiya; Nishijima, Masahiko; Fukushima, Takafumi; Tanaka, Tetsu; Koyanagi, Mitsumasa

    2009-07-01

    In this letter, cobalt nanodots (Co-NDs) had been formed via a self-assembled nanodot deposition. High resolution transmission electron microscopy and x-ray photoelectron spectroscopy analyses clearly show that the high metallic Co-ND is crystallized with small size of ˜2 nm and high density of (4-5)×1012/cm2. The metal-oxide-semiconductor device with high density Co-NDs floating gate and high-k HfO2 blocking dielectric exhibits a wide range memory window (0-12 V) due to the charge trapping into and distrapping from Co-NDs. After 10 years retention, a large memory window of ˜1.3 V with a low charge loss of ˜47% was extrapolated. The relative longer data retention demonstrates the advantage of Co-NDs for nonvolatile memory application.

  14. Gate voltage dependent 1/f noise variance model based on physical noise generation mechanisms in n-channel metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Arai, Yukiko; Aoki, Hitoshi; Abe, Fumitaka; Todoroki, Shunichiro; Khatami, Ramin; Kazumi, Masaki; Totsuka, Takuya; Wang, Taifeng; Kobayashi, Haruo

    2015-04-01

    1/f noise is one of the most important characteristics for designing analog/RF circuits including operational amplifiers and oscillators. We have analyzed and developed a novel 1/f noise model in the strong inversion, saturation, and sub-threshold regions based on SPICE2 type model used in any public metal-oxide-semiconductor field-effect transistor (MOSFET) models developed by the University of California, Berkeley. Our model contains two noise generation mechanisms that are mobility and interface trap number fluctuations. Noise variability dependent on gate voltage is also newly implemented in our model. The proposed model has been implemented in BSIM4 model of a SPICE3 compatible circuit simulator. Parameters of the proposed model are extracted with 1/f noise measurements for simulation verifications. The simulation results show excellent agreements between measurement and simulations.

  15. Self-correction of field-effect transistor characteristics in the mode of spontaneous space-charge ion polarization of gate oxide

    SciTech Connect

    Zhdan, A. G.; Naryshkina, V. G.; Chucheva, G. V.

    2009-05-15

    Spontaneous space-charge ion polarization of gate oxide in the inversion n-channel silicon field-effect transistor was accomplished in the mode of its Joule heating by the drain current I{sub d}. The transistor characteristics measured at room temperature (T{sub r}) before and after thermal-field treatment show that positive ion (Na{sup +}) localization near the SiO{sub 2}/Si interface is accompanied by an increase in the effective electron mobility (by a factor of {approx} 2.3), steepness, I{sub d}, and by a small decrease in the threshold voltage ({delta}V{sub th} = 0.58 V). At T = T{sub r}, the modified transistor characteristics are retained for months; they can be easily and predictably varied by changing I{sub d} and heating duration.

  16. Electron detrapping characteristics in positive bias temperature stressed n-channel metal-oxide-semiconductor field-effect transistors with ultrathin HfSiON gate dielectrics

    NASA Astrophysics Data System (ADS)

    Zhu, Shiyang; Nakajima, Anri

    2007-07-01

    Electrons trapped in the HfSiON gate dielectrics of n-channel metal-oxide-semiconductor field-effect transistors induced by positive bias temperature stress start to decay when the stress is interrupted or an opposite (recovery) voltage is applied. The decay begins with a quick detrapping within tens of nanoseconds followed by a slow detrapping. The quick detrapping depends on the recovery voltage and the trapping history, whereas the slow detrapping obeys approximately a logarithmic dependence on time with an almost identical slope before saturation. The observed detrapping behavior can be explained by a spatial and/or energetic distribution of trapped electrons in the HfSiON film. The device degradation under various dynamic stresses is found to be almost independent of frequency ranging from 0.001to1MHz, while it is slightly enhanced at 10MHz, probably due to insufficient recovery at the recovering half cycle.

  17. Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

    SciTech Connect

    Tari, Alireza Lee, Czang-Ho; Wong, William S.

    2015-07-13

    Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer into the IGZO and resulted in higher resistivity films.

  18. Towards a reliable and high sensitivity O₂-independent glucose sensor based on Ir oxide nanoparticles.

    PubMed

    Campbell, H B; Elzanowska, H; Birss, V I

    2013-04-15

    The primary goal of this work is the development of a rapidly responding, sensitive, and biocompatible Ir oxide (IrOx)-based glucose sensor that regenerates solely via IrOx-mediation in both O₂-free and aerobic environments. An important discovery is that, for films composed of IrOx nanoparticles, Nafion® and glucose oxidase (GOx), a Michaelis-Menten constant (K'(m)) of 20-30 mM is obtained in the case of dual-regeneration (O₂ and IrOx), while K'(m) values are much smaller (3-5 mM) when re-oxidation of GOx occurs only through IrOx-mediation. These smaller K'(m) values indicate that the regeneration of GOx via direct electron transfer to the IrOx nanoparticles is more rapid than to O₂. Small K'(m) values, which are obtained more commonly when Nafion® is not present in the films, are also important for the accurate measurement of low glucose concentrations under hypoglycemic conditions. In this work, the sensing film was also optimized for miniaturization. Depending on the IrOx and GOx surface loadings and the use of sonication before film deposition, the i(max) values ranged from 5 to 225 μA cm⁻², showing very good sensitivity down to 0.4 mM glucose. PMID:23261690

  19. Designing interlayers to improve the mechanical reliability of transparent conductive oxide coatings on flexible substrates

    SciTech Connect

    Kim, Eun-Hye; Yang, Chan-Woo; Park, Jin-Woo

    2012-05-01

    In this study, we investigate the effect of interlayers on the mechanical properties of transparent conductive oxide (TCO) on flexible polymer substrates. Indium tin oxide (ITO), which is the most widely used TCO film, and Ti, which is the most widely used adhesive interlayer, are selected as the coating and the interlayer, respectively. These films are deposited on the polymer substrates using dc-magnetron sputtering to achieve varying thicknesses. The changes in the following critical factors for film cracking and delamination are analyzed: the internal stress ({sigma}{sup i}) induced in the coatings during deposition using a white light interferometer, the crystallinity using a transmission electron microscope, and the surface roughness of ITO caused by the interlayer using an atomic force microscope. The resistances to the cracking and delamination of ITO are evaluated using a fragmentation test. Our tests and analyses reveal the important role of the interlayers, which significantly reduce the compressive {sigma}{sup i} that is induced in the ITO and increase the resistance to the buckling delamination of the ITO. However, the relaxation of {sigma}{sup i} is not beneficial to cracking because there is less compensation for the external tension as {sigma}{sup i} further decreases. Based on these results, the microstructural control is revealed as a more influential factor than {sigma}{sup i} for improving crack resistance.

  20. 18. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    18. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ARMS, PIERS AND DAM BRIDGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  1. 16. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    16. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ARM, TRUNNION PIN AND PIER, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  2. Reliability and degradation of oxide VCSELs due to reaction to atmospheric water vapor

    NASA Astrophysics Data System (ADS)

    Dafinca, Alexandru; Weidberg, Anthony R.; McMahon, Steven J.; Grillo, Alexander A.; Farthouat, Philippe; Ziolkowski, Michael; Herrick, Robert W.

    2013-03-01

    850nm oxide-aperture VCSELs are susceptible to premature failure if operated while exposed to atmospheric water vapor, and not protected by hermetic packaging. The ATLAS detector in CERN's Large Hadron Collider (LHC) has had approximately 6000 channels of Parallel Optic VCSELs fielded under well-documented ambient conditions. Exact time-to-failure data has been collected on this large sample, providing for the first time actual failure data at use conditions. In addition, the same VCSELs were tested under a variety of accelerated conditions to allow us to construct a more accurate acceleration model. Failure analysis information will also be presented to show what we believe causes corrosion-related failure for such VCSELs.

  3. Ceramic bearing development. Silicon nitride bearing balls of improved reliability: Thermal oxidation. Final report, 1 January 1995-31 October 1996

    SciTech Connect

    Burk, C.B.

    1996-11-01

    The major objective of this work was to improve the reliability of silicon nitride bearing balls by means of an optimized thermal oxidation treatment. Previous work had shown that the thermal fracture resistance of silicon nitride bearing balls increased when the balls were heated and oxidized in air. An optimized oxidation treatment for NBD-200 silicon nitride balls was developed, using a thermal proof test matrix. This oxidation treatment increased the thermal fracture resistance of the balls. Ball-on-rod RCF testing of oxidized and non-oxidized balls was performed at 786 KSI contact stress, with nitrided M50-NIL rods. RCF testing did not produce a significant percentage of ball failures for either the oxidized or non-oxidized condition. Alternative methods, such as four ball fatigue testing, should be considered for future work. The oxidation treatment degraded ball surface and geometry, and is suspected as a contributing factor to short rod life. Oxidation treatment does not appear to be a useful technique for improving the reliability of NBD-200 bearing balls.

  4. The reliability and predictive ability of a biomarker of oxidative DNA damage on functional outcomes after stroke rehabilitation.

    PubMed

    Hsieh, Yu-Wei; Lin, Keh-Chung; Korivi, Mallikarjuna; Lee, Tsong-Hai; Wu, Ching-Yi; Wu, Kuen-Yuh

    2014-01-01

    We evaluated the reliability of 8-hydroxy-2'-deoxyguanosine (8-OHdG), and determined its ability to predict functional outcomes in stroke survivors. The rehabilitation effect on 8-OHdG and functional outcomes were also assessed. Sixty-one stroke patients received a 4-week rehabilitation. Urinary 8-OHdG levels were determined by liquid chromatography-tandem mass spectrometry. The test-retest reliability of 8-OHdG was good (interclass correlation coefficient=0.76). Upper-limb motor function and muscle power determined by the Fugl-Meyer Assessment (FMA) and Medical Research Council (MRC) scales before rehabilitation showed significant negative correlation with 8-OHdG (r=-0.38, r=-0.30; p<0.05). After rehabilitation, we found a fair and significant correlation between 8-OHdG and FMA (r=-0.34) and 8-OHdG and pain (r=0.26, p<0.05). Baseline 8-OHdG was significantly correlated with post-treatment FMA, MRC, and pain scores (r=-0.34, -0.31, and 0.25; p<0.05), indicating its ability to predict functional outcomes. 8-OHdG levels were significantly decreased, and functional outcomes were improved after rehabilitation. The exploratory study findings conclude that 8-OHdG is a reliable and promising biomarker of oxidative stress and could be a valid predictor of functional outcomes in patients. Monitoring of behavioral indicators along with biomarkers may have crucial benefits in translational stroke research. PMID:24743892

  5. Retention and switching kinetics of protonated gate field effect transistors

    SciTech Connect

    DEVINE,R.A.B.; HERRERA,GILBERT V.

    2000-05-23

    The switching and memory retention time has been measured in 50 {micro}m gatelength pseudo-non-volatile memory MOSFETS containing, protonated 40 nm gate oxides. Times of the order of 3.3 seconds are observed for fields of 3 MV cm{sup {minus}1}. The retention time with protons placed either at the gate oxide/substrate or gate oxide/gate electrode interfaces is found to better than 96{percent} after 5,000 seconds. Measurement of the time dependence of the source-drain current during switching provides clear evidence for the presence of dispersive proton transport through the gate oxide.

  6. Retention and Switching Kinetics of Protonated Gate Field Effect Transistors

    SciTech Connect

    DEVINE,R.A.B.; HERRERA,GILBERT V.

    2000-06-27

    The switching and memory retention time has been measured in 50 {micro}m gatelength pseudo-non-volatile memory MOSFETs containing, protonated 40 nm gate oxides. Times of the order of 3.3 seconds are observed for fields of 3 MV cm{sup {minus}1}. The retention time with protons placed either at the gate oxide/substrate or gate oxide/gate electrode interfaces is found to better than 96% after 5,000 seconds. Measurement of the time dependence of the source-drain current during switching provides clear evidence for the presence of dispersive proton transport through the gate oxide.

  7. A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under simultaneous negative gate bias and illumination

    SciTech Connect

    Flewitt, A. J.; Powell, M. J.

    2014-04-07

    It has been previously observed that thin film transistors (TFTs) utilizing an amorphous indium gallium zinc oxide (a-IGZO) semiconducting channel suffer from a threshold voltage shift when subjected to a negative gate bias and light illumination simultaneously. In this work, a thermalization energy analysis has been applied to previously published data on negative bias under illumination stress (NBIS) in a-IGZO TFTs. A barrier to defect conversion of 0.65–0.75 eV is extracted, which is consistent with reported energies of oxygen vacancy migration. The attempt-to-escape frequency is extracted to be 10{sup 6}−10{sup 7} s{sup −1}, which suggests a weak localization of carriers in band tail states over a 20–40 nm distance. Models for the NBIS mechanism based on charge trapping are reviewed and a defect pool model is proposed in which two distinct distributions of defect states exist in the a-IGZO band gap: these are associated with states that are formed as neutrally charged and 2+ charged oxygen vacancies at the time of film formation. In this model, threshold voltage shift is not due to a defect creation process, but to a change in the energy distribution of states in the band gap upon defect migration as this allows a state formed as a neutrally charged vacancy to be converted into one formed as a 2+ charged vacancy and vice versa. Carrier localization close to the defect migration site is necessary for the conversion process to take place, and such defect migration sites are associated with conduction and valence band tail states. Under negative gate bias stressing, the conduction band tail is depleted of carriers, but the bias is insufficient to accumulate holes in the valence band tail states, and so no threshold voltage shift results. It is only under illumination that the quasi Fermi level for holes is sufficiently lowered to allow occupation of valence band tail states. The resulting charge localization then allows a negative threshold voltage

  8. Electrical Characteristics of Metal-Oxide-Semiconductor Capacitor with High-κ/Metal Gate Using Oxygen Scavenging Process.

    PubMed

    Lee, Junil; Kim, Jang Hyun; Kwon, Dae Woong; Park, Euyhwan; Park, Taehyung; Kim, Hyun Woo; Park, Byung-gook

    2016-05-01

    It has been widely accepted that the mismatch of lattice constants between HfO2 and Si generates interface traps at the HfO2-Si interface, which causes the degradation of device performances. For better interface quality, very thin SiO2 film (< 2 nm) has been inserted as an interlayer (IL) between HfO2 and Si despite of the increase of EOT. In order to obtain both the better interface quality and the reduction of EOT, we used Ti metal on HfO2/IL SiO2 stack as a scavenging layer to absorb oxygens in the SiO2 and various annealing conditions were applied to optimize the thickness of the SiO2. As a result, we can effectively shrink the EOT from 3.55 nm to 1.15 nm while maintaining the same physical thickness of gate stacks. Furthermore, the diffusion of oxygen was confirmed by high resolution transmission electron microscopy (HRTEM) and time-of-flight secondary ion mass Spectrometry (SIMS). PMID:27483842

  9. Gate dielectric scaling in MOSFETs device

    NASA Astrophysics Data System (ADS)

    Jing, K. Hui; Arshad, M. K. Md.; Huda, A. R. N.; Ruslinda, A. R.; Gopinath, Subash C. B.; M. Nuzaihan M., N.; Ayub, R. M.; Fathil, M. F. M.; Othman, Noraini; Hashim, U.

    2016-07-01

    Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is a basic type of transistor to be used as a switch since 1959. Since then, the successful of MOSFET is due to good properties between silicon and silicon dioxide. The reduction of silicon oxide thickness provide further enhancement in device performance. At 90 and 65 nm technology nodes, the gate oxide could not be scaled anymore due to the direct tunneling effect resulting significant increase of leakage current. At 45 nm the high-k + metal gate has been introduced. Recently, the ferroelectric effect material is introduced which significantly reduce the gate leakage current. This paper review the evolution of gate dielectric scaling from the era of silicon dioxide to high-k + metal gate and ferroelectric effect material.

  10. Prediction of Reliable Metal-PH₃ Bond Energies for Ni, Pd, and Pt in the 0 and +2 Oxidation States

    SciTech Connect

    Craciun, Raluca; Vincent, Andrew J.; Shaughnessy, Kevin H.; Dixon, David A.

    2010-06-21

    Phosphine-based catalysts play an important role in many metal-catalyzed carbon-carbon bond formation reactions yet reliable values of their bond energies are not available. We have been studying homogeneous catalysts consisting of a phosphine bonded to a Pt, Pd, or Ni. High level electronic structure calculations at the CCSD(T)/complete basis set level were used to predict the M-PH₃ bond energy (BE) for the 0 and +2 oxidation states for M=Ni, Pd, and Pt. The calculated bond energies can then be used, for example, in the design of new catalyst systems. A wide range of exchange-correlation functionals were also evaluated to assess the performance of density functional theory (DFT) for these important bond energies. None of the DFT functionals were able to predict all of the M-PH3 bond energies to within 5 kcal/mol, and the best functionals were generalized gradient approximation functionals in contrast to the usual hybrid functionals often employed for main group thermochemistry.