Science.gov

Sample records for gate oxide reliability

  1. A Unified Functional Reliability Model for N-channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub 2 nm Gate Oxide

    NASA Astrophysics Data System (ADS)

    Lee, Hai-Ming; Du, Long-Jye; Liang, Mong-Song; King, Ya-Ching; Hsu, Charles Ching-Hsiang

    2002-09-01

    Reliability tests of N-channel metal-oxide-semiconductor field-effect transistors (NMOSFET’s) with oxide thickness ranging from 3.3 nm to 1.7 nm are performed and analyzed in this work. New device failure mechanism due to gate-to-drain leakage path formation is observed, and it severely degrades the off-state performance of devices with sub 2 nm gate oxides. Among the device parameters monitored, on-state conduction current and off-state drain leakage are the two most decisive parameters which dominate NMOSFET’s functional reliability. A new unified functional reliability model is proposed, and lifetime predictions due to respective device parameters can be achieved.

  2. Degradation of Gate Oxide Reliability due to Plasma-Deposited Silicon Nitride

    NASA Astrophysics Data System (ADS)

    Ogino, Masaaki; Sugahara, Yoshiyuki; Kuribayashi, Hitoshi; Yamabe, Kikuo

    2004-03-01

    The effects of plasma-enhanced chemical vapor deposition (PE-CVD) silicon nitride (p-SiN) passivation films on time dependent dielectric breakdown (TDDB) of gate oxide were studied. It was found that degradation of TDDB characteristics with p-SiN films was suppressed by the change in p-SiN deposition conditions. The correlation between trapped electron density and TDDB characteristics varied, depending on the p-SiN films. The degradation of TDDB characteristics was also enhanced with phosphosilicate glass (PSG) under the p-SiN passivation film.

  3. Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET

    NASA Astrophysics Data System (ADS)

    Pradhan, K. P.; Sahu, P. K.; Singh, D.; Artola, L.; Mohapatra, S. K.

    2015-09-01

    A novel device named charge plasma based doping less double material gate oxide (DMGO) silicon-germanium on insulator (SGOI) double gate (DG) MOSFET is proposed for the first time. The fundamental objective in this work is to modify the channel potential, electric field and electron velocity for improving leakage current, transconductance (gm) and transconductance generation factor (TGF). Using 2-D simulation, we exhibit that the DMGO-SGOI MOSFET shows higher electron velocity at source side and lower electric field at drain side as compare to ultra-thin body (UTB) DG MOSFET. On the other hand DMGO-SGOI MOSFET demonstrates a significant improvement in gm and TGF in comparison to UTB-DG MOSFET. This work also evaluates the existence of a biasing point i.e. zero temperature coefficient (ZTC) bias point, where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performance metrics are also subjected to extensive analysis. This further validates the reliability of charge plasma DMGO SGOI MOSFET and its application opportunities involved in designing analog/RF circuits for a wide range of temperature applications.

  4. Improvement in reliability of amorphous indium-gallium-zinc oxide thin-film transistors with Teflon/SiO2 bilayer passivation under gate bias stress

    NASA Astrophysics Data System (ADS)

    Fan, Ching-Lin; Tseng, Fan-Ping; Li, Bo-Jyun; Lin, Yu-Zuo; Wang, Shea-Jue; Lee, Win-Der; Huang, Bohr-Ran

    2016-02-01

    The reliability of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with Teflon/SiO2 bilayer passivation prepared under positive and negative gate bias stresses (PGBS and NGBS, respectively) was investigated. Heavier electrical degradation was observed under PGBS than under NGBS, indicating that the environmental effects under PGBS are more evident than those under NGBS. The device with bilayer passivation under PGBS shows two-step degradation. The positive threshold voltage shifts during the initial stressing period (before 500 s), owing to the charges trapped in the gate insulator or at the gate insulator/a-IGZO active layer interface. The negative threshold voltage shift accompanies the increase in subthreshold swing (SS) for the continuous stressing period (after 500 s) owing to H2O molecules from ambience diffused within the a-IGZO TFTs. It is believed that Teflon/SiO2 bilayer passivation can effectively improve the reliability of the a-IGZO TFTs without passivation even though the devices are stressed under gate bias.

  5. Effects of N and F passivation on the reliability and interface structure of 700 °C grown ultrathin silicon oxide/Si(100) gate films

    NASA Astrophysics Data System (ADS)

    Yamada, Hiroshi

    2008-01-01

    Correlations between reliability and interfacial structure changes of ultrathin silicon oxide gate films grown at 700 °C with in situ pyrolytic-gas passivation (PGP) were investigated. PGP uses a little pyrolytic N2O and NF3 during ultradry oxidation with pure O2 at less than 1 ppb humidity and has a potential for application to future low-temperature device fabrication processes due to the reliability retention of the films. It was found that the reliability for the 700 °C grown PGP films is much like that of the 800-900 °C grown ones, with an interface state density of less than 1-3×1010/eV cm2 maintained. Quantitative analyses of N, F, and O indicated that this is probably due to microscopic, interfacial structure changes, that is, N and F passivation effectively contributes to compensate inconsistent-state bonding sites and to generate a high-density structure with few dangling bonds.

  6. Reliability assessment of germanium gate stacks with promising initial characteristics

    NASA Astrophysics Data System (ADS)

    Lu, Cimang; Lee, Choong Hyun; Nishimura, Tomonori; Nagashio, Kosuke; Toriumi, Akira

    2015-02-01

    This work reports on the reliability assessment of germanium (Ge) gate stacks with promising initial electrical properties, with focus on trap generation under a constant electric stress field (Estress). Initial Ge gate stack properties do not necessarily mean highly robust reliability when it is considered that traps are newly generated under high Estress. A small amount of yttrium- or scandium oxide-doped GeO2 (Y-GeO2 or Sc-GeO2, respectively) significantly reduces trap generation in Ge gate stacks without deterioration of the interface. This is explained by the increase in the average coordination number (Nav) of the modified GeO2 network that results from the doping.

  7. Reliability study of refractory gate gallium arsenide MESFETS

    NASA Technical Reports Server (NTRS)

    Yin, J. C. W.; Portnoy, W. M.

    1981-01-01

    Refractory gate MESFET's were fabricated as an alternative to aluminum gate devices, which have been found to be unreliable as RF power amplifiers. In order to determine the reliability of the new structures, statistics of failure and information about mechanisms of failure in refractory gate MESFET's are given. Test transistors were stressed under conditions of high temperature and forward gate current to enhance failure. Results of work at 150 C and 275 C are reported.

  8. Single event gate rupture in thin gate oxides

    SciTech Connect

    Sexton, F.W.; Fleetwood, D.M.; Shaneyfelt, M.R.; Dodd, P.E.; Hash, G.L.

    1997-06-01

    As integrated circuit densities increase with each new technology generation, both the lateral and vertical dimensions shrink. Operating voltages, however, have not scaled as aggressively as feature size, with a resultant increase in the electric fields within advanced geometry devices. Oxide electric fields are in fact increasing to greater than 5 MV/cm as feature size approaches 0.1 {micro}m. This trend raises the concern that single event gate rupture (SEGR) may limit the scaling of advanced integrated circuits (ICs) for space applications. The dependence of single event gate rupture (SEGR) critical field on oxide thickness is examined for thin gate oxides. Critical field for SEGR increases with decreasing oxide thickness, consistent with an increasing intrinsic breakdown field.

  9. Crystalline ZrTiO{sub 4} gated p-metal–oxide–semiconductor field effect transistors with sub-nm equivalent oxide thickness featuring good electrical characteristics and reliability

    SciTech Connect

    Wu, Chao-Yi; Hsieh, Ching-Heng; Lee, Ching-Wei; Wu, Yung-Hsien

    2015-02-02

    ZrTiO{sub 4} crystallized in orthorhombic (o-) phase was stacked with an amorphous Yb{sub 2}O{sub 3} interfacial layer as the gate dielectric for Si-based p-MOSFETs. With thermal annealing after gate electrode, the gate stack with equivalent oxide thickness (EOT) of 0.82 nm achieves high dielectric quality by showing a low interface trap density (D{sub it}) of 2.75 × 10{sup 11 }cm{sup −2}eV{sup −1} near the midgap and low oxide traps. Crystallization of ZrTiO{sub 4} and post metal annealing are also proven to introduce very limited amount of metal induced gap states or interfacial dipole. The p-MOSFETs exhibit good sub-threshold swing of 75 mV/dec which is ascribed to the low D{sub it} value and small EOT. Owing to the Y{sub 2}O{sub 3} interfacial layer and smooth interface with Si substrate that, respectively, suppress phonon and surface roughness scattering, the p-MOSFETs also display high hole mobility of 49 cm{sup 2}/V-s at 1 MV/cm. In addition, I{sub on}/I{sub off} ratio larger than 10{sup 6} is also observed. From the reliability evaluation by negative bias temperature instability test, after stressing with an electric field of −10 MV/cm at 85 °C for 1000 s, satisfactory threshold voltage shift of 12 mV and sub-threshold swing degradation of 3% were obtained. With these promising characteristics, the Yb{sub 2}O{sub 3}/o-ZrTiO{sub 4} gate stack holds the great potential for next-generation electronics.

  10. Improved linearity and reliability in GaN metal-oxide-semiconductor high-electron-mobility transistors using nanolaminate La2O3/SiO2 gate dielectric

    NASA Astrophysics Data System (ADS)

    Hsu, Ching-Hsiang; Shih, Wang-Cheng; Lin, Yueh-Chin; Hsu, Heng-Tung; Hsu, Hisang-Hua; Huang, Yu-Xiang; Lin, Tai-Wei; Wu, Chia-Hsun; Wu, Wen-Hao; Maa, Jer-Shen; Iwai, Hiroshi; Kakushima, Kuniyuki; Chang, Edward Yi

    2016-04-01

    Improved device performance to enable high-linearity power applications has been discussed in this study. We have compared the La2O3/SiO2 AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with other La2O3-based (La2O3/HfO2, La2O3/CeO2 and single La2O3) MOS-HEMTs. It was found that forming lanthanum silicate films can not only improve the dielectric quality but also can improve the device characteristics. The improved gate insulation, reliability, and linearity of the 8 nm La2O3/SiO2 MOS-HEMT were demonstrated.

  11. Performance and reliability improvement of HfSiON gate dielectrics using chlorine plasma treatment

    SciTech Connect

    Park, Hong Bae; Ju, Byongsun; Kang, Chang Yong; Park, Chanro; Park, Chang Seo; Lee, Byoung Hun; Kim, Tea Wan; Kim, Beom Seok; Choi, Rino

    2009-01-26

    The effects of chlorine plasma treatment on HfSiON gate dielectrics were investigated with respect to device performance and reliability characteristics. The chlorine plasma treatment was performed on atomic layer deposited HfSiON films to remove the residual carbon content. The optimal chlorine plasma treatment is shown to lower gate leakage current density without increasing equivalent oxide thickness of the gate stack. Secondary ion mass spectroscopy depth profiling showed that the carbon residue in HfSiON was reduced by the chlorine plasma treatment. It is demonstrated that an optimized chlorine plasma treatment improves the transistor I{sub on}-I{sub off} characteristics and reduces negative-bias temperature instability.

  12. Deuterium-incorporated gate oxide of MOS devices fabricated by using deuterium ion implantation

    NASA Astrophysics Data System (ADS)

    Lee, Jae-Sung; Lear, Kevin L.

    2012-04-01

    In the aspect of metal-oxide-semiconductor (MOS) device reliability, deuterium-incorporated gate oxide could be utilized to suppress the wear-out that is combined with oxide trap generation. An alternative deuterium process for the passivation of oxide traps or defects in the gate oxide of MOS devices has been suggested in this study. The deuterium ion is delivered to the location where the gate oxide resides by using an implantation process and subsequent N2 annealing process at the back-end of metallization process. A conventional MOS field-effect transistor (MOSFET) with a 3-nm-thick gate oxide and poly-to-ploy capacitor sandwiched with 20-nm-thick SiO2 were fabricated in order to demonstrate the deuterium effect in our process. An optimum condition of ion implantation was necessary to account for the topography of the overlaying layers in the device structure and to minimize the physical damage due to the energy of the implanted ion. Device parameter variations, the gate leakage current, and the dielectric breakdown phenomenon were investigated in the deuterium-ion-implanted devices. We found the isotope effect between hydrogen- and deuterium-implanted devices and an improved electrical reliability in the deuterated gate oxide. This implies that deuterium bonds are generated effectively at the Si/SiO2 interface and in the SiO2 bulk.

  13. Process Design for Preventing the Gate Oxide Thinning in the Integration of Dual Gate Oxide Transistor

    NASA Astrophysics Data System (ADS)

    Kim, Seong-Ho; Kim, Sung-Hoan; Kim, Sung-Eun; Kim, Myung-Soo; Park, Joo-Han; Kim, Eun-Soo; Kim, Jin-Tae

    2002-04-01

    In this study, a method is proposed to alleviate a gate oxide (GOX) thinning problem at the edge of shallow trench isolation (STI), when STI is adopted in the dual gate oxide process (DGOX). It is well known that the DGOX process is usually used for realizing both low and high voltage operating parts in one chip. However, it is found that severe GOX thinning occurs from 320 Å (in active area) to 79 Å (at STI top edge) and a dent profile exists at the top edge of STI, when conventional DGOX and STI processes are adopted. In order to solve these problems, a new DGOX process is used in this study. The GOX thinning is prevented mainly by a combination of a thick sidewall oxide with SiN pullback. Therefore, good subthreshold characteristics without a so-called double hump are obtained by the prevention of GOX thinning and a deep dent profile.

  14. Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement

    NASA Astrophysics Data System (ADS)

    Raad, Bhagwan Ram; Nigam, Kaushal; Sharma, Dheeraj; Kondekar, P. N.

    2016-06-01

    This script features a study of bandgap, gate material work function and gate dielectric engineering for enhancement of DC and Analog/RF performance, reduction in the hot carriers effect (HCEs) and drain induced barrier lowering (DIBL) for better device reliability. In this concern, the use of band gap and gate material work function engineering improves the device performance in terms of the ON-state current and suppressed ambipolar behaviour with maintaining the low OFF-state current. With these advantages, the use of gate material work function engineering imposes restriction on the high frequency performance due to increment in the parasitic capacitances and also introduces the hot carrier effects. Hence, the gate dielectric engineering with bandgap and gate material work function engineering are used in this paper to overcome the cons of the gate material work function engineering by obtaining a superior performance in terms of the current driving capability, ambipolar conduction, HCEs, DIBL and high frequency parameters of the device for ultra-low power applications. Finally, the optimization of length for different work function is performed to get the best out of this.

  15. Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

    PubMed

    Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

    2016-08-24

    Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing. PMID:27471861

  16. Mechanisms of heavy-ion induced gate rupture in thin oxides

    SciTech Connect

    Sexton, F.W.; Fleetwood, D.M.; Krisch, K.S.

    1998-08-01

    Single event gate rupture (SEGR) is a catastrophic failure mode that occurs in dielectric materials that are struck by energetic heavy ions while biased under a high electric field condition. SEGR can reduce the critical electric field to breakdown to less than half the value observed in normal voltage ramp reliability tests. As electric fields in gate oxides increase to greater than 5 MV/cm in advanced MOS technologies, the impact of SEGR on the reliability of space based electronics must be assessed. In this summary, the authors explore the nature of SEGR in oxides with thickness from 7 nm to less than 5 nm, where soft breakdown is often observed during traditional reliability tests. They discuss the possible connection between the present understanding of SEGR and voltage stress breakdown models.

  17. Effect of gate oxide thickness on the radiation hardness of silicon-gate CMOS

    SciTech Connect

    Nordstrom, T.V.; Gibbon, C.F.

    1981-01-01

    Significant improvements have been made in the radiation hardness of silicon-gate CMOS by reducing the gate oxide thickness. The device studied is an 8-bit arithmetic logic unit designed with Sandia's Expanded Linear Array (ELA) standard cells. Devices with gate oxide thicknesses of 400, 570 (standard), and 700 A were fabricated. Irradiations were done at a dose rate of 2 x 10/sup 6/ rads (Si) per hour. N- and P-channel maximum threshold shifts were reduced by 0.3 and 1.2 volts, respectively, for the thinnest oxide. Approximately, a linear relationship is found for threshold shift versus thickness. The functional radiation hardness of the full integrated circuit was also measured.

  18. Oxidative Modulation of Voltage-Gated Potassium Channels

    PubMed Central

    Sahoo, Nirakar; Hoshi, Toshinori

    2014-01-01

    Abstract Significance: Voltage-gated K+ channels are a large family of K+-selective ion channel protein complexes that open on membrane depolarization. These K+ channels are expressed in diverse tissues and their function is vital for numerous physiological processes, in particular of neurons and muscle cells. Potentially reversible oxidative regulation of voltage-gated K+ channels by reactive species such as reactive oxygen species (ROS) represents a contributing mechanism of normal cellular plasticity and may play important roles in diverse pathologies including neurodegenerative diseases. Recent Advances: Studies using various protocols of oxidative modification, site-directed mutagenesis, and structural and kinetic modeling provide a broader phenomenology and emerging mechanistic insights. Critical Issues: Physicochemical mechanisms of the functional consequences of oxidative modifications of voltage-gated K+ channels are only beginning to be revealed. In vivo documentation of oxidative modifications of specific amino-acid residues of various voltage-gated K+ channel proteins, including the target specificity issue, is largely absent. Future Directions: High-resolution chemical and proteomic analysis of ion channel proteins with respect to oxidative modification combined with ongoing studies on channel structure and function will provide a better understanding of how the function of voltage-gated K+ channels is tuned by ROS and the corresponding reducing enzymes to meet cellular needs. Antioxid. Redox Signal. 21, 933–952. PMID:24040918

  19. AlN and Al oxy-nitride gate dielectrics for reliable gate stacks on Ge and InGaAs channels

    NASA Astrophysics Data System (ADS)

    Guo, Y.; Li, H.; Robertson, J.

    2016-05-01

    AlN and Al oxy-nitride dielectric layers are proposed instead of Al2O3 as a component of the gate dielectric stacks on higher mobility channels in metal oxide field effect transistors to improve their positive bias stress instability reliability. It is calculated that the gap states of nitrogen vacancies in AlN lie further away in energy from the semiconductor band gap than those of oxygen vacancies in Al2O3, and thus AlN might be less susceptible to charge trapping and have a better reliability performance. The unfavourable defect energy level distribution in amorphous Al2O3 is attributed to its larger coordination disorder compared to the more symmetrically bonded AlN. Al oxy-nitride is also predicted to have less tendency for charge trapping.

  20. The understanding on the evolution of stress-induced gate leakage in high-k dielectric metal-oxide-field-effect transistor by random-telegraph-noise measurement

    NASA Astrophysics Data System (ADS)

    Hsieh, E. R.; Chung, Steve S.

    2015-12-01

    The evolution of gate-current leakage path has been observed and depicted by RTN signals on metal-oxide-silicon field effect transistor with high-k gate dielectric. An experimental method based on gate-current random telegraph noise (Ig-RTN) technique was developed to observe the formation of gate-leakage path for the device under certain electrical stress, such as Bias Temperature Instability. The results show that the evolution of gate-current path consists of three stages. In the beginning, only direct-tunnelling gate current and discrete traps inducing Ig-RTN are observed; in the middle stage, interaction between traps and the percolation paths presents a multi-level gate-current variation, and finally two different patterns of the hard or soft breakdown path can be identified. These observations provide us a better understanding of the gate-leakage and its impact on the device reliability.

  1. High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric.

    PubMed

    Fujii, Mami N; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

    2015-01-01

    The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices. PMID:26677773

  2. High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

    NASA Astrophysics Data System (ADS)

    Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

    2015-12-01

    The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

  3. High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

    PubMed Central

    Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

    2015-01-01

    The use of indium–gallium–zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic–inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic–inorganic hybrid devices. PMID:26677773

  4. High-κ oxide nanoribbons as gate dielectrics for high mobility top-gated graphene transistors

    PubMed Central

    Liao, Lei; Bai, Jingwei; Qu, Yongquan; Lin, Yung-chen; Li, Yujing; Huang, Yu; Duan, Xiangfeng

    2010-01-01

    Deposition of high-κ dielectrics onto graphene is of significant challenge due to the difficulties of nucleating high quality oxide on pristine graphene without introducing defects into the monolayer of carbon lattice. Previous efforts to deposit high-κ dielectrics on graphene often resulted in significant degradation in carrier mobility. Here we report an entirely new strategy to integrate high quality high-κ dielectrics with graphene by first synthesizing freestanding high-κ oxide nanoribbons at high temperature and then transferring them onto graphene at room temperature. We show that single crystalline Al2O3 nanoribbons can be synthesized with excellent dielectric properties. Using such nanoribbons as the gate dielectrics, we have demonstrated top-gated graphene transistors with the highest carrier mobility (up to 23,600 cm2/V·s) reported to date, and a more than 10-fold increase in transconductance compared to the back-gated devices. This method opens a new avenue to integrate high-κ dielectrics on graphene with the preservation of the pristine nature of graphene and high carrier mobility, representing an important step forward to high-performance graphene electronics. PMID:20308584

  5. Chemical gating of epitaxial graphene through ultrathin oxide layers

    NASA Astrophysics Data System (ADS)

    Larciprete, Rosanna; Lacovig, Paolo; Orlando, Fabrizio; Dalmiglio, Matteo; Omiciuolo, Luca; Baraldi, Alessandro; Lizzit, Silvano

    2015-07-01

    We achieved a controllable chemical gating of epitaxial graphene grown on metal substrates by exploiting the electrostatic polarization of ultrathin SiO2 layers synthesized below it. Intercalated oxygen diffusing through the SiO2 layer modifies the metal-oxide work function and hole dopes graphene. The graphene/oxide/metal heterostructure behaves as a gated plane capacitor with the in situ grown SiO2 layer acting as a homogeneous dielectric spacer, whose high capacity allows the Fermi level of graphene to be shifted by a few hundreds of meV when the oxygen coverage at the metal substrate is of the order of 0.5 monolayers. The hole doping can be finely tuned by controlling the amount of interfacial oxygen, as well as by adjusting the thickness of the oxide layer. After complete thermal desorption of oxygen the intrinsic doping of SiO2 supported graphene is evaluated in the absence of contaminants and adventitious adsorbates. The demonstration that the charge state of graphene can be changed by chemically modifying the buried oxide/metal interface hints at the possibility of tuning the level and sign of doping by the use of other intercalants capable of diffusing through the ultrathin porous dielectric and reach the interface with the metal.We achieved a controllable chemical gating of epitaxial graphene grown on metal substrates by exploiting the electrostatic polarization of ultrathin SiO2 layers synthesized below it. Intercalated oxygen diffusing through the SiO2 layer modifies the metal-oxide work function and hole dopes graphene. The graphene/oxide/metal heterostructure behaves as a gated plane capacitor with the in situ grown SiO2 layer acting as a homogeneous dielectric spacer, whose high capacity allows the Fermi level of graphene to be shifted by a few hundreds of meV when the oxygen coverage at the metal substrate is of the order of 0.5 monolayers. The hole doping can be finely tuned by controlling the amount of interfacial oxygen, as well as by adjusting

  6. Chemical gating of epitaxial graphene through ultrathin oxide layers.

    PubMed

    Larciprete, Rosanna; Lacovig, Paolo; Orlando, Fabrizio; Dalmiglio, Matteo; Omiciuolo, Luca; Baraldi, Alessandro; Lizzit, Silvano

    2015-08-01

    We achieved a controllable chemical gating of epitaxial graphene grown on metal substrates by exploiting the electrostatic polarization of ultrathin SiO2 layers synthesized below it. Intercalated oxygen diffusing through the SiO2 layer modifies the metal-oxide work function and hole dopes graphene. The graphene/oxide/metal heterostructure behaves as a gated plane capacitor with the in situ grown SiO2 layer acting as a homogeneous dielectric spacer, whose high capacity allows the Fermi level of graphene to be shifted by a few hundreds of meV when the oxygen coverage at the metal substrate is of the order of 0.5 monolayers. The hole doping can be finely tuned by controlling the amount of interfacial oxygen, as well as by adjusting the thickness of the oxide layer. After complete thermal desorption of oxygen the intrinsic doping of SiO2 supported graphene is evaluated in the absence of contaminants and adventitious adsorbates. The demonstration that the charge state of graphene can be changed by chemically modifying the buried oxide/metal interface hints at the possibility of tuning the level and sign of doping by the use of other intercalants capable of diffusing through the ultrathin porous dielectric and reach the interface with the metal. PMID:26148485

  7. Polysilicon Gate Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations in Sub-100 nm MOSFET's with Ultrathin Gate Oxide

    NASA Technical Reports Server (NTRS)

    Asenov, Asen; Saini, Subhash

    2000-01-01

    In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFET's with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3-D) "atomistic" simulation technique described else-where. MOSFET's with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled-in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide-thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect or the polysilicon grain boundaries on the threshold voltage variation are also presented.

  8. Enhanced Breakdown Reliability and Spatial Uniformity of Atomic Layer Deposited High-k Gate Dielectrics on Graphene via Organic Seeding Layers

    NASA Astrophysics Data System (ADS)

    Sangwan, Vinod; Jariwala, Deep; Filippone, Stephen; Karmel, Hunter; Johns, James; Alaboson, Justice; Marks, Tobin; Lauhon, Lincoln; Hersam, Mark

    2013-03-01

    Ultra-thin high- κ top-gate dielectrics are essential for high-speed graphene-based nanoelectronic circuits. Motivated by the need for high reliability and spatial uniformity, we report here the first statistical analysis of the breakdown characteristics of dielectrics grown on graphene. Based on these measurements, a rational approach is devised that simultaneously optimizes the gate capacitance and the key parameters of large-area uniformity and dielectric strength. In particular, vertically heterogeneous oxide stacks grown via atomic-layer deposition (ALD) seeded by a molecularly thin perylene-3,4,9,10-tetracarboxylic dianhydride (PTCDA) organic monolayer result in improved reliability (Weibull shape parameter β > 25) compared to the control dielectric directly grown on graphene without PTCDA (β < 1). The optimized sample also showed a large breakdown strength (Weibull scale parameter, EBD > 7 MV/cm) that is comparable to that of the control dielectric grown on Si substrates.

  9. Precursor ion damage and single event gate rupture in thin oxides

    SciTech Connect

    Sexton, F.W.; Fleetwood, D.M.; Shaneyfelt, M.R.; Dodd, P.E.; Hash, G.L.; Schanwald, L.P.; Krisch, K.S.

    1998-02-01

    Gate oxide electric fields are expected to increase to greater than 5 MV/cm as feature size approaches 0.1 micrometers in advanced integrated circuit (IC) technologies. Work by Johnston, et al. raised the concern that single event gate rupture (SEGR) may limit the scaling of advanced ICs for space applications. SEGR has also been observed in field programmable gate arrays, which rely on thin dielectrics for electrical programming at very high electric fields. The focus of this effort is to further explore the mechanisms for SEGR in thin gate oxides. The authors examine the characteristics of heavy ion induced breakdown and compare them to ion induced damage in thin gate oxides. Further, the authors study the impact of precursor damage in oxides on SEGR threshold. Finally, they compare thermal and nitrided oxides to see if SEGR is improved by incorporating nitrogen in the oxide.

  10. Surface photovoltage analysis of iron contamination in silicon processing and the relation to gate oxide integrity

    NASA Astrophysics Data System (ADS)

    Henley, Worth B.

    1995-09-01

    Surface photovoltage (SPV), a contactless optical technique for measuring minority carrier lifetime, is used to quantify the relationship between silicon iron contamination level and thin gate oxide integrity. Iron concentration levels in the range of 1 X 1010 cm-3 to 5 X 1013 cm-3 are evaluated for oxide thicknesses of 8 to 20 nm. Ramp voltage electrical breakdown and time dependant dielectric breakdown measurement on the iron contaminated gate oxide capacitors are reported. Distinct iron contamination threshold limits based on defect density and gate oxide integrity evaluate cleaning efficiencies and metallic cross contamination effects during thermal processing contamination. Iron-silicide precipitation kinetics are investigated by the lifetime analysis procedure.

  11. Vox/Eox-Driven Breakdown of Ultrathin SiON Gate Dielectrics in p-Type Metal Oxide Semiconductor Field Effect Transistors under Low-Voltage Inversion Stress

    NASA Astrophysics Data System (ADS)

    Tsujikawa, Shimpei; Shiga, Katsuya; Umeda, Hiroshi; Yugami, Jiro

    2007-01-01

    The breakdown mechanism of ultrathin SiON gate dielectrics in p-type metal oxide semiconductor field effect transistors having p+gates (p+gate-pMOSFETs) has been studied. Systematic study with varying gate doping concentrations has revealed that, in the case of p+gate-pMOSFET in inversion mode, gate dielectric breakdown under stress voltage lower than -4 V is driven by oxide voltage (Vox) or oxide field (Eox), while the breakdown under stress voltage higher than -4 V is driven by gate voltage (Vg). The Vox/Eox-driven breakdown observed under low stress voltage is quite important to the reliability of low-voltage complementary metal oxide semiconductor (CMOS). By studying the mechanism of the breakdown, it has been clarified that the breakdown is not induced by electron current. The concept that the breakdown is due to same mechanism as the negative bias temperature instability (NBTI), namely the interfacial hydrogen release driven by Eox, has been shown to be possible. However, direct tunneling of holes driven by Vox has also been found to be a possible driving force of the breakdown. Although a decisive conclusion concerning the mechanism issue has not yet been obtained, the key factor that governs the breakdown has been shown to be Vox or Eox.

  12. Room-temperature phosphorescence logic gates developed from nucleic acid functionalized carbon dots and graphene oxide.

    PubMed

    Gui, Rijun; Jin, Hui; Wang, Zonghua; Zhang, Feifei; Xia, Jianfei; Yang, Min; Bi, Sai; Xia, Yanzhi

    2015-05-14

    Room-temperature phosphorescence (RTP) logic gates were developed using capture ssDNA (cDNA) modified carbon dots and graphene oxide (GO). The experimental results suggested the feasibility of these developed RTP-based "OR", "INHIBIT" and "OR-INHIBIT" logic gate operations, using Hg(2+), target ssDNA (tDNA) and doxorubicin (DOX) as inputs. PMID:25882250

  13. Mesostructured HfxAlyO2 Thin Films as Reliable and Robust Gate Dielectrics with Tunable Dielectric Constants for High-Performance Graphene-Based Transistors.

    PubMed

    Lee, Yunseong; Jeon, Woojin; Cho, Yeonchoo; Lee, Min-Hyun; Jeong, Seong-Jun; Park, Jongsun; Park, Seongjun

    2016-07-26

    We introduce a reliable and robust gate dielectric material with tunable dielectric constants based on a mesostructured HfxAlyO2 film. The ultrathin mesostructured HfxAlyO2 film is deposited on graphene via a physisorbed-precursor-assisted atomic layer deposition process and consists of an intermediate state with small crystallized parts in an amorphous matrix. Crystal phase engineering using Al dopant is employed to achieve HfO2 phase transitions, which produce the crystallized part of the mesostructured HfxAlyO2 film. The effects of various Al doping concentrations are examined, and an enhanced dielectric constant of ∼25 is obtained. Further, the leakage current is suppressed (∼10(-8) A/cm(2)) and the dielectric breakdown properties are enhanced (breakdown field: ∼7 MV/cm) by the partially remaining amorphous matrix. We believe that this contribution is theoretically and practically relevant because excellent gate dielectric performance is obtained. In addition, an array of top-gated metal-insulator-graphene field-effect transistors is fabricated on a 6 in. wafer, yielding a capacitance equivalent oxide thickness of less than 1 nm (0.78 nm). This low capacitance equivalent oxide thickness has important implications for the incorporation of graphene into high-performance silicon-based nanoelectronics. PMID:27355098

  14. Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

    NASA Astrophysics Data System (ADS)

    Kim, Young-Hee

    Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is

  15. Automated Coronary Artery Calcification Scoring in Non-Gated Chest CT: Agreement and Reliability

    PubMed Central

    Takx, Richard A. P.; de Jong, Pim A.; Leiner, Tim; Oudkerk, Matthijs; de Koning, Harry J.; Mol, Christian P.; Viergever, Max A.; Išgum, Ivana

    2014-01-01

    Objective To determine the agreement and reliability of fully automated coronary artery calcium (CAC) scoring in a lung cancer screening population. Materials and Methods 1793 low-dose chest CT scans were analyzed (non-contrast-enhanced, non-gated). To establish the reference standard for CAC, first automated calcium scoring was performed using a preliminary version of a method employing coronary calcium atlas and machine learning approach. Thereafter, each scan was inspected by one of four trained raters. When needed, the raters corrected initially automaticity-identified results. In addition, an independent observer subsequently inspected manually corrected results and discarded scans with gross segmentation errors. Subsequently, fully automatic coronary calcium scoring was performed. Agatston score, CAC volume and number of calcifications were computed. Agreement was determined by calculating proportion of agreement and examining Bland-Altman plots. Reliability was determined by calculating linearly weighted kappa (κ) for Agatston strata and intraclass correlation coefficient (ICC) for continuous values. Results 44 (2.5%) scans were excluded due to metal artifacts or gross segmentation errors. In the remaining 1749 scans, median Agatston score was 39.6 (P25–P75∶0–345.9), median volume score was 60.4 mm3 (P25–P75∶0–361.4) and median number of calcifications was 2 (P25–P75∶0–4) for the automated scores. The κ demonstrated very good reliability (0.85) for Agatston risk categories between the automated and reference scores. The Bland-Altman plots showed underestimation of calcium score values by automated quantification. Median difference was 2.5 (p25–p75∶0.0–53.2) for Agatston score, 7.6 (p25–p75∶0.0–94.4) for CAC volume and 1 (p25–p75∶0–5) for number of calcifications. The ICC was very good for Agatston score (0.90), very good for calcium volume (0.88) and good for number of calcifications (0.64). Discussion Fully automated

  16. Influence of the Polysilicon Gate on the Random Dopant Induced Threshold Voltage Fluctuations in Sub 100 nm MOSFETS with Thin Gate Oxides

    NASA Technical Reports Server (NTRS)

    Asenov, Asen; Saini, S.

    2000-01-01

    In this paper for the first time we study the influence of the polysilicon gate on the random dopant induced threshold voltage fluctuations in sub 100 nm MOSFETs with tunnelling gate oxides. This is done by using an efficient 3D 'atomistic' simulation technique described elsewhere. Devices with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveale that the polysilicon gate is responsible for a substantial fraction of the threshold voltage fluctuations in both devices when the gate oxide is scaled to tunnelling thickness in the range of 1 - 2 nm.

  17. Reliability tests of gated silicon field emitters for use in space

    NASA Astrophysics Data System (ADS)

    Aplin, K. L.; Collingwood, C. M.; Kent, B. J.

    2004-07-01

    Neutralizers are required to prevent spacecraft charging from satellite ion propulsion. This paper discusses the development of a gated silicon tip field emitter (FE) neutralizer, specified to deliver 6 mA, with each tip emitting a mean current of 7 nA. It is important to investigate factors affecting the lifetime of field emitter arrays for a space application, as longevity and reliability are both critical requirements. Semi-automated procedures to prepare 400 arrays, each consisting of 765 FEs, for life tests are described with failure conditions strictly defined by mission constraints. Results of 25 life tests on 72 arrays driven to failure at constant emission current are summarized, and a case study of one test is presented. Two of the three failure mechanisms identified are consistent with thermal failure and damage by ion bombardment. Reduced field enhancement from tip erosion caused by ion bombardment is a common explanation for FE failure. However, scanning electron microscope examination of tip apex diameters showed no significant relationship between array failure and apex geometry. The third failure mechanism was associated with short-lived arrays and may be caused by manufacturing defects. Substantial intrinsic variability was observed in the arrays tested, even with the rigorous production standards required for space applications. Arrays without manufacturing defects had lifetimes of thousands of hours.

  18. A Low-Leakage Epitaxial High-κ Gate Oxide for Germanium Metal-Oxide-Semiconductor Devices.

    PubMed

    Hu, Chengqing; McDaniel, Martin D; Jiang, Aiting; Posadas, Agham; Demkov, Alexander A; Ekerdt, John G; Yu, Edward T

    2016-03-01

    Germanium (Ge)-based metal-oxide-semiconductor field-effect transistors are a promising candidate for high performance, low power electronics at the 7 nm technology node and beyond. However, the availability of high quality gate oxide/Ge interfaces that provide low leakage current density and equivalent oxide thickness (EOT), robust scalability, and acceptable interface state density (Dit) has emerged as one of the most challenging hurdles in the development of such devices. Here we demonstrate and present detailed electrical characterization of a high-κ epitaxial oxide gate stack based on crystalline SrHfO3 grown on Ge (001) by atomic layer deposition. Metal-oxide-Ge capacitor structures show extremely low gate leakage, small and scalable EOT, and good and reducible Dit. Detailed growth strategies and postgrowth annealing schemes are demonstrated to reduce Dit. The physical mechanisms behind these phenomena are studied and suggest approaches for further reduction of Dit. PMID:26859048

  19. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

    NASA Astrophysics Data System (ADS)

    Leng, X.; Bollinger, A. T.; Božović, I.

    2016-08-01

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.

  20. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

    DOE PAGESBeta

    Leng, X.; Bozovic, I.; Bollinger, A. T.

    2016-08-10

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a puremore » electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.« less

  1. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

    PubMed Central

    Leng, X.; Bollinger, A. T.; Božović, I.

    2016-01-01

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices. PMID:27506371

  2. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films.

    PubMed

    Leng, X; Bollinger, A T; Božović, I

    2016-01-01

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices. PMID:27506371

  3. Gate stack dielectric degradation of rare-earth oxides grown on high mobility Ge substrates

    NASA Astrophysics Data System (ADS)

    Shahinur Rahman, Md.; Evangelou, E. K.; Konofaos, N.; Dimoulas, A.

    2012-11-01

    We report on the reliability characteristics and their analysis, of rare-earth oxides (REOs) dielectric degradation, when used as interfacial buffer layers together with HfO2 high-k films (REOs/HfO2) on high mobility Ge substrates. Metal-oxide-semiconductor (MOS) devices with these stacks, show dissimilar charge trapping phenomena under varying levels of constant-voltage-stress (CVS) conditions, influencing the measured densities of the interface (Nit) and border (NBT) traps. In the present study, we report on C-Vg hysteresis curves related to both Nit and NBT. We propose a new model based on the Maxwell-Wagner mechanism, and this model explains the current decay transient observed under CVS bias from low to higher fields of MOS gate stack devices grown on Ge substrates. The proposed model is unlike to those used for other MOS devices. Finally, CVS measurements for very long times at moderate fields reveal an initial current decay due to relaxation, followed by charge trapping and generation of stress-induced leakage which eventually lead to hard breakdown.

  4. Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET

    NASA Astrophysics Data System (ADS)

    Pradhan, K. P.; Priyanka; Sahu, P. K.

    2016-01-01

    Symmetric Dual-k Spacer (SDS) Trigate Wavy FinFET is a novel hybrid device that combines three significant and advanced technologies i.e., ultra-thin-body (UTB), FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. This innovative architecture promises to enhance the device performance as compared to conventional FinFET without increasing the chip area. For the first time, we have incorporated two different dielectric materials (SiO2, and HfO2) as gate oxide to analyze the effect on various performance metrics of SDS wavy FinFET. This work evaluates the response of double material gate oxide (DMGO) on parameters like mobility, on current (Ion), transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) in SDS wavy FinFET. This work also reveals the presence of biasing point i.e., zero temperature coefficient (ZTC) bias point. The ZTC bias point is that point where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performances are also subjected to extensive analysis. This further validates the reliability of DMGO-SDS FinFET and its application opportunities involved in modeling analog/RF circuits for a broad range of temperature applications. From extensive 3-D device simulation, we have determined that the inclusion of DMGO in SDS wavy FinFET is superior in performance.

  5. Transient characteristics for proton gating in laterally coupled indium-zinc-oxide transistors.

    PubMed

    Liu, Ning; Zhu, Li Qiang; Xiao, Hui; Wan, Chang Jin; Liu, Yang Hui; Chao, Jin Yu

    2015-03-25

    The control and detection over processing, transport and delivery of chemical species is of great importance in sensors and biological systems. The transient characteristics of the migration of chemical species reflect the basic properties in the processings of chemical species. Here, we observed the field-configurable proton effects in a laterally coupled transistor gated by phosphorosilicate glass (PSG). The bias on the lateral gate would modulate the interplay between protons and electrons at the PSG/indium-zinc-oxide (IZO) channel interface. Due to the modulation of protons flux within the PSG films, the IZO channel current would be modified correspondingly. The characteristic time for the proton gating is estimated to be on the order of 20 ms. Such laterally coupled oxide based transistors with proton gating are promising for low-cost portable biosensors and neuromorphic system applications. PMID:25741771

  6. Room-temperature phosphorescence logic gates developed from nucleic acid functionalized carbon dots and graphene oxide

    NASA Astrophysics Data System (ADS)

    Gui, Rijun; Jin, Hui; Wang, Zonghua; Zhang, Feifei; Xia, Jianfei; Yang, Min; Bi, Sai; Xia, Yanzhi

    2015-04-01

    Room-temperature phosphorescence (RTP) logic gates were developed using capture ssDNA (cDNA) modified carbon dots and graphene oxide (GO). The experimental results suggested the feasibility of these developed RTP-based ``OR'', ``INHIBIT'' and ``OR-INHIBIT'' logic gate operations, using Hg2+, target ssDNA (tDNA) and doxorubicin (DOX) as inputs.Room-temperature phosphorescence (RTP) logic gates were developed using capture ssDNA (cDNA) modified carbon dots and graphene oxide (GO). The experimental results suggested the feasibility of these developed RTP-based ``OR'', ``INHIBIT'' and ``OR-INHIBIT'' logic gate operations, using Hg2+, target ssDNA (tDNA) and doxorubicin (DOX) as inputs. Electronic supplementary information (ESI) available: All experimental details, Part S1-3, Fig. S1-6 and Table S1. See DOI: 10.1039/c4nr07620f

  7. Investigation of metal oxide dielectrics for non-volatile floating gate and resistance switching memory applications

    NASA Astrophysics Data System (ADS)

    Chakrabarti, Bhaswar

    Floating gate transistor based flash memories have seen more than a decade of continuous growth as the prominent non-volatile memory technology. However, the recent trends indicate that the scaling of flash memory is expected to saturate in the near future. Several alternative technologies are being considered for the replacement of flash in the near future. The basic motivation for this work is to investigate the material properties of metal oxide based high-k dielectrics for potential applications in floating gate and resistance switching memory applications. This dissertation can be divided into two main sections. In the first section, the tunneling characteristics of the SiO2/HfO 2 stacks were investigated. Previous theoretical studies for thin SiO 2/ thick high-k stacks predict an increase in tunneling current in the high-bias regime (better programming) and a decrease in the low-bias regime (better retention) in comparison to pure SiO2 of same equivalent oxide thickness (EOT). However, our studies indicated that the performance improvement in SiO2/HfO2 stacks with thick HfO2 layer is difficult due to significant amount of charge traps in thick HfO2 layers. Oxygen anneal on the stacks did not improve the programming current and retention. X-ray photoelectron spectroscopy (XPS) studies indicated that this was due to formation of an interfacial oxide layer. The second part of the dissertation deals with the investigation of resistive switching in metal oxides. Although promising, practical applications of resistive random access memories (RRAM) require addressing several issues including high forming voltage, large operating currents and reliability. We first investigated resistive switching in HfTiOx nanolaminate with conventional TiN electrodes. The forming-free switching observed in the structures could be described by the quantum point contact model. The modelling results indicated that the forming-free characteristics can be due to a higher number of

  8. Analytical Model for Direct Tunneling Gate Current in Long-Channel Undoped Cylindrical Surrounding Gate Metal-Oxide-Semiconductor Field Effect Transistors

    NASA Astrophysics Data System (ADS)

    Han, Ru; Li, Cong

    2013-02-01

    In this study, an analytical direct tunneling gate current model for long-channel undoped cylindrical surrounding gate (CSG) MOSFETs is developed. On the basis of an analytical model, the direct tunneling gate current in CSG MOSFETs is investigated. It is found that direct tunneling gate current is a strong function of gate oxide thickness, but less affected by the change in channel radius. It is also revealed that considering the influence of the source and drain, as the length of the underlap region decreases to zero, the direct tunneling gate current drastically increases. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.

  9. Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

    NASA Astrophysics Data System (ADS)

    Chun, Minkyu; Um, Jae Gwang; Park, Min Sang; Chowdhury, Md Delwar Hossain; Jang, Jin

    2016-07-01

    We report the abnormal behavior of the threshold voltage (VTH) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (VTG), while bottom gate bias (VBG) is less effect than VTG. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of In metal diffusion to the top SiO2/a-IGZO and also the existence of large amount of In+ under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH- at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of VTG both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.

  10. Oxide thinning percolation statistical model for soft breakdown in ultrathin gate oxides

    NASA Astrophysics Data System (ADS)

    Chen, Ming-Jer; Kang, Ting-Kuo; Liu, Chuan-Hsi; Chang, Yih J.; Fu, Kuan-Yu

    2000-07-01

    An existing cell-based percolation model with parameter correlation can find its potential applications in assessing soft-breakdown (BD) statistics as long as the oxide thinning due to the localized physical damage near the SiO2/Si interface is accounted for. The resulting model is expressed explicitly with the critical trap number per cell nBD and the remaining oxide thickness tox' both as parameters. Reproduction of time-to-bimodal (soft- and hard-) breakdown statistical data from 3.3-nm-thick gate-oxide samples yields nBD of 3 and 4 for soft and hard breakdown, respectively. The extracted tox' of 1.0 nm for soft breakdown, plus the transition layer thickness of 0.5 nm in the model, is fairly comparable with literature values from current-voltage fitting. The dimension and area of the localized physically damaged region or percolation path (cell) are quantified as well. Based on the work, the origins of soft and hard breakdown are clarified in the following: (i) soft breakdown behaves intrinsically as hard breakdown, that is, they share the same defect (neutral trap) generation process and follow Poisson random statistics; (ii) both are independent events corresponding to different tox' requirements; and (iii) hard breakdown takes place in a certain path located differently from that for the first soft breakdown.

  11. Chemical Gated Field Effect Transistor by Hybrid Integration of One-Dimensional Silicon Nanowire and Two-Dimensional Tin Oxide Thin Film for Low Power Gas Sensor.

    PubMed

    Han, Jin-Woo; Rim, Taiuk; Baek, Chang-Ki; Meyyappan, M

    2015-09-30

    Gas sensors based on metal-oxide-semiconductor transistor with the polysilicon gate replaced by a gas sensitive thin film have been around for over 50 years. These are not suitable for the emerging mobile and wearable sensor platforms due to operating voltages and powers far exceeding the supply capability of batteries. Here we present a novel approach to decouple the chemically sensitive region from the conducting channel for reducing the drive voltage and increasing reliability. This chemically gated field effect transistor uses silicon nanowire for the current conduction channel with a tin oxide film on top of the nanowire serving as the gas sensitive medium. The potential change induced by the molecular adsorption and desorption allows the electrically floating tin oxide film to gate the silicon channel. As the device is designed to be normally off, the power is consumed only during the gas sensing event. This feature is attractive for the battery operated sensor and wearable electronics. In addition, the decoupling of the chemical reaction and the current conduction regions allows the gas sensitive material to be free from electrical stress, thus increasing reliability. The device shows excellent gas sensitivity to the tested analytes relative to conventional metal oxide transistors and resistive sensors. PMID:26381613

  12. Electrical control of Co/Ni magnetism adjacent to gate oxides with low oxygen ion mobility

    SciTech Connect

    Yan, Y. N.; Zhou, X. J.; Li, F.; Cui, B.; Wang, Y. Y.; Wang, G. Y.; Pan, F.; Song, C.

    2015-09-21

    We investigate the electrical manipulation of Co/Ni magnetization through a combination of ionic liquid and oxide gating, where HfO{sub 2} with a low O{sup 2−} ion mobility is employed. A limited oxidation-reduction process at the metal/HfO{sub 2} interface can be induced by large electric field, which can greatly affect the saturated magnetization and Curie temperature of Co/Ni bilayer. Besides the oxidation/reduction process, first-principles calculations show that the variation of d electrons is also responsible for the magnetization variation. Our work discloses the role of gate oxides with a relatively low O{sup 2−} ion mobility in electrical control of magnetism, and might pave the way for the magneto-ionic memory with low power consumption and high endurance performance.

  13. Mechanically reliable surface oxides for high-temperature corrosion resistance

    SciTech Connect

    Natesan, K.; Veal, B.W.; Grimsditch, M.; Renusch, D.; Paulikas, A.P.

    1995-05-01

    Corrosion is widely recognized as being important, but an understanding of the underlying phenomena involves factors such as the chemistry and physics of early stages of oxidation, chemistry and bonding at the substrate/oxide interface, role of segregants on the strength of that bond, transport processes through scale, mechanisms of residual stress generation and relief, and fracture behavior at the oxide/substrate interface. Because of this complexity a multilaboratory program has been initiated under the auspices of the DOE Center of Excellence for the Synthesis and Processing of Advanced Materials, with strong interactions and cross-leveraging with DOE Fossil Energy and US industry. Objective is to systematically generate the knowledge required to establish a scientific basis for designing and synthesizing improved protective oxide scales/coatings (slow-growing, adherent, sound) on high-temperature materials without compromising the requisite properties of the bulk materials. The objectives of program work at Argonne are to (1) correlate actual corrosion performance with stresses, voids, segregants, interface roughness, initial stages of oxidation, and microstructures; (2) study such behavior in growing or as-grown films; and (3) define prescriptive design and synthesis routes to mechanically reliable surface oxides. Several techniques, such as Auger electron spectroscopy, X-ray diffraction, X-ray grazing incidence reflectance, grazing-angle X-ray fluorescence, optical fluorescence, and Raman spectroscopy, are used in the studies. Tne project has selected Fe-25 wt.% Cr-20 wt.% Ni and Fe-Cr-Al alloys, which are chromia- and alumina-formers respectively, for the studies. This paper presents some of the results on early stages of oxidation and on surface segregation of elements.

  14. Reliability characterizations and failure mechanism of ultra-thin oxides for MOS devices

    NASA Astrophysics Data System (ADS)

    Wang, Bin

    The aggressive scaling of smaller/faster logic and memory devices demands accurate reliability characterization and knowledge of the failure mechanisms of ultra-thin (<30 A) silicon dioxide (SiO 2) layers in the gates of metal-oxide semiconductor (MOS) structures. The increased occurrence of soft breakdown in ultra-thin oxide films necessitates the development of more sophisticated techniques to detect breakdown. One such technique is by interrupting stress and monitoring stress-induced leakage current (SILC) or interface state density (Dit). The effect of interrupting stress was carefully studied and determined not to affect device lifetime. A comprehensive time-dependent dielectric breakdown (TDDB) study was conducted on ultra-thin oxide over a temperature ranging from 220°C to 350°C to study temperature acceleration. The results of the study showed that both hard and soft breakdown modes exhibit the same temperature dependence. The choice of a failure model for time/charge to breakdown (tBD /QBD) is critical for accurate reliability extrapolation. In this work, two more experiments were carried out to clarify the current physical mechanisms responsible to dielectric wear-out. The first experiment investigated the effects of pulsed biased stress on device lifetime. A lifetime enhancement under bipolar pulse stress was observed. The results suggest that previously proposed mechanism of hole de-trapping in thick oxide may not be responsible for the lifetime increase observed here for ultra-thin oxides. The second experiment studied the effects of heavy ion on the reliability of ultra-thin SiO2. Annealing and electron injection experiments on irradiated devices with heavy ion implied that holes were significantly created and trapped inside SiO2 without causing the SiO2 to breakdown. The results from these two studies suggest that breakdown of ultra-thin oxides is not caused by holes and that the anode hole injection (AHI) model for constant voltage stress (CVS) is

  15. Highly Reliable Liquid-Phase-Deposited SiO2 with Nitrous Oxide Plasma Post-Treatment for Low-Temperature-Processed Polysilicon Thin Film Transistors

    NASA Astrophysics Data System (ADS)

    Yeh, Ching-Fa; Chen, Darren Chi-Hsiang; Lu, Cheng-Yu; Liu, Chung; Lee, Su-Tseng; Liu, Cheng-Hong; Chen, Tai-Ju

    2002-10-01

    Low-temperature (˜300°C) N2O-plasma post-treatment for liquid-phase-deposited (LPD) gate oxide has been proposed for the first time. This treatment successfully takes the place of conventional furnace annealing in O2 ambient. Results of physicochemical and electrical characteristics show that N2O-plasma post-treated LPD-SiO2 has a high electrical breakdown field and low interface state density. In addition, N2O-plasma treatment also improves the Si-rich phenomenon of LPD-SiO2. From the comparison with pure N2O-plasma oxidation film, LPD-SiO2 with its short re-oxidation time in N2O plasma plays an important role in relieving interfacial stress. Finally, the novel technology is applied to the gate oxide of low-temperature-processed (LTP) polysilicon thin film transistors (poly-Si TFTs). The device performance reveals excellent electrical characteristics, and the reliability shows a satisfactory result, as well as the gate oxide reliability. It is believed that the N2O-plasma post-treatment not only improves the oxide quality, but also effectively passivates the trap states of poly-Si TFTs.

  16. Direct deposition of aluminum oxide gate dielectric on graphene channel using nitrogen plasma treatment

    SciTech Connect

    Lim, Taekyung; Kim, Dongchool; Ju, Sanghyun

    2013-07-01

    Deposition of high-quality dielectric on a graphene channel is an essential technology to overcome structural constraints for the development of nano-electronic devices. In this study, we investigated a method for directly depositing aluminum oxide (Al{sub 2}O{sub 3}) on a graphene channel through nitrogen plasma treatment. The deposited Al{sub 2}O{sub 3} thin film on graphene demonstrated excellent dielectric properties with negligible charge trapping and de-trapping in the gate insulator. A top-gate-structural graphene transistor was fabricated using Al{sub 2}O{sub 3} as the gate dielectric with nitrogen plasma treatment on graphene channel region, and exhibited p-type transistor characteristics.

  17. Dual Gate Thin Film Transistors Based on Indium Oxide Active Layers

    SciTech Connect

    Kekuda, Dhananjaya; Rao, K. Mohan; Tolpadi, Amita; Chu, C. W.

    2011-07-15

    Polycrystalline Indium Oxide (In{sub 2}O{sub 3}) thin films were employed as an active channel layer for the fabrication of bottom and top gate thin film transistors. While conventional SiO{sub 2} served as a bottom gate dielectric, cross-linked poly-4-vinylphenol (PVP) was used a top gate dielectric. These nano-crystalline TFTs exhibited n-channel behavior with their transport behavior highly dependent on the thickness of the channel. The correlation between the thickness of the active layer and TFT parameters such as on/off ratio, field-effect mobility, threshold voltage were carried out. The optical spectra revealed a high transmittance in the entire visible region, thus making them promising candidates for the display technology.

  18. Characterization of reliability of printed indium tin oxide thin films.

    PubMed

    Hong, Sung-Jei; Kim, Jong-Woong; Jung, Seung-Boo

    2013-11-01

    Recently, decreasing the amount of indium (In) element in the indium tin oxide (ITO) used for transparent conductive oxide (TCO) thin film has become necessary for cost reduction. One possible approach to this problem is using printed ITO thin film instead of sputtered. Previous studies showed potential for printed ITO thin films as the TCO layer. However, nothing has been reported on the reliability of printed ITO thin films. Therefore, in this study, the reliability of printed ITO thin films was characterized. ITO nanoparticle ink was fabricated and printed onto a glass substrate followed by heating at 400 degrees C. After measurement of the initial values of sheet resistance and optical transmittance of the printed ITO thin films, their reliabilities were characterized with an isothermal-isohumidity test for 500 hours at 85 degrees C and 85% RH, a thermal shock test for 1,000 cycles between 125 degrees C and -40 degrees C, and a high temperature storage test for 500 hours at 125 degrees C. The same properties were investigated after the tests. Printed ITO thin films showed stable properties despite extremely thermal and humid conditions. Sheet resistances of the printed ITO thin films changed slightly from 435 omega/square to 735 omega/square 507 omega/square and 442 omega/square after the tests, respectively. Optical transmittances of the printed ITO thin films were slightly changed from 84.74% to 81.86%, 88.03% and 88.26% after the tests, respectively. These test results suggest the stability of printed ITO thin film despite extreme environments. PMID:24245331

  19. Note: Design and construction of a simple and reliable printed circuit board-substrate Bradbury-Nielsen gate for ion mobility spectrometry

    NASA Astrophysics Data System (ADS)

    Du, Yongzhai; Cang, Huaiwen; Wang, Weiguo; Han, Fenglei; Chen, Chuang; Li, Lin; Hou, Keyong; Li, Haiyang

    2011-08-01

    A less laborious, structure-simple, and performance-reliable printed circuit board (PCB) based Bradbury-Nielsen gate for high-resolution ion mobility spectrometry was introduced and investigated. The gate substrate was manufactured using a PCB etching process with small holes (Φ 0.1 mm) drilled along the gold-plated copper lines. Two interdigitated sets of rigid stainless steel spring wire (Φ 0.1 mm) that stands high temperature and guarantees performance stability were threaded through the holes. Our homebuilt ion mobility spectrometer mounted with the gate gave results of about 40 for resolution while keeping a signal intensity of over 0.5 nano-amperes.

  20. Effect of reverse body bias on hot-electron-induced punchthrough reliability of pMOSFETs with thin gate dielectric at high temperatures

    NASA Astrophysics Data System (ADS)

    Kang, YongHa; Kim, JongKyun; Lee, NamHyun; Oh, MinGeon; Hwang, YuChul; Moon, ByungMoo

    2016-06-01

    The effect of the reverse body bias V SB on the hot-electron-induced punch-through (HEIP) reliability of pMOSFETs with a thin gate dielectric at high temperatures was investigated for the first time. Experimental results indicate that the reverse V SB increased the HEIP degradation for a thin pMOSFET because of the increase in the maximum electric field E m due to the increase in the threshold voltage V th. The sensitivity of HEIP degradation to V SB increased with increasing body effect coefficient γ at a given oxide thickness T ox. However, a thin device (22 Å) showed a much stronger dependence of HEIP degradation on V SB due to the decrease in the velocity saturation length l, although it had a smaller γ than a thick device (60 Å). These new observations suggest that the body bias technique for improving circuit performance can cause a reliability problem of nanoscale pMOSFETs at high temperatures and impose a significant limitation on CMOS device scaling.

  1. In-line 90 nm Technology Gate Oxide Nitrogen Monitoring With Non-Contact Electrical Technique

    NASA Astrophysics Data System (ADS)

    Pic, Nicolas; Polisski, Gennadi; Paire, Emmanuel; Rizzo, Véronique; Grosjean, Catherine; Bortolotti, Benjamin; D'Amico, John; Cabuil, Nicolas

    2009-09-01

    The continuous race to reduce the dimensions of IC components has lead to the introduction of Nitrogen in the thin gate oxide layer in order to increase the dielectric constant and to improve the gate dielectric properties. It is mandatory to apply in-line monitoring to control the amount of Nitrogen to ensure that electrical behavior is correct over time. Historically, this monitoring was performed by measuring the delay to reoxidation (D2R) with an ellipsometer. But, this method is not suitable in production as it is depending on both initial oxidation and reoxidation reproducibility, which implies implementing dedicated Statistical Process Control (SPC) monitoring at these two specific processing steps. We are here presenting an alternative method to D2R for 90 nm Technology gate oxide grown by Rapid Thermal Process (RTP). Applying a non-contact Metrology technique, which couples Kelvin probe surface voltage measurement with surface Corona deposition, directly after the nitridation step, the interface trapped charge (QIT) is obtained by integration of the interface state density over the space charge region. In summary, this electrical non-contact monitoring is more sensitive to the Nitrogen content compared to ellipsometer measurement after nitridation or after D2R, less sensitive compared to D2R to any initial oxide variation, and it allows simplification of the qualification procedure at this process step by skipping the reoxidation.

  2. Band offsets of a ruthenium gate on ultrathin high-{kappa} oxide films on silicon

    SciTech Connect

    Rangan, Sylvie; Bersch, Eric; Bartynski, Robert Allen; Garfunkel, Eric; Vescovo, Elio

    2009-02-15

    Valence-band and conduction-band edges of ultrathin oxides (SiO{sub 2}, HfO{sub 2}, Hf{sub 0.7}Si{sub 0.3}O{sub 2}, and Al{sub 2}O{sub 3} grown on silicon) and their shifts upon sequential metallization with ruthenium have been measured using synchrotron-radiation-excited x-ray, ultraviolet, and inverse photoemissions. From these techniques, the offsets between the valence-band and conduction-band edges of the oxides, and the ruthenium metal gate Fermi edge have been directly measured. In addition the core levels of the oxides and the ruthenium have been characterized. Upon deposition, Ru remains metallic and no chemical alteration of the underlying oxide gates, or interfacial SiO{sub 2} in the case of the high-{kappa} thin films, can be detected. However a clear shift of the band edges is measured for all samples due to the creation of an interface dipole at the ruthenium-oxide interface. Using the energy gap, the electron affinity of the oxides, and the ruthenium work function that have been directly measured on these samples, the experimental band offsets are compared to those predicted by the induced gap states model.

  3. Band Offsets of a Ruthenium Gate on Ultrathin High-k Oxide Films on Silicon

    SciTech Connect

    Rangan, S.; Bersch, W; Bartynski, R; Garfunkel, E; Vescovo, E

    2009-01-01

    Valence-band and conduction-band edges of ultrathin oxides and their shifts upon sequential metallization with ruthenium have been measured using synchrotron-radiation-excited x-ray, ultraviolet, and inverse photoemissions. From these techniques, the offsets between the valence-band and conduction-band edges of the oxides, and the ruthenium metal gate Fermi edge have been directly measured. In addition the core levels of the oxides and the ruthenium have been characterized. Upon deposition, Ru remains metallic and no chemical alteration of the underlying oxide gates, or interfacial SiO{sub 2} in the case of the high-? thin films, can be detected. However a clear shift of the band edges is measured for all samples due to the creation of an interface dipole at the ruthenium-oxide interface. Using the energy gap, the electron affinity of the oxides, and the ruthenium work function that have been directly measured on these samples, the experimental band offsets are compared to those predicted by the induced gap states model.

  4. Total-dose and charge-trapping effects in gate oxides for CMOS LSI devices

    SciTech Connect

    Singh, R.S.; Kaputa, D.J.; Korman, C.S.; Surowiec, E.P.

    1984-12-01

    The effect of gamma irradiation on CMOS devices fabricated using 3 Micron CMOS BULK process has been studied as a function of gate oxide processing and subsequent annealing. Threshold shifts, speed degradation, and power supply currents were measured as a function of total dose up to 10/sup 6/ Rad (Si). Using hot electron injection techniques, trapping densities and capture cross-sections of the traps in each oxide type have been determined at pre- and post-irradiation levels. Power supply leakage and speed performance of the devices were recovered within three to five hours by annealing them at 125/sup 0/C, +10 V bias.

  5. Effect of low and high temperature anneal on process-induced damage of gate oxide

    SciTech Connect

    King, J.C.; Hu, C. . Dept. of Electrical Engineering and Computer Sciences)

    1994-11-01

    The authors have investigated the ability of high and low temperature anneals to repair the gate oxide damage due to simulated electrical stress caused by wafer charging resulting from plasma etching, etc. Even 800 C anneal cannot restore the stability in interface trap generation. Even 900 C anneal cannot repair the deteriorated charge-to-breakdown and oxide charge trapping. As a small consolation, the ineffectiveness of anneal in repairing the process-induced damage allows them to monitor the damages even at the end of the fabrication process.

  6. The interfaces of lanthanum oxide-based subnanometer EOT gate dielectrics

    PubMed Central

    2014-01-01

    When pushing the gate dielectric thickness of metal-oxide-semiconductor (MOS) devices down to the subnanometer scale, the most challenging issue is the interface. The interfacial transition layers between the high-k dielectric/Si and between the high-k dielectric/gate metal become the critical constraints for the smallest achievable film thickness. This work presents a detailed study on the interface bonding structures of the tungsten/lanthanum oxide/silicon (W/La2O3/Si) MOS structure. We found that both W/La2O3 and La2O3/Si are thermally unstable. Thermal annealing can lead to W oxidation and the forming of a complex oxide layer at the W/La2O3 interface. For the La2O3/Si interface, thermal annealing leads to a thick low-k silicate layer. These interface layers do not only cause significant device performance degradation, but also impose a limit on the thinnest equivalent oxide thickness (EOT) to be achievable which may be well above the requirements of our future technology nodes. PMID:25246873

  7. Direct Imaging of Nanoscale Conductance Evolution in Ion-Gel-Gated Oxide Transistors.

    PubMed

    Ren, Yuan; Yuan, Hongtao; Wu, Xiaoyu; Chen, Zhuoyu; Iwasa, Yoshihiro; Cui, Yi; Hwang, Harold Y; Lai, Keji

    2015-07-01

    Electrostatic modification of functional materials by electrolytic gating has demonstrated a remarkably wide range of density modulation, a condition crucial for developing novel electronic phases in systems ranging from complex oxides to layered chalcogenides. Yet little is known microscopically when carriers are modulated in electrolyte-gated electric double-layer transistors (EDLTs) due to the technical challenge of imaging the buried electrolyte-semiconductor interface. Here, we demonstrate the real-space mapping of the channel conductance in ZnO EDLTs using a cryogenic microwave impedance microscope. A spin-coated ionic gel layer with typical thicknesses below 50 nm allows us to perform high resolution (on the order of 100 nm) subsurface imaging, while maintaining the capability of inducing the metal-insulator transition under a gate bias. The microwave images vividly show the spatial evolution of channel conductance and its local fluctuations through the transition as well as the uneven conductance distribution established by a large source-drain bias. The unique combination of ultrathin ion-gel gating and microwave imaging offers a new opportunity to study the local transport and mesoscopic electronic properties in EDLTs. PMID:26061780

  8. High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

    PubMed

    Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

    2015-07-01

    A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications. PMID:26039187

  9. Gate controllable resistive random access memory devices using reduced graphene oxide

    NASA Astrophysics Data System (ADS)

    Hazra, Preetam; Resmi, A. N.; Jinesh, K. B.

    2016-04-01

    The biggest challenge in the resistive random access memory (ReRAM) technology is that the basic operational parameters, such as the set and reset voltages, the current on-off ratios (hence the power), and their operational speeds, strongly depend on the active and electrode materials and their processing methods. Therefore, for its actual technological implementations, the unification of the operational parameters of the ReRAM devices appears to be a difficult task. In this letter, we show that by fabricating a resistive memory device in a thin film transistor configuration and thus applying an external gate bias, we can control the switching voltage very accurately. Taking partially reduced graphene oxide, the gate controllable switching is demonstrated, and the possible mechanisms are discussed.

  10. New Trap-Assisted Band-to-Band Tunneling Induced Gate Current Model for P-Channel Metal-Oxide-Semiconductor Field Effect Transistors with Sub-3 nm Oxides

    NASA Astrophysics Data System (ADS)

    Lee, Hai-Ming; Liu, Cheng-Jye; Hsu, Chih-Wei; Liang, Mong-Song; King, Ya-Chin; Hsu, Charles Ching-Hsiang

    2001-03-01

    A new trap-assisted band-to-band tunneling (TAB) gate current model is proposed to describe the new observed band-to-band tunneling (BBT) induced gate current characteristics of p-channel metal-oxide-semiconductor field effect transistors (PMOSFET’s) with ultra-thin gate oxide. Based on this new TAB gate current model, the off-state gate currents of PMOSFET’s with various sub-3 nm gate oxides can be well characterized, while the conventional BBT current model is no longer applicable in this regime.

  11. Random Interface-Traps-Induced Electrical Characteristic Fluctuation in 16-nm-Gate High-κ/Metal Gate Complementary Metal-Oxide-Semiconductor Device and Inverter Circuit

    NASA Astrophysics Data System (ADS)

    Li, Yiming; Cheng, Hui-Wen

    2012-04-01

    This work estimates electrical and transfer-characteristic fluctuations in 16-nm-gate high-κ/metal gate (HKMG) metal-oxide-semiconductor field effect transistor (MOSFET) devices and inverter circuit induced by random interface traps (ITs) at high-κ/silicon interface. Randomly generated devices with two-dimensional (2D) ITs at HfO2/Si interface are incorporated into quantum-mechanically corrected 3D device simulation. Device characteristics, as influenced by different degrees of fluctuation, are discussed in relation to random ITs near source and drain ends. Owing to a decreasing penetration of electric field from drain to source, the drain induced barrier lowering (DIBL) of the edvice decreases when the number of ITs increases. In contrast to random-dopant fluctuation, the screening effect of device's inversion layer cannot effectively screen potential's variation; thus, devices still have noticeable fluctuation of gate capacitance (CG) under high gate bias. The cutoff frequency decreases as increasing the number of ITs owing to the decreasing transconductance and increasing CG. Decreasing on-state current and increasing CG further result in increasing intrinsic gate delay time (τ) when the number of ITs increases. The fluctuation magnitude of DIBL, cutoff frequency, and τ above is increased as the number of ITs increases. Even for cases with the same number of random ITs, noise margins (NMs) of the 16-nm-gate complementary metal-oxide-semiconductor inverter circuit are still quite different due to the different distribution of random ITs. The NMs of inverter circuit increase as the number of random ITs increases; however, the NMs' fluctuations are increased due to the more sources of fluctuation at HfO2/Si interface of HKMG devices.

  12. Quantum-Mechanical Simulation of Gate Tunneling Current in Accumulated n-Channel Metal-Oxide-Semiconductor Devices with n+-Polysilicon Gates

    NASA Astrophysics Data System (ADS)

    Iwata, Hideyuki; Matsuda, Toshihiro; Ohzone, Takashi

    2002-08-01

    The gate tunneling current in n+-polysilicon gate n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) in accumulation regime has been simulated quantum-mechanically. The two current components, due to hole tunneling from the accumulation layer on the p-silicon surface and due to electron tunneling from the accumulation layer on the n+-polysilicon gate, have been investigated for bulk and silicon-on-insulator (SOI) MOSFETs with various SOI layer thicknesses. For bulk MOSFETs, the electron current from the gate becomes much larger than the hole current from the silicon surface. On the other hand, as the SOI layer thickness (tSOI) decreases, the hole current increases, but the electron current decreases, and thus the hole current exceeds the electron current at a certain tSOI. The total gate current increases with decreasing tSOI (>2 nm). For extremely thin tSOI, the contribution of the electron current almost disappears. Moreover, the quantum-mechanical effects on the tunneling current in accumulated SOI MOSFETs have been discussed in detail.

  13. Al and Ge simultaneous oxidation using neutral beam post-oxidation for formation of gate stack structures

    SciTech Connect

    Ohno, Takeo; Nakayama, Daiki; Samukawa, Seiji

    2015-09-28

    To obtain a high-quality Germanium (Ge) metal–oxide–semiconductor structure, a Ge gate stacked structure was fabricated using neutral beam post-oxidation. After deposition of a 1-nm-thick Al metal film on a Ge substrate, simultaneous oxidation of Al and Ge was carried out at 300 °C, and a Ge oxide film with 29% GeO{sub 2} content was obtained by controlling the acceleration bias power of the neutral oxygen beam. In addition, the fabricated AlO{sub x}/GeO{sub x}/Ge structure achieved a low interface state density of less than 1 × 10{sup 11 }cm{sup −2 }eV{sup −1} near the midgap.

  14. Top-gate zinc tin oxide thin-film transistors with high bias and environmental stress stability

    NASA Astrophysics Data System (ADS)

    Fakhri, M.; Theisen, M.; Behrendt, A.; Görrn, P.; Riedl, T.

    2014-06-01

    Top gated metal-oxide thin-film transistors (TFTs) provide two benefits compared to their conventional bottom-gate counterparts: (i) The gate dielectric may concomitantly serve as encapsulation layer for the TFT channel. (ii) Damage of the dielectric due to high-energetic particles during channel deposition can be avoided. In our work, the top-gate dielectric is prepared by ozone based atomic layer deposition at low temperatures. For ultra-low gas permeation rates, we introduce nano-laminates of Al2O3/ZrO2 as dielectrics. The resulting TFTs show a superior environmental stability even at elevated temperatures. Their outstanding stability vs. bias stress is benchmarked against bottom-gate devices with encapsulation.

  15. Top-gate zinc tin oxide thin-film transistors with high bias and environmental stress stability

    SciTech Connect

    Fakhri, M.; Theisen, M.; Behrendt, A.; Görrn, P.; Riedl, T.

    2014-06-23

    Top gated metal-oxide thin-film transistors (TFTs) provide two benefits compared to their conventional bottom-gate counterparts: (i) The gate dielectric may concomitantly serve as encapsulation layer for the TFT channel. (ii) Damage of the dielectric due to high-energetic particles during channel deposition can be avoided. In our work, the top-gate dielectric is prepared by ozone based atomic layer deposition at low temperatures. For ultra-low gas permeation rates, we introduce nano-laminates of Al{sub 2}O{sub 3}/ZrO{sub 2} as dielectrics. The resulting TFTs show a superior environmental stability even at elevated temperatures. Their outstanding stability vs. bias stress is benchmarked against bottom-gate devices with encapsulation.

  16. Control of interfacial properties of Pr-oxide/Ge gate stack structure by introduction of nitrogen

    NASA Astrophysics Data System (ADS)

    Kato, Kimihiko; Kondo, Hiroki; Sakashita, Mitsuo; Nakatsuka, Osamu; Zaima, Shigeaki

    2011-06-01

    We have demonstrated the control of interfacial properties of Pr-oxide/Ge gate stack structure by the introduction of nitrogen. From C- V characteristics of Al/Pr-oxide/Ge 3N 4/Ge MOS capacitors, the interface state density decreases without the change of the accumulation capacitance after annealing. The TEM and TED measurements reveal that the crystallization of Pr-oxide is enhanced with annealing and the columnar structure of cubic-Pr 2O 3 is formed after annealing. From the depth profiles measured using XPS with Ar sputtering for the Pr-oxide/Ge 3N 4/Ge stack structure, the increase in the Ge component is not observed in a Pr-oxide film and near the interface between a Pr-oxide film and a Ge substrate. In addition, the N component segregates near the interface region, amorphous Pr-oxynitride (PrON) is formed at the interface. As a result, Pr-oxide/PrON/Ge stacked structure without the Ge-oxynitride interlayer is formed.

  17. Study of charge control and gate tunneling in a ferroelectric-oxide-silicon field effect transistor: Comparison with a conventional metal-oxide-silicon structure

    NASA Astrophysics Data System (ADS)

    Lin, Yih-Yin; Zhang, Yifei; Singh, Jasprit; York, Robert; Mishra, Umesh

    2001-02-01

    It is known that conventional metal-oxide-silicon (MOS) devices will have gate tunneling related problems at very thin oxide thicknesses. Various high-dielectric-constant materials are being examined to suppress the gate currents. In this article we present theoretical results of a charge control and gate tunneling model for a ferroelectric-oxide-silicon field effect transistor and compare them to results for a conventional MOS device. The potential of high polarization charge to induce inversion without doping and high dielectric constant to suppress tunneling current is explored. The model is based on a self-consistent solution of the quantum problem and includes the ferroelectric hysteresis response self-consistently. We show that the polarization charge associated with ferroelectrics can allow greater controllability of the inversion layer charge density. Also the high dielectric constant of ferroelectrics results in greatly suppressed gate current.

  18. Trap Profiling Based on Frequency Varied Charge Pumping Method for Hot Carrier Stressed Thin Gate Oxide Metal Oxide Semiconductors Field Effect Transistors.

    PubMed

    Choi, Pyungho; Kim, Hyunjin; Kim, Sangsub; Kim, Soonkon; Javadi, Reza; Park, Hyoungsun; Choi, Byoungdeog

    2016-05-01

    In this study, pulse frequency and reverse bias voltage is modified in charge pumping and advanced technique is presented to extract oxide trap profile in hot carrier stressed thin gate oxide metal oxide semiconductor field effect transistors (MOSFETs). Carrier trapping-detrapping in a gate oxide was analyzed after hot carrier stress and the relationship between trapping depth and frequency was investigated. Hot carrier induced interface traps appears in whole channel area but induced border traps mainly appears in above pinch-off region near drain and gradually decreases toward center of the channel. Thus, hot carrier stress causes interface trap generation in whole channel area while most border trap generation occurs in the drain region under the gate. Ultimately, modified charge pumping method was performed to get trap density distribution of hot carrier stressed MOSFET devices, and the trapping-detrapping mechanism is also analyzed. PMID:27483833

  19. Lanthanide-based oxides and silicates for high-kappa gate dielectric applications

    NASA Astrophysics Data System (ADS)

    Jur, Jesse Stephen

    The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high current leakage between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high-kappa dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-kappa dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. In this work, lanthanum oxide films have been deposited by thermal evaporation on to a pre-grown chemical oxide layer on silicon. It is observed that the SiO2 interfacial layer can be consumed by a low-temperature reaction with lanthanum oxide to produce a high-quality silicate. This is opposed to depositing lanthanum oxide directly on silicon, which can possibly favor silicide formation. The importance of oxygen regulation in the surrounding environment of the La2O3-SiO2 reaction-anneal is observed. By controlling the oxygen available during the reaction, SiO2 growth can be limited to achieve high stoichiometric ratios of La2O 3 to SiO2. As a result, MOS devices with an equivalent oxide thickness (EOT) of 5 A and a leakage current density of 5.0 A/cm 2 are attained. This data equals the best value achieved in this field and is a

  20. Lateral-coupling coplanar-gate oxide-based thin-film transistors on bare paper substrates

    NASA Astrophysics Data System (ADS)

    Wu, Guodong; Wan, Xiang; Yang, Yi; Jiang, Shuanghe

    2014-11-01

    For conventional thin-film transistors (TFTs), bottom-gate or top-gate configuration is always adopted because the channel current is generally controlled by vertical capacitive coupling. In this article, depending on huge lateral electric-double-layer (EDL) capacitor induced by spatial movement of protons in phosphosilicate glass (PSG) solid electrolyte dielectrics, coplanar-gate indium-zinc-oxide (IZO)-TFTs based on the lateral capacitive coupling were fabricated on bare paper substrates. The PSG solid electrolyte films here were used at the same time as gate dielectrics and smooth buffer layers. These TFTs showed a low-voltage operation of only 1 V with a large field-effect mobility of 13.4 cm2 V-1·s, a high current on/off ratio of 6  ×  106 and a small subthreshold swing of 75 mV/decade. Furthermore, with introducing another coplanar gate, AND logic operation was also demonstrated on the coplanar dual-gate TFTs. These simple lateral-coupling coplanar-gate IZO-TFTs on bare paper substrates are very promising for low-cost portable sensors and bio-electronics.

  1. Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

    SciTech Connect

    Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

    2009-11-30

    We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgO{sub x} and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgO{sub x} gate operates under low voltage write-erase (WR-ER) pulse of {+-}20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of {+-}70 V for WR and ER states. Both devices stably operated under visible illuminations.

  2. Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics.

    PubMed

    Park, Sungjun; Lee, SeYeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

    2015-01-01

    Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 10(7), and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo. PMID:26271456

  3. Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics

    NASA Astrophysics Data System (ADS)

    Park, Sungjun; Lee, Seyeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

    2015-08-01

    Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 107, and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo.

  4. Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics

    PubMed Central

    Park, Sungjun; Lee, SeYeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

    2015-01-01

    Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 107, and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo. PMID:26271456

  5. Evolution of Insulator-Metal Phase Transitions in Epitaxial Tungsten Oxide Films during Electrolyte-Gating.

    PubMed

    Nishihaya, Shinichi; Uchida, Masaki; Kozuka, Yusuke; Iwasa, Yoshihiro; Kawasaki, Masashi; Nishihaya, S; Uchida, M; Kozuka, Y; Iwasa, Y; Kawasaki, M; Iwasa, Y; Kawasaki, M

    2016-08-31

    An interface between an oxide and an electrolyte gives rise to various processes as exemplified by electrostatic charge accumulation/depletion and electrochemical reactions such as intercalation/decalation under electric field. Here we directly compare typical device operations of those in electric double layer transistor geometry by adopting A-site vacant perovskite WO3 epitaxial thin films as a channel material and two different electrolytes as gating agent. In situ measurements of X-ray diffraction and channel resistance performed during the gating revealed that in both the cases WO3 thin film reaches a new metallic state through multiple phase transitions, accompanied by the change in out-of-plane lattice constant. Electrons are electrostatically accumulated from the interface side with an ionic liquid, while alkaline metal ions are more uniformly intercalated into the film with a polymer electrolyte. We systematically demonstrate this difference in the electrostatic and electrochemical processes, by comparing doped carrier density, lattice deformation behavior, and time constant of the phase transitions. PMID:27502546

  6. Multiplexed aptasensors and amplified DNA sensors using functionalized graphene oxide: application for logic gate operations.

    PubMed

    Liu, Xiaoqing; Aizen, Ruth; Freeman, Ronit; Yehezkeli, Omer; Willner, Itamar

    2012-04-24

    Graphene oxide (GO) is implemented as a functional matrix for developing fluorescent sensors for the amplified multiplexed detection of DNA, aptamer-substrate complexes, and for the integration of predesigned DNA constructs that activate logic gate operations. Fluorophore-labeled DNA strands acting as probes for two different DNA targets are adsorbed onto GO, leading to the quenching of the luminescence of the fluorophores. Desorption of the probes from the GO, through hybridization with the target DNAs, leads to the fluorescence of the respective label. By coupling exonuclease III, Exo III, to the system, the recycling of the target DNAs is demonstrated, and this leads to the amplified detection of the DNA targets (detection limit 5 × 10(-12) M). Similarly, adsorption of fluorophore-functionalized aptamers against thrombin or ATP onto the GO leads to the desorption of the aptamer-substrate complexes from GO and to the triggering of the luminescence corresponding to the respective fluorophore, thus, allowing the multiplexed analysis of the aptamer-substrate complexes. By designing functional fluorophore-labeled DNA constructs and their interaction with GO, in the presence (or absence) of nucleic acids, or two different substrates for aptamers, as inputs, the activation of the "OR" and "AND" logic gates is demonstrated. PMID:22404375

  7. Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

    NASA Astrophysics Data System (ADS)

    Inaba, Masafumi; Muta, Tsubasa; Kobayashi, Mikinori; Saito, Toshiki; Shibata, Masanobu; Matsumura, Daisuke; Kudo, Takuya; Hiraiwa, Atsushi; Kawarada, Hiroshi

    2016-07-01

    The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al2O3. Using Al2O3 as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

  8. High performance high-κ/metal gate complementary metal oxide semiconductor circuit element on flexible silicon

    NASA Astrophysics Data System (ADS)

    Torres Sevilla, G. A.; Almuslem, A. S.; Gumus, A.; Hussain, A. M.; Cruz, M. E.; Hussain, M. M.

    2016-02-01

    Thinned silicon based complementary metal oxide semiconductor (CMOS) electronics can be physically flexible. To overcome challenges of limited thinning and damaging of devices originated from back grinding process, we show sequential reactive ion etching of silicon with the assistance from soft polymeric materials to efficiently achieve thinned (40 μm) and flexible (1.5 cm bending radius) silicon based functional CMOS inverters with high-κ/metal gate transistors. Notable advances through this study shows large area of silicon thinning with pre-fabricated high performance elements with ultra-large-scale-integration density (using 90 nm node technology) and then dicing of such large and thinned (seemingly fragile) pieces into smaller pieces using excimer laser. The impact of various mechanical bending and bending cycles show undeterred high performance of flexible silicon CMOS inverters. Future work will include transfer of diced silicon chips to destination site, interconnects, and packaging to obtain fully flexible electronic systems in CMOS compatible way.

  9. Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

    NASA Astrophysics Data System (ADS)

    Lee, Eunji; Chowdhury, Md Delwar Hossain; Park, Min Sang; Jang, Jin

    2015-12-01

    We have studied the effect of top gate bias (VTG) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm2 intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the VTG from -15 to +15 V. By changing VTG from negative to positive, the Fermi level (EF) shifts toward conduction band edge (EC), which substantially controls the conversion of neutral vacancy to charged one (VO → VO+/VO2+ + e-/2e-), peroxide (O22-) formation or conversion of ionized interstitial (Oi2-) to neutral interstitial (Oi), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows -2.7 V shift at VTG = -15 V, which gradually decreases to -0.42 V shift at VTG = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (VO+/VO2+/O22-/Oi) and/or hole trapping in the a-IGZO /interfaces.

  10. Thermally stable, sub-nanometer equivalent oxide thickness gate stack for gate-first In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors

    NASA Astrophysics Data System (ADS)

    El Kazzi, M.; Czornomaz, L.; Rossel, C.; Gerl, C.; Caimi, D.; Siegwart, H.; Fompeyrine, J.; Marchiori, C.

    2012-02-01

    Metal-oxide-semiconductor (MOS) capacitors were fabricated by depositing composite 2 nm HfO2/1 nm Al2O3/1 nm a-Si gate stacks on p-In0.53Ga0.47As/InP (001) substrates. Thanks to the presence of the Al2O3 barrier layer, a minimum amount of the a-Si passivating layer is oxidized during the whole fabrication process. The capacitors exhibit excellent electrical characteristics with scaled equivalent oxide thickness (EOT) of 0.89 nm and mid-gap interface state density of 5 × 1011 eV-1 cm-2 upon post-metallization anneal up to 550 °C. Gate-first, self-aligned MOS field-effect-transistors were fabricated with a similar 5 nm HfO2/1 nm Al2O3/1 nm a-Si gate stack and raised source and drain (600 °C for 30 min). Owing to the excellent thermal stability of the stack, no degradation of the gate stack/semiconductor interface is observed, as demonstrated by the excellent capacitance vs voltage characteristics and the good mobility values (peak at 1030 cm2 V-1 s-1 and 740 cm2 V-1 s-1 at carrier density of 6.5 × 1012 cm-2) for a 1.3 nm EOT.

  11. A stable ATP binding to the nucleotide binding domain is important for reliable gating cycle in an ABC transporter CFTR

    PubMed Central

    Shimizu, Hiroyasu; Yu, Ying-Chun; Kono, Koichi; Kubota, Takahiro; Yasui, Masato; Li, Min

    2016-01-01

    Cystic fibrosis transmembrane conductance regulator (CFTR) anion channel, a member of ABC transporter superfamily, gates following ATP-dependent conformational changes of the nucleotide binding domains (NBD). Reflecting the hundreds of milliseconds duration of the channel open state corresponding to the dimerization of two NBDs, macroscopic WT-CFTR currents usually showed a fast, single exponential relaxation upon removal of cytoplasmic ATP. Mutations of tyrosine1219, a residue critical for ATP binding in second NBD (NBD2), induced a significant slow phase in the current relaxation, suggesting that weakening ATP binding affinity at NBD2 increases the probability of the stable open state. The slow phase was effectively diminished by a higher affinity ATP analogue. These data suggest that a stable binding of ATP to NBD2 is required for normal CFTR gating cycle, andthat the instability of ATP binding frequently halts the gating cycle in the open state presumably through a failure of ATP hydrolysis at NBD2. PMID:20628841

  12. A stable ATP binding to the nucleotide binding domain is important for reliable gating cycle in an ABC transporter CFTR.

    PubMed

    Shimizu, Hiroyasu; Yu, Ying-Chun; Kono, Koichi; Kubota, Takahiro; Yasui, Masato; Li, Min; Hwang, Tzyh-Chang; Sohma, Yoshiro

    2010-09-01

    Cystic fibrosis transmembrane conductance regulator (CFTR) anion channel, a member of ABC transporter superfamily, gates following ATP-dependent conformational changes of the nucleotide binding domains (NBD). Reflecting the hundreds of milliseconds duration of the channel open state corresponding to the dimerization of two NBDs, macroscopic WT-CFTR currents usually showed a fast, single exponential relaxation upon removal of cytoplasmic ATP. Mutations of tyrosine1219, a residue critical for ATP binding in second NBD (NBD2), induced a significant slow phase in the current relaxation, suggesting that weakening ATP binding affinity at NBD2 increases the probability of the stable open state. The slow phase was effectively diminished by a higher affinity ATP analogue. These data suggest that a stable binding of ATP to NBD2 is required for normal CFTR gating cycle, andthat the instability of ATP binding frequently halts the gating cycle in the open state presumably through a failure of ATP hydrolysis at NBD2. PMID:20628841

  13. Characterization of high-k gate dielectrics based on hafnium oxide and titanium oxide for CMOS application

    NASA Astrophysics Data System (ADS)

    Lee, Sanghyun

    Hafnium oxide, Titanium oxide, and ternary alloys with nitrided films of each of the above on Silicon and Germanium substrate were investigated in effort of understanding origins and various factors governing intrinsic band edge defects and interface trapped charges which are crucial to implent the high-k dielectrics into CMOS device below Electrical Equivalent Thickness (EOT) < 1nm. Novel design of atomic scale molecule was applied to achieve superb quality guided by the bond constrain theory. Tetrahedral bonding of Hf and Ti oxide in each Hf/Ti Silicon oxynitride gave the chemical stability upon annealing up to 1100°C. From the spectroscopic and electrical measurements, defect states were suppressed by reducing oxygen vacancy related defect states in Hf/Ti Silicon oxynitride. Conduction and valence band edge defect states were detected and reduced by limiting the thickness of HfO2 to 2 nm which is critical length for forming coherent inter-primitive pi bonding between Hf dpi-O ppi orbitals. As a result, Jahn-Teller d state term splittings were suppressed. The application of ultrathin Hf oxide and Hf Si oxynitride films onto Ge (100) and Ge (111) substrates resulted in the elimination of interfacial transition layer by removing Ge-N and possibly Ge-O bond after 800°C anneal. This could afford re-grown Ge epitaxial layer on top of Ge substrate which dramatically reduced the defect states between Hf Silicon oxynitride and Ge substrate. The gate leakage current for Hf Silicon oxynitride was lower than that on Si substrate.

  14. Electronic States of Hafnium and Vanadium oxide in Silicon Gate Stack Structure

    NASA Astrophysics Data System (ADS)

    Zhu, Chiyu; Tang, Fu; Liu, Xin; Yang, Jialing; Nemanich, Robert

    2010-03-01

    Vanadium oxide (VO2) is a narrow band gap material with a metal-insulator transition (MIT) at less than 100C. Hafnium oxide (HfO2) is currently the preferred high-k material for gate dielectrics. To utilize VO2 in a charge storage device, it is necessary to understand the band relationships between VO2, HfO2, and Si substrate. In this study, a 2nm thick VO2 layer is embedded in a dielectric stack structure between an oxidized n-type Si(100) surface and a 2nm HfO2 layer. The in situ experiments are carried out in an UHV multi-chamber system. After each growth step, the surface is characterized using XPS and UPS. After the initial plasma cleaning and oxidation treatment the Si substrate displayed essentially flat bands at the surface. After deposition of the VO2 layer, the Si 2p peak shifted to lower binding energy, and the Si 2p associated with the SiO2 layer also was shifted, indicating an internal field in the SiO2. The VO2 valence band maximum (VBM) was identified at 0.6 eV below the Fermi level (EF). This ultra thin VO2 exhibits the metal-insulator transition at a temperature higher than thicker films. As a comparison, a 100nm thick film of VO2 on Si showed a MIT at 60C. After the HfO2 deposition, the Si 2p substrate feature returned to the initial value indicating a return to flat band conditions. The UPS indicated the VBM of HfO2 at 4.0 eV below EF. This work is supported by the NSF (DMR-0805353).

  15. Electron mobility in ultra-thin InGaAs channels: Impact of surface orientation and different gate oxide materials

    NASA Astrophysics Data System (ADS)

    Krivec, Sabina; Poljak, Mirko; Suligoj, Tomislav

    2016-01-01

    Electron mobility is investigated in sub-20 nm-thick InGaAs channels, sandwiched between different gate oxides (SiO2, Al2O3, HfO2) and InP as substrate, using physics-based numerical modeling. Effects of body thickness downscaling to 2 nm, different gate oxides, and surface orientation [(1 0 0) and (1 1 1)] are examined by including all electron valleys and all relevant scattering mechanisms. We report that ultra-thin (1 1 1) Al2O3-InGaAs-InP devices offer greater electron mobility than (1 0 0) devices even in the extremely-thin channels. Furthermore, ultra-thin (1 0 0) InGaAs devices outperform SOI in terms of electron mobility for body thicknesses above ∼4 nm, while (1 1 1) InGaAs channels are superior to SOI for all body thickness values above ∼3 nm. The study of different gate oxides indicates that HfO2 is the optimum gate dielectric regardless of device orientation, offering a mobility improvement of up to 124% for (1 1 1) and 149% for (1 0 0) surface orientation, when compared to the initial Al2O3-InGaAs-InP structure. The (1 1 1) orientation offers improvement over (1 0 0) device irrespective of the body thickness and gate oxide material, with the highest difference reported for SiO2, followed by Al2O3 and HfO2.

  16. Analytical model for an asymmetric double-gate MOSFET with gate-oxide thickness and flat-band voltage variations in the subthreshold region

    NASA Astrophysics Data System (ADS)

    Shin, Yong Hyeon; Yun, Ilgu

    2016-06-01

    This paper proposes an analytical model for an asymmetric double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) with varying gate-oxide thickness (tox) and flat-band voltage (Vfb) in the subthreshold region. Since such variations cannot be completely avoided, the modeling of their behaviors is essential. The analytical model is developed by solving a 2D Poisson equation with a varying channel doping concentration (NA). To solve the 2D Poisson equation of the asymmetric DG MOSFET, a perturbation method is used to separate the solution of the channel potential into basic and perturbed terms. Since the basic terms can be regarded as the equations derived from a general symmetric doped DG MOSFET, the conventional analytical model is adopted. In addition, a solution related to the perturbed terms for the asymmetric structures is obtained using Fourier series. Based on the obtained channel potential, the electrical characteristics of the drive current (IDS) are expressed in the analytical model. The prediction of the electrical characteristics by the analytical model shows excellent agreement when compared with commercially available 2D numerical device simulation results with respect to not only tox and Vfb variations but also channel length and NA variations.

  17. GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistor Fabricated with Novel Wet Etching

    NASA Astrophysics Data System (ADS)

    Kodama, Masahito; Sugimoto, Masahiro; Hayashi, Eiko; Soejima, Narumasa; Ishiguro, Osamu; Kanechika, Masakazu; Itoh, Kenji; Ueda, Hiroyuki; Uesugi, Tsutomu; Kachi, Tetsu

    2008-02-01

    A novel method for fabricating trench structures on GaN was developed. A smooth non-polar (1100) plane was obtained by wet etching using tetramethylammonium hydroxide (TMAH) as the etchant. A U-shape trench with the (1100) plane side walls was formed with dry etching and the TMAH wet etching. A U-shape trench gate metal oxide semiconductor field-effect transistor (MOSFET) was also fabricated using the novel etching technology. This device has the excellent normally-off operation of drain current-gate voltage characteristics with the threshold voltage of 10 V. The drain breakdown voltage of 180 V was obtained. The results indicate that the trench gate structure can be applied to GaN-based transistors.

  18. Improvement in performance of solution-processed indium-zinc-tin oxide thin-film transistors by UV/O3 treatment on zirconium oxide gate insulator

    NASA Astrophysics Data System (ADS)

    Naik, Bukke Ravindra; Avis, Christophe; Delwar Hossain Chowdhury, Md; Kim, Taehun; Lin, Tengda; Jang, Jin

    2016-03-01

    We studied solution-processed amorphous indium-zinc-tin oxide (a-IZTO) thin-film transistors (TFTs) with spin-coated zirconium oxide (ZrOx) as the gate insulator. The ZrOx gate insulator was used without and with UV/O3 treatment. The TFTs with an untreated ZrOx gate dielectric showed a saturation mobility (μsat) of 0.91 ± 0.29 cm2 V-1 s-1, a threshold voltage (Vth) of 0.28 ± 0.36 V, a subthreshold swing (SS) of 199 ± 37.17 mV/dec, and a current ratio (ION/IOFF) of ˜107. The TFTs with a UV/O3-treated ZrOx gate insulator exhibited μsat of 2.65 ± 0.43 cm2 V-1 s-1, Vth of 0.44 ± 0.35 V, SS of 133 ± 24.81 mV/dec, and ION/IOFF of ˜108. Hysteresis was 0.32 V in the untreated TFTs and was eliminated by UV/O3 treatment. Also, the leakage current decreased significantly when the IZTO TFT was coated onto a UV/O3-treated ZrOx gate insulator.

  19. Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

    SciTech Connect

    Chun, Minkyu; Chowdhury, Md Delwar Hossain; Jang, Jin

    2015-05-15

    We investigated the effects of top gate voltage (V{sub TG}) and temperature (in the range of 25 to 70 {sup o}C) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The increment of V{sub TG} from -20V to +20V, decreases the threshold voltage (V{sub TH}) from 19.6V to 3.8V and increases the electron density to 8.8 x 10{sup 18}cm{sup −3}. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on V{sub TG}. At V{sub TG} of 20V, the mobility decreases from 19.1 to 15.4 cm{sup 2}/V ⋅ s with increasing temperature, showing a metallic conduction. On the other hand, at V{sub TG} of - 20V, the mobility increases from 6.4 to 7.5cm{sup 2}/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.

  20. Gate dielectric development for flexible electronics

    SciTech Connect

    Joshi, P. C.; Voutsas, A. T.; Hartzell, J. W.

    2007-07-15

    Thin film transistors integrated on flexible substrates are becoming increasingly attractive for low cost displays, sensors, and rf communication applications. The successful development of the flexible devices will be dictated by the enhancement in the thermal stability of the substrates and the low temperature (<300 deg. C) processing of the gate dielectric. The plasma-enhanced chemical-vapor deposition (PECVD) technique has successfully met the demands of the gate dielectric for display devices at processing temperatures lower than 600 deg. C. However, a further reduction in the processing temperatures below 300 deg. C is essential to realize low cost, highly functional devices on flexible substrates. The low temperature processing of gate dielectric films necessitates the development of processes and techniques with plasma controlled reaction kinetics dominating the thin film growth rather than the thermal state of the substrate. In the present work, the authors report on the processing of high quality gate dielectric films by high density PECVD technique at process temperatures lower than 300 deg. C. The bulk and interfacial electrical quality and reliability of the metal-oxide-semiconductor capacitors as a function of process temperature are discussed in this article. A comparison with the high temperature gate oxide films deposited by PECVD technique employing capacitively coupled plasma source has been made to establish the film quality and reliability. The films processed at low temperatures have shown good electrical performance and reliability as evaluated in terms of the leakage current, flatband voltage, midgap interface trap concentration, and bias temperature stress reliability characteristics.

  1. Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

    SciTech Connect

    Lee, Eunji; Chowdhury, Md Delwar Hossain; Park, Min Sang; Jang, Jin

    2015-12-07

    We have studied the effect of top gate bias (V{sub TG}) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm{sup 2} intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the V{sub TG} from −15 to +15 V. By changing V{sub TG} from negative to positive, the Fermi level (E{sub F}) shifts toward conduction band edge (E{sub C}), which substantially controls the conversion of neutral vacancy to charged one (V{sub O} → V{sub O}{sup +}/V{sub O}{sup 2+} + e{sup −}/2e{sup −}), peroxide (O{sub 2}{sup 2−}) formation or conversion of ionized interstitial (O{sub i}{sup 2−}) to neutral interstitial (O{sub i}), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows −2.7 V shift at V{sub TG} = −15 V, which gradually decreases to −0.42 V shift at V{sub TG} = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (V{sub O}{sup +}/V{sub O}{sup 2+}/O{sub 2}{sup 2−}/O{sub i}) and/or hole trapping in the a-IGZO /interfaces.

  2. Short-Term Synaptic Plasticity Regulation in Solution-Gated Indium-Gallium-Zinc-Oxide Electric-Double-Layer Transistors.

    PubMed

    Wan, Chang Jin; Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

    2016-04-20

    In the biological nervous system, synaptic plasticity regulation is based on the modulation of ionic fluxes, and such regulation was regarded as the fundamental mechanism underlying memory and learning. Inspired by such biological strategies, indium-gallium-zinc-oxide (IGZO) electric-double-layer (EDL) transistors gated by aqueous solutions were proposed for synaptic behavior emulations. Short-term synaptic plasticity, such as paired-pulse facilitation, high-pass filtering, and orientation tuning, was experimentally emulated in these EDL transistors. Most importantly, we found that such short-term synaptic plasticity can be effectively regulated by alcohol (ethyl alcohol) and salt (potassium chloride) additives. Our results suggest that solution gated oxide-based EDL transistors could act as the platforms for short-term synaptic plasticity emulation. PMID:27007748

  3. Self-aligned graphene field-effect transistors on SiC (0001) substrates with self-oxidized gate dielectric

    NASA Astrophysics Data System (ADS)

    Jia, Li; Cui, Yu; Li, Wang; Qingbin, Liu; Zezhao, He; Shujun, Cai; Zhihong, Feng

    2014-07-01

    A scalable self-aligned approach is employed to fabricate monolayer graphene field-effect transistors on semi-insulated 4H-SiC (0001) substrates. The self-aligned process minimized access resistance and parasitic capacitance. Self-oxidized Al2O3, formed by deposition of 2 nm Al followed by exposure in air to be oxidized, is used as gate dielectric and shows excellent insulation. An intrinsic cutoff frequency of 34 GHz and maximum oscillation frequency of 36.4 GHz are realized for the monolayer graphene field-effect transistor with a gate length of 0.2 μm. These studies show a pathway to fabricate graphene transistors for future applications in ultra-high frequency circuits.

  4. A Novel Sub-20 V Contact Gate Metal Oxide Semiconductor Field Effect Transistor with Fully Complementary Metal Oxide Semiconductor Compatible Process

    NASA Astrophysics Data System (ADS)

    Lee, Te Liang; Tsang Tsai, Ming; King, Ya Chin; Lin, Chrong Jung

    2013-04-01

    In this paper, a novel sub-20 V device which is called contact gate MOSFET (CGMOS) with fully CMOS logic compatible process is proposed and demonstrated. Comparing with lateral double diffusion MOSFET (LDMOS), CGMOS uses P substrate instead of N minus layer as drift region in logic process, and a contact on resistance protection oxide (RPO) layers to form an extra gate on the drain side of the channel region to provide a better gate control and reduce the surface field. This new device significantly rises up the breakdown voltage to 18 V with specific on-resistance 8.8 mΩ.mm2 in a small high voltage (HV) MOSFET area. Since there is no extra mask for creating the drift region or additional step for the wire bonding, CGMOS makes the integration of high voltage and logic circuits much simpler and area-saving.

  5. Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

    NASA Astrophysics Data System (ADS)

    Asahara, Ryohei; Hideshima, Iori; Oka, Hiroshi; Minoura, Yuya; Ogawa, Shingo; Yoshigoe, Akitaka; Teraoka, Yuden; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2015-06-01

    Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlOx) interlayers. A step-by-step in situ procedure by deposition of AlOx and hafnium oxide (HfOx) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO2/AlOx/GeOx/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlOx interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56 nm and very low interface state density of 2.4 × 1011 cm-2eV-1 with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

  6. Low-temperature formation of high-quality gate oxide by ultraviolet irradiation on spin-on-glass

    SciTech Connect

    Usuda, R.; Uchida, K.; Nozaki, S.

    2015-11-02

    Although a UV cure was found to effectively convert a perhydropolysilazane (PHPS) spin-on-glass film into a dense SiO{sub x} film at low temperature, the electrical characteristics were never reported in order to recommend the use of PHPS as a gate-oxide material that can be formed at low temperature. We have formed a high-quality gate oxide by UV irradiation on the PHPS film, and obtained an interface midgap trap density of 3.4 × 10{sup 11 }cm{sup −2} eV{sup −1} by the UV wet oxidation and UV post-metallization annealing (PMA), at a temperature as low as 160 °C. In contrast to the UV irradiation using short-wavelength UV light, which is well known to enhance oxidation by the production of the excited states of oxygen, the UV irradiation was carried out using longer-wavelength UV light from a metal halide lamp. The UV irradiation during the wet oxidation of the PHPS film generates electron-hole pairs. The electrons ionize the H{sub 2}O molecules and facilitate dissociation of the molecules into H and OH{sup −}. The OH{sup −} ions are highly reactive with Si and improve the stoichiometry of the oxide. The UV irradiation during the PMA excites the electrons from the accumulation layer, and the built-in electric field makes the electron injection into the oxide much easier. The electrons injected into the oxide recombine with the trapped holes, which have caused a large negative flat band voltage shift after the UV wet oxidation, and also ionize the H{sub 2}O molecules. The ionization results in the electron stimulated dissociation of H{sub 2}O molecules and the decreased interface trap density.

  7. Low-temperature formation of high-quality gate oxide by ultraviolet irradiation on spin-on-glass

    NASA Astrophysics Data System (ADS)

    Usuda, R.; Uchida, K.; Nozaki, S.

    2015-11-01

    Although a UV cure was found to effectively convert a perhydropolysilazane (PHPS) spin-on-glass film into a dense SiOx film at low temperature, the electrical characteristics were never reported in order to recommend the use of PHPS as a gate-oxide material that can be formed at low temperature. We have formed a high-quality gate oxide by UV irradiation on the PHPS film, and obtained an interface midgap trap density of 3.4 × 1011 cm-2 eV-1 by the UV wet oxidation and UV post-metallization annealing (PMA), at a temperature as low as 160 °C. In contrast to the UV irradiation using short-wavelength UV light, which is well known to enhance oxidation by the production of the excited states of oxygen, the UV irradiation was carried out using longer-wavelength UV light from a metal halide lamp. The UV irradiation during the wet oxidation of the PHPS film generates electron-hole pairs. The electrons ionize the H2O molecules and facilitate dissociation of the molecules into H and OH-. The OH- ions are highly reactive with Si and improve the stoichiometry of the oxide. The UV irradiation during the PMA excites the electrons from the accumulation layer, and the built-in electric field makes the electron injection into the oxide much easier. The electrons injected into the oxide recombine with the trapped holes, which have caused a large negative flat band voltage shift after the UV wet oxidation, and also ionize the H2O molecules. The ionization results in the electron stimulated dissociation of H2O molecules and the decreased interface trap density.

  8. Structural and thermodynamic consideration of metal oxide doped GeO{sub 2} for gate stack formation on germanium

    SciTech Connect

    Lu, Cimang Lee, Choong Hyun; Zhang, Wenfeng; Nishimura, Tomonori; Nagashio, Kosuke; Toriumi, Akira

    2014-11-07

    A systematic investigation was carried out on the material and electrical properties of metal oxide doped germanium dioxide (M-GeO{sub 2}) on Ge. We propose two criteria on the selection of desirable M-GeO{sub 2} for gate stack formation on Ge. First, metal oxides with larger cation radii show stronger ability in modifying GeO{sub 2} network, benefiting the thermal stability and water resistance in M-GeO{sub 2}/Ge stacks. Second, metal oxides with a positive Gibbs free energy for germanidation are required for good interface properties of M-GeO{sub 2}/Ge stacks in terms of preventing the Ge-M metallic bond formation. Aggressive equivalent oxide thickness scaling to 0.5 nm is also demonstrated based on these understandings.

  9. Impact of the crystallization of the high-k dielectric gate oxide on the positive bias temperature instability of the n-channel metal-oxide-semiconductor field emission transistor

    NASA Astrophysics Data System (ADS)

    Lim, Han Jin; Kim, Youngkuk; Sang Jeon, In; Yeo, Jaehyun; Im, Badro; Hong, Soojin; Kim, Bong-Hyun; Nam, Seok-Woo; Kang, Ho-kyu; Jung, E. S.

    2013-06-01

    The positive bias temperature instability (PBTI) characteristics of the n-channel metal-oxide-semiconductor field emission transistors which had different kinds of high-k dielectric gate oxides were studied with the different stress-relaxation times. The degradation in the threshold voltage followed a power-law on the stress times. In particular, we found that their PBTI behaviors were closely related to the structural phase of the high-k dielectric gate oxide. In an amorphous gate oxide, the negative charges were trapped into the stress-induced defects of which energy level was so deep that the trapped charges were de-trapped slowly. Meanwhile, in a crystalline gate oxide, the negative charges were trapped mostly in the pre-existing defects in the crystallized films during early stage of the stress time and de-trapped quickly due to the shallow energy level of the defects.

  10. Understanding the Structure of High-K Gate Oxides - Oral Presentation

    SciTech Connect

    Miranda, Andre

    2015-08-25

    Hafnium Oxide (HfO2) amorphous thin films are being used as gate oxides in transistors because of their high dielectric constant (κ) over Silicon Dioxide. The present study looks to find the atomic structure of HfO2 thin films which hasn’t been done with the technique of this study. In this study, two HfO2 samples were studied. One sample was made with thermal atomic layer deposition (ALD) on top of a Chromium and Gold layer on a silicon wafer. The second sample was made with plasma ALD on top of a Chromium and Gold layer on a Silicon wafer. Both films were deposited at a thickness of 50nm. To obtain atomic structure information, Grazing Incidence X-ray diffraction (GIXRD) was carried out on the HfO2 samples. Because of this, absorption, footprint, polarization, and dead time corrections were applied to the scattering intensity data collected. The scattering curves displayed a difference in structure between the ALD processes. The plasma ALD sample showed the broad peak characteristic of an amorphous structure whereas the thermal ALD sample showed an amorphous structure with characteristics of crystalline materials. This appears to suggest that the thermal process results in a mostly amorphous material with crystallites within. Further, the scattering intensity data was used to calculate a pair distribution function (PDF) to show more atomic structure. The PDF showed atom distances in the plasma ALD sample had structure up to 10 Å, while the thermal ALD sample showed the same structure below 10 Å. This structure that shows up below 10 Å matches the bond distances of HfO2 published in literature. The PDF for the thermal ALD sample also showed peaks up to 20 Å, suggesting repeating atomic spacing outside the HfO2 molecule in the sample. This appears to suggest that there is some crystalline structure within the thermal ALD sample.

  11. The physical origin of dispersion in accumulation in InGaAs based metal oxide semiconductor gate stacks

    NASA Astrophysics Data System (ADS)

    Krylov, Igor; Ritter, Dan; Eizenberg, Moshe

    2015-05-01

    Dispersion in accumulation is a widely observed phenomenon in technologically important InGaAs gate stacks. Two principal different interface defects were proposed as the physical origin of this phenomenon—disorder induced gap states and border traps. While the gap states are located at the semiconductor side of the interface, the border traps are related to the dielectric side. The study of Al2O3, HfO2, and an intermediate composition of HfxAlyO deposited on InGaAs enabled us to find a correlation between the dispersion and the dielectric/InGaAs band offset. At the same time, no change in the dispersion was observed after applying an effective pre-deposition treatment which results in significant reduction of the interface states. Both observations prove that border traps are the physical origin of the dispersion in accumulation in InGaAs based metal-oxide-semiconductor gate stacks.

  12. Metal-oxide thin-film transistor-based pH sensor with a silver nanowire top gate electrode

    NASA Astrophysics Data System (ADS)

    Yoo, Tae-Hee; Sang, Byoung-In; Wang, Byung-Yong; Lim, Dae-Soon; Kang, Hyun Wook; Choi, Won Kook; Lee, Young Tack; Oh, Young-Jei; Hwang, Do Kyung

    2016-04-01

    Amorphous InGaZnO (IGZO) metal-oxide-semiconductor thin-film transistors (TFTs) are one of the most promising technologies to replace amorphous and polycrystalline Si TFTs. Recently, TFT-based sensing platforms have been gaining significant interests. Here, we report on IGZO transistor-based pH sensors in aqueous medium. In order to achieve stable operation in aqueous environment and enhance sensitivity, we used Al2O3 grown by using atomic layer deposition (ALD) and a porous Ag nanowire (NW) mesh as the top gate dielectric and electrode layers, respectively. Such devices with a Ag NW mesh at the top gate electrode rapidly respond to the pH of solutions by shifting the turn-on voltage. Furthermore, the output voltage signals induced by the voltage shifts can be directly extracted by implantation of a resistive load inverter.

  13. A compact quantum correction model for symmetric double gate metal-oxide-semiconductor field-effect transistor

    SciTech Connect

    Cho, Edward Namkyu; Shin, Yong Hyeon; Yun, Ilgu

    2014-11-07

    A compact quantum correction model for a symmetric double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. The compact quantum correction model is proposed from the concepts of the threshold voltage shift (ΔV{sub TH}{sup QM}) and the gate capacitance (C{sub g}) degradation. First of all, ΔV{sub TH}{sup QM} induced by quantum mechanical (QM) effects is modeled. The C{sub g} degradation is then modeled by introducing the inversion layer centroid. With ΔV{sub TH}{sup QM} and the C{sub g} degradation, the QM effects are implemented in previously reported classical model and a comparison between the proposed quantum correction model and numerical simulation results is presented. Based on the results, the proposed quantum correction model can be applicable to the compact model of DG MOSFET.

  14. Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme

    NASA Astrophysics Data System (ADS)

    Veloso, Anabela; Boccardi, Guillaume; Ragnarsson, Lars-Åke; Higuchi, Yuichi; Arimura, Hiroaki; Lee, Jae Woo; Simoen, Eddy; Cho, Moon Ju; Roussel, Philippe J.; Paraschiv, Vasile; Shi, Xiaoping; Schram, Tom; Aik Chew, Soon; Brus, Stephan; Dangol, Anish; Vecchio, Emma; Sebaai, Farid; Kellens, Kristof; Heylen, Nancy; Devriendt, Katia; Dekkers, Harold; Van Ammel, Annemie; Witters, Thomas; Conard, Thierry; Vaesen, Inge; Richard, Olivier; Bender, Hugo; Athimulam, Raja; Chiarella, Thomas; Thean, Aaron; Horiguchi, Naoto

    2014-01-01

    We report on aggressively scaled replacement metal gate, high-k last (RMG-HKL) planar and multi-gate fin field-effect transistor (FinFET) devices, systematically investigating the impact of post high-k deposition thermal (PDA) and plasma (SF6) treatments on device characteristics, and providing a deeper insight into underlying degradation mechanisms. We demonstrate that: 1) substantially reduced gate leakage (JG) and noise can be obtained for both type of devices with PDA and F incorporation in the gate stack by SF6, without equivalent oxide thickness (EOT) penalty; 2) SF6 enables improved mobility and reduced interface trapped charge density (Nit) down to narrower fin devices [fin width (WFin) ≥ 5 nm], mitigating the impact of fin patterning and fin sidewall crystal orientations, while allowing a simplified dual-effective work function (EWF) CMOS scheme suitable for both device architectures; 3) PDA yields smaller, in absolute values, PMOS threshold voltage |VT|, and substantially improved reliability behavior due to reduction of bulk defects.

  15. Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors

    NASA Astrophysics Data System (ADS)

    Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

    2013-10-01

    In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements. Electronic supplementary information (ESI) available. See DOI: 10.1039/c3nr02987e

  16. Extraction of Distance Between Interface Trap and Oxide Trap from Random Telegraph Noise in Gate-Induced Drain Leakage.

    PubMed

    Seo, Youngsoo; Yoo, Sungwon; Shin, Joonha; Kim, Hyunsoo; Kim, Hyunsuk; Jeon, Sangbin; Shin, Hyungcheol

    2016-05-01

    This paper presents an analysis of the Random Telegraph Noise (RTN) of the Gate-Induced Drain Leakage (GIDL) of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The RTN data that was measured and analytical equations are used to extract the values of the parameters for the vertical distance of the oxide trap from the interface and of the energy level of the interface trap. These values and equations allow for the distance r between the interface trap and the oxide trap to be extracted. For the first time, the accurate field enhancement factor γ(F), which depends on the magnitude of the electric field at the Si/SiO2 interface, was used to calculate the current ratio before and after the electron trapping, and the value extracted for r is completely different depending on the enhancement factor that is used. PMID:27483908

  17. Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

    PubMed Central

    Hussin, H.; Soin, N.; Bukhori, M. F.; Wan Muhamad Hatta, S.; Abdul Wahab, Y.

    2014-01-01

    We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2 are increased but is reduced by 11% when the SiO2 interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2 interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated. PMID:25221784

  18. Performance enhancement of multiple-gate ZnO metal-oxide-semiconductor field-effect transistors fabricated using self-aligned and laser interference photolithography techniques

    PubMed Central

    2014-01-01

    The simple self-aligned photolithography technique and laser interference photolithography technique were proposed and utilized to fabricate multiple-gate ZnO metal-oxide-semiconductor field-effect transistors (MOSFETs). Since the multiple-gate structure could improve the electrical field distribution along the ZnO channel, the performance of the ZnO MOSFETs could be enhanced. The performance of the multiple-gate ZnO MOSFETs was better than that of the conventional single-gate ZnO MOSFETs. The higher the drain-source saturation current (12.41 mA/mm), the higher the transconductance (5.35 mS/mm) and the lower the anomalous off-current (5.7 μA/mm) for the multiple-gate ZnO MOSFETs were obtained. PMID:24948884

  19. Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors

    NASA Astrophysics Data System (ADS)

    Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

    2016-04-01

    In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade-1 and 3.62 × 1011 eV-1 cm-2, respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

  20. Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.

    PubMed

    Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

    2016-12-01

    In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade(-1) and 3.62 × 10(11) eV(-1) cm(-2), respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT. PMID:27129687

  1. Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature

    NASA Astrophysics Data System (ADS)

    Liuan, Li; Jiaqi, Zhang; Yang, Liu; Jin-Ping, Ao

    2016-03-01

    In this paper, TiN/AlOx gated AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600 °C with the contact resistance approximately 1.6 Ω·mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/AlOx gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate AlGaN/GaN MOS-HFETs. Project supported by the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260).

  2. Improvement of Ron under AC Operation of Floating Island and Thick Bottom Oxide Trench Gate MOSFET (FITMOS)

    NASA Astrophysics Data System (ADS)

    Takaya, Hidefumi; Miyagi, Kyosuke; Hamada, Kimimori

    A MOSFET structure called a FITMOS (Floating Island and Thick Bottom Oxide Trench Gate MOSFET) that exhibits a record low loss in the 60V breakdown voltage (BVdss) range has been successfully developed. The following improvements achieved progress in the characteristic of FITMOS. (1) At the time of AC operation, the charges in the floating P islands that are a feature of the floating type device become greater, thereby increasing the on-resistance (Ron) due to the JFET effect. This issue was solved by forming passive hole gates in the end walls of the trenches. The Ron under AC operation is equivalent to the Ron under DC operation. This paper clarified the influence of the passive hole gate diffusion layer shape and the impurity concentration to BVdss and AC operation. (2) The trade-off of BVdss and Ron has been improved by making the floating island into an elliptical form. A BVdss of 83V and a specific on-resistance (RonA) of 36mΩmm2 were obtained.

  3. Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

    SciTech Connect

    Chao, Jin Yu; Zhu, Li Qiang Xiao, Hui; Yuan, Zhi Guo

    2015-12-21

    Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ∼1.0 V such as on/off ratio of ∼3 × 10{sup 7}, subthreshold swing of ∼65 mV/dec, threshold voltage of ∼0.3 V, and mobility of ∼7 cm{sup 2}/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor in series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.

  4. Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

    NASA Astrophysics Data System (ADS)

    Chao, Jin Yu; Zhu, Li Qiang; Xiao, Hui; Yuan, Zhi Guo

    2015-12-01

    Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ˜1.0 V such as on/off ratio of ˜3 × 107, subthreshold swing of ˜65 mV/dec, threshold voltage of ˜0.3 V, and mobility of ˜7 cm2/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor in series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.

  5. High-performance GaAs-based metal-oxide-semiconductor heterostructure field-effect transistors with atomic-layer-deposited Al2O3 gate oxide and in situ AlN passivation by metalorganic chemical vapor deposition

    NASA Astrophysics Data System (ADS)

    Aoki, Takeshi; Fukuhara, Noboru; Osada, Takenori; Sazawa, Hiroyuki; Hata, Masahiko; Inoue, Takayuki

    2014-10-01

    GaAs-based metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with Al2O3 gate oxide and in situ AlN passivation were investigated. Passivation with AlN improved the quality of the MOS interfaces, leading to good control of the gate. The devices had a sufficiently small subthreshold swing of 84 mV decade-1 in the drain current vs gate voltage curves, as well as negligible frequency dispersions and nearly zero hysteresis in the gate capacitance vs gate voltage curves. A maximum drain current of 630 mA/mm and a peak effective mobility of 6720 cm2 V-1 s-1 at a sheet carrier density of 3 × 1012 cm-2 were achieved.

  6. A high-mobility electronic system at an electrolyte-gated oxide surface

    PubMed Central

    Gallagher, Patrick; Lee, Menyoung; Petach, Trevor A.; Stanwyck, Sam W.; Williams, James R.; Watanabe, Kenji; Taniguchi, Takashi; Goldhaber-Gordon, David

    2015-01-01

    Electrolyte gating is a powerful technique for accumulating large carrier densities at a surface. Yet this approach suffers from significant sources of disorder: electrochemical reactions can damage or alter the sample, and the ions of the electrolyte and various dissolved contaminants sit Angstroms from the electron system. Accordingly, electrolyte gating is well suited to studies of superconductivity and other phenomena robust to disorder, but of limited use when reactions or disorder must be avoided. Here we demonstrate that these limitations can be overcome by protecting the sample with a chemically inert, atomically smooth sheet of hexagonal boron nitride. We illustrate our technique with electrolyte-gated strontium titanate, whose mobility when protected with boron nitride improves more than 10-fold while achieving carrier densities nearing 1014 cm−2. Our technique is portable to other materials, and should enable future studies where high carrier density modulation is required but electrochemical reactions and surface disorder must be minimized. PMID:25762485

  7. A Back-Gated Ferroelectric Field-Effect Transistor with an Al-Doped Zinc Oxide Channel

    NASA Astrophysics Data System (ADS)

    Jia, Ze; Xu, Jian-Long; Wu, Xiao; Zhang, Ming-Ming; Liou, Juin-J.

    2015-02-01

    We report a back-gated metal-oxide-ferroelectric-metal (MOFM) field-effect transistor (FET) with lead zirconate titanate (PZT) material, in which an Al doped zinc oxide (AZO) channel layer with an optimized doping concentration of 1% is applied to reduce the channel resistance of the channel layer, thus guaranteeing a large enough load capacity of the transistor. The hysteresis loops of the Pt/PZT/AZO/Ti/Pt capacitor are measured and compared with a Pt/PZT/Pt capacitor, indicating that the remnant polarization is almost 40 μC/cm2 and the polarization is saturated at 20 V. The measured capacitance-voltage properties are analyzed as a result of the electron depletion and accumulation switching operation conducted by the modulation of PZT on AZO channel resistance caused by the switchable remnant polarization of PZT. The switching properties of the AZO channel layer are also proved by the current-voltage transfer curves measured in the back-gated MOFM ferroelectric FET, which also show a drain current switching ratio up to about 100 times.

  8. Reduction method of gate-to-drain capacitance by oxide spacer formation in tunnel field-effect transistor with elevated drain

    NASA Astrophysics Data System (ADS)

    Kwon, Dae Woong; Kim, Jang Hyun; Park, Euyhwan; Lee, Junil; Park, Taehyung; Lee, Ryoongbin; Kim, Sihyun; Park, Byung-Gook

    2016-06-01

    A novel fabrication method is proposed to reduce large gate-to-drain capacitance (C GD) and to improve AC switching characteristics in tunnel field-effect transistor (TFETs) with elevated drain (TFETED). In the proposed method, gate oxide at drain region (GDOX) is selectively formed through oxide deposition and spacer-etch process. Furthermore, the thicknesses of the GDOX are simply controlled by the amount of the oxide deposition and etch. Mixed-mode device and circuit technology computer aided design (TCAD) simulations are performed to verify the effects of the GDOX thickness on DC and AC switching characteristics of a TFETED inverter. As a result, it is found that AC switching characteristics such as output voltage pre-shoot and falling/rising delay are improved with nearly unchanged DC characteristics by thicker GDOX. This improvement is explained successfully by reduced C GD and positive shifted gate voltage (V G) versus C GD curves with the thicker GDOX.

  9. Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

    SciTech Connect

    Asahara, Ryohei; Hideshima, Iori; Oka, Hiroshi; Minoura, Yuya; Hosoi, Takuji Shimura, Takayoshi; Watanabe, Heiji; Ogawa, Shingo; Yoshigoe, Akitaka; Teraoka, Yuden

    2015-06-08

    Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlO{sub x}) interlayers. A step-by-step in situ procedure by deposition of AlO{sub x} and hafnium oxide (HfO{sub x}) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO{sub 2}/AlO{sub x}/GeO{sub x}/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlO{sub x} interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56 nm and very low interface state density of 2.4 × 10{sup 11 }cm{sup −2}eV{sup −1} with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

  10. A New Two-Dimensional Analytical Model for Short-Channel Symmetrical Dual-Material Double-Gate Metal-Oxide-Semiconductor Field Effect Transistors

    NASA Astrophysics Data System (ADS)

    Chiang, Te-Kuang; Chen, Mei-Li

    2007-06-01

    Based on resultant solution of a two-dimensional (2D) Poisson’s equation in the silicon region, a new analytical model for short-channel fully depleted, symmetrical dual-material double-gate (SDMDG) metal-oxide-semiconductor field effect transistors (MOSFETs) has been developed. The SDMDG MOSFET exhibits significantly reduced short-channel effects (SCEs) when compared with the symmetrical double-gate (SDG) MOSFET due to the step potential profile at the interface between different gate materials. It is found that the threshold voltage roll-off can be effectively reduced using both the thin Si film and thin gate oxide. A considerable portion of the large workfunction of metal gate 1 (M1) when laterally merged with the small workfunction of metal gate 2 (M2) can efficiently suppress drain-induced barrier lowering (DIBL) and maintain the low threshold voltage degradation. In this work, not only a precise 2D analytical model of the surface potential and threshold voltage is presented, but also the minimum surface potential in M1 of the shorter channel device that brings about subthreshold swing degradation for the SDMDG MOSFET is discussed. The new model is verified to be in good agreement with numerical simulation results over a wide range of device parameters.

  11. Simulation of Nanoscale Two-Bit Not-And-type Silicon-Oxide-Nitride-Oxide-Silicon Nonvolatile Memory Devices with a Separated Double-Gate Fin Field Effect Transistor Structure Containing Different Tunneling Oxide Thicknesses

    NASA Astrophysics Data System (ADS)

    Oh, Se Woong; Park, Sang Su; Kim, Dong Hun; Kim, Hyun Woo; Kim, Tae Whan

    2009-06-01

    Not-and (NAND)-type silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory (NVM) devices with a separated double-gate (SDG) Fin field effect transistor structure were proposed to reduce the unit cell size of such memory devices and increase their memory density in comparison with that of conventional NVM devices. The proposed memory device consisted of a pair of control gates separated along the length of the Fin channel direction. Each SDG had a different thickness of the tunneling oxide to operate the proposed memory device as a two-bit/cell device. A technology computer-aided design simulation was performed to investigate the program/erase and two-bit characteristics. The simulation results show that the proposed devices can be used to increase the scaling down capability and charge storage density of NAND-type SONOS NVM devices.

  12. The n-type metal-oxide semiconductor field-effect transistor bias impact on the modelling of the gate-induced drain leakage current

    NASA Astrophysics Data System (ADS)

    Touhami, A.; Bouhdada, A.

    2002-12-01

    The band-to-band tunnelling (BBT) effect in an n-type metal-oxide semiconductor field-effect transistor (n-MOSFET) is attributed not only to the transverse electric field ET but also to the lateral electric field EL in the gate-to-drain overlap region. The main sources of these electric fields are the gate-source (Vgs) and drain-source (Vds) voltages. The modelling of the gate-induced drain leakage current, Igidl, associated with BBT remains always dependent on the drain-gate voltage, Vdg, whatever the applied values of Vgs and Vds, which cannot describe accurately the evolution of the Igidl current according to biases. Therefore, it is necessary to clarify the impact of Vgs and Vds separately. In this paper, we propose a new model of the Igidl current, which can describe the BBT effect in n-MOSFETs under various Vgs and Vds biases.

  13. Indium-zinc-oxide electric-double-layer thin-film transistors gated by silane coupling agents 3-triethoxysilylpropylamine-graphene oxide solid electrolyte

    NASA Astrophysics Data System (ADS)

    Guo, Liqiang; Huang, Yukai; Shi, Yangyang; Cheng, Guanggui; Ding, Jianning

    2015-07-01

    Silane coupling agents 3-triethoxysilylpropyla-mine-graphene oxide (KH550-GO) solid electrolyte are prepared by spin coating process. A high proton conductivity of ~1.2   ×   10-3 Scm-1 is obtained at room temperature. A strong electric-double-layer (EDL) effect is observed due to the accumulation of protons at KH550-GO/IZO interface. Indium-Zinc-Oxide thin film transistors gated by KH550-GO solid electrolyte are self-assembled on ITO glass substrates. Good electrical performances are obtained, such as a low subthreshold swing of ~140 mV/dec., a high current on/off ratio of ~2.9   ×   107 and a high field-effect mobility of ~13.2 cm2 V-1 S-1, respectively.

  14. Improvement in gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors using microwave irradiation

    SciTech Connect

    Jo, Kwang-Won; Cho, Won-Ju

    2014-11-24

    In this study, we evaluated the effects of microwave irradiation (MWI) post-deposition-annealing (PDA) treatment on the gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) and compared the results with a conventional thermal annealing PDA treatment. The MWI-PDA-treated a-IGZO TFTs exhibited enhanced electrical performance as well as improved long-term stability with increasing microwave power. The positive turn-on voltage shift (ΔV{sub ON}) as a function of stress time with positive bias and varying temperature was precisely modeled on a stretched-exponential equation, suggesting that charge trapping is a dominant mechanism in the instability of MWI-PDA-treated a-IGZO TFTs. The characteristic trapping time and average effective barrier height for electron transport indicate that the MWI-PDA treatment effectively reduces the defects in a-IGZO TFTs, resulting in a superior resistance against gate bias stress.

  15. Comparison between chemical vapor deposited and physical vapor deposited WSi2 metal gate for InGaAs n-metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Ong, B. S.; Pey, K. L.; Ong, C. Y.; Tan, C. S.; Antoniadis, D. A.; Fitzgerald, E. A.

    2011-05-01

    We compare chemical vapor deposition (CVD) and physical vapor deposition (PVD) WSi2 metal gate process for In0.53Ga0.47As n-metal-oxide-semiconductor field-effect transistors using 10 and 6.5 nm Al2O3 as dielectric layer. The CVD-processed metal gate device with 6.5 nm Al2O3 shows enhanced transistor performance such as drive current, maximum transconductance and maximum effective mobility. These values are relatively better than the PVD-processed counterpart device with improvement of 51.8%, 46.4%, and 47.8%, respectively. The improvement for the performance of the CVD-processed metal gate device is due to the fluorine passivation at the oxide/semiconductor interface and a nondestructive deposition process.

  16. Recovery from ultraviolet-induced threshold voltage shift in indium gallium zinc oxide thin film transistors by positive gate bias

    SciTech Connect

    Liu, P.; Chen, T. P.; Li, X. D.; Wong, J. I.; Liu, Z.; Liu, Y.; Leong, K. C.

    2013-11-11

    The effect of short-duration ultraviolet (UV) exposure on the threshold voltage (V{sub th}) of amorphous indium gallium zinc oxide thin film transistors (TFTs) and its recovery characteristics were investigated. The V{sub th} exhibited a significant negative shift after UV exposure. The V{sub th} instability caused by UV illumination is attributed to the positive charge trapping in the dielectric layer and/or at the channel/dielectric interface. The illuminated devices showed a slow recovery in threshold voltage without external bias. However, an instant recovery can be achieved by the application of positive gate pulses, which is due to the elimination of the positive trapped charges as a result of the presence of a large amount of field-induced electrons in the interface region.

  17. Lateral protonic/electronic hybrid oxide thin-film transistor gated by SiO{sub 2} nanogranular films

    SciTech Connect

    Zhu, Li Qiang Chao, Jin Yu; Xiao, Hui

    2014-12-15

    Ionic/electronic interaction offers an additional dimension in the recent advancements of condensed materials. Here, lateral gate control of conductivities of indium-zinc-oxide (IZO) films is reported. An electric-double-layer (EDL) transistor configuration was utilized with a phosphorous-doped SiO{sub 2} nanogranular film to provide a strong lateral electric field. Due to the strong lateral protonic/electronic interfacial coupling effect, the IZO EDL transistor could operate at a low-voltage of 1 V. A resistor-loaded inverter is built, showing a high voltage gain of ∼8 at a low supply voltage of 1 V. The lateral ionic/electronic coupling effects are interesting for bioelectronics and portable electronics.

  18. Lateral protonic/electronic hybrid oxide thin-film transistor gated by SiO2 nanogranular films

    NASA Astrophysics Data System (ADS)

    Zhu, Li Qiang; Chao, Jin Yu; Xiao, Hui

    2014-12-01

    Ionic/electronic interaction offers an additional dimension in the recent advancements of condensed materials. Here, lateral gate control of conductivities of indium-zinc-oxide (IZO) films is reported. An electric-double-layer (EDL) transistor configuration was utilized with a phosphorous-doped SiO2 nanogranular film to provide a strong lateral electric field. Due to the strong lateral protonic/electronic interfacial coupling effect, the IZO EDL transistor could operate at a low-voltage of 1 V. A resistor-loaded inverter is built, showing a high voltage gain of ˜8 at a low supply voltage of 1 V. The lateral ionic/electronic coupling effects are interesting for bioelectronics and portable electronics.

  19. Liquid-Gated High Mobility and Quantum Oscillation of the Two-Dimensional Electron Gas at an Oxide Interface.

    PubMed

    Zeng, Shengwei; Lü, Weiming; Huang, Zhen; Liu, Zhiqi; Han, Kun; Gopinadhan, Kalon; Li, Changjian; Guo, Rui; Zhou, Wenxiong; Ma, Haijiao Harsan; Jian, Linke; Venkatesan, Thirumalai; Ariando

    2016-04-26

    Electric field effect in electronic double layer transistor (EDLT) configuration with ionic liquids as the dielectric materials is a powerful means of exploring various properties in different materials. Here, we demonstrate the modulation of electrical transport properties and extremely high mobility of two-dimensional electron gas at LaAlO3/SrTiO3 (LAO/STO) interface through ionic liquid-assisted electric field effect. With a change of the gate voltages, the depletion of charge carrier and the resultant enhancement of electron mobility up to 19 380 cm(2)/(V s) are realized, leading to quantum oscillations of the conductivity at the LAO/STO interface. The present results suggest that high-mobility oxide interfaces, which exhibit quantum phenomena, could be obtained by ionic liquid-assisted field effect. PMID:26974812

  20. Atomic layer etching of ultra-thin HfO2 film for gate oxide in MOSFET devices

    NASA Astrophysics Data System (ADS)

    Park, Jae Beom; Lim, Woong Sun; Park, Byoung Jae; Park, Ih Ho; Kim, Young Woon; Yeom, Geun Young

    2009-03-01

    Precise etch depth control of ultra-thin HfO2 (3.5 nm) films applied as a gate oxide material was investigated by using atomic layer etching (ALET) with an energetic Ar beam and BCl3 gas. A monolayer etching condition of 1.2 Å/cycle with a low surface roughness and an unchanged surface composition was observed for ultra-thin, ALET-etched HfO2 by supplying BCl3 gas and an Ar beam at higher levels than the critical pressure and dose, respectively. When HfO2-nMOSFET devices were fabricated by ALET, a 70% increase in the drain current and a lower leakage current were observed compared with the device fabricated by conventional reactive ion etching, which was attributed to the decreased structural and electrical damage.

  1. Model for the field effect from layers of biological macromolecules on the gates of metal-oxide-semiconductor transistors

    NASA Astrophysics Data System (ADS)

    Landheer, D.; Aers, G.; McKinnon, W. R.; Deen, M. J.; Ranuarez, J. C.

    2005-08-01

    The potential diagram for field-effect transistors used to detect charged biological macromolecules in an electrolyte is presented for the case where an insulating cover layer is used over a conventional eletrolyte-insulator metal-oxide-semiconductor (EIMOS) structure to tether or bind the biological molecules to a floating gate. The layer of macromolecules is modeled using the Poisson-Boltzmann equation for an ion-permeable membrane. Expressions are derived for the charges and potentials in the EIMOS and electrolyte-insulator-semiconductor structures, including the membrane and electrolyte. Exact solutions for the potentials and charges are calculated using numerical algorithms. Simple expressions for the response are presented for low solution potentials when the Donnan potential is approached in the bulk of the membrane. The implications of the model for the small-signal equivalent circuit and the noise analysis of these structures are discussed.

  2. Use of nonpolar BaHfO3 gate oxide for field effect on the high mobility BaSnO3

    NASA Astrophysics Data System (ADS)

    Park, Chulkwon; Kim, Useong; Kim, Young Mo; Ju, Chanjong; Char, Kookrin

    2015-03-01

    Recently, BaSnO3 (BSO) has attracted attentions as a transparent conducting oxide and/or a transparent oxide semiconductor due to its novel properties: the excellent oxygen stability even at high temperature and the high electrical mobility at room temperature. We fabricated field effect transistors using La-doped BSO as the semiconducting channel on undoped BSO buffer layers on SrTiO3 substrates. A non-polar perovskite BaHfO3 was used as the gate insulator, and 4% La-doped BSO as the source, the drain, and the gate electrodes grown by pulsed laser deposition. We have measured the optical and the dielectric properties of the epitaxial BaHfO3 gate oxide layer, namely the optical band gap, the dielectric constant, and the breakdown field. Using such BaHfO3 gate oxide, we observed carrier modulation in the active layer by field effect. In this presentation, we will report on the performance of such field effect transistors: the output and the transfer characteristics, the field effect mobility, the Ion/Ioff ratio, and the subthreshold swing.

  3. Aqueous combustion synthesis of aluminum oxide thin films and application as gate dielectric in GZTO solution-based TFTs.

    PubMed

    Branquinho, Rita; Salgueiro, Daniela; Santos, Lídia; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

    2014-11-26

    Solution processing has been recently considered as an option when trying to reduce the costs associated with deposition under vacuum. In this context, most of the research efforts have been centered in the development of the semiconductors processes nevertheless the development of the most suitable dielectrics for oxide based transistors is as relevant as the semiconductor layer itself. In this work we explore the solution combustion synthesis and report on a completely new and green route for the preparation of amorphous aluminum oxide thin films; introducing water as solvent. Optimized dielectric layers were obtained for a water based precursor solution with 0.1 M concentration and demonstrated high capacitance, 625 nF cm(-2) at 10 kHz, and a permittivity of 7.1. These thin films were successfully applied as gate dielectric in solution processed gallium-zinc-tin oxide (GZTO) thin film transistors (TFTs) yielding good electrical performance such as subthreshold slope of about 0.3 V dec(-1) and mobility above 1.3 cm2 V(-1) s(-1). PMID:25354332

  4. Reliability and fatigue failure modes of implant-supported aluminum-oxide fixed dental prostheses

    PubMed Central

    Stappert, Christian F. J.; Baldassarri, Marta; Zhang, Yu; Hänssler, Felix; Rekow, Elizabeth D.; Thompson, Van P.

    2012-01-01

    Objectives To investigate failure modes and reliability of implant-supported aluminum-oxide three-unit fixed-dental-prostheses (FDPs) using two different veneering porcelains. Material and methods Thirty-six aluminum-oxide FDP-frameworks were CAD/CAM fabricated and either hand-veneered(n=18) or over-pressed(n=18). All FDPs were adhesively luted to custom-made zirconium-oxide-abutments attached to dental implant fixtures (RP-4×13mm). Specimens were stored in water prior to mechanical testing. A Step-Stress-Accelerated-Life-Test (SSALT) with three load/cycles varying profiles was developed based on initial single-load-to-failure testing. Failure was defined by veneer chipping or chipping in combination with framework fracture. SSALT was performed on each FDP inclined 30° with respect to the applied load direction. For all specimens, failure modes were analyzed using polarized-reflected-light-microscopy and scanning-electron-microscopy (SEM). Reliability was computed using Weibull analysis software (Reliasoft). Results The dominant failure mode for the over-pressed FDPs was buccal chipping of the porcelain in the loading area of the pontic, while hand-veneered specimens failed mainly by combined failure modes in the veneering porcelain, framework and abutments. Chipping of the porcelain occurred earlier in the over-pressed specimens (350 N/85k, load/cycles) than in the hand-veneered (600 N/110k)(profile I). Given a mission at 300 N load and 100k or 200 K cycles the computed Weibull reliability (2-sided at 90.0 % confidence bounds) was 0.99(1/0.98) and 0.99(1/0.98) for hand-veneered FDPs, and 0.45(0.76/0.10) and 0.05(0.63/0) for over-pressed FDPs, respectively. Conclusions In the range of average clinical loads (300–700 N), hand-veneered aluminum-oxide FDPs showed significantly less failure by chipping of the veneer than the over-pressed. Hand-veneered FDPs under fatigue loading failed at loads ≥ 600N. PMID:22093019

  5. Solution processed lanthanum aluminate gate dielectrics for use in metal oxide-based thin film transistors

    SciTech Connect

    Esro, M.; Adamopoulos, G.; Mazzocco, R.; Kolosov, O.; Krier, A.; Vourlias, G.; Milne, W. I.

    2015-05-18

    We report on ZnO-based thin-film transistors (TFTs) employing lanthanum aluminate gate dielectrics (La{sub x}Al{sub 1−x}O{sub y}) grown by spray pyrolysis in ambient atmosphere at 440 °C. The structural, electronic, optical, morphological, and electrical properties of the La{sub x}Al{sub 1−x}O{sub y} films and devices as a function of the lanthanum to aluminium atomic ratio were investigated using a wide range of characterization techniques such as UV-visible absorption spectroscopy, impedance spectroscopy, spectroscopic ellipsometry, atomic force microscopy, x-ray diffraction, and field-effect measurements. As-deposited LaAlO{sub y} dielectrics exhibit a wide band gap (∼6.18 eV), high dielectric constant (k ∼ 16), low roughness (∼1.9 nm), and very low leakage currents (<3 nA/cm{sup 2}). TFTs employing solution processed LaAlO{sub y} gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with hysteresis-free operation, low operation voltages (∼10 V), high on/off current modulation ratio of >10{sup 6}, subthreshold swing of ∼650 mV dec{sup −1}, and electron mobility of ∼12 cm{sup 2} V{sup −1} s{sup −1}.

  6. Solution processed lanthanum aluminate gate dielectrics for use in metal oxide-based thin film transistors

    NASA Astrophysics Data System (ADS)

    Esro, M.; Mazzocco, R.; Vourlias, G.; Kolosov, O.; Krier, A.; Milne, W. I.; Adamopoulos, G.

    2015-05-01

    We report on ZnO-based thin-film transistors (TFTs) employing lanthanum aluminate gate dielectrics (LaxAl1-xOy) grown by spray pyrolysis in ambient atmosphere at 440 °C. The structural, electronic, optical, morphological, and electrical properties of the LaxAl1-xOy films and devices as a function of the lanthanum to aluminium atomic ratio were investigated using a wide range of characterization techniques such as UV-visible absorption spectroscopy, impedance spectroscopy, spectroscopic ellipsometry, atomic force microscopy, x-ray diffraction, and field-effect measurements. As-deposited LaAlOy dielectrics exhibit a wide band gap (˜6.18 eV), high dielectric constant (k ˜ 16), low roughness (˜1.9 nm), and very low leakage currents (<3 nA/cm2). TFTs employing solution processed LaAlOy gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with hysteresis-free operation, low operation voltages (˜10 V), high on/off current modulation ratio of >106, subthreshold swing of ˜650 mV dec-1, and electron mobility of ˜12 cm2 V-1 s-1.

  7. Reliability in Short-Channel p-Type Polycrystalline Silicon Thin-Film Transistor under High Gate and Drain Bias Stress

    NASA Astrophysics Data System (ADS)

    Choi, Sung-Hwan; Kim, Sun-Jae; Mo, Yeon-Gon; Kim, Hye-Dong; Han, Min-Koo

    2010-03-01

    We have investigated the electrical characteristics of short-channel p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under high gate and drain bias stress. We found that the threshold voltage of short-channel TFTs was significantly shifted in the negative direction owing to high gate and drain bias stress (ΔVTH = -2.08 V), whereas that of long-channel TFTs was rarely shifted in the negative direction (ΔVTH = -0.10 V). This negative shift of threshold voltage in the short-channel TFT may be attributed to interface state generation near the source junction and deep trap state creation near the drain junction between the poly-Si film and the gate insulator layer. It was also found that the gate-to-drain capacitance (CGD) characteristic of the stressed TFT severely stretched for the gate voltage below the flat band voltage VFB. The effects of high gate and drain bias stress are related to hot-hole-induced donor like interface state generation. The transfer characteristics of the forward and reverse modes after the high gate and drain bias stress also indicate that the interface state generation at the gate insulator/channel interface occurred near the source junction region.

  8. Reliability in Short-Channel p-Type Polycrystalline Silicon Thin-Film Transistor under High Gate and Drain Bias Stress

    NASA Astrophysics Data System (ADS)

    Sung-Hwan Choi,; Sun-Jae Kim,; Yeon-Gon Mo,; Hye-Dong Kim,; Min-Koo Han,

    2010-03-01

    We have investigated the electrical characteristics of short-channel p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under high gate and drain bias stress. We found that the threshold voltage of short-channel TFTs was significantly shifted in the negative direction owing to high gate and drain bias stress (Δ VTH = -2.08 V), whereas that of long-channel TFTs was rarely shifted in the negative direction (Δ VTH = -0.10 V). This negative shift of threshold voltage in the short-channel TFT may be attributed to interface state generation near the source junction and deep trap state creation near the drain junction between the poly-Si film and the gate insulator layer. It was also found that the gate-to-drain capacitance (CGD) characteristic of the stressed TFT severely stretched for the gate voltage below the flat band voltage VFB. The effects of high gate and drain bias stress are related to hot-hole-induced donor like interface state generation. The transfer characteristics of the forward and reverse modes after the high gate and drain bias stress also indicate that the interface state generation at the gate insulator/channel interface occurred near the source junction region.

  9. The Integration of Sub-10 nm Gate Oxide on MoS2 with Ultra Low Leakage and Enhanced Mobility

    PubMed Central

    Yang, Wen; Sun, Qing-Qing; Geng, Yang; Chen, Lin; Zhou, Peng; Ding, Shi-Jin; Zhang, David Wei

    2015-01-01

    The integration of ultra-thin gate oxide, especially at sub-10 nm region, is one of the principle problems in MoS2 based transistors. In this work, we demonstrate sub-10 nm uniform deposition of Al2O3 on MoS2 basal plane by applying ultra-low energy remote oxygen plasma pretreatment prior to atomic layer deposition. It is demonstrated that oxygen species in ultra-low energy plasma are physically adsorbed on MoS2 surfaces without making the flakes oxidized, and is capable of benefiting the mobility of MoS2 flake. Based on this method, top-gated MoS2 transistor with ultrathin Al2O3 dielectric is fabricated. With 6.6 nm Al2O3 as gate dielectric, the device shows gate leakage about 0.1 pA/μm2 at 4.5 MV/cm which is much lower than previous reports. Besides, the top-gated device shows great on/off ratio of over 108, subthreshold swing (SS) of 101 mV/dec and a mobility of 28 cm2/Vs. With further investigations and careful optimizations, this method can play an important role in future nanoelectronics. PMID:26146017

  10. Reliability of potassium ion electret in silicon oxide for vibrational energy harvester applications

    NASA Astrophysics Data System (ADS)

    Misawa, Kensuke; Sugiyama, Tatsuhiko; Hashiguchi, Gen; Toshiyoshi, Hiroshi

    2015-06-01

    In this paper, we report on the long-term reliability of potassium ion electret included in a thermally grown silicon oxide. The electret in this work is used in a microelectromechanical systems (MEMS) energy harvester to generate electrical current from mechanical vibration. A spring-mass system similar to a comb-drive electrostatic actuator is developed by silicon micromachining, and the surface is oxidized by wet-oxidation through a potassium hydroxide bubbler, thereby including potassium atoms at a high concentration. The potassium is then electrically polarized by an applied voltage of 150 V at 650 °C for 5 min. Degradation of the stored polarization potential is monitored in a vacuum of 1 × 10-3 Pa at elevated temperatures of 350, 400, and 450 °C. The time needed to cause a -1 dB decay of the potential is used as the lifetime of the electret, and the Arrhenius extrapolation plot suggested a life time of more than 400 years at 25 °C.

  11. Highly Conductive and Reliable Copper-Filled Isotropically Conductive Adhesives Using Organic Acids for Oxidation Prevention

    NASA Astrophysics Data System (ADS)

    Chen, Wenjun; Deng, Dunying; Cheng, Yuanrong; Xiao, Fei

    2015-07-01

    The easy oxidation of copper is one critical obstacle to high-performance copper-filled isotropically conductive adhesives (ICAs). In this paper, a facile method to prepare highly reliable, highly conductive, and low-cost ICAs is reported. The copper fillers were treated by organic acids for oxidation prevention. Compared with ICA filled with untreated copper flakes, the ICA filled with copper flakes treated by different organic acids exhibited much lower bulk resistivity. The lowest bulk resistivity achieved was 4.5 × 10-5 Ω cm, which is comparable to that of commercially available Ag-filled ICA. After 500 h of 85°C/85% relative humidity (RH) aging, the treated ICAs showed quite stable bulk resistivity and relatively stable contact resistance. Through analyzing the results of x-ray diffraction, x-ray photoelectron spectroscopy, and thermogravimetric analysis, we found that, with the assistance of organic acids, the treated copper flakes exhibited resistance to oxidation, thus guaranteeing good performance.

  12. Oxygen Defect-Induced Metastability in Oxide Semiconductors Probed by Gate Pulse Spectroscopy

    PubMed Central

    Lee, Sungsik; Nathan, Arokia; Jeon, Sanghun; Robertson, John

    2015-01-01

    We investigate instability mechanisms in amorphous In-Ga-Zn-O transistors based on bias and illumination stress-recovery experiments coupled with analysis using stretched exponentials and inverse Laplace transform to retrieve the distribution of activation energies associated with metastable oxygen defects. Results show that the recovery process after illumination stress is persistently slow by virtue of defect states with a broad range, 0.85 eV to 1.38 eV, suggesting the presence of ionized oxygen vacancies and interstitials. We also rule out charge trapping/detrapping events since this requires a much smaller activation energy ~0.53 eV, and which tends to be much quicker. These arguments are supported by measurements using a novel gate-pulse spectroscopy probing technique that reveals the post-stress ionized oxygen defect profile, including anti-bonding states within the conduction band. PMID:26446400

  13. A hot oxidant, 3-NO2Y122 radical, unmasks conformational gating in ribonucleotide reductase

    PubMed Central

    Yokoyama, Kenichi; Uhlin, Ulla; Stubbe, JoAnne

    2010-01-01

    Escherichia coli ribonucleotide reductase is an α2β2 complex that catalyzes the conversion of nucleotides to deoxynucleotides and requires a diferric-tyrosyl radical (Y•) cofactor to initiate catalysis. The initiation process requires long range proton-coupled electron transfer (PCET) over 35 Å between the two subunits by a specific pathway (Y122• → W48 → Y356 within β to Y731 → Y730 → C439 within α). The rate-limiting step in nucleotide reduction is the conformational gating of the PCET process, which masks the chemistry of radical propagation. 3-Nitrotyrosine (NO2Y) has recently been incorporated site-specifically in place of Y122 in β2. The protein as isolated contained a diferric cluster, but no nitrotyrosyl radical (NO2Y•) and was inactive. In the present paper we show that incubation of apo-Y122NO2Y-β2 with Fe2+ and O2 generates a diferric-NO2Y• that has a half-life of 40 s at 25 °C. Sequential mixing experiments, in which the cofactor is assembled to 1.2 NO2Y•/β2 and then mixed with α2, CDP, and ATP, have been analyzed by stopped flow spectroscopy, rapid freeze quench EPR spectroscopy and rapid chemical quench methods. These studies have for the first time unmasked the conformational gating. They reveal that the NO2Y• is reduced to the nitrotyrosinate with biphasic kinetics (283 and 67 s-1), that dCDP is produced at 107 s-1, and that a new Y• is produced at 97 s-1. Studies with pathway mutants suggest that the new Y• is predominantly located at 356 in β2. In conjunction with the crystal structure of Y122NO2Y-β2, a mechanism for PCET uncoupling in NO2Y•-RNR is proposed. PMID:20929229

  14. Oxidation of Phe454 in the Gating Segment Inactivates Trametes multicolor Pyranose Oxidase during Substrate Turnover

    PubMed Central

    Volc, Jindrich; Peterbauer, Clemens K.; Leitner, Christian; Haltrich, Dietmar

    2016-01-01

    The flavin-dependent enzyme pyranose oxidase catalyses the oxidation of several pyranose sugars at position C-2. In a second reaction step, oxygen is reduced to hydrogen peroxide. POx is of interest for biocatalytic carbohydrate oxidations, yet it was found that the enzyme is rapidly inactivated under turnover conditions. We studied pyranose oxidase from Trametes multicolor (TmPOx) inactivated either during glucose oxidation or by exogenous hydrogen peroxide using mass spectrometry. MALDI-MS experiments of proteolytic fragments of inactivated TmPOx showed several peptides with a mass increase of 16 or 32 Da indicating oxidation of certain amino acids. Most of these fragments contain at least one methionine residue, which most likely is oxidised by hydrogen peroxide. One peptide fragment that did not contain any amino acid residue that is likely to be oxidised by hydrogen peroxide (DAFSYGAVQQSIDSR) was studied in detail by LC-ESI-MS/MS, which showed a +16 Da mass increase for Phe454. We propose that oxidation of Phe454, which is located at the flexible active-site loop of TmPOx, is the first and main step in the inactivation of TmPOx by hydrogen peroxide. Oxidation of methionine residues might then further contribute to the complete inactivation of the enzyme. PMID:26828796

  15. Design and control of Ge-based metal-oxide-semiconductor interfaces for high-mobility field-effect transistors with ultrathin oxynitride gate dielectrics

    NASA Astrophysics Data System (ADS)

    Minoura, Yuya; Kasuya, Atsushi; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2013-07-01

    High-quality Ge-based metal-oxide-semiconductor (MOS) stacks were achieved with ultrathin oxynitride (GeON) gate dielectrics. An in situ process based on plasma nitridation of the base germanium oxide (GeO2) surface and subsequent metal electrode deposition was proven to be effective for suppressing electrical deterioration induced by the reaction at the metal/insulator interface. The electrical properties of the bottom GeON/Ge interface were further improved by both low-temperature oxidation for base GeO2 formation and high-temperature in situ vacuum annealing after plasma nitridation of the base oxide. Based on the optimized in situ gate stack fabrication process, very high inversion carrier mobility (μhole: 445 cm2/Vs, μelectron: 1114 cm2/Vs) was demonstrated for p- and n-channel Ge MOSFETs with Al/GeON/Ge gate stacks at scaled equivalent oxide thickness down to 1.4 nm.

  16. Phospho-silicate glass gated 4H-SiC metal-oxide-semiconductor devices: Phosphorus concentration dependence

    NASA Astrophysics Data System (ADS)

    Jiao, C.; Ahyi, A. C.; Xu, C.; Morisette, D.; Feldman, L. C.; Dhar, S.

    2016-04-01

    The correlation between phosphorus concentration in phospho-silicate glass (PSG) gate dielectrics and electrical properties of 4H-SiC MOS devices has been investigated. Varying P uptake in PSG is achieved by changing the POCl3 post-oxidation annealing temperature. The density of interface traps (Dit) at the PSG/4H-SiC interface decreases as the amount of interfacial P increases. Most significantly, the MOSFET channel mobility does not correlate with Dit for all samples, which is highly unusual for SiC MOSFETs. Further analysis reveals two types of field-effect mobility (μfe) behavior, depending on the annealing temperature. Annealing at 1000 °C improves the channel mobility most effectively, with a peak value ˜105 cm2 V-1 s-1, and results in a surface phonon scattering limited mobility at high oxide field. On the other hand, PSG annealed at other temperatures results in a surface roughness scattering limited mobility at similar field.

  17. A hot oxidant, 3-NO2Y122 radical, unmasks conformational gating in ribonucleotide reductase.

    PubMed

    Yokoyama, Kenichi; Uhlin, Ulla; Stubbe, JoAnne

    2010-11-01

    Escherichia coli ribonucleotide reductase is an α2β2 complex that catalyzes the conversion of nucleotides to deoxynucleotides and requires a diferric-tyrosyl radical (Y(•)) cofactor to initiate catalysis. The initiation process requires long-range proton-coupled electron transfer (PCET) over 35 Å between the two subunits by a specific pathway (Y(122)(•)→W(48)→Y(356) within β to Y(731)→Y(730)→C(439) within α). The rate-limiting step in nucleotide reduction is the conformational gating of the PCET process, which masks the chemistry of radical propagation. 3-Nitrotyrosine (NO(2)Y) has recently been incorporated site-specifically in place of Y(122) in β2. The protein as isolated contained a diferric cluster but no nitrotyrosyl radical (NO(2)Y(•)) and was inactive. In the present paper we show that incubation of apo-Y(122)NO(2)Y-β2 with Fe(2+) and O(2) generates a diferric-NO(2)Y(•) that has a half-life of 40 s at 25 °C. Sequential mixing experiments, in which the cofactor is assembled to 1.2 NO(2)Y(•)/β2 and then mixed with α2, CDP, and ATP, have been analyzed by stopped-flow absorption spectroscopy, rapid freeze quench EPR spectroscopy, and rapid chemical quench methods. These studies have, for the first time, unmasked the conformational gating. They reveal that the NO(2)Y(•) is reduced to the nitrotyrosinate with biphasic kinetics (283 and 67 s(-1)), that dCDP is produced at 107 s(-1), and that a new Y(•) is produced at 97 s(-1). Studies with pathway mutants suggest that the new Y(•) is predominantly located at 356 in β2. In consideration of these data and the crystal structure of Y(122)NO(2)Y-β2, a mechanism for PCET uncoupling in NO(2)Y(•)-RNR is proposed. PMID:20929229

  18. Bulk and interface trapping in the gate dielectric of GaN based metal-oxide-semiconductor high-electron-mobility transistors

    NASA Astrophysics Data System (ADS)

    Ťapajna, M.; Jurkovič, M.; Válik, L.; Haščík, Š.; Gregušová, D.; Brunner, F.; Cho, E.-M.; Kuzmík, J.

    2013-06-01

    The trapping phenomena in GaN metal-oxide-semiconductor high-electron mobility transistor structures with 10 and 20-nm thick Al2O3 gate dielectric grown by metal-organic chemical vapor deposition were deeply investigated using comprehensive capacitance-voltage measurements. By controlling the interface traps population, substantial electron trapping in the dielectric bulk was identified. Separation between the trapping process and the interface traps emission allowed us to determine distribution of interface trap density in a wide energy range. Temperature dependence of the trapping process indicates thermionic field emission of electrons from the gate into traps with a sheet density of ~1013 cm-2, located a few nm below the gate.

  19. Bulk and interface trapping in the gate dielectric of GaN based metal-oxide-semiconductor high-electron-mobility transistors

    NASA Astrophysics Data System (ADS)

    Ťapajna, M.; Jurkovič, M.; Válik, L.; Haščík, Š.; Gregušová, D.; Brunner, F.; Cho, E.-M.; Kuzmík, J.

    2013-06-01

    The trapping phenomena in GaN metal-oxide-semiconductor high-electron mobility transistor structures with 10 and 20-nm thick Al2O3 gate dielectric grown by metal-organic chemical vapor deposition were deeply investigated using comprehensive capacitance-voltage measurements. By controlling the interface traps population, substantial electron trapping in the dielectric bulk was identified. Separation between the trapping process and the interface traps emission allowed us to determine distribution of interface trap density in a wide energy range. Temperature dependence of the trapping process indicates thermionic field emission of electrons from the gate into traps with a sheet density of ˜1013 cm-2, located a few nm below the gate.

  20. The Impacts of Contact Etch Stop Layer Thickness and Gate Height on Channel Stress in Strained N-Metal Oxide Semiconductor Field Effect Transistors.

    PubMed

    Lin, K C; Twu, M J; Deng, R H; Liu, C H

    2015-04-01

    The stress induced by strain in the channel of metal oxide semiconductor field effect transistors (MOSFET) is an effective method to boost the device performance. The geometric dimensions of spacer, gate height, and the contact etch stop layer (CESL) are important factors among the feasible booster. This study utilized the mismatch of the thermal expansion coefficients of stressors to simulate the process-induced stress in the N-MOSFET. Different temperatures are applied to different region of the device to generate the required strain. The analysis was performed by well-developed finite element package. The composite spacers with variant width of inserted silicon nitride (SiO2/SiN/SiO2, ONO) were proposed and their impacts on channel stress were compared. Two aspects of the impacts of those factors on the channel stress in the longitudinal direction for N-MOSFET with variant channel length were investigated. Firstly, the channel stresses of device without CESL for different gate heights were studied. Secondly, with stress applied to CESL and ONO spacers, the induced stresses in the channel were analyzed for long/short gate length. Two conclusions were drawn from the results of simulation. The N-MOSFET device without CESL shows that the stressed spacer alone generates compressive stress and the magnitude increases along with higher gate height. The channel stress becomes tensile for device with CESL and increases when the thickness of CESL and the height of gate increase, especially for device with shorter gate length. The gate height plays more significant role in inducing channel stress compared with the thickness of CESL. The channel stress can be used to quantify the mobility of electron/hole for strained MOSFET device. Therefore, with the guideline disclosed in this study, better device performance can be expected for N-MOSFET. PMID:26353480

  1. The impact of implantation sequence on the characterization of n-MOSFET's with gate oxide grown on nitrogen-implanted Si substrate

    NASA Astrophysics Data System (ADS)

    Wu, You-Lin

    2002-08-01

    Both of the nitrogen implantation and threshold-voltage adjustment implantation introduce dopant atoms near the SiO 2/Si interface during the fabrication of n-channel metal-oxide-semiconductor field-effect transistor (n-MOSFET's) with gate oxide grown on nitrogen implanted silicon substrate. This work examined the impact of implantation sequence on the characterization of n-MOSFET's with gate oxide grown on nitrogen implanted silicon substrate. It is found that the sequence of nitrogen implantation and boron implantation affects both the electrical characteristics and hot-carrier properties of n-MOSFET's. It is found that no channel mobility degradation, less interface state density, lower subthreshold leakage current and better hot-carrier resistance can be achieved in the n-MOSFET's if the threshold-voltage adjustment implantation is performed after the nitrogen implantation during the gate oxide preparation. However lower channel mobility, higher interface state density, higher subthreshold leakage current and less hot-carrier resistance were observed if the implantation sequence was reversed.

  2. Electrical Properties and Reliability Analysis of Solution-Processed Indium Tin Zinc Oxide Thin Film Transistors with O2-Plasma Treatment.

    PubMed

    Ko, Sun Wook; Kim, Soon Kon; Kim, Jong Min; Cho, Jae Hee; Park, Hyoung Sun; Choi, Byoung Deog

    2015-10-01

    In this paper, we report the effects of O2-plasma treatment on the reliability and electrical properties of indium tin zinc oxide (ITZO) films. Excellent electrical properties, including a saturation mobility (μsat) of ~20.2 cm2/V · s, a threshold voltage (VTH) of ~-6.8 V, a sub-threshold swing (S.S) of ~0.956 V/decade, and an on/off current ratio (ION/OFF) of ~10(5) can be found with a molarity of 0.4 M and ratio of In:Zn:Sn = 2:1:2. Following O2-plasma treatment, it was confirmed that the electrical properties of the ITZO films are improved when compared to the untreated films. The devices showed a decreased S.S of ~0.51 V/decade, while the VTH and ION/OFF tended to increase. To determine the reliability of a-ITZO TFTs, we analyzed the electrical characteristics according to gate bias stress, VG,stress = 10 V for 4000 s. Improved reliability was confirmed when compared with the variation in threshold voltage prior to O2-plasma treatment, most likely stemming from a smooth surface on the active layer as a result of O2-plasma treatment. We were able to obtain a solution a-ITZO film transmittance of 92% in the visible light region (400~700 nm). These results show that a-ITZO TFTs fabricated via solution process with optimized molar ratio exhibit good electrical properties. a-ITZO films fabricated via spin-coating are a visible alternative to those fabricated via high-cost sputtering methods, and are applicable in flexible and transparent electronics. PMID:26726354

  3. Near-IR squaraine dye-loaded gated periodic mesoporous organosilica for photo-oxidation of phenol in a continuous-flow device.

    PubMed

    Borah, Parijat; Sreejith, Sivaramapanicker; Anees, Palapuravan; Menon, Nishanth Venugopal; Kang, Yuejun; Ajayaghosh, Ayyappanpillai; Zhao, Yanli

    2015-09-01

    Periodic mesoporous organosilica (PMO) has been widely used for the fabrication of a variety of catalytically active materials. We report the preparation of novel photo-responsive PMO with azobenzene-gated pores. Upon activation, the azobenzene gate undergoes trans-cis isomerization, which allows an unsymmetrical near-infrared squaraine dye (Sq) to enter into the pores. The gate closure by cis-trans isomerization of the azobenzene unit leads to the safe loading of the monomeric dye inside the pores. The dye-loaded and azobenzene-gated PMO (Sq-azo@PMO) exhibits excellent generation of reactive oxygen species upon excitation at 664 nm, which can be effectively used for the oxidation of phenol into benzoquinone in aqueous solution. Furthermore, Sq-azo@PMO as the catalyst was placed inside a custom-built, continuous-flow device to carry out the photo-oxidation of phenol to benzoquinone in the presence of 664-nm light. By using the device, about 23% production of benzoquinone with 100% selectivity was achieved. The current research presents a prototype of transforming heterogeneous catalysts toward practical use. PMID:26601266

  4. Near-IR squaraine dye–loaded gated periodic mesoporous organosilica for photo-oxidation of phenol in a continuous-flow device

    PubMed Central

    Borah, Parijat; Sreejith, Sivaramapanicker; Anees, Palapuravan; Menon, Nishanth Venugopal; Kang, Yuejun; Ajayaghosh, Ayyappanpillai; Zhao, Yanli

    2015-01-01

    Periodic mesoporous organosilica (PMO) has been widely used for the fabrication of a variety of catalytically active materials. We report the preparation of novel photo-responsive PMO with azobenzene-gated pores. Upon activation, the azobenzene gate undergoes trans-cis isomerization, which allows an unsymmetrical near-infrared squaraine dye (Sq) to enter into the pores. The gate closure by cis-trans isomerization of the azobenzene unit leads to the safe loading of the monomeric dye inside the pores. The dye-loaded and azobenzene-gated PMO (Sq-azo@PMO) exhibits excellent generation of reactive oxygen species upon excitation at 664 nm, which can be effectively used for the oxidation of phenol into benzoquinone in aqueous solution. Furthermore, Sq-azo@PMO as the catalyst was placed inside a custom-built, continuous-flow device to carry out the photo-oxidation of phenol to benzoquinone in the presence of 664-nm light. By using the device, about 23% production of benzoquinone with 100% selectivity was achieved. The current research presents a prototype of transforming heterogeneous catalysts toward practical use. PMID:26601266

  5. Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

    SciTech Connect

    Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A.

    2015-07-28

    Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

  6. Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

    NASA Astrophysics Data System (ADS)

    Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A.

    2015-07-01

    Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

  7. Modeling of n-InAs metal oxide semiconductor capacitors with high-κ gate dielectric

    NASA Astrophysics Data System (ADS)

    Babadi, A. S.; Lind, E.; Wernersson, L. E.

    2014-12-01

    A qualitative analysis on capacitance-voltage and conductance data for high-κ/InAs capacitors is presented. Our measured data were evaluated with a full equivalent circuit model, including both majority and minority carriers, as well as interface and border traps, formulated for narrow band gap metal-oxide-semiconductor capacitors. By careful determination of interface trap densities, distribution of border traps across the oxide thickness, and taking into account the bulk semiconductor response, it is shown that the trap response has a strong effect on the measured capacitances. Due to the narrow bandgap of InAs, there can be a large surface concentration of electrons and holes even in depletion, so a full charge treatment is necessary.

  8. Modeling of n-InAs metal oxide semiconductor capacitors with high-κ gate dielectric

    SciTech Connect

    Babadi, A. S. Lind, E.; Wernersson, L. E.

    2014-12-07

    A qualitative analysis on capacitance-voltage and conductance data for high-κ/InAs capacitors is presented. Our measured data were evaluated with a full equivalent circuit model, including both majority and minority carriers, as well as interface and border traps, formulated for narrow band gap metal-oxide-semiconductor capacitors. By careful determination of interface trap densities, distribution of border traps across the oxide thickness, and taking into account the bulk semiconductor response, it is shown that the trap response has a strong effect on the measured capacitances. Due to the narrow bandgap of InAs, there can be a large surface concentration of electrons and holes even in depletion, so a full charge treatment is necessary.

  9. Band alignment of vanadium oxide as an interlayer in a hafnium oxide-silicon gate stack structure

    NASA Astrophysics Data System (ADS)

    Zhu, Chiyu; Kaur, Manpuneet; Tang, Fu; Liu, Xin; Smith, David J.; Nemanich, Robert J.

    2012-10-01

    Vanadium oxide (VO2) is a narrow band gap material (Eg = 0.7 eV) with a thermally induced insulator-metal phase transition at ˜343 K and evidence of an electric field induced transition at T < 343 K. To explore the electronic properties of VO2, a sandwich structure was prepared with a 2 nm VO2 layer embedded between an oxidized Si(100) surface and a 2 nm hafnium oxide (HfO2) layer. The layer structure was confirmed with high resolution transmission electron microscopy. The electronic properties were characterized with x-ray and ultraviolet photoemission spectroscopy, and the band alignment was deduced on both n-type and p-type Si substrates. The valence band offset between VO2 and SiO2 is measured to be 4.0 eV. The valence band offset between HfO2 and VO2 is measured to be ˜3.4 eV. The band relation developed from these results demonstrates the potential for charge storage and switching for the embedded VO2 layer.

  10. Study of Novel Floating-Gate Oxide Semiconductor Memory Using Indium-Gallium-Zinc Oxide for Low-Power System-on-Panel Applications

    NASA Astrophysics Data System (ADS)

    Yamauchi, Yoshimitsu; Kamakura, Yoshinari; Isagi, Yousuke; Matsuoka, Toshimasa; Malotaux, Satoshi

    2013-09-01

    A novel floating-gate oxide semiconductor (FLOTOS) memory using a wide-band-gap indium-gallium-zinc oxide (IGZO) is presented for low-power system-on-panel applications. An IGZO thin-film-transistor (TFT) is used as a memory transistor for controlling read current as well as a switching transistor for storing charges in a storage capacitor (Cs). The FLOTOS memory is fabricated using a standard IGZO TFT process without any additional process or mask steps. The proposed precharge-assisted threshold voltage compensation technique makes it possible to realize an infinite number of write cycles and a low-power write operation with a bit-line voltage of 5 V. Furthermore, excellent data retention longer than 10 h is obtained at 60 °C even under the worst bias-stress condition of read operation with the ultra low off-state leakage (2.8×10-20 A/µm) of the IGZO TFTs, which is estimated to be smaller by more than 7 orders of magnitude than that of polycrystalline silicon TFTs.

  11. The effect of post oxide deposition annealing on the effective work function in metal/Al{sub 2}O{sub 3}/InGaAs gate stack

    SciTech Connect

    Winter, R.; Krylov, I.; Eizenberg, M.; Ahn, J.; McIntyre, P. C.

    2014-05-19

    The effect of post oxide deposition annealing on the effective work function in metal/Al{sub 2}O{sub 3}/ InGaAs gate stacks was investigated. Using a systematic method for effective work function extraction, a shift of 0.3 ± 0.1 eV was found between the effective work function of forming gas annealed samples and vacuum annealed samples. The electrical measurements enabled us to obtain the band alignment of the metal/Al{sub 2}O{sub 3}/InGaAs gate stack. This band alignment was confirmed by X-ray photoelectron spectroscopy. The measured shift in the effective work function between different annealing ambient may be attributed to indium out-diffusion during post oxide deposition annealing that is observed in forming gas anneal to a much larger extent than in vacuum.

  12. INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Quantum-Mechanical Study on Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Hu, Guang-Xi; Wang, Ling-Li; Liu, Ran; Tang, Ting-Ao; Qiu, Zhi-Jun

    2010-10-01

    As the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) scales into the nanometer regime, quantum mechanical effects are becoming more and more significant. In this work, a model for the surrounding-gate (SG) nMOSFET is developed. The Schrödinger equation is solved analytically. Some of the solutions are verified via results obtained from simulations. It is found that the percentage of the electrons with lighter conductivity mass increases as the silicon body radius decreases, or as the gate voltage reduces, or as the temperature decreases. The centroid of inversion-layer is driven away from the silicon-oxide interface towards the silicon body, therefore the carriers will suffer less scattering from the interface and the electrons effective mobility of the SG nMOSFETs will be enhanced.

  13. Effect of size and position of gold nanocrystals embedded in gate oxide of SiO2/Si MOS structures

    NASA Astrophysics Data System (ADS)

    Chakraborty, Chaitali; Bose, Chayanika

    2016-02-01

    The influence of single and double layered gold (Au) nanocrystals (NC), embedded in SiO2 matrix, on the electrical characteristics of metal-oxide-semiconductor (MOS) structures is reported in this communication. The size and position of the NCs are varied and study is made using Sentaurus TCAD simulation tools. In a single NC-layered MOS structure, the role of NCs is more prominent when they are placed closer to SiO2/Si‑substrate interface than to SiO2/Al-gate interface. In MOS structures with larger NC dots and double layered NCs, the charge storage capacity is increased due to charging of the dielectric in the presence of NCs. Higher breakdown voltage and smaller leakage current are also obtained in the case of dual NC-layered MOS device. A new phenomenon of smearing out of the capacitance-voltage curve is observed in the presence of dual NC layer indicating generation of interface traps. An internal electric field developed between these two charged NC layers is expected to generate such interface traps at the SiO2/Si interface.

  14. Quantum Mechanical Effects on the Threshold Voltage of Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Hu, Guang-Xi; Liu, Ran; Qiu, Zhi-Jun; Wang, Ling-Li; Tang, Ting-Ao

    2010-03-01

    A model for a metal-oxide-semiconductor field-effect transistor (MOSFET) with a double gate (DG) is developed. Quantum mechanical effects on the threshold voltage (VTH) are modeled and investigated analytically. The analytic model shows how VTH is increased with quantum mechanical effect. The model is applicable to both symmetric DG (SDG) and asymmetric DG (ADG) nMOSFETs, and is also applicable to both doped and undoped DG nMOSFETs. The analytic results are verified by comparing with the results obtained from simulations using Schred, and good agreement is observed. The VTH of an ADG nMOSFET will shift more than that of an SDG nMOSFET, and the VTH of a DG transistor with (110)-silicon (Si) orientation will shift more than that of a DG transistor with (100)-Si orientation. When the silicon thickness tsi < 3 nm, the VTH shift will be significant, and one should be careful in the use of an extremely thin silicon body. When the body doping density (NA) is not high (<1018 cm-3), the VTH shift is almost the same for different NA. When NA > 1018 cm-3, the higher the NA, the more the VTH shift.

  15. Theoretical Study of Triboelectric-Potential Gated/Driven Metal-Oxide-Semiconductor Field-Effect Transistor.

    PubMed

    Peng, Wenbo; Yu, Ruomeng; He, Yongning; Wang, Zhong Lin

    2016-04-26

    Triboelectric nanogenerator has drawn considerable attentions as a potential candidate for harvesting mechanical energies in our daily life. By utilizing the triboelectric potential generated through the coupling of contact electrification and electrostatic induction, the "tribotronics" has been introduced to tune/control the charge carrier transport behavior of silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET). Here, we perform a theoretical study of the performances of tribotronic MOSFET gated by triboelectric potential in two working modes through finite element analysis. The drain-source current dependence on contact-electrification generated triboelectric charges, gap separation distance, and externally applied bias are investigated. The in-depth physical mechanism of the tribotronic MOSFET operations is thoroughly illustrated by calculating and analyzing the charge transfer process, voltage relationship to gap separation distance, and electric potential distribution. Moreover, a tribotronic MOSFET working concept is proposed, simulated and studied for performing self-powered FET and logic operations. This work provides a deep understanding of working mechanisms and design guidance of tribotronic MOSFET for potential applications in micro/nanoelectromechanical systems (MEMS/NEMS), human-machine interface, flexible electronics, and self-powered active sensors. PMID:27077327

  16. Reliability investigation of high-k/metal gate in nMOSFETs by three-dimensional kinetic Monte-Carlo simulation with multiple trap interactions

    NASA Astrophysics Data System (ADS)

    Li, Yun; Jiang, Hai; Lun, Zhiyuan; Wang, Yijiao; Huang, Peng; Hao, Hao; Du, Gang; Zhang, Xing; Liu, Xiaoyan

    2016-04-01

    Degradation behaviors in the high-k/metal gate stacks of nMOSFETs are investigated by three-dimensional (3D) kinetic Monte-Carlo (KMC) simulation with multiple trap coupling. Novel microscopic mechanisms are simultaneously considered in a compound system: (1) trapping/detrapping from/to substrate/gate; (2) trapping/detrapping to other traps; (3) trap generation and recombination. Interacting traps can contribute to random telegraph noise (RTN), bias temperature instability (BTI), and trap-assisted tunneling (TAT). Simulation results show that trap interaction induces higher probability and greater complexity in trapping/detrapping processes and greatly affects the characteristics of RTN and BTI. Different types of trap distribution cause largely different behaviors of RTN, BTI, and TAT. TAT currents caused by multiple trap coupling are sensitive to the gate voltage. Moreover, trap generation and recombination have great effects on the degradation of HfO2-based nMOSFETs under a large stress.

  17. The development of non-uniform deposition of holes in gate oxides

    SciTech Connect

    Freitag, R.K.; Dozier, C.M.; Brown, D.B.; Burke, E.A.

    1988-12-01

    The subthreshold technique was used to study irradiated MOS transistors at 80 K. Stretchout of the subthreshold curve demonstrated production of lateral non-uniformities (LNUs) in the hole distribution. The LNUs were analyzed in terms of (a) a parallel transistor model, and (b) the statistics of the non-uniform distribution of dose deposition in the SiO/sub 2/. The results confirm the hypothesis that at 80 K the principal source of LNUs is the granularity in dose deposition. The relative standard deviation for the deposited dose is larger for thin oxides, for 10 kev x-rays (as opposed to Co-60), and at low doses. These physical phenomena are predicted to have a significant effect at room temperature also.

  18. Enhanced Total Ionizing Dose Hardness of Deep Sub-Micron Partially Depleted Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Field Effect Transistors by Applying Larger Back-Gate Voltage Stress

    NASA Astrophysics Data System (ADS)

    Zheng, Qi-Wen; Cui, Jiang-Wei; Yu, Xue-Feng; Guo, Qi; Zhou, Hang; Ren, Di-Yuan

    2014-12-01

    The larger back-gate voltage stress is applied on 130 nm partially depleted silicon-on-insulator n-type metal-oxide-semiconductor field-effect transistors isolated by shallow trench isolation. The experimental results show that the back-gate sub-threshold hump of the device is eliminated by stress. This observed behavior is caused by the high electric field in the oxide near the bottom corner of the silicon island. The total ionizing dose hardness of devices with pre back-gate stress is enhanced by the interface states induced by stress.

  19. Role of PheE15 Gate in Ligand Entry and Nitric Oxide Detoxification Function of Mycobacterium tuberculosis Truncated Hemoglobin N

    PubMed Central

    Bidon-Chanal, Axel; Forti, Flavio; Martí, Marcelo A.; Boechi, Leonardo; Estrin, Dario A.; Dikshit, Kanak L.; Luque, F. Javier

    2012-01-01

    The truncated hemoglobin N, HbN, of Mycobacterium tuberculosis is endowed with a potent nitric oxide dioxygenase (NOD) activity that allows it to relieve nitrosative stress and enhance in vivo survival of its host. Despite its small size, the protein matrix of HbN hosts a two-branched tunnel, consisting of orthogonal short and long channels, that connects the heme active site to the protein surface. A novel dual-path mechanism has been suggested to drive migration of O2 and NO to the distal heme cavity. While oxygen migrates mainly by the short path, a ligand-induced conformational change regulates opening of the long tunnel branch for NO, via a phenylalanine (PheE15) residue that acts as a gate. Site-directed mutagenesis and molecular simulations have been used to examine the gating role played by PheE15 in modulating the NOD function of HbN. Mutants carrying replacement of PheE15 with alanine, isoleucine, tyrosine and tryptophan have similar O2/CO association kinetics, but display significant reduction in their NOD function. Molecular simulations substantiated that mutation at the PheE15 gate confers significant changes in the long tunnel, and therefore may affect the migration of ligands. These results support the pivotal role of PheE15 gate in modulating the diffusion of NO via the long tunnel branch in the oxygenated protein, and hence the NOD function of HbN. PMID:23145144

  20. Impacts of Ti on electrical properties of Ge metal-oxide-semiconductor capacitors with ultrathin high- k LaTiON gate dielectric

    NASA Astrophysics Data System (ADS)

    Xu, H. X.; Xu, J. P.; Li, C. X.; Chan, C. L.; Lai, P. T.

    2010-06-01

    Ge Metal-Oxide-Semiconductor (MOS) capacitors with LaON gate dielectric incorporating different Ti contents are fabricated and their electrical properties are measured and compared. It is found that Ti incorporation can increase the dielectric permittivity, and the higher the Ti content, the larger is the permittivity. However, the interfacial and gate-leakage properties become poorer as the Ti content increases. Therefore, optimization of Ti content is important in order to obtain a good trade-off among the electrical properties of the device. For the studied range of the Ti/La2O3 ratio, a suitable Ti/La2O3 ratio of 14.7% results in a high relative permittivity of 24.6, low interface-state density of 3.1×1011 eV-1 cm-2, and relatively low gate-leakage current density of 2.0×10-3 A cm-2 at a gate voltage of 1 V.

  1. Metal-Oxide-Semiconductor Field-Effect-Transistors Possessing Step Functional I-V Curves Caused by the Punch Through between Drain and Inversion Layer of the Gate

    NASA Astrophysics Data System (ADS)

    Karasawa, Shinji; Yamanouchi, Kazuhiko; Tachibana, Yukio

    1992-02-01

    Through measurements of an Al gate p-channel Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) with a gap between the gate and drain, the behavior of the minority carrier in the depletion layer is clarified. The turn-on drain voltage depends upon the length and the density of impurity on the punch-through area. That is, Vd{=}-4 V for Lgap{=}0.5 μm in 3˜5 Ω\\cdotcm n-Si wafer and Vd{=}-3 V for Lgap{=}2.0 μm in 120˜200 Ω\\cdotcm n-Si wafer. The abrupt step functional I-V curve is revealed under the condition of low gate voltage. There are surface effects by which the higher the gate voltage, the lower the turn-on voltage of the drain becomes. The hole mobility in the depletion layer made from lightly doped < 111> wafer abruptly decreases when the temperature is lowered to below 20 K and the turn-on voltage on the step function MOSFET increases remarkably at 4.2 K.

  2. Hole trapping in thermal oxides grown under various oxidation conditions using avalanche injection in poly-silicon gate structures

    NASA Astrophysics Data System (ADS)

    Anand, K. V.; Cairns, B. R.; Strain, R. J.

    1985-03-01

    I/v data (where I is the dc current and v is the maximum value of the ac applied voltage across the device) was analyzed with respect to the theory and it was shown that the hole temperature not only depends on the substrate doping density and the electric field as measured by the Delta V subscript FB is not only a characteristic of the way that an oxide is grown and annealed, but it also depends on the quality of the substrate and its detailed thermal history. This substrate effect shows itself in the I/v characteristic of a particular device. If the dc current Idc was kept constant at a particular level (as was the case for our experiments), then the v value would represent the temperature of the hot carriers. Since the evidence suggests that the hot carriers generate trap levels, then any change in carrier temperature would reflect in Delta V subscript FB. These substrate related effects were found to be significant.

  3. Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating

    PubMed Central

    Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S.; Takeuchi, Ichiro; Greene, Richard. L.

    2016-01-01

    The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2−xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of −2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected. PMID:27221198

  4. Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating

    NASA Astrophysics Data System (ADS)

    Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S.; Takeuchi, Ichiro; Greene, Richard. L.

    2016-05-01

    The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2‑xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of ‑2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected.

  5. Chemical Bonding, Interfaces and Defects in Hafnium Oxide/Germanium Oxynitride Gate Stacks on Ge (100)

    SciTech Connect

    Oshima, Yasuhiro; Sun, Yun; Kuzum, Duygu; Sugawara, Takuya; Saraswat, Krishna C.; Pianetta, Piero; McIntyre, Paul C.; /Stanford U., Materials Sci. Dept.

    2008-10-31

    Correlations among interface properties and chemical bonding characteristics in HfO{sub 2}/GeO{sub x}N{sub y}/Ge MIS stacks were investigated using in-situ remote nitridation of the Ge (100) surface prior to HfO{sub 2} atomic layer deposition (ALD). Ultra thin ({approx}1.1 nm), thermally stable and aqueous etch-resistant GeO{sub x}N{sub y} interfaces layers that exhibited Ge core level photoelectron spectra (PES) similar to stoichiometric Ge{sub 3}N{sub 4} were synthesized. To evaluate GeO{sub x}N{sub y}/Ge interface defects, the density of interface states (D{sub it}) was extracted by the conductance method across the band gap. Forming gas annealed (FGA) samples exhibited substantially lower D{sub it} ({approx} 1 x 10{sup 12} cm{sup -2} eV{sup -1}) than did high vacuum annealed (HVA) and inert gas anneal (IGA) samples ({approx} 1x 10{sup 13} cm{sup -2} eV{sup -1}). Germanium core level photoelectron spectra from similar FGA-treated samples detected out-diffusion of germanium oxide to the HfO{sub 2} film surface and apparent modification of chemical bonding at the GeO{sub x}N{sub y}/Ge interface, which is related to the reduced D{sub it}.

  6. Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating.

    PubMed

    Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S; Takeuchi, Ichiro; Greene, Richard L

    2016-01-01

    The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2-xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of -2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected. PMID:27221198

  7. Universal Superreplication of Unitary Gates

    NASA Astrophysics Data System (ADS)

    Chiribella, G.; Yang, Y.; Huang, C.

    2015-03-01

    Quantum states obey an asymptotic no-cloning theorem, stating that no deterministic machine can reliably replicate generic sequences of identically prepared pure states. In stark contrast, we show that generic sequences of unitary gates can be replicated deterministically at nearly quadratic rates, with an error vanishing on most inputs except for an exponentially small fraction. The result is not in contradiction with the no-cloning theorem, since the impossibility of deterministically transforming pure states into unitary gates prevents the application of the gate replication protocol to states. In addition to gate replication, we show that N parallel uses of a completely unknown unitary gate can be compressed into a single gate acting on O (log2N ) qubits, leading to an exponential reduction of the amount of quantum communication needed to implement the gate remotely.

  8. Universal superreplication of unitary gates.

    PubMed

    Chiribella, G; Yang, Y; Huang, C

    2015-03-27

    Quantum states obey an asymptotic no-cloning theorem, stating that no deterministic machine can reliably replicate generic sequences of identically prepared pure states. In stark contrast, we show that generic sequences of unitary gates can be replicated deterministically at nearly quadratic rates, with an error vanishing on most inputs except for an exponentially small fraction. The result is not in contradiction with the no-cloning theorem, since the impossibility of deterministically transforming pure states into unitary gates prevents the application of the gate replication protocol to states. In addition to gate replication, we show that N parallel uses of a completely unknown unitary gate can be compressed into a single gate acting on O(log_{2}N) qubits, leading to an exponential reduction of the amount of quantum communication needed to implement the gate remotely. PMID:25860728

  9. Effect of proton irradiation dose on InAlN/GaN metal-oxide semiconductor high electron mobility transistors with Al2O3 gate oxide

    DOE PAGESBeta

    Ahn, Shihyun; Kim, Byung -Jae; Lin, Yi -Hsuan; Ren, Fan; Pearton, Stephen J.; Yang, Gwangseok; Kim, Jihyun; Kravchenko, Ivan I.

    2016-07-26

    The effects of proton irradiation on the dc performance of InAlN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) with Al2O3 as the gate oxide were investigated. The InAlN/GaN MOSHEMTs were irradiated with doses ranging from 1×1013 to 1×1015cm–2 at a fixed energy of 5MeV. There was minimal damage induced in the two dimensional electron gas at the lowest irradiation dose with no measurable increase in sheet resistance, whereas a 9.7% increase of the sheet resistance was observed at the highest irradiation dose. By sharp contrast, all irradiation doses created more severe degradation in the Ohmic metal contacts, with increases of specificmore » contact resistance from 54% to 114% over the range of doses investigated. These resulted in source-drain current–voltage decreases ranging from 96 to 242 mA/mm over this dose range. The trap density determined from temperature dependent drain current subthreshold swing measurements increased from 1.6 × 1013 cm–2 V–1 for the reference MOSHEMTs to 6.7 × 1013 cm–2 V–1 for devices irradiated with the highest dose. In conclusion, the carrier removal rate was 1287 ± 64 cm–1, higher than the authors previously observed in AlGaN/GaN MOSHEMTs for the same proton energy and consistent with the lower average bond energy of the InAlN.« less

  10. Near interface traps in SiO2/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

    NASA Astrophysics Data System (ADS)

    Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena; Roccaforte, Fabrizio

    2016-07-01

    This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO2/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in "gate-controlled-diode" configuration. The measurements revealed an anomalous non-steady conduction under negative bias (VG > |20 V|) through the SiO2/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (Ntrap ˜ 2 × 1011 cm-2).

  11. High mobility field effect transistor based on BaSnO{sub 3} with Al{sub 2}O{sub 3} gate oxide

    SciTech Connect

    Park, Chulkwon; Kim, Useong; Ju, Chan Jong; Park, Ji Sung; Kim, Young Mo; Char, Kookrin

    2014-11-17

    We fabricated an n-type accumulation-mode field effect transistor based on BaSnO{sub 3} transparent perovskite semiconductor, taking advantage of its high mobility and oxygen stability. We used the conventional metal-insulator-semiconductor structures: (In,Sn){sub 2}O{sub 3} as the source, drain, and gate electrodes, Al{sub 2}O{sub 3} as the gate insulator, and La-doped BaSnO{sub 3} as the semiconducting channel. The Al{sub 2}O{sub 3} gate oxide was deposited by atomic layer deposition technique. At room temperature, we achieved the field effect mobility value of 17.8 cm{sup 2}/Vs and the I{sub on}/I{sub off} ratio value higher than 10{sup 5} for V{sub DS} = 1 V. These values are higher than those previously reported on other perovskite oxides, in spite of the large density of threading dislocations in the BaSnO{sub 3} on SrTiO{sub 3} substrates. However, a relatively large subthreshold swing value was found, which we attribute to the large density of charge traps in the Al{sub 2}O{sub 3} as well as the threading dislocations.

  12. Gate protective device for insulated gate field-effect transistors

    NASA Technical Reports Server (NTRS)

    Sunshine, R. A.

    1972-01-01

    Device, which protects insulated gate field-effect transistors, improves reliability through utilization of layers of conductive material on top of each alternating semiconductor material region. Separation of layers is necessary to prevent shorting out junctions between alternating regions.

  13. Effect of Pr Valence State on Interfacial Structure and Electrical Properties of Pr Oxide/PrON/Ge Gate Stack Structure

    NASA Astrophysics Data System (ADS)

    Kato, Kimihiko; Sakashita, Mitsuo; Takeuchi, Wakana; Kondo, Hiroki; Nakatsuka, Osamu; Zaima, Shigeaki

    2011-04-01

    In this study, we investigated the valence state and chemical bonding state of Pr in a Pr oxide/PrON/Ge structure. We clarified the relationship between the valence state of Pr and the Pr oxide/Ge interfacial reaction using Pr oxide/Ge and Pr oxide/PrON/Ge samples. We found the formation of three Pr oxide phases in Pr oxide films; hexagonal Pr2O3 (h-Pr2O3) (Pr3+), cubic Pr2O3 (c-Pr2O3) (Pr3+), and c-PrO2 (Pr4+). We also investigated the effect of a nitride interlayer on the interfacial reaction in Pr oxide/Ge gate stacks. In a sample with a nitride interlayer (Pr oxide/PrON/Ge), metallic Pr-Pr bonds are also formed in the c-Pr2O3 film. After annealing in H2 ambient, the diffusion of Ge into Pr oxide is not observed in this sample. Pr-Pr bonds probably prevent the interfacial reaction and Ge oxide formation, considering that the oxygen chemical potential of this film is lower than that of a GeO2/Ge system. On the other hand, the rapid thermal oxidation (RTO) treatment terminates the O vacancies and defects in c-Pr2O3. As a result, c-PrO2 with tetravalent Pr is formed in the Pr oxide/PrON/Ge sample with RTO. In this sample, the leakage current density is effectively decreased in comparison with the sample without RTO. Hydrogen termination works effectively in Pr oxide/PrON/Ge samples with and without RTO, and we can achieve an interface state density of as low as 4 ×1011 eV-1·cm-2.

  14. A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stress

    NASA Astrophysics Data System (ADS)

    Niang, K. M.; Barquinha, P. M. C.; Martins, R. F. P.; Cobb, B.; Powell, M. J.; Flewitt, A. J.

    2016-02-01

    Thin film transistors (TFTs) employing an amorphous indium gallium zinc oxide (a-IGZO) channel layer exhibit a positive shift in the threshold voltage under the application of positive gate bias stress (PBS). The time and temperature dependence of the threshold voltage shift was measured and analysed using the thermalization energy concept. The peak energy barrier to defect conversion is extracted to be 0.75 eV and the attempt-to-escape frequency is extracted to be 107 s-1. These values are in remarkable agreement with measurements in a-IGZO TFTs under negative gate bias illumination stress (NBIS) reported recently (Flewitt and Powell, J. Appl. Phys. 115, 134501 (2014)). This suggests that the same physical process is responsible for both PBS and NBIS, and supports the oxygen vacancy defect migration model that the authors have previously proposed.

  15. GaN metal-oxide-semiconductor field-effect transistors on AlGaN/GaN heterostructure with recessed gate

    NASA Astrophysics Data System (ADS)

    Wang, Qingpeng; Ao, Jin-Ping; Wang, Pangpang; Jiang, Ying; Li, Liuan; Kawaharada, Kazuya; Liu, Yang

    2015-04-01

    GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure with a recess gate were fabricated and characterized. The device showed good pinch-off characteristics and a maximum field-effect mobility of 145.2 cm2·V-1·s-1. The effects of etching gas of Cl2 and SiCl4 were investigated in the gate recess process. SiCl4-etched devices showed higher channel mobility and lower threshold voltage. Atomic force microscope measurement was done to investigate the etching profile with different etching protection mask. Compared with photoresist, SiO2-masked sample showed lower surface roughness and better profile with stepper sidewall and weaker trenching effect resulting in higher channel mobility in the MOSFET.

  16. Interface trap density and mobility extraction in InGaAs buried quantum well metal-oxide-semiconductor field-effect-transistors by gated Hall method

    SciTech Connect

    Chidambaram, Thenappan; Madisetti, Shailesh; Greene, Andrew; Yakimov, Michael; Tokranov, Vadim; Oktyabrsky, Serge; Veksler, Dmitry; Hill, Richard

    2014-03-31

    In this work, we are using a gated Hall method for measurement of free carrier density and electron mobility in buried InGaAs quantum well metal-oxide-semiconductor field-effect-transistor channels. At room temperature, mobility over 8000 cm{sup 2}/Vs is observed at ∼1.4 × 10{sup 12} cm{sup −2}. Temperature dependence of the electron mobility gives the evidence that remote Coulomb scattering dominates at electron density <2 × 10{sup 11} cm{sup −2}. Spectrum of the interface/border traps is quantified from comparison of Hall data with capacitance-voltage measurements or electrostatic modeling. Above the threshold voltage, gate control is strongly limited by fast traps that cannot be distinguished from free channel carriers just by capacitance-based methods and can be the reason for significant overestimation of channel density and underestimation of carrier mobility from transistor measurements.

  17. Amorphous Indium Gallium Zinc Oxide Thin-Film Transistors with a Low-Temperature Polymeric Gate Dielectric on a Flexible Substrate

    NASA Astrophysics Data System (ADS)

    Hyung, Gun Woo; Park, Jaehoon; Wang, Jian-Xun; Lee, Ho Won; Li, Zhao-Hui; Koo, Ja-Ryong; Kwon, Sang Jik; Cho, Eou-Sik; Kim, Woo Young; Kim, Young Kwan

    2013-07-01

    Amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with a solution-processed polymeric gate dielectric of cross-linked poly(4-vinylphenol) (c-PVP) film were fabricated on a poly(ethylene terephthalate) (PET) substrate on which an a-IGZO film, as the active channel layer, was deposited by radio frequency (RF) sputtering. The entire TFT fabrication process was carried out at a temperature below 110 °C. The device exhibited an on/off ratio of 1.5×106 and a high field-effect mobility of 10.2 cm2 V-1 s-1, which is, to our knowledge, the best result ever achieved among a-IGZO TFTs with polymeric gate dielectrics on a plastic substrate.

  18. Reliability and failure modes of implant-supported zirconium-oxide fixed dental prostheses related to veneering techniques

    PubMed Central

    Baldassarri, Marta; Zhang, Yu; Thompson, Van P.; Rekow, Elizabeth D.; Stappert, Christian F. J.

    2011-01-01

    Summary Objectives To compare fatigue failure modes and reliability of hand-veneered and over-pressed implant-supported three-unit zirconium-oxide fixed-dental-prostheses(FDPs). Methods Sixty-four custom-made zirconium-oxide abutments (n=32/group) and thirty-two zirconium-oxide FDP-frameworks were CAD/CAM manufactured. Frameworks were veneered with hand-built up or over-pressed porcelain (n=16/group). Step-stress-accelerated-life-testing (SSALT) was performed in water applying a distributed contact load at the buccal cusp-pontic-area. Post failure examinations were carried out using optical (polarized-reflected-light) and scanning electron microscopy (SEM) to visualize crack propagation and failure modes. Reliability was compared using cumulative-damage step-stress analysis (Alta-7-Pro, Reliasoft). Results Crack propagation was observed in the veneering porcelain during fatigue. The majority of zirconium-oxide FDPs demonstrated porcelain chipping as the dominant failure mode. Nevertheless, fracture of the zirconium-oxide frameworks was also observed. Over-pressed FDPs failed earlier at a mean failure load of 696 ± 149 N relative to hand-veneered at 882 ± 61 N (profile I). Weibull-stress-number of cycles-unreliability-curves were generated. The reliability (2-sided at 90% confidence bounds) for a 400N load at 100K cycles indicated values of 0.84 (0.98-0.24) for the hand-veneered FDPs and 0.50 (0.82-0.09) for their over-pressed counterparts. Conclusions Both zirconium-oxide FDP systems were resistant under accelerated-life-time-testing. Over-pressed specimens were more susceptible to fatigue loading with earlier veneer chipping. PMID:21557985

  19. Theoretical comparison of Si, Ge, and GaAs ultrathin p-type double-gate metal oxide semiconductor transistors

    NASA Astrophysics Data System (ADS)

    Dib, Elias; Bescond, Marc; Cavassilas, Nicolas; Michelini, Fabienne; Raymond, Laurent; Lannoo, Michel

    2013-08-01

    Based on a self-consistent multi-band quantum transport code including hole-phonon scattering, we compare current characteristics of Si, Ge, and GaAs p-type double-gate transistors. Electronic properties are analyzed as a function of (i) transport orientation, (ii) channel material, and (iii) gate length. We first show that ⟨100⟩-oriented devices offer better characteristics than their ⟨110⟩-counterparts independently of the material choice. Our results also point out that the weaker impact of scattering in Ge produces better electrical performances in long devices, while the moderate tunneling effect makes Si more advantageous in ultimately scaled transistors. Moreover, GaAs-based devices are less advantageous for shorter lengths and do not offer a high enough ON current for longer gate lengths. According to our simulations, the performance switching between Si and Ge occurs for a gate length of 12 nm. The conclusions of the study invite then to consider ⟨100⟩-oriented double-gate devices with Si for gate length shorter than 12 nm and Ge otherwise.

  20. Drift region doping effects on characteristics and reliability of high-voltage n-type metal-oxide-semiconductor transistors

    NASA Astrophysics Data System (ADS)

    Chen, Jone F.; Chang, Chun-Po; Liu, Yu Ming; Tsai, Yan-Lin; Hsu, Hao-Tang; Chen, Chih-Yuan; Hwang, Hann-Ping

    2016-01-01

    In this study, off-state breakdown voltage (VBD) and hot-carrier-induced degradation in high-voltage n-type metal-oxide-semiconductor transistors with various BF2 implantation doses in the n- drift region are investigated. Results show that a higher BF2 implantation dose results in a higher VBD but leads to a greater hot-carrier-induced device degradation. Experimental data and technology computer-aided design simulations suggest that the higher VBD is due to the suppression of gate-induced drain current. On the other hand, the greater hot-carrier-induced device degradation can be explained by a lower net donor concentration and a different current-flow path, which is closer to the Si-SiO2 interface.

  1. Effect of electrical stress on Au/Pb (Zr0.52Ti0.48) O3/TiOxNy/Si gate stack for reliability analysis of ferroelectric field effect transistors

    NASA Astrophysics Data System (ADS)

    Khosla, Robin; Sharma, Deepak K.; Mondal, Kunal; Sharma, Satinder K.

    2014-10-01

    Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure with 20 nm thin lead zirconate titanate (PZT) ferroelectric film and 6 nm ultrathin high-κ titanium oxynitride (TiOxNy) insulator layer on p-Si substrate were fabricated. Effect of constant voltage stress (CVS) on electrical characteristics of MFIS structure was investigated to study the reliability of fabricated devices. The experimental results showed trivial variation in memory window (ΔW) from 1.05 to 1 V under CVS of 0 to 15 V (5.76 MV/cm) at sweep voltage of ±5 V. Also, leakage current density (J) reduced from 5.57 to 1.94 μA/cm2 under CVS of 5.76 MV/cm, supported by energy band diagram. It signifies highly reliable TiOxNy buffer layer for Ferroelectric Random Access Memory. After programming at ±5 V, the high (CH) and low (CL) capacitances reliability remains distinguishable for 5000 s even if we extrapolate measured data to 15 years. Microstructures analysis of XRD reveals the formation of (100) and (111) orientation of PZT and TiOxNy, respectively. Thus, Au/PZT/TiOxNy/Si, MFIS gate stacks can be potential candidate for next generation reliable Ferroelectric Field Effect Transistors.

  2. The impact of tunnel oxide nitridation to reliability performance of charge storage non-volatile memory devices.

    PubMed

    Lee, Meng Chuan; Wong, Hin Yong

    2014-02-01

    This paper is written to review the development of critical research on the overall impact of tunnel oxide nitridation (TON) with the aim to mitigate reliability issues due to incessant technology scaling of charge storage NVM devices. For more than 30 years, charge storage non-volatile memory (NVM) has been critical in the evolution of intelligent electronic devices and continuous development of integrated technologies. Technology scaling is the primary strategy implemented throughout the semiconductor industry to increase NVM density and drive down average cost per bit. In this paper, critical reliability challenges and key innovative technical mitigation methods are reviewed. TON is one of the major candidates to replace conventional oxide layer for its superior quality and reliability performance. Major advantages and caveats of key TON process techniques are discussed. The impact of TON on quality and reliability performance of charge storage NVM devices is carefully reviewed with emphasis on major advantages and drawbacks of top and bottom nitridation. Physical mechanisms attributed to charge retention and V(t) instability phenomenon are also reviewed in this paper. PMID:24749438

  3. Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

    NASA Astrophysics Data System (ADS)

    Liu, Hsi-Wen; Chang, Ting-Chang; Tsai, Jyun-Yu; Chen, Ching-En; Liu, Kuan-Ju; Lu, Ying-Hsin; Lin, Chien-Yu; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Ye, Yi-Han

    2016-04-01

    This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

  4. Electric field-induced transport modulation in VO2 FETs with high-k oxide/organic parylene-C hybrid gate dielectric

    NASA Astrophysics Data System (ADS)

    Wei, Tingting; Kanki, Teruo; Fujiwara, Kohei; Chikanari, Masashi; Tanaka, Hidekazu

    2016-02-01

    We report on the observation of reversible and immediate resistance switching by high-k oxide Ta2O5/organic parylene-C hybrid dielectric-gated VO2 thin films. Resistance change ratios at various temperatures in the insulating regime were demonstrated to occur in the vicinity of phase transition temperature. We also found an asymmetric hole-electron carrier modulation related to the suppression of phase transition temperature. The results in this research provide a possibility for clarifying the origin of metal-insulator transition in VO2 through the electrostatic field-induced transport modulation.

  5. Measurement of conduction band deformation potential constants using gate direct tunneling current in n-type metal oxide semiconductor field effect transistors under mechanical stress

    NASA Astrophysics Data System (ADS)

    Lim, Ji-Song; Yang, Xiaodong; Nishida, Toshikazu; Thompson, Scott E.

    2006-08-01

    An experimental method to determine both the hydrostatic and shear deformation potential constants is introduced. The technique is based on the change in the gate tunneling currents of Si-metal oxide semiconductor field effect transistors (MOSFETs) under externally applied mechanical stress and has been applied to industrial n-type MOSFETs. The conduction band hydrostatic and shear deformation potential constants (Ξd and Ξu) are extracted to be 1.0±0.1 and 9.6±1.0eV, respectively, which is consistent with recent theoretical works.

  6. Femtosecond all-optical parallel logic gates based on tunable saturable to reverse saturable absorption in graphene-oxide thin films

    SciTech Connect

    Roy, Sukhdev Yadav, Chandresh

    2013-12-09

    A detailed theoretical analysis of ultrafast transition from saturable absorption (SA) to reverse saturable absorption (RSA) has been presented in graphene-oxide thin films with femtosecond laser pulses at 800 nm. Increase in pulse intensity leads to switching from SA to RSA with increased contrast due to two-photon absorption induced excited-state absorption. Theoretical results are in good agreement with reported experimental results. Interestingly, it is also shown that increase in concentration results in RSA to SA transition. The switching has been optimized to design parallel all-optical femtosecond NOT, AND, OR, XOR, and the universal NAND and NOR logic gates.

  7. Positive bias temperature instability in p-type metal-oxide-semiconductor devices with HfSiON/SiO{sub 2} gate dielectrics

    SciTech Connect

    Samanta, Piyas; Huang, Heng-Sheng; Chen, Shuang-Yuan; Liu, Chuan-Hsi; Cheng, Li-Wei

    2014-02-21

    We present a detailed investigation on positive-bias temperature stress (PBTS) induced degradation of nitrided hafnium silicate (HfSiON)/SiO{sub 2} gate stack in n{sup +}-poly crystalline silicon (polySi) gate p-type metal-oxide-semiconductor (pMOS) devices. The measurement results indicate that gate dielectric degradation is a composite effect of electron trapping in as-fabricated as well as newly generated neutral traps, resulting a significant amount of stress-induced leakage current and generation of surface states at the Si/SiO{sub 2} interface. Although, a significant amount of interface states are created during PBTS, the threshold voltage (V{sub T}) instability of the HfSiON based pMOS devices is primarily caused by electron trapping and detrapping. It is also shown that PBTS creates both acceptor- and donor-like interface traps via different depassivation mechanisms of the Si{sub 3} ≡ SiH bonds at the Si/SiO{sub 2} interface in pMOS devices. However, the number of donor-like interface traps ΔN{sub it}{sup D} is significantly greater than that of acceptor-like interface traps ΔN{sup A}{sub it}, resulting the PBTS induced net interface traps as donor-like.

  8. Gate length and temperature dependence of negative differential transconductance in silicon quantum well metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Naquin, Clint; Lee, Mark; Edwards, Hal; Mathur, Guru; Chatterjee, Tathagata; Maggio, Ken

    2015-09-28

    Introducing quantum transport into silicon transistors in a manner compatible with industrial fabrication has the potential to transform the performance horizons of large scale integrated silicon devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) transistors fabricated using industrial silicon complementary metal-oxide-semiconductor processing. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (V{sub G}) spacing between NDTCs. The V{sub G} spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background.

  9. 20. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    20. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ARM, TRUNNION PIN, PIER AND GATE GAUGE, LOOKING WEST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  10. 17. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    17. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ARMS, PIERS AND DAM BRIDGE, WITH ROLLER GATE HEADHOUSE IN BACKGROUND, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  11. 20. DETAIL VIEW OF SUBMERSIBLE GATE, SHOWING GATE ARMS, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    20. DETAIL VIEW OF SUBMERSIBLE GATE, SHOWING GATE ARMS, GATE PIERS, TRUNNION PIN AND GATE GAUGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  12. 21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ARM, TRUNNION PIN, PIER AND GATE GAUGE, LOOKING EAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  13. Phosphorus and boron diffusion paths in polycrystalline silicon gate of a trench-type three-dimensional metal-oxide-semiconductor field effect transistor investigated by atom probe tomography

    SciTech Connect

    Han, Bin Takamizawa, Hisashi Shimizu, Yasuo; Inoue, Koji; Nagai, Yasuyoshi; Yano, Fumiko; Kunimune, Yorinobu; Inoue, Masao; Nishida, Akio

    2015-07-13

    The dopant (P and B) diffusion path in n- and p-types polycrystalline-Si gates of trench-type three-dimensional (3D) metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated using atom probe tomography, based on the annealing time dependence of the dopant distribution at 900 °C. Remarkable differences were observed between P and B diffusion behavior. In the initial stage of diffusion, P atoms diffuse into deeper regions from the implanted region along grain boundaries in the n-type polycrystalline-Si gate. With longer annealing times, segregation of P on the grain boundaries was observed; however, few P atoms were observed within the large grains or on the gate/gate oxide interface distant from grain boundaries. These results indicate that P atoms diffuse along grain boundaries much faster than through the bulk or along the gate/gate oxide interface. On the other hand, in the p-type polycrystalline-Si gate, segregation of B was observed only at the initial stage of diffusion. After further annealing, the B atoms became uniformly distributed, and no clear segregation of B was observed. Therefore, B atoms diffuse not only along the grain boundary but also through the bulk. Furthermore, B atoms diffused deeper than P atoms along the grain boundaries under the same annealing conditions. This information on the diffusion behavior of P and B is essential for optimizing annealing conditions in order to control the P and B distributions in the polycrystalline-Si gates of trench-type 3D MOSFETs.

  14. Oxidization of squalene, a human skin lipid: a new and reliable marker of environmental pollution studies.

    PubMed

    Pham, D-M; Boussouira, B; Moyal, D; Nguyen, Q L

    2015-08-01

    A review of the oxidization of squalene, a specific human compound produced by the sebaceous gland, is proposed. Such chemical transformation induces important consequences at various levels. Squalene by-products, mostly under peroxidized forms, lead to comedogenesis, contribute to the development of inflammatory acne and possibly modify the skin relief (wrinkling). Experimental conditions of oxidation and/or photo-oxidation mechanisms are exposed, suggesting that they could possibly be bio-markers of atmospheric pollution upon skin. Ozone, long UVA rays, cigarette smoke… are shown powerful oxidizing agents of squalene. Some in vitro, ex vivo and in vivo testings are proposed as examples, aiming at studying ingredients or products capable of boosting or counteracting such chemical changes that, globally, bring adverse effects to various cutaneous compartments. PMID:25656265

  15. Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

    NASA Astrophysics Data System (ADS)

    Tari, Alireza; Lee, Czang-Ho; Wong, William S.

    2015-07-01

    Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO2, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiNx, and (3) a PECVD SiOx/SiNx dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the Vo concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiNx (high Vo) and SiO2 (low Vo) had the highest and lowest conductivity, respectively. A PECVD SiOx/SiNx dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer into the IGZO and resulted in higher resistivity films.

  16. Resonant gate driver with efficient gate energy recovery and switching loss reduction

    NASA Astrophysics Data System (ADS)

    Kim, I.-G.; Kwak, S.-S.

    2016-04-01

    This article describes a novel resonant gate driver for charging the gate capacitor of power metal-oxide semiconductor field-effect-transistors (MOSFETs) that operate at a high switching frequency in power converters. The proposed resonant gate driver is designed with three small MOSFETs to build up the inductor current in addition to an inductor for temporary energy storage. The proposed resonant gate driver recovers the CV2 gate loss, which is the largest loss dissipated in the gate resistance in conventional gate drivers. In addition, the switching loss is reduced at the instants of turn on and turn off in the power MOSFETs of power converters by using the proposed gate driver. Mathematical analyses of the total loss appearing in the gate driver circuit and the switching loss reduction in the power switch of power converters are discussed. Finally, the proposed resonant gate driver is verified with experimental results at a switching frequency of 1 MHz.

  17. Surface cleaning effects on reliability for devices with ultrathin oxides or oxynitrides

    NASA Astrophysics Data System (ADS)

    Lai, Kafai; Hao, Ming-Yin; Chen, Wei-Ming; Lee, Jack C.

    1994-09-01

    A new wafer cleaning procedure has been developed for ultra-thin thermal oxidation process (oxides (48 angstrom) and oxynitrides grown in N2O (42 angstrom) were prepared using this new cleaning and other commonly used cleaning methods to investigate the effects of surface preparation on dielectric integrity. It has been found that this two-dip method produces dielectrics with reduced leakage current and stress-induced leakage current, which are believed to be the critical parameters for ultrathin oxides. Furthermore, this new cleaning procedure improves both intrinsic and defect-related breakdown as well as the uniformity of the current- voltage characteristics across a 4-inch wafer. The methanol/HF dip time has also been optimized. The improvement is believed to be due to enhanced silicon surface passivation by hydrogen, the reduced surface micro-roughness and the absence of native oxide.

  18. Nucleation and growth of atomic layer deposited HfO2 gate dielectric layers on chemical oxide (Si-O-H) and thermal oxide (SiO2 or Si-O-N) underlayers

    NASA Astrophysics Data System (ADS)

    Green, M. L.; Ho, M.-Y.; Busch, B.; Wilk, G. D.; Sorsch, T.; Conard, T.; Brijs, B.; Vandervorst, W.; Räisänen, P. I.; Muller, D.; Bude, M.; Grazul, J.

    2002-12-01

    A study was undertaken to determine the efficacy of various underlayers for the nucleation and growth of atomic layer deposited HfO2 films. These were compared to films grown on hydrogen terminated Si. The use of a chemical oxide underlayer results in almost no barrier to film nucleation, enables linear and predictable growth at constant film density, and the most two-dimensionally continuous HfO2 films. The ease of nucleation is due to the large concentration of OH groups in the hydrous, chemical oxide. HfO2 grows on chemical oxide at a coverage rate of about 14% of a monolayer per cycle, and films are about 90% of the theoretical density of crystalline HfO2. Growth on hydrogen terminated Si is characterized by a large barrier to nucleation and growth, resulting in three-dimensional, rough, and nonlinear growth. Thermal oxide/oxynitride underlayers result in a small nucleation barrier, and nonlinear growth at low HfO2 coverages. The use of chemical oxide underlayers clearly results in the best HfO2 layers. Further, the potential to minimize the chemical oxide thickness provides an important research opportunity for high-κ gate dielectric scaling below 1.0 nm effective oxide thickness.

  19. AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor with Polarized P(VDF-TrFE) Ferroelectric Polymer Gating

    PubMed Central

    Liu, Xinke; Lu, Youming; Yu, Wenjie; Wu, Jing; He, Jiazhu; Tang, Dan; Liu, Zhihong; Somasuntharam, Pannirselvam; Zhu, Deliang; Liu, Wenjun; Cao, Peijiang; Han, Sun; Chen, Shaojun; Seow Tan, Leng

    2015-01-01

    Effect of a polarized P(VDF-TrFE) ferroelectric polymer gating on AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) was investigated. The P(VDF-TrFE) gating in the source/drain access regions of AlGaN/GaN MOS-HEMTs was positively polarized (i.e., partially positively charged hydrogen were aligned to the AlGaN surface) by an applied electric field, resulting in a shift-down of the conduction band at the AlGaN/GaN interface. This increases the 2-dimensional electron gas (2-DEG) density in the source/drain access region of the AlGaN/GaN heterostructure, and thereby reduces the source/drain series resistance. Detailed material characterization of the P(VDF-TrFE) ferroelectric film was also carried out using the atomic force microscopy (AFM), X-ray Diffraction (XRD), and ferroelectric hysteresis loop measurement. PMID:26364872

  20. AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor with Polarized P(VDF-TrFE) Ferroelectric Polymer Gating

    NASA Astrophysics Data System (ADS)

    Liu, Xinke; Lu, Youming; Yu, Wenjie; Wu, Jing; He, Jiazhu; Tang, Dan; Liu, Zhihong; Somasuntharam, Pannirselvam; Zhu, Deliang; Liu, Wenjun; Cao, Peijiang; Han, Sun; Chen, Shaojun; Seow Tan, Leng

    2015-09-01

    Effect of a polarized P(VDF-TrFE) ferroelectric polymer gating on AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) was investigated. The P(VDF-TrFE) gating in the source/drain access regions of AlGaN/GaN MOS-HEMTs was positively polarized (i.e., partially positively charged hydrogen were aligned to the AlGaN surface) by an applied electric field, resulting in a shift-down of the conduction band at the AlGaN/GaN interface. This increases the 2-dimensional electron gas (2-DEG) density in the source/drain access region of the AlGaN/GaN heterostructure, and thereby reduces the source/drain series resistance. Detailed material characterization of the P(VDF-TrFE) ferroelectric film was also carried out using the atomic force microscopy (AFM), X-ray Diffraction (XRD), and ferroelectric hysteresis loop measurement.

  1. Optimization of a Solution-Processed SiO2 Gate Insulator by Plasma Treatment for Zinc Oxide Thin Film Transistors.

    PubMed

    Jeong, Yesul; Pearson, Christopher; Kim, Hyun-Gwan; Park, Man-Young; Kim, Hongdoo; Do, Lee-Mi; Petty, Michael C

    2016-01-27

    We report on the optimization of the plasma treatment conditions for a solution-processed silicon dioxide gate insulator for application in zinc oxide thin film transistors (TFTs). The SiO2 layer was formed by spin coating a perhydropolysilazane (PHPS) precursor. This thin film was subsequently thermally annealed, followed by exposure to an oxygen plasma, to form an insulating (leakage current density of ∼10(-7) A/cm(2)) SiO2 layer. Optimized ZnO TFTs (40 W plasma treatment of the gate insulator for 10 s) possessed a carrier mobility of 3.2 cm(2)/(V s), an on/off ratio of ∼10(7), a threshold voltage of -1.3 V, and a subthreshold swing of 0.2 V/decade. In addition, long-term exposure (150 min) of the pre-annealed PHPS to the oxygen plasma enabled the maximum processing temperature to be reduced from 180 to 150 °C. The resulting ZnO TFT exhibited a carrier mobility of 1.3 cm(2)/(V s) and on/off ratio of ∼10(7). PMID:26704352

  2. Properties of c-axis-aligned crystalline indium-gallium-zinc oxide field-effect transistors fabricated through a tapered-trench gate process

    NASA Astrophysics Data System (ADS)

    Asami, Yoshinobu; Kurata, Motomu; Okazaki, Yutaka; Higa, Eiji; Matsubayashi, Daisuke; Okamoto, Satoru; Sasagawa, Shinya; Moriwaka, Tomoaki; Kakehata, Tetsuya; Yakubo, Yuto; Kato, Kiyoshi; Hamada, Takashi; Sakakura, Masayuki; Hayakawa, Masahiko; Yamazaki, Shunpei

    2016-04-01

    To achieve both low power consumption and high-speed operation, we fabricated c-axis-aligned crystalline indium-gallium-zinc oxide (CAAC-IGZO) field-effect transistors (FETs) with In-rich IGZO and common IGZO (\\text{In}:\\text{Ga}:\\text{Zn} = 1:1:1 in atomic ratio) active layers through a simple process using trench gates, and evaluated their characteristics. The results confirm that 60-nm-node IGZO FETs fabricated through a 450 °C process show an extremely low off-state current below the detection limit (at most 2 × 10-16 A) even at a measurement temperature of 150 °C. The results also reveal that the FETs with the In-rich IGZO active layer show a higher on-state current than those with the common IGZO active layer and have excellent frequency characteristics with a cutoff frequency and a maximum oscillation frequency of up to 20 and 6 GHz, respectively. Thus, we demonstrated that CAAC-IGZO FETs with trench gates are promising for achieving both low power consumption and high-speed operation.

  3. The role of the substrate on the dispersion in accumulation in III-V compound semiconductor based metal-oxide-semiconductor gate stacks

    NASA Astrophysics Data System (ADS)

    Krylov, Igor; Ritter, Dan; Eizenberg, Moshe

    2015-09-01

    Dispersion in accumulation is a widely observed phenomenon in metal-oxide-semiconductor gate stacks based on III-V compound semiconductors. The physical origin of this phenomenon is attributed to border traps located in the dielectric material adjacent to the semiconductor. Here, we study the role of the semiconductor substrate on the electrical quality of the first layers at atomic layer deposited (ALD) dielectrics. For this purpose, either Al2O3 or HfO2 dielectrics with variable thicknesses were deposited simultaneously on two technology important semiconductors—InGaAs and InP. Significantly larger dispersion was observed in InP based gate stacks compared to those based on InGaAs. The observed difference is attributed to a higher border trap density in dielectrics deposited on InP compared to those deposited on InGaAs. We therefore conclude that the substrate plays an important role in the determination of the electrical quality of the first dielectric monolayers deposited by ALD. An additional observation is that larger dispersion was obtained in HfO2 based capacitors compared to Al2O3 based capacitors, deposited on the same semiconductor. This phenomenon is attributed to the lower conduction band offset rather than to a higher border trap density.

  4. Al{sub 2}O{sub 3}/GeO{sub x} gate stack on germanium substrate fabricated by in situ cycling ozone oxidation method

    SciTech Connect

    Yang, Xu; Zeng, Zhen-Hua; Wang, Sheng-Kai E-mail: xzhang62@aliyun.com Sun, Bing; Zhao, Wei; Chang, Hu-Dong; Liu, Honggang E-mail: xzhang62@aliyun.com; Zhang, Xiong E-mail: xzhang62@aliyun.com

    2014-09-01

    Al{sub 2}O{sub 3}/GeO{sub x}/Ge gate stack fabricated by an in situ cycling ozone oxidation (COO) method in the atomic layer deposition (ALD) system at low temperature is systematically investigated. Excellent electrical characteristics such as minimum interface trap density as low as 1.9 × 10{sup 11 }cm{sup −2 }eV{sup −1} have been obtained by COO treatment. The impact of COO treatment against the band alignment of Al{sub 2}O{sub 3} with respect to Ge is studied by x-ray photoelectron spectroscopy (XPS) and spectroscopic ellipsometry (SE). Based on both XPS and SE studies, the origin of gate leakage in the ALD-Al{sub 2}O{sub 3} is attributed to the sub-gap states, which may be correlated to the OH-related groups in Al{sub 2}O{sub 3} network. It is demonstrated that the COO method is effective in repairing the OH-related defects in high-k dielectrics as well as forming superior high-k/Ge interface for high performance Ge MOS devices.

  5. The role of the substrate on the dispersion in accumulation in III-V compound semiconductor based metal-oxide-semiconductor gate stacks

    SciTech Connect

    Krylov, Igor; Ritter, Dan; Eizenberg, Moshe

    2015-09-07

    Dispersion in accumulation is a widely observed phenomenon in metal-oxide-semiconductor gate stacks based on III-V compound semiconductors. The physical origin of this phenomenon is attributed to border traps located in the dielectric material adjacent to the semiconductor. Here, we study the role of the semiconductor substrate on the electrical quality of the first layers at atomic layer deposited (ALD) dielectrics. For this purpose, either Al{sub 2}O{sub 3} or HfO{sub 2} dielectrics with variable thicknesses were deposited simultaneously on two technology important semiconductors—InGaAs and InP. Significantly larger dispersion was observed in InP based gate stacks compared to those based on InGaAs. The observed difference is attributed to a higher border trap density in dielectrics deposited on InP compared to those deposited on InGaAs. We therefore conclude that the substrate plays an important role in the determination of the electrical quality of the first dielectric monolayers deposited by ALD. An additional observation is that larger dispersion was obtained in HfO{sub 2} based capacitors compared to Al{sub 2}O{sub 3} based capacitors, deposited on the same semiconductor. This phenomenon is attributed to the lower conduction band offset rather than to a higher border trap density.

  6. AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor with Polarized P(VDF-TrFE) Ferroelectric Polymer Gating.

    PubMed

    Liu, Xinke; Lu, Youming; Yu, Wenjie; Wu, Jing; He, Jiazhu; Tang, Dan; Liu, Zhihong; Somasuntharam, Pannirselvam; Zhu, Deliang; Liu, Wenjun; Cao, Peijiang; Han, Sun; Chen, Shaojun; Tan, Leng Seow

    2015-01-01

    Effect of a polarized P(VDF-TrFE) ferroelectric polymer gating on AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) was investigated. The P(VDF-TrFE) gating in the source/drain access regions of AlGaN/GaN MOS-HEMTs was positively polarized (i.e., partially positively charged hydrogen were aligned to the AlGaN surface) by an applied electric field, resulting in a shift-down of the conduction band at the AlGaN/GaN interface. This increases the 2-dimensional electron gas (2-DEG) density in the source/drain access region of the AlGaN/GaN heterostructure, and thereby reduces the source/drain series resistance. Detailed material characterization of the P(VDF-TrFE) ferroelectric film was also carried out using the atomic force microscopy (AFM), X-ray Diffraction (XRD), and ferroelectric hysteresis loop measurement. PMID:26364872

  7. Comparison between chemical vapor deposited and physical vapor deposited WSi{sub 2} metal gate for InGaAs n-metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Ong, B. S.; Pey, K. L.; Ong, C. Y.; Tan, C. S.; Antoniadis, D. A.; Fitzgerald, E. A.

    2011-05-02

    We compare chemical vapor deposition (CVD) and physical vapor deposition (PVD) WSi{sub 2} metal gate process for In{sub 0.53}Ga{sub 0.47}As n-metal-oxide-semiconductor field-effect transistors using 10 and 6.5 nm Al{sub 2}O{sub 3} as dielectric layer. The CVD-processed metal gate device with 6.5 nm Al{sub 2}O{sub 3} shows enhanced transistor performance such as drive current, maximum transconductance and maximum effective mobility. These values are relatively better than the PVD-processed counterpart device with improvement of 51.8%, 46.4%, and 47.8%, respectively. The improvement for the performance of the CVD-processed metal gate device is due to the fluorine passivation at the oxide/semiconductor interface and a nondestructive deposition process.

  8. Resistive switching memories based on metal oxides: mechanisms, reliability and scaling

    NASA Astrophysics Data System (ADS)

    Ielmini, Daniele

    2016-06-01

    With the explosive growth of digital data in the era of the Internet of Things (IoT), fast and scalable memory technologies are being researched for data storage and data-driven computation. Among the emerging memories, resistive switching memory (RRAM) raises strong interest due to its high speed, high density as a result of its simple two-terminal structure, and low cost of fabrication. The scaling projection of RRAM, however, requires a detailed understanding of switching mechanisms and there are potential reliability concerns regarding small device sizes. This work provides an overview of the current understanding of bipolar-switching RRAM operation, reliability and scaling. After reviewing the phenomenological and microscopic descriptions of the switching processes, the stability of the low- and high-resistance states will be discussed in terms of conductance fluctuations and evolution in 1D filaments containing only a few atoms. The scaling potential of RRAM will finally be addressed by reviewing the recent breakthroughs in multilevel operation and 3D architecture, making RRAM a strong competitor among future high-density memory solutions.

  9. A novel optical gating method for laser gated imaging

    NASA Astrophysics Data System (ADS)

    Ginat, Ran; Schneider, Ron; Zohar, Eyal; Nesher, Ofer

    2013-06-01

    For the past 15 years, Elbit Systems is developing time-resolved active laser-gated imaging (LGI) systems for various applications. Traditional LGI systems are based on high sensitive gated sensors, synchronized to pulsed laser sources. Elbit propriety multi-pulse per frame method, which is being implemented in LGI systems, improves significantly the imaging quality. A significant characteristic of the LGI is its ability to penetrate a disturbing media, such as rain, haze and some fog types. Current LGI systems are based on image intensifier (II) sensors, limiting the system in spectral response, image quality, reliability and cost. A novel propriety optical gating module was developed in Elbit, untying the dependency of LGI system on II. The optical gating module is not bounded to the radiance wavelength and positioned between the system optics and the sensor. This optical gating method supports the use of conventional solid state sensors. By selecting the appropriate solid state sensor, the new LGI systems can operate at any desired wavelength. In this paper we present the new gating method characteristics, performance and its advantages over the II gating method. The use of the gated imaging systems is described in a variety of applications, including results from latest field experiments.

  10. Modification of electronic properties of top-gated graphene devices by ultrathin yttrium-oxide dielectric layers.

    PubMed

    Wang, Lin; Chen, Xiaolong; Wang, Yang; Wu, Zefei; Li, Wei; Han, Yu; Zhang, Mingwei; He, Yuheng; Zhu, Chao; Fung, Kwok Kwong; Wang, Ning

    2013-02-01

    We report the structure characterization and electronic property modification of single layer graphene (SLG) field-effect transistor (FET) devices top-gated using ultrathin Y(2)O(3) as dielectric layers. Based on the Boltzmann transport theory within variant screening, Coulomb scattering is confirmed quantitatively to be dominant in Y(2)O(3)-covered SLG and a very few short-range impurities have been introduced by Y(2)O(3). Both DC transport and AC capacitance measurements carried out at cryogenic temperatures demonstrate that the broadening of Landau levels is mainly due to the additional charged impurities and inhomogeneity of carriers induced by Y(2)O(3) layers. PMID:23263255

  11. Recent progress in high performance and reliable n-type transition metal oxide-based thin film transistors

    NASA Astrophysics Data System (ADS)

    Kwon, Jang Yeon; Kyeong Jeong, Jae

    2015-02-01

    This review gives an overview of the recent progress in vacuum-based n-type transition metal oxide (TMO) thin film transistors (TFTs). Several excellent review papers regarding metal oxide TFTs in terms of fundamental electron structure, device process and reliability have been published. In particular, the required field-effect mobility of TMO TFTs has been increasing rapidly to meet the demands of the ultra-high-resolution, large panel size and three dimensional visual effects as a megatrend of flat panel displays, such as liquid crystal displays, organic light emitting diodes and flexible displays. In this regard, the effects of the TMO composition on the performance of the resulting oxide TFTs has been reviewed, and classified into binary, ternary and quaternary composition systems. In addition, the new strategic approaches including zinc oxynitride materials, double channel structures, and composite structures have been proposed recently, and were not covered in detail in previous review papers. Special attention is given to the advanced device architecture of TMO TFTs, such as back-channel-etch and self-aligned coplanar structure, which is a key technology because of their advantages including low cost fabrication, high driving speed and unwanted visual artifact-free high quality imaging. The integration process and related issues, such as etching, post treatment, low ohmic contact and Cu interconnection, required for realizing these advanced architectures are also discussed.

  12. Reliability of different blood indices to explore the oxidative stress in response to maximal cycling and static exercises.

    PubMed

    Steinberg, Jean Guillaume; Delliaux, Stéphane; Jammes, Yves

    2006-03-01

    This study compares the changes in four blood markers of exercise-induced oxidative stress in response to exercise protocols commonly used to explore the global muscle performance at work (maximal incremental cycle) and endurance to fatigue of selected muscles (static handgrip and thumb adduction). Cycling and static exercises allow the muscle to work in aerobic and anaerobic conditions, respectively. Healthy adults performed an incremental cycling exercise until volitional exhaustion and, on separated days, executed infra-maximal static thumb adduction and handgrip until exhaustion. Exercise-induced oxidative stress was assessed by the increased plasma concentration of thiobarbituric acid reactive substances (TBARS), the consumption of plasma reduced ascorbic acid (RAA), and erythrocyte reduced glutathione (GSH) antioxidants, and the changes in the total antioxidant status (TAS) of plasma. Five minutes after the end of the incremental cycling exercise, we measured a peak increase in TBARS level, maximal consumption of GSH and RAA, and a modest but significant decrease in TAS concentration. In response to both static thumb adduction and handgrip, significant variations of TBARS, GSH and RAA occurred but we did not measure any significant change in TAS level throughout the 20-min recovery period of both exercise bouts. The present study shows that only the changes in TBARS, GSH and RAA explore both dynamic and static exercises. In addition, TAS measurement does not seem to represent a reliable and unique tool to explore exercise-induced oxidative stress, at least during isometric efforts that allow the muscle to work under anaerobic condition. PMID:16494601

  13. Gate voltage dependent 1/f noise variance model based on physical noise generation mechanisms in n-channel metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Arai, Yukiko; Aoki, Hitoshi; Abe, Fumitaka; Todoroki, Shunichiro; Khatami, Ramin; Kazumi, Masaki; Totsuka, Takuya; Wang, Taifeng; Kobayashi, Haruo

    2015-04-01

    1/f noise is one of the most important characteristics for designing analog/RF circuits including operational amplifiers and oscillators. We have analyzed and developed a novel 1/f noise model in the strong inversion, saturation, and sub-threshold regions based on SPICE2 type model used in any public metal-oxide-semiconductor field-effect transistor (MOSFET) models developed by the University of California, Berkeley. Our model contains two noise generation mechanisms that are mobility and interface trap number fluctuations. Noise variability dependent on gate voltage is also newly implemented in our model. The proposed model has been implemented in BSIM4 model of a SPICE3 compatible circuit simulator. Parameters of the proposed model are extracted with 1/f noise measurements for simulation verifications. The simulation results show excellent agreements between measurement and simulations.

  14. Electron detrapping characteristics in positive bias temperature stressed n-channel metal-oxide-semiconductor field-effect transistors with ultrathin HfSiON gate dielectrics

    NASA Astrophysics Data System (ADS)

    Zhu, Shiyang; Nakajima, Anri

    2007-07-01

    Electrons trapped in the HfSiON gate dielectrics of n-channel metal-oxide-semiconductor field-effect transistors induced by positive bias temperature stress start to decay when the stress is interrupted or an opposite (recovery) voltage is applied. The decay begins with a quick detrapping within tens of nanoseconds followed by a slow detrapping. The quick detrapping depends on the recovery voltage and the trapping history, whereas the slow detrapping obeys approximately a logarithmic dependence on time with an almost identical slope before saturation. The observed detrapping behavior can be explained by a spatial and/or energetic distribution of trapped electrons in the HfSiON film. The device degradation under various dynamic stresses is found to be almost independent of frequency ranging from 0.001to1MHz, while it is slightly enhanced at 10MHz, probably due to insufficient recovery at the recovering half cycle.

  15. Memory characteristics of metal-oxide-semiconductor capacitor with high density cobalt nanodots floating gate and HfO2 blocking dielectric

    NASA Astrophysics Data System (ADS)

    Pei, Yanli; Yin, Chengkuan; Kojima, Toshiya; Nishijima, Masahiko; Fukushima, Takafumi; Tanaka, Tetsu; Koyanagi, Mitsumasa

    2009-07-01

    In this letter, cobalt nanodots (Co-NDs) had been formed via a self-assembled nanodot deposition. High resolution transmission electron microscopy and x-ray photoelectron spectroscopy analyses clearly show that the high metallic Co-ND is crystallized with small size of ˜2 nm and high density of (4-5)×1012/cm2. The metal-oxide-semiconductor device with high density Co-NDs floating gate and high-k HfO2 blocking dielectric exhibits a wide range memory window (0-12 V) due to the charge trapping into and distrapping from Co-NDs. After 10 years retention, a large memory window of ˜1.3 V with a low charge loss of ˜47% was extrapolated. The relative longer data retention demonstrates the advantage of Co-NDs for nonvolatile memory application.

  16. Self-correction of field-effect transistor characteristics in the mode of spontaneous space-charge ion polarization of gate oxide

    SciTech Connect

    Zhdan, A. G.; Naryshkina, V. G.; Chucheva, G. V.

    2009-05-15

    Spontaneous space-charge ion polarization of gate oxide in the inversion n-channel silicon field-effect transistor was accomplished in the mode of its Joule heating by the drain current I{sub d}. The transistor characteristics measured at room temperature (T{sub r}) before and after thermal-field treatment show that positive ion (Na{sup +}) localization near the SiO{sub 2}/Si interface is accompanied by an increase in the effective electron mobility (by a factor of {approx} 2.3), steepness, I{sub d}, and by a small decrease in the threshold voltage ({delta}V{sub th} = 0.58 V). At T = T{sub r}, the modified transistor characteristics are retained for months; they can be easily and predictably varied by changing I{sub d} and heating duration.

  17. Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

    SciTech Connect

    Tari, Alireza Lee, Czang-Ho; Wong, William S.

    2015-07-13

    Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer into the IGZO and resulted in higher resistivity films.

  18. Towards a reliable and high sensitivity O₂-independent glucose sensor based on Ir oxide nanoparticles.

    PubMed

    Campbell, H B; Elzanowska, H; Birss, V I

    2013-04-15

    The primary goal of this work is the development of a rapidly responding, sensitive, and biocompatible Ir oxide (IrOx)-based glucose sensor that regenerates solely via IrOx-mediation in both O₂-free and aerobic environments. An important discovery is that, for films composed of IrOx nanoparticles, Nafion® and glucose oxidase (GOx), a Michaelis-Menten constant (K'(m)) of 20-30 mM is obtained in the case of dual-regeneration (O₂ and IrOx), while K'(m) values are much smaller (3-5 mM) when re-oxidation of GOx occurs only through IrOx-mediation. These smaller K'(m) values indicate that the regeneration of GOx via direct electron transfer to the IrOx nanoparticles is more rapid than to O₂. Small K'(m) values, which are obtained more commonly when Nafion® is not present in the films, are also important for the accurate measurement of low glucose concentrations under hypoglycemic conditions. In this work, the sensing film was also optimized for miniaturization. Depending on the IrOx and GOx surface loadings and the use of sonication before film deposition, the i(max) values ranged from 5 to 225 μA cm⁻², showing very good sensitivity down to 0.4 mM glucose. PMID:23261690

  19. Designing interlayers to improve the mechanical reliability of transparent conductive oxide coatings on flexible substrates

    SciTech Connect

    Kim, Eun-Hye; Yang, Chan-Woo; Park, Jin-Woo

    2012-05-01

    In this study, we investigate the effect of interlayers on the mechanical properties of transparent conductive oxide (TCO) on flexible polymer substrates. Indium tin oxide (ITO), which is the most widely used TCO film, and Ti, which is the most widely used adhesive interlayer, are selected as the coating and the interlayer, respectively. These films are deposited on the polymer substrates using dc-magnetron sputtering to achieve varying thicknesses. The changes in the following critical factors for film cracking and delamination are analyzed: the internal stress ({sigma}{sup i}) induced in the coatings during deposition using a white light interferometer, the crystallinity using a transmission electron microscope, and the surface roughness of ITO caused by the interlayer using an atomic force microscope. The resistances to the cracking and delamination of ITO are evaluated using a fragmentation test. Our tests and analyses reveal the important role of the interlayers, which significantly reduce the compressive {sigma}{sup i} that is induced in the ITO and increase the resistance to the buckling delamination of the ITO. However, the relaxation of {sigma}{sup i} is not beneficial to cracking because there is less compensation for the external tension as {sigma}{sup i} further decreases. Based on these results, the microstructural control is revealed as a more influential factor than {sigma}{sup i} for improving crack resistance.

  20. 18. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    18. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ARMS, PIERS AND DAM BRIDGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  1. 16. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    16. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ARM, TRUNNION PIN AND PIER, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  2. Reliability and degradation of oxide VCSELs due to reaction to atmospheric water vapor

    NASA Astrophysics Data System (ADS)

    Dafinca, Alexandru; Weidberg, Anthony R.; McMahon, Steven J.; Grillo, Alexander A.; Farthouat, Philippe; Ziolkowski, Michael; Herrick, Robert W.

    2013-03-01

    850nm oxide-aperture VCSELs are susceptible to premature failure if operated while exposed to atmospheric water vapor, and not protected by hermetic packaging. The ATLAS detector in CERN's Large Hadron Collider (LHC) has had approximately 6000 channels of Parallel Optic VCSELs fielded under well-documented ambient conditions. Exact time-to-failure data has been collected on this large sample, providing for the first time actual failure data at use conditions. In addition, the same VCSELs were tested under a variety of accelerated conditions to allow us to construct a more accurate acceleration model. Failure analysis information will also be presented to show what we believe causes corrosion-related failure for such VCSELs.

  3. Ceramic bearing development. Silicon nitride bearing balls of improved reliability: Thermal oxidation. Final report, 1 January 1995-31 October 1996

    SciTech Connect

    Burk, C.B.

    1996-11-01

    The major objective of this work was to improve the reliability of silicon nitride bearing balls by means of an optimized thermal oxidation treatment. Previous work had shown that the thermal fracture resistance of silicon nitride bearing balls increased when the balls were heated and oxidized in air. An optimized oxidation treatment for NBD-200 silicon nitride balls was developed, using a thermal proof test matrix. This oxidation treatment increased the thermal fracture resistance of the balls. Ball-on-rod RCF testing of oxidized and non-oxidized balls was performed at 786 KSI contact stress, with nitrided M50-NIL rods. RCF testing did not produce a significant percentage of ball failures for either the oxidized or non-oxidized condition. Alternative methods, such as four ball fatigue testing, should be considered for future work. The oxidation treatment degraded ball surface and geometry, and is suspected as a contributing factor to short rod life. Oxidation treatment does not appear to be a useful technique for improving the reliability of NBD-200 bearing balls.

  4. The reliability and predictive ability of a biomarker of oxidative DNA damage on functional outcomes after stroke rehabilitation.

    PubMed

    Hsieh, Yu-Wei; Lin, Keh-Chung; Korivi, Mallikarjuna; Lee, Tsong-Hai; Wu, Ching-Yi; Wu, Kuen-Yuh

    2014-01-01

    We evaluated the reliability of 8-hydroxy-2'-deoxyguanosine (8-OHdG), and determined its ability to predict functional outcomes in stroke survivors. The rehabilitation effect on 8-OHdG and functional outcomes were also assessed. Sixty-one stroke patients received a 4-week rehabilitation. Urinary 8-OHdG levels were determined by liquid chromatography-tandem mass spectrometry. The test-retest reliability of 8-OHdG was good (interclass correlation coefficient=0.76). Upper-limb motor function and muscle power determined by the Fugl-Meyer Assessment (FMA) and Medical Research Council (MRC) scales before rehabilitation showed significant negative correlation with 8-OHdG (r=-0.38, r=-0.30; p<0.05). After rehabilitation, we found a fair and significant correlation between 8-OHdG and FMA (r=-0.34) and 8-OHdG and pain (r=0.26, p<0.05). Baseline 8-OHdG was significantly correlated with post-treatment FMA, MRC, and pain scores (r=-0.34, -0.31, and 0.25; p<0.05), indicating its ability to predict functional outcomes. 8-OHdG levels were significantly decreased, and functional outcomes were improved after rehabilitation. The exploratory study findings conclude that 8-OHdG is a reliable and promising biomarker of oxidative stress and could be a valid predictor of functional outcomes in patients. Monitoring of behavioral indicators along with biomarkers may have crucial benefits in translational stroke research. PMID:24743892

  5. Retention and Switching Kinetics of Protonated Gate Field Effect Transistors

    SciTech Connect

    DEVINE,R.A.B.; HERRERA,GILBERT V.

    2000-06-27

    The switching and memory retention time has been measured in 50 {micro}m gatelength pseudo-non-volatile memory MOSFETs containing, protonated 40 nm gate oxides. Times of the order of 3.3 seconds are observed for fields of 3 MV cm{sup {minus}1}. The retention time with protons placed either at the gate oxide/substrate or gate oxide/gate electrode interfaces is found to better than 96% after 5,000 seconds. Measurement of the time dependence of the source-drain current during switching provides clear evidence for the presence of dispersive proton transport through the gate oxide.

  6. Retention and switching kinetics of protonated gate field effect transistors

    SciTech Connect

    DEVINE,R.A.B.; HERRERA,GILBERT V.

    2000-05-23

    The switching and memory retention time has been measured in 50 {micro}m gatelength pseudo-non-volatile memory MOSFETS containing, protonated 40 nm gate oxides. Times of the order of 3.3 seconds are observed for fields of 3 MV cm{sup {minus}1}. The retention time with protons placed either at the gate oxide/substrate or gate oxide/gate electrode interfaces is found to better than 96{percent} after 5,000 seconds. Measurement of the time dependence of the source-drain current during switching provides clear evidence for the presence of dispersive proton transport through the gate oxide.

  7. A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under simultaneous negative gate bias and illumination

    SciTech Connect

    Flewitt, A. J.; Powell, M. J.

    2014-04-07

    It has been previously observed that thin film transistors (TFTs) utilizing an amorphous indium gallium zinc oxide (a-IGZO) semiconducting channel suffer from a threshold voltage shift when subjected to a negative gate bias and light illumination simultaneously. In this work, a thermalization energy analysis has been applied to previously published data on negative bias under illumination stress (NBIS) in a-IGZO TFTs. A barrier to defect conversion of 0.65–0.75 eV is extracted, which is consistent with reported energies of oxygen vacancy migration. The attempt-to-escape frequency is extracted to be 10{sup 6}−10{sup 7} s{sup −1}, which suggests a weak localization of carriers in band tail states over a 20–40 nm distance. Models for the NBIS mechanism based on charge trapping are reviewed and a defect pool model is proposed in which two distinct distributions of defect states exist in the a-IGZO band gap: these are associated with states that are formed as neutrally charged and 2+ charged oxygen vacancies at the time of film formation. In this model, threshold voltage shift is not due to a defect creation process, but to a change in the energy distribution of states in the band gap upon defect migration as this allows a state formed as a neutrally charged vacancy to be converted into one formed as a 2+ charged vacancy and vice versa. Carrier localization close to the defect migration site is necessary for the conversion process to take place, and such defect migration sites are associated with conduction and valence band tail states. Under negative gate bias stressing, the conduction band tail is depleted of carriers, but the bias is insufficient to accumulate holes in the valence band tail states, and so no threshold voltage shift results. It is only under illumination that the quasi Fermi level for holes is sufficiently lowered to allow occupation of valence band tail states. The resulting charge localization then allows a negative threshold voltage

  8. Electrical Characteristics of Metal-Oxide-Semiconductor Capacitor with High-κ/Metal Gate Using Oxygen Scavenging Process.

    PubMed

    Lee, Junil; Kim, Jang Hyun; Kwon, Dae Woong; Park, Euyhwan; Park, Taehyung; Kim, Hyun Woo; Park, Byung-gook

    2016-05-01

    It has been widely accepted that the mismatch of lattice constants between HfO2 and Si generates interface traps at the HfO2-Si interface, which causes the degradation of device performances. For better interface quality, very thin SiO2 film (< 2 nm) has been inserted as an interlayer (IL) between HfO2 and Si despite of the increase of EOT. In order to obtain both the better interface quality and the reduction of EOT, we used Ti metal on HfO2/IL SiO2 stack as a scavenging layer to absorb oxygens in the SiO2 and various annealing conditions were applied to optimize the thickness of the SiO2. As a result, we can effectively shrink the EOT from 3.55 nm to 1.15 nm while maintaining the same physical thickness of gate stacks. Furthermore, the diffusion of oxygen was confirmed by high resolution transmission electron microscopy (HRTEM) and time-of-flight secondary ion mass Spectrometry (SIMS). PMID:27483842

  9. Gate dielectric scaling in MOSFETs device

    NASA Astrophysics Data System (ADS)

    Jing, K. Hui; Arshad, M. K. Md.; Huda, A. R. N.; Ruslinda, A. R.; Gopinath, Subash C. B.; M. Nuzaihan M., N.; Ayub, R. M.; Fathil, M. F. M.; Othman, Noraini; Hashim, U.

    2016-07-01

    Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is a basic type of transistor to be used as a switch since 1959. Since then, the successful of MOSFET is due to good properties between silicon and silicon dioxide. The reduction of silicon oxide thickness provide further enhancement in device performance. At 90 and 65 nm technology nodes, the gate oxide could not be scaled anymore due to the direct tunneling effect resulting significant increase of leakage current. At 45 nm the high-k + metal gate has been introduced. Recently, the ferroelectric effect material is introduced which significantly reduce the gate leakage current. This paper review the evolution of gate dielectric scaling from the era of silicon dioxide to high-k + metal gate and ferroelectric effect material.

  10. Prediction of Reliable Metal-PH₃ Bond Energies for Ni, Pd, and Pt in the 0 and +2 Oxidation States

    SciTech Connect

    Craciun, Raluca; Vincent, Andrew J.; Shaughnessy, Kevin H.; Dixon, David A.

    2010-06-21

    Phosphine-based catalysts play an important role in many metal-catalyzed carbon-carbon bond formation reactions yet reliable values of their bond energies are not available. We have been studying homogeneous catalysts consisting of a phosphine bonded to a Pt, Pd, or Ni. High level electronic structure calculations at the CCSD(T)/complete basis set level were used to predict the M-PH₃ bond energy (BE) for the 0 and +2 oxidation states for M=Ni, Pd, and Pt. The calculated bond energies can then be used, for example, in the design of new catalyst systems. A wide range of exchange-correlation functionals were also evaluated to assess the performance of density functional theory (DFT) for these important bond energies. None of the DFT functionals were able to predict all of the M-PH3 bond energies to within 5 kcal/mol, and the best functionals were generalized gradient approximation functionals in contrast to the usual hybrid functionals often employed for main group thermochemistry.

  11. Transparently wrap-gated semiconductor nanowire arrays for studies of gate-controlled photoluminescence

    SciTech Connect

    Nylund, Gustav; Storm, Kristian; Torstensson, Henrik; Wallentin, Jesper; Borgström, Magnus T.; Hessman, Dan; Samuelson, Lars

    2013-12-04

    We present a technique to measure gate-controlled photoluminescence (PL) on arrays of semiconductor nanowire (NW) capacitors using a transparent film of Indium-Tin-Oxide (ITO) wrapping around the nanowires as the gate electrode. By tuning the wrap-gate voltage, it is possible to increase the PL peak intensity of an array of undoped InP NWs by more than an order of magnitude. The fine structure of the PL spectrum reveals three subpeaks whose relative peak intensities change with gate voltage. We interpret this as gate-controlled state-filling of luminescing quantum dot segments formed by zincblende stacking faults in the mainly wurtzite NW crystal structure.

  12. Epitaxial GeSn film formed by solid phase epitaxy and its application to Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor capacitors with sub-nm equivalent oxide thickness

    SciTech Connect

    Lee, Ching-Wei; Wu, Yung-Hsien; Hsieh, Ching-Heng; Lin, Chia-Chun

    2014-11-17

    Through the technique of solid phase epitaxy (SPE), an epitaxial Ge{sub 0.955}Sn{sub 0.045} film was formed on a Ge substrate by depositing an amorphous GeSn film followed by a rapid thermal annealing at 550 °C. A process that uses a SiO{sub 2} capping layer on the amorphous GeSn film during SPE was proposed and it prevents Sn precipitation from occurring while maintaining a smooth surface due to the reduced surface mobility of Sn atoms. The high-quality epitaxial GeSn film was observed to have single crystal structure, uniform thickness and composition, and tiny surface roughness with root mean square of 0.56 nm. With a SnO{sub x}-free surface, Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor (MOS) capacitors with equivalent oxide thickness (EOT) of 0.55 nm were developed. A small amount of traps inside the Yb{sub 2}O{sub 3} was verified by negligible hysteresis in capacitance measurement. Low leakage current of 0.4 A/cm{sup 2} at gate bias of flatband voltage (V{sub FB})-1 V suggests the high quality of the gate dielectric. In addition, the feasibility of using Yb{sub 2}O{sub 3} to well passivate GeSn surface was also evidenced by the small interface trap density (D{sub it}) of 4.02 × 10{sup 11} eV{sup −1} cm{sup −2}, which can be attributed to smooth GeSn surface and Yb{sub 2}O{sub 3} valency passivation. Both leakage current and D{sub it} performance outperform other passivation techniques at sub-nm EOT regime. The proposed epitaxial GeSn film along with Yb{sub 2}O{sub 3} dielectric paves an alternative way to enable high-performance GeSn MOS devices.

  13. Breakdown field enhancement of Si-based MOS capacitor by post-deposition annealing of the reactive sputtered ZrOxNy gate oxide

    NASA Astrophysics Data System (ADS)

    Chew, Chun Chet; Goh, Kian Heng; Gorji, Mohammad Saleh; Tan, Chee Ghuan; Ramesh, S.; Wong, Yew Hoong

    2016-02-01

    Zirconium oxynitride (ZrOxNy) thin films were deposited on silicon (100) substrates by radio frequency-reactive magnetron sputtering in an argon-oxygen-nitrogen atmosphere. Post-deposition annealing (PDA) process was performed in argon ambient at various annealing temperatures (500, 600, 700 and 800 °C) for 15 min. Metal-oxide-semiconductor capacitors were then fabricated with aluminum as the gate electrode. The effects of PDA process on the thin film's structural and electrical properties of the samples were investigated. The structural properties of the deposited films have been evaluated by atomic force microscopy, Fourier transform infrared spectroscopy and Raman spectroscopy. On the other hand, the electrical characterization of the film was conducted by current-voltage analysis. The Raman results revealed that (600-800 °C) annealed samples comprised of crystalline multiphase films (t-ZrO2, fcc-ZrN and bcc γ-Zr2ON2). Interfacial layer consisted of Zr-Si-O, Si-O-N and Si-O phase was formed for all investigated samples, and interfacial layer growth was suppressed when annealed at lower temperatures (500 °C). Electrical result revealed that the sample annealed at a relatively low temperature of 500 °C has demonstrated the highest breakdown field which was attributed to the low surface roughness, the low interface trap and the highly amorphous multiphase film.

  14. Self-aligned top-gate amorphous indium zinc oxide thin-film transistors exceeding low-temperature poly-Si transistor performance.

    PubMed

    Park, Jae Chul; Lee, Ho-Nyeon; Im, Seongil

    2013-08-14

    Thin-film transistor (TFT) is a key component of active-matrix flat-panel displays (AMFPDs). These days, the low-temperature poly silicon (LTPS) TFTs are to match with advanced AMFPDs such as the active matrix organic light-emitting diode (AMOLED) display, because of their high mobility for fast pixel switching. However, the manufacturing process of LTPS TFT is quite complicated, costly, and scale-limited. Amorphous oxide semiconductor (AOS) TFT technology is another candidate, which is as simple as that of conventioanl amorphous (a)-Si TFTs in fabrication but provides much superior device performances to those of a-Si TFTs. Hence, various AOSs have been compared with LTPS for active channel layer of the advanced TFTs, but have always been found to be relatively inferior to LTPS. In the present work, we clear the persistent inferiority, innovating the device performaces of a-IZO TFT by adopting a self-aligned coplanar top-gate structure and modifying the surface of a-IZO material. Herein, we demonstrate a high-performance simple-processed a-IZO TFT with mobility of ∼157 cm(2) V(-1) s(-1), SS of ∼190 mV dec(-1), and good bias/photostabilities, which overall surpass the performances of high-cost LTPS TFTs. PMID:23823486

  15. On the applicability of probabilistic analyses to assess the structural reliability of materials and components for solid-oxide fuel cells

    SciTech Connect

    Lara-Curzio, Edgar; Radovic, Miladin; Luttrell, Claire R

    2016-01-01

    The applicability of probabilistic analyses to assess the structural reliability of materials and components for solid-oxide fuel cells (SOFC) is investigated by measuring the failure rate of Ni-YSZ when subjected to a temperature gradient and comparing it with that predicted using the Ceramics Analysis and Reliability Evaluation of Structures (CARES) code. The use of a temperature gradient to induce stresses was chosen because temperature gradients resulting from gas flow patterns generate stresses during SOFC operation that are the likely to control the structural reliability of cell components The magnitude of the predicted failure rate was found to be comparable to that determined experimentally, which suggests that such probabilistic analyses are appropriate for predicting the structural reliability of materials and components for SOFCs. Considerations for performing more comprehensive studies are discussed.

  16. Multiple-stimuli responsive bioelectrocatalysis based on reduced graphene oxide/poly(N-isopropylacrylamide) composite films and its application in the fabrication of logic gates.

    PubMed

    Wang, Lei; Lian, Wenjing; Yao, Huiqin; Liu, Hongyun

    2015-03-11

    In the present work, reduced graphene oxide (rGO)/poly(N-isopropylacrylamide) (PNIPAA) composite films were electrodeposited onto the surface of Au electrodes in a fast and one-step manner from an aqueous mixture of a graphene oxide (GO) dispersion and N-isopropylacrylamide (NIPAA) monomer solutions. Reflection-absorption infrared (IR) and Raman spectroscopies were employed to characterize the successful construction of the rGO/PNIPAA composite films. The rGO/PNIPAA composite films exhibited reversible potential-, pH-, temperature-, and sulfate-sensitive cyclic voltammetric (CV) on-off behavior to the electroactive probe ferrocenedicarboxylic acid (Fc(COOH)2). For instance, after the composite films were treated at -0.7 V for 7 min, the CV responses of Fc(COOH)2 at the rGO/PNIPAA electrodes were quite large at pH 8.0, exhibiting the on state. However, after the films were treated at 0 V for 30 min, the CV peak currents became much smaller, demonstrating the off state. The mechanism of the multiple-stimuli switchable behaviors for the system was investigated not only by electrochemical methods but also by scanning electron microscopy and X-ray photoelectron spectroscopy. The potential-responsive behavior for this system was mainly attributed to the transformation between rGO and GO in the films at different potentials. The film system was further used to realize multiple-stimuli responsive bioelectrocatalysis of glucose catalyzed by the enzyme of glucose oxidase and mediated by the electroactive probe of Fc(COOH)2 in solution. On the basis of this, a four-input enabled OR (EnOR) logic gate network was established. PMID:25686462

  17. Configurable NOR gate arrays from Belousov-Zhabotinsky micro-droplets

    NASA Astrophysics Data System (ADS)

    Wang, A. L.; Gold, J. M.; Tompkins, N.; Heymann, M.; Harrington, K. I.; Fraden, S.

    2016-02-01

    We investigate the Belousov-Zhabotinsky (BZ) reaction in an attempt to establish a basis for computation using chemical oscillators coupled via inhibition. The system consists of BZ droplets suspended in oil. Interdrop coupling is governed by the non-polar communicator of inhibition, Br2. We consider a linear arrangement of three droplets to be a NOR gate, where the center droplet is the output and the other two are inputs. Oxidation spikes in the inputs, which we define to be TRUE, cause a delay in the next spike of the output, which we read to be FALSE. Conversely, when the inputs do not spike (FALSE) there is no delay in the output (TRUE), thus producing the behavior of a NOR gate. We are able to reliably produce NOR gates with this behavior in microfluidic experiment.

  18. Configurable NOR gate arrays from Belousov-Zhabotinsky micro-droplets

    PubMed Central

    Wang, A.L.; Gold, J.M.; Tompkins, N.; Heymann, M.; Harrington, K.I.; Fraden, S.

    2016-01-01

    We investigate the Belousov–Zhabotinsky (BZ) reaction in an attempt to establish a basis for computation using chemical oscillators coupled via inhibition. The system consists of BZ droplets suspended in oil. Interdrop coupling is governed by the non-polar communicator of inhibition, Br2. We consider a linear arrangement of three droplets to be a NOR gate, where the center droplet is the output and the other two are inputs. Oxidation spikes in the inputs, which we define to be TRUE, cause a delay in the next spike of the output, which we read to be FALSE. Conversely, when the inputs do not spike (FALSE) there is no delay in the output (TRUE), thus producing the behavior of a NOR gate. We are able to reliably produce NOR gates with this behavior in microfluidic experiment. PMID:27168916

  19. Materials reliability issues in microelectronics

    SciTech Connect

    Lloyd, J.R. ); Yost, F.G. ); Ho, P.S. )

    1991-01-01

    This book covers the proceedings of a MRS symposium on materials reliability in microelectronics. Topics include: electromigration; stress effects on reliability; stress and packaging; metallization; device, oxide and dielectric reliability; new investigative techniques; and corrosion.

  20. Effect of Oxidation Temperature on Physical and Electrical Properties of Sm2O3 Thin-Film Gate Oxide on Si Substrate

    NASA Astrophysics Data System (ADS)

    Goh, Kian Heng; Haseeb, A. S. M. A.; Wong, Yew Hoong

    2016-06-01

    Thermal oxidation of 150-nm sputtered pure samarium metal film on silicon substrate has been carried out in oxygen ambient at various temperatures (600°C to 900°C) for 15 min and the effect of the oxidation temperature on the structural, chemical, and electrical properties of the resulting Sm2O3 layers investigated. The crystallinity of the Sm2O3 films and the existence of an interfacial layer were evaluated by x-ray diffraction (XRD) analysis, Fourier-transform infrared (FTIR) spectroscopy, and Raman analysis. The crystallite size and microstrain of Sm2O3 were estimated by Williamson-Hall (W-H) plot analysis, with comparison of the former with the crystallite size of Sm2O3 as calculated using the Scherrer equation. High-resolution transmission electron microscopy (HRTEM) with energy-dispersive x-ray (EDX) spectroscopy analysis was carried out to investigate the cross-sectional morphology and chemical distribution of selected regions. The activation energy or growth rate of each stacked layer was calculated from Arrhenius plots. The surface roughness and topography of the Sm2O3 layers were examined by atomic force microscopy (AFM) analysis. A physical model based on semipolycrystalline nature of the interfacial layer is suggested and explained. Results supporting such a model were obtained by FTIR, XRD, Raman, EDX, and HRTEM analyses. Electrical characterization revealed that oxidation temperature at 700°C yielded the highest breakdown voltage, lowest leakage current density, and highest barrier height value.

  1. FLOW GATING

    DOEpatents

    Poppelbaum, W.J.

    1962-12-01

    BS>This invention is a fast gating system for eiectronic flipflop circuits. Diodes connect the output of one circuit to the input of another, and the voltage supply for the receiving flip-flop has two alternate levels. When the supply is at its upper level, no current can flow through the diodes, but when the supply is at its lower level, current can flow to set the receiving flip- flop to the same state as that of the circuit to which it is connected. (AEC)

  2. Atomic Layer Deposition of Zirconium-Based High-k Metal Gate Oxide: Effect of Si Containing Zr Precursor.

    PubMed

    Cho, Jun Hee; Lee, Sang-Ick; Kim, Jong Hyun; Yim, Sang Jun; Shin, Hyung Soo; Han, Mi Jeong; Chae, Won Mook; Lee, Sung Duck; Ahn, Chi Young; Kim, Myong-Woon

    2015-01-01

    Zirconium based thin film have been deposited by atomic layer deposition (ALD) process using Zr and Si containing Zr precursor with ozone as oxidant. We have pursued a means to control composition by varying Zr and Si containing precursor by cycle frequency. The molar ratio of Si to Zr in the Zr based films was 0.2, 0.25, 0.33, and 0.5. Addition of Si containing Zr precursor on Zirconium based thin films was effective for the decrease of the roughness, while an increase of density. XPS analysis indicated that the addition of Si containing Zr precursors in the Zr based film formed the silicate structure. The XRD analysis of the all ZrO2-SiO2 mixed films annealed at 600 degrees C for 5 min indicated the presence of amorphous. However, the ZrO2 film showed diffraction peaks at 2θ = 30.6 degrees due to the presence of the Tetragonal ZrO2. The incorporation of Si into ZrO2 films helps stabilize an amorphous structure during deposition and annealing. The Zr based thin film (Si/Zr = 0.25) exhibited that the leakage current density was 6.2 x 10(-7) A/cm2 at a bias of - 1.5 V. PMID:26328365

  3. Evolution of the gate current in 32 nm MOSFETs under irradiation

    NASA Astrophysics Data System (ADS)

    Palumbo, F.; Debray, M.; Vega, N.; Quinteros, C.; Kalstein, A.; Guarin, F.

    2016-05-01

    Radiation induced currents on single 32 nm MOSFET transistors have been studied using consecutive runs of 16O at 25 MeV. The main feature is the generation of current peaks - in the gate and channel currents - due to the collection of the electro-hole pairs generated by the incident radiation runs. It has been observed that the incident ions cause damage in the dielectric layer and in the substrate affecting the collection of carriers, and hence the radiation-induced current peaks. It has been find out a decrease of the current peak due to the increase of the series resistance by non-ionizing energy loss in the semiconductor substrate, and an increase of the leakage current due to defects in the gate oxide by ionizing energy loss. For low levels of damage in the gate oxide, the main feature is the shift of the VTH. Hot carriers heated by the incident radiation in the depletion region and injected in the gate oxide cause the change of the VTH due to electron or hole trapping for n- or p-channel respectively. The overall results illustrate that these effects must be taken into consideration for an accurate reliability projection.

  4. Sliding-gate valve for use with abrasive materials

    DOEpatents

    Ayers, Jr., William J.; Carter, Charles R.; Griffith, Richard A.; Loomis, Richard B.; Notestein, John E.

    1985-01-01

    The invention is a flow and pressure-sealing valve for use with abrasive solids. The valve embodies special features which provide for long, reliable operating lifetimes in solids-handling service. The valve includes upper and lower transversely slidable gates, contained in separate chambers. The upper gate provides a solids-flow control function, whereas the lower gate provides a pressure-sealing function. The lower gate is supported by means for (a) lifting that gate into sealing engagement with its seat when the gate is in its open and closed positions and (b) lowering the gate out of contact with its seat to permit abrasion-free transit of the gate between its open and closed positions. When closed, the upper gate isolates the lower gate from the solids. Because of this shielding action, the sealing surface of the lower gate is not exposed to solids during transit or when it is being lifted or lowered. The chamber containing the lower gate normally is pressurized slightly, and a sweep gas is directed inwardly across the lower-gate sealing surface during the vertical translation of the gate.

  5. Investigation of trap properties in high-k/metal gate p-type metal-oxide-semiconductor field-effect-transistors with aluminum ion implantation using random telegraph noise analysis

    SciTech Connect

    Kao, Tsung-Hsien; Chang, Shoou-Jinn Fang, Yean-Kuen; Huang, Po-Chin; Wu, Chung-Yi; Wu, San-Lein

    2014-08-11

    In this study, the impact of aluminum ion implantation (Al I/I) on random telegraph noise (RTN) in high-k/metal gate (HK/MG) p-type metal-oxide-semiconductor field-effect-transistors (pMOSFETs) was investigated. The trap parameters of HK/MG pMOSFETs with Al I/I, such as trap energy level, capture time and emission time, activation energies for capture and emission, and trap location in the gate dielectric, were determined. The configuration coordinate diagram was also established. It was observed that the implanted Al could fill defects and form a thin Al{sub 2}O{sub 3} layer and thus increase the tunneling barrier height for holes. It was also observed that the trap position in the Al I/I samples was lower due to the Al I/I-induced dipole at the HfO{sub 2}/SiO{sub 2} interface.

  6. Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

    SciTech Connect

    Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Ho, Szu-Han; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Lu, Ching-Sen

    2014-10-06

    This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO{sub 2} interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

  7. Gate stack engineering for GaN lateral power transistors

    NASA Astrophysics Data System (ADS)

    Yang, Shu; Liu, Shenghou; Liu, Cheng; Hua, Mengyuan; Chen, Kevin J.

    2016-02-01

    Developing optimal gate-stack technology is a key to enhancing the reliability and performance of GaN insulated-gate devices for high-voltage power switching applications. In this paper, we discuss current challenges and review our recent progresses in gate-stack technology development toward high-performance and high-reliability GaN power devices, including (1) interface engineering that creates a high-quality dielectric/III-nitride interface with low trap density; (2) barrier-layer engineering that enables optimal trade-off between performance and stability; (3) bulk quality and reliability enhancement of the gate dielectric. These gate-stack techniques in terms of new process development and device structure design are valuable to realize highly reliable and competitive GaN power devices.

  8. Electrical properties of GaAs metal-oxide-semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal-organic vapor deposition/atomic layer deposition hybrid system

    NASA Astrophysics Data System (ADS)

    Aoki, Takeshi; Fukuhara, Noboru; Osada, Takenori; Sazawa, Hiroyuki; Hata, Masahiko; Inoue, Takayuki

    2015-08-01

    This paper presents a compressive study on the fabrication and optimization of GaAs metal-oxide-semiconductor (MOS) structures comprising a Al2O3 gate oxide, deposited via atomic layer deposition (ALD), with an AlN interfacial passivation layer prepared in situ via metal-organic chemical vapor deposition (MOCVD). The established protocol afforded self-limiting growth of Al2O3 in the atmospheric MOCVD reactor. Consequently, this enabled successive growth of MOCVD-formed AlN and ALD-formed Al2O3 layers on the GaAs substrate. The effects of AlN thickness, post-deposition anneal (PDA) conditions, and crystal orientation of the GaAs substrate on the electrical properties of the resulting MOS capacitors were investigated. Thin AlN passivation layers afforded incorporation of optimum amounts of nitrogen, leading to good capacitance-voltage (C-V) characteristics with reduced frequency dispersion. In contrast, excessively thick AlN passivation layers degraded the interface, thereby increasing the interfacial density of states (Dit) near the midgap and reducing the conduction band offset. To further improve the interface with the thin AlN passivation layers, the PDA conditions were optimized. Using wet nitrogen at 600 °C was effective to reduce Dit to below 2 × 1012 cm-2 eV-1. Using a (111)A substrate was also effective in reducing the frequency dispersion of accumulation capacitance, thus suggesting the suppression of traps in GaAs located near the dielectric/GaAs interface. The current findings suggest that using an atmosphere ALD process with in situ AlN passivation using the current MOCVD system could be an efficient solution to improving GaAs MOS interfaces.

  9. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 49 Transportation 4 2011-10-01 2011-10-01 false Gate arm and gate mechanism. 234.255 Section 234... Maintenance, Inspection, and Testing Inspections and Tests § 234.255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall...

  10. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... 49 Transportation 4 2013-10-01 2013-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month....

  11. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 49 Transportation 4 2014-10-01 2014-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month....

  12. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Gate arm and gate mechanism. 234.255 Section 234... Maintenance, Inspection, and Testing Inspections and Tests § 234.255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall...

  13. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 49 Transportation 4 2012-10-01 2012-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month....

  14. Nitric oxide inhibits neuroendocrine CaV1 L-channel gating via cGMP-dependent protein kinase in cell-attached patches of bovine chromaffin cells

    PubMed Central

    Carabelli, Valentina; D'Ascenzo, Marcello; Carbone, Emilio; Grassi, Claudio

    2002-01-01

    Nitric oxide (NO) regulates the release of catecholamines from the adrenal medulla but the molecular targets of its action are not yet well identified. Here we show that the NO donor sodium nitroprusside (SNP, 200 μM) causes a marked depression of the single CaV1 L-channel activity in cell-attached patches of bovine chromaffin cells. SNP action was complete within 3-5 min of cell superfusion. In multichannel patches the open probability (NPo) decreased by ∼60 % between 0 and +20 mV. Averaged currents over a number of traces were proportionally reduced and showed no drastic changes to their time course. In single-channel patches the open probability (Po) at +10 mV decreased by the same amount as that of multichannel patches (∼61 %). Such a reduction was mainly associated with an increased probability of null sweeps and a prolongation of mean shut times, while first latency, mean open time and single-channel conductance were not significantly affected. Addition of the NO scavenger carboxy-PTIO or cell treatment with the guanylate cyclase inhibitor ODQ prevented the SNP-induced inhibition. 8-Bromo-cyclicGMP (8-Br-cGMP; 400 μM) mimicked the action of the NO donor and the protein kinase G blocker KT-5823 prevented this effect. The depressive action of SNP was preserved after blocking the cAMP-dependent up-regulatory pathway with the protein kinase A inhibitor H89. Similarly, the inhibitory action of 8-Br-cGMP proceeded regardless of the elevation of cAMP levels, suggesting that cGMP/PKG and cAMP/PKA act independently on L-channel gating. The inhibitory action of 8-Br-cGMP was also independent of the G protein-induced inhibition of L-channels mediated by purinergic and opiodergic autoreceptors. Since Ca2+ channels contribute critically to both the local production of NO and catecholamine release, the NO/PKG-mediated inhibition of neuroendocrine L-channels described here may represent an important autocrine signalling mechanism for controlling the rate of

  15. Nitric oxide inhibits neuroendocrine Ca(V)1 L-channel gating via cGMP-dependent protein kinase in cell-attached patches of bovine chromaffin cells.

    PubMed

    Carabelli, Valentina; D'Ascenzo, Marcello; Carbone, Emilio; Grassi, Claudio

    2002-06-01

    Nitric oxide (NO) regulates the release of catecholamines from the adrenal medulla but the molecular targets of its action are not yet well identified. Here we show that the NO donor sodium nitroprusside (SNP, 200 microM) causes a marked depression of the single Ca(V)1 L-channel activity in cell-attached patches of bovine chromaffin cells. SNP action was complete within 3-5 min of cell superfusion. In multichannel patches the open probability (NP(o)) decreased by approximately 60 % between 0 and +20 mV. Averaged currents over a number of traces were proportionally reduced and showed no drastic changes to their time course. In single-channel patches the open probability (P(o)) at +10 mV decreased by the same amount as that of multichannel patches (approximately 61 %). Such a reduction was mainly associated with an increased probability of null sweeps and a prolongation of mean shut times, while first latency, mean open time and single-channel conductance were not significantly affected. Addition of the NO scavenger carboxy-PTIO or cell treatment with the guanylate cyclase inhibitor ODQ prevented the SNP-induced inhibition. 8-Bromo-cyclicGMP (8-Br-cGMP; 400 microM) mimicked the action of the NO donor and the protein kinase G blocker KT-5823 prevented this effect. The depressive action of SNP was preserved after blocking the cAMP-dependent up-regulatory pathway with the protein kinase A inhibitor H89. Similarly, the inhibitory action of 8-Br-cGMP proceeded regardless of the elevation of cAMP levels, suggesting that cGMP/PKG and cAMP/PKA act independently on L-channel gating. The inhibitory action of 8-Br-cGMP was also independent of the G protein-induced inhibition of L-channels mediated by purinergic and opiodergic autoreceptors. Since Ca(2+) channels contribute critically to both the local production of NO and catecholamine release, the NO/PKG-mediated inhibition of neuroendocrine L-channels described here may represent an important autocrine signalling mechanism

  16. Using a floating-gate MOS transistor as a transducer in a MEMS gas sensing system.

    PubMed

    Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M; Avila-García, Alejandro; Vazquez-Acosta, E N; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

    2010-01-01

    Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe(2)O(3) layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

  17. Oxide Charge Engineering of Atomic Layer Deposited AlOxNy/Al2O3 Gate Dielectrics: A Path to Enhancement Mode GaN Devices.

    PubMed

    Negara, M A; Kitano, M; Long, R D; McIntyre, P C

    2016-08-17

    Nitrogen incorporation to produce negative fixed charge in Al2O3 gate insulator layers is investigated as a path to achieve enhancement mode GaN device operation. A uniform distribution of nitrogen across the resulting AlOxNy films is obtained using N2 plasma enhanced atomic layer deposition (ALD). The flat band voltage (Vfb) increases to a significantly more positive value with increasing nitrogen concentration. Insertion of a 2 nm thick Al2O3 interlayer greatly decreases the trap density of the insulator/GaN interface, and reduces the voltage hysteresis and frequency dispersion of gate capacitance compared to single-layer AlOxNy gate insulators in GaN MOSCAPs. PMID:27459343

  18. Gating of Permanent Molds for ALuminum Casting

    SciTech Connect

    David Schwam; John F. Wallace; Tom Engle; Qingming Chang

    2004-03-30

    This report summarizes a two-year project, DE-FC07-01ID13983 that concerns the gating of aluminum castings in permanent molds. The main goal of the project is to improve the quality of aluminum castings produced in permanent molds. The approach taken was determine how the vertical type gating systems used for permanent mold castings can be designed to fill the mold cavity with a minimum of damage to the quality of the resulting casting. It is evident that somewhat different systems are preferred for different shapes and sizes of aluminum castings. The main problems caused by improper gating are entrained aluminum oxide films and entrapped gas. The project highlights the characteristic features of gating systems used in permanent mold aluminum foundries and recommends gating procedures designed to avoid common defects. The study also provides direct evidence on the filling pattern and heat flow behavior in permanent mold castings.

  19. Gate-Leakage and Carrier-Transport Mechanisms for Plasma-PH3 Passivated InGaAs N-Channel Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Azzah Bte Suleiman, Sumarlina; Lee, Sungjoo

    2012-02-01

    Gate leakage mechanism of the HfAlO plasma-PH3 passivated and non-passivated In0.53Ga0.47As N-channel metal-oxide-semiconductor field-effect transistors (N-MOSFETs) have been evaluated, in order to correlate the quality of the oxide deposited with the gate leakage mechanisms observed. At temperatures higher than 300 K, trap-free space charge limited conduction (SCLC) mechanism dominates the gate leakage of passivated device but non-passivated device consists of exponentially distributed SCLC mechanism at low electric field and Frenkel-Poole emission at high electric field. This Frenkel-Poole emission is associated with energy trap levels of ˜0.95 to 1.3 eV and is responsible for the increased gate leakage of non-passivated device. In addition, the electrical properties of the non-passivated device has also been extracted from the SCLC mechanism, with the average trap concentration of the shallow traps given as 1.3×1019 cm-3 and the average activation energy given as ˜0.22 to 0.27 eV. The existence of these defect levels in non-passivated device can be attributed to the interdiffusion of Ga/As/O elements across the HfAlO/In0.53Ga0.47As interface. On the other hand, passivated device does not contain Frenkel-Poole emission nor exponentially distributed SCLC mechanism, indicating a reduction in traps in the bulk of the oxide. In addition, the temperature dependent characteristics of off-state leakage have also been evaluated to provide insight into the off-state mechanism. The off-state leakage of both passivated and non-passivated device is determined by junction leakage, with Shockley-Read-Hall mechanism being its main contributor, and has activation energy of 0.38 eV for passivated device and 0.4 eV for non-passivated device. From Id∝T-0.37 observed for passivated device, in comparison to Id∝T-0.18 for non-passivated device, we have further confirmed the phonon scattering dominance of the passivated device at high electric field.

  20. Gate-Leakage and Carrier-Transport Mechanisms for Plasma-PH3 Passivated InGaAs N-Channel Metal--Oxide--Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Suleiman, Sumarlina Azzah Bte; Lee, Sungjoo

    2012-02-01

    Gate leakage mechanism of the HfAlO plasma-PH3 passivated and non-passivated In0.53Ga0.47As N-channel metal--oxide--semiconductor field-effect transistors (N-MOSFETs) have been evaluated, in order to correlate the quality of the oxide deposited with the gate leakage mechanisms observed. At temperatures higher than 300 K, trap-free space charge limited conduction (SCLC) mechanism dominates the gate leakage of passivated device but non-passivated device consists of exponentially distributed SCLC mechanism at low electric field and Frenkel--Poole emission at high electric field. This Frenkel--Poole emission is associated with energy trap levels of ˜0.95 to 1.3 eV and is responsible for the increased gate leakage of non-passivated device. In addition, the electrical properties of the non-passivated device has also been extracted from the SCLC mechanism, with the average trap concentration of the shallow traps given as 1.3× 1019 cm-3 and the average activation energy given as ˜0.22 to 0.27 eV. The existence of these defect levels in non-passivated device can be attributed to the interdiffusion of Ga/As/O elements across the HfAlO/In0.53Ga0.47As interface. On the other hand, passivated device does not contain Frenkel--Poole emission nor exponentially distributed SCLC mechanism, indicating a reduction in traps in the bulk of the oxide. In addition, the temperature dependent characteristics of off-state leakage have also been evaluated to provide insight into the off-state mechanism. The off-state leakage of both passivated and non-passivated device is determined by junction leakage, with Shockley--Read--Hall mechanism being its main contributor, and has activation energy of 0.38 eV for passivated device and 0.4 eV for non-passivated device. From Id\\propto T-0.37 observed for passivated device, in comparison to Id\\propto T-0.18 for non-passivated device, we have further confirmed the phonon scattering dominance of the passivated device at high electric field.

  1. Ferroelectric/Dielectric Double Gate Insulator Spin-Coated Using Barium Titanate Nanocrystals for an Indium Oxide Nanocrystal-Based Thin-Film Transistor.

    PubMed

    Pham, Hien Thu; Yang, Jin Ho; Lee, Don-Sung; Lee, Byoung Hun; Jeong, Hyun-Dam

    2016-03-23

    Barium titanate nanocrystals (BT NCs) were prepared under solvothermal conditions at 200 °C for 24 h. The shape of the BT NCs was tuned from nanodot to nanocube upon changing the polarity of the alcohol solvent, varying the nanosize in the range of 14-22 nm. Oleic acid-passivated NCs showed good solubility in a nonpolar solvent. The effect of size and shape of the BT NCs on the ferroelectric properties was also studied. The maximum polarization value of 7.2 μC/cm(2) was obtained for the BT-5 NC thin film. Dielectric measurements of the films showed comparable dielectric constant values of BT NCs over 1-100 kHz without significant loss. Furthermore, the bottom gate In2O3 NC thin film transistors exhibited outstanding device performance with a field-effect mobility of 11.1 cm(2) V(-1) s(-1) at a low applied gate voltage with BT-5 NC/SiO2 as the gate dielectric. The low-density trapped state was observed at the interface between the In2O3 NC semiconductor and the BT-5 NCs/SiO2 dielectric film. Furthermore, compensation of the applied gate field by an electric dipole-induced dipole field within the BT-5 NC film was also observed. PMID:26927618

  2. Influence of uniaxial strain in Si and Ge p-type double-gate metal-oxide-semiconductor field effect transistors

    NASA Astrophysics Data System (ADS)

    Moussavou, Manel; Cavassilas, Nicolas; Dib, Elias; Bescond, Marc

    2015-09-01

    We theoretically investigate the impact of uniaxial strain in extremely thin Si and Ge p-type double-gate transistors. Quantum transport modeling is treated using a 6-band k.p Hamiltonian and the non-equilibrium Green's function formalism including phonon scattering. Based on this framework, we analyze the influence of strain on current characteristics considering different transport directions and gate lengths. Our results first confirm the superiority of Ge over Si in long devices (15 nm gate length) for which best electrical performances are obtained considering channels along <110 > with a uni-axial compressive strain. For this configuration, Si devices suffer from inter-subband coupling which generates a strong hole-phonon scattering. Material dominance is reversed for shorter devices (7 nm gate length) where the small effective masses of Ge deteriorate the off-regime of the nano-transistor regardless of strain and crystallographic options. Due to weaker hole-phonon-scattering, <100 > -Si devices with a tensile strain are interestingly found to be more competitive than their <110 > -compressive counterparts. These results show that Si is still the most relevant material to reach the ultimate nanometer scale. More importantly, the same tensile strain can be considered to boost performances of both p- and n-type planar transistors which would lead to a significant simplification of the technological strain manufacturing.

  3. Galvanic effects in Si-based microelectromechanical systems: Thick oxide formation and its implications for fatigue reliability

    NASA Astrophysics Data System (ADS)

    Pierron, O. N.; Macdonald, D. D.; Muhlstein, C. L.

    2005-05-01

    Nanometer-scale reaction layers have a profound impact on the fracture and fatigue resistance of the Si films used in microelectromechanical systems (MEMS). This letter presents experimental evidence that thick (i.e., greater than 10nm) oxides can form at room temperature during manufacturing due to a galvanic effect between n+-type Si and Au. The growth of such oxides in concentrated HF solutions that are usually associated with oxide dissolution can be predicted from the measured current density-voltage (i-V) behavior and geometry of the galvanic couple. These results can account for unexplained findings in the literature and can be used to improve the performance of MEMS.

  4. Influence of the charge trap density distribution in a gate insulator on the positive-bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors

    NASA Astrophysics Data System (ADS)

    Kim, Eungtaek; Kim, Choong-Ki; Lee, Myung Keun; Bang, Tewook; Choi, Yang-Kyu; Park, Sang-Hee Ko; Choi, Kyung Cheol

    2016-05-01

    We investigated the positive-bias stress (PBS) instability of thin film transistors (TFTs) composed of different types of first-gate insulators, which serve as a protection layer of the active surface. Two different deposition methods, i.e., the thermal atomic layer deposition (THALD) and plasma-enhanced ALD (PEALD) of Al2O3, were applied for the deposition of the first GI. When THALD was used to deposit the GI, amorphous indium-gallium-zinc oxide (a-IGZO) TFTs showed superior stability characteristics under PBS. For example, the threshold voltage shift (ΔVth) was 0 V even after a PBS time (tstress) of 3000 s under a gate voltage (VG) condition of 5 V (with an electrical field of 1.25 MV/cm). On the other hand, when the first GI was deposited by PEALD, the ΔVth value of a-IGZO TFTs was 0.82 V after undergoing an identical amount of PBS. In order to interpret the disparate ΔVth values resulting from PBS quantitatively, the average oxide charge trap density (NT) in the GI and its spatial distribution were investigated through low-frequency noise characterizations. A higher NT resulted during in the PEALD type GI than in the THALD case. Specifically, the PEALD process on a-IGZO layer surface led to an increasing trend of NT near the GI/a-IGZO interface compared to bulk GI owing to oxygen plasma damage on the a-IGZO surface.

  5. Improved interfacial and electrical properties of GaAs metal-oxide-semiconductor capacitors with HfTiON as gate dielectric and TaON as passivation interlayer

    NASA Astrophysics Data System (ADS)

    Wang, L. S.; Xu, J. P.; Zhu, S. Y.; Huang, Y.; Lai, P. T.

    2013-08-01

    The interfacial and electrical properties of sputtered HfTiON on sulfur-passivated GaAs with or without TaON as interfacial passivation layer (IPL) are investigated. Experimental results show that the GaAs metal-oxide-semiconductor capacitor with HfTiON/TaON stacked gate dielectric annealed at 600 °C exhibits low interface-state density (1.0 × 1012 cm-2 eV-1), small gate leakage current (7.3 × 10-5 A cm-2 at Vg = Vfb + 1 V), small capacitance equivalent thickness (1.65 nm), and large equivalent dielectric constant (26.2). The involved mechanisms lie in the fact that the TaON IPL can effectively block the diffusions of Hf, Ti, and O towards GaAs surface and suppress the formation of interfacial As-As bonds, Ga-/As-oxides, thus unpinning the Femi level at the TaON/GaAs interface and improving the interface quality and electrical properties of the device.

  6. 21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, GATE PIER, TRUNNION PIN AND GATE GAUGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  7. Improved device reliability in organic light emitting devices by controlling the etching of indium zinc oxide anode

    NASA Astrophysics Data System (ADS)

    Liao, Ying-Jie; Lou, Yan-Hui; Wang, Zhao-Kui; Liao, Liang-Sheng

    2014-11-01

    A controllable etching process for indium zinc oxide (IZO) films was developed by using a weak etchant of oxalic acid with a slow etching ratio. With controllable etching time and temperature, a patterned IZO electrode with smoothed surface morphology and slope edge was achieved. For the practical application in organic light emitting devices (OLEDs), a suppression of the leak current in the current—voltage characteristics of OLEDs was observed. It resulted in a 1.6 times longer half lifetime in the IZO-based OLEDs compared to that using an indium tin oxide (ITO) anode etched by a conventional strong etchant of aqua regia.

  8. G4-FETs as Universal and Programmable Logic Gates

    NASA Technical Reports Server (NTRS)

    Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

    2007-01-01

    An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

  9. Adaptive quantum gate-set tomography

    NASA Astrophysics Data System (ADS)

    Blume-Kohout, Robin

    2013-03-01

    Quantum information hardware needs to be characterized and calibrated. This is the job of quantum state and process tomography, but standard tomographic methods have an Achilles heel: to characterize an unknown process, they rely on a set of absolutely calibrated measurements. But many technologies (e.g., solid-state qubits) admit only a single native measurement basis, and other bases are measured using unitary control. So tomography becomes circular - tomographic protocols are using gates to calibrate themselves! Gate-set tomography confronts this problem head-on and resolves it by treating gates relationally. We abandon all assumptions about what a given gate operation does, and characterize entire universal gate sets from the ground up using only the observed statistics of an [unknown] 2-outcome measurement after various strings of [unknown] gate operations. The accuracy and reliability of the resulting estimate depends critically on which gate strings are used, and benefits greatly from adaptivity. Sandia National Labs is a multiprogram laboratory operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Dept. of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000

  10. Parallelizable adiabatic gate teleportation

    NASA Astrophysics Data System (ADS)

    Nakago, Kosuke; Hajdušek, Michal; Nakayama, Shojun; Murao, Mio

    2015-12-01

    To investigate how a temporally ordered gate sequence can be parallelized in adiabatic implementations of quantum computation, we modify adiabatic gate teleportation, a model of quantum computation proposed by Bacon and Flammia [Phys. Rev. Lett. 103, 120504 (2009), 10.1103/PhysRevLett.103.120504], to a form deterministically simulating parallelized gate teleportation, which is achievable only by postselection. We introduce a twisted Heisenberg-type interaction Hamiltonian, a Heisenberg-type spin interaction where the coordinates of the second qubit are twisted according to a unitary gate. We develop parallelizable adiabatic gate teleportation (PAGT) where a sequence of unitary gates is performed in a single step of the adiabatic process. In PAGT, numeric calculations suggest the necessary time for the adiabatic evolution implementing a sequence of L unitary gates increases at most as O (L5) . However, we show that it has the interesting property that it can map the temporal order of gates to the spatial order of interactions specified by the final Hamiltonian. Using this property, we present a controlled-PAGT scheme to manipulate the order of gates by a control qubit. In the controlled-PAGT scheme, two differently ordered sequential unitary gates F G and G F are coherently performed depending on the state of a control qubit by simultaneously applying the twisted Heisenberg-type interaction Hamiltonians implementing unitary gates F and G . We investigate why the twisted Heisenberg-type interaction Hamiltonian allows PAGT. We show that the twisted Heisenberg-type interaction Hamiltonian has an ability to perform a transposed unitary gate by just modifying the space ordering of the final Hamiltonian implementing a unitary gate in adiabatic gate teleportation. The dynamics generated by the time-reversed Hamiltonian represented by the transposed unitary gate enables deterministic simulation of a postselected event of parallelized gate teleportation in adiabatic

  11. Digital Microfluidic Logic Gates

    NASA Astrophysics Data System (ADS)

    Zhao, Yang; Xu, Tao; Chakrabarty, Krishnendu

    Microfluidic computing is an emerging application for microfluidics technology. We propose microfluidic logic gates based on digital microfluidics. Using the principle of electrowetting-on-dielectric, AND, OR, NOT and XOR gates are implemented through basic droplet-handling operations such as transporting, merging and splitting. The same input-output interpretation enables the cascading of gates to create nontrivial computing systems. We present a potential application for microfluidic logic gates by implementing microfluidic logic operations for on-chip HIV test.

  12. Impact of parylene-C thickness on performance of KTaO3 field-effect transistors with high-k oxide/parylene-C hybrid gate dielectric

    NASA Astrophysics Data System (ADS)

    Wei, Tingting; Fujiwara, Kohei; Kanki, Teruo; Tanaka, Hidekazu

    2016-01-01

    The proposal of a hybrid gate dielectric systematically modulated with low-k material layer has been shown to be a promising strategy in the development of low-consumption field-effect transistors (FETs) with high performance. In this work, by fabricating KTaO3 FETs containing Y-doped Ta2O5/parylene-C hybrid gate dielectrics with different ratios of component thicknesses, we explored the dependence of the transistor electrical properties on the parylene-C layer thickness. Based on the results and analysis, an optimized transistor performance was achieved with an appropriate Y-doped Ta2O5/parylene-C thickness ratio from the point of view on low voltage operation. This study contributes to provide guidance for future device design and applications.

  13. Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

    PubMed

    Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

    2015-03-01

    Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively. PMID:25679117

  14. Investigation of field induced trapping on floating gates

    NASA Technical Reports Server (NTRS)

    Gosney, W. M.

    1975-01-01

    The development of a technology for building electrically alterable read only memories (EAROMs) or reprogrammable read only memories (RPROMs) using a single level metal gate p channel MOS process with all conventional processing steps is outlined. Nonvolatile storage of data is achieved by the use of charged floating gate electrodes. The floating gates are charged by avalanche injection of hot electrodes through gate oxide, and discharged by avalanche injection of hot holes through gate oxide. Three extra diffusion and patterning steps are all that is required to convert a standard p channel MOS process into a nonvolatile memory process. For identification, this nonvolatile memory technology was given the descriptive acronym DIFMOS which stands for Dual Injector, Floating gate MOS.

  15. Using Classical Reliability Models and Single Event Upset (SEU) Data to Determine Optimum Implementation Schemes for Triple Modular Redundancy (TMR) in SRAM-Based Field Programmable Gate Array (FPGA) Devices

    NASA Technical Reports Server (NTRS)

    Berg, M.; Kim, H.; Phan, A.; Seidleck, C.; LaBel, K.; Pellish, J.; Campola, M.

    2015-01-01

    Space applications are complex systems that require intricate trade analyses for optimum implementations. We focus on a subset of the trade process, using classical reliability theory and SEU data, to illustrate appropriate TMR scheme selection.

  16. Elementary reaction schemes for physical and chemical vapor deposition of transition metal oxides on silicon for high-k gate dielectric applications

    NASA Astrophysics Data System (ADS)

    Niu, D.; Ashcraft, R. W.; Kelly, M. J.; Chambers, J. J.; Klein, T. M.; Parsons, G. N.

    2002-05-01

    This article describes the kinetics of reactions that result in substrate consumption during formation of ultrathin transition metal oxides on silicon. Yttrium silicate films (˜40 Å) with an equivalent silicon dioxide thickness of ˜11 Å are demonstrated by physical vapor deposition (PVD) routes. Interface reactions that occur during deposition and during postdeposition treatment are observed and compared for PVD and chemical vapor deposition (CVD) yttrium oxides and CVD aluminum-oxide systems. Silicon diffusion, metal-silicon bond formation, and reactions involving hydroxides are proposed as critical processes in interface layer formation. For PVD of yttrium silicate, oxidation is thermally activated with an effective barrier of 0.3 eV, consistent with the oxidation of silicide being the rate-limited step. For CVD aluminum oxide, interface oxidation is consistent with a process limited by silicon diffusion into the deposited oxide layer.

  17. Hydrogen storage on metal oxide model clusters using density-functional methods and reliable van der Waals corrections.

    PubMed

    Gebhardt, Julian; Viñes, Francesc; Bleiziffer, Patrick; Hieringer, Wolfgang; Görling, Andreas

    2014-03-21

    We investigate the capability of low-coordinated sites on small model clusters to act as active centers for hydrogen storage. A set of small magic clusters with the formula (XY)6 (X = Mg, Ba, Be, Zn, Cd, Na, Li, B and Y = O, Se, S, F, I, N) and a "drumlike" hexagonal shape showing a low coordination number of three was screened. Oxide clusters turned out to be the most promising candidates for hydrogen storage. For these ionic compounds we explored the suitability of different van der Waals (vdW) corrections to density-functional calculations by comparing the respective H2 physisorption profile to highly accurate CCSD(T) (Coupled Cluster Singles Doubles with perturbative Triples) calculations. The Grimme D3 vdW correction in combination with the Perdew-Burke-Ernzerhof exchange-correlation functional was found to be the best approach compared to CCSD(T) hydrogen physisorption profiles and is, therefore, suited to study these and other light metal oxide systems. H2 adsorption on sites of oxide model clusters is found to meet the adsorption energy criteria for H2 storage, with bond strengths ranging from 0.15 to 0.21 eV. Energy profiles and estimates of kinetic constants for the H2 splitting reaction reveal that H2 is likely to be adsorbed molecularly on sites of (MgO)6, (BaO)6, and (BeO)6 clusters, suggesting a rapid H2 uptake/release at operating temperatures and moderate pressures. The small mass of beryllium and magnesium makes such systems appealing for meeting the gravimetric criterion for H2 storage. PMID:24499810

  18. Study of the physics of insulating films as related to the reliability of metal-oxide semiconductor devices

    NASA Astrophysics Data System (ADS)

    Young, D. R.; Dimaria, D. J.

    1983-08-01

    The papers enclosed with this report include: a new method for studying hot electron energy distributions in SiO2, plasma enhanced chemical vapor deposition of Si-rich SiO2, the use of Si-rich SiO2 to greatly reduce electron trapping effects, the use of Si-rich SiO2 to increase the yield of thin film capacitors, ellipsometry measurements of polycrystalline silicon films and the use of a delay time technique to measure the diffusion of the oxidant in SiO2 films.

  19. Gated strip proportional detector

    DOEpatents

    Morris, Christopher L.; Idzorek, George C.; Atencio, Leroy G.

    1987-01-01

    A gated strip proportional detector includes a gas tight chamber which encloses a solid ground plane, a wire anode plane, a wire gating plane, and a multiconductor cathode plane. The anode plane amplifies the amount of charge deposited in the chamber by a factor of up to 10.sup.6. The gating plane allows only charge within a narrow strip to reach the cathode. The cathode plane collects the charge allowed to pass through the gating plane on a set of conductors perpendicular to the open-gated region. By scanning the open-gated region across the chamber and reading out the charge collected on the cathode conductors after a suitable integration time for each location of the gate, a two-dimensional image of the intensity of the ionizing radiation incident on the detector can be made.

  20. Gated strip proportional detector

    DOEpatents

    Morris, C.L.; Idzorek, G.C.; Atencio, L.G.

    1985-02-19

    A gated strip proportional detector includes a gas tight chamber which encloses a solid ground plane, a wire anode plane, a wire gating plane, and a multiconductor cathode plane. The anode plane amplifies the amount of charge deposited in the chamber by a factor of up to 10/sup 6/. The gating plane allows only charge within a narrow strip to reach the cathode. The cathode plane collects the charge allowed to pass through the gating plane on a set of conductors perpendicular to the open-gated region. By scanning the open-gated region across the chamber and reading out the charge collected on the cathode conductors after a suitable integration time for each location of the gate, a two-dimensional image of the intensity of the ionizing radiation incident on the detector can be made.

  1. Direct measurement and characterization of n+ superhalo implants in a 120 nm gate-length Si metal-oxide-semiconductor field-effect transistor using cross-sectional scanning capacitance microscopy

    NASA Astrophysics Data System (ADS)

    Rosenthal, P. A.; Taur, Y.; Yu, E. T.

    2002-11-01

    We have directly measured nanoscale electronic features associated with a 120 nm physical gate length p-channel silicon metal-oxide-semiconductor field-effect transistor device structure including n+ superhalo implants using cross-sectional scanning capacitance microscopy (SCM). A dc bias-dependent voltage series of SCM images representing nine bias conditions from 2 to -2 V in 0.5 V steps was obtained. The SCM contrast observed varies with the ac and dc bias applied to the sample and allows delineation of the device features, including the p+ source and drain contacts, p+ source and drain extensions, p+ polycrystalline silicon gate, electrical p-n junction, n-well, and n+ superhalo implants. It is demonstrated that the superhalo implant features are imaged only under specific SCM bias conditions. Detailed analysis of the resulting SCM contrast indicates an apparent channel length of 73±11 nm, and reveals clear asymmetry in the individual lobes of the n+ superhalo implant features.

  2. High-permitivity cerium oxide prepared by molecular beam deposition as gate dielectric and passivation layer and applied to AlGaN/GaN power high electron mobility transistor devices

    NASA Astrophysics Data System (ADS)

    Chiu, Yu Sheng; Liao, Jen Ting; Lin, Yueh Chin; Chien Liu, Shin; Lin, Tai Ming; Iwai, Hiroshi; Kakushima, Kuniyuki; Chang, Edward Yi

    2016-05-01

    High-κ cerium oxide (CeO2) was applied to AlGaN/GaN high-electron-mobility transistors (HEMTs) as a gate insulator and a passivation layer by molecular beam deposition (MBD) for high-power applications. From capacitance–voltage (C–V) measurement results, the dielectric constant of the CeO2 film was 25.2. The C–V curves showed clear accumulation and depletion behaviors with a small hysteresis (20 mV). Moreover, the interface trap density (D it) was calculated to be 5.5 × 1011 eV‑1 cm‑2 at 150 °C. A CeO2 MOS-HEMT was fabricated and demonstrated a low subthreshold swing (SS) of 87 mV/decade, a high ON/OFF drain current ratio (I ON/I OFF) of 1.14 × 109, and a low gate leakage current density (J leakage) of 2.85 × 10‑9 A cm‑2 with an improved dynamic ON-resistance (R ON), which is about one order of magnitude lower than that of a conventional HEMT.

  3. Exhaled nitric oxide levels in childhood asthma: a more reliable indicator of asthma severity than lung function measurement?

    PubMed

    Piacentini, G L; Suzuki, Y; Bodini, A

    2000-04-01

    The level of exhaled nitric oxide (NO) has been demonstrated to reflect the degree of airway inflammation in patients with asthma and to be related to the severity of asthma, as well as to the efficacy of treatment. In contrast, lung function tests provide information about airway volumes and flows reflecting the level of airway obstruction, but do not allow any direct information about the degree of airway inflammation. Several studies have evaluated the relationships between the level of airway inflammation assessed by exhaled NO and the levels of airway obstruction and/or bronchial hyperresponsiveness in asthmatic adults and children. These studies highlight the complex pathophysiology of asthma and suggest that exhaled NO may have a promising role in addition to lung function measurement in the evaluation of asthma severity in children. PMID:18034534

  4. Range gated imaging experiments using gated intensifiers

    SciTech Connect

    McDonald, T.E. Jr.; Yates, G.J.; Cverna, F.H.; Gallegos, R.A.; Jaramillo, S.A.; Numkena, D.M.; Payton, J.; Pena-Abeyta, C.R.

    1999-03-01

    A variety of range gated imaging experiments using high-speed gated/shuttered proximity focused microchannel plate image intensifiers (MCPII) are reported. Range gated imaging experiments were conducted in water for detection of submerged mines in controlled turbidity tank test and in sea water for the Naval Coastal Sea Command/US Marine Corps. Field experiments have been conducted consisting of kilometer range imaging of resolution targets and military vehicles in atmosphere at Eglin Air Force Base for the US Air Force, and similar imaging experiments, but in smoke environment, at Redstone Arsenal for the US Army Aviation and Missile Command (AMCOM). Wavelength of the illuminating laser was 532 nm with pulse width ranging from 6 to 12 ns and comparable gate widths. These tests have shown depth resolution in the tens of centimeters range from time phasing reflected LADAR images with MCPII shutter opening.

  5. Confirming Pseudomonas putida as a reliable bioassay for demonstrating biocompatibility enhancement by solar photo-oxidative processes of a biorecalcitrant effluent.

    PubMed

    García-Ripoll, A; Amat, A M; Arques, A; Vicente, R; Ballesteros Martín, M M; Pérez, J A Sánchez; Oller, I; Malato, S

    2009-03-15

    Experiments based on Vibrio fischeri, activated sludge and Pseudomonas putida have been employed to check variation in the biocompatibility of an aqueous solution of a commercial pesticide, along solar photo-oxidative process (TiO(2) and Fenton reagent). Activated sludge-based experiments have demonstrated a complete detoxification of the solution, although important toxicity is still detected according to the more sensitive V. fischeri assays. In parallel, the biodegradability of organic matter is strongly enhanced, with BOD(5)/COD ratio above 0.8. Bioassays run with P. putida have given similar trends, remarking the convenience of using P. putida culture as a reliable and reproducible method for assessing both toxicity and biodegradability, as a substitute to other more time consuming methods. PMID:18639379

  6. Evolution of conductive filament and its impact on reliability issues in oxide-electrolyte based resistive random access memory

    PubMed Central

    Lv, Hangbing; Xu, Xiaoxin; Liu, Hongtao; Liu, Ruoyu; Liu, Qi; Banerjee, Writam; Sun, Haitao; Long, Shibing; Li, Ling; Liu, Ming

    2015-01-01

    The electrochemical metallization cell, also referred to as conductive bridge random access memory, is considered to be a promising candidate or complementary component to the traditional charge based memory. As such, it is receiving additional focus to accelerate the commercialization process. To create a successful mass product, reliability issues must first be rigorously solved. In-depth understanding of the failure behavior of the ECM is essential for performance optimization. Here, we reveal the degradation of high resistance state behaves as the majority cases of the endurance failure of the HfO2 electrolyte based ECM cell. High resolution transmission electron microscopy was used to characterize the change in filament nature after repetitive switching cycles. The result showed that Cu accumulation inside the filament played a dominant role in switching failure, which was further supported by measuring the retention of cycle dependent high resistance state and low resistance state. The clarified physical picture of filament evolution provides a basic understanding of the mechanisms of endurance and retention failure, and the relationship between them. Based on these results, applicable approaches for performance optimization can be implicatively developed, ranging from material tailoring to structure engineering and algorithm design. PMID:25586207

  7. Evolution of conductive filament and its impact on reliability issues in oxide-electrolyte based resistive random access memory.

    PubMed

    Lv, Hangbing; Xu, Xiaoxin; Liu, Hongtao; Liu, Ruoyu; Liu, Qi; Banerjee, Writam; Sun, Haitao; Long, Shibing; Li, Ling; Liu, Ming

    2015-01-01

    The electrochemical metallization cell, also referred to as conductive bridge random access memory, is considered to be a promising candidate or complementary component to the traditional charge based memory. As such, it is receiving additional focus to accelerate the commercialization process. To create a successful mass product, reliability issues must first be rigorously solved. In-depth understanding of the failure behavior of the ECM is essential for performance optimization. Here, we reveal the degradation of high resistance state behaves as the majority cases of the endurance failure of the HfO2 electrolyte based ECM cell. High resolution transmission electron microscopy was used to characterize the change in filament nature after repetitive switching cycles. The result showed that Cu accumulation inside the filament played a dominant role in switching failure, which was further supported by measuring the retention of cycle dependent high resistance state and low resistance state. The clarified physical picture of filament evolution provides a basic understanding of the mechanisms of endurance and retention failure, and the relationship between them. Based on these results, applicable approaches for performance optimization can be implicatively developed, ranging from material tailoring to structure engineering and algorithm design. PMID:25586207

  8. Analyzing Single-Event Gate Ruptures In Power MOSFET's

    NASA Technical Reports Server (NTRS)

    Zoutendyk, John A.

    1993-01-01

    Susceptibilities of power metal-oxide/semiconductor field-effect transistors (MOSFET's) to single-event gate ruptures analyzed by exposing devices to beams of energetic bromine ions while applying appropriate bias voltages to source, gate, and drain terminals and measuring current flowing into or out of each terminal.

  9. Thermally deposited Ag-doped CdS thin film transistors with high-k rare-earth oxide Nd{sub 2}O{sub 3} as gate dielectric

    SciTech Connect

    Gogoi, P.

    2013-03-15

    The performance of thermally deposited CdS thin film transistors doped with Ag has been reported. Ag-doped CdS thin films have been prepared using chemical method. High dielectric constant rare earth oxide Nd{sub 2}O{sub 3} has been used as gate insulator. The thin film trasistors are fabricated in coplanar electrode structure on ultrasonically cleaned glass substrates with a channel length of 50 {mu}m. The thin film transistors exhibit a high mobility of 4.3 cm{sup 2} V{sup -1} s{sup -1} and low threshold voltage of 1 V. The ON-OFF ratio of the thin film transistors is found as 10{sup 5}. The TFTs also exhibit good transconductance and gain band-width product of 1.15 Multiplication-Sign 10{sup -3} mho and 71 kHz respectively.

  10. Anomalous negative bias temperature instability behavior in p-channel metal-oxide-semiconductor field-effect transistors with HfSiON /SiO2 gate stack

    NASA Astrophysics Data System (ADS)

    Chen, Shih-Chang; Chien, Chao-Hsin; Lou, Jen-Chung

    2007-06-01

    In this letter, the authors systematically investigated the behavior of negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with HfSiON /SiO2 gate stack. They found that typical linear extrapolation does not work well for the lifetime extraction at the normal operation conditions since the polarities of the net trapped charge inside the high-κ dielectrics are not the same at lower and higher stress voltage regimes. In other words, as ∣Vg∣<2.5V electron trapping dominated while hole trapping dominated when ∣Vg∣>2.5V. This phenomenon obviously contradicts the essence of the linear prediction in which the same degradation mechanism is assumed through the entire stress voltage range.

  11. Molecular doping for control of gate bias stress in organic thin film transistors

    SciTech Connect

    Hein, Moritz P. Lüssem, Björn; Jankowski, Jens; Tietze, Max L.; Riede, Moritz K.; Zakhidov, Alexander A.; Leo, Karl; Fraunhofer COMEDD, Maria-Reiche-Str. 2, 01109 Dresden

    2014-01-06

    The key active devices of future organic electronic circuits are organic thin film transistors (OTFTs). Reliability of OTFTs remains one of the most challenging obstacles to be overcome for broad commercial applications. In particular, bias stress was identified as the key instability under operation for numerous OTFT devices and interfaces. Despite a multitude of experimental observations, a comprehensive mechanism describing this behavior is still missing. Furthermore, controlled methods to overcome these instabilities are so far lacking. Here, we present the approach to control and significantly alleviate the bias stress effect by using molecular doping at low concentrations. For pentacene and silicon oxide as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias stress behavior is explained in terms of the shift of Fermi Level and, thus, exponentially reduced proton generation at the pentacene/oxide interface.

  12. The dispersion in accumulation at InGaAs-based metal/oxide/semiconductor gate stacks with a bi-layered dielectric structure

    NASA Astrophysics Data System (ADS)

    Krylov, Igor; Ritter, Dan; Eizenberg, Moshe

    2015-08-01

    InGaAs gate stacks comprising the moderate dielectric constant (k) Al2O3 have a significantly lower dispersion in accumulation in comparison to stacks with the high-k HfO2 of the same physical thickness. As a result, a HfO2/Al2O3 bi-layer structure seems attractive in terms of both high effective dielectric constant and low dispersion in accumulation. The influence of Al2O3 thickness on the dispersion was investigated in metal/HfO2/Al2O3/InGaAs gate stacks with a fixed overall dielectric thickness. An effective suppression of the dispersion with the increase of the Al2O3 thickness was observed. However, the Al2O3 thickness required for passivation of the dispersion in accumulation was significantly higher in comparison to both the border traps related tunneling distance in Al2O3 and the minimal thickness required for the Al2O3/InGaAs band offset stabilization. The phenomenon can be explained by the lower dielectric constant of Al2O3 film (compared to the subsequently deposited HfO2 layer), where Al2O3 dielectric constant dependence on the film thickness enhances the dispersion intensity. As a result, the guidelines for the passivation layer engineering are: maximization of both majority carriers band offsets and of the dielectric constant of the passivation layer.

  13. Gate-set tomography and beyond

    NASA Astrophysics Data System (ADS)

    Blume-Kohout, Robin

    Four years ago, there was no reliable way to characterize and debug quantum gates. Process tomography required perfectly pre-calibrated gates, while randomized benchmarking only yielded an overall error rate. Gate-set tomography (GST) emerged around 2012-13 in several variants (most notably at IBM; see PRA 87, 062119) to address this need, providing complete and calibration-free characterization of gates. At Sandia, we have pushed the capabilities of GST well beyond these initial goals. In this talk, I'll demonstrate our open web interface, show how we characterize gates with accuracy at the Heisenberg limit, discuss how we put error bars on the results, and present experimental GST estimates with 1e-5 error bars. I'll also present preliminary results of GST on 2-qubit gates, including a brief survey of the tricks we use to make it possible. I'll conclude with an analysis of GST's limitations (e.g., it scales poorly), and the techniques under development for characterizing and debugging larger (3+ qubit) systems.

  14. Determination of prospective displacement-based gate threshold for respiratory-gated radiation delivery from retrospective phase-based gate threshold selected at 4D CT simulation

    SciTech Connect

    Vedam, S.; Archambault, L.; Starkschall, G.; Mohan, R.; Beddar, S.

    2007-11-15

    and delivery gate thresholds to within 0.3%. For patient data analysis, differences between simulation and delivery gate thresholds are reported as a fraction of the total respiratory motion range. For the smaller phase interval, the differences between simulation and delivery gate thresholds are 8{+-}11% and 14{+-}21% with and without audio-visual biofeedback, respectively, when the simulation gate threshold is determined based on the mean respiratory displacement within the 40%-60% gating phase interval. For the longer phase interval, corresponding differences are 4{+-}7% and 8{+-}15% with and without audio-visual biofeedback, respectively. Alternatively, when the simulation gate threshold is determined based on the maximum average respiratory displacement within the gating phase interval, greater differences between simulation and delivery gate thresholds are observed. A relationship between retrospective simulation gate threshold and prospective delivery gate threshold for respiratory gating is established and validated for regular and nonregular respiratory motion. Using this relationship, the delivery gate threshold can be reliably estimated at the time of 4D CT simulation, thereby improving the accuracy and efficiency of respiratory-gated radiation delivery.

  15. MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

    NASA Astrophysics Data System (ADS)

    Riggert, C.; Ziegler, M.; Schroeder, D.; Krautschneider, W. H.; Kohlstedt, H.

    2014-10-01

    Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.

  16. Low interfacial trap density and sub-nm equivalent oxide thickness in In0.53Ga0.47As (001) metal-oxide-semiconductor devices using molecular beam deposited HfO2/Al2O3 as gate dielectrics

    NASA Astrophysics Data System (ADS)

    Chu, L. K.; Merckling, C.; Alian, A.; Dekoster, J.; Kwo, J.; Hong, M.; Caymax, M.; Heyns, M.

    2011-07-01

    We investigated the passivation of In0.53Ga0.47As (001) surface by molecular beam epitaxy techniques. After growth of strained In0.53Ga0.47As on InP (001) substrate, HfO2/Al2O3 high-κ oxide stacks have been deposited in-situ after surface reconstruction engineering. Excellent capacitance-voltage characteristics have been demonstrated along with low gate leakage currents. The interfacial density of states (Dit) of the Al2O3/In0.53Ga0.47As interface have been revealed by conductance measurement, indicating a downward Dit profile from the energy close to the valence band (medium 1012 cm-2eV-1) towards that close to the conduction band (1011 cm-2eV-1). The low Dit's are in good agreement with the high Fermi-level movement efficiency of greater than 80%. Moreover, excellent scalability of the HfO2 has been demonstrated as evidenced by the good dependence of capacitance oxide thickness on the HfO2 thickness (dielectric constant of HfO2 ˜20) and the remained low Dit's due to the thin Al2O3 passivation layer. The sample with HfO2 (3.4 nm)/Al2O3 (1.2 nm) as the gate dielectrics has exhibited an equivalent oxide thickness of ˜0.93 nm.

  17. An enzyme-free and DNA-based Feynman gate for logically reversible operation.

    PubMed

    Zhou, Chunyang; Wang, Kun; Fan, Daoqing; Wu, Changtong; Liu, Dali; Liu, Yaqing; Wang, Erkang

    2015-06-28

    A logically reversible Feynman gate was successfully realized under enzyme-free conditions by integrating graphene oxide and DNA for the first time. The gate has a one-to-one mapping function to identify inputs from the corresponding outputs. This type of reversible logic gate may have great potential applications in information processing and biosensing systems. PMID:26028329

  18. 6. DETAIL VIEW OF DAM, SHOWING TAINTER GATES, GATE PIERS ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    6. DETAIL VIEW OF DAM, SHOWING TAINTER GATES, GATE PIERS AND DAM BRIDGE, WITH ROLLER GATE HEADHOUSE IN BACKGROUND, LOOKING EAST, UPSTREAM - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  19. 5. DETAIL VIEW OF DAM, SHOWING TAINTER GATES, GATE PIERS ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    5. DETAIL VIEW OF DAM, SHOWING TAINTER GATES, GATE PIERS AND DAM BRIDGE, WITH ROLLER GATE HEADHOUSES IN BACKGROUND, LOOKING NORTHWEST, UPSTREAM - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  20. 8. VIEW OF ROLLER GATE PIER AND ROLLER GATE OPERATING ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    8. VIEW OF ROLLER GATE PIER AND ROLLER GATE OPERATING MACHINERY HOUSE, SHOWING SERVICE BRIDGE AND ROLLER GATE, LOOKING EAST - Upper Mississippi River Nine-Foot Channel Project, Lock & Dam No. 25, Cap au Gris, Lincoln County, MO

  1. 28. VIEW OF MITER GATE OPERATING MACHINERY, SHOWING MITER GATE, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    28. VIEW OF MITER GATE OPERATING MACHINERY, SHOWING MITER GATE, GATE STRUT, AND SECTOR ARM, LOOKING EAST - Upper Mississippi River Nine-Foot Channel Project, Lock & Dam No. 25, Cap au Gris, Lincoln County, MO

  2. 19. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    19. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, PIER, TRUNNION PIN AND GATE GAUGE, LOOKING NORTH - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  3. 15. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATES AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    15. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATES AND GATE ARMS, PIERS AND DAM BRIDGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  4. 4. DETAIL VIEW OF TAINTER GATE PIER AND TAINTER GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    4. DETAIL VIEW OF TAINTER GATE PIER AND TAINTER GATE NO. 7 AND NON-SUBMERSIBLE TAINTER GATES, LOOKING WEST (UPSTREAM) - Upper Mississippi River 9-Foot Channel Project, Lock & Dam 26R, Alton, Madison County, IL

  5. Effect of F on B penetration through gate oxide for BF{sub 2} implants used to obtain ultra-shallow junctions by RTA

    SciTech Connect

    Sultan, A.; Craig, M.; Banerjee, S.

    1996-12-31

    We have studied enhancement of B penetration due to the presence of F, when BF{sub 2} implants are used for s/d extension implants in p{sup +} poly gate PMOS devices. A 0.35 {mu}m CMOS full flow is used to characterize the change in linear and saturation threshold voltage due to increased B penetration. The effect of F on other device characteristics is also examined. Contrary to previous concerns, it is found that the threshold voltage shift is quite small (18 mV) for the realistic conditions studied (2{times}10{sup 14} cm{sup -2} or BF{sub 2} dose). The presence of F does not degrade other electrical characteristics such as leakage current, sub-threshold slope or transconductance.

  6. Compact drain-current model for undoped cylindrical surrounding-gate metal-oxide-semiconductor field effect transistors including short channel effects

    NASA Astrophysics Data System (ADS)

    Smaani, Billel; Latreche, Saida; Iñiguez, Benjamín

    2013-12-01

    In this paper, we present a compact model for undoped short-channel cylindrical surrounding-gate MOSFETs. The drain-current model is expressed as a function of the mobile charge density, which is calculated using the analytical expressions of the surface potential and the difference between surface and center potentials model. The short-channel effects are well incorporated in the drain-current model, such as the drain-induced barrier lowering, the charge sharing effect (VT Roll-off), the subthreshold slope degradation, and the channel length modulation. A comparison of the model results with 3D numerical simulations using Silvaco Atlas-TCAD presents a good agreement from subthreshold to strong inversion regime and for different bias voltages.

  7. Analysis of size quantization and temperature effects on the threshold voltage of thin silicon film double-gate metal-oxide-semiconductor field-effect transistor (MOSFET)

    NASA Astrophysics Data System (ADS)

    Sankar Medury, Aditya; Bhat, K. N.; Bhat, Navakanta

    2013-07-01

    In this paper, we analyze the combined effects of size quantization and device temperature variations (T = 50 K to 400 K) on the intrinsic carrier concentration (ni), electron concentration (n) and thereby on the threshold voltage (Vth) for thin silicon film (tsi = 1 nm to 10 nm) based fully-depleted Double-Gate Silicon-on-Insulator MOSFETs. The threshold voltage (Vth) is defined as the gate voltage (Vg) at which the potential at the center of the channel (Φc) begins to saturate (Φc=Φc(sat)). It is shown that in the strong quantum confinement regime (tsi≤3nm), the effects of size quantization far over-ride the effects of temperature variations on the total change in band-gap (ΔEg(eff)), intrinsic carrier concentration (ni), electron concentration (n), Φc(sat) and the threshold voltage (Vth). On the other hand, for tsi≥4 nm, it is shown that size quantization effects recede with increasing tsi, while the effects of temperature variations become increasingly significant. Through detailed analysis, a physical model for the threshold voltage is presented both for the undoped and doped cases valid over a wide-range of device temperatures, silicon film thicknesses and substrate doping densities. Both in the undoped and doped cases, it is shown that the threshold voltage strongly depends on the channel charge density and that it is independent of incomplete ionization effects, at lower device temperatures. The results are compared with the published work available in literature, and it is shown that the present approach incorporates quantization and temperature effects over the entire temperature range. We also present an analytical model for Vth as a function of device temperature (T).

  8. Shielded silicon gate complementary MOS integrated circuit.

    NASA Technical Reports Server (NTRS)

    Lin, H. C.; Halsor, J. L.; Hayes, P. J.

    1972-01-01

    An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.

  9. Sliding-gate valve

    DOEpatents

    Usnick, George B.; Ward, Gene T.; Blair, Henry O.; Roberts, James W.; Warner, Terry N.

    1979-01-01

    This invention is a novel valve of the slidable-gate type. The valve is designed especially for long-term use with highly abrasive slurries. The sealing surfaces of the gate are shielded by the valve seats when the valve is fully open or closed, and the gate-to-seat clearance is swept with an inflowing purge gas while the gate is in transit. A preferred form of the valve includes an annular valve body containing an annular seat assembly defining a flow channel. The seat assembly comprises a first seat ring which is slidably and sealably mounted in the body, and a second seat ring which is tightly fitted in the body. These rings cooperatively define an annular gap which, together with passages in the valve body, forms a guideway extending normal to the channel. A plate-type gate is mounted for reciprocation in the guideway between positions where a portion of the plate closes the channel and where a circular aperture in the gate is in register with the channel. The valve casing includes opposed chambers which extend outwardly from the body along the axis of the guideway to accommodate the end portions of the gate. The chambers are sealed from atmosphere; when the gate is in transit, purge gas is admitted to the chambers and flows inwardly through the gate-to-seat-ring, clearance, minimizing buildup of process solids therein. A shaft reciprocated by an external actuator extends into one of the sealed chambers through a shaft seal and is coupled to an end of the gate. Means are provided for adjusting the clearance between the first seat ring and the gate while the valve is in service.

  10. Improved Reading Gate For Vertical-Bloch-Line Memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

    1994-01-01

    Improved design for reading gate of vertical-Bloch-line magnetic-bubble memory increases reliability of discrimination between binary ones and zeros. Magnetic bubbles that signify binary "1" and "0" produced by applying sufficiently large chopping currents to memory stripes. Bubbles then propagated differentially in bubble sorter. Method of discriminating between ones and zeros more reliable.

  11. Control of Threshold Voltage for Top-Gated Ambipolar Field-Effect Transistor by Gate Buffer Layer.

    PubMed

    Khim, Dongyoon; Shin, Eul-Yong; Xu, Yong; Park, Won-Tae; Jin, Sung-Ho; Noh, Yong-Young

    2016-07-13

    The threshold voltage and onset voltage for p-channel and n-channel regimes of solution-processed ambipolar organic transistors with top-gate/bottom-contact (TG/BC) geometry were effectively tuned by gate buffer layers in between the gate electrode and the dielectric. The work function of a pristine Al gate electrode (-4.1 eV) was modified by cesium carbonate and vanadium oxide to -2.1 and -5.1 eV, respectively, which could control the flat-band voltage, leading to a remarkable shift of transfer curves in both negative and positive gate voltage directions without any side effects. One important feature is that the mobility of transistors is not very sensitive to the gate buffer layer. This method is simple but useful for electronic devices where the threshold voltage should be precisely controlled, such as ambipolar circuits, memory devices, and light-emitting device applications. PMID:27323003

  12. Multi-gate synergic modulation in laterally coupled synaptic transistors

    NASA Astrophysics Data System (ADS)

    Zhu, Li Qiang; Xiao, Hui; Liu, Yang Hui; Wan, Chang Jin; Shi, Yi; Wan, Qing

    2015-10-01

    Laterally coupled oxide-based synaptic transistors with multiple gates are fabricated on phosphorosilicate glass electrolyte films. Electrical performance of the transistor can be evidently improved when the device is operated in a tri-gate synergic modulation mode. Excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked, and PPF index can be effectively tuned by the voltage applied on the modulatory terminal. At last, superlinear to sublinear synaptic integration regulation is also mimicked by applying a modulatory pulse on the third modulatory terminal. The multi-gate oxide-based synaptic transistors may find potential applications in biochemical sensors and neuromorphic systems.

  13. Adiabatically implementing quantum gates

    SciTech Connect

    Sun, Jie; Lu, Songfeng Liu, Fang

    2014-06-14

    We show that, through the approach of quantum adiabatic evolution, all of the usual quantum gates can be implemented efficiently, yielding running time of order O(1). This may be considered as a useful alternative to the standard quantum computing approach, which involves quantum gates transforming quantum states during the computing process.

  14. Gates Speaks to Librarians.

    ERIC Educational Resources Information Center

    St. Lifer, Evan

    1997-01-01

    In an interview, Microsoft CEO Bill Gates answers questions about the Gates Library Foundation; Libraries Online; tax-support for libraries; comparisons to Andrew Carnegie; charges of "buying" the library market; Internet filters, policies, and government censorship; the future of the World Wide Web and the role of librarians in its future.(PEN)

  15. Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

    NASA Astrophysics Data System (ADS)

    Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

    2013-06-01

    In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

  16. Scalability of Gate/N- Overlapped Lightly Doped Drain in Deep-Submicrometer Regime

    NASA Astrophysics Data System (ADS)

    Shimizu, Masahiro; Mitsui, Katsuyoshi; Inuishi, Masahide; Arima, Hideaki; Hamaguchi, Chihiro

    1998-12-01

    In this paper an experimental study of the scalability of a gate/N- overlapped lightly doped drain (OL-LDD) structure in the deep-submicrometer regime is presented. Devices were optimized for processes with a design rule down to 0.15 µm. The allowable power supply voltage is obtained by investigating the time-dependent dielectric breakdown reliability, the minimum operating voltage, the gate-induced-drain-leakage current, the drain-induced-barrier-lowering effect and the DC hot carrier reliability. It was found that the maximum allowable supply voltage is mainly limited by the DC hot carrier reliability even in the deep-submicrometer range. A higher current-driving ability in the OL-LDD structure is achieved in comparison to that in a single drain (SD) structure when VDmax is applied as a supply voltage. The OL-LDD structure has a smaller CGD in the inversion region as well as in the accumulated region, as compared with the SD structure, especially with smaller LG. Consequently, the performance of complementary metal-oxide-semiconductor (CMOS) devices with the OL-LDD structure is superior to that with the SD structure in the deep-submicrometer regime. It is also confirmed that the OL-LDD structure has a scaling merit even for 0.15 µm CMOS devices.

  17. Optical NAND gate

    DOEpatents

    Skogen, Erik J.; Raring, James; Tauke-Pedretti, Anna

    2011-08-09

    An optical NAND gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator and a photodetector. One pair of the optical waveguide devices is electrically connected in parallel to operate as an optical AND gate; and the other pair of the optical waveguide devices is connected in series to operate as an optical NOT gate (i.e. an optical inverter). The optical NAND gate utilizes two digital optical inputs and a continuous light input to provide a NAND function output. The optical NAND gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  18. Hafnium dioxide gate dielectrics, metal gate electrodes, and phenomena occurring at their interfaces

    NASA Astrophysics Data System (ADS)

    Schaeffer, James Kenyon, III

    As metal-oxide-semiconductor field-effect transistor (MOSFET) gate lengths scale down below 45 nm, the gate oxide thickness approaches 1 nm equivalent oxide thickness. At this thickness, conventional silicon dioxide (SiO 2) gate dielectrics suffer from excessive gate leakage. Higher permittivity dielectrics are required to counter the increase in gate leakage. Hafnium dioxide (HfO2) has emerged as a promising dielectric candidate. HfO2 films deposited using metal organic chemical vapor deposition are being studied to determine the impact of process and annealing conditions on the physical and electrical properties of the gate dielectric. This study indicates that deposition and annealing temperatures influence the microstructure, density, impurity concentration, chemical environment of the impurities, and band-gap of the HfO2 dielectric. Correlations of the electrical and physical properties of the films indicate that impurities in the form of segregated carbon clusters, and low HfO2 density are detrimental to the leakage properties of the gate dielectric. Additionally, as the HfO2 thickness scales, the additional series capacitance due to poly-silicon depletion plays a larger roll in reducing the total gate capacitance. To solve this problem, high performance bulk MOSFETs will require dual metal gate electrodes possessing work functions near the silicon band edges for optimized drive current. This investigation evaluates TiN, Ta-Si-N, Ti-Al-N, WN, TaN, TaSi, Ir and IrO2 electrodes as candidate electrodes on HfO2 dielectrics. The metal-dielectric compatibility was studied by annealing the gate stacks at different temperatures. The physical stability and effective work functions of metal electrodes on HfO2 are discussed. Finally, Fermi level pinning of the metal is a barrier to identifying materials with appropriate threshold voltages. The contributions to the Fermi level pinning of platinum electrodes on HfO2 gate dielectrics are investigated by examining the

  19. Reliability issue on pipeline defects in CMOS memory devices

    NASA Astrophysics Data System (ADS)

    Youn, So; Terrell, Kyle; Wu, Chau-Chin; Shy, Paul; Lien, Chuen-Der

    1996-09-01

    Pipeline defects have recently been reported in a leakage source of CMOS devices when die shrink. We report the observed physical defects which shorted source and drain under .6 u short channel CMOS devices by the Wright-etching of the defective devices. We also found pipeline defects filled with phosphorous doped n-type material by the cross- sectioning of the pipeline in the channel of NMOS transistor. We also observed that devices are failing during high temperature reliability test, which causes single bit failure. This indicates that there are many potential defective die to reach assembly process even though most of detectives are discarded at wafer sort. SEM analysis identifies that location of defective parts is decorated with a pair of protruding holes at the 90 degree corner of field island of faulty pass-gate of SRAM. These pipeline defects are caused mainly by the compressed stress from field oxide. Reliability and yield have been improved since the pipeline were minimized after relieving stress on pass- gate.

  20. Correlation between density and oxidation temperature for pyrolytic-gas passivated ultrathin silicon oxide films

    NASA Astrophysics Data System (ADS)

    Yamada, Hiroshi

    2004-01-01

    Pyrolytic-gas passivation (PGP) with a small amount nitrogen gas enhances the breakdown reliability of silicon oxide gate films. To clarify the reliability retention of the PGP-grown films oxidized at low temperature, densities (ρox's) of the 3.5-6.5-nm-thick PGP-grown films on Si(100) oxidized at 700-900 °C were investigated. Since ρox's correlate well with the reliability and are useful as an index of the intrinsic structural characteristics of the films. Moreover, changes in ρox and nitrogen content corresponding to oxidation temperature are similar to those in breakdown reliability and interface state density (Dit), respectively. In addition, ρox's of the 700 °C-grown PGP films do not deteriorate as much when compared with those of the films grown by normal ultradry oxidation at 800 °C and their Dit's are less than about 6×1010/eV cm2. This suggests that PGP probably improves the reliability by generating the higher-ρox microscopic structure with few Si dangling bonds and effective passivation. .

  1. Gallium arsenide processing for gate array logic

    NASA Technical Reports Server (NTRS)

    Cole, Eric D.

    1989-01-01

    The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

  2. Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

    PubMed Central

    Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

    2015-01-01

    A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs. PMID:26674338

  3. Inversion gate capacitance of undoped single-gate and double-gate field-effect transistor geometries in the extreme quantum limit

    SciTech Connect

    Majumdar, Amlan

    2015-05-28

    We present first-principle analytical derivations and numerically modeled data to show that the gate capacitance per unit gate area C{sub G} of extremely thin undoped-channel single-gate and double-gate field-effect transistor geometries in the extreme quantum limit with single-subband occupancy can be written as 1/C{sub G} = 1/C{sub OX} + N{sub G}/C{sub DOS} + N{sub G}/ηC{sub WF}, where N{sub G} is the number of gates, C{sub OX} is the oxide capacitance per unit area, C{sub DOS} is the density-of-states capacitance per unit area, C{sub WF} is the wave function spreading capacitance per unit area, and η is a constant on the order of 1.

  4. 18. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    18. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATE AND GATE ARMS, GATE PIER AND DAM BRIDGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  5. 17. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    17. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATE AND GATE ARM, GATE PIER AND DAM BRIDGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  6. Optical NOR gate

    DOEpatents

    Skogen, Erik J.; Tauke-Pedretti, Anna

    2011-09-06

    An optical NOR gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical NOR gate utilizes two digital optical inputs and a continuous light input to provide a NOR function digital optical output. The optical NOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  7. Optical XOR gate

    SciTech Connect

    Vawter, G. Allen

    2013-11-12

    An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  8. Reliability training

    NASA Technical Reports Server (NTRS)

    Lalli, Vincent R. (Editor); Malec, Henry A. (Editor); Dillard, Richard B.; Wong, Kam L.; Barber, Frank J.; Barina, Frank J.

    1992-01-01

    Discussed here is failure physics, the study of how products, hardware, software, and systems fail and what can be done about it. The intent is to impart useful information, to extend the limits of production capability, and to assist in achieving low cost reliable products. A review of reliability for the years 1940 to 2000 is given. Next, a review of mathematics is given as well as a description of what elements contribute to product failures. Basic reliability theory and the disciplines that allow us to control and eliminate failures are elucidated.

  9. Optimal simulation of Deutsch gates and the Fredkin gate

    NASA Astrophysics Data System (ADS)

    Yu, Nengkun; Ying, Mingsheng

    2015-03-01

    In this paper, we study the optimal simulation of the three-qubit unitary using two-qubit gates. First, we completely characterize the two-qubit gate cost of simulating the Deutsch gate (controlled-controlled gate) by generalizing our result on the two-qubit cost of the Toffoli gate. The function of any Deutsch gate is simply a three-qubit controlled-unitary gate and can be intuitively explained as follows: The gate outputs the states of the two control qubits directly, and applies the given one-qubit unitary u on the target qubit only if both the states of the control qubits are |1 > . Previously, it was only known that five two-qubit gates are sufficient for implementing such a gate [Sleator and Weinfurter, Phys. Rev. Lett. 74, 4087 (1995), 10.1103/PhysRevLett.74.4087]. We show that if the determinant of u is 1, four two-qubit gates are optimal. Otherwise, five two-qubit gates are required. For the Fredkin gate (the controlled-swap gate), we prove that five two-qubit gates are necessary and sufficient, which settles the open problem introduced in Smolin and DiVincenzo [Phys. Rev. A 53, 2855 (1996), 10.1103/PhysRevA.53.2855].

  10. Integration of High-k Oxide on MoS2 by Using Ozone Pretreatment for High-Performance MoS2 Top-Gated Transistor with Thickness-Dependent Carrier Scattering Investigation.

    PubMed

    Wang, Jingli; Li, Songlin; Zou, Xuming; Ho, Johnny; Liao, Lei; Xiao, Xiangheng; Jiang, Changzhong; Hu, Weida; Wang, Jianlu; Li, Jinchai

    2015-11-25

    A top-gated MoS2 transistor with 6 nm thick HfO2 is fabricated using an ozone pretreatment. The influence to the top-gated mobility brought about by the deposition of HfO2 is studied statistically, for the first time. The top-gated mobility is suppressed by the deposition of HfO2 , and multilayered samples are less susceptible than monolayer ones. PMID:26426344

  11. Lifetime of high-k gate dielectrics and analogy with strength of quasibrittle structures

    NASA Astrophysics Data System (ADS)

    Le, Jia-Liang; Bažant, Zdeněk P.; Bazant, Martin Z.

    2009-11-01

    The two-parameter Weibull distribution has been widely adopted to model the lifetime statistics of dielectric breakdown under constant voltage, but recent lifetime testing for high-k gate dielectrics has revealed a systematic departure from Weibull statistics, evocative of lifetime statistics for small quasibrittle structures under constant stress. Here we identify a mathematical analogy between the dielectric breakdown in semiconductor electronic devices and the finite-size weakest-link model for mechanical strength of quasibrittle structures and adapt a recently developed probabilistic theory of structural failure to gate dielectrics. Although the theory is general and does not rely on any particular model of local breakdown events, we show how its key assumptions can be derived from the classical dielectric breakdown model, which predicts certain scaling exponents. The theory accurately fits the observed kinked shape of the histograms of lifetime plotted in Weibull scale, as well as the measured dependence of the median lifetime on the gate area (or size), including its deviation from a power law. The theory also predicts that the Weibull modulus for breakdown lifetime increases in proportion to the thickness of the oxide layer and suggests new ideas for more effective reliability testing.

  12. The human respiratory gate

    NASA Technical Reports Server (NTRS)

    Eckberg, Dwain L.

    2003-01-01

    Respiratory activity phasically alters membrane potentials of preganglionic vagal and sympathetic motoneurones and continuously modulates their responsiveness to stimulatory inputs. The most obvious manifestation of this 'respiratory gating' is respiratory sinus arrhythmia, the rhythmic fluctuations of electrocardiographic R-R intervals observed in healthy resting humans. Phasic autonomic motoneurone firing, reflecting the throughput of the system, depends importantly on the intensity of stimulatory inputs, such that when levels of stimulation are low (as with high arterial pressure and sympathetic activity, or low arterial pressure and vagal activity), respiratory fluctuations of sympathetic or vagal firing are also low. The respiratory gate has a finite capacity, and high levels of stimulation override the ability of respiration to gate autonomic responsiveness. Autonomic throughput also depends importantly on other factors, including especially, the frequency of breathing, the rate at which the gate opens and closes. Respiratory sinus arrhythmia is small at rapid, and large at slow breathing rates. The strong correlation between systolic pressure and R-R intervals at respiratory frequencies reflects the influence of respiration on these two measures, rather than arterial baroreflex physiology. A wide range of evidence suggests that respiratory activity gates the timing of autonomic motoneurone firing, but does not influence its tonic level. I propose that the most enduring significance of respiratory gating is its use as a precisely controlled experimental tool to tease out and better understand otherwise inaccessible human autonomic neurophysiological mechanisms.

  13. Low interfacial trap density and sub-nm equivalent oxide thickness in In{sub 0.53}Ga{sub 0.47}As (001) metal-oxide-semiconductor devices using molecular beam deposited HfO{sub 2}/Al{sub 2}O{sub 3} as gate dielectrics

    SciTech Connect

    Chu, L. K.; Merckling, C.; Dekoster, J.; Caymax, M.; Alian, A.; Heyns, M.; Kwo, J.; Hong, M.

    2011-07-25

    We investigated the passivation of In{sub 0.53}Ga{sub 0.47}As (001) surface by molecular beam epitaxy techniques. After growth of strained In{sub 0.53}Ga{sub 0.47}As on InP (001) substrate, HfO{sub 2}/Al{sub 2}O{sub 3} high-{kappa} oxide stacks have been deposited in-situ after surface reconstruction engineering. Excellent capacitance-voltage characteristics have been demonstrated along with low gate leakage currents. The interfacial density of states (D{sub it}) of the Al{sub 2}O{sub 3}/In{sub 0.53}Ga{sub 0.47}As interface have been revealed by conductance measurement, indicating a downward D{sub it} profile from the energy close to the valence band (medium 10{sup 12} cm{sup -2}eV{sup -1}) towards that close to the conduction band (10{sup 11} cm{sup -2}eV{sup -1}). The low D{sub it}'s are in good agreement with the high Fermi-level movement efficiency of greater than 80%. Moreover, excellent scalability of the HfO{sub 2} has been demonstrated as evidenced by the good dependence of capacitance oxide thickness on the HfO{sub 2} thickness (dielectric constant of HfO{sub 2}{approx}20) and the remained low D{sub it}'s due to the thin Al{sub 2}O{sub 3} passivation layer. The sample with HfO{sub 2} (3.4 nm)/Al{sub 2}O{sub 3} (1.2 nm) as the gate dielectrics has exhibited an equivalent oxide thickness of {approx}0.93 nm.

  14. Advanced insulated gate bipolar transistor gate drive

    DOEpatents

    Short, James Evans; West, Shawn Michael; Fabean, Robert J.

    2009-08-04

    A gate drive for an insulated gate bipolar transistor (IGBT) includes a control and protection module coupled to a collector terminal of the IGBT, an optical communications module coupled to the control and protection module, a power supply module coupled to the control and protection module and an output power stage module with inputs coupled to the power supply module and the control and protection module, and outputs coupled to a gate terminal and an emitter terminal of the IGBT. The optical communications module is configured to send control signals to the control and protection module. The power supply module is configured to distribute inputted power to the control and protection module. The control and protection module outputs on/off, soft turn-off and/or soft turn-on signals to the output power stage module, which, in turn, supplies a current based on the signal(s) from the control and protection module for charging or discharging an input capacitance of the IGBT.

  15. High-sensitivity extended-gate field-effect transistors as pH sensors with oxygen-modified reduced graphene oxide films coated on different reverse-pyramid silicon structures as sensing heads

    NASA Astrophysics Data System (ADS)

    Li, Yu-Ren; Chang, Shih-hsueh; Chang, Chia-Tsung; Tsai, Wan-Lin; Chiu, Yu-Kai; Yang, Po-Yu; Cheng, Huang-Chung

    2016-04-01

    A high-performance extended-gate field-effect transistor (EGFET) as pH sensor with its microstructured sensing head composed of an oxygen-modified reduced graphene oxide film (RGOF) on a reverse-pyramid (RP) Si structure was developed to achieve a high sensitivity of 57.5 mV/pH with an excellent linearity of 0.9929 in a wide pH sensing range of 1-13. These features were ascribed to the large amount of sensing sites and large sensing area. In contrast, the planar Si substrate with the oxygen-plasma-treated RGOF (OPT-RGOF) at the optimal bias power showed a sensitivity of 52.9 mV/pH compared with 45.0 mV/pH for that without plasma treatment. It reveals that oxygen plasma can produce oxygen-containing groups as sensing sites, enhancing proton sensing characteristics. However, oxygen plasma treatment at high bias powers would cause damage to the RGOFs, resulting in poor conducting and sensing properties. On the other hand, the use of the RP structures could increase the effective sensing area and further promote the sensing performance.

  16. Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure

    PubMed Central

    Khan, Z. N.; Ahmed, S.; Ali, M.

    2016-01-01

    Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

  17. Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure.

    PubMed

    Khan, Z N; Ahmed, S; Ali, M

    2016-01-01

    Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device's output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

  18. Demonstrating 1 nm-oxide-equivalent-thickness HfO{sub 2}/InSb structure with unpinning Fermi level and low gate leakage current density

    SciTech Connect

    Trinh, Hai-Dang; Department of Physics, Hanoi National University of Education, 136 Xuan Thuy, Cau Giay, Hanoi ; Lin, Yueh-Chin; Nguyen, Hong-Quan; Luc, Quang-Ho; Nguyen, Minh-Thuy; Duong, Quoc-Van; Nguyen, Manh-Nghia; Wang, Shin-Yuan; Yi Chang, Edward; Department of Electronic Engineering, National Chiao Tung University 1001, University Rd., Hsinchu 300, Taiwan

    2013-09-30

    In this work, the band alignment, interface, and electrical characteristics of HfO{sub 2}/InSb metal-oxide-semiconductor structure have been investigated. By using x-ray photoelectron spectroscopy analysis, the conduction band offset of 1.78 ± 0.1 eV and valence band offset of 3.35 ± 0.1 eV have been extracted. The transmission electron microscopy analysis has shown that HfO{sub 2} layer would be a good diffusion barrier for InSb. As a result, 1 nm equivalent-oxide-thickness in the 4 nm HfO{sub 2}/InSb structure has been demonstrated with unpinning Fermi level and low leakage current of 10{sup −4} A/cm{sup −2}. The D{sub it} value of smaller than 10{sup 12} eV{sup −1}cm{sup −2} has been obtained using conduction method.

  19. Radiation-hardened gate-around n-MOSFET structure for radiation-tolerant application-specific integrated circuits

    NASA Astrophysics Data System (ADS)

    Lee, Min Su; Lee, Hee Chul

    2012-11-01

    To overcome the total ionizing dose effect on an n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET), we designed a radiation-hardened gate-around n-MOSFET structure and evaluated it through a radiation-exposure experiment. Each test device was fabricated in a commercial 0.35-micron complementary metal-oxide-semiconductor (CMOS) process. The fabricated devices were evaluated under a total dose of 1 Mrad (Si) at a dose rate of 250 krad/h to obtain very high reliability for space electronics. The experimental results showed that the gate-around n-MOSFET structure had very good performance against 1 Mrad (Si) of gamma radiation, while the conventional n-MOSFET experienced a considerable amount of radiation-induced leakage current. Furthermore, a source follower designed with the gate-around transistor worked properly at 1 Mrad (Si) of gamma radiation while a source follower designed with the conventional n-MOSFET lost its functionality.

  20. Pressure Sensitive Insulated Gate Field Effect Transistor

    NASA Astrophysics Data System (ADS)

    Suminto, James Tjan-Meng

    A pressure sensitive insulated gate field effect transistor has been developed. The device is an elevated gate field-effect-transistor. It consists of a p-type silicon substrate in which two n^+ region, the source and drain, are formed. The gate electrode is a metal film sandwiched in an insulated micro-diaphragm resembling a pill-box which covers the gate oxide, drain, and source. The space between the gate electrode and the oxide is vacuum or an air-gap. When pressure is applied on the diaphragm it deflects and causes a change in the gate capacitance, and thus modulates the conductance of the channel between source and drain. A general theory dealing with the characteristic of this pressure sensitive insulated gate field effect transistor has been derived, and the device fabricated. The fabrication process utilizes the standard integrated circuit fabrication method. It features a batch fabrication of field effect devices followed by the batch fabrication of the deposited diaphragm on top of each field effect device. The keys steps of the diaphragm fabrication are the formation of spacer layer, formation of the diaphragm layer, and the subsequent removal of the spacer layer. The chip size of the device is 600 μm x 1050 mum. The diaphragm size is 200 μm x 200 mum. Characterization of the device has been performed. The current-voltage characteristics with pressure as parameters have been demonstrated and the current-pressure transfer curves obtained. They show non-linear characteristics as those of conventional capacitive pressure sensors. The linearity of threshold voltage versus pressure transfer curves has been demonstrated. The temperature effect on the device performances has been tested. The temperature coefficient of threshold voltage, rather than the electron mobility, has dominated the temperature coefficient of the device. Two temperature compensation schemes have been tested: one method is by connecting two identical PSIGFET in a differential amplifier

  1. The vertical replacement-gate (VRG) MOSFET

    NASA Astrophysics Data System (ADS)

    Hergenrother, J. M.; Oh, Sang-Hyun; Nigam, T.; Monroe, D.; Klemens, F. P.; Kornblit, A.

    2002-07-01

    We have fabricated and demonstrated a new device called the vertical replacement-gate (VRG) MOSFET. This is the first MOSFET ever built in which: (1) all critical transistor dimensions are controlled precisely without lithography and dry etch, (2) the gate length is defined by a deposited film thickness, independently of lithography and etch, and (3) a high-quality gate oxide is grown on a single-crystal Si channel. In addition to this unique combination, the VRG-MOSFET includes self-aligned source/drain extensions (SDEs) formed by solid source diffusion (SSD), small parasitic overlap, junction, and source/drain capacitances, and a replacement-gate approach to enable alternative gate stacks. We have demonstrated nMOSFETs with an initial VRG process, and pMOSFETs with a more mature process. Since both sides of the device pillar drive in parallel, the drive current per μm of coded width can far exceed that of advanced planar MOSFETs. Our 100 nm VRG-pMOSFETs with tOX=25 Å drive 615 μA/μm at 1.5 V with IOFF=8 nA/μm—80% more drive than specified in the 1999 ITRS Roadmap at the same IOFF. Our 50 nm VRG-pMOSFETs with tOX=25 Å approach the 1.0 V roadmap target of ION=350 μA/μm at IOFF=20 nA/μm without the need for a hyperthin (<20 Å) gate oxide. We have described a process for integrating n-channel and p-channel VRG-MOSFETs to form side-by-side CMOS that retains the key VRG advantages while providing packing density and process complexity that is competitive with traditional planar CMOS. All of this is achieved using current manufacturing methods, materials, and tools, and high-performance devices with 50 nm physical gate lengths ( LG) have been demonstrated with precise gate length control without advanced lithography.

  2. CFTR Gating I

    PubMed Central

    Bompadre, Silvia G.; Ai, Tomohiko; Cho, Jeong Han; Wang, Xiaohui; Sohma, Yoshiro; Li, Min; Hwang, Tzyh-Chang

    2005-01-01

    The CFTR chloride channel is activated by phosphorylation of serine residues in the regulatory (R) domain and then gated by ATP binding and hydrolysis at the nucleotide binding domains (NBDs). Studies of the ATP-dependent gating process in excised inside-out patches are very often hampered by channel rundown partly caused by membrane-associated phosphatases. Since the severed ΔR-CFTR, whose R domain is completely removed, can bypass the phosphorylation-dependent regulation, this mutant channel might be a useful tool to explore the gating mechanisms of CFTR. To this end, we investigated the regulation and gating of the ΔR-CFTR expressed in Chinese hamster ovary cells. In the cell-attached mode, basal ΔR-CFTR currents were always obtained in the absence of cAMP agonists. Application of cAMP agonists or PMA, a PKC activator, failed to affect the activity, indicating that the activity of ΔR-CFTR channels is indeed phosphorylation independent. Consistent with this conclusion, in excised inside-out patches, application of the catalytic subunit of PKA did not affect ATP-induced currents. Similarities of ATP-dependent gating between wild type and ΔR-CFTR make this phosphorylation-independent mutant a useful system to explore more extensively the gating mechanisms of CFTR. Using the ΔR-CFTR construct, we studied the inhibitory effect of ADP on CFTR gating. The Ki for ADP increases as the [ATP] is increased, suggesting a competitive mechanism of inhibition. Single channel kinetic analysis reveals a new closed state in the presence of ADP, consistent with a kinetic mechanism by which ADP binds at the same site as ATP for channel opening. Moreover, we found that the open time of the channel is shortened by as much as 54% in the presence of ADP. This unexpected result suggests another ADP binding site that modulates channel closing. PMID:15767295

  3. CMOS Active-Pixel Image Sensor With Simple Floating Gates

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

    1996-01-01

    Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

  4. Threshold-voltage instability in 4H-SiC MOSFETs with nitrided gate oxide revealed by non-relaxation method

    NASA Astrophysics Data System (ADS)

    Sometani, Mitsuru; Okamoto, Dai; Harada, Shinsuke; Ishimori, Hitoshi; Takasu, Shinji; Hatakeyama, Tetsuo; Takei, Manabu; Yonezawa, Yoshiyuki; Fukuda, Kenji; Okumura, Hajime

    2016-04-01

    The threshold-voltage (V th) shift of 4H-SiC MOSFETs with Ar or N2O post-oxidation annealing (POA) was measured by conventional sweep and non-relaxation methods. Although the V th shift values of both samples were almost identical when measured by the sweep method, those for the Ar POA samples were larger than those for the N2O POA samples when measured by the non-relaxation method. Thus, we can say that investigating the exact V th shifts using only the conventional sweep method is difficult. The temperature-dependent analysis of the V th shifts measured by both methods revealed that the N2O POA decreases charge trapping in the near-interface region of the SiO2.

  5. Single electron transistor with P-type sidewall spacer gates.

    PubMed

    Lee, Jung Han; Li, Dong Hua; Lee, Joung-Eob; Kang, Kwon-Chil; Kim, Kyungwan; Park, Byung-Gook

    2011-07-01

    A single-electron transistor (SET) is one of the promising solutions to overcome the scaling limit of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). Up to now, various kinds of SETs are being proposed and SETs with a dual gate (DG) structure using an electrical potential barrier have been demonstrated for room temperature operation. To operate DG-SETs, however, extra bias of side gates is necessary. It causes new problems that the electrode for side gates and the extra bias for electrical barrier increase the complexity in circuit design and operation power consumption, respectively. For the reason, a new mechanism using work function (WF) difference is applied to operate a SET at room temperature by three electrodes. Its structure consists of an undoped active region, a control gate, n-doped source/drain electrodes, and metal/silicide or p-type silicon side gates, and a SET with metal/silicide gates or p-type silicon gates forms tunnel barriers induced by work function between an undoped channel and grounded side gates. Via simulation, the effectiveness of the new mechanism is confirmed through various silicide materials that have different WF values. Furthermore, by considering the realistic conditions of the fabrication process, SET with p-type sidewall spacer gates was designed, and its brief fabrication process was introduced. The characteristics of its electrical barrier and the controllability of its control gate were also confirmed via simulation. Finally, a single-hole transistor with n-type sidewall spacer gates was designed. PMID:22121580

  6. Fabrication of midgap metal gates compatible with ultrathin dielectrics

    NASA Astrophysics Data System (ADS)

    Buchanan, D. A.; McFeely, F. R.; Yurkas, J. J.

    1998-09-01

    A process has been described which can produce a midgap tungsten gate compatible with the current and future complementary metal-oxide-semiconductor technology. The tungsten was deposited directly onto a 3.0 nm SiO2 gate dielectric without measurable degradation of any of its electrical properties. The tungsten deposition process yields no reactive or corrosive by-products that affect the gate dielectric integrity. The tungsten film is found to be pure within the limits of several analytical techniques and the resistivity of the tungsten films was found to be within a factor of 2 of the bulk value.

  7. The human respiratory gate

    PubMed Central

    Eckberg, Dwain L

    2003-01-01

    Respiratory activity phasically alters membrane potentials of preganglionic vagal and sympathetic motoneurones and continuously modulates their responsiveness to stimulatory inputs. The most obvious manifestation of this ‘respiratory gating’ is respiratory sinus arrhythmia, the rhythmic fluctuations of electrocardiographic R–R intervals observed in healthy resting humans. Phasic autonomic motoneurone firing, reflecting the throughput of the system, depends importantly on the intensity of stimulatory inputs, such that when levels of stimulation are low (as with high arterial pressure and sympathetic activity, or low arterial pressure and vagal activity), respiratory fluctuations of sympathetic or vagal firing are also low. The respiratory gate has a finite capacity, and high levels of stimulation override the ability of respiration to gate autonomic responsiveness. Autonomic throughput also depends importantly on other factors, including especially, the frequency of breathing, the rate at which the gate opens and closes. Respiratory sinus arrhythmia is small at rapid, and large at slow breathing rates. The strong correlation between systolic pressure and R–R intervals at respiratory frequencies reflects the influence of respiration on these two measures, rather than arterial baroreflex physiology. A wide range of evidence suggests that respiratory activity gates the timing of autonomic motoneurone firing, but does not influence its tonic level. I propose that the most enduring significance of respiratory gating is its use as a precisely controlled experimental tool to tease out and better understand otherwise inaccessible human autonomic neurophysiological mechanisms. PMID:12626671

  8. Reliability physics

    NASA Technical Reports Server (NTRS)

    Cuddihy, E. F.; Ross, R. G., Jr.

    1984-01-01

    Speakers whose topics relate to the reliability physics of solar arrays are listed and their topics briefly reviewed. Nine reports are reviewed ranging in subjects from studies of photothermal degradation in encapsulants and polymerizable ultraviolet stabilizers to interface bonding stability to electrochemical degradation of photovoltaic modules.

  9. 25. DETAIL VIEW OF TAINTER GATE, SHOWING GATE PIER, SWITCH ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    25. DETAIL VIEW OF TAINTER GATE, SHOWING GATE PIER, SWITCH AND CHAIN MOUNTED ON UNDERSIDE OF DAM BRIDGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  10. 24. DETAIL VIEW OF TAINTER GATE, SHOWING GATE PIER, SWITCH ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    24. DETAIL VIEW OF TAINTER GATE, SHOWING GATE PIER, SWITCH AND CHAIN MOUNTED ON UNDERSIDE OF DAM BRIDGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  11. 7. DETAIL VIEW OF DAM, SHOWING ROLLER GATES, GATE PIERS, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    7. DETAIL VIEW OF DAM, SHOWING ROLLER GATES, GATE PIERS, HEADHOUSES AND DAM BRIDGE, LOOKING NORTHWEST, UPSTREAM - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  12. 5. VIEW OF DAM, SHOWING TAINTER GATE PIERS, TAINTER GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    5. VIEW OF DAM, SHOWING TAINTER GATE PIERS, TAINTER GATE NO. 1, AND SERVICE BRIDGE, LOOKING SOUTHEAST (DOWNSTREAM) - Upper Mississippi River Nine-Foot Channel Project, Lock & Dam No. 25, Cap au Gris, Lincoln County, MO

  13. 4. VIEW OF DAM, SHOWING TAINTER GATE PIERS, TAINTER GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    4. VIEW OF DAM, SHOWING TAINTER GATE PIERS, TAINTER GATE NO. 1 SERVICE BRIDGE, AND LOCOMOTIVE CRANE, LOOKING NORTHEAST (UPSTREAM) - Upper Mississippi River Nine-Foot Channel Project, Lock & Dam No. 25, Cap au Gris, Lincoln County, MO

  14. Detail of gate, gate slots, and connection between the two ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    Detail of gate, gate slots, and connection between the two segments of the rectangular rearing tank. Pump house (1962) at entrance is in the background. View to the southwest. - Prairie Creek Fish Hatchery, Hwy. 101, Orick, Humboldt County, CA

  15. Cardiac gated ventilation

    SciTech Connect

    Hanson, C.W. III; Hoffman, E.A.

    1995-12-31

    There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. The authors evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50 msec scan aperture. Multi slice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. The authors observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a non-failing model of the heart.

  16. Cardiac gated ventilation

    NASA Astrophysics Data System (ADS)

    Hanson, C. William, III; Hoffman, Eric A.

    1995-05-01

    There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. We evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50msec scan aperture. Multislice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. We observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a nonfailing model of the heart.

  17. Low Gate Voltage Operated Multi-emitter-dot H+ Ion-Sensitive Gated Lateral Bipolar Junction Transistor

    NASA Astrophysics Data System (ADS)

    Yuan, Heng; Zhang, Ji-Xing; Zhang, Chen; Zhang, Ning; Xu, Li-Xia; Ding, Ming; Patrick, J. Clarke

    2015-02-01

    A low gate voltage operated multi-emitter-dot gated lateral bipolar junction transistor (BJT) ion sensor is proposed. The proposed device is composed of an arrayed gated lateral BJT, which is driven in the metal-oxide-semiconductor field-effect transistor (MOSFET)-BJT hybrid operation mode. Further, it has multiple emitter dots linked to each other in parallel to improve ionic sensitivity. Using hydrogen ionic solutions as reference solutions, we conduct experiments in which we compare the sensitivity and threshold voltage of the multi-emitter-dot gated lateral BJT with that of the single-emitter-dot gated lateral BJT. The multi-emitter-dot gated lateral BJT not only shows increased sensitivity but, more importantly, the proposed device can be operated under very low gate voltage, whereas the conventional ion-sensitive field-effect transistors cannot. This special characteristic is significant for low power devices and for function devices in which the provision of a gate voltage is difficult.

  18. Simulation of temperature dependent dielectric breakdown in n+-polySi/SiO2/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias

    NASA Astrophysics Data System (ADS)

    Samanta, Piyas; Mandal, Krishna C.

    2016-08-01

    We present for the first time a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7-25 nm) silicon dioxide (SiO2) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC). Gate oxide reliability was studied during both constant voltage and current stress with positive bias on the degenerately doped n-type poly-crystalline silicon (n+-polySi) gate at a wide range of temperatures between 27 and 225 °C. The gate leakage current was identified as the Poole-Frenkel (PF) emission of electrons trapped at an energy 0.92 eV below the SiO2 conduction band. Holes were generated in the n+-polySi anode material as well as in the oxide bulk via band-to-band ionization depending on the film thickness tox and the energy of the hot-electrons (emitted via PF mechanism) during their transport through oxide films at oxide electric fields Eox ranging from 5 to 10 MV/cm. Our simulated time-to-breakdown (tBD) results are in excellent agreement with those obtained from time consuming TDDB measurements. It is observed that irrespective of stress temperatures, the tBD values estimated in the field range between 5 and 9 MV/cm better fit to reciprocal field (1/E) model for the thickness range studied here. Furthermore, for a 10 year projected device lifetime, a good reliability margin of safe operating field from 8.5 to 7.5 MV/cm for 7 nm and 8.1 to 6.9 MV/cm for 25 nm thick SiO2 was observed between 27 and 225 °C.

  19. Effects of thickness and geometric variations in the oxide gate stack on the nonvolatile memory behaviors of charge-trap memory thin-film transistors

    NASA Astrophysics Data System (ADS)

    Bak, Jun Yong; Kim, So-Jung; Byun, Chun-Won; Pi, Jae-Eun; Ryu, Min-Ki; Hwang, Chi Sun; Yoon, Sung-Min

    2015-09-01

    Device designs of charge-trap oxide memory thin-film transistors (CTM-TFTs) were investigated to enhance their nonvolatile memory performances. The first strategy was to optimize the film thicknesses of the tunneling and charge-trap (CT) layers in order to meet requirements of both higher operation speed and longer retention time. While the program speed and memory window were improved for the device with a thinner tunneling layer, a long retention time was obtained only for the device with a tunneling layer thicker than 5 nm. The carrier concentration and charge-trap densities were optimized in the 30-nm-thick CT layer. It was observed that 10-nm-thick tunneling, 30-nm-thick CT, and 50-nm-thick blocking layers were the best configuration for our proposed CTM-TFTs, where a memory on/off margin higher than 107 was obtained, and a memory margin of 6.6 × 103 was retained even after the lapse of 105 s. The second strategy was to examine the effects of the geometrical relations between the CT and active layers for the applications of memory elements embedded in circuitries. The CTM-TFTs fabricated without an overlap between the CT layer and the drain electrode showed an enhanced program speed by the reduced parasitic capacitance. The drain-bias disturbance for the memory off-state was effectively suppressed even when a higher read-out drain voltage was applied. Appropriate device design parameters, such as the film thicknesses of each component layer and the geometrical relations between them, can improve the memory performances and expand the application fields of the proposed CTM-TFTs.

  20. Outlet side of gate, showing the Radial Gate, hoist mechanism ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    Outlet side of gate, showing the Radial Gate, hoist mechanism and concrete walkway across the canal. The concrete baffle separating the afterbay and the cipoletti weir is in the foreground - Wellton-Mohawk Irrigation System, Radial Gate Check with Drop, Wellton Canal 9.9, West of Avenue 34 East & north of County Ninth Street, Wellton, Yuma County, AZ

  1. Analysis of gate underlap channel double gate MOS transistor for electrical detection of bio-molecules

    NASA Astrophysics Data System (ADS)

    Ajay; Narang, Rakhi; Saxena, Manoj; Gupta, Mridula

    2015-12-01

    In this paper, an analytical model for gate drain underlap channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG-MOSFET) for label free electrical detection of biomolecules has been proposed. The conformal mapping technique has been used to derive the expressions for surface potential, lateral electric field, energy bands (i.e. conduction and valence band) and threshold voltage (Vth). Subsequently a full drain current model to analyze the sensitivity of the biosensor has been developed. The shift in the threshold voltage and drain current (after the biomolecules interaction with the gate underlap channel region of the MOS transistor) has been used as a sensing metric. All the characteristic trends have been verified through ATLAS (SILVACO) device simulation results.

  2. Characterization and reliability of aluminum gallium nitride/gallium nitride high electron mobility transistors

    NASA Astrophysics Data System (ADS)

    Douglas, Erica Ann

    Compound semiconductor devices, particularly those based on GaN, have found significant use in military and civilian systems for both microwave and optoelectronic applications. Future uses in ultra-high power radar systems will require the use of GaN transistors operated at very high voltages, currents and temperatures. GaN-based high electron mobility transistors (HEMTs) have proven power handling capability that overshadows all other wide band gap semiconductor devices for high frequency and high-power applications. Little conclusive research has been reported in order to determine the dominating degradation mechanisms of the devices that result in failure under standard operating conditions in the field. Therefore, it is imperative that further reliability testing be carried out to determine the failure mechanisms present in GaN HEMTs in order to improve device performance, and thus further the ability for future technologies to be developed. In order to obtain a better understanding of the true reliability of AlGaN/GaN HEMTs and determine the MTTF under standard operating conditions, it is crucial to investigate the interaction effects between thermal and electrical degradation. This research spans device characterization, device reliability, and device simulation in order to obtain an all-encompassing picture of the device physics. Initially, finite element thermal simulations were performed to investigate the effect of device design on self-heating under high power operation. This was then followed by a study of reliability of HEMTs and other tests structures during high power dc operation. Test structures without Schottky contacts showed high stability as compared to HEMTs, indicating that degradation of the gate is the reason for permanent device degradation. High reverse bias of the gate has been shown to induce the inverse piezoelectric effect, resulting in a sharp increase in gate leakage current due to crack formation. The introduction of elevated

  3. A Pt-Ti-O gate Si-metal-insulator-semiconductor field-effect transistor hydrogen gas sensor

    NASA Astrophysics Data System (ADS)

    Usagawa, Toshiyuki; Kikuchi, Yota

    2010-10-01

    A hydrogen gas sensor based on platinum-titanium-oxygen (Pt-Ti-O) gate silicon-metal-insulator-semiconductor field-effect transistors (Si-MISFETs) was developed. The sensor has a unique gate structure composed of titanium and oxygen accumulated around platinum grains on top of a novel mixed layer of nanocrystalline TiOx and superheavily oxygen-doped amorphous titanium formed on SiO2/Si substrates. The FET hydrogen sensor shows high reliability and high sensing amplitude (Δ Vg) defined by the magnitude of the threshold voltage shift. Δ Vg is well fitted by a linear function of the logarithm of air-diluted hydrogen concentration C (ppm), i.e., Δ Vg(V) =0.355 log C(ppm ) -0.610 , between 100 ppm and 1%. This high gradient coefficient of Δ Vg for the wide sensing range demonstrates that the sensor is suitable for most hydrogen-safety-monitoring sensor systems. The Pt-Ti-O structures of the sensor are typically realized by annealing Pt (15 nm)/Ti (5 nm)-gate Si-metal-oxide-semiconductor structures in air at 400 °C for 2 h. The Pt-Ti-O gate MIS structures were analyzed by transmission electron microscope (TEM), x-ray diffraction, Auger electron spectroscopy, and TEM energy dispersive x-ray spectroscopy. From the viewpoint of practical sensing applications, hydrogen postannealing of the Pt-Ti-O gate Si-MISFETs is necessary to reduce the residual sensing amplitudes with long tailing profiles.

  4. Modeling and simulation of floating gate nanocrystal FET devices and circuits

    NASA Astrophysics Data System (ADS)

    Hasaneen, El-Sayed A. M.

    The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to

  5. The four-gate transistor

    NASA Technical Reports Server (NTRS)

    Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

    2002-01-01

    The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

  6. Stanford, Duke, Rice,... and Gates?

    ERIC Educational Resources Information Center

    Carey, Kevin

    2009-01-01

    This article presents an open letter to Bill Gates. In his letter, the author suggests that Bill Gates should build a brand-new university, a great 21st-century institution of higher learning. This university will be unlike anything the world has ever seen. He asks Bill Gates not to stop helping existing colleges create the higher-education system…

  7. Strategy Retooled at Gates

    ERIC Educational Resources Information Center

    Robelen, Erik W.

    2008-01-01

    In rolling out plans last week to revamp its high school strategy and launch a major new effort on the postsecondary front, the Bill & Melinda Gates Foundation is undertaking a more sweeping approach to grantmaking that appears aimed at reshaping some core elements of the U.S. education system. The philanthropy's agenda on secondary schools…

  8. Toll Gate Metrication Project

    ERIC Educational Resources Information Center

    Izzi, John

    1974-01-01

    The project director of the Toll Gate Metrication Project describes the project as the first structured United States public school educational experiment in implementing change toward the adoption of the International System of Units. He believes the change will simplify, rather than complicate, the educational task. (AG)

  9. Single-Event Gate Rupture in Power MOSFETs: A New Radiation Hardness Assurance Approach

    NASA Technical Reports Server (NTRS)

    Lauenstein, Jean-Marie

    2011-01-01

    Almost every space mission uses vertical power metal-semiconductor-oxide field-effect transistors (MOSFETs) in its power-supply circuitry. These devices can fail catastrophically due to single-event gate rupture (SEGR) when exposed to energetic heavy ions. To reduce SEGR failure risk, the off-state operating voltages of the devices are derated based upon radiation tests at heavy-ion accelerator facilities. Testing is very expensive. Even so, data from these tests provide only a limited guide to on-orbit performance. In this work, a device simulation-based method is developed to measure the response to strikes from heavy ions unavailable at accelerator facilities but posing potential risk on orbit. This work is the first to show that the present derating factor, which was established from non-radiation reliability concerns, is appropriate to reduce on-orbit SEGR failure risk when applied to data acquired from ions with appropriate penetration range. A second important outcome of this study is the demonstration of the capability and usefulness of this simulation technique for augmenting SEGR data from accelerator beam facilities. The mechanisms of SEGR are two-fold: the gate oxide is weakened by the passage of the ion through it, and the charge ionized along the ion track in the silicon transiently increases the oxide electric field. Most hardness assurance methodologies consider the latter mechanism only. This work demonstrates through experiment and simulation that the gate oxide response should not be neglected. In addition, the premise that the temporary weakening of the oxide due to the ion interaction with it, as opposed to due to the transient oxide field generated from within the silicon, is validated. Based upon these findings, a new approach to radiation hardness assurance for SEGR in power MOSFETs is defined to reduce SEGR risk in space flight projects. Finally, the potential impact of accumulated dose over the course of a space mission on SEGR

  10. The split-gate flash memory with an extra select gate for automotive applications

    NASA Astrophysics Data System (ADS)

    Tsair, Yong-Shiuan; Fang, Yean-Kuen; Wang, Yu-Hsiung; Chu, Wen-Ting; Hsieh, Chia-Ta; Lin, Yung-Tao; Wang, Chung S.; Wong, Myron; Lee, Scott; Smolen, Richard; Liu, Bill

    2009-10-01

    In this paper, novel split-gate flash memory with an extra select gate (ESG) to improve the operation window has been investigated in details. Experimental results show that with the ESG (called 2.5T cell), the cell showed a better program wordline disturb window than that of the traditional split-gate flash memory cells (called 1.5T cell) around 0.5 V (at Vs = 10 V). The offset of minimum drain voltage to avoid punch through disturb between without and with wordline stress for 2.5T cell and 1.5T cell are around 0.05 V and 0.2 V, respectively. We attribute these improvements in wordline disturb behaviors to the reduction of channel leakage current with the addition of ESG. During the erase stage, the gate oxide of the ESG suffers free stress, thus having better oxide integrity to resist the generation of channel leakage current. In addition, the ESG offers a reverse bias to retard the leakage current from drain to source.

  11. Network reliability

    NASA Technical Reports Server (NTRS)

    Johnson, Marjory J.

    1985-01-01

    Network control (or network management) functions are essential for efficient and reliable operation of a network. Some control functions are currently included as part of the Open System Interconnection model. For local area networks, it is widely recognized that there is a need for additional control functions, including fault isolation functions, monitoring functions, and configuration functions. These functions can be implemented in either a central or distributed manner. The Fiber Distributed Data Interface Medium Access Control and Station Management protocols provide an example of distributed implementation. Relative information is presented here in outline form.

  12. Alternative Gate Dielectrics on Semiconductors for MOSFET Device Applications

    SciTech Connect

    Norton, D.P.; Budai, J.D.; Chisholm, M.F.; Pennycook, S.J.; McKee, R.; Walker, F.; Lee, Y.; Park, C.

    1999-12-06

    We have investigated the synthesis and properties of deposited oxides on Si and Ge for use as alternative gate dielectrics in MOSFET applications. The capacitance and leakage current behavior of polycrystalline Y{sub 2}O{sub 3} films synthesized by pulsed-laser deposition is reported. In addition, we also discuss the growth of epitaxial oxide structures. In particular, we have investigated the use of silicide termination for oxide growth on (001) Si using laser-molecular beam epitaxy. In addition, we discuss a novel approach involving the use of hydrogen to eliminate native oxide during initial dielectric oxide nucleation on (001) Ge.

  13. Electroluminescence from individual air-suspended carbon nanotubes within split-gate structures

    NASA Astrophysics Data System (ADS)

    Higashide, N.; Uda, T.; Yoshida, M.; Ishii, A.; Kato, Y. K.

    Electrically induced light emission from chirality-identified single-walled carbon nanotubes are investigated by utilizing split-gate field-effect devices fabricated on silicon-on-insulator substrates. We begin by etching trenches through the top silicon layer into the buried oxide, and the silicon layer is thermally oxidized for use as local gates. We partially remove the oxide and form gate electrodes, then contacts for nanotubes are deposited on both sides of the trench. Catalyst particles are placed on the contacts, and nanotubes are grown over the trench by chemical vapor deposition. We use photoluminescence microscopy to locate the nanotubes and perform excitation spectroscopy to identify their chirality. Gate-induced photoluminescence quenching is used to confirm carrier doping, and electroluminescence intensity is investigated as a function of the split-gate and bias voltages. Work supported by JSPS (KAKENHI 24340066, 26610080), MEXT (Photon Frontier Network Program, Nanotechnology Platform), Canon Foundation, and Asahi Glass Foundation.

  14. Multifunctional Logic Gate Controlled by Supply Voltage

    NASA Technical Reports Server (NTRS)

    Stoica, Adrian; Zebulum, Ricardo

    2005-01-01

    A complementary metal oxide/semiconductor (CMOS) electronic circuit functions as a NAND gate at a power-supply potential (V(sub dd)) of 3.3 V and as NOR gate for V(sub dd) = 1.8 V. In the intermediate V(sub dd) range of 1.8 to 3.3 V, this circuit performs a function intermediate between NAND and NOR with degraded noise margin. Like the circuit of the immediately preceding article, this circuit serves as a demonstration of the evolutionary approach to design of polymorphic electronics -- a technological discipline that emphasizes evolution of the design of a circuit to perform different analog and/or digital functions under different conditions. In this instance, the different conditions are different values of V(sub dd).

  15. Multifunctional Logic Gate Controlled by Temperature

    NASA Technical Reports Server (NTRS)

    Stoica, Adrian; Zebulum, Ricardo

    2005-01-01

    A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

  16. Bit Distribution and Reliability of High Density 1.5 V Ferroelectric Random Access Memory Embedded with 130 nm, 5 lm Copper Complementary Metal Oxide Semiconductor Logic

    NASA Astrophysics Data System (ADS)

    Udayakumar, K. R.; Boku, K.; Remack, K. A.; Rodriguez, J.; Summerfelt, S. R.; Celii, F. G.; Aggarwal, S.; Martin, J. S.; Hall, L.; Matz, L.; Rathsack, B.; McAdams, H.; Moise, T. S.

    2006-04-01

    High density embedded ferroelectric random access memory (FRAM), operable at 1.5 V, has been fabricated within a 130 nm, 5 lm Cu/fluorosilicate glass (FSG) logic process. To evaluate FRAM extendability to future process nodes, we have measured the bit distribution and reliability properties of arrays with varying individual capacitor areas ranging from 0.40 μm2 (130 nm node) to 0.15 μm2 (˜65 nm node). Wide signal margins, stable retention (≫10 years at 85 °C), and high endurance read/write cycling (≫1012 cycles) have been demonstrated, suggesting that reliable, high density FRAM can be realized.

  17. Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

    NASA Astrophysics Data System (ADS)

    Tianfei, Lei; Xiaorong, Luo; Rui, Ge; Xi, Chen; Yuangang, Wang; Guoliang, Yao; Yongheng, Jiang; Bo, Zhang; Zhaoji, Li

    2011-10-01

    An ultra-low specific on-resistance (Ron, sp) silicon-on-insulator (SOI) double-gate trench-type MOSFET (DG trench MOSFET) is proposed. The MOSFET features double gates and an oxide trench: the oxide trench is in the drift region, one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide. Firstly, the double gates reduce Ron, sp by forming dual conduction channels. Secondly, the oxide trench not only folds the drift region, but also modulates the electric field, thereby reducing device pitch and increasing the breakdown voltage (BV). ABV of 93 V and a Ron, sp of 51.8 mΩ·mm2 is obtained for a DG trench MOSFET with a 3 μm half-cell pitch. Compared with a single-gate SOI MOSFET (SG MOSFET) and a single-gate SOI MOSFET with an oxide trench (SG trench MOSFET), the Ron, sp of the DG trench MOSFET decreases by 63.3% and 33.8% at the same BV, respectively.

  18. Improved Retention Characteristic in Polycrystalline Silicon-Oxide-Hafnium Oxide-Oxide-Silicon-Type Nonvolatile Memory with Robust Tunnel Oxynitride

    NASA Astrophysics Data System (ADS)

    Hsieh, Chih Ren; Lai, Chiung Hui; Lin, Bo Chun; Zheng, Yuan Kai; Chung Lou, Jen; Lin, Gray

    2011-03-01

    In this paper, we present a simple novel process for forming a robust and reliable oxynitride dielectric with a high nitrogen content. It is highly suitable for n-channel metal-oxide-semiconductor field-effect transistor (nMOSFETs) and polycrystalline silicon-oxide-hafnium oxide-oxide-silicon (SOHOS)-type memory applications. The proposed approach is realized by using chemical oxide with ammonia (NH3) nitridation followed by reoxidation with oxygen (O2). The novel oxynitride process is not only compatible with the standard complementary metal-oxide-semiconductor (CMOS) process, but also can ensure the improvement of flash memory with low-cost manufacturing. The characteristics of nMOSFETs and SOHOS-type nonvolatile memories (NVMs) with a robust oxynitride as a gate oxide or tunnel oxide are studied to demonstrate their advantages such as the retardation of the stress-induced trap generation during constant-voltage stress (CVS), the program/erase behaviors, cycling endurance, and data retention. The results indicate that the proposed robust oxynitride is suitable for future nonvolatile flash memory technology application.

  19. Building on Cram’s Legacy: Stimulated Gating in Hemicarcerands

    PubMed Central

    2015-01-01

    Conspectus Donald Cram’s pioneering Nobel Prize-winning work on host–guest molecules led eventually to his creation of the field of container molecules. Cram defined two types of container molecules: carcerands and hemicarcerands. Host–guest complexes of carcerands, called carceplexes, are formed during their synthesis; once a carceplex is formed, the trapped guest cannot exit without breaking covalent bonds. Cram defined a quantity called constrictive binding, arising from the mechanical force that prevents guest escape. The constrictive binding in carceplexes is high. In contrast, hemicarcerands have low constrictive binding and are able to release the incarcerated guests at elevated temperatures without breaking covalent bonds. We have designed molecules that can switch from carcerand to hemicarcerand through a change in structure that we call gating. The original discovery of gating in container molecules involved our computational studies of a Cram hemicarceplex that was observed to release a guest upon heating. We found that the side portals of this hemicarceplex have multiple thermally accessible conformations. An eight-membered ring that is part of a portal changes from a “chair” to a “boat” structure, leading to the enlargement of the side portal and the release of the guest. This type of gating is analogous to phenomena often observed with peptide loops in enzymes. We refer to this phenomenon as thermally controlled gating. We have also designed and synthesized redox and photochemically controlled gated hemicarceplexes. Gates are built onto host molecules so that the opening or closing of such gates is stimulated by reducing or oxidizing conditions, or by ultraviolet irradiation. In both cases, the appropriate stimuli can produce a carceplex (closed gates) or hemicarceplex (open gates). A hemicarceplex with closed gates behaves like a carceplex, due to its very high constrictive binding energy. When the gates are opened, constrictive binding

  20. A quantum Fredkin gate

    PubMed Central

    Patel, Raj B.; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C.; Pryde, Geoff J.

    2016-01-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently. PMID:27051868

  1. A quantum Fredkin gate.

    PubMed

    Patel, Raj B; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C; Pryde, Geoff J

    2016-03-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently. PMID:27051868

  2. Modeling split gate tunnel barriers in lateral double top gated Si-MOS nanostructures

    NASA Astrophysics Data System (ADS)

    Shirkhorshidian, Amir; Bishop, Nathaniel; Young, Ralph; Wendt, Joel; Lilly, Michael; Carroll, Malcolm

    2012-02-01

    Reliable interpretation of quantum dot and donor transport experiments depends critically on understanding the tunnel barriers separating the localized electron state from the 2DEG regions which serve as source and drain. We analyze transport measurements through split gate point contacts, defined in a double gate enhancement mode Si-MOS device structure. We use a square barrier WKB model which accounts for barrier height dependence on applied voltage. This constant interaction model is found to produce a self-consistent characterization of barrier height and width over a wide range of applied source-drain and gate bias. The model produces similar results for many different split gate structures. We discuss this models potential for mapping between experiment and barrier simulations. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE, Office of Basic Energy Sciences user facility. The work was supported by the Sandia National Laboratories Directed Research and Development Program. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. DOE's National Nuclear Security Administration under contract DE-AC04-94AL85000.

  3. Noncollinear Polarization Gating of Attosecond Pulse Trains in the Relativistic Regime

    NASA Astrophysics Data System (ADS)

    Yeung, M.; Bierbach, J.; Eckner, E.; Rykovanov, S.; Kuschel, S.; Sävert, A.; Förster, M.; Rödel, C.; Paulus, G. G.; Cousens, S.; Coughlan, M.; Dromey, B.; Zepf, M.

    2015-11-01

    High order harmonics generated at relativistic intensities have long been recognized as a route to the most powerful extreme ultraviolet pulses. Reliably generating isolated attosecond pulses requires gating to only a single dominant optical cycle, but techniques developed for lower power lasers have not been readily transferable. We present a novel method to temporally gate attosecond pulse trains by combining noncollinear and polarization gating. This scheme uses a split beam configuration which allows pulse gating to be implemented at the high beam fluence typical of multi-TW to PW class laser systems. Scalings for the gate width demonstrate that isolated attosecond pulses are possible even for modest pulse durations achievable for existing and planned future ultrashort high-power laser systems. Experimental results demonstrating the spectral effects of temporal gating on harmonic spectra generated by a relativistic laser plasma interaction are shown.

  4. Scattering noise estimation of range-gated imaging system in turbid condition.

    PubMed

    Tan, ChingSeong; Seet, Gerald; Sluzek, Andrzej; Wang, Xin; Yuen, Chai Tong; Fam, Chen Yep; Wong, Hin Yong

    2010-09-27

    The range-gated imaging systems are reliable underwater imaging system with the capability to minimize backscattering effect from turbid media. The tail-gating technique has been developed to fine tune the signal to backscattering ratio and hence improve the gated image quality. However, the tail-gating technique has limited image quality enhancement in high turbidity levels. In this paper, we developed a numerical model of range-gated underwater imaging system for near target in turbid medium. The simulation results matched the experimental work favorably. Further investigation using this numerical model shows that the multiple scattering components of the backscattering noise dominate for propagation length larger than 4.2 Attenuation Length (AL). This has limited the enhancement of tail-gating technique in high turbidity conditions. PMID:20941011

  5. Noncollinear Polarization Gating of Attosecond Pulse Trains in the Relativistic Regime.

    PubMed

    Yeung, M; Bierbach, J; Eckner, E; Rykovanov, S; Kuschel, S; Sävert, A; Förster, M; Rödel, C; Paulus, G G; Cousens, S; Coughlan, M; Dromey, B; Zepf, M

    2015-11-01

    High order harmonics generated at relativistic intensities have long been recognized as a route to the most powerful extreme ultraviolet pulses. Reliably generating isolated attosecond pulses requires gating to only a single dominant optical cycle, but techniques developed for lower power lasers have not been readily transferable. We present a novel method to temporally gate attosecond pulse trains by combining noncollinear and polarization gating. This scheme uses a split beam configuration which allows pulse gating to be implemented at the high beam fluence typical of multi-TW to PW class laser systems. Scalings for the gate width demonstrate that isolated attosecond pulses are possible even for modest pulse durations achievable for existing and planned future ultrashort high-power laser systems. Experimental results demonstrating the spectral effects of temporal gating on harmonic spectra generated by a relativistic laser plasma interaction are shown. PMID:26588384

  6. Gated Treatment Delivery Verification With On-Line Megavoltage Fluoroscopy

    SciTech Connect

    Tai An; Christensen, James D.; Gore, Elizabeth; Khamene, Ali; Boettger, Thomas; Li, X. Allen

    2010-04-15

    Purpose: To develop and clinically demonstrate the use of on-line real-time megavoltage (MV) fluoroscopy for gated treatment delivery verification. Methods and Materials: Megavoltage fluoroscopy (MVF) image sequences were acquired using a flat panel equipped for MV cone-beam CT in synchrony with the respiratory signal obtained from the Anzai gating device. The MVF images can be obtained immediately before or during gated treatment delivery. A prototype software tool (named RTReg4D) was developed to register MVF images with phase-sequenced digitally reconstructed radiograph images generated from the treatment planning system based on four-dimensional CT. The image registration can be used to reposition the patient before or during treatment delivery. To demonstrate the reliability and clinical usefulness, the system was first tested using a thoracic phantom and then prospectively in actual patient treatments under an institutional review board-approved protocol. Results: The quality of the MVF images for lung tumors is adequate for image registration with phase-sequenced digitally reconstructed radiographs. The MVF was found to be useful for monitoring inter- and intrafractional variations of tumor positions. With the planning target volume contour displayed on the MVF images, the system can verify whether the moving target stays within the planning target volume margin during gated delivery. Conclusions: The use of MVF images was found to be clinically effective in detecting discrepancies in tumor location before and during respiration-gated treatment delivery. The tools and process developed can be useful for gated treatment delivery verification.

  7. Gating of Permanent Molds for Aluminum Casting

    SciTech Connect

    David Schwam; John F. Wallace; Tom Engle; Qingming Chang

    2004-01-01

    This report summarizes a two-year project, DE-FC07-011D13983 that concerns the gating of aluminum castings in permanent molds. The main goal of the project is to improve the quality of aluminum castings produced in permanent molds. The approach taken was to determine how the vertical type gating systems used for permanent mold castings can be designed to fill the mold cavity with a minimum of damage to the quality of the resulting casting. It is evident that somewhat different systems are preferred for different shapes and sizes of aluminum castings. The main problems caused by improper gating are entrained aluminum oxide films and entrapped gas. The project highlights the characteristic features of gating systems used in permanent mold aluminum foundries and recommends gating procedures designed to avoid common defects. The study also provides direct evidence on the filling pattern and heat flow behavior in permanent mold castings. Equipment and procedure for real time X-Ray radiography of molten aluminum flow into permanent molds have been developed. Other studies have been conducted using water flow and behavior of liquid aluminum in sand mold using real time photography. This investigation utilizes graphite molds transparent to X-Rays making it possible to observe the flow pattern through a number of vertically oriented grating systems. These have included systems that are choked at the base of a rounded vertical sprue and vertical gating systems with a variety of different ingates into the bottom of a mold cavity. These systems have also been changed to include gating systems with vertical and horizontal gate configurations. Several conclusions can be derived from this study. A sprue-well, as designed in these experiments, does not eliminate the vena contracta. Because of the swirling at the sprue-base, the circulating metal begins to push the entering metal stream toward the open runner mitigating the intended effect of the sprue-well. Improved designs of

  8. ZnO-based multiple channel and multiple gate FinMOSFETs

    NASA Astrophysics Data System (ADS)

    Lee, Ching-Ting; Huang, Hung-Lin; Tseng, Chun-Yen; Lee, Hsin-Ying

    2016-02-01

    In recent years, zinc oxide (ZnO)-based metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted much attention, because ZnO-based semiconductors possess several advantages, including large exciton binding energy, nontoxicity, biocompatibility, low material cost, and wide direct bandgap. Moreover, the ZnO-based MOSFET is one of most potential devices, due to the applications in microwave power amplifiers, logic circuits, large scale integrated circuits, and logic swing. In this study, to enhance the performances of the ZnO-based MOSFETs, the ZnObased multiple channel and multiple gate structured FinMOSFETs were fabricated using the simple laser interference photolithography method and the self-aligned photolithography method. The multiple channel structure possessed the additional sidewall depletion width control ability to improve the channel controllability, because the multiple channel sidewall portions were surrounded by the gate electrode. Furthermore, the multiple gate structure had a shorter distance between source and gate and a shorter gate length between two gates to enhance the gate operating performances. Besides, the shorter distance between source and gate could enhance the electron velocity in the channel fin structure of the multiple gate structure. In this work, ninety one channels and four gates were used in the FinMOSFETs. Consequently, the drain-source saturation current (IDSS) and maximum transconductance (gm) of the ZnO-based multiple channel and multiple gate structured FinFETs operated at a drain-source voltage (VDS) of 10 V and a gate-source voltage (VGS) of 0 V were respectively improved from 11.5 mA/mm to 13.7 mA/mm and from 4.1 mS/mm to 6.9 mS/mm in comparison with that of the conventional ZnO-based single channel and single gate MOSFETs.

  9. Technical and dosimetric aspects of respiratory gating using a pressure-sensor motion monitoring system

    SciTech Connect

    Li, X. Allen; Stepaniak, Christopher; Gore, Elizabeth

    2006-01-15

    This work introduces a gating technique that uses 4DCT to determine gating parameters and to plan gated treatment, and employs a Siemens linear accelerator to deliver the gated treatment. Because of technology incompatibility, the 4DCT scanner (LightSpeed, GE) and the Siemens accelerator require two different motion-monitoring systems. The motion monitoring system (AZ-773V, Anzai Med.) used for the gated delivery utilizes a pressure sensor to detect the external respiratory motion (pressure change) in real time. Another system (RPM, Varian) used for the 4DCT scanner (LightSpeed, GE) is based on an infrared camera to detect motion of external markers. These two motion monitoring systems (RPM and Anzai systems) were found to correlate well with each other. The depth doses and profile measured for gated delivery (with a duty cycle of 25% or 50%) were found to agree within 1.0% with those measured for ungated delivery, indicating that gating did not significantly alter beam characteristics. The measurement verified also that the MU linearity and beam output remained unchanged (within 0.3%). A practical method of using 4DCT to plan a gated treatment was developed. The duty cycle for either phase or amplitude gating can be determined based on 4DCT with consideration of set-up error and delivery efficiency. The close-loop measurement involving the entire gating process (imaging, planning, and delivery) showed that the measured isodose distributions agreed with those intended, validating the accuracy and reliability of the gating technique. Based these observations, we conclude that the gating technique introduced in this work, integrating Siemens linear accelerator and Anzai pressure sensor device with GE/Varian RPM 4DCT, is reliable and effective, and it can be used clinically to account for respiratory motion during radiation therapy.

  10. A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

    NASA Astrophysics Data System (ADS)

    Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

    2015-05-01

    This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

  11. Threshold voltage model of junctionless cylindrical surrounding gate MOSFETs including fringing field effects

    NASA Astrophysics Data System (ADS)

    Gupta, Santosh Kumar

    2015-12-01

    2D Analytical model of the body center potential (BCP) in short channel junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs is developed using evanescent mode analysis (EMA). This model also incorporates the gate bias dependent inner and outer fringing capacitances due to the gate-source/drain fringing fields. The developed model provides results in good agreement with simulated results for variations of different physical parameters of JLCSG MOSFET viz. gate length, channel radius, doping concentration, and oxide thickness. Using the BCP, an analytical model for the threshold voltage has been derived and validated against results obtained from 3D device simulator.

  12. Automation of a gated-pipe irrigation system. Final report

    SciTech Connect

    Manges, H.L.; Blume, H.R.; Matteson, D.K.; Butler, K.G.

    1981-03-01

    An existing gated-pipe system was automated by controlling flow into short segments of gated pipe with flow-control valves. Irrigation controllers and a microcomputer both operated the flow-control valves automatically by radio controls. The irrigation controllers and the microcomputer successfully operated the system. Although both can provide cutback-head irrigation, the microcomputer is capable of more flexible system operation. Radio controls sold for controlling model airplanes did not give reliable service when operated continuously in an irrigated field. Operation of the flo-control valves was satisfactory.

  13. A graphical language for reliability model generation

    NASA Technical Reports Server (NTRS)

    Howell, Sandra V.; Bavuso, Salvatore J.; Haley, Pamela J.

    1990-01-01

    A graphical interface capability of the hybrid automated reliability predictor (HARP) is described. The graphics-oriented (GO) module provides the user with a graphical language for modeling system failure modes through the selection of various fault tree gates, including sequence dependency gates, or by a Markov chain. With this graphical input language, a fault tree becomes a convenient notation for describing a system. In accounting for any sequence dependencies, HARP converts the fault-tree notation to a complex stochastic process that is reduced to a Markov chain which it can then solve for system reliability. The graphics capability is available for use on an IBM-compatible PC, a Sun, and a VAX workstation. The GO module is written in the C programming language and uses the Graphical Kernel System (GKS) standard for graphics implementation. The PC, VAX, and Sun versions of the HARP GO module are currently in beta-testing.

  14. Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

    1989-01-01

    Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

  15. ONE SHAKE GATE FORMER

    DOEpatents

    Kalibjian, R.; Perez-Mendez, V.

    1957-08-20

    An improved circuit for forming square pulses having substantially short and precise durations is described. The gate forming circuit incorporates a secondary emission R. F. pentode adapted to receive input trigger pulses amd having a positive feedback loop comnected from the dynode to the control grid to maintain conduction in response to trigger pulses. A short circuited pulse delay line is employed to precisely control the conducting time of the tube and a circuit for squelching spurious oscillations is provided in the feedback loop.

  16. Tide gate valve

    SciTech Connect

    Raftis, S. G.

    1985-01-08

    A tide gate check valve in which at least three converging sides are provided at a tapered region of a flexible sleeve, so that on reverse back pressure build-up of fluid, reverse fluid flow is prevented, while the valve sleeve does not invert or collapse. The present configuration features embedded reinforcing elements for resisting inversion or collapsing when the back pressure builds up. This feature is especially important for large-sized conduits of 36'' or 72'' diameter, or even larger, such as are common in storm sewer applications.

  17. Compact gate valve

    DOEpatents

    Bobo, Gerald E.

    1977-01-01

    This invention relates to a double-disc gate valve which is compact, comparatively simple to construct, and capable of maintaining high closing pressures on the valve discs with low frictional forces. The valve casing includes axially aligned ports. Mounted in the casing is a sealed chamber which is pivotable transversely of the axis of the ports. The chamber contains the levers for moving the valve discs axially, and an actuator for the levers. When an external drive means pivots the chamber to a position where the discs are between the ports and axially aligned therewith, the actuator for the levers is energized to move the discs into sealing engagement with the ports.

  18. 12. INTERIOR VIEW OF GATE OPERATOR ROOM, SHOWING SLIDES GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    12. INTERIOR VIEW OF GATE OPERATOR ROOM, SHOWING SLIDES GATE OPERATORS, LOOKING NORTHWEST. - Sacramento River Water Treatment Plant Intake Pier & Access Bridge, Spanning Sacramento River approximately 175 feet west of eastern levee on river; roughly .5 mile downstream from confluence of Sacramento & American Rivers, Sacramento, Sacramento County, CA

  19. 5. GATE 5, INTAKE CHANNEL LOOKING SOUTH; WATER FROM GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    5. GATE 5, INTAKE CHANNEL LOOKING SOUTH; WATER FROM GATE 5 ENTERED DITCH AND IRRIGATED HONDIUS' FIELDS. - Hondius Water Line, 1.6 miles Northwest of Park headquarters building & 1 mile Northwest of Beaver Meadows entrance station, Estes Park, Larimer County, CO

  20. 14. DETAIL: Gate recess at east gate area. Planking of ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    14. DETAIL: Gate recess at east gate area. Planking of chamber walls and spikes (rear corner) are clearly visible. - Wabash & Erie Canal, Lock No. 2, 8 miles east of Fort Wayne, adjacent to U.S. Route 24, New Haven, Allen County, IN

  1. Radial gate hoist mechanisms mounted above radial gates, view to ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    Radial gate hoist mechanisms mounted above radial gates, view to the east - Wellton-Mohawk Irrigation System, Wasteway No. 1, Wellton-Mohawk Canal, North side of Wellton-Mohawk Canal, bounded by Gila River to North & the Union Pacific Railroad & Gila Mountains to south, Wellton, Yuma County, AZ

  2. 16. Little Hell Gate Bridge with Big Hell Gate Bridge ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    16. Little Hell Gate Bridge with Big Hell Gate Bridge in background. Wards Island, New York Co., NY. Sec. 4207, MP 8.02. - Northeast Railroad Corridor, Amtrak Route between New Jersey/New York & New York/Connecticut State Lines, New York County, NY

  3. 3. TAINTER GATES (LEFT FOREGROUND) AND ROLLING SECTOR GATE AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    3. TAINTER GATES (LEFT FOREGROUND) AND ROLLING SECTOR GATE AND SPILLWAY (BACKGROUND) OF THE NORTH CHANNEL DAM, LOOKING SOUTH. - Washington Water Power Company Post Falls Power Plant, North Channel Dam, West of intersection of Spokane & Fourth Streets, Post Falls, Kootenai County, ID

  4. Nanogranular SiO2 proton gated silicon layer transistor mimicking biological synapses

    NASA Astrophysics Data System (ADS)

    Liu, M. J.; Huang, G. S.; Feng, P.; Guo, Q. L.; Shao, F.; Tian, Z. A.; Li, G. J.; Wan, Q.; Mei, Y. F.

    2016-06-01

    Silicon on insulator (SOI)-based transistors gated by nanogranular SiO2 proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

  5. Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs

    NASA Astrophysics Data System (ADS)

    Dentoni Litta, E.; Hellström, P.-E.; Östling, M.

    2015-06-01

    High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

  6. Theory and experiments of electron-hole recombination at silicon/silicon dioxide interface traps and tunneling in thin oxide MOS transistors

    NASA Astrophysics Data System (ADS)

    Cai, Jin

    2000-10-01

    Surface recombination and channel have dominated the electrical characteristics, performance and reliability of p/n junction diodes and transistors. This dissertation uses a sensitive direct-current current voltage (DCIV) method to measure base terminal currents (IB) modulated by the gate bias (VGB) and forward p/n junction bias (VPN) in a MOS transistor (MOST). Base terminal currents originate from electron-hole recombination at Si/SiO2 interface traps. Fundamental theories which relate DCIV characteristics to device and material parameters are presented. Three theory-based applications are demonstrated on both the unstressed as well as hot-carrier-stressed MOSTs: (1) determination of interface trap density and energy levels, (2) spatial profile of interface traps in the drain/base junction-space-charge region and in the channel region, and (3) determination of gate oxide thickness and impurity doping concentrations. The results show that interface trap energy levels are discrete, which is consistent with those from silicon dangling bonds; in unstressed MOS transistors interface trap density in the channel region rises sharply toward source and drain, and after channel-hot-carrier stress, interface trap density increases mostly in the junction space-charge region. As the gate oxide thins below 3 nm, the gate oxide leakage current via quantum mechanical tunneling becomes significant. A gate oxide tunneling theory which refined the traditional WKB tunneling probability is developed for modeling tunneling currents at low electric fields through a trapezoidal SiO2 barrier. Correlation with experimental data on thin oxide MOSTs reveals two new results: (1) hole tunneling dominates over electron tunneling in p+gate p-channel MOSTs, and (2) the small gate/drain overlap region passes higher tunneling currents than the channel region under depletion to flatband gate voltages. The good theory-experimental correlation enables the extraction of impurity doping concentrations

  7. Development and Application of Tools to Characterize the Oxidative Degradation of AP/HTPB/Al Propellants in a Propellant Reliability Study

    NASA Technical Reports Server (NTRS)

    Celina, Mathew; Minier, Leanna; Assink, Roger

    2000-01-01

    The oxidative thermal aging of a crosslinked hydroxyl-terminated polybutadiene (HTPB)/isophorone diisocyanate (IPDI) polyurethane rubber was studied at temperatures between 25 C and 125 C. Changes in tensile elongation, mechanical hardening, polymer network properties, density, O2 permeation, and molecular chain dynamics were investigated as a function of age. The techniques used include solvent swelling, detailed modulus profiling, and NMR relaxation measurements. The Arrhenius methodology, which normally assumes a linear extrapolation of high temperature aging data, is critically evaluated by using extensive data superposition and highly sensitive oxygen consumption measurements. Significant curvature in the Arrhenius diagram of these oxidation rates is observed to be similar to previous results found for other rubber materials that have been evaluated by this technique. Preliminary gel/network properties suggest that crosslinking is the dominant process at higher temperatures. The effect on the oxidation rate of the binder when other constituents found in propellants are present, such as ammonium perchlorate, plasticizer and aluminum powder, is presented.

  8. Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio.

    PubMed

    Vu, Quoc An; Shin, Yong Seon; Kim, Young Rae; Nguyen, Van Luan; Kang, Won Tae; Kim, Hyun; Luong, Dinh Hoa; Lee, Il Min; Lee, Kiyoung; Ko, Dong-Su; Heo, Jinseong; Park, Seongjun; Lee, Young Hee; Yu, Woo Jong

    2016-01-01

    Concepts of non-volatile memory to replace conventional flash memory have suffered from low material reliability and high off-state current, and the use of a thick, rigid blocking oxide layer in flash memory further restricts vertical scale-up. Here, we report a two-terminal floating gate memory, tunnelling random access memory fabricated by a monolayer MoS2/h-BN/monolayer graphene vertical stack. Our device uses a two-terminal electrode for current flow in the MoS2 channel and simultaneously for charging and discharging the graphene floating gate through the h-BN tunnelling barrier. By effective charge tunnelling through crystalline h-BN layer and storing charges in graphene layer, our memory device demonstrates an ultimately low off-state current of 10(-14) A, leading to ultrahigh on/off ratio over 10(9), about ∼10(3) times higher than other two-terminal memories. Furthermore, the absence of thick, rigid blocking oxides enables high stretchability (>19%) which is useful for soft electronics. PMID:27586841

  9. Gate Set Tomography on a trapped ion qubit

    NASA Astrophysics Data System (ADS)

    Nielsen, Erik; Blume-Kohout, Robin; Gamble, John; Rundinger, Kenneth; Mizrahi, Jonathan; Sterk, Johathan; Maunz, Peter

    2015-03-01

    We present enhancements to gate-set tomography (GST), which is a framework in which an entire set of quantum logic gates (including preparation and measurement) can be fully characterized without need for pre-calibrated operations. Our new method, ``extended Linear GST'' (eLGST) uses fast, reliable analysis of structured long gate sequences to deliver tomographic precision at the Heisenberg limit with GST's calibration-free framework. We demonstrate this precision on a trapped-ion qubit, and show significant (orders of magnitude) advantage over both standard process tomography and randomized benchmarking. This work was supported by the Laboratory Directed Research and Development (LDRD) program at Sandia National Laboratories. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy's National Nuclear Security Administration under Contract DE-AC04-94AL85000.

  10. Image-guided adaptive gating of lung cancer radiotherapy: a computer simulation study

    NASA Astrophysics Data System (ADS)

    Aristophanous, Michalis; Rottmann, Joerg; Park, Sang-June; Nishioka, Seiko; Shirato, Hiroki; Berbeco, Ross I.

    2010-08-01

    regularity of the breathing pattern suggesting that image-guided adaptive gating should be combined with breath coaching. The adaptive gating window technique was able to track the exhale position of the breathing cycle quite successfully. Out of a total of 53 fractions the duty cycle was greater than 20% for 42 fractions for the fixed gating window technique and for 39 fractions for the adaptive gating window technique. The results of this study suggest that real-time updating of the gating window can result in reliably low residual tumor motion and therefore can facilitate safe margin reduction.

  11. Simulation of dual-gate SOI MOSFET with different dielectric layers

    NASA Astrophysics Data System (ADS)

    Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.

    2016-04-01

    The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).

  12. Penn State DOE GATE Program

    SciTech Connect

    Anstrom, Joel

    2012-08-31

    The Graduate Automotive Technology Education (GATE) Program at The Pennsylvania State University (Penn State) was established in October 1998 pursuant to an award from the U.S. Department of Energy (U.S. DOE). The focus area of the Penn State GATE Program is advanced energy storage systems for electric and hybrid vehicles.

  13. Gates Learns to Think Big

    ERIC Educational Resources Information Center

    Robelen, Erik W.

    2006-01-01

    This article discusses how the philanthropy of Microsoft Corp software magnate co-chairs, Bill Gates and his wife Melinda, are reshaping the American high school nowadays. Gates and his wife have put the issue on the national agenda like never before, with a commitment of more than 1.3 billion US dollars this decade toward the foundation's agenda…

  14. MOV reliability evaluation and periodic verification scheduling

    SciTech Connect

    Bunte, B.D.

    1996-12-01

    The purpose of this paper is to establish a periodic verification testing schedule based on the expected long term reliability of gate or globe motor operated valves (MOVs). The methodology in this position paper determines the nominal (best estimate) design margin for any MOV based on the best available information pertaining to the MOVs design requirements, design parameters, existing hardware design, and present setup. The uncertainty in this margin is then determined using statistical means. By comparing the nominal margin to the uncertainty, the reliability of the MOV is estimated. The methodology is appropriate for evaluating the reliability of MOVs in the GL 89-10 program. It may be used following periodic testing to evaluate and trend MOV performance and reliability. It may also be used to evaluate the impact of proposed modifications and maintenance activities such as packing adjustments. In addition, it may be used to assess the impact of new information of a generic nature which impacts safety related MOVs.

  15. Reliability and Confidence.

    ERIC Educational Resources Information Center

    Test Service Bulletin, 1952

    1952-01-01

    Some aspects of test reliability are discussed. Topics covered are: (1) how high should a reliability coefficient be?; (2) two factors affecting the interpretation of reliability coefficients--range of talent and interval between testings; (3) some common misconceptions--reliability of speed tests, part vs. total reliability, reliability for what…

  16. Conical surrounding gate MOSFET: a possibility in gate-all-around family

    NASA Astrophysics Data System (ADS)

    Jena, B.; Ramkrishna, B. S.; Dash, S.; Mishra, G. P.

    2016-03-01

    In this paper a new conical surrounding gate metal-oxide-semiconductor field effect transistor (MOSFET) with triple-material gate has been proposed and verified using TCAD device simulator from Synopsis. The electrostatic performance of conical model with different tapering ratios is extensively investigated and compared with that of cylindrical model (tapering ratio TR = 1). The present model exhibits improved electrostatic behavior for an optimized tapering ratio of 0.98 as compared to the conventional cylindrical model. The results reveal that the triple-material conical model provides better ON current performance, transconductance and reduced threshold voltage. On the contrary the single-material conical model exhibits maximum {{I}}{{O}{{N}}}/{{I}}{{O}{{F}}{{F}}} ratio, minimum OFF current and reduced subthreshold swing (SS) in comparison to other models. Thus, the conical model with optimized tapering ratio can be a possible replacement of cylindrical model for low-power and high speed application.

  17. Advanced Gate and Stack Dielectric Characterization with FastGate® Technology

    NASA Astrophysics Data System (ADS)

    Hillard, Robert J.; Tan, Louison C.; Reid, Kimberly G.

    2009-09-01

    In this paper a non-damaging and non-contaminating method for performing Capacitance-Voltage (CV) and Current-Voltage (IV) electrical characterization of advanced gate dielectrics and stack capacitor films is presented. The method uses a contacting Elastic Material Probe (EM-Probe) that is made of a semiconductor compatible material and forms a gate contact diameter of about 30 to 50 microns. Key electrical parameters that are measured are, Capacitive Effective Thickness (CET), Equivalent Oxide Thickness (EOT), Interface Trap Density (Dit), delta VFB Hysteresis (ΔVFB), leakage current density (JLK), Field-to-breakdown (FBD), Charge-to-breakdown (QBD) and Stress Induced Leakage Current (SILC). Measurements can be made on either blanket or in scribe line test areas in patterned wafers.

  18. Reliable wet-chemical cleaning of natively oxidized high-efficiency Cu(In,Ga)Se2 thin-film solar cell absorbers

    NASA Astrophysics Data System (ADS)

    Lehmann, Jascha; Lehmann, Sebastian; Lauermann, Iver; Rissom, Thorsten; Kaufmann, Christian A.; Lux-Steiner, Martha Ch.; Bär, Marcus; Sadewasser, Sascha

    2014-12-01

    Currently, Cu-containing chalcopyrite-based solar cells provide the highest conversion efficiencies among all thin-film photovoltaic (PV) technologies. They have reached efficiency values above 20%, the same performance level as multi-crystalline silicon-wafer technology that dominates the commercial PV market. Chalcopyrite thin-film heterostructures consist of a layer stack with a variety of interfaces between different materials. It is the chalcopyrite/buffer region (forming the p-n junction), which is of crucial importance and therefore frequently investigated using surface and interface science tools, such as photoelectron spectroscopy and scanning probe microscopy. To ensure comparability and validity of the results, a general preparation guide for "realistic" surfaces of polycrystalline chalcopyrite thin films is highly desirable. We present results on wet-chemical cleaning procedures of polycrystalline Cu(In1-xGax)Se2 thin films with an average x = [Ga]/([In] + [Ga]) = 0.29, which were exposed to ambient conditions for different times. The hence natively oxidized sample surfaces were etched in KCN- or NH3-based aqueous solutions. By x-ray photoelectron spectroscopy, we find that the KCN treatment results in a chemical surface structure which is - apart from a slight change in surface composition - identical to a pristine as-received sample surface. Additionally, we discover a different oxidation behavior of In and Ga, in agreement with thermodynamic reference data, and we find indications for the segregation and removal of copper selenide surface phases from the polycrystalline material.

  19. 1500 Gate standard cell compatible radiation hard gate array

    SciTech Connect

    Mills, B.D.; Shafer, B.D.; Melancon, E.P.

    1984-11-01

    The G1500 gate array combines Sandia Labs' 4/3..mu.. CMOS silicon gate radiation hard process with a novel gate isolated standard cell compatible design for quick turnaround time, low cost, and radiation hardness. This device is hard to 5 x 10/sup 5/ rads, utilizes a configuration that provides high packing density, and is supported on both the Daisy and Mentor workstations. This paper describes Sandia Labs' radiation hard 4/3..mu.. process, the G1500's unique design, and the complete design capabilities offered by the workstations.

  20. Measurement of ventricular function by ECG gating during atrial fibrillation

    SciTech Connect

    Bacharach, S.L.; Green, M.V.; Bonow, R.O.; Findley, S.L.; Ostrow, H.G.; Johnston, G.S.

    1981-03-01

    The assumptions necessary to perform ECG-gated cardiac studies are seemingly not valid for patients in atrial fibrillation (AF). To evaluate the effect of AF on equilibrium gated scintigraphy, beat-by-beat measurements of left-ventricular function were made on seven subjects in AF (mean heart rate 64 bpm), using a high-efficiency nonimaging detector. The parameters evaluated were ejection fraction (EF), time to end-systole (TES), peak rates of ejection and filling (PER,PFR), and their times of occurrence (TPER, TPFR). By averaging together single-beat values of EF, PER, etc., it was possible to determine the true mean values of these parameters. The single-beam mean values were compared with the corresponding parameters calculated from one ECG-gated time-activity curve (TAC) obtained by superimposing all the single-beat TACs irrespective of their length. For this population with slow heart rates, we find that the values for EF, etc., produced from ECG-gated time-activity curves, are very similar to those obtained from the single-beat data. Thus use of ECG gating at low heart rates may allow reliable estimation of average cardiac function even in subjects with AF.

  1. Tomographic characterization of a linear optical quantum Toffoli gate

    NASA Astrophysics Data System (ADS)

    Mičuda, M.; Miková, M.; Straka, I.; Sedlák, M.; Dušek, M.; Ježek, M.; Fiurášek, J.

    2015-09-01

    We report on a detailed characterization of a three-qubit linear optical quantum Toffoli gate. Our experiment utilizes correlated photon pairs generated in the process of spontaneous parametric down-conversion. Two qubits are encoded into polarization and spatial degrees of freedom of a signal photon, and the third qubit is represented by polarization of an idler photon. The linear optical Toffoli gate is implemented by interference of photons on a partially polarizing beam splitter inserted inside a Mach Zehnder interferometer formed by two calcite beam displacers. We have measured 4032 different two-photon coincidences, which allows us to estimate the fidelity of the gate to be 90%. Although these data are not tomographically complete, we show that they are sufficient for a reliable reconstruction of the quantum process matrix of the gate via the recently proposed maximum likelihood-maximum entropy estimation procedure. To probe the entangling capability of the gate, we have investigated generation of three-qubit GHZ states from fully and partially separable input states and we have performed a full tomography of the output states. We compare the reconstructed states with theoretical predictions obtained with the use of the estimated quantum process matrix and obtain a very good agreement.

  2. Monolithic metal oxide transistors.

    PubMed

    Choi, Yongsuk; Park, Won-Yeong; Kang, Moon Sung; Yi, Gi-Ra; Lee, Jun-Young; Kim, Yong-Hoon; Cho, Jeong Ho

    2015-04-28

    We devised a simple transparent metal oxide thin film transistor architecture composed of only two component materials, an amorphous metal oxide and ion gel gate dielectric, which could be entirely assembled using room-temperature processes on a plastic substrate. The geometry cleverly takes advantage of the unique characteristics of the two components. An oxide layer is metallized upon exposure to plasma, leading to the formation of a monolithic source-channel-drain oxide layer, and the ion gel gate dielectric is used to gate the transistor channel effectively at low voltages through a coplanar gate. We confirmed that the method is generally applicable to a variety of sol-gel-processed amorphous metal oxides, including indium oxide, indium zinc oxide, and indium gallium zinc oxide. An inverter NOT logic device was assembled using the resulting devices as a proof of concept demonstration of the applicability of the devices to logic circuits. The favorable characteristics of these devices, including (i) the simplicity of the device structure with only two components, (ii) the benign fabrication processes at room temperature, (iii) the low-voltage operation under 2 V, and (iv) the excellent and stable electrical performances, together support the application of these devices to low-cost portable gadgets, i.e., cheap electronics. PMID:25777338

  3. High-fidelity gate operations for quantum computing beyond dephasing time limits

    NASA Astrophysics Data System (ADS)

    Souza, Alexandre M.; Sarthour, Roberto S.; Oliveira, Ivan S.; Suter, Dieter

    2015-12-01

    The implementation of quantum gates with fidelities that exceed the threshold for reliable quantum computing requires robust gates whose performance is not limited by the precision of the available control fields. The performance of these gates also should not be affected by the noisy environment of the quantum register. Here we use randomized benchmarking of quantum gate operations to compare the performance of different families of gates that compensate errors in the control field amplitudes and decouple the system from the environmental noise. We obtain average fidelities of up to 99.8%, which exceeds the threshold value for some quantum error correction schemes as well as the expected limit from the dephasing induced by the environment.

  4. Reliable wet-chemical cleaning of natively oxidized high-efficiency Cu(In,Ga)Se{sub 2} thin-film solar cell absorbers

    SciTech Connect

    Lehmann, Jascha; Lehmann, Sebastian; Lauermann, Iver; Rissom, Thorsten; Kaufmann, Christian A.; Lux-Steiner, Martha Ch.; Bär, Marcus; Sadewasser, Sascha

    2014-12-21

    Currently, Cu-containing chalcopyrite-based solar cells provide the highest conversion efficiencies among all thin-film photovoltaic (PV) technologies. They have reached efficiency values above 20%, the same performance level as multi-crystalline silicon-wafer technology that dominates the commercial PV market. Chalcopyrite thin-film heterostructures consist of a layer stack with a variety of interfaces between different materials. It is the chalcopyrite/buffer region (forming the p-n junction), which is of crucial importance and therefore frequently investigated using surface and interface science tools, such as photoelectron spectroscopy and scanning probe microscopy. To ensure comparability and validity of the results, a general preparation guide for “realistic” surfaces of polycrystalline chalcopyrite thin films is highly desirable. We present results on wet-chemical cleaning procedures of polycrystalline Cu(In{sub 1-x}Ga{sub x})Se{sub 2} thin films with an average x = [Ga]/([In] + [Ga]) = 0.29, which were exposed to ambient conditions for different times. The hence natively oxidized sample surfaces were etched in KCN- or NH{sub 3}-based aqueous solutions. By x-ray photoelectron spectroscopy, we find that the KCN treatment results in a chemical surface structure which is – apart from a slight change in surface composition – identical to a pristine as-received sample surface. Additionally, we discover a different oxidation behavior of In and Ga, in agreement with thermodynamic reference data, and we find indications for the segregation and removal of copper selenide surface phases from the polycrystalline material.

  5. Gate length variation effect on performance of gate-first self-aligned In₀.₅₃Ga₀.₄₇As MOSFET.

    PubMed

    Mohd Razip Wee, Mohd F; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y

    2013-01-01

    A multi-gate n-type In₀.₅₃Ga₀.₄₇As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm(2)/Vs are achieved for the gate length and width of 0.2 µm and 30 µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10(-8) A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared. PMID:24367548

  6. Gate Length Variation Effect on Performance of Gate-First Self-Aligned In0.53Ga0.47As MOSFET

    PubMed Central

    Mohd Razip Wee, Mohd F.; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y.

    2013-01-01

    A multi-gate n-type In0.53Ga0.47As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm2/Vs are achieved for the gate length and width of 0.2 µm and 30µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10−8 A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared. PMID:24367548

  7. A novel 3D embedded gate field effect transistor - Screen-grid FET - Device concept and modelling

    NASA Astrophysics Data System (ADS)

    Fobelets, K.; Ding, P. W.; Velazquez-Perez, J. E.

    2007-05-01

    A novel 3D field effect transistor on SOI - screen-grid FET (SGrFET) - is proposed and an analysis of its DC behaviour is presented by means of 2D TCAD analysis. The novel feature of the SGrFET is the design of 3D insulated gate cylinders embedded in the SOI body. This novel gate topology improves efficiency and allows great flexibility in device and gate geometry to optimize DC performance. The floating body effect is avoided and the double gating row configuration controls short channel effects. The traditional intimate relationship between gate length and source-drain distance is removed, resulting in easy control of drain induced barrier lowering, improved output conductance and ideal sub-threshold slope. The separation between the gate fingers in each row is the key factor to optimize the performance, whilst downscaling of the source-drain distance and oxide thickness is not essential from an operational point of view. The device exhibits a huge potential in low power electronics as given by an efficiency of transconductance " gm/ Id" of 39 S/A at VDS = 100 mV over a large gate voltage range and at a source-drain distance of 825 nm. We present the modelling results of the influence of gate cylinder distribution in the channel, channel doping, gate oxide thickness, gate finger distance and source-drain distance on the characteristics of the device.

  8. A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process

    NASA Astrophysics Data System (ADS)

    Xu, Gao-Bo; Xu, Qiu-Xia; Yin, Hua-Xiang; Zhou, Hua-Jie; Yang, Tao; Niu, Jie-Bin; Yu, Jia-Han; Li, Jun-Feng; Zhao, Chao

    2013-11-01

    A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors (NMOSFETs) is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10 Å was prepared by a simple physical vapor deposition method. Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate. After the source/drain formation, the poly-Si dummy gate was removed by tetramethylammonium hydroxide (TMAH) wet-etching and replaced by a TaN metal gate. Because the metal gate was formed after the ion-implant doping activation process, the effects of the high temperature process on the metal gate were avoided. The fabricated device exhibits good electrical characteristics, including good driving ability and excellent sub-threshold characteristics. The device's gate length is 73 nm, the driving current is 117 μA/μm under power supply voltages of VGS = VDS = 1.5 V and the off-state current is only 4.4 nA/μm. The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage (~ 0.24 V) for high performance NMOSFETs. The device's excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.

  9. Ion polarization behavior in alumina under pulsed gate bias stress

    SciTech Connect

    Liu, Yu; Diallo, Abdou Karim; Katz, Howard E.

    2015-03-16

    Alkali metal ion incorporation in alumina significantly increases alumina capacitance by ion polarization. With high capacitance, ion-incorporated aluminas become promising high dielectric constant (high-k) gate dielectric materials in field-effect transistors (FETs) to enable reduced operating voltage, using oxide or organic semiconductors. Alumina capacitance can be manipulated by incorporation of alkali metal ions, including potassium (K{sup +}), sodium (Na{sup +}), and lithium (Li{sup +}), having different bond strengths with oxygen. To investigate the electrical stability of zinc tin oxide-based transistors using ion incorporated alumina as gate dielectrics, pulsed biases at different duty cycles (20%, 10%, and 2% representing 5 ms, 10 ms, and 50 ms periods, respectively) were applied to the gate electrode, sweeping the gate voltage over series of these cycles. We observed a particular bias stress-induced decrease of saturation field-effect mobility accompanied by threshold voltage shifts (ΔV{sub th}) in potassium and sodium-incorporated alumina (abbreviated as PA and SA)-based FETs at high duty cycle that persisted over multiple gate voltage sweeps, suggesting a possible creation of new defects in the semiconductor. This conclusion is also supported by the greater change in the mobility-capacitance (μC) product than in capacitance itself. Moreover, a more pronounced ΔV{sub th} over shorter times was observed in lithium-incorporated alumina (abbreviated as LA)-based transistors, suggesting trapping of electrons in existing interfacial states. ΔV{sub th} from multiple gate voltage sweeps over time were fit to stretched exponential forms. All three dielectrics show good stability using 50-ms intervals (20-Hz frequencies), corresponding to 2% duty cycles.

  10. Reversible logic gates on Physarum Polycephalum

    SciTech Connect

    Schumann, Andrew

    2015-03-10

    In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum.

  11. 49 CFR 234.223 - Gate arm.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 49 Transportation 4 2012-10-01 2012-10-01 false Gate arm. 234.223 Section 234.223 Transportation... SYSTEMS Maintenance, Inspection, and Testing Maintenance Standards § 234.223 Gate arm. Each gate arm, when... maintained in a condition sufficient to be clearly viewed by approaching highway users. Each gate arm...

  12. 49 CFR 234.223 - Gate arm.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... 49 Transportation 4 2013-10-01 2013-10-01 false Gate arm. 234.223 Section 234.223 Transportation... SYSTEMS Maintenance, Inspection, and Testing Maintenance Standards § 234.223 Gate arm. Each gate arm, when... maintained in a condition sufficient to be clearly viewed by approaching highway users. Each gate arm...

  13. 49 CFR 234.223 - Gate arm.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 49 Transportation 4 2014-10-01 2014-10-01 false Gate arm. 234.223 Section 234.223 Transportation... SYSTEMS Maintenance, Inspection, and Testing Maintenance Standards § 234.223 Gate arm. Each gate arm, when... maintained in a condition sufficient to be clearly viewed by approaching highway users. Each gate arm...

  14. 49 CFR 234.223 - Gate arm.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 49 Transportation 4 2011-10-01 2011-10-01 false Gate arm. 234.223 Section 234.223 Transportation... Maintenance Standards § 234.223 Gate arm. Each gate arm, when in the downward position, shall extend across... clearly viewed by approaching highway users. Each gate arm shall start its downward motion not less...

  15. 49 CFR 234.223 - Gate arm.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Gate arm. 234.223 Section 234.223 Transportation... Maintenance Standards § 234.223 Gate arm. Each gate arm, when in the downward position, shall extend across... clearly viewed by approaching highway users. Each gate arm shall start its downward motion not less...

  16. Graphical workstation capability for reliability modeling

    NASA Technical Reports Server (NTRS)

    Bavuso, Salvatore J.; Koppen, Sandra V.; Haley, Pamela J.

    1992-01-01

    In addition to computational capabilities, software tools for estimating the reliability of fault-tolerant digital computer systems must also provide a means of interfacing with the user. Described here is the new graphical interface capability of the hybrid automated reliability predictor (HARP), a software package that implements advanced reliability modeling techniques. The graphics oriented (GO) module provides the user with a graphical language for modeling system failure modes through the selection of various fault-tree gates, including sequence-dependency gates, or by a Markov chain. By using this graphical input language, a fault tree becomes a convenient notation for describing a system. In accounting for any sequence dependencies, HARP converts the fault-tree notation to a complex stochastic process that is reduced to a Markov chain, which it can then solve for system reliability. The graphics capability is available for use on an IBM-compatible PC, a Sun, and a VAX workstation. The GO module is written in the C programming language and uses the graphical kernal system (GKS) standard for graphics implementation. The PC, VAX, and Sun versions of the HARP GO module are currently in beta-testing stages.

  17. A new analytical threshold voltage model for symmetrical double-gate MOSFETs with high- k gate dielectrics

    NASA Astrophysics Data System (ADS)

    Chiang, T. K.; Chen, M. L.

    2007-03-01

    Based on the fully two-dimensional (2D) Poisson's solution in both silicon film and insulator layer, a compact and analytical threshold voltage model, which accounts for the fringing field effect of the short channel symmetrical double-gate (SDG) MOSFETs, has been developed. Exploiting the new model, a concerned analysis combining FIBL-enhanced short-channel effects and high- k gate dielectrics assess their overall impact on SDG MOSFET's scaling. It is found that for the same equivalent oxide thickness, the gate insulator with high- k dielectric constant which keeps a great characteristic length allows less design space than SiO 2 to sustain the same FIBL induced threshold voltage degradation.

  18. Persistent optical gating of a topological insulator

    PubMed Central

    Yeats, Andrew L.; Pan, Yu; Richardella, Anthony; Mintun, Peter J.; Samarth, Nitin; Awschalom, David D.

    2015-01-01

    The spin-polarized surface states of topological insulators (TIs) are attractive for applications in spintronics and quantum computing. A central challenge with these materials is to reliably tune the chemical potential of their electrons with respect to the Dirac point and the bulk bands. We demonstrate persistent, bidirectional optical control of the chemical potential of (Bi,Sb)2Te3 thin films grown on SrTiO3. By optically modulating a space-charge layer in the SrTiO3 substrates, we induce a persistent field effect in the TI films comparable to electrostatic gating techniques but without additional materials or processing. This enables us to optically pattern arbitrarily shaped p- and n-type regions in a TI, which we subsequently image with scanning photocurrent microscopy. The ability to optically write and erase mesoscopic electronic structures in a TI may aid in the investigation of the unique properties of the topological insulating phase. The gating effect also generalizes to other thin-film materials, suggesting that these phenomena could provide optical control of chemical potential in a wide range of ultrathin electronic systems. PMID:26601300

  19. Multiple gates on working memory

    PubMed Central

    Chatham, Christopher H; Badre, David

    2015-01-01

    The contexts for action may be only transiently visible, accessible, and relevant. The corticobasal ganglia (BG) circuit addresses these demands by allowing the right motor plans to drive action at the right times, via a BG-mediated gate on motor representations. A long-standing hypothesis posits these same circuits are replicated in more rostral brain regions to support gating of cognitive representations. Key evidence now supports the prediction that BG can act as a gate on the input to working memory, as a gate on its output, and as a means of reallocating working memory representations rendered irrelevant by recent events. These discoveries validate key tenets of many computational models, circumscribe motor and cognitive models of recurrent cortical dynamics alone, and identify novel directions for research on the mechanisms of higher-level cognition. PMID:26719851

  20. Shortcut to adiabatic gate teleportation

    NASA Astrophysics Data System (ADS)

    Santos, Alan C.; Silva, Raphael D.; Sarandy, Marcelo S.

    2016-01-01

    We introduce a shortcut to the adiabatic gate teleportation model of quantum computation. More specifically, we determine fast local counterdiabatic Hamiltonians able to implement teleportation as a universal computational primitive. In this scenario, we provide the counterdiabatic driving for arbitrary n -qubit gates, which allows to achieve universality through a variety of gate sets. Remarkably, our approach maps the superadiabatic Hamiltonian HSA for an arbitrary n -qubit gate teleportation into the implementation of a rotated superadiabatic dynamics of an n -qubit state teleportation. This result is rather general, with the speed of the evolution only dictated by the quantum speed limit. In particular, we analyze the energetic cost for different Hamiltonian interpolations in the context of the energy-time complementarity.

  1. Providing Reliability of Physical Systems: Partially Programmable Circuit Design

    NASA Astrophysics Data System (ADS)

    Matrosova, A. Yu.; Ostanin, S. A.; Kirienko, I. E.

    2014-10-01

    One of the important properties of physical systems is reliability.of their functioning, in particular, reliability of functioning of logical control components of the systems. A new approach to partially programmable circuit design that allows masking stuck-at faults at gate poles of logical circuits is considered. The logical circuit consists of gates. It is supposed that only one gate pole may be fault. There are reserved programmable blocks configurable logic blocks (CLBs) based on Look Up Table (LUT) technology that may mask the fault. First, the suggested approach in contrast to the well-known ones, allows masking any stuck-at fault rather than a part of them. Second, the approach is oriented to deriving more simple masking circuit from CLBs based on a compact description of incompletely specified functions of subcircuits.

  2. The Gates, 1979-2005

    ERIC Educational Resources Information Center

    School Arts: The Art Education Magazine for Teachers, 2005

    2005-01-01

    One art critic called it pure Despite the mixed reviews of Christo and Jeanne-Claude's temporary art installation in New York's Central Park, the public reaction to The Gates was largely positive.The Gates consisted of 7,500 orange PVC frames straddling the park's walkways that varied in widths from 5 1/2 feet to 18 feet. Eight-foot-long ripstop…

  3. A molecular logic gate

    PubMed Central

    Kompa, K. L.; Levine, R. D.

    2001-01-01

    We propose a scheme for molecule-based information processing by combining well-studied spectroscopic techniques and recent results from chemical dynamics. Specifically it is discussed how optical transitions in single molecules can be used to rapidly perform classical (Boolean) logical operations. In the proposed way, a restricted number of states in a single molecule can act as a logical gate equivalent to at least two switches. It is argued that the four-level scheme can also be used to produce gain, because it allows an inversion, and not only a switching ability. The proposed scheme is quantum mechanical in that it takes advantage of the discrete nature of the energy levels but, we here discuss the temporal evolution, with the use of the populations only. On a longer time range we suggest that the same scheme could be extended to perform quantum logic, and a tentative suggestion, based on an available experiment, is discussed. We believe that the pumping can provide a partial proof of principle, although this and similar experiments were not interpreted thus far in our terms. PMID:11209046

  4. Latest design of gate valves

    SciTech Connect

    Kurzhofer, U.; Stolte, J.; Weyand, M.

    1996-12-01

    Babcock Sempell, one of the most important valve manufacturers in Europe, has delivered valves for the nuclear power industry since the beginning of the peaceful application of nuclear power in the 1960s. The latest innovation by Babcock Sempell is a gate valve that meets all recent technical requirements of the nuclear power technology. At the moment in the United States, Germany, Sweden, and many other countries, motor-operated gate and globe valves are judged very critically. Besides the absolute control of the so-called {open_quotes}trip failure,{close_quotes} the integrity of all valve parts submitted to operational forces must be maintained. In case of failure of the limit and torque switches, all valve designs have been tested with respect to the quality of guidance of the gate. The guidances (i.e., guides) shall avoid a tilting of the gate during the closing procedure. The gate valve newly designed by Babcock Sempell fulfills all these characteristic criteria. In addition, the valve has cobalt-free seat hardfacing, the suitability of which has been proven by friction tests as well as full-scale blowdown tests at the GAP of Siemens in Karlstein, West Germany. Babcock Sempell was to deliver more than 30 gate valves of this type for 5 Swedish nuclear power stations by autumn 1995. In the presentation, the author will report on the testing performed, qualifications, and sizing criteria which led to the new technical design.

  5. Redox Regulation of Neuronal Voltage-Gated Calcium Channels

    PubMed Central

    Jevtovic-Todorovic, Vesna

    2014-01-01

    Abstract Significance: Voltage-gated calcium channels are ubiquitously expressed in neurons and are key regulators of cellular excitability and synaptic transmitter release. There is accumulating evidence that multiple subtypes of voltage-gated calcium channels may be regulated by oxidation and reduction. However, the redox mechanisms involved in the regulation of channel function are not well understood. Recent Advances: Several studies have established that both T-type and high-voltage-activated subtypes of voltage-gated calcium channel can be redox-regulated. This article reviews different mechanisms that can be involved in redox regulation of calcium channel function and their implication in neuronal function, particularly in pain pathways and thalamic oscillation. Critical Issues: A current critical issue in the field is to decipher precise mechanisms of calcium channel modulation via redox reactions. In this review we discuss covalent post-translational modification via oxidation of cysteine molecules and chelation of trace metals, and reactions involving nitric oxide-related molecules and free radicals. Improved understanding of the roles of redox-based reactions in regulation of voltage-gated calcium channels may lead to improved understanding of novel redox mechanisms in physiological and pathological processes. Future Directions: Identification of redox mechanisms and sites on voltage-gated calcium channel may allow development of novel and specific ion channel therapies for unmet medical needs. Thus, it may be possible to regulate the redox state of these channels in treatment of pathological process such as epilepsy and neuropathic pain. Antioxid. Redox Signal. 21, 880–891. PMID:24161125

  6. Compatibility of RPECVD silicon dioxide with depletion gate materials for silicon-based nanostructures

    NASA Astrophysics Data System (ADS)

    Rack, Mary Jo

    The focus of this work has been upon deposited oxide and gate materials suitable for use in silicon-based nanostructures. The latter use e-beam patterned depletion gates in order to create three-dimensional confinement of electrons in the 2-dimensional electron gas of a metal-oxide-semiconductor field effect transistor (MOSFET) inversion layer. Remote Plasma Enhanced chemical Vapor Deposition (RPECVD) silicon dioxide was selected as the deposited oxide. The deposition process was optimized using statistical techniques. Typically, low temperature deposited oxide is annealed in order to achieve device quality. The behavior of the oxide as a function of deposition and annealing temperature was characterized in order to understand the advantages of the anneal and the thermal budget required to accomplish the objectives of the MOSFET gate oxide quality oxide. Bulk oxide was assessed using etch rates in HF containing solutions, infrared absorption data, refractive index, and AFM measurements of surface roughness. The interface quality was examined using C-V measurements. Breakdown measurements were performed. The impact of the oxide deposition process on a thermally established Si/SiOsb2 interface was explored. Three materials were investigated for the role of depletion gates that might tolerate a high temperature aneal: cobalt silicide, cobalt and chrome. Their thermal stability was tested, sandwiched between a thermal oxide and a deposited oxide, for annealing temperatures of 700, 800 and 900 C by Auger electron spectroscopy and cross-sectional transmission electron spectroscopy. The impact of the oxide deposition process on the depletion gates was significant and so this has been studied as well.

  7. Numerical simulation study of organic nonvolatile memory with polysilicon floating gate

    NASA Astrophysics Data System (ADS)

    Zhao-wen, Yan; Jiao, Wang; Jian-li, Qiao; Wen-jie, Chen; Pan, Yang; Tong, Xiao; Jian-hong, Yang

    2016-06-01

    A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated, in which polysilicon is sandwiched between oxide layers as a floating gate. Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed. The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing (P/E) operations at various P/E voltages are discussed. The simulated results show that present memory exhibits a large memory window of 57.5 V, and a high read current on/off ratio of ≈ 103. Compared with the reported experimental results, these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects, which shows great promise in device designing and practical application.

  8. Volumetric measurement of human red blood cells by MOSFET-based microfluidic gate.

    PubMed

    Guo, Jinhong; Ai, Ye; Cheng, Yuanbing; Li, Chang Ming; Kang, Yuejun; Wang, Zhiming

    2015-08-01

    In this paper, we present a MOSFET-based (metal oxide semiconductor field-effect transistor) microfluidic gate to characterize the translocation of red blood cells (RBCs) through a gate. In the microfluidic system, the bias voltage modulated by the particles or biological cells is connected to the gate of MOSFET. The particles or cells can be detected by monitoring the MOSFET drain current instead of DC/AC-gating method across the electronic gate. Polystyrene particles with various standard sizes are utilized to calibrate the proposed device. Furthermore, RBCs from both adults and newborn blood sample are used to characterize the performance of the device in distinguishing the two types of RBCs. As compared to conventional DC/AC current modulation method, the proposed device demonstrates a higher sensitivity and is capable of being a promising platform for bioassay analysis. PMID:25349117

  9. Reliability model generator

    NASA Technical Reports Server (NTRS)

    McMann, Catherine M. (Inventor); Cohen, Gerald C. (Inventor)

    1991-01-01

    An improved method and system for automatically generating reliability models for use with a reliability evaluation tool is described. The reliability model generator of the present invention includes means for storing a plurality of low level reliability models which represent the reliability characteristics for low level system components. In addition, the present invention includes means for defining the interconnection of the low level reliability models via a system architecture description. In accordance with the principles of the present invention, a reliability model for the entire system is automatically generated by aggregating the low level reliability models based on the system architecture description.

  10. The impact of cardiac gating on the detection of coronary calcifications in dual-energy chest radiography: a phantom study

    NASA Astrophysics Data System (ADS)

    Sabol, John M.; Liu, Ray; Saunders, Rowland; Markley, Jonathan; Moreno, Nery; Seamans, John; Wiese, Scott; Jabri, Kadri; Gilkeson, Robert C.

    2006-03-01

    The detection of coronary calcifications with CT is generally accepted as a useful method for predicting early onset of coronary artery disease. Film-screen X-ray and fluoroscopy have also been shown to have high predictive value for coronary disease diagnosis, but have minimal sensitivity. Recently, flat-panel detectors capable of dual-energy techniques have enabled the separation of soft-tissue and bone from images. Clinical studies report substantially improved sensitivity for the detection of coronary calcifications using these techniques. However, heart motion causes minor artefacts from misregistration of both calcified and soft-tissue structures, resulting in inconsistent detection of calcifications. This research examines whether cardiac gating improves the reliability of calcification detection. Single-energy, gated, and non-gated dual-energy imaging techniques are examined in a dynamic phantom model. A gating system was developed to synchronize two dual-energy exposures to a specified phase of the cardiac cycle. The performance and repeatability of the gating system was validated with the use of a cyclical phantom. An anthropomorphic phantom was developed to simulate both cardiac and soft-tissue motion, and generate ECG-like output signals. The anthropomorphic phantom and motion artefact accuracy was verified by comparison with clinical images of patients with calcifications. The ability of observers to detect calcifications in non-gated, and gated techniques was compared through the use of an ROC experiment. Gating visibly reduces the effect of motion artifacts in the dual-energy images. Without gating, motion artefacts cause greater variability in calcification detection. Comparison of the average area-under-the-curve of the ROC curves show that gating significantly increases the accuracy of calcification detection. The effects of motion and gating on DE cardiac calcification detection have been demonstrated and characterized in a phantom model that

  11. A detailed coupled-mode-space non-equilibrium Green's function simulation study of source-to-drain tunnelling in gate-all-around Si nanowire metal oxide semiconductor field effect transistors

    NASA Astrophysics Data System (ADS)

    Seoane, N.; Martinez, A.

    2013-09-01

    In this paper we present a 3D quantum transport simulation study of source-to-drain tunnelling in gate-all-around Si nanowire transistors by using the non-equilibrium Green's function approach. The impact of the channel length, device cross-section, and drain and gate applied biases on the source-to-drain tunnelling is examined in detail. The overall effect of tunnelling on the ID-VG characteristics is also investigated. Tunnelling in devices with channel lengths of 10 nm or less substantially enhances the off-current. This enhancement is more important at high drain biases and at larger cross-sections where the sub-threshold slope is substantially degraded. A less common effect is the increase in the on-current due to the tunnelling which contributes as much as 30% of the total on-current. This effect is almost independent of the cross-section, and it depends weakly on the studied channel lengths.

  12. Design of optical reversible logic gates using electro-optic effect of lithium niobate based Mach-Zehnder interferometers.

    PubMed

    Kumar, Santosh; Chanderkanta; Raghuwanshi, Sanjeev Kumar

    2016-07-20

    In recent years reversible logic has come as a promising solution in the optical computing domain. In reversible gates, there is one-to-one mapping between input and output, causing no loss of information. Reversible gates are useful for application in low power complementary metal-oxide semiconductors, with less dissipation, and in quantum computing. These benefits can be utilized by implementing reversible gate structures in the optical domain. In this paper, basic reversible Feynman and Fredkin logic gates using a lithium niobate based Mach-Zehnder interferometer are proposed. The different applications utilizing the proposed structures are also explained in this study. PMID:27463925

  13. Controlled ambient and temperature treatment of InGaZnO thin film transistors for improved bias-illumination stress reliability

    SciTech Connect

    Vemuri, Rajitha N. P.; Hasin, Muhammad R.; Alford, T. L.

    2014-03-15

    The failure mechanisms arising from the instability in operation of indium gallium zinc oxide based thin film transistors (TFTs) upon prolonged real application stresses (bias and illumination) have been extensively studied and reported. Positive and negative gate bias conditions, along with high photonic energy wavelengths within visible light spectrum are used as stress conditions. The increased carrier concentration due to photonic excitation of defects within bandgap and ionization of deep level vacancies is compensated by the reduction in off currents under illumination due to the trapping of carriers in the intermetal dielectric. Band lowering at the source-channel junction due to accumulation of negative carriers repelled due to negative gate bias stress further causes high carrier flow into the channel and drives the devices into failure. The defect identification during failure and degradation assisted in proposing suitable low temperature post processing in specific ambients. Reliability tests after specific anneals in oxygen, vacuum, and forming gas ambients confirm the correlation of the defect type with anneal ambient. Annealed TFTs demonstrate high stabilities under illumination stresses and do not fail when subjected to combined stresses that cause failure in as-fabricated TFTs. Oxygen and forming gas anneals are impactful on the reliability and opens an area of study on donor and vacancy behavior in amorphous mixed oxide based TFTs. The subthreshold swing, field-effect mobilities, and off currents provide knowledge on best anneal practices by understanding role of hydrogen and oxygen in vacancy annihilation and transistor switching properties.

  14. Reliability Generalization: "Lapsus Linguae"

    ERIC Educational Resources Information Center

    Smith, Julie M.

    2011-01-01

    This study examines the proposed Reliability Generalization (RG) method for studying reliability. RG employs the application of meta-analytic techniques similar to those used in validity generalization studies to examine reliability coefficients. This study explains why RG does not provide a proper research method for the study of reliability,…

  15. Vertical gating of sketched nanodevices

    NASA Astrophysics Data System (ADS)

    Pai, Yun-Yi; Park, Dong-Wook; Huang, Mengchen; Annadi, Anil; Lee, Hyungwoo; Ma, Zhenqiang; Eom, Chang-Beom; Irvin, Patrick; Levy, Jeremy

    Conductive-atomic force microscope (c-AFM) lithography at the LaAlO3/SrTiO3 interface has enabled the creation of various classes of nanostructures, such as nanoscale transistors, single-electron transistors and has proven to be a promising testbed for mesoscopic physics. To date, these devices have used lithographically-defined side gates, which are limited by leakage currents. To reduce leakage and improve the electric field effect, we have investigated nanostructures with in-situ grown gold top gate. We will discuss designs of logic devices such as inverters, NAND, and NOR gates. In the quantum regime, we compare the performance of in-situ vertical top gates and that of written coplanar side gates with Quantum Dot devices. We gratefully acknowledge financial support from the following agencies and grants: AFOSR (FA9550-­10-­1­-0524(JL), FA9550-­12-­1-­0342(CBE)), NSF (DMR­1124131 (JL, CBE) and DMR­1234096 (CBE)), ONR (N00014-15-1-2847 (JL)).

  16. Electrolyte Gated Transistors based on Solution Processed Mesoporous Tungsten Trioxide Thin Films

    NASA Astrophysics Data System (ADS)

    Santato, Clara; Isik, Dilek; Cicoira, Fabio

    2012-02-01

    Tungsten trioxide (WO3) is an important material for electrochromic displays, gas sensors, and photoelectrochemical cells. Despite intensive research efforts, the charge transport properties of nanostructured WO3 films, as well as of other metal oxide films, are still largely undiscovered. Electrolyte gating provides a powerful platform to study the charge transport properties of nanostructured WO3 films permitting to achieve high charge density regimes. In turn, this opens the possibility to improve the film transport properties for a wide range of applications. Here we report on electrolyte gated transistors making use of WO3 films as the semiconductor and H2SO4(aq) 1M as the gate dielectric. WO3 films, prepared by sol-gel method, were deposited on source and drain patterned ITO substrates. The liquid electrolyte was confined using a PDMS well. Atomic force microscopy and scanning electron microscopy images show a mesoporous film structure where the electrolyte can easily penetrate. The mesoporous structure permits an efficient electrolyte gating compared to bulk WO3 films because of the higher surface available for electrical double layers, which are the underpinning of the electrolyte gating. Upon application of gate bias in the 0-1 V range, with an applied drain voltage ranging between 0-1 V, we were able to tune the conductivity in the WO3 transistor channel: electrolyte gating of the films led to clear transistor behaviour. Electrolyte gating of WO3 electrochromism is presently under investigation.

  17. Gate bias stress effects due to polymer gate dielectrics in organic thin-film transistors

    NASA Astrophysics Data System (ADS)

    Ng, Tse Nga; Daniel, Jürgen H.; Sambandan, Sanjiv; Arias, Ana-Claudia; Chabinyc, Michael L.; Street, Robert A.

    2008-02-01

    The operational stability of organic thin-film transistors (OTFTs) comprising bilayer polymer dielectric of poly(methylsilsesquioxane) (pMSSQ) and either the epoxy resin SU-8 or poly(4-vinyl phenol) was examined. Although not in direct contact with the semiconductor materials, the bottom dielectric layer did affect OTFT stability through water ion movement or charge injection inside the bottom dielectrics. In the comparison between our best polymer dielectric pMSSQ/SU-8 to the silicon oxide dielectric, the result emphasized that, at equal initial charge concentration, polymer dielectrics did not alleviate threshold-voltage shift but did maintain more stable current due to the lower gate capacitance than silicon oxide.

  18. Alstom Francis Turbine Ring Gates: from Retrofitting to Commissioning

    NASA Astrophysics Data System (ADS)

    A, Nguyen P.; G, Labrecque; M-O, Thibault; M, Bergeron; A, Steinhilber; D, Havard

    2014-03-01

    The Ring Gate synchronisation system developed by Alstom is new and patented. It uses hydraulic cylinders connected in pairs by a serial connection. The new hydraulic synchronisation system, when compared to the previous mechanical synchronisation system, has several advantages. It is a compact design; it reduces the number of mechanical components as well as maintenance costs. The new system maintains the Ring Gates robustness. The new approach is an evolution from mechanical to hydraulic synchronization assisted by electronic control. The new synchronization system eliminates several mechanical components that used to add wear and friction and which are usually difficult to adjust during maintenance. Tension chains and sprockets and associated controls are eliminated. Through the position sensors, the redundancy of the ring gate synchronization system makes it predictable and reliable. The electronic control compensates for any variation in operation, for example a leak in the hydraulic system. An emergency closing is possible without the electronic control system due to the stiffness of hydraulic serial connection in the hydraulic cylinder pairs. The Ring Gate can work safely against uneven loads and frictions. The development will be reviewed and its application discussed through commissioning results.

  19. Positive-bias gate-controlled metal–insulator transition in ultrathin VO2 channels with TiO2 gate dielectrics

    PubMed Central

    Yajima, Takeaki; Nishimura, Tomonori; Toriumi, Akira

    2015-01-01

    The next generation of electronics is likely to incorporate various functional materials, including those exhibiting ferroelectricity, ferromagnetism and metal–insulator transitions. Metal–insulator transitions can be controlled by electron doping, and so incorporating such a material in transistor channels will enable us to significantly modulate transistor current. However, such gate-controlled metal–insulator transitions have been challenging because of the limited number of electrons accumulated by gate dielectrics, or possible electrochemical reaction in ionic liquid gate. Here we achieve a positive-bias gate-controlled metal–insulator transition near the transition temperature. A significant number of electrons were accumulated via a high-permittivity TiO2 gate dielectric with subnanometre equivalent oxide thickness in the inverse-Schottky-gate geometry. An abrupt transition in the VO2 channel is further exploited, leading to a significant current modulation far beyond the capacitive coupling. This solid-state operation enables us to discuss the electrostatic mechanism as well as the collective nature of gate-controlled metal–insulator transitions, paving the pathway for developing functional field effect transistors. PMID:26657761

  20. Long-Term Reliability of a Hard-Switched Boost Power Processing Unit Utilizing SiC Power MOSFETs

    NASA Technical Reports Server (NTRS)

    Ikpe, Stanley A.; Lauenstein, Jean-Marie; Carr, Gregory A.; Hunter, Don; Ludwig, Lawrence L.; Wood, William; Iannello, Christopher J.; Del Castillo, Linda Y.; Fitzpatrick, Fred D.; Mojarradi, Mohammad M.; Chen, Yuan

    2016-01-01

    Silicon carbide (SiC) power devices have demonstrated many performance advantages over their silicon (Si) counterparts. As the inherent material limitations of Si devices are being swiftly realized, wide-band-gap (WBG) materials such as SiC have become increasingly attractive for high power applications. In particular, SiC power metal oxide semiconductor field effect transistors' (MOSFETs) high breakdown field tolerance, superior thermal conductivity and low-resistivity drift regions make these devices an excellent candidate for power dense, low loss, high frequency switching applications in extreme environment conditions. In this paper, a novel power processing unit (PPU) architecture is proposed utilizing commercially available 4H-SiC power MOSFETs from CREE Inc. A multiphase straight boost converter topology is implemented to supply up to 10 kilowatts full-scale. High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) characterization is performed to evaluate the long-term reliability of both the gate oxide and the body diode of the SiC components. Finally, susceptibility of the CREE SiC MOSFETs to damaging effects from heavy-ion radiation representative of the on-orbit galactic cosmic ray environment are explored. The results provide the baseline performance metrics of operation as well as demonstrate the feasibility of a hard-switched PPU in harsh environments.

  1. Efficient Toffoli Gate in Circuit Quantum Electrodynamics

    NASA Astrophysics Data System (ADS)

    Reed, Matthew; Dicarlo, Leonardo; Sun, Luyan; Frunzio, Luigi; Schoelkopf, Robert

    2011-03-01

    The fidelity of quantum gates in circuit quantum electrodynamics is typically limited by qubit decoherence. As such, significant improvements can be realized by shortening gate duration. The three-qubit Toffoli gate, also called the controlled-controlled NOT, is an important operation in basic quantum error correction. We report a scheme for a Toffoli gate that exploits interactions with non-computational excited states of transmon qubits which can be executed faster than an equivalent construction using one- and two-qubit gates. The application of this gate to efficient measurement-free quantum error correction will be discussed. Research supported by NSF, NSA, and ARO.

  2. Can There Be Reliability without "Reliability?"

    ERIC Educational Resources Information Center

    Mislevy, Robert J.

    2004-01-01

    An "Educational Researcher" article by Pamela Moss (1994) asks the title question, "Can there be validity without reliability?" Yes, she answers, if by reliability one means "consistency among independent observations intended as interchangeable" (Moss, 1994, p. 7), quantified by internal consistency indices such as KR-20 coefficients and…

  3. HELIOS Critical Design Review: Reliability

    NASA Technical Reports Server (NTRS)

    Benoehr, H. C.; Herholz, J.; Prem, H.; Mann, D.; Reichert, L.; Rupp, W.; Campbell, D.; Boettger, H.; Zerwes, G.; Kurvin, C.

    1972-01-01

    This paper presents Helios Critical Design Review Reliability form October 16-20, 1972. The topics include: 1) Reliability Requirement; 2) Reliability Apportionment; 3) Failure Rates; 4) Reliability Assessment; 5) Reliability Block Diagram; and 5) Reliability Information Sheet.

  4. CROSS-DISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Growth Related Carrier Mobility Enhancement of Pentacene Thin-Film Transistors with High-k Oxide Gate Dielectric

    NASA Astrophysics Data System (ADS)

    Yu, Ai-Fang; Qi, Qiong; Jiang, Peng; Jiang, Chao

    2009-07-01

    Carrier mobility enhancement from 0.09 to 0.59 cm2/Vs is achieved for pentacene-based thin-film transistors (TFTs) by modifying the HfO2 gate dielectric with a polystyrene (PS) thin film. The improvement of the transistor's performance is found to be strongly related to the initial film morphologies of pentacene on the dielectrics. In contrast to the three-dimensional island-like growth mode on the HfO2 surface, the Stranski-Krastanov growth mode on the smooth and nonpolar PS/HfO2 surface is believed to be the origin of the excellent carrier mobility of the TFTs. A large well-connected first monolayer with fewer boundaries is formed via the Stranski-Krastanov growth mode, which facilitates a charge transport parallel to the substrate and promotes higher carrier mobility.

  5. Red-green-blue light sensitivity of oxide nanowire transistors for transparent display applications

    NASA Astrophysics Data System (ADS)

    Lee, Sumi; Kim, Seongmin; Janes, David B.; Meyyappan, M.; Ju, Sanghyun

    2013-01-01

    In this study, the sensitivity of oxide nanowire transistors under red (R, 470 nm), green (G, 530 nm), and blue (B, 625 nm) light illumination was investigated. As the wavelength of light illuminating the nanowire channel region became shorter, a negative shift of threshold voltage, degradation of subthreshold slope, and increase of on-current were observed. This phenomenon can be explained in terms of photo-induced holes, creating interfacial traps between the gate dielectric and nanowire channel or reacting with oxygen ions on the surface of the nanowires. Thus, the attempt to minimize characteristic changes due to all RGB light sources was performed by employing ultraviolet-ozone treatment and passivation process. As a result, we could successfully fabricate oxide nanowire transistors providing high optical reliability which has broadened the possibilities for applying it to transparent and/or flexible pixel operation circuitry for displays with high optical reliability.

  6. Effect of hot carrier stress on RF reliability of 40 nm PMOSFETs with and without SiGe source/drain

    NASA Astrophysics Data System (ADS)

    Tang, Mao-Chyuan; Fang, Yean-Kuen; Wei, Sun-Chin; Chen, David C.; Yeh, Chune-Sin; Huang-Lu, Shiang

    2008-11-01

    For the first time, the effect of hot carrier stress (HCS) on RF reliability of 40 nm PMOSFETs with and without SiGe source/drain (S/D) was studied in detail. After HCS, the extra SiGe S/D mechanical stress deteriorated the hot carrier reliability more by inducing more defects at the interface between the gate oxide and the extension of S/D. However, the SiGe S/D strain did not change the worst HCS condition and the dependence of fT degradation. The fT is still dominated by gm only, even though the Cgs and Cgd have been changed by the SiGe S/D strain.

  7. Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

    PubMed

    Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

    2016-06-15

    Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s). PMID:27193379

  8. Glutamate-gated Chloride Channels*

    PubMed Central

    Wolstenholme, Adrian J.

    2012-01-01

    Glutamate-gated chloride channels (GluCls) are found only in protostome invertebrate phyla but are closely related to mammalian glycine receptors. They have a number of roles in these animals, controlling locomotion and feeding and mediating sensory inputs into behavior. In nematodes and arthropods, they are targeted by the macrocyclic lactone family of anthelmintics and pesticides, making the GluCls of considerable medical and economic importance. Recently, the three-dimensional structure of a GluCl was solved, the first for any eukaryotic ligand-gated anion channel, revealing a macrocyclic lactone-binding site between the channel domains of adjacent subunits. This minireview will highlight some unique features of the GluCls and illustrate their contribution to our knowledge of the entire Cys loop ligand-gated ion channel superfamily. PMID:23038250

  9. Quantum gates by periodic driving

    PubMed Central

    Shi, Z. C.; Wang, W.; Yi, X. X.

    2016-01-01

    Topological quantum computation has been extensively studied in the past decades due to its robustness against decoherence. One way to realize the topological quantum computation is by adiabatic evolutions—it requires relatively long time to complete a gate, so the speed of quantum computation slows down. In this work, we present a method to realize single qubit quantum gates by periodic driving. Compared to adiabatic evolution, the single qubit gates can be realized at a fixed time much shorter than that by adiabatic evolution. The driving fields can be sinusoidal or square-well field. With the sinusoidal driving field, we derive an expression for the total operation time in the high-frequency limit, and an exact analytical expression for the evolution operator without any approximations is given for the square well driving. This study suggests that the period driving could provide us with a new direction in regulations of the operation time in topological quantum computation. PMID:26911900

  10. Charge Pumping Profiling Technique for the Evaluation of Plasma-Charging-Enhanced Hot-Carrier Effect in Short-N-Channel Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Chen, Shang-Jr; Chung, Steve Shao-Shiun; Lin, Horng-Chih

    2002-07-01

    Plasma etching of poly-silicon in a metal-oxide-semiconductor field-effect transistor (MOSFET) during the gate definition process induces edge damage at the gate-drain overlap edge. This edge damage will be further enhanced by the antenna effect and cause a more serious hot-carrier (HC) effect, particularly in short-channel devices. We call this phenomenon the plasma-charging-enhanced HC effect. In this paper, this plasma-charging-enhanced HC effect is evaluated by the charge pumping (CP) profiling technique, in which the enhanced damage at the gate-drain overlap gate oxide region can be identified. A three-phase plasma damage mechanism is then proposed to explain the observed effect. According to experimental results, it was shown that the interface traps generated at the gate-drain overlap edge are mainly attributed to the plasma-charging-enhanced HC effect. These interface traps (Nit) become the dominant mechanism of the drain current (ID) degradation, which increases with a reducing channel length (L). Again, the enhanced HC-effect-induced-degradation will dominate the device reliability under long-term operations.

  11. Reading Gate Positions with a Smartphone

    NASA Astrophysics Data System (ADS)

    van Overloop, Peter-Jules; Hut, Rolf

    2015-04-01

    Worldwide many flow gates are built in water networks in order to direct water to appropriate locations. Most of these gates are adjusted manually by field operators of water management organizations and it is often centrally not known what the new position of the gate is. This makes centralized management of the entire water network difficult. One of the reasons why the measurement of the gate position is usually not executed, is that for certain gates it is not easy to do such a reading. Tilting weirs or radial gates are examples where operators need special equipment (measuring rod and long level) to determine the position and it could even be a risky procedure. Another issue is that once the measurement is done, the value is jotted down in a notebook and later, at the office, entered in a computer system. So the entire monitoring procedure is not real-time and prone to human errors. A new way of monitoring gate positions is introduced. It consists of a level that is attached to the gate and an app with which a picture can be taken from the level. Using dedicated pattern recognition algorithms, the gate position can be read by using the angle of the level versus reference points on the gate, the radius of that gate and the absolute level of the joint around which the gate turn. The method uses gps-localization of the smartphone to store the gate position in the right location in the central database.

  12. Localizing a gate in CFTR.

    PubMed

    Gao, Xiaolong; Hwang, Tzyh-Chang

    2015-02-24

    Experimental and computational studies have painted a picture of the chloride permeation pathway in cystic fibrosis transmembrane conductance regulator (CFTR) as a short narrow tunnel flanked by wider inner and outer vestibules. Although these studies also identified a number of transmembrane segments (TMs) as pore-lining, the exact location of CFTR's gate(s) remains unknown. Here, using a channel-permeant probe, [Au(CN)2](-), we provide evidence that CFTR bears a gate that coincides with the predicted narrow section of the pore defined as residues 338-341 in TM6. Specifically, cysteines introduced cytoplasmic to the narrow region (i.e., positions 344 in TM6 and 1148 in TM12) can be modified by intracellular [Au(CN)2](-) in both open and closed states, corroborating the conclusion that the internal vestibule does not harbor a gate. However, cysteines engineered to positions external to the presumed narrow region (e.g., 334, 335, and 337 in TM6) are all nonreactive toward cytoplasmic [Au(CN)2](-) in the absence of ATP, whereas they can be better accessed by extracellular [Au(CN)2](-) when the open probability is markedly reduced by introducing a second mutation, G1349D. As [Au(CN)2](-) and chloride ions share the same permeation pathway, these results imply a gate is situated between amino acid residues 337 and 344 along TM6, encompassing the very segment that may also serve as the selectivity filter for CFTR. The unique position of a gate in the middle of the ion translocation pathway diverges from those seen in ATP-binding cassette (ABC) transporters and thus distinguishes CFTR from other members of the ABC transporter family. PMID:25675504

  13. Localizing a gate in CFTR

    PubMed Central

    Gao, Xiaolong; Hwang, Tzyh-Chang

    2015-01-01

    Experimental and computational studies have painted a picture of the chloride permeation pathway in cystic fibrosis transmembrane conductance regulator (CFTR) as a short narrow tunnel flanked by wider inner and outer vestibules. Although these studies also identified a number of transmembrane segments (TMs) as pore-lining, the exact location of CFTR’s gate(s) remains unknown. Here, using a channel-permeant probe, [Au(CN)2]−, we provide evidence that CFTR bears a gate that coincides with the predicted narrow section of the pore defined as residues 338–341 in TM6. Specifically, cysteines introduced cytoplasmic to the narrow region (i.e., positions 344 in TM6 and 1148 in TM12) can be modified by intracellular [Au(CN)2]− in both open and closed states, corroborating the conclusion that the internal vestibule does not harbor a gate. However, cysteines engineered to positions external to the presumed narrow region (e.g., 334, 335, and 337 in TM6) are all nonreactive toward cytoplasmic [Au(CN)2]− in the absence of ATP, whereas they can be better accessed by extracellular [Au(CN)2]− when the open probability is markedly reduced by introducing a second mutation, G1349D. As [Au(CN)2]− and chloride ions share the same permeation pathway, these results imply a gate is situated between amino acid residues 337 and 344 along TM6, encompassing the very segment that may also serve as the selectivity filter for CFTR. The unique position of a gate in the middle of the ion translocation pathway diverges from those seen in ATP-binding cassette (ABC) transporters and thus distinguishes CFTR from other members of the ABC transporter family. PMID:25675504

  14. Dual gated nuclear cardiac images

    SciTech Connect

    Zubal, I.G.; Bennett, G.W.; Bizais, Y.; Brill, A.B.

    1984-02-01

    A data acquisition system has been developed to collect camera events simultaneously with continually digitized electrocardiograph signals and respiratory flow measurements. Software processing of the list mode data creates more precisely gated cardiac frames. Additionally, motion blur due to heart movement during breathing is reduced by selecting events within a specific respiratory phase. Thallium myocardium images of a healthy volunteer show increased definition. This technique of combined cardiac and respiratory gating has the potential of improving the detectability of small lesions, and the characterization of cardiac wall motion.

  15. Biophysics of BK Channel Gating.

    PubMed

    Pantazis, A; Olcese, R

    2016-01-01

    BK channels are universal regulators of cell excitability, given their exceptional unitary conductance selective for K(+), joint activation mechanism by membrane depolarization and intracellular [Ca(2+)] elevation, and broad expression pattern. In this chapter, we discuss the structural basis and operational principles of their activation, or gating, by membrane potential and calcium. We also discuss how the two activation mechanisms interact to culminate in channel opening. As members of the voltage-gated potassium channel superfamily, BK channels are discussed in the context of archetypal family members, in terms of similarities that help us understand their function, but also seminal structural and biophysical differences that confer unique functional properties. PMID:27238260

  16. HELLS GATE ROADLESS AREA, ARIZONA.

    USGS Publications Warehouse

    Conway, Clay M.; McColly, Robert A.

    1984-01-01

    Although no mineral-resource potential was identified in the Hells Gate Roadless Area during mineral surveys, the area is largely underlain by a regionally extensive Proterozoic granite-rhyolite complex which is tin-bearing. The geologic setting precludes the occurrence of fossil fuel resources and no other energy resources were identified. The potential for tin and associated metals in the Hells Gate Roadless Area and the region cannot be fully evaluated at this point. The granophyre and the upper part of the granite pluton along the northwestern margin of the area should be explored.

  17. Analysis of nickel-cadmium battery reliability data containing zero failures

    NASA Technical Reports Server (NTRS)

    Denson, William K.; Klein, Glenn C.

    1992-01-01

    An analysis of reliability data on Nickel-Cadmium (NiCd) batteries (for use in spacecraft) is presented. The data were collected by Gates Aerospace and represent a substantial reliability database. The data were taken from the performance of 183 satellites which were in operation from between .1 and 22 years, for a total of 278 million cell-hours of operation.

  18. SiC Power MOSFET with Improved Gate Dielectric

    SciTech Connect

    Sbrockey, Nick M; Tompa, Gary S; Spencer, Michael G; Chandrashekhar, Chandra MVS

    2010-08-23

    In this STTR program, Structured Materials Industries (SMI), and Cornell University are developing novel gate oxide technology, as a critical enabler for silicon carbide (SiC) devices. SiC is a wide bandgap semiconductor material, with many unique properties. SiC devices are ideally suited for high-power, highvoltage, high-frequency, high-temperature and radiation resistant applications. The DOE has expressed interest in developing SiC devices for use in extreme environments, in high energy physics applications and in power generation. The development of transistors based on the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure will be critical to these applications.

  19. Interface engineering with an MOCVD grown ZnO interface passivation layer for ZrO 2-GaAs metal-oxide-semiconductor devices

    NASA Astrophysics Data System (ADS)

    Kundu, Souvik; Shripathi, T.; Banerji, P.

    2011-12-01

    This work deals with the fabrication of a GaAs metal-oxide-semiconductor device with an unpinned interface environment. An ultrathin ( ˜2 nm) interface passivation layer (IPL) of ZnO on GaAs was grown by metal organic chemical vapor deposition to control the interface trap densities and to prevent the Fermi level pinning before high-k deposition. X-ray photoelectron spectroscopy and high resolution transmission electron microscopy results show that an ultra thin layer of ZnO IPL can effectively suppress the oxides formation and minimize the Fermi level pinning at the interface between the GaAs and ZrO 2. By incorporating ZnO IPL, GaAs MOS devices with improved capacitance-voltage and reduced gate leakage current were achieved. The charge trapping behavior of the ZrO 2/ZnO gate stack under constant voltage stressing exhibits an improved interface quality and high dielectric reliability.

  20. Structured back gates for high-mobility two-dimensional electron systems using oxygen ion implantation

    NASA Astrophysics Data System (ADS)

    Berl, M.; Tiemann, L.; Dietsche, W.; Karl, H.; Wegscheider, W.

    2016-03-01

    We present a reliable method to obtain patterned back gates compatible with high mobility molecular beam epitaxy via local oxygen ion implantation that suppresses the conductivity of an 80 nm thick silicon doped GaAs epilayer. Our technique was optimized to circumvent several constraints of other gating and implantation methods. The ion-implanted surface remains atomically flat which allows unperturbed epitaxial overgrowth. We demonstrate the practical application of this gating technique by using magneto-transport spectroscopy on a two-dimensional electron system (2DES) with a mobility exceeding 20 × 106 cm2/V s. The back gate was spatially separated from the Ohmic contacts of the 2DES, thus minimizing the probability for electrical shorts or leakage and permitting simple contacting schemes.