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Sample records for hf-based high-k gate

  1. Interface engineering and chemistry of Hf-based high-k dielectrics on III-V substrates

    NASA Astrophysics Data System (ADS)

    He, Gang; Chen, Xiaoshuang; Sun, Zhaoqi

    2013-03-01

    Recently, III-V materials have been extensively studied as potential candidates for post-Si complementary metal-oxide-semiconductor (CMOS) channel materials. The main obstacle to implement III-V compound semiconductors for CMOS applications is the lack of high quality and thermodynamically stable insulators with low interface trap densities. Due to their excellent thermal stability and relatively high dielectric constants, Hf-based high-k gate dielectrics have been recently highlighted as the most promising high-k dielectrics for III-V-based devices. This paper provides an overview of interface engineering and chemistry of Hf-based high-k dielectrics on III-V substrates. We begin with a survey of methods developed for generating Hf-based high-k gate dielectrics. To address the impact of these hafnium based materials, their interfaces with GaAs as well as a variety of semiconductors are discussed. After that, the integration issues are highlighted, including the development of high-k deposition without Fermi level pinning, surface passivation and interface state, and integration of novel device structure with Si technology. Finally, we conclude this review with the perspectives and outlook on the future developments in this area. This review explores the possible influences of research breakthroughs of Hf-based gate dielectrics on the current and future applications for nano-MOSFET devices.

  2. Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs

    NASA Astrophysics Data System (ADS)

    Dentoni Litta, E.; Hellström, P.-E.; Östling, M.

    2015-06-01

    High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

  3. Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

    NASA Astrophysics Data System (ADS)

    Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

    2013-06-01

    In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

  4. A new analytical threshold voltage model for symmetrical double-gate MOSFETs with high- k gate dielectrics

    NASA Astrophysics Data System (ADS)

    Chiang, T. K.; Chen, M. L.

    2007-03-01

    Based on the fully two-dimensional (2D) Poisson's solution in both silicon film and insulator layer, a compact and analytical threshold voltage model, which accounts for the fringing field effect of the short channel symmetrical double-gate (SDG) MOSFETs, has been developed. Exploiting the new model, a concerned analysis combining FIBL-enhanced short-channel effects and high- k gate dielectrics assess their overall impact on SDG MOSFET's scaling. It is found that for the same equivalent oxide thickness, the gate insulator with high- k dielectric constant which keeps a great characteristic length allows less design space than SiO 2 to sustain the same FIBL induced threshold voltage degradation.

  5. Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

    NASA Astrophysics Data System (ADS)

    Jayanti, Srikant

    Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG

  6. Divergent dielectric characteristics in cascaded high-K gate stacks with reverse gradient bandgap structures

    NASA Astrophysics Data System (ADS)

    Tsai, Meng-Chen; Cheng, Po-Hsien; Lee, Min-Hung; Lin, Hsin-Chih; Chen, Miin-Jang

    2016-07-01

    The characteristics of cascaded high-K gate stacks with reverse dielectric sequence, TiO2/ZrO2/Al2O3 and Al2O3/ZrO2/ TiO2, on the Si substrate were investigated. The reverse sequence with different gradient bandgap structure gives rise to distinct conduction pathways, resulting in significant divergence of the leakage current density (J g) and the capacitance equivalent thickness (CET). The trapping sites in the high-permittivity TiO2 layer dominate the leakage current paths and strongly impact the conductance and the capacitance of the cascaded high-K gate stacks. Thus, a low CET of 1.05 nm and a low J g of ∼5  ×  10–4 A cm‑2 were achieved due to effective suppression of the leakage current through the traps of TiO2 in the cascaded TiO2/ZrO2/Al2O3 gate stack. In addition, the TiO2 layer gets crystallized in the cascaded TiO2/ZrO2/Al2O3 structure to achieve a higher capacitance because of the intermixing between TiO2 and ZrO2 due to the different reactivity of the precursors for Ti and Zr. This study demonstrates a way to effectively incorporate the high permittivity and low-bandgap materials, such as TiO2, into high-K gate stacks, to further improve device scaling.

  7. Analysis of high-k spacer on symmetric underlap DG-MOSFET with Gate Stack architecture

    NASA Astrophysics Data System (ADS)

    Das, Rahul; Chakraborty, Shramana; Dasgupta, Arpan; Dutta, Arka; Kundu, Atanu; Sarkar, Chandan K.

    2016-09-01

    This paper shows the systematic study of underlap double gate (U-DG) NMOSFETs with Gate Stack (GS) under the influence of high-k spacers. In highly scaled devices, underlap is used at the Source and Drain side so as to reduce the short channel effects (SCE's), however, it significantly reduces the on current due to the increased channel resistance. To overcome these drawbacks, the use of high-k spacers is projected as one of the remedies. In this paper, the analog performance of the devices is studied on the basis of parameters like transconductance (gm), transconductance generation factor (gm/Id) and intrinsic gain (gmro). The RF performance is analyzed on the merits of intrinsic capacitance (Cgd, Cgs), resistance (Rgd, Rgs), transport delay (τm), inductance (Lsd), cutoff frequency (fT), and the maximum frequency of oscillation (fmax). The circuit performance of the devices are studied by implementing the device as the driver MOSFET in a Single Stage Common Source Amplifier. The Gain Bandwidth Product (GBW) has been analyzed from the frequency response of the circuit.

  8. Lifetime of high-k gate dielectrics and analogy with strength of quasibrittle structures

    NASA Astrophysics Data System (ADS)

    Le, Jia-Liang; Bažant, Zdeněk P.; Bazant, Martin Z.

    2009-11-01

    The two-parameter Weibull distribution has been widely adopted to model the lifetime statistics of dielectric breakdown under constant voltage, but recent lifetime testing for high-k gate dielectrics has revealed a systematic departure from Weibull statistics, evocative of lifetime statistics for small quasibrittle structures under constant stress. Here we identify a mathematical analogy between the dielectric breakdown in semiconductor electronic devices and the finite-size weakest-link model for mechanical strength of quasibrittle structures and adapt a recently developed probabilistic theory of structural failure to gate dielectrics. Although the theory is general and does not rely on any particular model of local breakdown events, we show how its key assumptions can be derived from the classical dielectric breakdown model, which predicts certain scaling exponents. The theory accurately fits the observed kinked shape of the histograms of lifetime plotted in Weibull scale, as well as the measured dependence of the median lifetime on the gate area (or size), including its deviation from a power law. The theory also predicts that the Weibull modulus for breakdown lifetime increases in proportion to the thickness of the oxide layer and suggests new ideas for more effective reliability testing.

  9. Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

    NASA Astrophysics Data System (ADS)

    Charles Pravin, J.; Nirmal, D.; Prajoon, P.; Ajayan, J.

    2016-09-01

    This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO2 than SiO2 in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, ION/IOFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO2, DIBL shows a reduction of 61.5% over SiO2. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO2 when compared to SiO2. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO2 based device. From the analysis, it is found that HfO2 will be a better alternative for the future nanoscale device.

  10. Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions.

    PubMed

    Wu, Jun; Babadi, Aein Shiri; Jacobsson, Daniel; Colvin, Jovana; Yngman, Sofie; Timm, Rainer; Lind, Erik; Wernersson, Lars-Erik

    2016-04-13

    In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (Dit) profile of the vertical wrap-gated InAs/high-k nanowire semiconductor-dielectric gate stack. We also perform the first detailed characterization and optimization of the influence of the in situ doping supplied during the nanowire epitaxial growth on the sequential transistor gate stack quality. Results show that the intrinsic nanowire channels have a significant reduction in Dit as compared to planar references. It is also found that introducing tetraethyltin (TESn) doping during nanowire growth severely degrades the Dit profile. By adopting a high temperature, low V/III ratio tailored growth scheme, the influence of doping is minimized. Finally, characterization using a unique frequency behavior of the nanowire capacitance-voltage (C-V) characteristics reveals a change of the dopant incorporation mechanism as the growth condition is changed. PMID:26978479

  11. A high-k ferroelectric relaxor terpolymer as a gate dielectric for orgnaic thin film transistors

    SciTech Connect

    Wu, Shan; Shao, Ming; Burlingame, Quinn; Chen, Xiangzhong; Lin, Minren; Xiao, Kai; Zhang, Qiming

    2013-01-01

    Poly(vinylidenefluoride-trifluoroethylene-chlorofluoroethylene) (P(VDF-TrFE-CFE)) is a ferroelectric terpolymer relaxor with a static dielectric constant of 50, which was developed using defect modification to eliminate remnant polarization in the normal ferroelectric PVDF. In this work, this solution processable terpolymer was used as the gate insulator in bottom gated organic thin-film transistors with a pentacene semiconductor layer. Due to the high dielectric constant of P(VDF-TrFE- CFE), a large capacitive coupling between the gate and channel can be achieved which causes a high charge concentration at the interface of the semiconductor and dielectric layers. In this device, an on/ off ratio of 104 and a low minimum operation gate voltage (5-10 V) were attained

  12. Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET

    NASA Astrophysics Data System (ADS)

    Sharma, Aniruddh; Jain, Arushi; Pratap, Yogesh; Gupta, R. S.

    2016-09-01

    In this paper, the impact of asymmetric gate stack architecture using a combination of vacuum and high-k dielectrics on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET has been investigated. A comparative evaluation of short channel effects (SCEs) for various device structures has also been carried out with figure of merit (FOM) metrics such as electric field, electron temperature, drain current (Ids), and drain induced barrier lowering (DIBL). A two-dimensional analytical model has been developed for the asymmetric architecture using Poisson's equation in cylindrical coordinates assuming a parabolic potential profile. It is observed that the asymmetric gate stack device demonstrates effectiveness in suppressing hot carrier degradation and short channel effects along with improving the current drivability of the device as compared to the other device configurations. The analytical results have been verified with the simulated data obtained from ATLAS 3-D device simulator.

  13. Hard X-ray photoemission experiments on novel Ge-based metal gate/high-k stacks

    NASA Astrophysics Data System (ADS)

    Rubio-Zuazo, J.; Martinez, E.; Batude, P.; Clavelier, L.; Soria, F.; Chabli, A.; Castro, G. R.

    2007-09-01

    The scaling of CMOS devices makes mandatory the study of new materials to overcome the physical limitations of the Si technology. Germanium is a good candidate to replace silicon for the channel to improve the carrier mobility. High-K dielectrics such as HfO2 are investigated to replace the gate oxide (SiO2) to decrease both leakage currents and EOT. For the gate electrode, it is also crucial to move from poly-silicon to a metal gate like TiN to adjust work function and to suppress poly-depletion in order to decrease EOT. However, to reach optimal device performances, both the Ge/high-K and high-K/TiN interfaces need to be optimized. In order to passive and prevent Ge oxidation we have deposited a very thin Si interlayer prior to the high-k growth. A thin Si layer (Si capping) is epitaxially grown on Ge and then partially oxidized before high-k deposition. The exact control of the Si capping layer is of major importance. It must be enough thick to prevent germanium oxidation when the partial oxidation of Si is realized and as low as possible in order to keep the benefit of the better transport properties in germanium. In this contribution, we present non-destructive chemical and concentration profile of both critical buried interfaces by mean of Hard X-ray Photoelectron Spectroscopy (HAXPES) of a Ge/Si/SiO2/HfO2/TiN stack, with thickness of 2500, 0.9, 0.5, 4 and 4 nm, respectively. Experiments are performed at the SpLine HAXPES station of the ESRF equipped with a novel photoemission set-up in combination with surface X-ray diffraction (SXRD). The profiles obtained clearly show that the Si interlayer prevents the Ge oxidation and the presence of a new Hf state which is related to an interface chemical shift. Our results demonstrate the excellent capability of HAXPES to study buried interfaces.

  14. Band Offsets of a Ruthenium Gate on Ultrathin High-k Oxide Films on Silicon

    SciTech Connect

    Rangan, S.; Bersch, W; Bartynski, R; Garfunkel, E; Vescovo, E

    2009-01-01

    Valence-band and conduction-band edges of ultrathin oxides and their shifts upon sequential metallization with ruthenium have been measured using synchrotron-radiation-excited x-ray, ultraviolet, and inverse photoemissions. From these techniques, the offsets between the valence-band and conduction-band edges of the oxides, and the ruthenium metal gate Fermi edge have been directly measured. In addition the core levels of the oxides and the ruthenium have been characterized. Upon deposition, Ru remains metallic and no chemical alteration of the underlying oxide gates, or interfacial SiO{sub 2} in the case of the high-? thin films, can be detected. However a clear shift of the band edges is measured for all samples due to the creation of an interface dipole at the ruthenium-oxide interface. Using the energy gap, the electron affinity of the oxides, and the ruthenium work function that have been directly measured on these samples, the experimental band offsets are compared to those predicted by the induced gap states model.

  15. Cross-linking high-k fluoropolymer gate dielectrics enhances the charge mobility in rubrene field effect transistors

    NASA Astrophysics Data System (ADS)

    Adhikari, Jwala; Gadinski, Matthew; Wang, Qing; Gomez, Enrique

    2015-03-01

    Polymer dielectrics are promising materials where the chemical flexibility enables gate insulators with desired properties. For example, polar groups can be introduced to enhance the dielectric constant, although fluctuations in chain conformations at the semiconductor-dielectric interface can introduce energetic disorder and limit charge mobilities in thin-film transistors. Here, we demonstrate a photopatternable high-K fluoropolymer, poly(vinylidene fluoride-bromotrifluoroethylene) P(VDF-BTFE), with a dielectric constant between 8 and 11. The bromotrifluoroethylene moiety enables photo-crosslinking and stabilization of gate insulator films while also significantly enhancing the population of trans torsional conformations of the chains. Using rubrene single crystals as the active layer, charge mobilities exceeding 10 cm2/Vs are achieved in thin film transistors with cross-linked P(VDF-BTFE) gate dielectrics. We hypothesize that crosslinking reduces energetic disorder at the dielectric-semiconductor interface by suppressing segmental motion and controlling chain conformations of P(VDF-BTFE), thereby leading to approximately a three-fold enhancement in the charge mobility of rubrene thin-film transistors over devices incorporating uncross-linked dielectrics or silicon oxide. Center for Flexible Electronic, Penn State; The Dow Chemical Company.

  16. Al2O3 nanocrystals embedded in amorphous Lu2O3 high-k gate dielectric for floating gate memory application

    NASA Astrophysics Data System (ADS)

    Yuan, C. L.; Chan, M. Y.; Lee, P. S.; Darmawan, P.; Setiawan, Y.

    2007-04-01

    The integration of nanoparticles has high potential in technological applications and opens up possibilities of the development of new devices. Compared to the conventional floating gate memory, a structure containing nanocrystals embedded in dielectrics shows high potential to produce a memory with high endurance, low operating voltage, fast write-erase speeds and better immunity to soft errors [S. Tiwari, F. Rana, H. Hanafi et al. 1996 Appl.Phys. Lett. 68, 1377]. A significant improvement on data retention [J. J. Lee, X. Wang et al. 2003 Proceedings of the VLSI Technol. Symposium, p33] can be observed when discrete nanodots are used instead of continuous floating gate as charge storage nodes because local defect related leakage can be reduced efficiently. Furthermore, using a high-k dielectric in place of the conventional SiO2 based dielectric, nanodots flash memory is able to achieve significantly improved programming efficiency and data retention [A. Thean and J. -P. Leburton, 2002 IEEE Potentials 21, 35; D. W. Kim, T. Kim and S. K. Banerjee, 2003 IEEE Trans. Electron Devices 50, 1823]. We have recently successfully developed a method to produce nanodots embedded in high-k gate dielectrics [C. L. Yuan, P. Darmawan, Y. Setiawan and P. S. Lee, 2006 Electrochemical and Solid-State Letters 9, F53; C. L. Yuan, P. Darmawan, Y. Setiawan and P. S. Lee, 2006 Europhys. Lett. 74, 177]. In this paper, we fabricated the memory structure of Al2O3 nanocrystals embedded in amorphous Lu2O3 high k dielectric using pulsed laser ablation. The mean size and density of the Al2O3 nanocrystals are estimated to be about 5 nm and 7x1011 cm-2, respectively. Good electrical performances in terms of large memory window and good data retention were observed. Our preparation method is simple, fast and economical.

  17. The understanding on the evolution of stress-induced gate leakage in high-k dielectric metal-oxide-field-effect transistor by random-telegraph-noise measurement

    NASA Astrophysics Data System (ADS)

    Hsieh, E. R.; Chung, Steve S.

    2015-12-01

    The evolution of gate-current leakage path has been observed and depicted by RTN signals on metal-oxide-silicon field effect transistor with high-k gate dielectric. An experimental method based on gate-current random telegraph noise (Ig-RTN) technique was developed to observe the formation of gate-leakage path for the device under certain electrical stress, such as Bias Temperature Instability. The results show that the evolution of gate-current path consists of three stages. In the beginning, only direct-tunnelling gate current and discrete traps inducing Ig-RTN are observed; in the middle stage, interaction between traps and the percolation paths presents a multi-level gate-current variation, and finally two different patterns of the hard or soft breakdown path can be identified. These observations provide us a better understanding of the gate-leakage and its impact on the device reliability.

  18. Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

    NASA Astrophysics Data System (ADS)

    Asahara, Ryohei; Hideshima, Iori; Oka, Hiroshi; Minoura, Yuya; Ogawa, Shingo; Yoshigoe, Akitaka; Teraoka, Yuden; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2015-06-01

    Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlOx) interlayers. A step-by-step in situ procedure by deposition of AlOx and hafnium oxide (HfOx) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO2/AlOx/GeOx/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlOx interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56 nm and very low interface state density of 2.4 × 1011 cm-2eV-1 with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

  19. Low Temperature Deposition of High-k/Metal Gate Stacks on High-Sn Content (Si)GeSn-Alloys.

    PubMed

    Schulte-Braucks, C; von den Driesch, N; Glass, S; Tiedemann, A T; Breuer, U; Besmehn, A; Hartmann, J-M; Ikonic, Z; Zhao, Q T; Mantl, S; Buca, D

    2016-05-25

    (Si)GeSn is an emerging group IV alloy system offering new exciting properties, with great potential for low power electronics due to the fundamental direct band gap and prospects as high mobility material. In this Article, we present a systematic study of HfO2/TaN high-k/metal gate stacks on (Si)GeSn ternary alloys and low temperature processes for large scale integration of Sn based alloys. Our investigations indicate that SiGeSn ternaries show enhanced thermal stability compared to GeSn binaries, allowing the use of the existing Si technology. Despite the multielemental interface and large Sn content of up to 14 atom %, the HfO2/(Si)GeSn capacitors show small frequency dispersion and stretch-out. The formed TaN/HfO2/(Si)GeSn capacitors present a low leakage current of 2 × 10(-8) A/cm(2) at -1 V and a high breakdown field of ∼8 MV/cm. For large Sn content SiGeSn/GeSn direct band gap heterostructures, process temperatures below 350 °C are required for integration. We developed an atomic vapor deposition process for TaN metal gate on HfO2 high-k dielectric and validated it by resistivity as well as temperature and frequency dependent capacitance-voltage measurements of capacitors on SiGeSn and GeSn. The densities of interface traps are deduced to be in the low 10(12) cm(-2) eV(-1) range and do not depend on the Sn-concentration. The new processes developed here are compatible with (Si)GeSn integration in large scale applications. PMID:27149260

  20. Investigation of MOS Interfaces with Atomic-Layer-Deposited High-k Gate Dielectrics on III-V Semiconductors

    NASA Astrophysics Data System (ADS)

    Suri, Rahul

    The purpose of this research work was to investigate the surface passivation methods and metal gate/high-k dielectric gate stacks for metal-oxide-semiconductor devices (MOS) on III-V compound semiconductor materials -- (i) GaAs for future high-speed low-power logic devices and (ii) AlGaN/GaN heterostructure for future high-speed high-power devices. GaAs is a candidate material for high-mobility channel in a NMOS transistor to extend the CMOS scaling up to and beyond the 16-nm technology node. AlGaN/GaN heterostructure is useful in a MOS-high electron mobility transistor (MOS-HEMT) device for providing a high current-carrying two dimensional electron gas (2DEG) channel. The interaction of GaAs surface with atomic layer deposition of high- k dielectrics was investigated to gain fundamental insights into the chemical properties of GaAs surface oxides and high-k/GaAs interface. Electrical characterization of devices was performed to understand the impact of high-k/GaAs interface on MOS device characteristics in order to form a suitable metal/high-k/GaAs gatestack for future high-speed logic and power devices. Reduction of native oxides on GaAs was found to occur during atomic layer deposition (ALD) of high-k dielectrics- HfO2 and Al2O3/HfO 2 nanolaminates on GaAs. Reaction between ALD metal precursor and native oxides on GaAs was identified to be the cause for consumption of native oxides. It was established that the ALD growth temperature has a strong impact on this phenomenon. During post-dielectric annealing the residual arsenic oxides at the interface decomposed leading to an increase in the interfacial gallium oxides. Presence of gallium oxide, Ga2O3 was identified as a cause for observed frequency dispersion in MOS capacitance-voltage curves indicative of a high interface state density. The chemical properties of the AlGaN/GaN heterostructure surface prepared by wet chemical treatment using HCl/HF and NH4OH solutions were investigated and compared. Both HCl and

  1. Understanding the Structure of High-K Gate Oxides - Oral Presentation

    SciTech Connect

    Miranda, Andre

    2015-08-25

    Hafnium Oxide (HfO2) amorphous thin films are being used as gate oxides in transistors because of their high dielectric constant (κ) over Silicon Dioxide. The present study looks to find the atomic structure of HfO2 thin films which hasn’t been done with the technique of this study. In this study, two HfO2 samples were studied. One sample was made with thermal atomic layer deposition (ALD) on top of a Chromium and Gold layer on a silicon wafer. The second sample was made with plasma ALD on top of a Chromium and Gold layer on a Silicon wafer. Both films were deposited at a thickness of 50nm. To obtain atomic structure information, Grazing Incidence X-ray diffraction (GIXRD) was carried out on the HfO2 samples. Because of this, absorption, footprint, polarization, and dead time corrections were applied to the scattering intensity data collected. The scattering curves displayed a difference in structure between the ALD processes. The plasma ALD sample showed the broad peak characteristic of an amorphous structure whereas the thermal ALD sample showed an amorphous structure with characteristics of crystalline materials. This appears to suggest that the thermal process results in a mostly amorphous material with crystallites within. Further, the scattering intensity data was used to calculate a pair distribution function (PDF) to show more atomic structure. The PDF showed atom distances in the plasma ALD sample had structure up to 10 Å, while the thermal ALD sample showed the same structure below 10 Å. This structure that shows up below 10 Å matches the bond distances of HfO2 published in literature. The PDF for the thermal ALD sample also showed peaks up to 20 Å, suggesting repeating atomic spacing outside the HfO2 molecule in the sample. This appears to suggest that there is some crystalline structure within the thermal ALD sample.

  2. A quantum mechanical treatment of low frequency noise in high-K NMOS transistors with ultra-thin gate dielectrics

    NASA Astrophysics Data System (ADS)

    Zhang, Xiaochen; White, Marvin H.

    2012-12-01

    Our paper presents a quantum mechanical treatment of low-frequency noise in scaled NMOS transistors to extend the "unified" noise model and includes remote Coulomb scattering and surface roughness - the latter is a new consideration in the theory. Our experimental work focuses on scaled NMOS devices with a composite dielectric consisting of a 0.5 nm SiO2 covered with a high-K, 1.6 nm HfO2 with a metal gate. In the past, Coulomb scattering was assumed to arise from trapping centers located at the Si-SiO2 interface; however, this cannot give rise to a 1/f noise spectrum. We model remote Coulomb scattering into the dielectric film as traps in these films easily lie within a tunneling distance from the interface. This approach explains the decrease in the Coulomb scattering parameter (α) as a function of gate voltage. In addition, we introduce surface roughness scattering through fluctuations in the normal electric field due to fluctuations in the free carrier density with a surface scattering parameter (β) proportional to the SPICE surface roughness parameter, θS. Good agreement is obtained between our model and experimental results for both IDS-VGS and the power spectral density, SId, characteristics in very strong inversion region where surface quantization of the 2D subbands is strong.

  3. Temperature- and voltage-dependent trap generation model in high-k metal gate MOS device with percolation simulation

    NASA Astrophysics Data System (ADS)

    Xu, Hao; Yang, Hong; Wang, Yan-Rong; Wang, Wen-Wu; Luo, Wei-Chun; Qi, Lu-Wei; Li, Jun-Feng; Zhao, Chao; Chen, Da-Peng; Ye, Tian-Chun

    2016-08-01

    High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes. The reliability of thin dielectric films becomes a limitation to device manufacturing, especially to the breakdown characteristic. In this work, a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up, and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation. It is found that all degradation factors, such as trap generation rate time exponent m, Weibull slope β and percolation factor s, each could be expressed as a function of trap density time exponent α. Based on the percolation relation and power law lifetime projection, a temperature related trap generation model is proposed. The validity of this model is confirmed by comparing with experiment results. For other device and material conditions, the percolation relation provides a new way to study the relationship between trap generation and lifetime projection. Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601), the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129), and the Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of MicroElectronics of Chinese Academy of Sciences.

  4. Sensing with Advanced Computing Technology: Fin Field-Effect Transistors with High-k Gate Stack on Bulk Silicon.

    PubMed

    Rigante, Sara; Scarbolo, Paolo; Wipf, Mathias; Stoop, Ralph L; Bedner, Kristine; Buitrago, Elizabeth; Bazigos, Antonios; Bouvet, Didier; Calame, Michel; Schönenberger, Christian; Ionescu, Adrian M

    2015-05-26

    Field-effect transistors (FETs) form an established technology for sensing applications. However, recent advancements and use of high-performance multigate metal-oxide semiconductor FETs (double-gate, FinFET, trigate, gate-all-around) in computing technology, instead of bulk MOSFETs, raise new opportunities and questions about the most suitable device architectures for sensing integrated circuits. In this work, we propose pH and ion sensors exploiting FinFETs fabricated on bulk silicon by a fully CMOS compatible approach, as an alternative to the widely investigated silicon nanowires on silicon-on-insulator substrates. We also provide an analytical insight of the concept of sensitivity for the electronic integration of sensors. N-channel fully depleted FinFETs with critical dimensions on the order of 20 nm and HfO2 as a high-k gate insulator have been developed and characterized, showing excellent electrical properties, subthreshold swing, SS ∼ 70 mV/dec, and on-to-off current ratio, Ion/Ioff ∼ 10(6), at room temperature. The same FinFET architecture is validated as a highly sensitive, stable, and reproducible pH sensor. An intrinsic sensitivity close to the Nernst limit, S = 57 mV/pH, is achieved. The pH response in terms of output current reaches Sout = 60%. Long-term measurements have been performed over 4.5 days with a resulting drift in time δVth/δt = 0.10 mV/h. Finally, we show the capability to reproduce experimental data with an extended three-dimensional commercial finite element analysis simulator, in both dry and wet environments, which is useful for future advanced sensor design and optimization. PMID:25817336

  5. Wet Etching of Heat Treated Atomic Layer Chemical Vapor Deposited Zirconium Oxide in HF Based Solutions

    NASA Astrophysics Data System (ADS)

    Balasubramanian, Sriram; Raghavan, Srini

    2008-06-01

    Alternative materials are being considered to replace silicon dioxide as gate dielectric material. Of these, the oxides of hafnium and zirconium show the most promise. However, integrating these new high-k materials into the existing complementary metal-oxide-semiconductor (CMOS) process remains a challenge. One particular area of concern is the wet etching of heat treated high-k dielectrics. In this paper, work done on the wet etching of heat treated atomic layer chemical vapor deposited (ALCVD) zirconium oxide in HF based solutions is presented. It was found that heat treated material, while refractory to wet etching at room temperature, is more amenable to etching at higher temperatures when methane sulfonic acid is added to dilute HF solutions. Selectivity over SiO2 is still a concern.

  6. Effect of atomic-arrangement matching on La2O3/Ge heterostructures for epitaxial high-k-gate-stacks

    NASA Astrophysics Data System (ADS)

    Kanashima, T.; Nohira, H.; Zenitaka, M.; Kajihara, Y.; Yamada, S.; Hamaya, K.

    2015-12-01

    We demonstrate a high-quality La2O3 layer on germanium (Ge) as an epitaxial high-k-gate-insulator, where there is an atomic-arrangement matching condition between La2O3(001) and Ge(111). Structural analyses reveal that (001)-oriented La2O3 layers were grown epitaxially only when we used Ge(111) despite low growth temperatures less than 300 °C. The permittivity (k) of the La2O3 layer is roughly estimated to be ˜19 from capacitance-voltage (C-V) analyses in Au/La2O3/Ge structures after post-metallization-annealing treatments, although the C-V curve indicates the presence of carrier traps near the interface. By using X-ray photoelectron spectroscopy analyses, we find that only Ge-O-La bonds are formed at the interface, and the thickness of the equivalent interfacial Ge oxide layer is much smaller than that of GeO2 monolayer. We discuss a model of the interfacial structure between La2O3 and Ge(111) and comment on the C-V characteristics.

  7. Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

    SciTech Connect

    Asahara, Ryohei; Hideshima, Iori; Oka, Hiroshi; Minoura, Yuya; Hosoi, Takuji Shimura, Takayoshi; Watanabe, Heiji; Ogawa, Shingo; Yoshigoe, Akitaka; Teraoka, Yuden

    2015-06-08

    Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlO{sub x}) interlayers. A step-by-step in situ procedure by deposition of AlO{sub x} and hafnium oxide (HfO{sub x}) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO{sub 2}/AlO{sub x}/GeO{sub x}/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlO{sub x} interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56 nm and very low interface state density of 2.4 × 10{sup 11 }cm{sup −2}eV{sup −1} with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

  8. Mechanisms of temperature dependence of threshold voltage in high-k/metal gate transistors with different TiN thicknesses

    NASA Astrophysics Data System (ADS)

    Nishida, Yukio; Yokoyama, Shin

    2016-04-01

    The change in temperature coefficient of the threshold voltage (=dVth/dT) for poly-Si/TiN/high-k gate insulator metal-oxide-semiconductor field-effect transistors (MOSFETs) was systematically investigated with respect to various TiN thicknesses for both n- and p-channel MOSFETs. With increasing TiN thickness, dVth/dT shifts towards negative values for both n- and p-MOSFETs. A mechanism that changes dVth/dT, depending on TiN thickness is proposed. The main origins are the work function of TiN (ΦTiN) and its temperature coefficient (dΦTiN/dT). These are revealed to change when decreasing the thickness of the TiN layer, because the crystallinity of the TiN layer is degraded for thinner films, which was confirmed by ultraviolet photoelectron spectroscopy (UPS), transmission electron microscopy (TEM) and X-ray diffraction (XRD).

  9. A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric

    NASA Astrophysics Data System (ADS)

    Chaowen, Liu; Jingping, Xu; Lu, Liu; Hanhan, Lu; Yuan, Huang

    2016-02-01

    A threshold-voltage model for a stacked high-k gate dielectric GaAs MOSFET is established by solving a two-dimensional Poisson's equation in channel and considering the short-channel, DIBL and quantum effects. The simulated results are in good agreement with the Silvaco TCAD data, confirming the correctness and validity of the model. Using the model, impacts of structural and physical parameters of the stack high-k gate dielectric on the threshold-voltage shift and the temperature characteristics of the threshold voltage are investigated. The results show that the stacked gate dielectric structure can effectively suppress the fringing-field and DIBL effects and improve the threshold and temperature characteristics, and on the other hand, the influence of temperature on the threshold voltage is overestimated if the quantum effect is ignored. Project supported by the National Natural Science Foundation of China (No. 61176100).

  10. Characterization of high-k gate dielectrics based on hafnium oxide and titanium oxide for CMOS application

    NASA Astrophysics Data System (ADS)

    Lee, Sanghyun

    Hafnium oxide, Titanium oxide, and ternary alloys with nitrided films of each of the above on Silicon and Germanium substrate were investigated in effort of understanding origins and various factors governing intrinsic band edge defects and interface trapped charges which are crucial to implent the high-k dielectrics into CMOS device below Electrical Equivalent Thickness (EOT) < 1nm. Novel design of atomic scale molecule was applied to achieve superb quality guided by the bond constrain theory. Tetrahedral bonding of Hf and Ti oxide in each Hf/Ti Silicon oxynitride gave the chemical stability upon annealing up to 1100°C. From the spectroscopic and electrical measurements, defect states were suppressed by reducing oxygen vacancy related defect states in Hf/Ti Silicon oxynitride. Conduction and valence band edge defect states were detected and reduced by limiting the thickness of HfO2 to 2 nm which is critical length for forming coherent inter-primitive pi bonding between Hf dpi-O ppi orbitals. As a result, Jahn-Teller d state term splittings were suppressed. The application of ultrathin Hf oxide and Hf Si oxynitride films onto Ge (100) and Ge (111) substrates resulted in the elimination of interfacial transition layer by removing Ge-N and possibly Ge-O bond after 800°C anneal. This could afford re-grown Ge epitaxial layer on top of Ge substrate which dramatically reduced the defect states between Hf Silicon oxynitride and Ge substrate. The gate leakage current for Hf Silicon oxynitride was lower than that on Si substrate.

  11. Attainment of dual-band edge work function by using a single metal gate and single high-k dielectric via ion implantation for HP CMOS device

    NASA Astrophysics Data System (ADS)

    Xu, Qiuxia; Xu, G.; Zhou, H.; Zhu, H.; Liu, J.; Wang, Y.; Li, J.; Xiang, J.; Liang, Q.; Wu, H.; Zhong, J.; Xu, M.; Xu, W.; Ma, X.; Wang, X.; Tong, X.; Chen, D.; Yan, J.; Zhao, C.; Ye, T.

    2016-01-01

    Attainment of dual band-edge effective work functions by using a single metal gate and single high k gate dielectric via P/BF2 implantation into a TiN metal gate for HP HKMG CMOS device applications are investigated under a gate-last process flow for the first time. The flat band voltage (VFB) modulations of about -750 mV/570 mV for N-/P-type MOS device with P/BF2 implanted TiN/HfO2/ILSiO2 gate stack are obtained respectively in the experiment range. Suitable low threshold voltages of CMOSFETs are gotten while simultaneously shrinking the EOT. The effects of P/BF2 ion implantation energy, dose and TiN gate thickness on the properties of implanted TiN/HfO2/ILSiO2 gate stack are studied, the possible mechanisms are discussed. This technique has been successfully integrated into the fabrications of aggressively scaled HP HKMG CMOSFETs and 32 CMOS frequency dividers under a gate-last process flow.

  12. Fabrication of high-k/metal-gate MoS2 field-effect transistor by device isolation process utilizing Ar-plasma etching

    NASA Astrophysics Data System (ADS)

    Ninomiya, Naruki; Mori, Takahiro; Uchida, Noriyuki; Watanabe, Eiichiro; Tsuya, Daiju; Moriyama, Satoshi; Tanaka, Masatoshi; Ando, Atsushi

    2015-04-01

    We investigated a device isolation process for MoS2-based devices and fabricated high-k/metal-gate MoS2 MOSFETs. An Ar-ion etching process was utilized for the device isolation process. It circumvents damage in the device channel, as confirmed by Raman spectroscopy. A top-gate MoS2 MOSFET was fabricated with a HfO2 thin film 16 nm thick as the gate insulator. Utilizing capacitance-voltage (C-V) measurements, the capacitance equivalent thickness (CET) was estimated to be 5.36 nm, which indicates that a gate stack with the sufficiently thin insulator was successfully realized. The device exhibited a mobility of 25.3 cm2/(V·s), a subthreshold swing (SS) of 86.0 mV/decade, and an ON/OFF ratio of 107. This satisfactory device performance demonstrates the feasibility of the proposed device isolation process.

  13. Improved n-channel Ge gate stack performance using HfAlO high-k dielectric for various Al concentrations

    NASA Astrophysics Data System (ADS)

    Kothari, Shraddha; Joishi, Chandan; Ghosh, Sayantan; Biswas, Dipankar; Vaidya, Dhirendra; Ganguly, Swaroop; Lodha, Saurabh

    2016-07-01

    We demonstrate improved Ge n-channel gate stack performance versus HfO2 using HfAlO high-k dielectric for a wide (1.5–33%) range of Al% and post-high-k-deposition annealing (PDA) at 400 °C. Addition of Al to HfO2 is shown to mitigate degradation of the GeO2/Ge interface during PDA. HfAlO stacks with an equivalent oxide thickness (EOT) of 8 nm and large Al% exhibit improved transistor mobility (1.8 times higher) and midgap D it (2 times lower), whereas thin (1.9 nm) EOT HfAlO stacks show reduced gate leakage J g (by 10 times) and D it (by 1.5 times) and 1.6 times higher mobility for Al% as low as 1.5% at matched EOT.

  14. Evolution of metal-compound residues on the walls of plasma etching reactor and their effect on critical dimensions of high-k/metal gate

    SciTech Connect

    Iwakoshi, Takehisa; Ono, Tetsuo; Aoyama, Takayuki; Nara, Yasuo; Ohji, Yuzuru

    2009-05-15

    It was found that critical dimensions of high-k/metal gates obey the multivariate linear approximation with the precision of 3{sigma}={+-}0.86 nm, whose explanatory variables are amounts of metal compounds remaining on the plasma reactor walls. To measure their amounts, the authors assumed they are proportional to amounts of atoms sputtered out by Ar plasma and falling onto a Si wafers placed on a wafer stage. In this study, effects of metal compounds of W, Ti, Ta, and Hf, which are used to construct full-metal/high-k gates, were measured. It was found that Ti and Ta compounds dominate the fluctuation of critical dimensions and the dependency of their amount on wafer numbers being etched obeys a simple difference equation. From these results, they can estimate and minimize the fluctuations of critical dimensions in mass fabrications.

  15. Reliability investigation of high-k/metal gate in nMOSFETs by three-dimensional kinetic Monte-Carlo simulation with multiple trap interactions

    NASA Astrophysics Data System (ADS)

    Li, Yun; Jiang, Hai; Lun, Zhiyuan; Wang, Yijiao; Huang, Peng; Hao, Hao; Du, Gang; Zhang, Xing; Liu, Xiaoyan

    2016-04-01

    Degradation behaviors in the high-k/metal gate stacks of nMOSFETs are investigated by three-dimensional (3D) kinetic Monte-Carlo (KMC) simulation with multiple trap coupling. Novel microscopic mechanisms are simultaneously considered in a compound system: (1) trapping/detrapping from/to substrate/gate; (2) trapping/detrapping to other traps; (3) trap generation and recombination. Interacting traps can contribute to random telegraph noise (RTN), bias temperature instability (BTI), and trap-assisted tunneling (TAT). Simulation results show that trap interaction induces higher probability and greater complexity in trapping/detrapping processes and greatly affects the characteristics of RTN and BTI. Different types of trap distribution cause largely different behaviors of RTN, BTI, and TAT. TAT currents caused by multiple trap coupling are sensitive to the gate voltage. Moreover, trap generation and recombination have great effects on the degradation of HfO2-based nMOSFETs under a large stress.

  16. Extremely scaled high-k/In₀.₅₃Ga₀.₄₇As gate stacks with low leakage and low interface trap densities

    SciTech Connect

    Chobpattana, Varistha; Mikheev, Evgeny; Zhang, Jack Y.; Mates, Thomas E.; Stemmer, Susanne

    2014-09-28

    Highly scaled gate dielectric stacks with low leakage and low interface trap densities are required for complementary metal-oxide-semiconductor technology with III-V semiconductor channels. Here, we show that a novel pre-deposition technique, consisting of alternating cycles of nitrogen plasma and tetrakis(dimethylamino)titanium, allows for HfO₂ and ZrO₂ gate stacks with extremely high accumulation capacitance densities of more than 5 μF/cm₂ at 1 MHz, low leakage current, low frequency dispersion, and low midgap interface trap densities (10¹²cm⁻²eV⁻¹range). Using x-ray photoelectron spectroscopy, we show that the interface contains TiO₂ and small quantities of In₂O₃, but no detectable Ga- or As-oxides, or As-As bonding. The results allow for insights into the microscopic mechanisms that control leakage and frequency dispersion in high-k/III-V gate stacks.

  17. Study of Hf-Ti-O Thin Film as High-k Gate Dielectric and Application for ETSOI MOSFETs

    NASA Astrophysics Data System (ADS)

    Chen, Xiaoqiang; Zhao, Hongbin; Xiong, Yuhua; Wei, Feng; Du, Jun; Tang, Zhaoyun; Tang, Bo; Yan, Jiang

    2016-05-01

    This work focused on the metal-oxide-semiconductor (MOS) capacitor and extremely thin silicon-on-insulator (ETSOI) p-type MOS field-effect transistor (pMOSFET) with laminated hafnium and titanium oxide (Hf-Ti-O) thin films as gate dielectric. The electrical behavior of the MOS capacitor shows that the capacitor with Hf-Ti-O gate dielectric has high performance with low equivalent oxide thickness (EOT, ~0.77 nm), small hysteresis (ΔV fb, ~4 mV), and gate current density of 0.33 A/cm2 at V g = V fb - 1 V. The dominant conduction mechanism of the Hf-Ti-O thin film (25°C to 125°C) was Schottky emission at lower gate voltage (-0.8 V to -0.2 V) and Fowler-Nordheim (F-N) tunneling at higher gate voltage (<-0.8 V). An ETSOI pMOSFET with 25 nm gate length (L g) also exhibited good electrical properties with switch ratio of 3.2 × 104, appropriate threshold voltage of -0.16 V, maximum transconductance (G max) of 2.63 mS, drain-induced barrier lowering of 53 mV/V, and subthreshold swing of 65 mV/dec.

  18. Study of Hf-Ti-O Thin Film as High- k Gate Dielectric and Application for ETSOI MOSFETs

    NASA Astrophysics Data System (ADS)

    Chen, Xiaoqiang; Zhao, Hongbin; Xiong, Yuhua; Wei, Feng; Du, Jun; Tang, Zhaoyun; Tang, Bo; Yan, Jiang

    2016-08-01

    This work focused on the metal-oxide-semiconductor (MOS) capacitor and extremely thin silicon-on-insulator (ETSOI) p-type MOS field-effect transistor ( pMOSFET) with laminated hafnium and titanium oxide (Hf-Ti-O) thin films as gate dielectric. The electrical behavior of the MOS capacitor shows that the capacitor with Hf-Ti-O gate dielectric has high performance with low equivalent oxide thickness (EOT, ~0.77 nm), small hysteresis (Δ V fb, ~4 mV), and gate current density of 0.33 A/cm2 at V g = V fb - 1 V. The dominant conduction mechanism of the Hf-Ti-O thin film (25°C to 125°C) was Schottky emission at lower gate voltage (-0.8 V to -0.2 V) and Fowler-Nordheim (F-N) tunneling at higher gate voltage (<-0.8 V). An ETSOI pMOSFET with 25 nm gate length ( L g) also exhibited good electrical properties with switch ratio of 3.2 × 104, appropriate threshold voltage of -0.16 V, maximum transconductance ( G max) of 2.63 mS, drain-induced barrier lowering of 53 mV/V, and subthreshold swing of 65 mV/dec.

  19. High-k gate dielectric GaAs MOS device with LaON as interlayer and NH3-plasma surface pretreatment

    NASA Astrophysics Data System (ADS)

    Liu, Chao-Wen; Xu, Jing-Ping; Liu, Lu; Lu, Han-Han

    2015-12-01

    High-k gate dielectric HfTiON GaAs metal-oxide-semiconductor (MOS) capacitors with LaON as interfacial passivation layer (IPL) and NH3- or N2-plasma surface pretreatment are fabricated, and their interfacial and electrical properties are investigated and compared with their counterparts that have neither LaON IPL nor surface treatment. It is found that good interface quality and excellent electrical properties can be achieved for a NH3-plasma pretreated GaAs MOS device with a stacked gate dielectric of HfTiON/LaON. These improvements should be ascribed to the fact that the NH3-plasma can provide H atoms and NH radicals that can effectively remove defective Ga/As oxides. In addition, LaON IPL can further block oxygen atoms from being in-diffused, and Ga and As atoms from being out-diffused from the substrate to the high-k dielectric. This greatly suppresses the formation of Ga/As native oxides and gives rise to an excellent high-k/GaAs interface. Project supported by the National Natural Science Foundation of China (Grant Nos. 61176100 and 61274112).

  20. W versus Co-Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes

    NASA Astrophysics Data System (ADS)

    Veloso, Anabela; Aik Chew, Soon; Schram, Tom; Dekkers, Harold; Van Ammel, Annemie; Witters, Thomas; Tielens, Hilde; Heylen, Nancy; Devriendt, Katia; Sebaai, Farid; Brus, Stephan; Ragnarsson, Lars-Åke; Pantisano, Luigi; Eneman, Geert; Carbonell, Laure; Richard, Olivier; Favia, Paola; Geypen, Jef; Bender, Hugo; Higuchi, Yuichi; Phatak, Anup; Thean, Aaron; Horiguchi, Naoto

    2013-04-01

    In this work we provide a comprehensive evaluation of a novel, low-resistance Co-Al alloy vs W to fill aggressively scaled gates with high aspect-ratios [gate height (Hgate) ˜50-60 nm, gate length (Lgate) ≥20-25 nm]. We demonstrate that, with careful liner/barrier materials selection and tuning, well-behaved devices are obtained, showing: tight gate resistance (Rgate) distributions down to Lgate˜20 nm, low threshold voltage (VT) values, comparable DC and bias temperature instability (BTI) behavior, and improved RF response. The impact of fill-metals intrinsic stress, including the presence of occasional voids in narrow W-gates, on devices fabrication and performance is also explored.

  1. High-k gate stacks on low bandgap tensile strained Ge and GeSn alloys for field-effect transistors.

    PubMed

    Wirths, Stephan; Stange, Daniela; Pampillón, Maria-Angela; Tiedemann, Andreas T; Mussler, Gregor; Fox, Alfred; Breuer, Uwe; Baert, Bruno; San Andrés, Enrique; Nguyen, Ngoc D; Hartmann, Jean-Michel; Ikonic, Zoran; Mantl, Siegfried; Buca, Dan

    2015-01-14

    We present the epitaxial growth of Ge and Ge0.94Sn0.06 layers with 1.4% and 0.4% tensile strain, respectively, by reduced pressure chemical vapor deposition on relaxed GeSn buffers and the formation of high-k/metal gate stacks thereon. Annealing experiments reveal that process temperatures are limited to 350 °C to avoid Sn diffusion. Particular emphasis is placed on the electrical characterization of various high-k dielectrics, as 5 nm Al2O3, 5 nm HfO2, or 1 nmAl2O3/4 nm HfO2, on strained Ge and strained Ge0.94Sn0.06. Experimental capacitance-voltage characteristics are presented and the effect of the small bandgap, like strong response of minority carriers at applied field, are discussed via simulations. PMID:25531887

  2. Electric field-induced transport modulation in VO2 FETs with high-k oxide/organic parylene-C hybrid gate dielectric

    NASA Astrophysics Data System (ADS)

    Wei, Tingting; Kanki, Teruo; Fujiwara, Kohei; Chikanari, Masashi; Tanaka, Hidekazu

    2016-02-01

    We report on the observation of reversible and immediate resistance switching by high-k oxide Ta2O5/organic parylene-C hybrid dielectric-gated VO2 thin films. Resistance change ratios at various temperatures in the insulating regime were demonstrated to occur in the vicinity of phase transition temperature. We also found an asymmetric hole-electron carrier modulation related to the suppression of phase transition temperature. The results in this research provide a possibility for clarifying the origin of metal-insulator transition in VO2 through the electrostatic field-induced transport modulation.

  3. Investigation of low-frequency noise of 28-nm technology process of high-k/metal gate p-MOSFETs with fluorine incorporation

    NASA Astrophysics Data System (ADS)

    Kao, Tsung-Hsien; Chang, Shoou-Jinn; Fang, Yean-Kuen; Huang, Po-Chin; Wang, Bo-Chin; Wu, Chung-Yi; Wu, San-Lein

    2016-01-01

    In this study, the properties of dielectric traps by the impact of Fluorine (F) implantation on 1/f noise and the random telegraph noise (RTN) of high-k/metal gate (HK/MG) p-type metal-oxide-semiconductor field-effect transistors (pMOSFETs) were investigated. The incorporation of F has been identified as an effective method to passivate oxygen vacancies, defect sites, and reduce the gate leakage current in pMOSFETs. Compared with a control device, the F-implanted HK/MG devices show that the trap positions were closer to the SiO2 interfacial layer (IL)/Si channel. Furthermore, we found that F implantation could result in a smaller tunneling attenuation length (λ) and smaller slow oxide interface trap density (Nt).

  4. Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

    NASA Astrophysics Data System (ADS)

    Veloso, Anabela; Aik Chew, Soon; Higuchi, Yuichi; Ragnarsson, Lars-Åke; Simoen, Eddy; Schram, Tom; Witters, Thomas; Van Ammel, Annemie; Dekkers, Harold; Tielens, Hilde; Devriendt, Katia; Heylen, Nancy; Sebaai, Farid; Brus, Stephan; Favia, Paola; Geypen, Jef; Bender, Hugo; Phatak, Anup; Chen, Michael S.; Lu, Xinliang; Ganguli, Seshadri; Lei, Yu; Tang, Wei; Fu, Xinyu; Gandikota, Srinivas; Noori, Atif; Brand, Adam; Yoshida, Naomi; Thean, Aaron; Horiguchi, Naoto

    2013-04-01

    This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), exploring several options for effective work function (EWF) engineering, and targeting logic high-performance and low-power applications. Tight low-threshold voltage (VT) distributions for scaled NMOS devices are obtained by controlled TiN/TiAl-alloying, either by using RF-physical vapor deposition (RF-PVD) or atomic layer deposition (ALD) for TiN growth. The first technique allows optimization of the TiAl/TiN thicknesses at the bottom of gate trenches while maximizing the space to be filled with a low-resistance metal; using ALD minimizes the occurrence of preferential paths, at gate sidewalls, for Al diffusion into the high-k dielectric, reducing gate leakage (JG). For multi-gate fin field-effect transistors (FinFETs) which require smaller EWF shifts from mid-gap for low-VT: 1) conformal, lower-JG ALD-TiN/TaSiAl; and 2) Al-rich ALD-TiN by controlled Al diffusion from the fill-metal are demonstrated to be promising candidates. Comparable bias temperature instability (BTI), improved noise behavior, and slightly reduced equivalent oxide thickness (EOT) are measured on Al-rich EWF-metal stacks.

  5. An effective work-function tuning method of nMOSCAP with high-k/metal gate by TiN/TaN double-layer stack thickness

    NASA Astrophysics Data System (ADS)

    Xueli, Ma; Hong, Yang; Wenwu, Wang; Huaxiang, Yin; Huilong, Zhu; Chao, Zhao; Dapeng, Chen; Tianchun, Ye

    2014-09-01

    We evaluated the TiN/TaN/TiAl triple-layer to modulate the effective work function (EWF) of a metal gate stack for the n-type metal-oxide-semiconductor (NMOS) devices application by varying the TiN/TaN thickness. In this paper, the effective work function of EWF ranges from 4.22 to 4.56 eV with different thicknesses of TiN and TaN. The thinner TiN and/or thinner in situ TaN capping, the closer to conduction band of silicon the EWF is, which is appropriate for 2-D planar NMOS. Mid-gap work function behavior is observed with thicker TiN, thicker in situ TaN capping, indicating a strong potential candidate of metal gate material for replacement gate processed three-dimensional devices such as FIN shaped field effect transistors. The physical understandings of the sensitivity of EWF to TiN and TaN thickness are proposed. The thicker TiN prevents the Al diffusion then induces the EWF to shift to mid-gap. However, the TaN plays a different role in effective work function tuning from TiN, due to the Ta—O dipoles formed at the interface between the metal gate and the high-k layer.

  6. High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

    PubMed Central

    2012-01-01

    A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials. PMID:22853458

  7. High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure.

    PubMed

    Chen, Szu-Hung; Liao, Wen-Shiang; Yang, Hsin-Chia; Wang, Shea-Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haoshuang; Wang, Mu-Chun

    2012-01-01

    A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal-semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials. PMID:22853458

  8. Structural and electrical properties of thin SrHfON films for high-k gate dielectric

    SciTech Connect

    Feng Liping; Liu Zhengtang

    2009-06-22

    Thin SrHfON films were prepared by reactive cosputtering of Hf-O and Sr-O targets in Ar/N{sub 2} ambient environment. Structural and electrical properties of the as-deposited and annealed SrHfON films used as gate dielectrics have been investigated. The SrHfON films have crystallization temperature higher than 900 deg. C. After annealing at 900 deg. C, high dielectric constant of 19.3 and effective work function of 4.13 eV was obtained for the SrHfON films. It is worth mentioning that the leakage current density of Au/SrHfON/IL SiO{sub x} gate stack is two orders of magnitude lower than that of polycrystalline silicon/HfO{sub 2} structure.

  9. Low voltage and high ON/OFF ratio field-effect transistors based on CVD MoS2 and ultra high-k gate dielectric PZT.

    PubMed

    Zhou, Changjian; Wang, Xinsheng; Raju, Salahuddin; Lin, Ziyuan; Villaroman, Daniel; Huang, Baoling; Chan, Helen Lai-Wa; Chan, Mansun; Chai, Yang

    2015-05-21

    MoS2 and other atomic-level thick layered materials have been shown to have a high potential for outperforming Si transistors at the scaling limit. In this work, we demonstrate a MoS2 transistor with a low voltage and high ON/OFF ratio. A record small equivalent oxide thickness of ∼1.1 nm has been obtained by using ultra high-k gate dielectric Pb(Zr0.52Ti0.48)O3. The low threshold voltage (<0.5 V) is comparable to that of the liquid/gel gated MoS2 transistor. The small sub-threshold swing of 85.9 mV dec(-1), the high ON/OFF ratio of ∼10(8) and the negligible hysteresis ensure a high performance of the MoS2 transistor operating at 1 V. The extracted field-effect mobility of 1-10 cm(2) V(-1) s(-1) suggests a high crystalline quality of the CVD-grown MoS2 flakes. The combination of the two-dimensional layered semiconductor and the ultra high-k dielectric may enable the development of low-power electronic applications. PMID:25907959

  10. Electric Field-induced Resistance Switching in VO2 Channels using Hybrid Gate Dielectric of High- k Ta2O5/Organic material Parylene-C

    NASA Astrophysics Data System (ADS)

    Wei, Tingting; Kanki, Teruo; Fujiwara, Kohei; Chikanari, Masashi; Tanaka, Hidekazu

    Electrostatic approach utilizing field-effect transistor (FET) with correlated electron materials provides an avenue to realize the novel devices (Mott-transistor) and to clarify condensed matter physics. In this study, we have prepared Mott-transistors using vanadium dioxide (VO2) channels and employed hybrid gate dielectric consisted of high- k material Ta2O5 and organic polymer parylene-C to trigger carrier transport modulation in VO2. Obvious resistance modulations were observed in insulating regime through time-dependent resistance measurement at varied square-shaped gate bias (VG) . Contrasting to the hysteretic response in electric double layer transistor (EDLT), an abrupt resistance switching in less than of 2-second-interval enables us to attribute such immediate modulation to pure electrostatic effect. Moreover, the maximum of resistance change was identified to appear around phase transition temperature (TMI) , which confirmed the disordered heterogeneous regime at TMI. Taking advantage of systematic modulation using VO2-based devices, we demonstrated the pronounced shifts of TMI by gate bias. Another fascinating behavior on asymmetric drop in TMI by hole-electron carrier doping was observed.

  11. Epitaxial growth of yttrium-stabilized HfO2 high-k gate dielectric thin films on Si

    NASA Astrophysics Data System (ADS)

    Dai, J. Y.; Lee, P. F.; Wong, K. H.; Chan, H. L. W.; Choy, C. L.

    2003-07-01

    Epitaxial yttrium-stabilized HfO2 thin films were deposited on p-type (100) Si substrates by pulsed laser deposition at a relatively lower substrate temperature of 550 °C. Transmission electron microscopy observation revealed a fixed orientation relationship between the epitaxial film and Si; that is, (100)Si//(100)HfO2 and [001]Si//[001]HfO2. The film/Si interface is not atomically flat, suggesting possible interfacial reaction and diffusion. X-ray photoelectron spectrum analysis also revealed the interfacial reaction and diffusion evidenced by Hf silicate and Hf-Si bond formation at the interface. The epitaxial growth of the yttrium stabilized HfO2 thin film on bare Si is via a direct growth mechanism without involving the reaction between Hf atoms and SiO2 layer. High-frequency capacitance-voltage measurement on an as-grown 40-Å yttrium-stabilized HfO2 epitaxial film yielded an effective dielectric constant of about 14 and equivalent oxide thickness to SiO2 of 12 Å. The leakage current density is 7.0×10-2 A/cm2 at 1 V gate bias voltage.

  12. Trap properties of high-k/metal gate pMOSFETs with aluminum ion implantation by random telegraph noise and 1/f noise measurements

    NASA Astrophysics Data System (ADS)

    Kao, Tsung-Hsien; Wu, San-Lein; Tsai, Kai-Shiang; Fang, Yean-Kuen; Lai, Chien-Ming; Hsu, Chia-Wei; Chen, Yi-Wen; Cheng, Osbert; Chang, Shoou-Jinn

    2014-01-01

    In this study, the impact of aluminum ion implantation on 1/f noise characteristics and random telegraph noise (RTN) in high-k/metal gate (HK/MG) p-type metal-oxide-semiconductor field-effect transistors (pMOSFETs) was investigated. Aluminum ion implantation (Al I/I) into TiN/HfO2/SiO2 was implemented to tune an effective work function (EWF) in pMOSFETs without EOT increase complicated processes. RTN and 1/f results revealed that regardless of the implanted dose, HK/MG devices with Al I/I exhibit lower slow oxide trap densities than the control devices, which are responsible for the reduced trap position (xt) from the SiO2 interfacial layer (IL)/Si interface. For the HK/MG devices with different implanted doses, no significant differences in trap properties were observed.

  13. Series resistance effect on time zero dielectrics breakdown characteristics of MOSCAP with ultra-thin EOT high-k/metal gate stacks

    NASA Astrophysics Data System (ADS)

    Hao, Xu; Hong, Yang; Yanrong, Wang; Wenwu, Wang; Guangxing, Wan; Shangqing, Ren; Weichun, Luo; Luwei, Qi; Chao, Zhao; Dapeng, Chen; Xinyu, Liu; Tianchun, Ye

    2016-05-01

    The time zero dielectric breakdown characteristics of MOSCAP with ultra-thin EOT high-k metal gate stacks are studied. The TZDB results show an abnormal area dependence due to the series resistance effect. The series resistance components extracted from the Fowler–Nordheim tunneling relation are attributed to the spreading resistance due to the asymmetry electrodes. Based on a series model to eliminate the series resistance effect, an area acceleration dependence is obtained by correcting the TZDB results. The area dependence follows Poisson area scaling rules, which indicates that the mechanism of TZDB is the same as TDDB and could be considered as a trap generation process. Project supported by the National High Technology Research and Development Program (863 Program) of China (No. SS2015AA010601), the National Natural Science Foundation of China (Nos. 61176091, 61306129), and the Opening Project of the Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences.

  14. Interface Engineering for the Enhancement of Carrier Transport in Black Phosphorus Transistor with Ultra-Thin High-k Gate Dielectric

    NASA Astrophysics Data System (ADS)

    Ling, Zhi-Peng; Zhu, Jun-Tao; Liu, Xinke; Ang, Kah-Wee

    2016-05-01

    Black phosphorus (BP) is the most stable allotrope of phosphorus which exhibits strong in-plane anisotropic charge transport. Discovering its interface properties between BP and high-k gate dielectric is fundamentally important for enhancing the carrier mobility and electrostatics control. Here, we investigate the impact of interface engineering on the transport properties of BP transistors with an ultra-thin hafnium-dioxide (HfO2) gate dielectric of ~3.4 nm. A high hole mobility of ~536 cm2V‑1s‑1 coupled with a near ideal subthreshold swing (SS) of ~66 mV/dec were simultaneously achieved at room temperature by improving the BP/HfO2 interface quality through thermal treatment. This is attributed to the passivation of phosphorus dangling bonds by hafnium (Hf) adatoms which produces a more chemically stable interface, as evidenced by the significant reduction in interface states density. Additionally, we found that an excessively high thermal treatment temperature (beyond 200 °C) could detrimentally modify the BP crystal structure, which results in channel resistance and mobility degradation due to charge-impurities scattering and lattice displacement. This study contributes to an insight for the development of high performance BP-based transistors through interface engineering.

  15. Interface Engineering for the Enhancement of Carrier Transport in Black Phosphorus Transistor with Ultra-Thin High-k Gate Dielectric

    PubMed Central

    Ling, Zhi-Peng; Zhu, Jun-Tao; Liu, Xinke; Ang, Kah-Wee

    2016-01-01

    Black phosphorus (BP) is the most stable allotrope of phosphorus which exhibits strong in-plane anisotropic charge transport. Discovering its interface properties between BP and high-k gate dielectric is fundamentally important for enhancing the carrier mobility and electrostatics control. Here, we investigate the impact of interface engineering on the transport properties of BP transistors with an ultra-thin hafnium-dioxide (HfO2) gate dielectric of ~3.4 nm. A high hole mobility of ~536 cm2V−1s−1 coupled with a near ideal subthreshold swing (SS) of ~66 mV/dec were simultaneously achieved at room temperature by improving the BP/HfO2 interface quality through thermal treatment. This is attributed to the passivation of phosphorus dangling bonds by hafnium (Hf) adatoms which produces a more chemically stable interface, as evidenced by the significant reduction in interface states density. Additionally, we found that an excessively high thermal treatment temperature (beyond 200 °C) could detrimentally modify the BP crystal structure, which results in channel resistance and mobility degradation due to charge-impurities scattering and lattice displacement. This study contributes to an insight for the development of high performance BP-based transistors through interface engineering. PMID:27222074

  16. Interface Engineering for the Enhancement of Carrier Transport in Black Phosphorus Transistor with Ultra-Thin High-k Gate Dielectric.

    PubMed

    Ling, Zhi-Peng; Zhu, Jun-Tao; Liu, Xinke; Ang, Kah-Wee

    2016-01-01

    Black phosphorus (BP) is the most stable allotrope of phosphorus which exhibits strong in-plane anisotropic charge transport. Discovering its interface properties between BP and high-k gate dielectric is fundamentally important for enhancing the carrier mobility and electrostatics control. Here, we investigate the impact of interface engineering on the transport properties of BP transistors with an ultra-thin hafnium-dioxide (HfO2) gate dielectric of ~3.4 nm. A high hole mobility of ~536 cm(2)V(-1)s(-1) coupled with a near ideal subthreshold swing (SS) of ~66 mV/dec were simultaneously achieved at room temperature by improving the BP/HfO2 interface quality through thermal treatment. This is attributed to the passivation of phosphorus dangling bonds by hafnium (Hf) adatoms which produces a more chemically stable interface, as evidenced by the significant reduction in interface states density. Additionally, we found that an excessively high thermal treatment temperature (beyond 200 °C) could detrimentally modify the BP crystal structure, which results in channel resistance and mobility degradation due to charge-impurities scattering and lattice displacement. This study contributes to an insight for the development of high performance BP-based transistors through interface engineering. PMID:27222074

  17. Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

    PubMed Central

    Hussin, H.; Soin, N.; Bukhori, M. F.; Wan Muhamad Hatta, S.; Abdul Wahab, Y.

    2014-01-01

    We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2 are increased but is reduced by 11% when the SiO2 interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2 interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated. PMID:25221784

  18. Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

    SciTech Connect

    Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Ho, Szu-Han; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Lu, Ching-Sen

    2014-10-06

    This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO{sub 2} interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

  19. Impact of the crystallization of the high-k dielectric gate oxide on the positive bias temperature instability of the n-channel metal-oxide-semiconductor field emission transistor

    NASA Astrophysics Data System (ADS)

    Lim, Han Jin; Kim, Youngkuk; Sang Jeon, In; Yeo, Jaehyun; Im, Badro; Hong, Soojin; Kim, Bong-Hyun; Nam, Seok-Woo; Kang, Ho-kyu; Jung, E. S.

    2013-06-01

    The positive bias temperature instability (PBTI) characteristics of the n-channel metal-oxide-semiconductor field emission transistors which had different kinds of high-k dielectric gate oxides were studied with the different stress-relaxation times. The degradation in the threshold voltage followed a power-law on the stress times. In particular, we found that their PBTI behaviors were closely related to the structural phase of the high-k dielectric gate oxide. In an amorphous gate oxide, the negative charges were trapped into the stress-induced defects of which energy level was so deep that the trapped charges were de-trapped slowly. Meanwhile, in a crystalline gate oxide, the negative charges were trapped mostly in the pre-existing defects in the crystallized films during early stage of the stress time and de-trapped quickly due to the shallow energy level of the defects.

  20. Improved thermal stability and electrical properties of atomic layer deposited HfO{sub 2}/AlN high-k gate dielectric stacks on GaAs

    SciTech Connect

    Cao, Yan-Qiang; Li, Xin; Zhu, Lin; Cao, Zheng-Yi; Wu, Di; Li, Ai-Dong

    2015-01-15

    The thermal stability and electrical properties of atomic layer deposited HfO{sub 2}/AlN high-k gate dielectric stacks on GaAs were investigated. Compared to HfO{sub 2}/Al{sub 2}O{sub 3} gate dielectric, significant improvements in interfacial quality as well as electrical characteristics after postdeposition annealing are confirmed by constructing HfO{sub 2}/AlN dielectric stacks. The chemical states were carefully explored by the x-ray photoelectron spectroscopy, which indicates the AlN layers effectively prevent from the formation of defective native oxides at elevated temperatures. In addition, it is found that NH{sub 3} plasma during AlN plasma-enhanced atomic layer deposition also has the self-cleaning effect as Al(CH{sub 3}){sub 3} in removing native oxides. The passivating AlN layers suppress the formation of interfacial oxide and trap charge, leading to the decrease of capacitance equivalent thickness after annealing. Moreover, HfO{sub 2}/AlN/GaAs sample has a much lower leakage current density of 2.23 × 10{sup −4} A/cm{sup 2} than HfO{sub 2}/Al{sub 2}O{sub 3}/GaAs sample of 2.58 × 10{sup −2} A/cm{sup 2}. For the HfO{sub 2}/AlN/GaAs sample annealed at 500 °C, it has a lowest interface trap density value of 2.11 × 10{sup 11} eV{sup −1} cm{sup −2}. These results indicate that adopting HfO{sub 2}/AlN dielectric stacks may be a promising approach for the realization of high quality GaAs-based transistor devices.

  1. Effect of atomic-arrangement matching on La{sub 2}O{sub 3}/Ge heterostructures for epitaxial high-k-gate-stacks

    SciTech Connect

    Kanashima, T. Zenitaka, M.; Kajihara, Y.; Yamada, S.; Hamaya, K.; Nohira, H.

    2015-12-14

    We demonstrate a high-quality La{sub 2}O{sub 3} layer on germanium (Ge) as an epitaxial high-k-gate-insulator, where there is an atomic-arrangement matching condition between La{sub 2}O{sub 3}(001) and Ge(111). Structural analyses reveal that (001)-oriented La{sub 2}O{sub 3} layers were grown epitaxially only when we used Ge(111) despite low growth temperatures less than 300 °C. The permittivity (k) of the La{sub 2}O{sub 3} layer is roughly estimated to be ∼19 from capacitance-voltage (C-V) analyses in Au/La{sub 2}O{sub 3}/Ge structures after post-metallization-annealing treatments, although the C-V curve indicates the presence of carrier traps near the interface. By using X-ray photoelectron spectroscopy analyses, we find that only Ge–O–La bonds are formed at the interface, and the thickness of the equivalent interfacial Ge oxide layer is much smaller than that of GeO{sub 2} monolayer. We discuss a model of the interfacial structure between La{sub 2}O{sub 3} and Ge(111) and comment on the C-V characteristics.

  2. Preliminary results on low power sigmoid neuron transistor response in 28 nm high-k metal gate Fully Depleted SOI technology

    NASA Astrophysics Data System (ADS)

    Galy, Ph.; Dehan, P.; Jimenez, J.; Heitz, B.

    2013-11-01

    The purpose of this paper is to describe a preliminary approach to achieve a sigmoid neuron transistor response using the 28 nm high-k metal gate Fully Depleted SOI (FDSOI) technology. It is well known that a neural network is an ambitious way to handle signal and/or data flow. Of interest also is the 'learning phase' of the proposed structure. However, the major difficulty of such structures, where the elementary device is a "Neuron Design (ND)" is in their integration. The elementary ND is based upon a circuit with at least ten interconnected CMOS transistors in order to obtain a sigmoid response activation function (in this example) with multiple inputs typically as per the McCulloch and Pitts model. Given that a large number of NDs are required to build an Artificial Neural Network (ANN), the power consumption of such a structure is a key topic that is also addressed. Another open question concerns the dispersion response due to process variability. This study reports on a new single undoped Formal Neuron Transistor (NT) solution.

  3. Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22 nm all-last high-k/metal-gate pMOSFETs

    NASA Astrophysics Data System (ADS)

    Qin, Changliang; Wang, Guilei; Hong, Peizhen; Liu, Jinbiao; Yin, Huaxiang; Yin, Haizhou; Ma, Xiaolong; Cui, Hushan; Lu, Yihong; Meng, Lingkuan; Xiang, Jinjuan; Zhong, Huicai; Zhu, Huilong; Xu, Qiuxia; Li, Junfeng; Yan, Jian; Zhao, Chao; Radamson, Henry H.

    2016-09-01

    In this paper, the technology of recessed embedded SiGe (e-SiGe) source/drain (S/D) module is optimized for the performance enhancement in 22 nm all-last high-k/metal-gate (HK/MG) pMOSFETs. Different Si recess-etch techniques were applied in S/D regions to increase the strain in the channel and subsequently, improve the performance of transistors. A new recess-etch method consists of a two-step etch method is proposed. This process is an initial anisotropic etch for the formation of shallow trench followed by a final isotropic etch. By introducing the definition of the upper edge distance (D) between the recessed S/D region and the channel region, the process advantage of the new approach is clearly presented. It decreases the value of D than those by conventional one-step isotropic or anisotropic etch of Si. Therefore, the series resistance is reduced and the channel strain is increased, which confirmed by the simulation results. The physical reason of D reducing is analyzed in brief. Applying this recess design, the implant conditions for S/D extension (SDE) are also optimized by using a two-step implantation of BF2 in SiGe layers. The overlap space between doping junction and channel region has great effect on the device's performance. The designed implantation profile decreases the overlap space while keeps a shallow junction depth for a controllable short channel effect. The channel resistance as well as the transfer ID-VG curves varying with different process conditions are demonstrated. It shows the drive current of the device with the optimized SDE implant condition and Si recess-etch process is obviously improved. The change trend of on-off current distributions extracted from a series of devices confirmed the conclusions. This study provides a useful guideline for developing high performance strained PMOS SiGe technology.

  4. Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

    NASA Astrophysics Data System (ADS)

    Liu, Hsi-Wen; Chang, Ting-Chang; Tsai, Jyun-Yu; Chen, Ching-En; Liu, Kuan-Ju; Lu, Ying-Hsin; Lin, Chien-Yu; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Ye, Yi-Han

    2016-04-01

    This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

  5. Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme

    NASA Astrophysics Data System (ADS)

    Veloso, Anabela; Boccardi, Guillaume; Ragnarsson, Lars-Åke; Higuchi, Yuichi; Arimura, Hiroaki; Lee, Jae Woo; Simoen, Eddy; Cho, Moon Ju; Roussel, Philippe J.; Paraschiv, Vasile; Shi, Xiaoping; Schram, Tom; Aik Chew, Soon; Brus, Stephan; Dangol, Anish; Vecchio, Emma; Sebaai, Farid; Kellens, Kristof; Heylen, Nancy; Devriendt, Katia; Dekkers, Harold; Van Ammel, Annemie; Witters, Thomas; Conard, Thierry; Vaesen, Inge; Richard, Olivier; Bender, Hugo; Athimulam, Raja; Chiarella, Thomas; Thean, Aaron; Horiguchi, Naoto

    2014-01-01

    We report on aggressively scaled replacement metal gate, high-k last (RMG-HKL) planar and multi-gate fin field-effect transistor (FinFET) devices, systematically investigating the impact of post high-k deposition thermal (PDA) and plasma (SF6) treatments on device characteristics, and providing a deeper insight into underlying degradation mechanisms. We demonstrate that: 1) substantially reduced gate leakage (JG) and noise can be obtained for both type of devices with PDA and F incorporation in the gate stack by SF6, without equivalent oxide thickness (EOT) penalty; 2) SF6 enables improved mobility and reduced interface trapped charge density (Nit) down to narrower fin devices [fin width (WFin) ≥ 5 nm], mitigating the impact of fin patterning and fin sidewall crystal orientations, while allowing a simplified dual-effective work function (EWF) CMOS scheme suitable for both device architectures; 3) PDA yields smaller, in absolute values, PMOS threshold voltage |VT|, and substantially improved reliability behavior due to reduction of bulk defects.

  6. Electrical properties of Ge metal–oxide–semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti

    NASA Astrophysics Data System (ADS)

    Huoxi, Xu; Jingping, Xu

    2016-06-01

    LaON, LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La2O3 using the sputtering method to fabricate Ge MOS capacitors, and the electrical properties of the devices are carefully examined. LaON/Ge capacitors exhibit the best interface quality, gate leakage property and device reliability, but a smaller k value (14.9). LaTiO/Ge capacitors exhibit a higher k value (22.7), but a deteriorated interface quality, gate leakage property and device reliability. LaTiON/Ge capacitors exhibit the highest k value (24.6), and a relatively better interface quality (3.1 × 1011 eV‑1 cm‑2), gate leakage property (3.6 × 10‑3 A/cm2 at V g = 1 V + V fb) and device reliability. Therefore, LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials. Project supported by the National Natural Science Foundation of China (No. 61274112), the Natural Science Foundation of Hubei Province (No. 2011CDB165), and the Scientific Research Program of Huanggang Normal University (No. 2012028803).

  7. Impacts of Ti on electrical properties of Ge metal-oxide-semiconductor capacitors with ultrathin high- k LaTiON gate dielectric

    NASA Astrophysics Data System (ADS)

    Xu, H. X.; Xu, J. P.; Li, C. X.; Chan, C. L.; Lai, P. T.

    2010-06-01

    Ge Metal-Oxide-Semiconductor (MOS) capacitors with LaON gate dielectric incorporating different Ti contents are fabricated and their electrical properties are measured and compared. It is found that Ti incorporation can increase the dielectric permittivity, and the higher the Ti content, the larger is the permittivity. However, the interfacial and gate-leakage properties become poorer as the Ti content increases. Therefore, optimization of Ti content is important in order to obtain a good trade-off among the electrical properties of the device. For the studied range of the Ti/La2O3 ratio, a suitable Ti/La2O3 ratio of 14.7% results in a high relative permittivity of 24.6, low interface-state density of 3.1×1011 eV-1 cm-2, and relatively low gate-leakage current density of 2.0×10-3 A cm-2 at a gate voltage of 1 V.

  8. Investigation of trap properties in high-k/metal gate p-type metal-oxide-semiconductor field-effect-transistors with aluminum ion implantation using random telegraph noise analysis

    SciTech Connect

    Kao, Tsung-Hsien; Chang, Shoou-Jinn Fang, Yean-Kuen; Huang, Po-Chin; Wu, Chung-Yi; Wu, San-Lein

    2014-08-11

    In this study, the impact of aluminum ion implantation (Al I/I) on random telegraph noise (RTN) in high-k/metal gate (HK/MG) p-type metal-oxide-semiconductor field-effect-transistors (pMOSFETs) was investigated. The trap parameters of HK/MG pMOSFETs with Al I/I, such as trap energy level, capture time and emission time, activation energies for capture and emission, and trap location in the gate dielectric, were determined. The configuration coordinate diagram was also established. It was observed that the implanted Al could fill defects and form a thin Al{sub 2}O{sub 3} layer and thus increase the tunneling barrier height for holes. It was also observed that the trap position in the Al I/I samples was lower due to the Al I/I-induced dipole at the HfO{sub 2}/SiO{sub 2} interface.

  9. Impact of parylene-C thickness on performance of KTaO3 field-effect transistors with high-k oxide/parylene-C hybrid gate dielectric

    NASA Astrophysics Data System (ADS)

    Wei, Tingting; Fujiwara, Kohei; Kanki, Teruo; Tanaka, Hidekazu

    2016-01-01

    The proposal of a hybrid gate dielectric systematically modulated with low-k material layer has been shown to be a promising strategy in the development of low-consumption field-effect transistors (FETs) with high performance. In this work, by fabricating KTaO3 FETs containing Y-doped Ta2O5/parylene-C hybrid gate dielectrics with different ratios of component thicknesses, we explored the dependence of the transistor electrical properties on the parylene-C layer thickness. Based on the results and analysis, an optimized transistor performance was achieved with an appropriate Y-doped Ta2O5/parylene-C thickness ratio from the point of view on low voltage operation. This study contributes to provide guidance for future device design and applications.

  10. Structure, sodium ion role, and practical issues for β-alumina as a high-k solution-processed gate layer for transparent and low-voltage electronics.

    PubMed

    Zhang, Bo; Liu, Yu; Agarwala, Shweta; Agarwal, Shweta; Yeh, Ming-Ling; Katz, Howard E

    2011-11-01

    Sodium β-alumina (SBA)-based gate dielectric films have been developed for all solution-processed, transparent and low voltage field-effect transistors (FETs). Its high dielectric constant has been ascribed to sodium (Na+) ions in the crystal structure; however, there are no published experimental results concerning the contribution of Na+ ions to the dielectric behavior, and the degree of crystallinity of the thin films. In addition, as an ionic conductor, β-alumina could give rise to some issues such as leakage current caused by Na diffusion, threshold voltage shift due to interface charge accumulation and longer response time due to slower polarization of the Na+ ions. This paper will address these issues using zinc tin oxide (ZTO) FETs, and propose possible measures to further improve SBA-based gate materials for electronic devices. PMID:21978249

  11. Enhanced Breakdown Reliability and Spatial Uniformity of Atomic Layer Deposited High-k Gate Dielectrics on Graphene via Organic Seeding Layers

    NASA Astrophysics Data System (ADS)

    Sangwan, Vinod; Jariwala, Deep; Filippone, Stephen; Karmel, Hunter; Johns, James; Alaboson, Justice; Marks, Tobin; Lauhon, Lincoln; Hersam, Mark

    2013-03-01

    Ultra-thin high- κ top-gate dielectrics are essential for high-speed graphene-based nanoelectronic circuits. Motivated by the need for high reliability and spatial uniformity, we report here the first statistical analysis of the breakdown characteristics of dielectrics grown on graphene. Based on these measurements, a rational approach is devised that simultaneously optimizes the gate capacitance and the key parameters of large-area uniformity and dielectric strength. In particular, vertically heterogeneous oxide stacks grown via atomic-layer deposition (ALD) seeded by a molecularly thin perylene-3,4,9,10-tetracarboxylic dianhydride (PTCDA) organic monolayer result in improved reliability (Weibull shape parameter β > 25) compared to the control dielectric directly grown on graphene without PTCDA (β < 1). The optimized sample also showed a large breakdown strength (Weibull scale parameter, EBD > 7 MV/cm) that is comparable to that of the control dielectric grown on Si substrates.

  12. The role of ZrN capping layer deposited on ultra-thin high-k Zr-doped yttrium oxide for metal-gate metal–insulator–semiconductor applications

    SciTech Connect

    Juan, Pi-Chun; Mong, Fan-Chen; Huang, Jen-Hung

    2013-08-28

    Metal-gate MIS structures with and without ZrN capping layer on high-k Y{sub 2}O{sub 3}:Zr/Y{sub 2}O{sub 3} stack were fabricated. The binding energies and depth profiles were investigated by x-ray photoelectron spectroscopy (XPS). The x-ray diffraction (XRD) patterns were compared. It is found that Ti out-diffusion into Zr-based high-k dielectric becomes lesser with the insertion of ZrN capping layer. The electrical properties of current-voltage (I-V) and capacitance-voltage (C-V) characteristics were measured in the postannealing temperature range of 550–850 °C. According to the defect reaction model, Zr cation vacancies are associated with the concentration of Ti ion by a transition from +3 to +2 states. The amount of Zr cation vacancies is quantified and equal to a half of Ti substitution amount at Zr site. The reduction in cation vacancies at high temperatures can well explain the decrease in ΔV{sub FB} for samples with ZrN layer. In contrast, an excess of Ti outdiffusion will produce the interstitial defects in high-k films without ZrN capping.

  13. In situ atomic layer nitridation on the top and down regions of the amorphous and crystalline high-K gate dielectrics

    NASA Astrophysics Data System (ADS)

    Tsai, Meng-Chen; Lee, Min-Hung; Kuo, Chin-Lung; Lin, Hsin-Chih; Chen, Miin-Jang

    2016-11-01

    Amorphous and crystalline ZrO2 gate dielectrics treated with in situ atomic layer nitridation on the top and down regions (top and down nitridation, abbreviated as TN and DN) were investigated. In a comparison between the as-deposited amorphous DN and TN samples, the DN sample has a lower leakage current density (Jg) of ∼7 × 10-4 A/cm2 with a similar capacitance equivalent thickness (CET) of ∼1.53 nm, attributed to the formation of SiOxNy in the interfacial layer (IL). The post-metallization annealing (PMA) leads to the transformation of ZrO2 from the amorphous to the crystalline tetragonal/cubic phase, resulting in an increment of the dielectric constant. The PMA-treated TN sample exhibits a lower CET of 1.22 nm along with a similar Jg of ∼1.4 × 10-5 A/cm2 as compared with the PMA-treated DN sample, which can be ascribed to the suppression of IL regrowth. The result reveals that the nitrogen engineering in the top and down regions has a significant impact on the electrical characteristics of amorphous and crystalline ZrO2 gate dielectrics, and the nitrogen incorporation at the top of crystalline ZrO2 is an effective approach to scale the CET and Jg, as well as to improve the reliability.

  14. Impact of the TiN barrier layer on the positive bias temperature instabilities of high-k/metal-gate field effect transistors

    NASA Astrophysics Data System (ADS)

    Huang, Da-Cheng; Gong, Jeng; Huang, Chih-Fang; Chung, Steve S.

    2015-04-01

    This study examined the impact of positive bias temperature instability (PBTI) on n-channel metal-oxide-semiconductor field-effect transistor (n-MOSFET) with TiN barrier layer sandwiched between metal gate electrode and HfO2 dielectric. The experimental results clearly demonstrate that the diffusion mechanism of oxygen and nitrogen as a result of the post metallization treatment was the root cause of the PBTI. In this mechanism, the oxygen during the post metallization annealing (PMA) was diffused into TiN layer and replaced the nitrogen in the TiN layer. Subsequently, these replaced nitrogens were diffused into the HfO2, from which these replaced nitrogen atoms were used to passivate the defects in the HfO2. Results show that by increasing the thickness of TiN barrier layer, the driving current and the PBTI of n-MOSFET can be greatly improved. The larger the thickness of the TiN layer is, the better the PBTI reliability becomes.

  15. Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

    NASA Astrophysics Data System (ADS)

    Kim, Young-Hee

    Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is

  16. Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-k metal gate NMOSFET with kMC TDDB simulations

    NASA Astrophysics Data System (ADS)

    Xu, Hao; Yang, Hong; Luo, Wei-Chun; Xu, Ye-Feng; Wang, Yan-Rong; Tang, Bo; Wang, Wen-Wu; Qi, Lu-Wei; Li, Jun-Feng; Yan, Jiang; Zhu, Hui-Long; Zhao, Chao; Chen, Da-Peng; Ye, Tian-Chun

    2016-08-01

    The thickness effect of the TiN capping layer on the time dependent dielectric breakdown (TDDB) characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper. Based on experimental results, it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer. From the charge pumping measurement and secondary ion mass spectroscopy (SIMS) analysis, it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density. In addition, the influences of interface and bulk trap density ratio N it/N ot are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo (kMC) method. The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses. Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601), the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129), and the Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of MicroElectronics of Chinese Academy of Sciences.

  17. Integration of High-k Oxide on MoS2 by Using Ozone Pretreatment for High-Performance MoS2 Top-Gated Transistor with Thickness-Dependent Carrier Scattering Investigation.

    PubMed

    Wang, Jingli; Li, Songlin; Zou, Xuming; Ho, Johnny; Liao, Lei; Xiao, Xiangheng; Jiang, Changzhong; Hu, Weida; Wang, Jianlu; Li, Jinchai

    2015-11-25

    A top-gated MoS2 transistor with 6 nm thick HfO2 is fabricated using an ozone pretreatment. The influence to the top-gated mobility brought about by the deposition of HfO2 is studied statistically, for the first time. The top-gated mobility is suppressed by the deposition of HfO2 , and multilayered samples are less susceptible than monolayer ones. PMID:26426344

  18. The effects of STI induced mechanical strain on GIDL current in Hf-based and SiON MOSFETs

    NASA Astrophysics Data System (ADS)

    Cheng, C. Y.; Fang, Y. K.; Liao, J. C.; Wang, T. J.; Hou, Y. T.; Hsu, P. F.; Lin, K. C.; Huang, K. T.; Lee, T. L.; Liang, M. S.

    2009-08-01

    The effects of shallow trench isolation (STI) induced mechanical strain on gate induced drain leakage (GIDL) current in Hf-based and SiON n-type metal oxide semiconductor field effect transistors (nMOSFETs) are investigated in detail. With T-CAD simulator, the compressive strain is found to increase with decreasing active area length. The STI-induced mechanical strain induces band narrowing and increases intrinsic carrier concentration, thus enhancing GIDL current via both trap-assisted tunneling and band-to-band tunneling. In addition, the HfO 2 gated nMOSFET has higher strain sensitivity than that of the SiON gated device for the higher density of interface states induced by the mechanical strain. Finally, the symmetric layout shows a higher ability to suppress the STI-enhanced GIDL current with the same active area length.

  19. Plasma etching of Hf-based high-k thin films. Part III. Modeling the reaction mechanisms

    SciTech Connect

    Martin, Ryan M.; Chang, Jane P.

    2009-03-15

    A generalized etch rate model was formulated to describe metal oxide etching in complex plasma chemistries, based on the understanding gained from detailed plasma characterization and experimental investigation into the metal oxide etching mechanisms. Using a surface site balance-based approach, the correct etch rate dependencies on neutral-to-ion flux ratio, ion energy, competing deposition and etching reaction pathways, and film properties were successfully incorporated into the model. The applicability of the model was assessed by fitting to experimental etch rate data in both Cl{sub 2} and BCl{sub 3} chemistries. Plasma gas phase analysis as well as etch and deposition rate measurements were used to calculate initial values and appropriate ranges for model parameter variation. Physically meaningful parameter values were extracted from the modeling fitting to the experimental data, thereby demonstrating the applicability of this model in assessing the plasma etching of other complex materials systems.

  20. Plasma etching of Hf-based high-k thin films. Part II. Ion-enhanced surface reaction mechanisms

    SciTech Connect

    Martin, Ryan M.; Blom, Hans-Olof; Chang, Jane P.

    2009-03-15

    The mechanism for ion-enhanced chemical etching of hafnium aluminate thin films in Cl{sub 2}/BCl{sub 3} plasmas was investigated in this work, specifically how the film composition, ion energy, and plasma chemistry determine their etch rates. Several compositions of Hf{sub 1-x}Al{sub x}O{sub y} thin films ranging from pure HfO{sub 2} to pure Al{sub 2}O{sub 3} were etched in BCl{sub 3}/Cl{sub 2} plasmas and their etch rates were found to scale with {radical}(E{sub ion}) in both Cl{sub 2} and BCl{sub 3} plasmas. In Cl{sub 2} plasmas, a transition point was observed around 50 eV, where the etch rate was significantly enhanced while the linear dependence to {radical}(E{sub ion}) was maintained, corresponding to a change in the removal of fully chlorinated to less chlorinated reaction products. In BCl{sub 3} plasma, deposition dominates at ion energies below 50 eV, while etching occurs above that energy with an etch rate of three to seven times that in Cl{sub 2}. The faster etch rate in BCl{sub 3} was attributed to a change in the dominant ion from Cl{sub 2}{sup +} in Cl{sub 2} plasma to BCl{sub 2}{sup +} in BCl{sub 3}, which facilitated the formation of more volatile etch products and their removal. The surface chlorination (0-3 at. %) was enhanced with increasing ion energy while the amount of boron on the surface increases with decreasing ion energy, highlighting the effect of different plasma chemistries on the etch rates, etch product formation, and surface termination.

  1. CROSS-DISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Growth Related Carrier Mobility Enhancement of Pentacene Thin-Film Transistors with High-k Oxide Gate Dielectric

    NASA Astrophysics Data System (ADS)

    Yu, Ai-Fang; Qi, Qiong; Jiang, Peng; Jiang, Chao

    2009-07-01

    Carrier mobility enhancement from 0.09 to 0.59 cm2/Vs is achieved for pentacene-based thin-film transistors (TFTs) by modifying the HfO2 gate dielectric with a polystyrene (PS) thin film. The improvement of the transistor's performance is found to be strongly related to the initial film morphologies of pentacene on the dielectrics. In contrast to the three-dimensional island-like growth mode on the HfO2 surface, the Stranski-Krastanov growth mode on the smooth and nonpolar PS/HfO2 surface is believed to be the origin of the excellent carrier mobility of the TFTs. A large well-connected first monolayer with fewer boundaries is formed via the Stranski-Krastanov growth mode, which facilitates a charge transport parallel to the substrate and promotes higher carrier mobility.

  2. Thermally deposited Ag-doped CdS thin film transistors with high-k rare-earth oxide Nd{sub 2}O{sub 3} as gate dielectric

    SciTech Connect

    Gogoi, P.

    2013-03-15

    The performance of thermally deposited CdS thin film transistors doped with Ag has been reported. Ag-doped CdS thin films have been prepared using chemical method. High dielectric constant rare earth oxide Nd{sub 2}O{sub 3} has been used as gate insulator. The thin film trasistors are fabricated in coplanar electrode structure on ultrasonically cleaned glass substrates with a channel length of 50 {mu}m. The thin film transistors exhibit a high mobility of 4.3 cm{sup 2} V{sup -1} s{sup -1} and low threshold voltage of 1 V. The ON-OFF ratio of the thin film transistors is found as 10{sup 5}. The TFTs also exhibit good transconductance and gain band-width product of 1.15 Multiplication-Sign 10{sup -3} mho and 71 kHz respectively.

  3. Dielectric relaxation of high-k oxides

    PubMed Central

    2013-01-01

    Frequency dispersion of high-k dielectrics was observed and classified into two parts: extrinsic cause and intrinsic cause. Frequency dependence of dielectric constant (dielectric relaxation), that is the intrinsic frequency dispersion, could not be characterized before considering the effects of extrinsic frequency dispersion. Several mathematical models were discussed to describe the dielectric relaxation of high-k dielectrics. For the physical mechanism, dielectric relaxation was found to be related to the degree of polarization, which depended on the structure of the high-k material. It was attributed to the enhancement of the correlations among polar nanodomain. The effect of grain size for the high-k materials' structure mainly originated from higher surface stress in smaller grain due to its higher concentration of grain boundary. PMID:24180696

  4. Assessment of technological and geometrical device parameters by low-frequency noise investigation in SOI omega-gate nanowire NMOS FETs

    NASA Astrophysics Data System (ADS)

    Koyama, M.; Cassé, M.; Barraud, S.; Ghibaudo, G.; Iwai, H.; Faynot, O.; Reimbold, G.

    2015-06-01

    A study of the gate oxide/channel interface quality in ultra-scaled SOI omega-gate nanowire NMOS FETs with cross-section as small as 10 nm × 10 nm is experimentally presented by low-frequency noise measurements. The noise study has been efficiently applied for the characterization of various technological parameters, including strained channel, additional hydrogen anneal, or channel orientation difference. A method for rigorous contribution assessment of the two oxide/channel interfaces (top surface vs. side-walls) is also demonstrated. Quality of the interface is slightly altered among the 4-types of technological parameters and the structural variety down to nanowire. However, an excellent quality of Hf-based high-k/metal gate stack is observed and sustained in all the devices. In particular, efficient tensile strain stressor is demonstrated with high enhancement of the NMOS FET performance and preserved 1/f noise performance fulfilling the requirement for future CMOS logic node stated in the international technology roadmap for semiconductors.

  5. Reactions for yttrium silicate high-k dielectrics

    NASA Astrophysics Data System (ADS)

    Chambers, James Joseph

    The continued scaling of metal-oxide-semiconductor-field-effect-transistors (MOSFETs) will require replacing the silicon dioxide gate dielectric with an alternate high dielectric constant (high-k) material. We have exploited the high reactivity of yttrium with both silicon and oxygen to form yttrium silicate high-k dielectrics. Yttrium silicate films with composition of (Y 2O3)x ·(SiO2)1-x and x = 0.32 to 0.87 are formed by oxidizing yttrium on silicon where yttrium reacts concurrently with silicon and oxygen. The competition between silicon and oxygen for yttrium is studied using X-ray photoelectron spectroscopy (XPS) and medium energy ion scattering (MEIS). The initial yttrium thickness mediates the silicon consumption, and a critical thickness (˜40--80 A) exists below which silicon is consumed to form yttrium silicate and above which Y2O3 forms without silicon incorporation. Engineered interfaces modify the silicon consumption, and a nitrided silicon interface results in film with composition close to Y2O3. The silicon consumption also depends on the oxidation temperature, and oxidation at higher temperature generally results in greater silicon incorporation with an activation energy of 0.3--0.5 eV. Yttrium silicate films (˜40 A) formed by oxidation of yttrium on silicon have an amorphous microstructure and an equivalent silicon dioxide thickness of ˜12 A with leakage current <1 A/cm2. Yttrium silicate formation on silicon is also demonstrated using plasma oxidation of yttrium on silicon, reactive sputtering of yttrium and annealing/oxidation of yttrium on thermal SiO 2. The interface reactions described here for yttrium are expected to be active during both physical and chemical vapor deposition of other high-k dielectrics containing Hf, Zr and La.

  6. Charge Trapping Flash Memory With High-k Dielectrics

    NASA Astrophysics Data System (ADS)

    Eun, Dong Seog

    2011-12-01

    High capacity and affordable price of flash memory make portable electronic devices popular, which in turn stimulates the further scaling down effort of the flash memory cells. Indeed the flash memory cells have been scaling down aggressively and face several crucial challenges. As a result, the technology trend is shifting from the floating-gate cell to the charge-trap cell in order to overcome fatal interference problems between cells. There are critical problems in the charge-trap memory cell which will become main-stream in the near future. The first potential problem is related to the memory retention which is degraded by the charge leakage through thin tunnel dielectrics. The second is the reduction of charge-storage capacity in the scaled down SiN trapping layer. The third is the low operation-efficiency resulting from the methods used to solve the first two problems. Using high-k tunnel dielectrics can solve the first problem. The second problem can be overcome by adopting a high-k trapping dielectric. The dielectric constant of the blocking layer must be higher than those of the tunnel dielectric and the trapping dielectric in order to maintain operation efficiency. This dissertation study is focused on adopting high-k dielectrics in all three of the aforementioned layers for figure generations of flash memory technology. For the high-k tunnel dielectric, the MAD Si3N4 and the MAD Al2O3 are used to fabricate the MANNS structure and the MANAS structure. The MANNS structure has the advantage of reducing the erase voltage due to its low barrier height for holes. In addition, the retention characteristic of the MANAS structure is not sensitive to temperature. The reason is that the carrier transport in MAD Al2O3 is dominated by F-N tunneling, which is nearly independent of temperature. Adopting TiOx as the trapping dielectric forms the MATAS structure. Although the charge capacity of TiOx is not very high, the operating voltage can be reduced to less than 10V

  7. HF-based etching processes for improving laser damage resistance of fused silica optical surfaces

    SciTech Connect

    Suratwala, T I; Miller, P E; Bude, J D; Steele, R A; Shen, N; Monticelli, M V; Feit, M D; Laurence, T A; Norton, M A; Carr, C W; Wong, L L

    2010-02-23

    The effect of various HF-based etching processes on the laser damage resistance of scratched fused silica surfaces has been investigated. Conventionally polished and subsequently scratched fused silica plates were treated by submerging in various HF-based etchants (HF or NH{sub 4}F:HF at various ratios and concentrations) under different process conditions (e.g., agitation frequencies, etch times, rinse conditions, and environmental cleanliness). Subsequently, the laser damage resistance (at 351 or 355 nm) of the treated surface was measured. The laser damage resistance was found to be strongly process dependent and scaled inversely with scratch width. The etching process was optimized to remove or prevent the presence of identified precursors (chemical impurities, fracture surfaces, and silica-based redeposit) known to lead to laser damage initiation. The redeposit precursor was reduced (and hence the damage threshold was increased) by: (1) increasing the SiF{sub 6}{sup 2-} solubility through reduction in the NH4F concentration and impurity cation impurities, and (2) improving the mass transport of reaction product (SiF{sub 6}{sup 2-}) (using high frequency ultrasonic agitation and excessive spray rinsing) away from the etched surface. A 2D finite element crack-etching and rinsing mass transport model (incorporating diffusion and advection) was used to predict reaction product concentration. The predictions are consistent with the experimentally observed process trends. The laser damage thresholds also increased with etched amount (up to {approx}30 {micro}m), which has been attributed to: (1) etching through lateral cracks where there is poor acid penetration, and (2) increasing the crack opening resulting in increased mass transport rates. With the optimized etch process, laser damage resistance increased dramatically; the average threshold fluence for damage initiation for 30 {micro}m wide scratches increased from 7 to 41 J/cm{sup 2}, and the statistical

  8. Metallorganic chemical vapor deposition and atomic layer deposition approaches for the growth of hafnium-based thin films from dialkylamide precursors for advanced CMOS gate stack applications

    NASA Astrophysics Data System (ADS)

    Consiglio, Steven P.

    To continue the rapid progress of the semiconductor industry as described by Moore's Law, the feasibility of new material systems for front end of the line (FEOL) process technologies needs to be investigated, since the currently employed polysilicon/SiO2-based transistor system is reaching its fundamental scaling limits. Revolutionary breakthroughs in complementary-metal-oxide-semiconductor (CMOS) technology were recently announced by Intel Corporation and International Business Machines Corporation (IBM), with both organizations revealing significant progress in the implementation of hafnium-based high-k dielectrics along with metal gates. This announcement was heralded by Gordon Moore as "...the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s." Accordingly, the study described herein focuses on the growth of Hf-based dielectrics and Hf-based metal gates using chemical vapor-based deposition methods, specifically metallorganic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). A family of Hf source complexes that has received much attention recently due to their desirable properties for implementation in wafer scale manufacturing is the Hf dialkylamide precursors. These precursors are room temperature liquids and possess sufficient volatility and desirable decomposition characteristics for both MOCVD and ALD processing. Another benefit of using these sources is the existence of chemically compatible Si dialkylamide sources as co-precursors for use in Hf silicate growth. The first part of this study investigates properties of MOCVD-deposited HfO2 and HfSixOy using dimethylamido Hf and Si precursor sources using a customized MOCVD reactor. The second part of this study involves a study of wet and dry surface pre-treatments for ALD growth of HfO2 using tetrakis(ethylmethylamido)hafnium in a wafer scale manufacturing environment. The third part of this study is an investigation of

  9. Memory functions of nanocrystalline cadmium selenide embedded ZrHfO high-k dielectric stack

    SciTech Connect

    Lin, Chi-Chou; Kuo, Yue

    2014-02-28

    Metal-oxide-semiconductor capacitors made of the nanocrystalline cadmium selenide nc-CdSe embedded Zr-doped HfO{sub 2} high-k stack on the p-type silicon wafer have been fabricated and studied for their charge trapping, detrapping, and retention characteristics. Both holes and electrons can be trapped to the nanocrystal-embedded dielectric stack depending on the polarity of the applied gate voltage. With the same magnitude of applied gate voltage, the sample can trap more holes than electrons. A small amount of holes are loosely trapped at the nc-CdSe/high-k interface and the remaining holes are strongly trapped to the bulk nanocrystalline CdSe site. Charges trapped to the nanocrystals caused the Coulomb blockade effect in the leakage current vs. voltage curve, which is not observed in the control sample. The addition of the nanocrystals to the dielectric film changed the defect density and the physical thickness, which are reflected on the leakage current and the breakdown voltage. More than half of the originally trapped holes can be retained in the embedded nanocrystals for more than 10 yr. The nanocrystalline CdSe embedded high-k stack is a useful gate dielectric for this nonvolatile memory device.

  10. Oxygen vacancy defect engineering using atomic layer deposited HfAlOx in multi-layered gate stack

    NASA Astrophysics Data System (ADS)

    Bhuyian, M. N.; Sengupta, R.; Vurikiti, P.; Misra, D.

    2016-05-01

    This work evaluates the defects in high quality atomic layer deposited (ALD) HfAlOx with extremely low Al (<3% Al/(Al + Hf)) incorporation in the Hf based high-k dielectrics. The defect activation energy estimated by the high temperature current voltage measurement shows that the charged oxygen vacancies, V+/V2+, are the primary source of defects in these dielectrics. When Al is added in HfO2, the V+ type defects with a defect activation energy of Ea ˜ 0.2 eV modify to V2+ type to Ea ˜ 0.1 eV with reference to the Si conduction band. When devices were stressed in the gate injection mode for 1000 s, more V+ type defects are generated and Ea reverts back to ˜0.2 eV. Since Al has a less number of valence electrons than do Hf, the change in the co-ordination number due to Al incorporation seems to contribute to the defect level modifications. Additionally, the stress induced leakage current behavior observed at 20 °C and at 125 °C demonstrates that the addition of Al in HfO2 contributed to suppressed trap generation process. This further supports the defect engineering model as reduced flat-band voltage shifts were observed at 20 °C and at 125 °C.

  11. Hard magnetic property enhancement of Co{sub 7}Hf-based ribbons by boron doping

    SciTech Connect

    Chang, H. W.; Liao, M. C.; Shih, C. W.; Chang, W. C.; Yang, C. C.; Hsiao, C. H.; Ouyang, H.

    2014-11-10

    Hard magnetic property enhancement of melt spun Co{sub 88}Hf{sub 12} ribbons by boron doping is demonstrated. B-doping could not only remarkably enhance the magnetic properties from energy product ((BH){sub max}) of 2.6 MGOe and intrinsic coercivity ({sub i}H{sub c}) of 1.5 kOe for B-free Co{sub 88}Hf{sub 12} ribbons to (BH){sub max} = 7.7 MGOe and {sub i}H{sub c} = 3.1 kOe for Co{sub 85}Hf{sub 12}B{sub 3} ribbons but also improve the Curie temperature (T{sub C}) of 7:1 phase. The (BH){sub max} value achieved in Co{sub 85}Hf{sub 12}B{sub 3} ribbons is the highest in Co-Hf alloy ribbons ever reported, which is about 15% higher than that of Co{sub 11}Hf{sub 2}B ribbons spun at 16 m/s [M. A. McGuire, O. Rios, N. J. Ghimire, and M. Koehler, Appl. Phys. Lett. 101, 202401 (2012)]. The structural analysis confirms that B enters the orthorhombic Co{sub 7}Hf (7:1) crystal structure as interstitial atoms, forming Co{sub 7}HfB{sub x}, in the as-spun state. Yet B may diffuse out from the 7:1 phase after post-annealing, leading to the reduction of Curie temperature and the magnetic properties. The uniformly refined microstructure with B-doping results in high remanence (B{sub r}) and improves the squareness of demagnetization curve. The formation of interstitial-atom-modified Co{sub 7}HfB{sub x} phase and the microstructure refinement are the main reasons to give rise to the enhancement of hard magnetic properties in the B-containing Co{sub 7}Hf-based ribbons.

  12. Gate dielectric scaling in MOSFETs device

    NASA Astrophysics Data System (ADS)

    Jing, K. Hui; Arshad, M. K. Md.; Huda, A. R. N.; Ruslinda, A. R.; Gopinath, Subash C. B.; M. Nuzaihan M., N.; Ayub, R. M.; Fathil, M. F. M.; Othman, Noraini; Hashim, U.

    2016-07-01

    Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is a basic type of transistor to be used as a switch since 1959. Since then, the successful of MOSFET is due to good properties between silicon and silicon dioxide. The reduction of silicon oxide thickness provide further enhancement in device performance. At 90 and 65 nm technology nodes, the gate oxide could not be scaled anymore due to the direct tunneling effect resulting significant increase of leakage current. At 45 nm the high-k + metal gate has been introduced. Recently, the ferroelectric effect material is introduced which significantly reduce the gate leakage current. This paper review the evolution of gate dielectric scaling from the era of silicon dioxide to high-k + metal gate and ferroelectric effect material.

  13. Silicate formation and thermal stability of ternary rare earth oxides as high-k dielectrics

    SciTech Connect

    Elshocht, S. van; Adelmann, C.; Conard, T.; Delabie, A.; Franquet, A.; Nyns, L.; Richard, O.; Lehnen, P.; Swerts, J.; Gendt, S. de

    2008-07-15

    Hf-based dielectrics are currently being introduced into complementary metal oxide semiconductor transistors as replacement for SiON to limit gate leakage current densities. Alternative materials such as rare earth based dielectrics are of interest to obtain proper threshold voltages as well as to engineer a material with a high thermal stability. The authors have studied rare earth based dielectrics such as Dy{sub 2}O{sub 3}, DyHfO{sub x}, DyScO{sub x}, La{sub 2}O{sub 3}, HfLaO{sub x}, and LaAlO{sub x} by means of ellipsometry, time of flight secondary ion mass spectroscopy x-ray diffraction, and x-ray photoelectron spectroscopy. The authors show that ellipsometry is an easy and powerful tool to study silicate formation. For ternary rare earth oxides, this behavior is heavily dependent on the composition of the deposited layer and demonstrates a nonlinear dependence. The system evolves to a stable composition that is controlled by the thermal budget and the rare earth content of the layer. It is shown that silicate formation can lead to a severe overestimation of the thermal stability of ternary rare earth oxides.

  14. Indium diffusion through high-k dielectrics in high-k/InP stacks

    SciTech Connect

    Dong, H.; Cabrera, W.; Santosh KC,; Brennan, B.; Qin, X.; McDonnell, S.; Hinkle, C. L.; Cho, K.; Chabal, Y. J.; Galatage, R. V.; Zhernokletov, D.; Wallace, R. M.

    2013-08-05

    Evidence of indium diffusion through high-k dielectric (Al{sub 2}O{sub 3} and HfO{sub 2}) films grown on InP (100) by atomic layer deposition is observed by angle resolved X-ray photoelectron spectroscopy and low energy ion scattering spectroscopy. The analysis establishes that In-out diffusion occurs and results in the formation of a PO{sub x} rich interface.

  15. High-k shallow traps observed by charge pumping with varying discharging times

    SciTech Connect

    Ho, Szu-Han; Chen, Ching-En; Tseng, Tseung-Yuen; Chang, Ting-Chang; Lu, Ying-Hsin; Lo, Wen-Hung; Tsai, Jyun-Yu; Liu, Kuan-Ju; Wang, Bin-Wei; Cao, Xi-Xin; Chen, Hua-Mao; Cheng, Osbert; Huang, Cheng-Tung; Chen, Tsai-Fu

    2013-11-07

    In this paper, we investigate the influence of falling time and base level time on high-k bulk shallow traps measured by charge pumping technique in n-channel metal-oxide-semiconductor field-effect transistors with HfO{sub 2}/metal gate stacks. N{sub T}-V{sub high} {sub level} characteristic curves with different duty ratios indicate that the electron detrapping time dominates the value of N{sub T} for extra contribution of I{sub cp} traps. N{sub T} is the number of traps, and I{sub cp} is charge pumping current. By fitting discharge formula at different temperatures, the results show that extra contribution of I{sub cp} traps at high voltage are in fact high-k bulk shallow traps. This is also verified through a comparison of different interlayer thicknesses and different Ti{sub x}N{sub 1−x} metal gate concentrations. Next, N{sub T}-V{sub high} {sub level} characteristic curves with different falling times (t{sub falling} {sub time}) and base level times (t{sub base} {sub level}) show that extra contribution of I{sub cp} traps decrease with an increase in t{sub falling} {sub time}. By fitting discharge formula for different t{sub falling} {sub time}, the results show that electrons trapped in high-k bulk shallow traps first discharge to the channel and then to source and drain during t{sub falling} {sub time}. This current cannot be measured by the charge pumping technique. Subsequent measurements of N{sub T} by charge pumping technique at t{sub base} {sub level} reveal a remainder of electrons trapped in high-k bulk shallow traps.

  16. Charge trapping at Pt/high- k dielectric (Ta 2O 5) interface

    NASA Astrophysics Data System (ADS)

    Stojanovska-Georgievska, L.; Novkovski, N.; Atanassova, E.

    2011-09-01

    A detailed analysis of the effects of constant low current injection was done, both in accumulation ( J=0.001-0.2 mA cm -2) and in inversion ( J=0.001-0.04 mA/cm 2). The samples under investigation were metal-insulator-silicon structures containing high- k dielectric Ta 2O 5 radio frequency sputtered on p-type Si wafers, with Pt metal gate electrodes. The obtained results were compared with the ones obtained for Al gate samples. This experiment confirms the occurrence of charge trapping in the case of high-work-function Pt as metal. The effect has been attributed to emitting of electrons into the Pt conduction band during which creation of empty traps in the dielectric occurs, which then attract electrons injected in the dielectric. In order to examine the reversibility of the process, successive short runs as well as long runs (up to 10000 s) were performed.

  17. 17. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    17. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ARMS, PIERS AND DAM BRIDGE, WITH ROLLER GATE HEADHOUSE IN BACKGROUND, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  18. 20. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    20. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ARM, TRUNNION PIN, PIER AND GATE GAUGE, LOOKING WEST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  19. 20. DETAIL VIEW OF SUBMERSIBLE GATE, SHOWING GATE ARMS, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    20. DETAIL VIEW OF SUBMERSIBLE GATE, SHOWING GATE ARMS, GATE PIERS, TRUNNION PIN AND GATE GAUGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  20. 21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ARM, TRUNNION PIN, PIER AND GATE GAUGE, LOOKING EAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  1. Structural and optical properties of germanium nanostructures on Si(100) and embedded in high-k oxides

    PubMed Central

    2011-01-01

    The structural and optical properties of Ge quantum dots (QDs) grown on Si(001) for mid-infrared photodetector and Ge nanocrystals embedded in oxide matrices for floating gate memory devices are presented. The infrared photoluminescence (PL) signal from Ge islands has been studied at a low temperature. The temperature- and bias-dependent photocurrent spectra of a capped Si/SiGe/Si(001) QDs infrared photodetector device are presented. The properties of Ge nanocrystals of different size and density embedded in high-k matrices grown using radio frequency magnetron sputtering have been studied. Transmission electron micrographs have revealed the formation of isolated spherical Ge nanocrystals in high-k oxide matrix of sizes ranging from 4 to 18 nm. Embedded nanocrystals in high band gap oxides have been found to act as discrete trapping sites for exchanging charge carriers with the conduction channel by direct tunneling that is desired for applications in floating gate memory devices. PMID:21711749

  2. Effects of Titanium Layer Oxygen Scavenging on the High-k/InGaAs Interface.

    PubMed

    Winter, Roy; Shekhter, Pini; Tang, Kechao; Floreano, Luca; Verdini, Alberto; McIntyre, Paul C; Eizenberg, Moshe

    2016-07-01

    One of the main challenges in the path to incorporating InGaAs based metal-oxide-semiconductor structures in nanoelectronics is the passivation of high-k/InGaAs interfaces. Here, the oxygen scavenging effect of thin Ti layers on high-k/InGaAs gate stacks was studied. Electrical measurements and synchrotron X-ray photoelectron spectroscopy measurements, with in situ metal deposition, were used. Oxygen removal from the InGaAs native oxide surface layer remotely through interposed Al2O3 and HfO2 layers observed. Synchrotron X-ray photoelectron spectroscopy has revealed a decrease in the intensity of InOx features relative to In in InGaAs after Ti deposition. The signal ratio decreases further after annealing. In addition, Ti 2p spectra clearly show oxidation of the thin Ti layer in the ultrahigh vacuum XPS environment. Using capacitance-voltage and conductance-voltage measurements, Pt/Ti/Al2O3/InGaAs and Pt/Al2O3/InGaAs capacitors were characterized both before and after annealing. It was found that the remote oxygen scavenging from the oxide/semiconductor interface using a thin Ti layer can influence the density of interface traps in the high-k/InGaAs interface. PMID:27282201

  3. Spectroscopic Study of Band Alignment in Alternative High-k MOS Dielectric Stacks

    NASA Astrophysics Data System (ADS)

    Bersch, E.; Rangan, S.; Garfunkel, E.; Bartynski, R. A.

    2007-03-01

    The study of high-k dielectrics and metal gate electrodes is critical to next generation MOSFETs. We have measured the band offsets of alternative MOS stacks using photoemission and inverse photoemission in the same chamber as well as synchrotron photoemission. At Rutgers, we have measured the valence and conduction band densities of states (DOS) and edges with UV photoemission and inverse photoemission, respectively, in situ. Using synchrotron photoemission we have measured the core level positions as well as the valence band DOS of clean and metallized dielectric/Si systems. The measurement of the chemical shifts of the core levels upon metallization enables us to evaluate the conduction band offset at the metal/dielectric interface. For Hf(x)Si(1-x)O(2), we find the conduction band offset (CBO) does not change as x is varied from 1 to 0.8, but the valence band offset increases by 0.4 eV. Titanium, aluminum and ruthenium were chosen as gate metals because of their prospective use as low and high workfunction metals in dual metal gate CMOS devices. We measured the CBO for the Ti, Al and Ru/Hf(x)Si(1-x)O(2) interfaces and found barriers involving Ti and Ru to be in good agreement with the interface gap state model, whereas the barrier involving Al deviated substantially from it due to the formation of an AlO(X) layer at the interface.

  4. 18. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    18. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ARMS, PIERS AND DAM BRIDGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  5. 16. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    16. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ARM, TRUNNION PIN AND PIER, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  6. High-K States as a Probe of Nuclear Structure

    NASA Astrophysics Data System (ADS)

    Dracoulis, G. D.

    High-K states played a key part in the discovery and understanding of deformed nuclei. An example is given of the recent use of high-K states as a signature of axially-symmetric prolate deformation in a nucleus which is predicted to show co-existence between spherical, oblate and prolate shapes. When associated bands can be identified, high-K states can also be used as a probe of pairing, and its modifiication of rotational motion. New results in 178W imply that the underlying rigid moment-of-inertia revealed when orbits are blocked to form multi-quasiparticle high-K states is substantially less than the “classical” rigid-body value. The corollary is that static pairing is quenched when only a few orbits are blocked. Recent measurements of g-factors in related high-K states in 179W allow the extraction of gR values whose behaviour as a function of seniority agrees with this suggestion.

  7. Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs)

    NASA Astrophysics Data System (ADS)

    Narendar, Vadthiya; Mishra, R. A.

    2015-09-01

    The Fin shaped Field Effect Transistor (FinFET), is a leading contender in modern microelectronics. Its unique structure allows to scale the device at sub-nanometer regime and to mimic the electrical characteristics of a MOSFET. A three-dimensional (3D) analytical modeling of SOI multigate (Gate-All-Around (GAA), Triple-Gate (TG) and Double-Gate (DG)) FinFETs and relative comparison among them is presented. The channel potential is derived from 3D Poisson's equation of each FinFET using the superposition method with appropriate boundary conditions, effective dimensions. The analytically modeled data are in good agreement with numerically simulated data of all the structures and the channel potential of GAA FinFET demonstrates the ameliorated electrostatic control over the other two structures. The impact of gate-stack (GS) high-k gate dielectrics on short channel effects (SCEs) of all aforementioned devices has been investigated with fin thickness (Tfin) variations. The GS C4 configuration reveals a significant suppression of SCEs in all FinFETs. It has been noticed that among the stated devices, the GAA FinFET with C4 configuration manifests the alleviated subthreshold swing (SS), drain induced barrier lowering (DIBL). In overall comparison, the SCEs are reasonably controlled with GS high-k gate dielectrics. The numerical simulations were performed on 3D ATLAS™.

  8. High-k dielectric Al2O3 nanowire and nanoplate field effect sensors for improved pH sensing

    PubMed Central

    Reddy, Bobby; Dorvel, Brian R.; Go, Jonghyun; Nair, Pradeep R.; Elibol, Oguz H.; Credo, Grace M.; Daniels, Jonathan S.; Chow, Edmond K. C.; Su, Xing; Varma, Madoo; Alam, Muhammad A.

    2011-01-01

    Over the last decade, field-effect transistors (FETs) with nanoscale dimensions have emerged as possible label-free biological and chemical sensors capable of highly sensitive detection of various entities and processes. While significant progress has been made towards improving their sensitivity, much is yet to be explored in the study of various critical parameters, such as the choice of a sensing dielectric, the choice of applied front and back gate biases, the design of the device dimensions, and many others. In this work, we present a process to fabricate nanowire and nanoplate FETs with Al2O3 gate dielectrics and we compare these devices with FETs with SiO2 gate dielectrics. The use of a high-k dielectric such as Al2O3 allows for the physical thickness of the gate dielectric to be thicker without losing sensitivity to charge, which then reduces leakage currents and results in devices that are highly robust in fluid. This optimized process results in devices stable for up to 8 h in fluidic environments. Using pH sensing as a benchmark, we show the importance of optimizing the device bias, particularly the back gate bias which modulates the effective channel thickness. We also demonstrate that devices with Al2O3 gate dielectrics exhibit superior sensitivity to pH when compared to devices with SiO2 gate dielectrics. Finally, we show that when the effective electrical silicon channel thickness is on the order of the Debye length, device response to pH is virtually independent of device width. These silicon FET sensors could become integral components of future silicon based Lab on Chip systems. PMID:21203849

  9. Thermally stable yttrium-scandium oxide high-k dielectrics deposited by a solution process

    NASA Astrophysics Data System (ADS)

    Hu, Wenbing; Frost, Bradley; Peterson, Rebecca L.

    2016-03-01

    We investigated the thermal stability of electrical properties in ternary alloy (Y x Sc1-x )2O3 high-k oxides as a function of yttrium fraction, x. The yttrium-scandium oxide dielectric films are deposited using a facile ink-based process. The oxides have a stoichiometry-dependent relative dielectric constant of 26.0 to 7.7 at 100 kHz, low leakage current density of 10-8 A·cm-2, high breakdown field of 4 MVṡcm-1, and interface trap density of 1012 cm-2·eV-1 with silicon. Compared with binary oxides, ternary alloys exhibit less frequency dispersion of the dielectric constant and a higher crystallization temperature. After crystallization is induced through a 900 °C anneal, ternary (Y0.6Sc0.4)2O3 films maintain their low leakage current and high breakdown field. In contrast, the electrical performance of the binary oxides significantly degrades following the same treatment. The solution-processed ternary oxide dielectrics demonstrated here may be used as high-k gate insulators in complementary metal-oxide semiconductor (CMOS) technologies, in novel electronic material systems and devices, and in printed, flexible thin film electronics, and as passivation layers for high power devices. These oxides may also be used as insulators in fabrication process flows that require a high thermal budget.

  10. Breakdown-induced thermochemical reactions in HfO2 high-κ/polycrystalline silicon gate stacks

    NASA Astrophysics Data System (ADS)

    Ranjan, R.; Pey, K. L.; Tung, C. H.; Tang, L. J.; Ang, D. S.; Groeseneken, G.; De Gendt, S.; Bera, L. K.

    2005-12-01

    The chemistry of dielectric-breakdown-induced microstructural changes in HfO2 high-κ/polycrystalline silicon gate nMOSFETs under constant voltage stress has been studied. Based on an electron energy loss spectrometry analysis, the hafnium and oxygen chemical bonding in the breakdown induced Hf-based compounds of a "ball-shaped" defect is found to be different compared to the stoichiometric HfO2 and SiO2. The formation of possibly HfSixOy and HfSix compounds in the "ball-shaped" defect is attributed to a thermochemical reaction triggered by the gate dielectric breakdown.

  11. The work function engineering and thermal stability of novel metal gate electrodes for advanced CMOS devices

    NASA Astrophysics Data System (ADS)

    Zhao, Penghui

    The continuous scaling of Complementary Metal Oxide Semiconductor (CMOS) integrated circuits requires the replacement of the conventional poly-silicon gate electrode and silicon dioxide gate dielectric with metal gate electrodes and high-agate dielectrics, respectively. The most critical requirements for alternative metal gates are proper work function and good thermal stability. This dissertation has focused on the effective work function and thermal stability of molybdenum-based metal gates (Mo, MoN, and MoSiN) and fully silicided (FUSI) NiSi metal gates. Capacitance-Voltage (C-V) and Current-Voltage (I-V) measurements of MOS capacitors were performed to investigate the electrical properties of molybdenum-based metal gates. Four-point probe resistivity measurements, Rutherford Backscattering Spectroscopy (RBS), X-ray Photoelectron Spectroscopy (XPS), High Resolution Transmission Electron Microscopy (HR-TEM), Electron Nanodiffraction analysis, X-ray Diffraction (XRD) and backside Secondary Ion Mass Spectroscopy (SIMS) methods were performed as well, to characterize the thermal stability of metal gate electrodes. The effective work function and thermal stability of molybdenum-based metal gates (Mo, MoN and MoSiN) on both SiO2 and Hf-based high-kappadielectrics have been evaluated systematically. The effects of silicon and nitrogen concentrations on the work function and thermal stability are discussed. The effective work function of molybdenum nitrides on both SiO2 and Hf-based high-kappadielectrics can be tuned to ˜4.4-4.5 eV, however, the thermal budgets should be less than 900°C 10 sec due to nitrogen loss and the phase transformation behavior of molybdenum nitrides. Silicon incorporation in the Mo-N system can improve the film thermal stability and diffusion barrier properties at the interface of metal gates/dielectrics due to the presence of Si-N bonds. By optimizing the film composition, the work function of MoSiN gates on SiO2 can be tuned for fully

  12. Selective Passivation of GeO2/Ge Interface Defects in Atomic Layer Deposited High-k MOS Structures.

    PubMed

    Zhang, Liangliang; Li, Huanglong; Guo, Yuzheng; Tang, Kechao; Woicik, Joseph; Robertson, John; McIntyre, Paul C

    2015-09-23

    Effective passivation of interface defects in high-k metal oxide/Ge gate stacks is a longstanding goal of research on germanium metal-oxide-semiconductor devices. In this paper, we use photoelectron spectroscopy to probe the formation of a GeO2 interface layer between an atomic layer deposited Al2O3 gate dielectric and a Ge(100) substrate during forming gas anneal (FGA). Capacitance- and conductance-voltage data were used to extract the interface trap density energy distribution. These results show selective passivation of interface traps with energies in the top half of the Ge band gap under annealing conditions that produce GeO2 interface layer growth. First-principles modeling of Ge/GeO2 and Ge/GeO/GeO2 structures and calculations of the resulting partial density of states (PDOS) are in good agreement with the experiment results. PMID:26334784

  13. Seeding atomic layer deposition of high-k dielectric on graphene with ultrathin poly(4-vinylphenol) layer for enhanced device performance and reliability

    NASA Astrophysics Data System (ADS)

    Cheol Shin, Woo; Yong Kim, Taek; Sul, Onejae; Jin Cho, Byung

    2012-07-01

    We demonstrate that ultrathin poly(4-vinylphenol) (PVP) acts as an effective organic seeding layer for atomic layer deposition (ALD) of high-k dielectric on large-scale graphene fabricated by chemical vapor deposition (CVD). While identical ALD conditions result in incomplete and rough dielectric deposition on CVD graphene, the reactive groups provided by the PVP seeding layer yield conformal and pinhole-free dielectric films throughout the large-scale graphene. Top-gate graphene field effect transistors fabricated with the high quality, PVP-seeded Al2O3 gate dielectric show superior carrier mobility and enhanced reliability performance, which are desirable for graphene nanoelectronics.

  14. FLOW GATING

    DOEpatents

    Poppelbaum, W.J.

    1962-12-01

    BS>This invention is a fast gating system for eiectronic flipflop circuits. Diodes connect the output of one circuit to the input of another, and the voltage supply for the receiving flip-flop has two alternate levels. When the supply is at its upper level, no current can flow through the diodes, but when the supply is at its lower level, current can flow to set the receiving flip- flop to the same state as that of the circuit to which it is connected. (AEC)

  15. A hetero-dielectric stack gate SOI-TFET with back gate and its application as a digital inverter

    NASA Astrophysics Data System (ADS)

    Mitra, Suman Kr.; Goswami, Rupam; Bhowmick, Brinda

    2016-04-01

    A Silicon based two dimensional (2D) hetero-dielectric stack gate SOI Tunneling Field Effect Transistor (SOI-TFET) with back-gate is proposed. Simulation results show that the proposed structure can be scaled down without affecting Subthreshold Swing unlike conventional TFETs with SiO2 as gate dielectric. On state of the device is independent of back-gate voltage unlike MOSFETs. The effects of gate lengths, lengths of high-k dielectric in lower stack (L) and back-gate voltages on the threshold voltage, Ion/Ioff and Subthreshold Swing (SS) of the SOI-TFET are analyzed. Capacitance components CGG, CGD, CGS are also observed and device shows good performance as an inverter. The fall time, overshoot and undershoot are not above 27 fs, 1.712% and 0.77% respectively considering mixed mode device and circuit simulation of capacitive loaded inverter.

  16. Modelling and extraction procedure for gate insulator and fringing gate capacitance components of an MIS structure

    NASA Astrophysics Data System (ADS)

    Tinoco, J. C.; Martinez-Lopez, A. G.; Lezama, G.; Mendoza-Barrera, C.; Cerdeira, A.; Estrada, M.

    2016-07-01

    CMOS technology has been guided by the continuous reduction of MOS transistors used to fabricate integrated circuits. Additionally, the use of high-k dielectrics as well as a metal gate electrode have promoted the development of nanometric MOS transistors. Under this scenario, the proper modelling of the gate capacitance, with the aim of adequately evaluating the dielectric film thickness, becomes challenging for nanometric metal-insulator-semiconductor (MIS) structures due to the presence of extrinsic fringing capacitance components which affect the total gate capacitance. In this contribution, a complete intrinsic–extrinsic model for gate capacitance under accumulation of an MIS structure, together with an extraction procedure in order to independently determine the different capacitance components, is presented. ATLAS finite element simulation has been used to validate the proposed methodology.

  17. Subthreshold analysis of nanoscale FinFETs for ultra low power application using high-k materials

    NASA Astrophysics Data System (ADS)

    Nirmal, D.; Vijayakumar, P.; Chella Samuel, P. Patrick; Jebalin, Binola K.; Mohankumar, N.

    2013-06-01

    Fin Field Effect Transistors (FinFETs) are used for Complementary Metal Oxide Semiconductor applications beyond the 45 nm node of the Semiconductor Industry Association (SIA) roadmap because of their excellent scalability and better immunity to short channel effects. This article examines the impact of high-k dielectrics on FinFETs. The FinFET device performance is analysed for On Current, Off Current, I on/I off ratio, drain induced barrier lowering, electrostatic potential along the channel, electric field along the channel, transconductance, output resistance, intrinsic gain, gate capacitance and transconductance generation factor, by replacing the conventional silicon dioxide gate dielectric material, with various high dielectric constant materials. Nanosize ZrO2 (zirconium-di-oxide) is found out to be the best alternative for SiO2 (silicon-di-oxide). It is also observed that the integration of high-k dielectrics in the devices significantly reduces the short channel effects and leakage current. The suitability of nanoscale FinFETs is observed with the help of an inverter circuit and their gain values are calculated for circuit applications.

  18. Novel gate-all-around polycrystalline silicon nanowire memory device with HfAlO charge-trapping layer

    NASA Astrophysics Data System (ADS)

    Lee, Ko-Hui; Lin, Horng-Chih; Huang, Tiao-Yuan

    2014-01-01

    Gate-all-around (GAA) nanowire (NW) memory devices with a SiN- or Hf-based charge-trapping (CT) layer of the same thickness were studied in this work. The GAA NW devices were fabricated with planar thin-film transistors (TFTs) on the same substrate using a novel scheme without resorting to the use of advanced lithographic tools. Owing to their higher dielectric constant, the GAA NW devices with a HfO2 or HfAlO CT layer show greatly enhanced programming/erasing (P/E) efficiency as compared with those with a SiN CT layer. Furthermore, the incorporation of Al into the Hf-based dielectric increases the thermal stability of the CT layer, improving retention and endurance characteristics.

  19. Evolutionary search for new high-k dielectric materials: methodology and applications to hafnia-based oxides.

    PubMed

    Zeng, Qingfeng; Oganov, Artem R; Lyakhov, Andriy O; Xie, Congwei; Zhang, Xiaodong; Zhang, Jin; Zhu, Qiang; Wei, Bingqing; Grigorenko, Ilya; Zhang, Litong; Cheng, Laifei

    2014-02-01

    High-k dielectric materials are important as gate oxides in microelectronics and as potential dielectrics for capacitors. In order to enable computational discovery of novel high-k dielectric materials, we propose a fitness model (energy storage density) that includes the dielectric constant, bandgap, and intrinsic breakdown field. This model, used as a fitness function in conjunction with first-principles calculations and the global optimization evolutionary algorithm USPEX, efficiently leads to practically important results. We found a number of high-fitness structures of SiO2 and HfO2, some of which correspond to known phases and some of which are new. The results allow us to propose characteristics (genes) common to high-fitness structures--these are the coordination polyhedra and their degree of distortion. Our variable-composition searches in the HfO2-SiO2 system uncovered several high-fitness states. This hybrid algorithm opens up a new avenue for discovering novel high-k dielectrics with both fixed and variable compositions, and will speed up the process of materials discovery. PMID:24508952

  20. Mechanical Design of the NSTX High-k Scattering Diagnostic

    SciTech Connect

    Feder, R.; Mazzucato, E.; Munsat, T.; Park, H,; Smith, D. R.; Ellis, R.; Labik, G.; Priniski, C.

    2005-09-26

    The NSTX High-k Scattering Diagnostic measures small-scale density fluctuations by the heterodyne detection of waves scattered from a millimeter wave probe beam at 280 GHz and {lambda}=1.07 mm. To enable this measurement, major alterations were made to the NSTX vacuum vessel and Neutral Beam armor. Close collaboration between the PPPL physics and engineering staff resulted in a flexible system with steerable launch and detection optics that can position the scattering volume either near the magnetic axis ({rho} {approx} .1) or near the edge ({rho} {approx} .8). 150 feet of carefully aligned corrugated waveguide was installed for injection of the probe beam and collection of the scattered signal in to the detection electronics.

  1. An effective approach for restraining electrochemical corrosion of polycrystalline silicon caused by an HF-based solution and its application for mass production of MEMS devices

    NASA Astrophysics Data System (ADS)

    Liu, Yunfei; Xie, Jing; Zhao, Hui; Luo, Wei; Yang, Jinling; An, Ji; Yang, Fuhua

    2012-03-01

    This paper presents a novel method to effectively protect the structural material polycrystalline silicon (polysilicon) from electrochemical corrosion, which often occurs when the MEMS device is released in HF-based solutions, especially when the device contains a noble metal. This corrosion seriously degrades the electrical and mechanical performance as well as the reliability of MEMS devices. In this method, a photoresist (PR) is employed to cover the noble metal, which is electrically coupled with the underlying polysilicon layer. This PR cover can effectually prevent an HF-based solution from diffusing through and arriving at the surface of the noble metal, thus cutting off the electrical current of the electrochemical corrosion reaction. The polysilicon is well protected for longer than 80 min in 49% concentrated HF solutions by a 3 µm-thick AZ 6130 PR film. This fabrication process is simple, reliable and suitable for mass production of high-end micromechanical disk resonators. Benefiting from the technology breakthrough mentioned above, a novel low-cost microfabrication method for disk resonators with high performance has been developed, and the VHF polysilicon disk resonators with resonance frequencies around 282 MHz and Q values larger than 2000 at atmosphere have been produced at wafer level.

  2. The energy-band alignment at molybdenum disulphide and high-k dielectrics interfaces

    SciTech Connect

    Tao, Junguang; Chai, J. W.; Zhang, Z.; Pan, J. S.; Wang, S. J.

    2014-06-09

    Energy-band alignments for molybdenum disulphide (MoS{sub 2}) films on high-k dielectric oxides have been studied using photoemission spectroscopy. The valence band offset (VBO) at monolayer MoS{sub 2}/Al{sub 2}O{sub 3} (ZrO{sub 2}) interface was measured to be 3.31 eV (2.76 eV), while the conduction-band offset (CBO) was 3.56 eV (1.22 eV). For bulk MoS{sub 2}/Al{sub 2}O{sub 3} interface, both VBO and CBO increase by ∼0.3 eV, due to the upwards shift of Mo 4d{sub z{sup 2}} band. The symmetric change of VBO and CBO implies Fermi level pinning by interfacial states. Our finding ensures the practical application of both p-type and n-type MoS{sub 2} based complementary metal-oxide semiconductor and other transistor devices using Al{sub 2}O{sub 3} and ZrO{sub 2} as gate materials.

  3. High-k Scattering and FIReTIP Diagnostic Upgrades for NSTX-U

    NASA Astrophysics Data System (ADS)

    Barchfeld, Robert; Scott, Evan; Domier, Calvin; Muscatello, Christopher; Riemenschneider, Paul; Sohrabi, Mohammad; Luhmann, Neville; Ren, Yang; Kaita, Robert

    2015-11-01

    A major upgrade to the High-k Scattering system is underway on NSTX-U, which is being transformed from a primarily toroidal detection geometry (for kr measurements) to a poloidal detection geometry (for kθ measurements) in which a probe beam is launched from Bay G and collected on Bay L. Combined with an increase in probing frequency to 693 GHz, the poloidal wavenumber sensitivity has been extended from kθ = 7 cm-1 up to 40 cm-1. The system will be installed and commissioned in 2016 with an initial 4-channel receiver, with plans to eventually upgrade to an 8x2 configuration, which can probe the plasma from the core out to the edge of the pedestal region. The Far Infrared Tangential Interferometer/Polarimeter (FIReTIP) system is being upgraded with field programmable gate array (FPGA) electronics to support real time feedback density control, and will be installed on Bay G this fall. Design and implementation details regarding both diagnostics will be presented. Work supported in part by U.S. DOE Grant DE-FG02-99ER54518 and DE-AC02-09CH1146.

  4. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 49 Transportation 4 2011-10-01 2011-10-01 false Gate arm and gate mechanism. 234.255 Section 234... Maintenance, Inspection, and Testing Inspections and Tests § 234.255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall...

  5. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... 49 Transportation 4 2013-10-01 2013-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month....

  6. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 49 Transportation 4 2014-10-01 2014-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month....

  7. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Gate arm and gate mechanism. 234.255 Section 234... Maintenance, Inspection, and Testing Inspections and Tests § 234.255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall...

  8. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 49 Transportation 4 2012-10-01 2012-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month....

  9. Contactless analysis of electric dipoles at high-k/SiO2 interfaces by surface-charge-switched electron spectroscopy

    NASA Astrophysics Data System (ADS)

    Toyoda, S.; Fukuda, K.; Itoh, E.; Sugaya, H.; Morita, M.; Nakata, A.; Uchimoto, Y.; Matsubara, E.

    2016-05-01

    The continuous development of silicon devices has been supported by fundamental understanding of the two interfaces that predict the device properties: high-dielectric oxide (high-k)/SiO2 and SiO2/Si. In the absence of metal electrode fabrication, it is challenging to use spectroscopic approaches to deduce the electric dipoles in these interfaces for the prediction of electrical characteristics such as the leakage current and threshold voltage. Here, we propose a method to analyze the permanent dipole at the high-k/SiO2 interface by surface-charge-switched electron spectroscopy (SuCSES). An electron flood gun was used to switch the electrical polarity at the insulating surface to extract the interface-dipole contribution from the macroscopic dielectric polarization in the high-k/SiO2/Si stack structure. TaO3- nanosheet (TaNS) crystallites, which are a family of high-k tantalate materials deposited on the SiO2/Si substrates, were annealed to prepare a nanoscale model interface. The properties of this interface were examined as a function of annealing temperature across the crystalline-to-amorphous transition. Macroscopic dielectric polarization of the TaNS/SiO2/Si gate stack was found to exhibit a gradual decay that depended upon the quantum tunneling processes of induced carriers at the SiO2/Si interface. Additionally, the dipole at the high-k/thin-SiO2 interface abruptly changed by ˜0.4 eV before and after annealing at 400 °C, which may be the result of a decrease in conduction-band offsets at the high-k/Si interface. Thus, SuCSES can aid in determining the inherent valence-band offsets in dielectric interfaces by using X-ray photoelectron spectroscopy with high accuracy and precision. Furthermore, SuCSES can determine whether dielectric polarization, including the interfacial dipole, affects the experimental value of the band offsets.

  10. High-k lithium phosphorous oxynitride thin films

    NASA Astrophysics Data System (ADS)

    Fu, Zheng-Wen; Liu, Wen-Yuan; Li, Chi-Lin; Qin, Qi-Zong; Yao, Yin; Lu, Fang

    2003-12-01

    Lithium phosphorous oxynitride (Lipon) thin films have been fabricated onto n-Si substrate at room temperature by nitrogen plasma-assisted deposition of electron-beam reactive evaporated Li3PO4. The capacitance-voltage (C-V) and I-V characteristics of Al/Lipon/Si capacitors were measured. The accumulation, depletion, and inversion phenomena in the C-V curves of the as-deposited Lipon thin film could be clearly observed. The isothermal transient ionic current of Al/Lipon/Al as a function of time during voltage stepping from 0 to 3 V exhibits a large current response due to dipole orientation. The dielectric constant of Lipon thin films is found to be 16.6, and the leakage current density at an applied electric field of 5 kV/cm is about 6.0×10-7 A/cm2. These results suggest that lithium phosphorous oxynitride thin films are high-k materials. The incorporation of N into amorphous of Li3PO4 could significantly increase the dielectric constant of Lipon thin films.

  11. 21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, GATE PIER, TRUNNION PIN AND GATE GAUGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  12. A model for the frequency dispersion of the high-k metal-oxide-semiconductor capacitance in accumulation

    NASA Astrophysics Data System (ADS)

    Yao, B.; Fang, Z. B.; Zhu, Y. Y.; Ji, T.; He, G.

    2012-05-01

    High-frequency capacitance-voltage measurements have been made on metal-oxide-semiconductor capacitors by using single crystalline Er2O3 high-k gate dielectrics. Based on our analysis, it has been found that frequency dispersion of Er2O3 capacitance in accumulation decreases consistently with the increase of the frequency. A correction model is proposed to explain these frequency dispersion phenomena and the capacitance-frequency equations are obtained from the impedance expression of the equivalent circuit. Based on the simulated capacitance-frequency, it can be concluded that frequency dispersion of Er2O3 capacitance in accumulation originates from the existence of the parasitic resistances, the series resistances, and the formed SiOx interfacial layer.

  13. Low-voltage Organic Thin Film Transistors (OTFTs) with Solution-processed High-k Dielectric cum Interface Engineering

    NASA Astrophysics Data System (ADS)

    Su, Yaorong

    Although impressive progress has been made in improving the performance of organic thin film transistors (OTFTs), the high operation voltage resulting from the low gate areal capacitance of traditional SiO 2 remains a severe limitation that hinders OTFTs' development in practical applications. In this regard, developing new materials with high- k characteristics at low cost is of great scientific and technological importance in the area of both academia and industry. In this thesis, we first describe a simple solution-based method to fabricate a high-k bilayer Al2Oy/TiOx (ATO) dielectric system at low temperature. Then the dielectric properties of the ATO are characterized and discussed in detail. Furthermore, by employing the high-k ATO as gate dielectric, low-voltage copper phthalocyanine (CuPc) based OTFTs are successfully developed. Interestingly, the obtained low-voltage CuPc TFT exhibits outstanding electrical performance, which is even higher than the device fabricated on traditional low-k SiO2. The above results seem to be contradictory to the reported results due to the fact that high-k usually shows adverse effect on the device performance. This abnormal phenomenon is then studied in detail. Characterization on the initial growth shows that the CuPc molecules assemble in a "rod-like" nano crystal with interconnected network on ATO, which probably promotes the charge carrier transport, whereas, they form isolated small islands with amorphous structure on SiO2. In addition, a better metal/organic contact is observed on ATO, which benefits the charge carrier injection. Our studies suggest that the low-temperature, solution-processed high-k ATO is a promising candidate for fabrication of high-performance, low-voltage OTFTs. Furthermore, it is well known that the properties of the dielectric/semiconductor and electrode/semiconductor interfaces are crucial in controlling the electrical properties of OTFTs. Hence, investigation the effects of interfaces

  14. Parallelizable adiabatic gate teleportation

    NASA Astrophysics Data System (ADS)

    Nakago, Kosuke; Hajdušek, Michal; Nakayama, Shojun; Murao, Mio

    2015-12-01

    To investigate how a temporally ordered gate sequence can be parallelized in adiabatic implementations of quantum computation, we modify adiabatic gate teleportation, a model of quantum computation proposed by Bacon and Flammia [Phys. Rev. Lett. 103, 120504 (2009), 10.1103/PhysRevLett.103.120504], to a form deterministically simulating parallelized gate teleportation, which is achievable only by postselection. We introduce a twisted Heisenberg-type interaction Hamiltonian, a Heisenberg-type spin interaction where the coordinates of the second qubit are twisted according to a unitary gate. We develop parallelizable adiabatic gate teleportation (PAGT) where a sequence of unitary gates is performed in a single step of the adiabatic process. In PAGT, numeric calculations suggest the necessary time for the adiabatic evolution implementing a sequence of L unitary gates increases at most as O (L5) . However, we show that it has the interesting property that it can map the temporal order of gates to the spatial order of interactions specified by the final Hamiltonian. Using this property, we present a controlled-PAGT scheme to manipulate the order of gates by a control qubit. In the controlled-PAGT scheme, two differently ordered sequential unitary gates F G and G F are coherently performed depending on the state of a control qubit by simultaneously applying the twisted Heisenberg-type interaction Hamiltonians implementing unitary gates F and G . We investigate why the twisted Heisenberg-type interaction Hamiltonian allows PAGT. We show that the twisted Heisenberg-type interaction Hamiltonian has an ability to perform a transposed unitary gate by just modifying the space ordering of the final Hamiltonian implementing a unitary gate in adiabatic gate teleportation. The dynamics generated by the time-reversed Hamiltonian represented by the transposed unitary gate enables deterministic simulation of a postselected event of parallelized gate teleportation in adiabatic

  15. Digital Microfluidic Logic Gates

    NASA Astrophysics Data System (ADS)

    Zhao, Yang; Xu, Tao; Chakrabarty, Krishnendu

    Microfluidic computing is an emerging application for microfluidics technology. We propose microfluidic logic gates based on digital microfluidics. Using the principle of electrowetting-on-dielectric, AND, OR, NOT and XOR gates are implemented through basic droplet-handling operations such as transporting, merging and splitting. The same input-output interpretation enables the cascading of gates to create nontrivial computing systems. We present a potential application for microfluidic logic gates by implementing microfluidic logic operations for on-chip HIV test.

  16. Atomic Layer Deposition of Zirconium-Based High-k Metal Gate Oxide: Effect of Si Containing Zr Precursor.

    PubMed

    Cho, Jun Hee; Lee, Sang-Ick; Kim, Jong Hyun; Yim, Sang Jun; Shin, Hyung Soo; Han, Mi Jeong; Chae, Won Mook; Lee, Sung Duck; Ahn, Chi Young; Kim, Myong-Woon

    2015-01-01

    Zirconium based thin film have been deposited by atomic layer deposition (ALD) process using Zr and Si containing Zr precursor with ozone as oxidant. We have pursued a means to control composition by varying Zr and Si containing precursor by cycle frequency. The molar ratio of Si to Zr in the Zr based films was 0.2, 0.25, 0.33, and 0.5. Addition of Si containing Zr precursor on Zirconium based thin films was effective for the decrease of the roughness, while an increase of density. XPS analysis indicated that the addition of Si containing Zr precursors in the Zr based film formed the silicate structure. The XRD analysis of the all ZrO2-SiO2 mixed films annealed at 600 degrees C for 5 min indicated the presence of amorphous. However, the ZrO2 film showed diffraction peaks at 2θ = 30.6 degrees due to the presence of the Tetragonal ZrO2. The incorporation of Si into ZrO2 films helps stabilize an amorphous structure during deposition and annealing. The Zr based thin film (Si/Zr = 0.25) exhibited that the leakage current density was 6.2 x 10(-7) A/cm2 at a bias of - 1.5 V. PMID:26328365

  17. Gated strip proportional detector

    DOEpatents

    Morris, Christopher L.; Idzorek, George C.; Atencio, Leroy G.

    1987-01-01

    A gated strip proportional detector includes a gas tight chamber which encloses a solid ground plane, a wire anode plane, a wire gating plane, and a multiconductor cathode plane. The anode plane amplifies the amount of charge deposited in the chamber by a factor of up to 10.sup.6. The gating plane allows only charge within a narrow strip to reach the cathode. The cathode plane collects the charge allowed to pass through the gating plane on a set of conductors perpendicular to the open-gated region. By scanning the open-gated region across the chamber and reading out the charge collected on the cathode conductors after a suitable integration time for each location of the gate, a two-dimensional image of the intensity of the ionizing radiation incident on the detector can be made.

  18. Gated strip proportional detector

    DOEpatents

    Morris, C.L.; Idzorek, G.C.; Atencio, L.G.

    1985-02-19

    A gated strip proportional detector includes a gas tight chamber which encloses a solid ground plane, a wire anode plane, a wire gating plane, and a multiconductor cathode plane. The anode plane amplifies the amount of charge deposited in the chamber by a factor of up to 10/sup 6/. The gating plane allows only charge within a narrow strip to reach the cathode. The cathode plane collects the charge allowed to pass through the gating plane on a set of conductors perpendicular to the open-gated region. By scanning the open-gated region across the chamber and reading out the charge collected on the cathode conductors after a suitable integration time for each location of the gate, a two-dimensional image of the intensity of the ionizing radiation incident on the detector can be made.

  19. Range gated imaging experiments using gated intensifiers

    SciTech Connect

    McDonald, T.E. Jr.; Yates, G.J.; Cverna, F.H.; Gallegos, R.A.; Jaramillo, S.A.; Numkena, D.M.; Payton, J.; Pena-Abeyta, C.R.

    1999-03-01

    A variety of range gated imaging experiments using high-speed gated/shuttered proximity focused microchannel plate image intensifiers (MCPII) are reported. Range gated imaging experiments were conducted in water for detection of submerged mines in controlled turbidity tank test and in sea water for the Naval Coastal Sea Command/US Marine Corps. Field experiments have been conducted consisting of kilometer range imaging of resolution targets and military vehicles in atmosphere at Eglin Air Force Base for the US Air Force, and similar imaging experiments, but in smoke environment, at Redstone Arsenal for the US Army Aviation and Missile Command (AMCOM). Wavelength of the illuminating laser was 532 nm with pulse width ranging from 6 to 12 ns and comparable gate widths. These tests have shown depth resolution in the tens of centimeters range from time phasing reflected LADAR images with MCPII shutter opening.

  20. Four-Quasiparticle High-K States in Neutron-Deficient Lead and Polonium Nuclei

    NASA Astrophysics Data System (ADS)

    Shi, Yue; Xu, Furong

    2012-06-01

    Configuration-constrained potential energy surface calculations have been performed to investigate four-quasiparticle high-K configurations in neutron-deficient lead and polonium isotopes. A good agreement between the calculations and the experimental data has been found for the excitation energy of the observed Kπ = 19- state in 188Pb. Several lowly excited high-K states are predicted, and the large oblate deformation and low energy indicate high-K isomerism in these nuclei.

  1. 6. DETAIL VIEW OF DAM, SHOWING TAINTER GATES, GATE PIERS ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    6. DETAIL VIEW OF DAM, SHOWING TAINTER GATES, GATE PIERS AND DAM BRIDGE, WITH ROLLER GATE HEADHOUSE IN BACKGROUND, LOOKING EAST, UPSTREAM - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  2. 5. DETAIL VIEW OF DAM, SHOWING TAINTER GATES, GATE PIERS ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    5. DETAIL VIEW OF DAM, SHOWING TAINTER GATES, GATE PIERS AND DAM BRIDGE, WITH ROLLER GATE HEADHOUSES IN BACKGROUND, LOOKING NORTHWEST, UPSTREAM - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  3. 19. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    19. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, PIER, TRUNNION PIN AND GATE GAUGE, LOOKING NORTH - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  4. 15. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATES AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    15. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATES AND GATE ARMS, PIERS AND DAM BRIDGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  5. 4. DETAIL VIEW OF TAINTER GATE PIER AND TAINTER GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    4. DETAIL VIEW OF TAINTER GATE PIER AND TAINTER GATE NO. 7 AND NON-SUBMERSIBLE TAINTER GATES, LOOKING WEST (UPSTREAM) - Upper Mississippi River 9-Foot Channel Project, Lock & Dam 26R, Alton, Madison County, IL

  6. 8. VIEW OF ROLLER GATE PIER AND ROLLER GATE OPERATING ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    8. VIEW OF ROLLER GATE PIER AND ROLLER GATE OPERATING MACHINERY HOUSE, SHOWING SERVICE BRIDGE AND ROLLER GATE, LOOKING EAST - Upper Mississippi River Nine-Foot Channel Project, Lock & Dam No. 25, Cap au Gris, Lincoln County, MO

  7. 28. VIEW OF MITER GATE OPERATING MACHINERY, SHOWING MITER GATE, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    28. VIEW OF MITER GATE OPERATING MACHINERY, SHOWING MITER GATE, GATE STRUT, AND SECTOR ARM, LOOKING EAST - Upper Mississippi River Nine-Foot Channel Project, Lock & Dam No. 25, Cap au Gris, Lincoln County, MO

  8. Sliding-gate valve

    DOEpatents

    Usnick, George B.; Ward, Gene T.; Blair, Henry O.; Roberts, James W.; Warner, Terry N.

    1979-01-01

    This invention is a novel valve of the slidable-gate type. The valve is designed especially for long-term use with highly abrasive slurries. The sealing surfaces of the gate are shielded by the valve seats when the valve is fully open or closed, and the gate-to-seat clearance is swept with an inflowing purge gas while the gate is in transit. A preferred form of the valve includes an annular valve body containing an annular seat assembly defining a flow channel. The seat assembly comprises a first seat ring which is slidably and sealably mounted in the body, and a second seat ring which is tightly fitted in the body. These rings cooperatively define an annular gap which, together with passages in the valve body, forms a guideway extending normal to the channel. A plate-type gate is mounted for reciprocation in the guideway between positions where a portion of the plate closes the channel and where a circular aperture in the gate is in register with the channel. The valve casing includes opposed chambers which extend outwardly from the body along the axis of the guideway to accommodate the end portions of the gate. The chambers are sealed from atmosphere; when the gate is in transit, purge gas is admitted to the chambers and flows inwardly through the gate-to-seat-ring, clearance, minimizing buildup of process solids therein. A shaft reciprocated by an external actuator extends into one of the sealed chambers through a shaft seal and is coupled to an end of the gate. Means are provided for adjusting the clearance between the first seat ring and the gate while the valve is in service.

  9. Adiabatically implementing quantum gates

    SciTech Connect

    Sun, Jie; Lu, Songfeng Liu, Fang

    2014-06-14

    We show that, through the approach of quantum adiabatic evolution, all of the usual quantum gates can be implemented efficiently, yielding running time of order O(1). This may be considered as a useful alternative to the standard quantum computing approach, which involves quantum gates transforming quantum states during the computing process.

  10. Gates Speaks to Librarians.

    ERIC Educational Resources Information Center

    St. Lifer, Evan

    1997-01-01

    In an interview, Microsoft CEO Bill Gates answers questions about the Gates Library Foundation; Libraries Online; tax-support for libraries; comparisons to Andrew Carnegie; charges of "buying" the library market; Internet filters, policies, and government censorship; the future of the World Wide Web and the role of librarians in its future.(PEN)

  11. Optical NAND gate

    DOEpatents

    Skogen, Erik J.; Raring, James; Tauke-Pedretti, Anna

    2011-08-09

    An optical NAND gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator and a photodetector. One pair of the optical waveguide devices is electrically connected in parallel to operate as an optical AND gate; and the other pair of the optical waveguide devices is connected in series to operate as an optical NOT gate (i.e. an optical inverter). The optical NAND gate utilizes two digital optical inputs and a continuous light input to provide a NAND function output. The optical NAND gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  12. 18. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    18. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATE AND GATE ARMS, GATE PIER AND DAM BRIDGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  13. 17. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    17. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATE AND GATE ARM, GATE PIER AND DAM BRIDGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  14. Optical XOR gate

    SciTech Connect

    Vawter, G. Allen

    2013-11-12

    An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  15. Optical NOR gate

    DOEpatents

    Skogen, Erik J.; Tauke-Pedretti, Anna

    2011-09-06

    An optical NOR gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical NOR gate utilizes two digital optical inputs and a continuous light input to provide a NOR function digital optical output. The optical NOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  16. Hole mobility modulation of solution-processed nickel oxide thin-film transistor based on high-k dielectric

    NASA Astrophysics Data System (ADS)

    Liu, Ao; Liu, Guoxia; Zhu, Huihui; Shin, Byoungchul; Fortunato, Elvira; Martins, Rodrigo; Shan, Fukai

    2016-06-01

    Solution-processed p-type oxide semiconductors have recently attracted increasing interests for the applications in low-cost optoelectronic devices and low-power consumption complementary metal-oxide-semiconductor circuits. In this work, p-type nickel oxide (NiOx) thin films were prepared using low-temperature solution process and integrated as the channel layer in thin-film transistors (TFTs). The electrical properties of NiOx TFTs, together with the characteristics of NiOx thin films, were systematically investigated as a function of annealing temperature. By introducing aqueous high-k aluminum oxide (Al2O3) gate dielectric, the electrical performance of NiOx TFT was improved significantly compared with those based on SiO2 dielectric. Particularly, the hole mobility was found to be 60 times enhancement, quantitatively from 0.07 to 4.4 cm2/V s, which is mainly beneficial from the high areal capacitance of the Al2O3 dielectric and high-quality NiOx/Al2O3 interface. This simple solution-based method for producing p-type oxide TFTs is promising for next-generation oxide-based electronic applications.

  17. Yttrium scandate thin film as alternative high-permittivity dielectric for germanium gate stack formation

    SciTech Connect

    Lu, Cimang Lee, Choong Hyun; Nishimura, Tomonori; Toriumi, Akira

    2015-08-17

    We investigated yttrium scandate (YScO{sub 3}) as an alternative high-permittivity (k) dielectric thin film for Ge gate stack formation. Significant enhancement of k-value is reported in YScO{sub 3} comparing to both of its binary compounds, Y{sub 2}O{sub 3} and Sc{sub 2}O{sub 3}, without any cost of interface properties. It suggests a feasible approach to a design of promising high-k dielectrics for Ge gate stack, namely, the formation of high-k ternary oxide out of two medium-k binary oxides. Aggressive scaling of equivalent oxide thickness (EOT) with promising interface properties is presented by using YScO{sub 3} as high-k dielectric and yttrium-doped GeO{sub 2} (Y-GeO{sub 2}) as interfacial layer, for a demonstration of high-k gate stack on Ge. In addition, we demonstrate Ge n-MOSFET performance showing the peak electron mobility over 1000 cm{sup 2}/V s in sub-nm EOT region by YScO{sub 3}/Y-GeO{sub 2}/Ge gate stack.

  18. Detection of high k turbulence using two dimensional phase contrast imaging on LHD

    SciTech Connect

    Michael, C. A.; Tanaka, K.; Akiyama, T.; Kawahata, K.; Vyacheslavov, L. N.; Sanin, A.; Kharchev, N. K.; Okajima, S.

    2008-10-15

    High k turbulence, up to 30 cm{sup -1}, can be measured using the two dimensional CO2 laser phase contrast imaging system on LHD. Recent hardware improvements and experimental results are presented. Precise control over the lens positions in the detection system is necessary because of the short depth of focus for high k modes. Remote controllable motors to move optical elements were installed, which, combined with measurements of the response to ultrasound injection, allowed experimental verification and shot-to-shot adjustment of the object plane. Strong high k signals are observed within the first 100-200 ms after the initial electron cyclotron heating (ECH) breakdown, in agreement with gyrotron scattering. During later times in the discharge, the entire k spectrum shifts to lower values (although the total amplitude does not change significantly), and the weaker high k signals are obscured by leakage of low k components at low frequency, and detector noise, at high frequency.

  19. Detection of high k turbulence using two dimensional phase contrast imaging on LHD.

    PubMed

    Michael, C A; Tanaka, K; Vyacheslavov, L N; Sanin, A; Kharchev, N K; Akiyama, T; Kawahata, K; Okajima, S

    2008-10-01

    High k turbulence, up to 30 cm(-1), can be measured using the two dimensional CO2 laser phase contrast imaging system on LHD. Recent hardware improvements and experimental results are presented. Precise control over the lens positions in the detection system is necessary because of the short depth of focus for high k modes. Remote controllable motors to move optical elements were installed, which, combined with measurements of the response to ultrasound injection, allowed experimental verification and shot-to-shot adjustment of the object plane. Strong high k signals are observed within the first 100-200 ms after the initial electron cyclotron heating (ECH) breakdown, in agreement with gyrotron scattering. During later times in the discharge, the entire k spectrum shifts to lower values (although the total amplitude does not change significantly), and the weaker high k signals are obscured by leakage of low k components at low frequency, and detector noise, at high frequency. PMID:19044541

  20. Optimal simulation of Deutsch gates and the Fredkin gate

    NASA Astrophysics Data System (ADS)

    Yu, Nengkun; Ying, Mingsheng

    2015-03-01

    In this paper, we study the optimal simulation of the three-qubit unitary using two-qubit gates. First, we completely characterize the two-qubit gate cost of simulating the Deutsch gate (controlled-controlled gate) by generalizing our result on the two-qubit cost of the Toffoli gate. The function of any Deutsch gate is simply a three-qubit controlled-unitary gate and can be intuitively explained as follows: The gate outputs the states of the two control qubits directly, and applies the given one-qubit unitary u on the target qubit only if both the states of the control qubits are |1 > . Previously, it was only known that five two-qubit gates are sufficient for implementing such a gate [Sleator and Weinfurter, Phys. Rev. Lett. 74, 4087 (1995), 10.1103/PhysRevLett.74.4087]. We show that if the determinant of u is 1, four two-qubit gates are optimal. Otherwise, five two-qubit gates are required. For the Fredkin gate (the controlled-swap gate), we prove that five two-qubit gates are necessary and sufficient, which settles the open problem introduced in Smolin and DiVincenzo [Phys. Rev. A 53, 2855 (1996), 10.1103/PhysRevA.53.2855].

  1. Nitric Oxide-mediated Relaxation by High K in Human Gastric Longitudinal Smooth Muscle.

    PubMed

    Kim, Young Chul; Choi, Woong; Yun, Hyo-Young; Sung, Rohyun; Yoo, Ra Young; Park, Seon-Mee; Yun, Sei Jin; Kim, Mi-Jung; Song, Young-Jin; Xu, Wen-Xie; Lee, Sang Jin

    2011-12-01

    This study was designed to elucidate high-K(+)induced response of circular and longitudinal smooth muscle from human gastric corpus using isometric contraction. Contraction from circular and longitudinal muscle stripes of gastric corpus greater curvature and lesser curvature were compared. Circular smooth muscle from corpus greater curvature showed high K(+) (50 mM)-induced tonic contraction. On the contrary, however, longitudinal smooth muscle strips showed high K(+) (50 mM)-induced sustained relaxation. To find out the reason for the discrepancy we tested several relaxation mechanisms. Protein kinase blockers like KT5720, PKA inhibitor, and KT5823, PKG inhibitor, did not affect high K(+)-induced relaxation. K(+) channel blockers like tetraethylammonium (TEA), apamin (APA), glibenclamide (Glib) and barium (Ba(2+)) also had no effect. However, N(G)-nitro-L-arginine (L-NNA) and 1H-(1,2,4) oxadiazolo (4,3-A) quinoxalin-1-one (ODQ), an inhibitor of soluble guanylate cyclase (sGC) and 4-AP (4-aminopyridine), voltage-dependent K(+) channel (K(V)) blocker, inhibited high K(+)-induced relaxation, hence reversing to tonic contraction. High K(+)-induced relaxation was observed in gastric corpus of human stomach, but only in the longitudinal muscles from greater curvature not lesser curvature. L-NNA, ODQ and K(V) channel blocker sensitive high K(+)-induced relaxation in longitudinal muscle of higher portion of corpus was also observed. These results suggest that longitudinal smooth muscle from greater curvature of gastric corpus produced high K(+)-induced relaxation which was activated by NO/sGC pathway and by K(V) channel dependent mechanism. PMID:22359479

  2. Explicit model for direct tunneling current in double-gate MOSFETs through a dielectric stack

    NASA Astrophysics Data System (ADS)

    Chaves, Ferney; Jiménez, David; Suñé, Jordi

    2012-10-01

    In this paper, we present an explicit compact quantum model for the direct tunneling current through dual layer SiO2/high-K dielectrics in Double Gate (DG) structures. Specifically, an explicit closed-form expression is proposed, useful to study the impact of dielectric constants and band offsets in determining the gate leakage, allowing to identify materials to construct these devices, and useful for the fast evaluation of the gate leakage in the context of electrical circuit simulators. A comparison with self-consistent numerical solution of Schrödinger-Poisson (SP) equations has been performed to demonstrate the accuracy of the model. Finally, a benchmarking test of different gate stacks have been proposed searching to fulfill the gate tunneling limits as projected by the International Technology Roadmap for Semiconductors.

  3. The human respiratory gate

    NASA Technical Reports Server (NTRS)

    Eckberg, Dwain L.

    2003-01-01

    Respiratory activity phasically alters membrane potentials of preganglionic vagal and sympathetic motoneurones and continuously modulates their responsiveness to stimulatory inputs. The most obvious manifestation of this 'respiratory gating' is respiratory sinus arrhythmia, the rhythmic fluctuations of electrocardiographic R-R intervals observed in healthy resting humans. Phasic autonomic motoneurone firing, reflecting the throughput of the system, depends importantly on the intensity of stimulatory inputs, such that when levels of stimulation are low (as with high arterial pressure and sympathetic activity, or low arterial pressure and vagal activity), respiratory fluctuations of sympathetic or vagal firing are also low. The respiratory gate has a finite capacity, and high levels of stimulation override the ability of respiration to gate autonomic responsiveness. Autonomic throughput also depends importantly on other factors, including especially, the frequency of breathing, the rate at which the gate opens and closes. Respiratory sinus arrhythmia is small at rapid, and large at slow breathing rates. The strong correlation between systolic pressure and R-R intervals at respiratory frequencies reflects the influence of respiration on these two measures, rather than arterial baroreflex physiology. A wide range of evidence suggests that respiratory activity gates the timing of autonomic motoneurone firing, but does not influence its tonic level. I propose that the most enduring significance of respiratory gating is its use as a precisely controlled experimental tool to tease out and better understand otherwise inaccessible human autonomic neurophysiological mechanisms.

  4. Advanced insulated gate bipolar transistor gate drive

    DOEpatents

    Short, James Evans; West, Shawn Michael; Fabean, Robert J.

    2009-08-04

    A gate drive for an insulated gate bipolar transistor (IGBT) includes a control and protection module coupled to a collector terminal of the IGBT, an optical communications module coupled to the control and protection module, a power supply module coupled to the control and protection module and an output power stage module with inputs coupled to the power supply module and the control and protection module, and outputs coupled to a gate terminal and an emitter terminal of the IGBT. The optical communications module is configured to send control signals to the control and protection module. The power supply module is configured to distribute inputted power to the control and protection module. The control and protection module outputs on/off, soft turn-off and/or soft turn-on signals to the output power stage module, which, in turn, supplies a current based on the signal(s) from the control and protection module for charging or discharging an input capacitance of the IGBT.

  5. CFTR Gating I

    PubMed Central

    Bompadre, Silvia G.; Ai, Tomohiko; Cho, Jeong Han; Wang, Xiaohui; Sohma, Yoshiro; Li, Min; Hwang, Tzyh-Chang

    2005-01-01

    The CFTR chloride channel is activated by phosphorylation of serine residues in the regulatory (R) domain and then gated by ATP binding and hydrolysis at the nucleotide binding domains (NBDs). Studies of the ATP-dependent gating process in excised inside-out patches are very often hampered by channel rundown partly caused by membrane-associated phosphatases. Since the severed ΔR-CFTR, whose R domain is completely removed, can bypass the phosphorylation-dependent regulation, this mutant channel might be a useful tool to explore the gating mechanisms of CFTR. To this end, we investigated the regulation and gating of the ΔR-CFTR expressed in Chinese hamster ovary cells. In the cell-attached mode, basal ΔR-CFTR currents were always obtained in the absence of cAMP agonists. Application of cAMP agonists or PMA, a PKC activator, failed to affect the activity, indicating that the activity of ΔR-CFTR channels is indeed phosphorylation independent. Consistent with this conclusion, in excised inside-out patches, application of the catalytic subunit of PKA did not affect ATP-induced currents. Similarities of ATP-dependent gating between wild type and ΔR-CFTR make this phosphorylation-independent mutant a useful system to explore more extensively the gating mechanisms of CFTR. Using the ΔR-CFTR construct, we studied the inhibitory effect of ADP on CFTR gating. The Ki for ADP increases as the [ATP] is increased, suggesting a competitive mechanism of inhibition. Single channel kinetic analysis reveals a new closed state in the presence of ADP, consistent with a kinetic mechanism by which ADP binds at the same site as ATP for channel opening. Moreover, we found that the open time of the channel is shortened by as much as 54% in the presence of ADP. This unexpected result suggests another ADP binding site that modulates channel closing. PMID:15767295

  6. Constant voltage stress induced current in Ta2O5 stacks and its dependence on a gate electrode

    NASA Astrophysics Data System (ADS)

    Atanassova, E.; Stojadinovic, N.; Paskaleva, A.; Spassov, D.; Vracar, L.; Georgieva, M.

    2008-07-01

    Response of 8 nm Ta2O5 stacks with different gates (Al, W and Au) to voltage stress at gate injection is studied by probing under various voltage/time conditions at room temperature and at 100 °C. A stress-induced leakage current (SILC) is detected in all samples and reveals gate dependence. It is established that the pre-existing traps actually govern this response, and the impact of gate-induced defects is stronger. The Au-gated devices are the most susceptible to the stress degradation. Two processes—electron trapping at pre-existing traps and positive charge build-up—are suggested to be responsible for generation of SILC. It is concluded that despite some gate effects, the origin of CVS degradation in this particular high-k dielectric is different from that in SiO2.

  7. The human respiratory gate

    PubMed Central

    Eckberg, Dwain L

    2003-01-01

    Respiratory activity phasically alters membrane potentials of preganglionic vagal and sympathetic motoneurones and continuously modulates their responsiveness to stimulatory inputs. The most obvious manifestation of this ‘respiratory gating’ is respiratory sinus arrhythmia, the rhythmic fluctuations of electrocardiographic R–R intervals observed in healthy resting humans. Phasic autonomic motoneurone firing, reflecting the throughput of the system, depends importantly on the intensity of stimulatory inputs, such that when levels of stimulation are low (as with high arterial pressure and sympathetic activity, or low arterial pressure and vagal activity), respiratory fluctuations of sympathetic or vagal firing are also low. The respiratory gate has a finite capacity, and high levels of stimulation override the ability of respiration to gate autonomic responsiveness. Autonomic throughput also depends importantly on other factors, including especially, the frequency of breathing, the rate at which the gate opens and closes. Respiratory sinus arrhythmia is small at rapid, and large at slow breathing rates. The strong correlation between systolic pressure and R–R intervals at respiratory frequencies reflects the influence of respiration on these two measures, rather than arterial baroreflex physiology. A wide range of evidence suggests that respiratory activity gates the timing of autonomic motoneurone firing, but does not influence its tonic level. I propose that the most enduring significance of respiratory gating is its use as a precisely controlled experimental tool to tease out and better understand otherwise inaccessible human autonomic neurophysiological mechanisms. PMID:12626671

  8. Gate dielectric degradation: Pre-existing vs. generated defects

    SciTech Connect

    Veksler, Dmitry E-mail: gennadi.bersuker@sematech.org; Bersuker, Gennadi E-mail: gennadi.bersuker@sematech.org

    2014-01-21

    We consider the possibility that degradation of the electrical characteristics of high-k gate stacks under low voltage stresses of practical interest is caused primarily by activation of pre-existing defects rather than generation of new ones. In nFETs in inversion, in particular, defect activation is suggested to be associated with the capture of an injected electron: in this charged state, defects can participate in a fast exchange of charge carriers with the carrier reservoir (substrate or gate electrode) that constitutes the physical process underlying a variety of electrical measurements. The degradation caused by the activation of pre-existing defects, as opposed to that of new defect generation, is both reversible and exhibits a tendency to saturate through the duration of stress. By using the multi-phonon assisted charge transport description, it is demonstrated that the trap activation concept allows reproducing a variety of experimental results including stress time dependency of the threshold voltage, leakage current, charge pumping current, and low frequency noise. Continuous, long-term degradation described by the power law time dependency is shown to be determined by the activation of defects located in the interfacial SiO{sub 2} layer of the high-k gate stacks. The findings of this study can direct process optimization efforts towards reduction of as-grown precursors of the charge trapping defects as the major factor affecting reliability.

  9. Detail of gate, gate slots, and connection between the two ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    Detail of gate, gate slots, and connection between the two segments of the rectangular rearing tank. Pump house (1962) at entrance is in the background. View to the southwest. - Prairie Creek Fish Hatchery, Hwy. 101, Orick, Humboldt County, CA

  10. 7. DETAIL VIEW OF DAM, SHOWING ROLLER GATES, GATE PIERS, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    7. DETAIL VIEW OF DAM, SHOWING ROLLER GATES, GATE PIERS, HEADHOUSES AND DAM BRIDGE, LOOKING NORTHWEST, UPSTREAM - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  11. 25. DETAIL VIEW OF TAINTER GATE, SHOWING GATE PIER, SWITCH ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    25. DETAIL VIEW OF TAINTER GATE, SHOWING GATE PIER, SWITCH AND CHAIN MOUNTED ON UNDERSIDE OF DAM BRIDGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  12. 24. DETAIL VIEW OF TAINTER GATE, SHOWING GATE PIER, SWITCH ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    24. DETAIL VIEW OF TAINTER GATE, SHOWING GATE PIER, SWITCH AND CHAIN MOUNTED ON UNDERSIDE OF DAM BRIDGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  13. 5. VIEW OF DAM, SHOWING TAINTER GATE PIERS, TAINTER GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    5. VIEW OF DAM, SHOWING TAINTER GATE PIERS, TAINTER GATE NO. 1, AND SERVICE BRIDGE, LOOKING SOUTHEAST (DOWNSTREAM) - Upper Mississippi River Nine-Foot Channel Project, Lock & Dam No. 25, Cap au Gris, Lincoln County, MO

  14. 4. VIEW OF DAM, SHOWING TAINTER GATE PIERS, TAINTER GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    4. VIEW OF DAM, SHOWING TAINTER GATE PIERS, TAINTER GATE NO. 1 SERVICE BRIDGE, AND LOCOMOTIVE CRANE, LOOKING NORTHEAST (UPSTREAM) - Upper Mississippi River Nine-Foot Channel Project, Lock & Dam No. 25, Cap au Gris, Lincoln County, MO

  15. High-k (k=30) amorphous hafnium oxide films from high rate room temperature deposition

    SciTech Connect

    Li, Flora M.; Bayer, Bernhard C.; Hofmann, Stephan; Milne, William I.; Flewitt, Andrew J.; Dutson, James D.; Wakeham, Steve J.; Thwaites, Mike J.

    2011-06-20

    Amorphous hafnium oxide (HfO{sub x}) is deposited by sputtering while achieving a very high k{approx}30. Structural characterization suggests that the high k is a consequence of a previously unreported cubiclike short range order in the amorphous HfO{sub x} (cubic k{approx}30). The films also possess a high electrical resistivity of 10{sup 14} {Omega} cm, a breakdown strength of 3 MV cm{sup -1}, and an optical gap of 6.0 eV. Deposition at room temperature and a high deposition rate ({approx}25 nm min{sup -1}) makes these high-k amorphous HfO{sub x} films highly advantageous for plastic electronics and high throughput manufacturing.

  16. Cardiac gated ventilation

    SciTech Connect

    Hanson, C.W. III; Hoffman, E.A.

    1995-12-31

    There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. The authors evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50 msec scan aperture. Multi slice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. The authors observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a non-failing model of the heart.

  17. Cardiac gated ventilation

    NASA Astrophysics Data System (ADS)

    Hanson, C. William, III; Hoffman, Eric A.

    1995-05-01

    There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. We evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50msec scan aperture. Multislice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. We observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a nonfailing model of the heart.

  18. Charge trapping characterization methodology for the evaluation of hafnium-based gate dielectric film systems

    NASA Astrophysics Data System (ADS)

    Young, Chadwin Delin

    Scaling of advanced CMOS device dimensions, as set forth for future technology nodes by the International Technology Roadmap for Semiconductors (ITRS), will require reduction of the equivalent oxide thickness (EOT) of gate dielectrics below a point that can be physically realized using silicon dioxide. In order to continue EOT scaling below ˜1.5nm and reduce gate leakage current, higher dielectric constant materials will be needed to replace SiO2. Hafnium-based dielectrics are being widely investigated as potential candidates for the gate dielectric application. Their charge trapping characteristics were identified as a primary issue preventing the introduction of Hf-based materials into CMOS technology, potentially causing threshold voltage instability and mobility degradation. Several measurement techniques can be used to study and quantify charge trapping: Capacitance-Voltage (C-V) hysteresis, alternating stress and sense Vfb/Vt instability, charge pumping (CP), and fast transient Id-Vg (FT) measurement. The two most promising techniques are CP and FT measurements. Fixed-amplitude (FA) CP can measure interface state densities, while variable-amplitude (VA) CP can measure trap densities in the high-kappa bulk. In the FT measurement, the shift of the Id -Vg curves generated by the up and down swing of a trapezoidal pulse (i.e., DeltaVt) corresponds to the amount of the trapped charge. By using these two measurement approaches on varying physical thicknesses of Hf-based gate dielectric stacks, the impact of interfacial and bulk high-kappa charge-trapping properties on device performance (i.e., mobility) was investigated. Fixed-amplitude CP gives low interface state densities for all depositions indicating good interface passivation, whereas VA CP and FT shows large trap densities in the bulk of the high-kappa layer. Results demonstrate that the bulk trapping in the high-kappa film contributes to the degradation of device performance. Using fast transient

  19. Geochronology of high-K aluminous mare basalt clasts from Apollo 14 breccia 14304

    NASA Technical Reports Server (NTRS)

    Shih, C.-Y.; Bansal, B. M.; Nyquist, L. E.; Bogard, D. D.; Dasch, E. J.

    1987-01-01

    Two aluminous mare basalt clasts of high K abundances from Apollo 14 breccia 14304 (the 14304,127 and 14304,128 samples) were characterized with respect to the Rb and Sr concentrations and isotopic compositions, and the Rb-Sr, K-Ar, and Sm-Nd isotopic age determinations were carried out. The results suggest that these high-K basalts were melts derived from mantle material and that they have experienced about ten-fold Rb/Sr and K/La enrichments at approximately the time of crystallization.

  20. Geochronology of high-K aluminous mare basalt clasts from Apollo 14 breccia 14304

    NASA Astrophysics Data System (ADS)

    Shih, C.-Y.; Nyquist, L. E.; Bogard, D. D.; Dasch, E. J.; Bansal, B. M.; Wiesmann, H.

    1987-12-01

    Two aluminous mare basalt clasts of high K abundances from Apollo 14 breccia 14304 (the 14304,127 and 14304,128 samples) were characterized with respect to the Rb and Sr concentrations and isotopic compositions, and the Rb-Sr, K-Ar, and Sm-Nd isotopic age determinations were carried out. The results suggest that these high-K basalts were melts derived from mantle material and that they have experienced about ten-fold Rb/Sr and K/La enrichments at approximately the time of crystallization.

  1. Effects of high-order deformation on high-K isomers in superheavy nuclei

    SciTech Connect

    Liu, H. L.; Bertulani, C. A.; Xu, F. R.; Walker, P. M.

    2011-01-15

    Using, for the first time, configuration-constrained potential-energy-surface calculations with the inclusion of {beta}{sub 6} deformation, we find remarkable effects of the high-order deformation on the high-K isomers in {sup 254}No, the focus of recent spectroscopy experiments on superheavy nuclei. For shapes with multipolarity six, the isomers are more tightly bound and, microscopically, have enhanced deformed shell gaps at N=152 and Z=100. The inclusion of {beta}{sub 6} deformation significantly improves the description of the very heavy high-K isomers.

  2. Atomic layer deposition of crystalline SrHfO{sub 3} directly on Ge (001) for high-k dielectric applications

    SciTech Connect

    McDaniel, Martin D.; Ngo, Thong Q.; Ekerdt, John G.; Hu, Chengqing; Jiang, Aiting; Yu, Edward T.; Lu, Sirong; Smith, David J.; Posadas, Agham; Demkov, Alexander A.

    2015-02-07

    The current work explores the crystalline perovskite oxide, strontium hafnate, as a potential high-k gate dielectric for Ge-based transistors. SrHfO{sub 3} (SHO) is grown directly on Ge by atomic layer deposition and becomes crystalline with epitaxial registry after post-deposition vacuum annealing at ∼700 °C for 5 min. The 2 × 1 reconstructed, clean Ge (001) surface is a necessary template to achieve crystalline films upon annealing. The SHO films exhibit excellent crystallinity, as shown by x-ray diffraction and transmission electron microscopy. The SHO films have favorable electronic properties for consideration as a high-k gate dielectric on Ge, with satisfactory band offsets (>2 eV), low leakage current (<10{sup −5} A/cm{sup 2} at an applied field of 1 MV/cm) at an equivalent oxide thickness of 1 nm, and a reasonable dielectric constant (k ∼ 18). The interface trap density (D{sub it}) is estimated to be as low as ∼2 × 10{sup 12 }cm{sup −2 }eV{sup −1} under the current growth and anneal conditions. Some interfacial reaction is observed between SHO and Ge at temperatures above ∼650 °C, which may contribute to increased D{sub it} value. This study confirms the potential for crystalline oxides grown directly on Ge by atomic layer deposition for advanced electronic applications.

  3. Outlet side of gate, showing the Radial Gate, hoist mechanism ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    Outlet side of gate, showing the Radial Gate, hoist mechanism and concrete walkway across the canal. The concrete baffle separating the afterbay and the cipoletti weir is in the foreground - Wellton-Mohawk Irrigation System, Radial Gate Check with Drop, Wellton Canal 9.9, West of Avenue 34 East & north of County Ninth Street, Wellton, Yuma County, AZ

  4. Silicon Nanowires with High-k Hafnium Oxide Dielectrics for Sensitive Detection of Small Nucleic Acid Oligomers

    PubMed Central

    Dorvel, Brian R.; Reddy, Bobby; Go, Jonghyun; Guevara, Carlos Duarte; Salm, Eric; Alam, Muhammad Ashraful; Bashir, Rashid

    2012-01-01

    Nanobiosensors based on silicon nanowire field effect transistors offer advantages of low cost, label-free detection, and potential for massive parallelization. As a result, these sensors have often been suggested as an attractive option for applications in Point-of-care (POC) medical diagnostics. Unfortunately, a number of performance issues such as gate leakage and current instability due to fluid contact, have prevented widespread adoption of the technology for routine use. High-k dielectrics, such as hafnium oxide (HfO2), have the known ability to address these challenges by passivating the exposed surfaces against destabilizing concerns of ion transport. With these fundamental stability issues addressed, a promising target for POC diagnostics and SiNWFET’s has been small oligonucleotides, more specifically microRNA (miRNA). MicroRNA’s are small RNA oligonucleotides which bind to messenger RNA’s, causing translational repression of proteins, gene silencing, and expressions are typically altered in several forms of cancer. In this paper, we describe a process for fabricating stable HfO2 dielectric based silicon nanowires for biosensing applications. Here we demonstrate sensing of single stranded DNA analogues to their microRNA cousins using miR-10b and miR-21 as templates, both known to be upregulated in breast cancer. We characterize the effect of surface functionalization on device performance using the miR-10b DNA analogue as the target sequence and different molecular weight poly-l-lysine as the functionalization layer. By optimizing the surface functionalization and fabrication protocol, we were able to achieve <100fM detection levels of miR-10b DNA analogue, with a theoretical limit of detection of 1fM. Moreover, the non-complementary DNA target strand, based on miR-21, showed very little response, indicating a highly sensitive and highly selective biosensing platform. PMID:22695179

  5. The four-gate transistor

    NASA Technical Reports Server (NTRS)

    Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

    2002-01-01

    The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

  6. Stanford, Duke, Rice,... and Gates?

    ERIC Educational Resources Information Center

    Carey, Kevin

    2009-01-01

    This article presents an open letter to Bill Gates. In his letter, the author suggests that Bill Gates should build a brand-new university, a great 21st-century institution of higher learning. This university will be unlike anything the world has ever seen. He asks Bill Gates not to stop helping existing colleges create the higher-education system…

  7. Toll Gate Metrication Project

    ERIC Educational Resources Information Center

    Izzi, John

    1974-01-01

    The project director of the Toll Gate Metrication Project describes the project as the first structured United States public school educational experiment in implementing change toward the adoption of the International System of Units. He believes the change will simplify, rather than complicate, the educational task. (AG)

  8. Strategy Retooled at Gates

    ERIC Educational Resources Information Center

    Robelen, Erik W.

    2008-01-01

    In rolling out plans last week to revamp its high school strategy and launch a major new effort on the postsecondary front, the Bill & Melinda Gates Foundation is undertaking a more sweeping approach to grantmaking that appears aimed at reshaping some core elements of the U.S. education system. The philanthropy's agenda on secondary schools…

  9. A threshold voltage model of short-channel fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs with high-k dielectric

    NASA Astrophysics Data System (ADS)

    Gopi Krishna, Saramekala; Sarvesh, Dubey; Pramod, Kumar Tiwari

    2015-10-01

    In this paper, a surface potential based threshold voltage model of fully-depleted (FD) recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is presented while considering the effects of high-k gate-dielectric material induced fringing-field. The two-dimensional (2D) Poisson’s equation is solved in a channel region in order to obtain the surface potential under the assumption of the parabolic potential profile in the transverse direction of the channel with appropriate boundary conditions. The accuracy of the model is verified by comparing the model’s results with the 2D simulation results from ATLAS over a wide range of channel lengths and other parameters, including the dielectric constant of gate-dielectric material. The author, Pramod Kumar Tiwari, was supported by the Science and Engineering Research Board (SERB), Department of Science and Technology, Ministry of Human Resource and Development, Government of India under Young Scientist Research (Grant No. SB/FTP/ETA-415/2012).

  10. Hydraulic Tomography: Continuity and Discontinuity of High-K and Low-K Zones.

    PubMed

    Hochstetler, David L; Barrash, Warren; Leven, Carsten; Cardiff, Michael; Chidichimo, Francesco; Kitanidis, Peter K

    2016-03-01

    Hydraulic tomography is an emerging field and modeling method that provides a continuous hydraulic conductivity (K) distribution for an investigated region. Characterization approaches that rely on interpolation between one-dimensional (1D) profiles have limited ability to accurately identify high-K channels, juxtapositions of lenses with high K contrast, and breaches in layers or channels between such profiles. However, locating these features is especially important for groundwater flow and transport modeling, and for design and operation of in situ remediation in complex hydrogeologic environments. We use transient hydraulic tomography to estimate 3D K in a volume of 15-m diameter by 20-m saturated thickness in a highly heterogeneous unconfined alluvial (clay to sand-and-gravel) aquifer with a K range of approximately seven orders of magnitude at an active industrial site in Assemini, Sardinia, Italy. A modified Levenberg-Marquardt algorithm was used for geostatistical inversion to deal with the nonlinear nature of the highly heterogeneous system. The imaging results are validated with pumping tests not used in the tomographic inversion. These tests were conducted from three of five clusters of continuous multichannel tubing (CMTs) installed for observation in the tomographic testing. Locations of high-K continuity and discontinuity, juxtaposition of very high-K and very low-K lenses, and low-K "plugs" are evident in regions of the investigated volume where they likely would not have been identified with interpolation from 1D profiles at the positions of the pumping well and five CMT clusters. Quality assessment methods identified a suspect high-K feature between the tested volume and a lateral boundary of the model. PMID:26096272

  11. Universal Superreplication of Unitary Gates

    NASA Astrophysics Data System (ADS)

    Chiribella, G.; Yang, Y.; Huang, C.

    2015-03-01

    Quantum states obey an asymptotic no-cloning theorem, stating that no deterministic machine can reliably replicate generic sequences of identically prepared pure states. In stark contrast, we show that generic sequences of unitary gates can be replicated deterministically at nearly quadratic rates, with an error vanishing on most inputs except for an exponentially small fraction. The result is not in contradiction with the no-cloning theorem, since the impossibility of deterministically transforming pure states into unitary gates prevents the application of the gate replication protocol to states. In addition to gate replication, we show that N parallel uses of a completely unknown unitary gate can be compressed into a single gate acting on O (log2N ) qubits, leading to an exponential reduction of the amount of quantum communication needed to implement the gate remotely.

  12. Universal superreplication of unitary gates.

    PubMed

    Chiribella, G; Yang, Y; Huang, C

    2015-03-27

    Quantum states obey an asymptotic no-cloning theorem, stating that no deterministic machine can reliably replicate generic sequences of identically prepared pure states. In stark contrast, we show that generic sequences of unitary gates can be replicated deterministically at nearly quadratic rates, with an error vanishing on most inputs except for an exponentially small fraction. The result is not in contradiction with the no-cloning theorem, since the impossibility of deterministically transforming pure states into unitary gates prevents the application of the gate replication protocol to states. In addition to gate replication, we show that N parallel uses of a completely unknown unitary gate can be compressed into a single gate acting on O(log_{2}N) qubits, leading to an exponential reduction of the amount of quantum communication needed to implement the gate remotely. PMID:25860728

  13. Ion polarization behavior in alumina under pulsed gate bias stress

    SciTech Connect

    Liu, Yu; Diallo, Abdou Karim; Katz, Howard E.

    2015-03-16

    Alkali metal ion incorporation in alumina significantly increases alumina capacitance by ion polarization. With high capacitance, ion-incorporated aluminas become promising high dielectric constant (high-k) gate dielectric materials in field-effect transistors (FETs) to enable reduced operating voltage, using oxide or organic semiconductors. Alumina capacitance can be manipulated by incorporation of alkali metal ions, including potassium (K{sup +}), sodium (Na{sup +}), and lithium (Li{sup +}), having different bond strengths with oxygen. To investigate the electrical stability of zinc tin oxide-based transistors using ion incorporated alumina as gate dielectrics, pulsed biases at different duty cycles (20%, 10%, and 2% representing 5 ms, 10 ms, and 50 ms periods, respectively) were applied to the gate electrode, sweeping the gate voltage over series of these cycles. We observed a particular bias stress-induced decrease of saturation field-effect mobility accompanied by threshold voltage shifts (ΔV{sub th}) in potassium and sodium-incorporated alumina (abbreviated as PA and SA)-based FETs at high duty cycle that persisted over multiple gate voltage sweeps, suggesting a possible creation of new defects in the semiconductor. This conclusion is also supported by the greater change in the mobility-capacitance (μC) product than in capacitance itself. Moreover, a more pronounced ΔV{sub th} over shorter times was observed in lithium-incorporated alumina (abbreviated as LA)-based transistors, suggesting trapping of electrons in existing interfacial states. ΔV{sub th} from multiple gate voltage sweeps over time were fit to stretched exponential forms. All three dielectrics show good stability using 50-ms intervals (20-Hz frequencies), corresponding to 2% duty cycles.

  14. Direct observation of bias-dependence potential distribution in metal/HfO{sub 2} gate stack structures by hard x-ray photoelectron spectroscopy under device operation

    SciTech Connect

    Yamashita, Y.; Yoshikawa, H.; Kobayashi, K.; Chikyo, T.

    2014-01-28

    Although gate stack structures with high-k materials have been extensively investigated, there are some issues to be solved for the formation of high quality gate stack structures. In the present study, we employed hard x-ray photoelectron spectroscopy in operating devices. This method allows us to investigate bias dependent electronic states, while keeping device structures intact. Using this method, we have investigated electronic states and potential distribution in gate metal/HfO{sub 2} gate stack structures under device operation. Analysis of the core levels shifts as a function of the bias voltage indicated that a potential drop occurred at the Pt/HfO{sub 2} interface for a Pt/HfO{sub 2} gate structure, while a potential gradient was not observed at the Ru/HfO{sub 2} interface for a Ru/HfO{sub 2} gate structure. Angle resolved photoelectron spectroscopy revealed that a thicker SiO{sub 2} layer was formed at the Pt/HfO{sub 2} interface, indicating that the origin of potential drop at Pt/HfO{sub 2} interface is formation of the thick SiO{sub 2} layer at the interface. The formation of the thick SiO{sub 2} layer at the metal/high-k interface might concern the Fermi level pinning, which is observed in metal/high-k gate stack structures.

  15. Si-compatible candidates for high-K dielectrics with the Pbnm perovskite structure

    SciTech Connect

    Coh, Sinisa; Heeg, Tassilo; Haeni, Jeffery; Biegalski, Michael D; Letteri, James; Bernhagen, M; Reiche, Paul; O'brien, Kevin; Uecker, Rinhold; Trolier-McKinstry, Susan; Schlom, Darrell; Vanderbilt, David

    2010-01-01

    We analyze both experimentally (where possible) and theoretically from first-principles the dielectric tensor components and crystal structure of five classes of Pbnm perovskites. All of these materials are believed to be stable on silicon and are therefore promising candidates for high-K dielectrics. We also analyze the structure of these materials with various simple models, decompose the lattice contribution to the dielectric tensor into force constant matrix eigenmode contributions, explore a peculiar correlation between structural and dielectric anisotropies in these compounds and give phonon frequencies and infrared activities of those modes that are infrared-active. We find that CaZrO3, SrZrO3, LaHoO3, and LaYO3 are among the most promising candidates for high-K dielectrics among the compounds we considered.

  16. High-K isomers in transactinide nuclei close to N = 162

    SciTech Connect

    Prassa, V. Nikšić, T.; Vretenar, D.; Lu, Bing-Nan; Ackermann, D.

    2015-10-15

    Transactinide nuclei around neutron number N = 162 display axially deformed equilibrium shapes, as shown in our previous analysis [1] of constrained mean-field energy surfaces and collective excitation spectra. In the present study we are particularly interested in the occurrence of high-K isomers in the axially deformed isotopes of Rf (Z = 104), Sg (Z = 106), Hs (Z = 108), and Ds (Z = 110), with neutron number N = 160 − 166 and the effect of the N=162 closure on the structure and distribution of two-quasiparticle (2qp) states. The evolution of high-K isomers is analysed in a self-consistent axially-symmetric relativistic Hartree-Bogoliubov calculation using the blocking approximation with time-reversal symmetry breaking.

  17. A quantum Fredkin gate.

    PubMed

    Patel, Raj B; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C; Pryde, Geoff J

    2016-03-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently. PMID:27051868

  18. A quantum Fredkin gate

    PubMed Central

    Patel, Raj B.; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C.; Pryde, Geoff J.

    2016-01-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently. PMID:27051868

  19. Spatial resolution study and power calibration of the high-k scattering system on NSTX

    SciTech Connect

    Lee, W.; Park, H. K.; Cho, M. H.; Namkung, W.; Smith, D. R.; Domier, C. W.; Luhmann, N. C. Jr

    2008-10-15

    NSTX high-k scattering system has been extensively utilized in studying the microturbulence and coherent waves. An absolute calibration of the scattering system was performed employing a new millimeter-wave source and calibrated attenuators. One of the key parameters essential for the calibration of the multichannel scattering system is the interaction length. This interaction length is significantly different from the conventional one due to the curvature and magnetic shear effect.

  20. Origin of Indium Diffusion in High-k Oxide HfO2.

    PubMed

    Hu, Yaoqiao; Wang, Changhong; Dong, Hong; Wallace, Robert M; Cho, Kyeongjae; Wang, Wei-Hua; Wang, Weichao

    2016-03-23

    Indium (In) out-diffusion through high-k oxides severely undermines the thermal reliability of the next generation device of III-V/high-k based metal oxide semiconductor (MOS). To date, the microscopic mechanism of In diffusion is not yet fully understood. Here, we utilize angle resolved X-ray photoelectron spectroscopy (ARXPS) and density functional theory (DFT) to explore In diffusion in high-k oxide HfO2. Our ARXPS results confirm the In diffusion through as-prepared and annealed HfO2 grown on InP substrate. The theoretical results show that the In diffusion barrier is reduced to ∼0.88 eV in the presence of oxygen vacancies (VO), whereas this barrier is as high as ∼4.78 eV in pristine HfO2. Fundamentally, we found that the high feasibility of In diffusion is owing to In nonbonding with its neighboring atoms. These findings can be extended to understand the In diffusion in other materials in addition to HfO2. PMID:26939534

  1. Candidates for long-lived high-K ground states in superheavy nuclei

    NASA Astrophysics Data System (ADS)

    Jachimowicz, P.; Kowal, M.; Skalski, J.

    2015-10-01

    On the basis of systematic calculations for 1364 heavy and superheavy (SH) nuclei, including odd systems, we have found a few candidates for high-K ground states in superheavy nuclei. The macroscopic-microscopic model based on the deformed Woods-Saxon single-particle potential that we use offers a reasonable description of SH systems, including known nuclear masses, Qα values, fission barriers, ground state (g.s.) deformations, and super- and hyperdeformed minima in the heaviest nuclei. Exceptionally untypical high-K intruder contents of the g.s. found for some nuclei, accompanied by a sizable excitation of the parent configuration in the daughter, suggest a dramatic hindrance of the α decay. Multidimensional hypercube configuration-constrained calculations of the potential energy surfaces (PESs) for one especially promising candidate, 272Mt, shows a ⋍ 6 MeV increase in the fission barrier above the configuration-unconstrained barrier. There is a possibility that one such high-K ground or low-lying state may be the longest-lived superheavy isotope.

  2. Tailoring Dielectric Properties and Energy Density of Ferroelectric Polymer Nanocomposites by High-k Nanowires.

    PubMed

    Wang, Guanyao; Huang, Xingyi; Jiang, Pingkai

    2015-08-19

    High dielectric constant (k) polymer nanocomposites have shown great potential in dielectric and energy storage applications in the past few decades. The introduction of high-k nanomaterials into ferroelectric polymers has proven to be a promising strategy for the fabrication of high-k nanocomposites. One-dimensional large-aspect-ratio nanowires exhibit superiority in enhancing k values and energy density of polymer nanocomposites in comparison to their spherical counterparts. However, the impact of their intrinsic properties on the dielectric properties of polymer nanocomposites has been seldom investigated. Herein, four kinds of nanowires (Na2Ti3O7, TiO2, BaTiO3, and SrTiO3) with different inherent characteristics are elaborately selected to fabricate high-k ferroelectric polymer nanocomposites. Dopamine functionalization facilitates the excellent dispersion of these nanowires in the ferroelectric polymer matrix because of the strong polymer/nanowire interfacial adhesion. A thorough comparative study on the dielectric properties and energy storage capability of the nanowires-based nanocomposites has been presented. The results reveal that, among the four types of nanowires, BaTiO3 NWs show the best potential in improving the energy storage capability of the proposed nanocomposites, resulting from the most signficant increase of k while retaining the rather low dielectric loss and leakage current. PMID:26225887

  3. Mechanisms of Ca uptake in high K/low Na solutions

    SciTech Connect

    Lodge, N.J.; Gelband, H.

    1986-03-05

    Ca uptake into neonatal rat atrium was measured with /sup 45/Ca. Extracellular /sup 45/Ca was displaced by washing tissues (45 min) in ice-cold Tyrode's containing 6.8 mM Ca/5 mM EGTA. Unless otherwise stated, solutions were pH balanced with HCO/sub 3//PO/sub 4//CO/sub 2/. Solutions in which 129 mM K or choline were substituted for 129 mM Na significantly stimulated Ca uptake (p < 0.001 for both). Inhibition of the Na/K pump (0 mM K solution), to increase intracellular Na, increased subsequent Ca uptakes measured in control, choline/low Na and high K/low Na solutions. The choline/low Na-stimulated uptake was increased by 104% while the high K/low Na stimulated uptake was increased only 11%. Cadmium (0.01-10 mM) blockade of the choline/low Na and high K/low Na uptakes was tested. Hepes buffered (HCO/sub 3//PO/sub 4//CO/sub 2/-free) solutions were used to avoid precipitation of Cd salts. The high K/low Na (Hepes) uptake was significantly (p < 0.001) greater than control and was 50% inhibited by 0.3 mM Cd. Choline/low Na in Hepes buffer increased Ca uptake only 5.1 +/- 4.3 ..mu..mol/kg (n=22) above control. In separate experiments, the choline/low Na (Hepes)-stimulated uptake (12.8 +/- 4.3 ..mu..mol/kg, n=8) was increased to 29.3 +/- 4.7 ..mu..mol/kg (n=8) by the addition of 1.8 mM PO/sub 4/. This intervention reduced the high K/low Na (Hepes)-stimulated uptake (47.1 +/- 6.4 ..mu..mol/kg, n=8) to 33.8 +/- 4.5 ..mu..mol/kg (n=8). They hypothesize that the uptake of Ca, induced by solutions of elevated K and lowered Na, is mediated by a minimum of two mechanisms; one stimulated by PO/sub 4/ and sensitive to transmembrane ion gradients, the other reduced by PO/sub 4/ and relatively insensitive to ion gradients.

  4. Low leakage current gate dielectrics prepared by ion beam assisted deposition for organic thin film transistors

    NASA Astrophysics Data System (ADS)

    Kim, Chang Su; Jo, Sung Jin; Kim, Jong Bok; Ryu, Seung Yoon; Noh, Joo Hyon; Baik, Hong Koo; Lee, Se Jong; Kim, Youn Sang

    2007-12-01

    This communication reports on the fabrication of low operating voltage pentacene thin-film transistors with high-k gate dielectrics by ion beam assisted deposition (IBAD). These densely packed dielectric layers by IBAD show a much lower level of leakage current than those created by e-beam evaporation. These results, from the fact that those thin films deposited with low adatom mobility, have an open structure, consisting of spherical grains with pores in between, that acts as a significant path for leakage current. By contrast, our results demonstrate the potential to limit this leakage. The field effect mobility, on/off current ratio, and subthreshold slope obtained from pentacene thin-film transistors (TFTs) were 1.14 cm2/V s, 105, and 0.41 V/dec, respectively. Thus, the high-k gate dielectrics obtained by IBAD show promise in realizing low leakage current, low voltage, and high mobility pentacene TFTs.

  5. Enhancement mode AlGaN/GaN MOS high-electron-mobility transistors with ZrO2 gate dielectric deposited by atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Anderson, Travis J.; Wheeler, Virginia D.; Shahin, David I.; Tadjer, Marko J.; Koehler, Andrew D.; Hobart, Karl D.; Christou, Aris; Kub, Francis J.; Eddy, Charles R., Jr.

    2016-07-01

    Advanced applications of AlGaN/GaN high-electron-mobility transistors (HEMTs) in high-power RF and power switching are driving the need for insulated gate technology. We present a metal–oxide–semiconductor (MOS) gate structure using atomic-layer-deposited ZrO2 as a high-k, high-breakdown gate dielectric for reduced gate leakage and a recessed barrier structure for enhancement mode operation. Compared to a Schottky metal-gate HEMT, the recessed MOS-HEMT structure demonstrated a reduction in the gate leakage current by 4 orders of magnitude and a threshold voltage shift of +6 V to a record +3.99 V, enabled by a combination of a recessed barrier structure and negative oxide charge.

  6. ONE SHAKE GATE FORMER

    DOEpatents

    Kalibjian, R.; Perez-Mendez, V.

    1957-08-20

    An improved circuit for forming square pulses having substantially short and precise durations is described. The gate forming circuit incorporates a secondary emission R. F. pentode adapted to receive input trigger pulses amd having a positive feedback loop comnected from the dynode to the control grid to maintain conduction in response to trigger pulses. A short circuited pulse delay line is employed to precisely control the conducting time of the tube and a circuit for squelching spurious oscillations is provided in the feedback loop.

  7. Tide gate valve

    SciTech Connect

    Raftis, S. G.

    1985-01-08

    A tide gate check valve in which at least three converging sides are provided at a tapered region of a flexible sleeve, so that on reverse back pressure build-up of fluid, reverse fluid flow is prevented, while the valve sleeve does not invert or collapse. The present configuration features embedded reinforcing elements for resisting inversion or collapsing when the back pressure builds up. This feature is especially important for large-sized conduits of 36'' or 72'' diameter, or even larger, such as are common in storm sewer applications.

  8. Compact gate valve

    DOEpatents

    Bobo, Gerald E.

    1977-01-01

    This invention relates to a double-disc gate valve which is compact, comparatively simple to construct, and capable of maintaining high closing pressures on the valve discs with low frictional forces. The valve casing includes axially aligned ports. Mounted in the casing is a sealed chamber which is pivotable transversely of the axis of the ports. The chamber contains the levers for moving the valve discs axially, and an actuator for the levers. When an external drive means pivots the chamber to a position where the discs are between the ports and axially aligned therewith, the actuator for the levers is energized to move the discs into sealing engagement with the ports.

  9. 3. TAINTER GATES (LEFT FOREGROUND) AND ROLLING SECTOR GATE AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    3. TAINTER GATES (LEFT FOREGROUND) AND ROLLING SECTOR GATE AND SPILLWAY (BACKGROUND) OF THE NORTH CHANNEL DAM, LOOKING SOUTH. - Washington Water Power Company Post Falls Power Plant, North Channel Dam, West of intersection of Spokane & Fourth Streets, Post Falls, Kootenai County, ID

  10. 16. Little Hell Gate Bridge with Big Hell Gate Bridge ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    16. Little Hell Gate Bridge with Big Hell Gate Bridge in background. Wards Island, New York Co., NY. Sec. 4207, MP 8.02. - Northeast Railroad Corridor, Amtrak Route between New Jersey/New York & New York/Connecticut State Lines, New York County, NY

  11. 14. DETAIL: Gate recess at east gate area. Planking of ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    14. DETAIL: Gate recess at east gate area. Planking of chamber walls and spikes (rear corner) are clearly visible. - Wabash & Erie Canal, Lock No. 2, 8 miles east of Fort Wayne, adjacent to U.S. Route 24, New Haven, Allen County, IN

  12. Radial gate hoist mechanisms mounted above radial gates, view to ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    Radial gate hoist mechanisms mounted above radial gates, view to the east - Wellton-Mohawk Irrigation System, Wasteway No. 1, Wellton-Mohawk Canal, North side of Wellton-Mohawk Canal, bounded by Gila River to North & the Union Pacific Railroad & Gila Mountains to south, Wellton, Yuma County, AZ

  13. 12. INTERIOR VIEW OF GATE OPERATOR ROOM, SHOWING SLIDES GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    12. INTERIOR VIEW OF GATE OPERATOR ROOM, SHOWING SLIDES GATE OPERATORS, LOOKING NORTHWEST. - Sacramento River Water Treatment Plant Intake Pier & Access Bridge, Spanning Sacramento River approximately 175 feet west of eastern levee on river; roughly .5 mile downstream from confluence of Sacramento & American Rivers, Sacramento, Sacramento County, CA

  14. 5. GATE 5, INTAKE CHANNEL LOOKING SOUTH; WATER FROM GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    5. GATE 5, INTAKE CHANNEL LOOKING SOUTH; WATER FROM GATE 5 ENTERED DITCH AND IRRIGATED HONDIUS' FIELDS. - Hondius Water Line, 1.6 miles Northwest of Park headquarters building & 1 mile Northwest of Beaver Meadows entrance station, Estes Park, Larimer County, CO

  15. A novel optical gating method for laser gated imaging

    NASA Astrophysics Data System (ADS)

    Ginat, Ran; Schneider, Ron; Zohar, Eyal; Nesher, Ofer

    2013-06-01

    For the past 15 years, Elbit Systems is developing time-resolved active laser-gated imaging (LGI) systems for various applications. Traditional LGI systems are based on high sensitive gated sensors, synchronized to pulsed laser sources. Elbit propriety multi-pulse per frame method, which is being implemented in LGI systems, improves significantly the imaging quality. A significant characteristic of the LGI is its ability to penetrate a disturbing media, such as rain, haze and some fog types. Current LGI systems are based on image intensifier (II) sensors, limiting the system in spectral response, image quality, reliability and cost. A novel propriety optical gating module was developed in Elbit, untying the dependency of LGI system on II. The optical gating module is not bounded to the radiance wavelength and positioned between the system optics and the sensor. This optical gating method supports the use of conventional solid state sensors. By selecting the appropriate solid state sensor, the new LGI systems can operate at any desired wavelength. In this paper we present the new gating method characteristics, performance and its advantages over the II gating method. The use of the gated imaging systems is described in a variety of applications, including results from latest field experiments.

  16. High-k dielectrics on (100) and (110) n-InAs: Physical and electrical characterizations

    SciTech Connect

    Wang, C. H. Hsu, W. C.; Doornbos, G.; Astromskas, G.; Vellianitis, G.; Oxland, R.; Holland, M. C.; Passlack, M.; Huang, M. L.; Lin, C. H.; Hsieh, C. H.; Chang, Y. S.; Lee, T. L.; Chen, Y. Y.; Diaz, C. H.; Ramvall, P.; Lind, E.; Wernersson, L.-E.; Droopad, R.

    2014-04-15

    Two high-k dielectric materials (Al{sub 2}O{sub 3} and HfO{sub 2}) were deposited on n-type (100) and (110) InAs surface orientations to investigate physical properties of the oxide/semiconductor interfaces and the interface trap density (D{sub it}). X-ray photoelectron spectroscopy analyses (XPS) for native oxides of (100) and (110) as-grown n-InAs epi wafers show an increase in As-oxide on the (100) surface and an increase in InOx on the (110) surface. In addition, XPS analyses of high-k (Al{sub 2}O{sub 3} and HfO{sub 2}) on n-InAs epi show that the intrinsic native oxide difference between (100) and (110) epi surfaces were eliminated by applying conventional in-situ pre-treatment (TriMethyAluminium (TMA)) before the high-k deposition. The capacitance-voltage (C-V) characterization of HfO{sub 2} and Al{sub 2}O{sub 3} MOSCAPs on both types of n-InAs surfaces shows very similar C-V curves. The interface trap density (D{sub it}) profiles show D{sub it} minima of 6.1 × 10{sup 12}/6.5 × 10{sup 12} and 6.6 × 10{sup 12}/7.3 × 10{sup 12} cm{sup −2} eV{sup −1} for Al{sub 2}O{sub 3} and HfO{sub 2}, respectively for (100) and (110) InAs surfaces. The similar interface trap density (D{sub it}) on (100) and (110) surface orientation were observed, which is beneficial to future InAs FinFET device with both (100) and (110) surface channel orientations present.

  17. Penn State DOE GATE Program

    SciTech Connect

    Anstrom, Joel

    2012-08-31

    The Graduate Automotive Technology Education (GATE) Program at The Pennsylvania State University (Penn State) was established in October 1998 pursuant to an award from the U.S. Department of Energy (U.S. DOE). The focus area of the Penn State GATE Program is advanced energy storage systems for electric and hybrid vehicles.

  18. Gates Learns to Think Big

    ERIC Educational Resources Information Center

    Robelen, Erik W.

    2006-01-01

    This article discusses how the philanthropy of Microsoft Corp software magnate co-chairs, Bill Gates and his wife Melinda, are reshaping the American high school nowadays. Gates and his wife have put the issue on the national agenda like never before, with a commitment of more than 1.3 billion US dollars this decade toward the foundation's agenda…

  19. Responses of rat hippocampal slices in a high-K+ medium following in vivo global ischaemia.

    PubMed

    el-Sabban, F; Reid, K H; Edmonds, H L

    1998-01-01

    1. We hypothesized that burst activity induced in rat hippocampal tissue by a high-K+ medium in vitro would be increased by a previous episode of global ischaemia, severe enough to induce persistent neurological dysfunction. 2. Male Wistar rats that were subjected to 9 min of chest compression, sufficient to reduce blood pressure (BP) to zero, showed evidence of neurological damage attributed to a global ischaemic insult. Hindlimb function was impaired for 24-48 h and a susceptibility to sound-induced seizures was induced in 25 to 35 rats. The seizure susceptibility cleared spontaneously within 2 weeks in 10 of 25 rats. 3. Hippocampal slices from postischaemic rats were prepared, tested for viability and were then exposed to an 8.0 mmol/L K+ artificial cerebrospinal fluid in vitro. Spontaneous epileptiform bursting activity in the high-K+ medium was not increased. Instead, burst size decreased with time after ischaemia. 4. The decrement in bursting activity is attributed to loss of cellular activity or integrity. These changes correlate with functional changes described by others, but not necessarily to histologically verifiable cell death. The time course of these changes was remarkably long, continuing for almost 3 weeks. Thus, a less-than-lethal ischaemia appears to induce neuronal changes, possibly reversible, that continue for at least 20 days after the global ischaemic insult. PMID:9673437

  20. Elemental maps in human allantochorial placental vessels cells: 1. High K + and acetylcholine effects

    NASA Astrophysics Data System (ADS)

    Michelet-Habchi, C.; Barberet, Ph.; Dutta, R. K.; Guiet-Bara, A.; Bara, M.; Moretto, Ph.

    2003-09-01

    Regulation of vascular tone in the fetal extracorporeal circulation most likely depends on circulating hormones, local paracrine mechanisms and changes in membrane potential of vascular smooth muscle cells (VSMCs) and of vascular endothelial cells (VECs). The membrane potential is a function of the physiological activities of ionic channels (particularly, K + and Ca 2+ channels in these cells). These channels regulate the ionic distribution into these cells. Micro-particle induced X-ray emission (PIXE) analysis was applied to determine the ionic composition of VSMC and of VEC in the placental human allantochorial vessels in a physiological survival medium (Hanks' solution) modified by the addition of acetylcholine (ACh: which opens the calcium-sensitive K + channels, K Ca) and of high concentration of K + (which blocks the voltage-sensitive K + channels, K df). In VSMC (media layer), the addition of ACh induced no modification of the Na, K, Cl, P, S, Mg and Ca concentrations and high K + medium increased significantly the Cl and K concentrations, the other ion concentrations remaining constant. In endothelium (VEC), ACh addition implicated a significant increase of Na and K concentration, and high K + medium, a significant increase in Cl and K concentration. These results indicated the importance of K df, K Ca and K ATP channels in the regulation of K + intracellular distribution in VSMC and VEC and the possible intervention of a Na-K-2Cl cotransport and corroborated the previous electrophysiological data.

  1. Effects of papaverine on carbachol- and high K+-induced contraction in the bovine abomasum

    PubMed Central

    KANEDA, Takeharu; SAITO, Erika; KANDA, Hidenori; URAKAWA, Norimoto; SHIMIZU, Kazumasa

    2015-01-01

    The effects of papaverine on carbachol (CCh) -and high K+- induced contraction in the bovine abomasum were investigated. Papaverine inhibited CCh (1 µM) -and KCl (65 mM) -induced contractions in a concentration-dependent manner. Forskolin or sodium nitroprusside inhibited CCh-induced contractions in a concentration-dependent manner in association with increases in the cAMP or cGMP contents, whereas papaverine increased cGMP contents only at 30 µM. Changes in the extracellular Ca2+ from 1.5 mM to 7.5 mM reduced verapamil-induced relaxation in high K+-depolarized muscles, but papaverine-induced relaxation did not change. Futhermore, papaverine (30 µM) and NaCN (300 µM) decreased the creatine phosphate contents. These results suggest that the relaxing effects of papaverine on the bovine abomasum are mainly due to the inhibition of aerobic energy metabolism. PMID:26018357

  2. Influence of the octupole mode on nuclear high-K isomeric properties

    NASA Astrophysics Data System (ADS)

    Minkov, Nikolay; Walker, Phil

    2014-05-01

    The influence of quadrupole-octupole deformations on the energy and magnetic properties of high-K isomeric states in even-even actinide (U, Pu, Cm, Fm, No), rare-earth (Nd, Sm and Gd), and superheavy (^{270}\\text{Ds}) nuclei is examined within a deformed shell model with pairing interaction. The neutron two-quasiparticle (2qp) isomeric energies and magnetic dipole moments are calculated over a wide range in the plane of quadrupole and octupole deformations. In most cases the magnetic moments exhibit a pronounced sensitivity to the octupole deformation. At the same time, the calculations outline three different groups of nuclei: with pronounced, shallow, and missing minima in the 2qp energy surfaces with respect to the octupole deformation. The result indicates regions of nuclei with octupole softness as well as with possible octupole deformation in the high-K isomeric states. These findings show the need for further theoretical analysis as well as of detailed experimental measurements of magnetic moments in heavy deformed nuclei.

  3. Elementary reaction schemes for physical and chemical vapor deposition of transition metal oxides on silicon for high-k gate dielectric applications

    NASA Astrophysics Data System (ADS)

    Niu, D.; Ashcraft, R. W.; Kelly, M. J.; Chambers, J. J.; Klein, T. M.; Parsons, G. N.

    2002-05-01

    This article describes the kinetics of reactions that result in substrate consumption during formation of ultrathin transition metal oxides on silicon. Yttrium silicate films (˜40 Å) with an equivalent silicon dioxide thickness of ˜11 Å are demonstrated by physical vapor deposition (PVD) routes. Interface reactions that occur during deposition and during postdeposition treatment are observed and compared for PVD and chemical vapor deposition (CVD) yttrium oxides and CVD aluminum-oxide systems. Silicon diffusion, metal-silicon bond formation, and reactions involving hydroxides are proposed as critical processes in interface layer formation. For PVD of yttrium silicate, oxidation is thermally activated with an effective barrier of 0.3 eV, consistent with the oxidation of silicide being the rate-limited step. For CVD aluminum oxide, interface oxidation is consistent with a process limited by silicon diffusion into the deposited oxide layer.

  4. The influence of carbon doping on the performance of Gd{sub 2}O{sub 3} as high-k gate dielectric

    SciTech Connect

    Shekhter, P.; Yehezkel, S.; Shriki, A.; Eizenberg, M.; Chaudhuri, A. R.; Osten, H. J.; Laha, A.

    2014-12-29

    One of the approaches for overcoming the issue of leakage current in modern metal-oxide-semiconductor devices is utilizing the high dielectric constants of lanthanide based oxides. We investigated the effect of carbon doping directly into Gd{sub 2}O{sub 3} layers on the performance of such devices. It was found that the amount of carbon introduced into the dielectric is above the solubility limit; carbon atoms enrich the oxide-semiconductor interface and cause a significant shift in the flat band voltage of the stack. Although the carbon atoms slightly degrade this interface, this method has a potential for tuning the flat band voltage of such structures.

  5. Dry-etching properties of TiN for metal/high-k gate stack using BCl{sub 3}-based inductively coupled plasma

    SciTech Connect

    Kim, Dong-Pyo; Yang Xue; Woo, Jong-Chang; Um, Doo-Seung; Kim, Chang-Il

    2009-11-15

    The etch rate of TiN film and the selectivities of TiN/SiO{sub 2} and TiN/HfO{sub 2} were systematically investigated in Cl{sub 2}/BCl{sub 3}/Ar plasmas as functions of Cl{sub 2} flow rate, radio-frequency (rf) power, and direct-current (dc) bias voltage under different substrate temperatures of 10 and 80 degree sign C. The etch rate of TiN films increased with increasing Cl{sub 2} flow rate, rf power, and dc-bias voltage at a fixed substrate temperature. In addition, the etch rate of TiN films at 80 degree sign C were higher than that at 10 degree sign C when other plasma parameters were fixed. However, the selectivities of TiN/SiO{sub 2} and TiN/HfO{sub 2} showed different tendencies compared with etch-rate behavior as a function of rf power and dc bias voltage. The relative-volume densities of Ar (750.0 nm), Cl (725.2 nm), and Cl{sup +} (386.6 nm) were monitored with an optical-emission spectroscopy. When rf power increased, the relative-volume densities of all studied particles were increased. X-ray photoelectron spectroscopy was carried out to detect nonvolatile etch by-products from the surface, and nonvolatile peaks (TiCl{sub x} bonds) in Ti 2p and Cl 2p were observed due to their high melting points. Based on the experimental results, we can conclude that the TiN etch is dependent on the substrate temperature when other plasma parameters are fixed. This can be explained by the enhanced chemical pathway with the assistance of ion bombardment.

  6. Plasma-enhanced atomic layer deposition and etching of high-k gadolinium oxide

    SciTech Connect

    Vitale, Steven A.; Wyatt, Peter W.; Hodson, Chris J.

    2012-01-15

    Atomic layer deposition (ALD) of high-quality gadolinium oxide thin films is achieved using Gd(iPrCp){sub 3} and O{sub 2} plasma. Gd{sub 2}O{sub 3} growth is observed from 150 to 350 deg. C, though the optical properties of the film improve at higher temperature. True layer-by-layer ALD growth of Gd{sub 2}O{sub 3} occurred in a relatively narrow window of temperature and precursor dose. A saturated growth rate of 1.4 A/cycle was observed at 250 deg. C. As the temperature increases, high-quality films are deposited, but the growth mechanism appears to become CVD-like, indicating the onset of precursor decomposition. At 250 deg. C, the refractive index of the film is stable at {approx}1.80 regardless of other deposition conditions, and the measured dispersion characteristics are comparable to those of bulk Gd{sub 2}O{sub 3}. XPS data show that the O/Gd ratio is oxygen deficient at 1.3, and that it is also very hygroscopic. The plasma etching rate of the ALD Gd{sub 2}O{sub 3} film in a high-density helicon reactor is very low. Little difference is observed in etching rate between Cl{sub 2} and pure Ar plasmas, suggesting that physical sputtering dominates the etching. A threshold bias power exists below which etching does not occur; thus it may be possible to etch a metal gate material and stop easily on the Gd{sub 2}O{sub 3} gate dielectric. The Gd{sub 2}O{sub 3} film has a dielectric constant of about 16, exhibits low C-V hysteresis, and allows a 50 x reduction in gate leakage compared to SiO{sub 2}. However, the plasma enhanced atomic layer deposition (PE-ALD) process causes formation of an {approx}1.8 nm SiO{sub 2} interfacial layer, and generates a fixed charge of -1.21 x 10{sup 12} cm{sup -2}, both of which may limit use of PE-ALD Gd{sub 2}O{sub 3} as a gate dielectric.

  7. Ferroelectric gated electrical transport in CdS nanotetrapods.

    PubMed

    Fu, Wangyang; Qin, Shengyong; Liu, Lei; Kim, Tae-Hwan; Hellstrom, Sondra; Wang, Wenlong; Liang, Wenjie; Bai, Xuedong; Li, An-Ping; Wang, Enge

    2011-05-11

    Complex nanostructures such as branched semiconductor nanotetrapods are promising building blocks for next-generation nanoelectronics. Here we report on the electrical transport properties of individual CdS tetrapods in a field effect transistor (FET) configuration with a ferroelectric Ba(0.7)Sr(0.3)TiO(3) film as high-k, switchable gate dielectric. A cryogenic four-probe scanning tunneling microscopy (STM) is used to probe the electrical transport through individual nanotetrapods at different temperatures. A p-type field effect is observed at room temperature, owing to the enhanced gate capacitance coupling. And the reversible remnant polarization of the ferroelectric gate dielectric leads to a well-defined nonvolatile memory effect. The field effect is shown to originate from the channel tuning in the arm/core/arm junctions of nanotetrapods. At low temperature (8.5 K), the nanotetrapod devices exhibit a ferroelectric-modulated single-electron transistor (SET) behavior. The results illustrate how the characteristics of a ferroelectric such as switchable polarization and high dielectric constant can be exploited to control the functionality of individual three-dimensional nanoarchitectures. PMID:21513340

  8. Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs)

    NASA Astrophysics Data System (ADS)

    Choi, Woo Young; Lee, Hyun Kook

    2016-06-01

    The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

  9. Impact of post metal annealing on gate work function engineering for advanced MOS applications

    NASA Astrophysics Data System (ADS)

    Kumar, S. Sachin; Prasad, Amitesh; Sinha, Amrita; Raut, Pratikhya; Das, Palash; Mahato, S. S.; Mallik, S.

    2016-05-01

    Ultra thin HfO2 high-k gate dielectric has been deposited directly on strained Si0.81Ge0.19 by Atomic Layer Deposition (ALD) technique. The influence of different types of metal gate electrodes (Al, Au, Pt) on electrical characteristics of Metal-Oxide-Semiconductor capacitors has been studied. Our results show that the electrical characteristics of MOS device are highly dependent on the gate electrodes used. The dependency of electrical characteristics on post metal annealing was studied in detail. The measured flat band (Vfb) and hysteresis (ΔVfb) from high frequency C-V characteristics were used to study the pre-existing traps in the dielectric. Impact of PMA on interface state density (Dit), border trap density (Nbt) and oxide trap density (Qf/q) of high-k gate stack were also examined for all the devices. The Nbt and frequency dispersion significantly reduces to ~2.77x1010 cm-2 and ~11.34 % respectively in case of Al electrode with a Dit value of ~4x1012 eV-1cm-2 after PMA (350°C) in N2, suggesting an improvement in device performance while Pt electrode shows a much less value of ΔVfb (~0.02 V) and Dit (~3.44x1012 eV-1cm-2) after PMA.

  10. 1500 Gate standard cell compatible radiation hard gate array

    SciTech Connect

    Mills, B.D.; Shafer, B.D.; Melancon, E.P.

    1984-11-01

    The G1500 gate array combines Sandia Labs' 4/3..mu.. CMOS silicon gate radiation hard process with a novel gate isolated standard cell compatible design for quick turnaround time, low cost, and radiation hardness. This device is hard to 5 x 10/sup 5/ rads, utilizes a configuration that provides high packing density, and is supported on both the Daisy and Mentor workstations. This paper describes Sandia Labs' radiation hard 4/3..mu.. process, the G1500's unique design, and the complete design capabilities offered by the workstations.

  11. Defectivity control of aluminum chemical mechanical planarization in replacement metal gate process of MOSFET

    NASA Astrophysics Data System (ADS)

    Jin, Zhang; Yuling, Liu; Chenqi, Yan; Yangang, He; Baohong, Gao

    2016-04-01

    The replacement metal gate (RMG) defectivity performance control is very challenging in high-k metal gate (HKMG) chemical mechanical polishing (CMP). In this study, three major defect types, including fall-on particles, micro-scratch and corrosion have been investigated. The research studied the effects of polishing pad, pressure, rotating speed, flow rate and post-CMP cleaning on the three kinds of defect, which finally eliminated the defects and achieved good surface morphology. This study will provide an important reference value for the future research of aluminum metal gate CMP. Project supported by the Major National Science and Technology Special Projects (No. 2009ZX02308), the Natural Science Foundation for the Youth of Hebei Province (Nos. F2012202094, F2015202267), and the Outstanding Youth Science and Technology Innovation Fund of Hebei University of Technology (No. 2013010).

  12. A charge transport study in diamond, surface passivated by high-k dielectric oxides

    SciTech Connect

    Kovi, Kiran Kumar Majdi, Saman; Gabrysch, Markus; Isberg, Jan

    2014-11-17

    The recent progress in the growth of high-quality single-crystalline diamond films has sparked interest in the realization of efficient diamond power electronic devices. However, finding a suitable passivation is essential to improve the reliability and electrical performance of devices. In the current work, high-k dielectric materials such as aluminum oxide and hafnium oxide were deposited by atomic layer deposition on intrinsic diamond as a surface passivation layer. The hole transport properties in the diamond films were evaluated and compared to unpassivated films using the lateral time-of-flight technique. An enhancement of the near surface hole mobility in diamond films of up to 27% is observed when using aluminum oxide passivation.

  13. Theory of an improved vertical power MOSFET using high-k insulator

    NASA Astrophysics Data System (ADS)

    Huang, Mingmin; Chen, Xingbi

    2015-12-01

    An improved structure of the vertical power MOSFET using high-k insulator (Hk-MOSFET), which has a better relationship between specific on-resistance (Ron) and breakdown voltage (VB) than the conventional Hk-MOSFET and the superjunction MOSFET, is studied. An analytic model of this improved Hk-MOSFET is proposed, which can be used to well explain the physical reason of the improvement as well as to obtain an optimal design. It is found that the theoretical results match well with the numerical simulation results, where the errors of VB and Ron are both less than 7%. Moreover, the numerical simulation results show that, with the guidance of the proposed analytic model, Ron of the improved Hk-MOSFET can be optimized to be about 30%-50% lower than that of the conventional Hk-MOSFET with VB = 300-1000 V.

  14. Graphene liquid crystal retarded percolation for new high-k materials

    PubMed Central

    Yuan, Jinkai; Luna, Alan; Neri, Wilfrid; Zakri, Cécile; Schilling, Tanja; Colin, Annie; Poulin, Philippe

    2015-01-01

    Graphene flakes with giant shape anisotropy are extensively used to establish connectedness electrical percolation in various heterogeneous systems. However, the percolation behaviour of graphene flakes has been recently predicted to be far more complicated than generally anticipated on the basis of excluded volume arguments. Here we confirm experimentally that graphene flakes self-assemble into nematic liquid crystals below the onset of percolation. The competition of percolation and liquid crystal transition provides a new route towards high-k materials. Indeed, near-percolated liquid-crystalline graphene-based composites display unprecedented dielectric properties with a dielectric constant improved by 260-fold increase as compared with the polymer matrix, while maintaining the loss tangent as low as 0.4. This performance is shown to depend on the structure of monodomains of graphene liquid-crystalline phases. Insights into how the liquid crystal phase transition interferes with percolation transition and thus alters the dielectric constant are discussed. PMID:26567720

  15. Graphene liquid crystal retarded percolation for new high-k materials.

    PubMed

    Yuan, Jinkai; Luna, Alan; Neri, Wilfrid; Zakri, Cécile; Schilling, Tanja; Colin, Annie; Poulin, Philippe

    2015-01-01

    Graphene flakes with giant shape anisotropy are extensively used to establish connectedness electrical percolation in various heterogeneous systems. However, the percolation behaviour of graphene flakes has been recently predicted to be far more complicated than generally anticipated on the basis of excluded volume arguments. Here we confirm experimentally that graphene flakes self-assemble into nematic liquid crystals below the onset of percolation. The competition of percolation and liquid crystal transition provides a new route towards high-k materials. Indeed, near-percolated liquid-crystalline graphene-based composites display unprecedented dielectric properties with a dielectric constant improved by 260-fold increase as compared with the polymer matrix, while maintaining the loss tangent as low as 0.4. This performance is shown to depend on the structure of monodomains of graphene liquid-crystalline phases. Insights into how the liquid crystal phase transition interferes with percolation transition and thus alters the dielectric constant are discussed. PMID:26567720

  16. Graphene liquid crystal retarded percolation for new high-k materials

    NASA Astrophysics Data System (ADS)

    Yuan, Jinkai; Luna, Alan; Neri, Wilfrid; Zakri, Cécile; Schilling, Tanja; Colin, Annie; Poulin, Philippe

    2015-11-01

    Graphene flakes with giant shape anisotropy are extensively used to establish connectedness electrical percolation in various heterogeneous systems. However, the percolation behaviour of graphene flakes has been recently predicted to be far more complicated than generally anticipated on the basis of excluded volume arguments. Here we confirm experimentally that graphene flakes self-assemble into nematic liquid crystals below the onset of percolation. The competition of percolation and liquid crystal transition provides a new route towards high-k materials. Indeed, near-percolated liquid-crystalline graphene-based composites display unprecedented dielectric properties with a dielectric constant improved by 260-fold increase as compared with the polymer matrix, while maintaining the loss tangent as low as 0.4. This performance is shown to depend on the structure of monodomains of graphene liquid-crystalline phases. Insights into how the liquid crystal phase transition interferes with percolation transition and thus alters the dielectric constant are discussed.

  17. Gate protective device for insulated gate field-effect transistors

    NASA Technical Reports Server (NTRS)

    Sunshine, R. A.

    1972-01-01

    Device, which protects insulated gate field-effect transistors, improves reliability through utilization of layers of conductive material on top of each alternating semiconductor material region. Separation of layers is necessary to prevent shorting out junctions between alternating regions.

  18. Reversible logic gates on Physarum Polycephalum

    SciTech Connect

    Schumann, Andrew

    2015-03-10

    In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum.

  19. 49 CFR 234.223 - Gate arm.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 49 Transportation 4 2012-10-01 2012-10-01 false Gate arm. 234.223 Section 234.223 Transportation... SYSTEMS Maintenance, Inspection, and Testing Maintenance Standards § 234.223 Gate arm. Each gate arm, when... maintained in a condition sufficient to be clearly viewed by approaching highway users. Each gate arm...

  20. 49 CFR 234.223 - Gate arm.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... 49 Transportation 4 2013-10-01 2013-10-01 false Gate arm. 234.223 Section 234.223 Transportation... SYSTEMS Maintenance, Inspection, and Testing Maintenance Standards § 234.223 Gate arm. Each gate arm, when... maintained in a condition sufficient to be clearly viewed by approaching highway users. Each gate arm...

  1. 49 CFR 234.223 - Gate arm.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 49 Transportation 4 2014-10-01 2014-10-01 false Gate arm. 234.223 Section 234.223 Transportation... SYSTEMS Maintenance, Inspection, and Testing Maintenance Standards § 234.223 Gate arm. Each gate arm, when... maintained in a condition sufficient to be clearly viewed by approaching highway users. Each gate arm...

  2. 49 CFR 234.223 - Gate arm.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 49 Transportation 4 2011-10-01 2011-10-01 false Gate arm. 234.223 Section 234.223 Transportation... Maintenance Standards § 234.223 Gate arm. Each gate arm, when in the downward position, shall extend across... clearly viewed by approaching highway users. Each gate arm shall start its downward motion not less...

  3. 49 CFR 234.223 - Gate arm.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Gate arm. 234.223 Section 234.223 Transportation... Maintenance Standards § 234.223 Gate arm. Each gate arm, when in the downward position, shall extend across... clearly viewed by approaching highway users. Each gate arm shall start its downward motion not less...

  4. Multiple gates on working memory

    PubMed Central

    Chatham, Christopher H; Badre, David

    2015-01-01

    The contexts for action may be only transiently visible, accessible, and relevant. The corticobasal ganglia (BG) circuit addresses these demands by allowing the right motor plans to drive action at the right times, via a BG-mediated gate on motor representations. A long-standing hypothesis posits these same circuits are replicated in more rostral brain regions to support gating of cognitive representations. Key evidence now supports the prediction that BG can act as a gate on the input to working memory, as a gate on its output, and as a means of reallocating working memory representations rendered irrelevant by recent events. These discoveries validate key tenets of many computational models, circumscribe motor and cognitive models of recurrent cortical dynamics alone, and identify novel directions for research on the mechanisms of higher-level cognition. PMID:26719851

  5. Shortcut to adiabatic gate teleportation

    NASA Astrophysics Data System (ADS)

    Santos, Alan C.; Silva, Raphael D.; Sarandy, Marcelo S.

    2016-01-01

    We introduce a shortcut to the adiabatic gate teleportation model of quantum computation. More specifically, we determine fast local counterdiabatic Hamiltonians able to implement teleportation as a universal computational primitive. In this scenario, we provide the counterdiabatic driving for arbitrary n -qubit gates, which allows to achieve universality through a variety of gate sets. Remarkably, our approach maps the superadiabatic Hamiltonian HSA for an arbitrary n -qubit gate teleportation into the implementation of a rotated superadiabatic dynamics of an n -qubit state teleportation. This result is rather general, with the speed of the evolution only dictated by the quantum speed limit. In particular, we analyze the energetic cost for different Hamiltonian interpolations in the context of the energy-time complementarity.

  6. The Gates, 1979-2005

    ERIC Educational Resources Information Center

    School Arts: The Art Education Magazine for Teachers, 2005

    2005-01-01

    One art critic called it pure Despite the mixed reviews of Christo and Jeanne-Claude's temporary art installation in New York's Central Park, the public reaction to The Gates was largely positive.The Gates consisted of 7,500 orange PVC frames straddling the park's walkways that varied in widths from 5 1/2 feet to 18 feet. Eight-foot-long ripstop…

  7. A molecular logic gate

    PubMed Central

    Kompa, K. L.; Levine, R. D.

    2001-01-01

    We propose a scheme for molecule-based information processing by combining well-studied spectroscopic techniques and recent results from chemical dynamics. Specifically it is discussed how optical transitions in single molecules can be used to rapidly perform classical (Boolean) logical operations. In the proposed way, a restricted number of states in a single molecule can act as a logical gate equivalent to at least two switches. It is argued that the four-level scheme can also be used to produce gain, because it allows an inversion, and not only a switching ability. The proposed scheme is quantum mechanical in that it takes advantage of the discrete nature of the energy levels but, we here discuss the temporal evolution, with the use of the populations only. On a longer time range we suggest that the same scheme could be extended to perform quantum logic, and a tentative suggestion, based on an available experiment, is discussed. We believe that the pumping can provide a partial proof of principle, although this and similar experiments were not interpreted thus far in our terms. PMID:11209046

  8. Latest design of gate valves

    SciTech Connect

    Kurzhofer, U.; Stolte, J.; Weyand, M.

    1996-12-01

    Babcock Sempell, one of the most important valve manufacturers in Europe, has delivered valves for the nuclear power industry since the beginning of the peaceful application of nuclear power in the 1960s. The latest innovation by Babcock Sempell is a gate valve that meets all recent technical requirements of the nuclear power technology. At the moment in the United States, Germany, Sweden, and many other countries, motor-operated gate and globe valves are judged very critically. Besides the absolute control of the so-called {open_quotes}trip failure,{close_quotes} the integrity of all valve parts submitted to operational forces must be maintained. In case of failure of the limit and torque switches, all valve designs have been tested with respect to the quality of guidance of the gate. The guidances (i.e., guides) shall avoid a tilting of the gate during the closing procedure. The gate valve newly designed by Babcock Sempell fulfills all these characteristic criteria. In addition, the valve has cobalt-free seat hardfacing, the suitability of which has been proven by friction tests as well as full-scale blowdown tests at the GAP of Siemens in Karlstein, West Germany. Babcock Sempell was to deliver more than 30 gate valves of this type for 5 Swedish nuclear power stations by autumn 1995. In the presentation, the author will report on the testing performed, qualifications, and sizing criteria which led to the new technical design.

  9. The Meaning of High K2O Volcanism In the U.S. Cordillera

    NASA Astrophysics Data System (ADS)

    Putirka, K. D.; Busby, C.

    2010-12-01

    K2O contents provide a highly effective discriminant between volcanic rocks erupted in the Cascades and Basin-and Range-provinces, with Cascades volcanics having lower K2O contents at a given SiO2. To differentiate these suites, we use a K-index, where K-index = K2Oobserved - 0.12[SiO2] + 5.1 (oxides in wt. %). In the Sierra Nevada, regional K2O contents are not controlled by wall-rock assimilation. In addition, none are candidates for K-metasomatism, and none are likely to be derived by partial melting of a K-metasomatized source. As to the latter issue, even volcanic rocks with the highest K2O in the Sierra Nevada have K2O/Na2O <5, and most such ratios are <3. In contrast, K-metasomatized rocks have K2O/Na2O >5, and as high as 30-40 (Brooks and Snee (1996). Also, Sierra-wide K2O variations are not connected to indices of subduction-related mantle enrichments (such as La/Nb, Ba/Nb or Sr/P2O5), and so K2O is unconnected to regional variations in source composition. K2O contents are instead controlled by the degree of partial melting (F) in the mantle source and fractional crystallization. Putirka and Busby (2007) show that maximum K2O in the Sierra increases with increasing crust thickness, and this relationship also holds across the U.S. the Cordillera (at 39oN latitude). This relationship implies that low F magmas more easily transit thick, low-density upper crust (Putirka and Busby, 2007), which is a consequence of the fact that low F melts are enriched not just in K2O, but also in H2O, which greatly lowers magma density (Ochs and Lange, 1999). This model can explain the contrast in Cascade and Basin-and-Range K2O contents: the modern Cascades are built on the thinner crust of accreted terranes, while typical Basin-and-Range volcanics are erupted on older, and thicker, cratonized crust. Mean crust density, however, cannot be the only explanation of high K2O. In the central Sierra Nevada, the Colorado River Extensional Corridor, and at the Lunar Crater

  10. Nonvolatile Quantum Dot Gate Memory (NVQDM): Tunneling Rate from Quantum Well Channel to Quantum Dot Gate

    NASA Astrophysics Data System (ADS)

    Hasaneen, El-Sayed; Heller, Evan; Bansal, Rajeev; Jain, Faquir

    2003-10-01

    In this paper, we compute the tunneling of electrons in a nonvolatile quantum dot memory (NVQDM) cell during the WRITE operation. The transition rate of electrons from a quantum well channel to the quantum dots forming the floating gate is calculated using a recently reported method by Chuang et al.[1]. Tunneling current is computed based on transport of electrons from the channel to the floating quantum dots. The maximum number of electrons on a dot is calculated using surface electric field and break down voltage of the tunneling dielectric material. Comparison of tunneling for silicon oxide and high-k dielectric gate insulators is also described. Capacitance-Voltage characteristics of a NVQDM device are calculated by solving the Schrodinger and Poisson equations self-consistently. In addition, the READ operation of the memory has been investigated analytically. Results for 70 nm channel length Si NVQDMs are presented. Threshold voltage is calculated including the effect of the charge on nanocrystal quantum dots. Current-voltage characteristics are obtained using BSIM3v3 model [2-3]. This work is supported by Office of Navel Research (N00014210883, Dr. D. Purdy, Program Monitor), Connecticut Innovations Inc./TranSwitch (CII # 00Y17), and National Science Foundation (CCR-0210428) grants. [1] S. L. Chuang and N. Holonyak, Appl. Phys. Lett., 80, pp. 1270, 2002. [2] Y. Chen et. al., BSIM3v3 Manual, Elect. Eng. and Comp. Dept., U. California, Berkeley, CA, 1996. [3] W. Liu, MOSFET Models for SPICE Simulation, John Wiley & Sons, Inc., 2001.