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Sample records for high speed cmos

  1. A CMOS high speed imaging system design based on FPGA

    NASA Astrophysics Data System (ADS)

    Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

    2015-10-01

    CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

  2. High-speed multicolour photometry with CMOS cameras

    NASA Astrophysics Data System (ADS)

    Pokhvala, S. M.; Zhilyaev, B. E.; Reshetnyk, V. M.

    2012-11-01

    We present the results of testing the commercial digital camera Nikon D90 with a CMOS sensor for high-speed photometry with a small telescope Celestron 11'' at the Peak Terskol Observatory. CMOS sensor allows to perform photometry in 3 filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system of CMOS sensors is close to the Johnson BVR system. The results of testing show that one can carry out photometric measurements with CMOS cameras for stars with the V-magnitude up to ≃14^{m} with the precision of 0.01^{m}. Stars with the V-magnitude up to ˜10 can be shot at 24 frames per second in the video mode.

  3. Envelope tracking CMOS power amplifier with high-speed CMOS envelope amplifier for mobile handsets

    NASA Astrophysics Data System (ADS)

    Yoshida, Eiji; Sakai, Yasufumi; Oishi, Kazuaki; Yamazaki, Hiroshi; Mori, Toshihiko; Yamaura, Shinji; Suto, Kazuo; Tanaka, Tetsu

    2014-01-01

    A high-efficiency CMOS power amplifier (PA) based on envelope tracking (ET) has been reported for a wideband code division multiple access (W-CDMA) and long term evolution (LTE) application. By adopting a high-speed CMOS envelope amplifier with current direction sensing, a 5% improvement in total power-added efficiency (PAE) and a 11 dB decrease in adjacent channel leakage ratio (ACLR) are achieved with a W-CDMA signal. Moreover, the proposed PA achieves a PAE of 25.4% for a 10 MHz LTE signal at an output power (Pout) of 25.6 dBm and a gain of 24 dB.

  4. A high speed CMOS A/D converter

    NASA Technical Reports Server (NTRS)

    Wiseman, Don R.; Whitaker, Sterling R.

    1992-01-01

    This paper presents a high speed analog-to-digital (A/D) converter. The converter is a 7 bit flash converter with one half LSB accuracy. Typical parts will function at approximately 200 MHz. The converter uses a novel comparator circuit that is shown to out perform more traditional comparators, and thus increases the speed of the converter. The comparator is a clocked, precharged circuit that offers very fast operation with a minimal offset voltage (2 mv). The converter was designed using a standard 1 micron digital CMOS process and is 2,244 microns by 3,972 microns.

  5. Precision of FLEET Velocimetry Using High-speed CMOS Camera Systems

    NASA Technical Reports Server (NTRS)

    Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

    2015-01-01

    Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 micro sec, precisions of 0.5 m/s in air and 0.2 m/s in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision High Speed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

  6. Precision of FLEET Velocimetry Using High-Speed CMOS Camera Systems

    NASA Technical Reports Server (NTRS)

    Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

    2015-01-01

    Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 microseconds, precisions of 0.5 meters per second in air and 0.2 meters per second in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision HighSpeed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

  7. A CMOS image sensor using high-speed lock-in pixels for stimulated Raman scattering

    NASA Astrophysics Data System (ADS)

    Lioe, DeXing; Mars, Kamel; Takasawa, Taishi; Yasutomi, Keita; Kagawa, Keiichiro; Hashimoto, Mamoru; Kawahito, Shoji

    2016-03-01

    A CMOS image sensor using high-speed lock-in pixels for stimulated Raman scattering (SRS) spectroscopy is presented in this paper. The effective SRS signal from the stimulated emission of SRS mechanism is very small in contrast to the offset of a probing laser source, which is in the ratio of 10-4 to 10-5. In order to extract this signal, the common offset component is removed, and the small difference component is sampled using switched-capacitor integrator with a fully differential amplifier. The sampling is performed over many integration cycles to achieve appropriate amplification. The lock-in pixels utilizes high-speed lateral electric field charge modulator (LEFM) to demodulate the SRS signal which is modulated at high-frequency of 20MHz. A prototype chip is implemented using 0.11μm CMOS image sensor technology.

  8. A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Ye, Han; Quanliang, Li; Cong, Shi; Nanjian, Wu

    2013-08-01

    This paper presents a high-speed column-parallel cyclic analog-to-digital converter (ADC) for a CMOS image sensor. A correlated double sampling (CDS) circuit is integrated in the ADC, which avoids a stand-alone CDS circuit block. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.02 mm2 was implemented in a 0.13 μm CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively. The power consumption from 3.3 V supply is only 0.66 mW. An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels. The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.

  9. A High-Speed CMOS Image Sensor with Global Electronic Shutter Pixels Using Pinned Diodes

    NASA Astrophysics Data System (ADS)

    Yasutomi, Keita; Tamura, Toshihiro; Furuta, Masanori; Itoh, Shinya; Kawahito, Shoji

    This paper describes a high-speed CMOS image sensor with a new type of global electronic shutter pixel. A global electronic shutter is necessary for imaging fast-moving objects without motion blur or distortion. The proposed pixel has two potential wells with pinned diode structure for two-stage charge transfer that enables a global electronic shuttering and reset noise canceling. A prototype high-speed image sensor fabricated in 0.18μm standard CMOS image sensor process consists of the proposed pixel array, 12-bit column-parallel cyclic ADC arrays and 192-channel digital outputs. The sensor achieves a good linearity at low-light intensity, demonstrating the perfect charge transfer between two pinned diodes. The input referred noise of the proposed pixel is measured to be 6.3 e-.

  10. High-speed CMOS image sensor for high-throughput lensless microfluidic imaging system

    NASA Astrophysics Data System (ADS)

    Yan, Mei; Huang, Xiwei; Jia, Qixiang; Nadipalli, Revanth; Wang, Tongxi; Shang, Yang; Yu, Hao; Je, Minkyu; Yeo, Kiatseng

    2012-03-01

    The integration of CMOS image sensor and microfluidics becomes a promising technology for point-of-care (POC) diagnosis. However, commercial image sensors usually have limited speed and low-light sensitivity. One high-speed and high-sensitivity CMOS image sensor chip is introduced in this paper, targeted for high-throughput microfluidic imaging system. Firstly, high speed image sensor architecture is introduced with design of column-parallel single-slope analog-todigital converter (ADC) with digital correlated double sampling (CDS). The frame rate can be achieved to 2400 frames/second (fps) with resolution of 128×96 for high-throughput microfluidic imaging. Secondly, the designed system has superior low-light sensitivity, which is achieved by large pixel size (10μm×10μm, 56% fill factor). Pixel peak signalnoise- ratio (SNR) reaches to 50dB with 10dB improvement compared to the commercial pixel (2.2μm×2.2μm). The degradation of pixel resolution is compensated by super-resolution image processing algorithm. By reconstructing single image with multiple low-resolution frames, we can equivalently achieve 2μm resolution with physical 10μm pixel. Thirdly, the system-on-chip (SoC) integration results in a real-time controlled intelligent imaging system without expensive data storage and time-consuming computer analysis. This initial sensor prototype with timing-control makes it possible to develop high-throughput lensless microfluidic imaging system for POC diagnosis.

  11. High-speed bipolar phototransistors in a 180 nm CMOS process

    PubMed Central

    Kostov, P.; Gaberl, W.; Zimmermann, H.

    2013-01-01

    Several high-speed pnp phototransistors built in a standard 180 nm CMOS process are presented. The phototransistors were implemented in sizes of 40×40 μm2 and 100×100 μm2. Different base and emitter areas lead to different characteristics of the phototransistors. As starting material a p+ wafer with a p− epitaxial layer on top was used. The phototransistors were optically characterized at wavelengths of 410, 675 and 850 nm. Bandwidths up to 92 MHz and dynamic responsivities up to 2.95 A/W were achieved. Evaluating the results, we can say that the presented phototransistors are well suited for high speed photosensitive optical applications where inherent amplification is needed. Further on, the standard silicon CMOS implementation opens the possibility for cheap integration of integrated optoelectronic circuits. Possible applications for the presented phototransistors are low cost high speed image sensors, opto-couplers, etc. PMID:23847388

  12. High-speed bipolar phototransistors in a 180 nm CMOS process.

    PubMed

    Kostov, P; Gaberl, W; Zimmermann, H

    2013-03-01

    Several high-speed pnp phototransistors built in a standard 180 nm CMOS process are presented. The phototransistors were implemented in sizes of 40×40 μm(2) and 100×100 μm(2). Different base and emitter areas lead to different characteristics of the phototransistors. As starting material a p(+) wafer with a p(-) epitaxial layer on top was used. The phototransistors were optically characterized at wavelengths of 410, 675 and 850 nm. Bandwidths up to 92 MHz and dynamic responsivities up to 2.95 A/W were achieved. Evaluating the results, we can say that the presented phototransistors are well suited for high speed photosensitive optical applications where inherent amplification is needed. Further on, the standard silicon CMOS implementation opens the possibility for cheap integration of integrated optoelectronic circuits. Possible applications for the presented phototransistors are low cost high speed image sensors, opto-couplers, etc. PMID:23847388

  13. A high speed, low power consumption LVDS interface for CMOS pixel sensors

    NASA Astrophysics Data System (ADS)

    Shi, Zhan; Tang, Zhenan; Tian, Yong; Pham, Hung; Valin, Isabelle; Jaaskelainen, Kimmo

    2015-01-01

    The use of CMOS Pixel Sensors (CPSs) offers a promising approach to the design of vertex detectors in High Energy Physics (HEP) experiments. As the CPS equipping the upgraded Solenoidal Tracker at RHIC (STAR) pixel detector, ULTIMATE perfectly illustrates the potential of CPSs for HEP applications. However, further development of CPSs with respect to readout speed is required to fulfill the readout time requirement of the next generation HEP detectors, such as the upgrade of A Large Ion Collider Experiment (ALICE) Inner Tracking System (ITS), the International Linear Collider (ILC), and the Compressed Baryonic Matter (CBM) vertex detectors. One actual limitation of CPSs is related to the speed of the Low-Voltage Differential Signaling (LVDS) circuitry implementing the interface between the sensor and the Data Acquisition (DAQ) system. To improve the transmission rate while keeping the power consumption at a low level, a source termination technique and a special current comparator were adopted for the LVDS driver and receiver, respectively. Moreover, hardening techniques are used. The circuitry was designed and submitted for fabrication in a 0.18-μm CMOS Image Sensor (CIS) process at the end of 2011. The test results indicated that the LVDS driver and receiver can operate properly at the data rate of 1.2 Gb/s with power consumption of 19.6 mW.

  14. A low-power column-parallel ADC for high-speed CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Han, Ye; Li, Quanliang; Shi, Cong; Liu, Liyuan; Wu, Nanjian

    2013-08-01

    This paper presents a 10-bit low-power column-parallel cyclic analog-to-digital converter (ADC) used for high-speed CMOS image sensor (CIS). An opamp sharing technique is used to save power and area. Correlated double sampling (CDS) circuit and programmable gain amplifier (PGA) are integrated in the ADC, which avoids stand-alone circuit blocks. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.03mm2 was implemented in a 0.18μm 1P4M CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 2MS/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.62 LSB and 2.1 LSB together with CDS, respectively. The power consumption from 1.8V supply is only 0.36mW.

  15. A new high speed thermal imaging concept based on a logarithmic CMOS imager technology

    NASA Astrophysics Data System (ADS)

    Hutter, Franz X.; Brosch, Daniel; Burghartz, Joachim N.; Graf, Heinz-Gerd; Strobel, Markus

    2008-04-01

    HDRC (high dynamic range CMOS) allows for more than 120 dB signal range in image processing. Scene details with both very high and extremely low radiant flux may thus appear within the same image. Color constancy over the entire signal range and good high speed performance are further aspects of this logarithmic imager technology. These features qualify HDRC cameras for thermography, since the signal range of Planck's temperature radiation in a two dimensional array is comparable to HDRC's intensity range. Especially in material welding and laser cutting processes, in high power light sources and in high temperature material processing, fast monitoring of the spacial and dynamic temperature distributions present a challenge to conventional thermal imaging and thus call for innovative concepts. A particular challenge is in the compensation of the emissivity of the radiating surface. Here, we present a new concept based on a modified HDRC VGA color camera, allowing for visualization and measurement of temperatures from about 800 °C up to 2300 °C. The modifications include an optical filter for minimizing UV and IR straylight and a notch filter for clipping off the green optical range in order to separate the blue and red RGB regions. An enhanced and adapted software provides a division of the neighboured red and blue pixel signals by means of simply subtracting the HDRC signals. As a result the local temperature information of the visualized scene spot is independent of emissivity. This is, to our knowledge, the first demonstration of a high speed thermal imager to date.

  16. High-speed laser Doppler perfusion imaging using an integrating CMOS image sensor.

    PubMed

    Serov, Alexandre; Lasser, Theo

    2005-08-22

    This paper describes the design and the performance of a new high-speed laser Doppler imaging system for monitoring blood flow over an area of tissue. The new imager delivers high-resolution flow images (256x256 pixels) every 2 to 10 seconds, depending on the number of points in the acquired time-domain signal (32-512 points). This new imaging modality utilizes a digital integrating CMOS image sensor to detect Doppler signals in a plurality of points over the area illuminated by a divergent laser beam of a uniform intensity profile. The integrating property of the detector improves the signal-to-noise ratio of the measurements, which results in high-quality flow images. We made a series of measurements in vitro to test the performance of the system in terms of bandwidth, SNR, etc. Subsequently we give some examples of flow-related images measured on human skin, thus demonstrating the performance of the imager in vivo. The perspectives for future implementations of the imager for clinical and physiological applications are discussed. PMID:19498655

  17. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors

    PubMed Central

    Gao, Zhiyuan; Yang, Congjie; Xu, Jiangtao; Nie, Kaiming

    2015-01-01

    This paper presents a dynamic range (DR) enhanced readout technique with a two-step time-to-digital converter (TDC) for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA) structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within −Tclk~+Tclk. A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration. PMID:26561819

  18. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors.

    PubMed

    Gao, Zhiyuan; Yang, Congjie; Xu, Jiangtao; Nie, Kaiming

    2015-01-01

    This paper presents a dynamic range (DR) enhanced readout technique with a two-step time-to-digital converter (TDC) for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA) structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within -T(clk)~+T(clk). A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration. PMID:26561819

  19. High-Speed Scanning Interferometer Using CMOS Image Sensor and FPGA Based on Multifrequency Phase-Tracking Detection

    NASA Technical Reports Server (NTRS)

    Ohara, Tetsuo

    2012-01-01

    A sub-aperture stitching optical interferometer can provide a cost-effective solution for an in situ metrology tool for large optics; however, the currently available technologies are not suitable for high-speed and real-time continuous scan. NanoWave s SPPE (Scanning Probe Position Encoder) has been proven to exhibit excellent stability and sub-nanometer precision with a large dynamic range. This same technology can transform many optical interferometers into real-time subnanometer precision tools with only minor modification. The proposed field-programmable gate array (FPGA) signal processing concept, coupled with a new-generation, high-speed, mega-pixel CMOS (complementary metal-oxide semiconductor) image sensor, enables high speed (>1 m/s) and real-time continuous surface profiling that is insensitive to variation of pixel sensitivity and/or optical transmission/reflection. This is especially useful for large optics surface profiling.

  20. Novel CMOS time-delay integration using single-photon counting for high-speed industrial and aerospace applications

    NASA Astrophysics Data System (ADS)

    El-Desouki, Munir M.; Al-Azem, Badeea

    2014-03-01

    Time-delay integration (TDI) is a popular imaging technique that is used in many applications such as machine vision, dental scanning and satellite earth observation. One of the main advantages of using TDI imagers is the increased effective integration time that is achieved while maintaining high frame-rates. Another use for TDI imagers is with moving objects, such as the earth's surface or industrial machine vision applications, where integration time is limited in order to avoid motion blurs. Such technique may even find its way in mobile and consumer based imaging applications where the reduction in pixel size can limit the performance during low-light and high speed applications. Until recently, TDI was only used with charge-coupled devices (CCDs) mainly due to their charge transfer characteristics. CCDs however, are power consuming and slow when compared to CMOS technology and are no longer favorable for mobile applications. In this work, we report on novel single-photon counting based TDI technique that is implemented in standard CMOS technology allowing for complete camera-on-a-chip solution. The imager was fabricated in a standard CMOS 150 nm 5-metal digital process from LFoundry.

  1. LGSD/NGSD: high speed optical CMOS imagers for E-ELT adaptive optics

    NASA Astrophysics Data System (ADS)

    Downing, Mark; Kolb, Johann; Balard, Philippe; Dierickx, Bart; Defernez, Arnaud; Feautrier, Philippe; Finger, Gert; Fryer, Martin; Gach, Jean-Luc; Guillaume, Christian; Hubin, Norbert; Jerram, Paul; Jorden, Paul; Meyer, Manfred; Payne, Andrew; Pike, Andrew; Reyes, Javier; Simpson, Robert; Stadler, Eric; Stent, Jeremy; Swift, Nick

    2014-07-01

    The success of the next generation of instruments for ELT class telescopes will depend upon improving the image quality by exploiting sophisticated Adaptive Optics (AO) systems. One of the critical components of the AO systems for the E-ELT has been identified as the optical Laser/Natural Guide Star WFS detector. The combination of large format, 1760×1680 pixels to finely sample the wavefront and the spot elongation of laser guide stars, fast frame rate of 700 frames per second (fps), low read noise (< 3e-), and high QE (> 90%) makes the development of this device extremely challenging. Design studies concluded that a highly integrated Backside Illuminated CMOS Imager built on High Resistivity silicon as the most likely technology to succeed. Two generations of the CMOS Imager are being developed: a) the already designed and manufactured NGSD (Natural Guide Star Detector), a quarter-sized pioneering device of 880×840 pixels capable of meeting first light needs of the E-ELT; b) the LGSD (Laser Guide Star Detector), the larger full size device. The detailed design is presented including the approach of using massive parallelism (70,400 ADCs) to achieve the low read noise at high pixel rates of ~3 Gpixel/s and the 88 channel LVDS 220Mbps serial interface to get the data off-chip. To enable read noise closer to the goal of 1e- to be achieved, a split wafer run has allowed the NGSD to be manufactured in the more speculative, but much lower read noise, Ultra Low Threshold Transistors in the unit cell. The NGSD has come out of production, it has been thinned to 12μm, backside processed and packaged in a custom 370pin Ceramic PGA (Pin Grid Array). First results of tests performed both at e2v and ESO are presented.

  2. A Comparative Study of Heavy Ion and Proton Induced Bit Error Sensitivity and Complex Burst Error Modes in Commercially Available High Speed SiGe BiCMOS

    NASA Technical Reports Server (NTRS)

    Marshall, Paul; Carts, Marty; Campbell, Art; Reed, Robert; Ladbury, Ray; Seidleck, Christina; Currie, Steve; Riggs, Pam; Fritz, Karl; Randall, Barb

    2004-01-01

    A viewgraph presentation that reviews recent SiGe bit error test data for different commercially available high speed SiGe BiCMOS chips that were subjected to various levels of heavy ion and proton radiation. Results for the tested chips at different operating speeds are displayed in line graphs.

  3. High speed wide field CMOS camera for Transneptunian Automatic Occultation Survey

    NASA Astrophysics Data System (ADS)

    Wang, Shiang-Yu; Geary, John C.; Amato, Stephen M.; Hu, Yen-Sang; Ling, Hung-Hsu; Huang, Pin-Jie; Furesz, Gabor; Chen, Hsin-Yo; Chang, Yin-Chang; Szentgyorgyi, Andrew; Lehner, Matthew; Norton, Timothy

    2014-08-01

    The Transneptunian Automated Occultation Survey (TAOS II) is a three robotic telescope project to detect the stellar occultation events generated by Trans Neptunian Objects (TNOs). TAOS II project aims to monitor about 10000 stars simultaneously at 20Hz to enable statistically significant event rate. The TAOS II camera is designed to cover the 1.7 degree diameter field of view (FoV) of the 1.3m telescope with 10 mosaic 4.5kx2k CMOS sensors. The new CMOS sensor has a back illumination thinned structure and high sensitivity to provide similar performance to that of the backillumination thinned CCDs. The sensor provides two parallel and eight serial decoders so the region of interests can be addressed and read out separately through different output channels efficiently. The pixel scale is about 0.6"/pix with the 16μm pixels. The sensors, mounted on a single Invar plate, are cooled to the operation temperature of about 200K by a cryogenic cooler. The Invar plate is connected to the dewar body through a supporting ring with three G10 bipods. The deformation of the cold plate is less than 10μm to ensure the sensor surface is always within ±40μm of focus range. The control electronics consists of analog part and a Xilinx FPGA based digital circuit. For each field star, 8×8 pixels box will be readout. The pixel rate for each channel is about 1Mpix/s and the total pixel rate for each camera is about 80Mpix/s. The FPGA module will calculate the total flux and also the centroid coordinates for every field star in each exposure.

  4. High Speed, Radiation Hard CMOS Pixel Sensors for Transmission Electron Microscopy

    NASA Astrophysics Data System (ADS)

    Contarato, Devis; Denes, Peter; Doering, Dionisio; Joseph, John; Krieger, Brad

    CMOS monolithic active pixel sensors are currently being established as the technology of choice for new generation digital imaging systems in Transmission Electron Microscopy (TEM). A careful sensor design that couples μm-level pixel pitches with high frame rate readout and radiation hardness to very high electron doses enables the fabrication of direct electron detectors that are quickly revolutionizing high-resolution TEM imaging in material science and molecular biology. This paper will review the principal characteristics of this novel technology and its advantages over conventional, optically-coupled cameras, and retrace the sensor development driven by the Transmission Electron Aberration corrected Microscope (TEAM) project at the LBNL National Center for Electron Microscopy (NCEM), illustrating in particular the imaging capabilities enabled by single electron detection at high frame rate. Further, the presentation will report on the translation of the TEAM technology to a finer feature size process, resulting in a sensor with higher spatial resolution and superior radiation tolerance currently serving as the baseline for a commercial camera system.

  5. A Stimulated Raman Scattering CMOS Pixel Using a High-Speed Charge Modulator and Lock-in Amplifier.

    PubMed

    Lioe, De Xing; Mars, Kamel; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Yamada, Takahiro; Hashimoto, Mamoru

    2016-01-01

    A complementary metal-oxide semiconductor (CMOS) lock-in pixel to observe stimulated Raman scattering (SRS) using a high speed lateral electric field modulator (LEFM) for photo-generated charges and in-pixel readout circuits is presented. An effective SRS signal generated after the SRS process is very small and needs to be extracted from an extremely large offset due to a probing laser signal. In order to suppress the offset components while amplifying high-frequency modulated small SRS signal components, the lock-in pixel uses a high-speed LEFM for demodulating the SRS signal, resistor-capacitor low-pass filter (RC-LPF) and switched-capacitor (SC) integrator with a fully CMOS differential amplifier. AC (modulated) components remained in the RC-LPF outputs are eliminated by the phase-adjusted sampling with the SC integrator and the demodulated DC (unmodulated) components due to the SRS signal are integrated over many samples in the SC integrator. In order to suppress further the residual offset and the low frequency noise (1/f noise) components, a double modulation technique is introduced in the SRS signal measurements, where the phase of high-frequency modulated laser beam before irradiation of a specimen is modulated at an intermediate frequency and the demodulation is done at the lock-in pixel output. A prototype chip for characterizing the SRS lock-in pixel is implemented and a successful operation is demonstrated. The reduction effects of residual offset and 1/f noise components are confirmed by the measurements. A ratio of the detected small SRS to offset a signal of less than 10(-)⁵ is experimentally demonstrated, and the SRS spectrum of a Benzonitrile sample is successfully observed. PMID:27089339

  6. A Stimulated Raman Scattering CMOS Pixel Using a High-Speed Charge Modulator and Lock-in Amplifier

    PubMed Central

    Lioe, De Xing; Mars, Kamel; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Yamada, Takahiro; Hashimoto, Mamoru

    2016-01-01

    A complementary metal-oxide semiconductor (CMOS) lock-in pixel to observe stimulated Raman scattering (SRS) using a high speed lateral electric field modulator (LEFM) for photo-generated charges and in-pixel readout circuits is presented. An effective SRS signal generated after the SRS process is very small and needs to be extracted from an extremely large offset due to a probing laser signal. In order to suppress the offset components while amplifying high-frequency modulated small SRS signal components, the lock-in pixel uses a high-speed LEFM for demodulating the SRS signal, resistor-capacitor low-pass filter (RC-LPF) and switched-capacitor (SC) integrator with a fully CMOS differential amplifier. AC (modulated) components remained in the RC-LPF outputs are eliminated by the phase-adjusted sampling with the SC integrator and the demodulated DC (unmodulated) components due to the SRS signal are integrated over many samples in the SC integrator. In order to suppress further the residual offset and the low frequency noise (1/f noise) components, a double modulation technique is introduced in the SRS signal measurements, where the phase of high-frequency modulated laser beam before irradiation of a specimen is modulated at an intermediate frequency and the demodulation is done at the lock-in pixel output. A prototype chip for characterizing the SRS lock-in pixel is implemented and a successful operation is demonstrated. The reduction effects of residual offset and 1/f noise components are confirmed by the measurements. A ratio of the detected small SRS to offset a signal of less than 10−5 is experimentally demonstrated, and the SRS spectrum of a Benzonitrile sample is successfully observed. PMID:27089339

  7. A high speed CMOS image sensor with a novel digital correlated double sampling and a differential difference amplifier.

    PubMed

    Kim, Daehyeok; Bae, Jaeyoung; Song, Minkyu

    2015-01-01

    In order to increase the operating speed of a CMOS image sensor (CIS), a new technique of digital correlated double sampling (CDS) is described. In general, the fixed pattern noise (FPN) of a CIS has been reduced with the subtraction algorithm between the reset signal and pixel signal. This is because a single-slope analog-to-digital converter (ADC) has been normally adopted in the conventional digital CDS with the reset ramp and signal ramp. Thus, the operating speed of a digital CDS is much slower than that of an analog CDS. In order to improve the operating speed, we propose a novel digital CDS based on a differential difference amplifier (DDA) that compares the reset signal and the pixel signal using only one ramp. The prototype CIS has been fabricated with 0.13 µm CIS technology and it has the VGA resolution of 640 × 480. The measured conversion time is 16 µs, and a high frame rate of 131 fps is achieved at the VGA resolution. PMID:25738765

  8. A High Speed CMOS Image Sensor with a Novel Digital Correlated Double Sampling and a Differential Difference Amplifier

    PubMed Central

    Kim, Daehyeok; Bae, Jaeyoung; Song, Minkyu

    2015-01-01

    In order to increase the operating speed of a CMOS image sensor (CIS), a new technique of digital correlated double sampling (CDS) is described. In general, the fixed pattern noise (FPN) of a CIS has been reduced with the subtraction algorithm between the reset signal and pixel signal. This is because a single-slope analog-to-digital converter (ADC) has been normally adopted in the conventional digital CDS with the reset ramp and signal ramp. Thus, the operating speed of a digital CDS is much slower than that of an analog CDS. In order to improve the operating speed, we propose a novel digital CDS based on a differential difference amplifier (DDA) that compares the reset signal and the pixel signal using only one ramp. The prototype CIS has been fabricated with 0.13 µm CIS technology and it has the VGA resolution of 640 × 480. The measured conversion time is 16 µs, and a high frame rate of 131 fps is achieved at the VGA resolution. PMID:25738765

  9. High-speed modulator with interleaved junctions in zero-change CMOS photonics

    NASA Astrophysics Data System (ADS)

    Alloatti, L.; Cheian, D.; Ram, R. J.

    2016-03-01

    A microring depletion modulator is demonstrated with T-shaped lateral p-n junctions used to realize efficient modulation while maximizing the RC limited bandwidth. The device having a 3 dB bandwidth of 13 GHz has been fabricated in a standard 45 nm microelectronics CMOS process. The cavity has a linewidth of 17 GHz and an average wavelength-shift of 9 pm/V in reverse-bias conditions.

  10. Optimal high speed CMOS inverter design using craziness based Particle Swarm Optimization Algorithm

    NASA Astrophysics Data System (ADS)

    De, Bishnu P.; Kar, Rajib; Mandal, Durbadal; Ghoshal, Sakti P.

    2015-07-01

    The inverter is the most fundamental logic gate that performs a Boolean operation on a single input variable. In this paper, an optimal design of CMOS inverter using an improved version of particle swarm optimization technique called Craziness based Particle Swarm Optimization (CRPSO) is proposed. CRPSO is very simple in concept, easy to implement and computationally efficient algorithm with two main advantages: it has fast, nearglobal convergence, and it uses nearly robust control parameters. The performance of PSO depends on its control parameters and may be influenced by premature convergence and stagnation problems. To overcome these problems the PSO algorithm has been modiffed to CRPSO in this paper and is used for CMOS inverter design. In birds' flocking or ffsh schooling, a bird or a ffsh often changes direction suddenly. In the proposed technique, the sudden change of velocity is modelled by a direction reversal factor associated with the previous velocity and a "craziness" velocity factor associated with another direction reversal factor. The second condition is introduced depending on a predeffned craziness probability to maintain the diversity of particles. The performance of CRPSO is compared with real code.gnetic algorithm (RGA), and conventional PSO reported in the recent literature. CRPSO based design results are also compared with the PSPICE based results. The simulation results show that the CRPSO is superior to the other algorithms for the examples considered and can be efficiently used for the CMOS inverter design.

  11. PNP PIN bipolar phototransistors for high-speed applications built in a 180 nm CMOS process

    PubMed Central

    Kostov, P.; Gaberl, W.; Hofbauer, M.; Zimmermann, H.

    2012-01-01

    This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180 nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge region between base and collector and thus to a high −3 dB bandwidth at low collector–emitter voltages. For a further increase of the bandwidth the presented phototransistors were designed with small emitter areas resulting in a small base-emitter capacitance. The three presented phototransistors were implemented in sizes of 40 × 40 μm2 and 100 × 100 μm2. Optical DC and AC measurements at 410 nm, 675 nm and 850 nm were done for phototransistor characterization. Due to the speed optimized design and the layer structure of the phototransistors, bandwidths up to 76.9 MHz and dynamic responsivities up to 2.89 A/W were achieved. Furthermore simulations of the electric field strength and space-charge regions were done. PMID:23482349

  12. High speed CMOS imager with motion artifact supression and anti-blooming

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor); Wrigley, Chris (Inventor); Yang, Guang (Inventor); Yadid-Pecht, Orly (Inventor)

    2001-01-01

    An image sensor includes pixels formed on a semiconductor substrate. Each pixel includes a photoactive region in the semiconductor substrate, a sense node, and a power supply node. A first electrode is disposed near a surface of the semiconductor substrate. A bias signal on the first electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the sense node. A second electrode is disposed near the surface of the semiconductor substrate. A bias signal on the second electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the power supply node. The image sensor includes a controller that causes bias signals to be provided to the electrodes so that photocharges generated in the photoactive region are accumulated in the photoactive region during a pixel integration period, the accumulated photocharges are transferred to the sense node during a charge transfer period, and photocharges generated in the photoactive region are transferred to the power supply node during a third period without passing through the sense node. The imager can operate at high shutter speeds with simultaneous integration of pixels in the array. High quality images can be produced free from motion artifacts. High quantum efficiency, good blooming control, low dark current, low noise and low image lag can be obtained.

  13. High-speed low-voltage CMOS line driver for SerDes applications

    NASA Astrophysics Data System (ADS)

    Rogers, M.; Hayatleh, K.; Lidgey, F. J.; Joy, A.

    2013-04-01

    The challenge facing SerDes (Serialiser De-Serialiser) designers is common with all current communications technologies. Industry advances show a trend to increase speed, reduce power and improve efficiency. In this article a novel line driver that can operate at speeds of up to 40 Gbps with a power supply of 1 V and a power consumption of 4.54 mW/Gb/s is presented. Pre-distortion on the front-end is used to maintain signal integrity.

  14. Experimental Comparison of the High-Speed Imaging Performance of an EM-CCD and sCMOS Camera in a Dynamic Live-Cell Imaging Test Case

    PubMed Central

    Beier, Hope T.; Ibey, Bennett L.

    2014-01-01

    The study of living cells may require advanced imaging techniques to track weak and rapidly changing signals. Fundamental to this need is the recent advancement in camera technology. Two camera types, specifically sCMOS and EM-CCD, promise both high signal-to-noise and high speed (>100 fps), leaving researchers with a critical decision when determining the best technology for their application. In this article, we compare two cameras using a live-cell imaging test case in which small changes in cellular fluorescence must be rapidly detected with high spatial resolution. The EM-CCD maintained an advantage of being able to acquire discernible images with a lower number of photons due to its EM-enhancement. However, if high-resolution images at speeds approaching or exceeding 1000 fps are desired, the flexibility of the full-frame imaging capabilities of sCMOS is superior. PMID:24404178

  15. A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.

    PubMed

    Lyu, Tao; Yao, Suying; Nie, Kaiming; Xu, Jiangtao

    2014-01-01

    A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors. PMID:25407903

  16. A high-speed CMOS image sensor with column-parallel single capacitor CDSs and single-slope ADCs

    NASA Astrophysics Data System (ADS)

    Li, Quanliang; Shi, Cong; Wu, Nanjian

    2011-08-01

    This paper presents a high speed CMOS image sensor (CIS) with column-parallel single capacitor correlated double samplings (CDSs), programmable gain amplifiers (PGAs) and single-slope analog-to-digital converters (ADCs). The single capacitor CDS circuit has only one capacitor so that the area CDS circuit is small. In order to attain appropriate image contrast under different light conditions, the signal range can be adjusted by PGA. Single-slope ADC has smaller chip area than others ADCs and is suitable for column-parallel CIS architectures. A prototype sensor of 256x256 pixels was realized in a 0.13μm 1P3M CIS process. Its pixel circuit is 4T active pixel sensor (APS) and pixel size is 10x10μm2. Total chip area is 4x4mm2. The prototype achieves the full frame rate in excess of 250 frames per second, the sensitivity of 10.7V/lx•s, the conversion gain of 55.6μV/e and the column-to- column fixed-pattern noise (FPN) 0.41%.

  17. Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

    NASA Astrophysics Data System (ADS)

    Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

    2016-05-01

    In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

  18. A high-speed, low-noise CMOS 16-channel charge-sensitivepreamplifier ASIC for APD-based PET detectors

    SciTech Connect

    Weng, M.; Mandelli, E.; Moses, W.W.; Derenzo, S.E.

    2002-12-02

    A high-speed, low-noise 16-channel amplifier IC has beenfabricated in the HP 0.5 mm CMOS process. It is a prototype for use witha PET detector which uses a 4x4 avalanche photodiode (APD) array having 3pF of capacitance and 75 nA of leakage current per pixel. Thepreamplifier must have a fast rise time (a few ns) in order to generatean accurate timing signal, low noise in order to accurately measure theenergy of the incident gamma radiation, and high density in order to readout 2-D arrays of small (2 mm) pixels. A single channel consists of acharge-sensitive preamplifier followed by a pad-driving buffer. Thepreamplifier is reset by an NMOS transistor in the triode region which iscontrolled by an externally supplied current. The IC has 16 differentgain settings which range from 2.085 mV/fC to 10.695 mV/fC. The gain isdetermined by four switched capacitors in the feedback loop. The switchstate is set by two digital input lines which control a 64-bit shiftregister on the IC. A preamplifier 10-90 percent rise time as low as 2.7ns with no external input load and 3.6 ns with a load of 5.8 pF wasachieved. For the maximum gain setting and 5.8 pF of input load, theamplifier had 400 electrons of RMS noise at a peaking time of 0.7 us. TheIC is powered by a +3.3 V supply drawing 60 mA.

  19. Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process

    PubMed Central

    Rahman, Labonnah Farzana; Reaz, Mamun Bin Ibne; Yin, Chia Chieu; Ali, Mohammad Alauddin Mohammad; Marufuzzaman, Mohammad

    2014-01-01

    The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2. PMID:25299266

  20. High-voltage CMOS detectors

    NASA Astrophysics Data System (ADS)

    Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

    2016-07-01

    High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented.

  1. A 12-bit compact column-parallel SAR ADC with dynamic power control technique for high-speed CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Quanliang, Li; Liyuan, Liu; Ye, Han; Zhongxiang, Cao; Nanjian, Wu

    2014-10-01

    This paper presents a 12-bit column-parallel successive approximation register analog-to-digital converter (SAR ADC) for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital-to-analog converter (CDAC) and a staggered structure MOM unit capacitor is used to reduce the ADC area and to make its layout fit double pixel pitches. An electrical field shielding layout method is proposed to eliminate the parasitic capacitance on the top plate of the unit capacitor. A dynamic power control technique is proposed to reduce the power consumption of a single channel during readout. An off-chip foreground digital calibration is adopted to compensate for the nonlinearity due to the mismatch of unit capacitors among the CDAC. The prototype SAR ADC is fabricated in a 0.18 μm 1P5M CIS process. A single SAR ADC occupies 20 × 2020 μm2. Sampling at 833 kS/s, the measured differential nonlinearity, integral nonlinearity and effective number of bits of SAR ADC with calibration are 0.9/-1 LSB, 1/-1.1 LSB and 11.24 bits, respectively; the power consumption is only 0.26 mW under a 1.8-V supply and decreases linearly as the frame rate decreases.

  2. Observations of in situ deep-sea marine bioluminescence with a high-speed, high-resolution sCMOS camera

    NASA Astrophysics Data System (ADS)

    Phillips, Brennan T.; Gruber, David F.; Vasan, Ganesh; Roman, Christopher N.; Pieribone, Vincent A.; Sparks, John S.

    2016-05-01

    Observing and measuring marine bioluminescence in situ presents unique challenges, characterized by the difficult task of approaching and imaging weakly illuminated bodies in a three-dimensional environment. To address this problem, a scientific complementary-metal-oxide-semiconductor (sCMOS) microscopy camera was outfitted for deep-sea imaging of marine bioluminescence. This system was deployed on multiple platforms (manned submersible, remotely operated vehicle, and towed body) in three oceanic regions (Western Tropical Pacific, Eastern Equatorial Pacific, and Northwestern Atlantic) to depths up to 2500 m. Using light stimulation, bioluminescent responses were recorded at high frame rates and in high resolution, offering unprecedented low-light imagery of deep-sea bioluminescence in situ. The kinematics of light production in several zooplankton groups was observed, and luminescent responses at different depths were quantified as intensity vs. time. These initial results signify a clear advancement in the bioluminescent imaging methods available for observation and experimentation in the deep-sea.

  3. Video-rate fluorescence lifetime imaging camera with CMOS single-photon avalanche diode arrays and high-speed imaging algorithm.

    PubMed

    Li, David D-U; Arlt, Jochen; Tyndall, David; Walker, Richard; Richardson, Justin; Stoppa, David; Charbon, Edoardo; Henderson, Robert K

    2011-09-01

    A high-speed and hardware-only algorithm using a center of mass method has been proposed for single-detector fluorescence lifetime sensing applications. This algorithm is now implemented on a field programmable gate array to provide fast lifetime estimates from a 32 × 32 low dark count 0.13 μm complementary metal-oxide-semiconductor single-photon avalanche diode (SPAD) plus time-to-digital converter array. A simple look-up table is included to enhance the lifetime resolvability range and photon economics, making it comparable to the commonly used least-square method and maximum-likelihood estimation based software. To demonstrate its performance, a widefield microscope was adapted to accommodate the SPAD array and image different test samples. Fluorescence lifetime imaging microscopy on fluorescent beads in Rhodamine 6G at a frame rate of 50 fps is also shown. PMID:21950926

  4. High-temperature Complementary Metal Oxide Semiconductors (CMOS)

    NASA Technical Reports Server (NTRS)

    Mcbrayer, J. D.

    1981-01-01

    The results of an investigation into the possibility of using complementary metal oxide semiconductor (CMOS) technology for high temperature electronics are presented. A CMOS test chip was specifically developed as the test bed. This test chip incorporates CMOS transistors that have no gate protection diodes; these diodes are the major cause of leakage in commercial devices.

  5. Monolithic integration of high bandwidth waveguide coupled Ge photodiode in a photonic BiCMOS process

    NASA Astrophysics Data System (ADS)

    Lischke, S.; Knoll, D.; Zimmermann, L.

    2015-03-01

    Monolithic integration of photonic functionality in the frontend-of-line (FEOL) of an advanced microelectronics technology is a key step towards future communication applications. This combines photonic components such as waveguides, couplers, modulators, and photo detectors with high-speed electronics plus shortest possible interconnects crucial for high-speed performance. Integration of photonics into CMOS FEOL is therefore in development for quite some time reaching 90nm node recently [1]. However, an alternative to CMOS is high-performance BiCMOS, offering significant advantages for integrated photonics-electronics applications with regard to cost and RF performance. We already presented results of FEOL integration of photonic components in a high-performance SiGe:C BiCMOS baseline to establish a novel, photonic BiCMOS process. Process cornerstone is a local-SOI approach which allows us to fabricate SOI-based, thus low-loss photonic components in a bulk BiCMOS environment [2]. A monolithically integrated 10Gbit/sec Silicon modulator with driver was shown here [3]. A monolithically integrated 25Gbps receiver was presented in [4], consisting of 200GHz bipolar transistors and CMOS devices, low-loss waveguides, couplers, and highspeed Ge photo diodes showing 3-dB bandwidth of 35GHz, internal responsivity of more than 0.6A/W at λ= 1.55μm, and ~ 50nA dark current at 1V. However, the BiCMOS-given thermal steps cause a significant smearing of the Germanium photo diodes doping profile, limiting the photo diode performance. Therefore, we introduced implantation of non-doping elements to overcome such limiting factors, resulting in photo diode bandwidths of more than 50GHz even under the effect of thermal steps necessary when the diodes are integrated in a high performance BiCMOS process.

  6. High speed handpieces

    PubMed Central

    Bhandary, Nayan; Desai, Asavari; Shetty, Y Bharath

    2014-01-01

    High speed instruments are versatile instruments used by clinicians of all specialties of dentistry. It is important for clinicians to understand the types of high speed handpieces available and the mechanism of working. The centers for disease control and prevention have issued guidelines time and again for disinfection and sterilization of high speed handpieces. This article presents the recent developments in the design of the high speed handpieces. With a view to prevent hospital associated infections significant importance has been given to disinfection, sterilization & maintenance of high speed handpieces. How to cite the article: Bhandary N, Desai A, Shetty YB. High speed handpieces. J Int Oral Health 2014;6(1):130-2. PMID:24653618

  7. Theoretical performance analysis for CMOS based high resolution detectors.

    PubMed

    Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2013-03-01

    High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive. PMID:24353390

  8. High Speed data acquisition

    SciTech Connect

    Cooper, Peter S.

    1998-02-01

    A general introduction to high Speed data acquisition system techniques in modern particle physics experiments is given. Examples are drawn from the SELEX(E781) high statistics charmed baryon production and decay experiment now taking data at Fermilab.

  9. Delta Doping High Purity CCDs and CMOS for LSST

    NASA Technical Reports Server (NTRS)

    Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

    2006-01-01

    A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

  10. High Speed Research Program

    NASA Technical Reports Server (NTRS)

    Anderson, Robert E.; Corsiglia, Victor R.; Schmitz, Frederic H. (Technical Monitor)

    1994-01-01

    An overview of the NASA High Speed Research Program will be presented from a NASA Headquarters perspective. The presentation will include the objectives of the program and an outline of major programmatic issues.

  11. High-performance VGA-resolution digital color CMOS imager

    NASA Astrophysics Data System (ADS)

    Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

    1999-04-01

    This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be

  12. High Speed Civil Transport

    NASA Technical Reports Server (NTRS)

    1997-01-01

    This computer generated animation depicts a conceptual simulation of the flight of a High Speed Civil Transport (HSCT). As envisioned, the HSCT is a next-generation supersonic (faster than the speed of sound) passenger jet that would fly 300 passengers at more than 1,500 miles per hour -- more than twice the speed of sound. It will cross the Pacific or Atlantic in less than half the time of modern subsonic jets, and at a ticket price less than 20 percent above comparable, slower flights.

  13. High speed civil transport

    NASA Technical Reports Server (NTRS)

    Mcknight, R. L.

    1992-01-01

    The design requirements of the High Speed Civil Transport (HSCT) are discussed. The following design concerns are presented: (1) environmental impact (emissions and noise); (2) critical components (the high temperature combustor and the lightweight exhaust nozzle); and (3) advanced materials (high temperature ceramic matrix composites (CMC's)/intermetallic matrix composites (IMC's)/metal matrix composites (MMC's)).

  14. A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

    NASA Astrophysics Data System (ADS)

    Lattuca, A.; Mazza, G.; Aglieri Rinella, G.; Cavicchioli, C.; Chanlek, N.; Collu, A.; Degerli, Y.; Dorokhov, A.; Flouzat, C.; Gajanana, D.; Gao, C.; Guilloux, F.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kim, D.; Kofarago, M.; Kugathasan, T.; Kwon, Y.; Mager, M.; Sielewicz, K. Marek; Marin Tobon, C. Augusto; Marras, D.; Martinengo, P.; Mugnier, H.; Musa, L.; Pham, T. Hung; Puggioni, C.; Reidt, F.; Riedler, P.; Rousset, J.; Siddhanta, S.; Snoeys, W.; Song, M.; Usai, G.; Van Hoorne, J. Willem; Yang, P.

    2016-01-01

    This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.

  15. High Speed data acquisition

    SciTech Connect

    Cooper, P.S.

    1998-02-01

    A general introduction to high Speed data acquisition system techniques in modern particle physics experiments is given. Examples are drawn from the SELEX(E781) high statistics charmed baryon production and decay experiment now taking data at Fermilab. {copyright} {ital 1998 American Institute of Physics.}

  16. High speed door assembly

    DOEpatents

    Shapiro, Carolyn

    1993-01-01

    A high speed door assembly, comprising an actuator cylinder and piston rods, a pressure supply cylinder and fittings, an electrically detonated explosive bolt, a honeycomb structured door, a honeycomb structured decelerator, and a structural steel frame encasing the assembly to close over a 3 foot diameter opening within 50 milliseconds of actuation, to contain hazardous materials and vapors within a test fixture.

  17. High speed door assembly

    DOEpatents

    Shapiro, C.

    1993-04-27

    A high speed door assembly is described, comprising an actuator cylinder and piston rods, a pressure supply cylinder and fittings, an electrically detonated explosive bolt, a honeycomb structured door, a honeycomb structured decelerator, and a structural steel frame encasing the assembly to close over a 3 foot diameter opening within 50 milliseconds of actuation, to contain hazardous materials and vapors within a test fixture.

  18. High-performance monolithic CMOS detectors for space applications

    NASA Astrophysics Data System (ADS)

    Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Vignon, Bruno; Magnan, Pierre; Farre, Jean A.; Corbiere, Franck; Martin-Gonthier, Philippe

    2001-12-01

    During the last 10 years, research about CMOS image sensors (also called APS - Active Pixel Sensors) has been intensively carried out, in order to offer an alternative to CCDs as image sensors. This is particularly the case for space applications as CMOS image sensors feature characteristics which are obviously of interest for flight hardware: parallel or semi-parallel architecture, on chip control and processing electronics, low power dissipation, high level of radiation tolerance... Many image sensor companies, institutes and laboratories have demonstrated the compatibility of CMOS image sensors with consumer applications: micro-cameras, video-conferencing, digital- still cameras. And recent designs have shown that APS is getting closer to the CCD in terms of performance level. However, he large majority of the existing products do not offer the specific features which are required for many space applications. ASTRIUM and SUPAERO/CIMI have decided to work together in view of developing CMOS image sensors dedicated to space business. After a brief presentation of the team organization for space image sensor design and production, the latest results of a high performances 512 X 512 pixels CMOS device characterization are presented with emphasis on the achieved electro-optical performance. Finally, the on going and short-term coming activities of the team are discussed.

  19. High Speed Vortex Flows

    NASA Technical Reports Server (NTRS)

    Wood, Richard M.; Wilcox, Floyd J., Jr.; Bauer, Steven X. S.; Allen, Jerry M.

    2000-01-01

    A review of the research conducted at the National Aeronautics and Space Administration (NASA), Langley Research Center (LaRC) into high-speed vortex flows during the 1970s, 1980s, and 1990s is presented. The data reviewed is for flat plates, cavities, bodies, missiles, wings, and aircraft. These data are presented and discussed relative to the design of future vehicles. Also presented is a brief historical review of the extensive body of high-speed vortex flow research from the 1940s to the present in order to provide perspective of the NASA LaRC's high-speed research results. Data are presented which show the types of vortex structures which occur at supersonic speeds and the impact of these flow structures to vehicle performance and control is discussed. The data presented shows the presence of both small- and large scale vortex structures for a variety of vehicles, from missiles to transports. For cavities, the data show very complex multiple vortex structures exist at all combinations of cavity depth to length ratios and Mach number. The data for missiles show the existence of very strong interference effects between body and/or fin vortices and the downstream fins. It was shown that these vortex flow interference effects could be both positive and negative. Data are shown which highlights the effect that leading-edge sweep, leading-edge bluntness, wing thickness, location of maximum thickness, and camber has on the aerodynamics of and flow over delta wings. The observed flow fields for delta wings (i.e. separation bubble, classical vortex, vortex with shock, etc.) are discussed in the context of' aircraft design. And data have been shown that indicate that aerodynamic performance improvements are available by considering vortex flows as a primary design feature. Finally a discussing of a design approach for wings which utilize vortex flows for improved aerodynamic performance at supersonic speed is presented.

  20. High speed door assembly

    SciTech Connect

    Shapiro, C.

    1991-12-31

    This invention is comprised of a high speed door assembly, comprising an actuator cylinder and piston rods, a pressure supply cylinder and fittings, an electrically detonated explosive bolt, a honeycomb structured door, a honeycomb structured decelerator, and a structural steel frame encasing the assembly to close over a 3 foot diameter opening within 50 milliseconds of actuation, to contain hazardous materials and vapors within a test fixture.

  1. PALM and STORM: Into large fields and high-throughput microscopy with sCMOS detectors.

    PubMed

    Almada, Pedro; Culley, Siân; Henriques, Ricardo

    2015-10-15

    Single Molecule Localization Microscopy (SMLM) techniques such as Photo-Activation Localization Microscopy (PALM) and Stochastic Optical Reconstruction Microscopy (STORM) enable fluorescence microscopy super-resolution: the overcoming of the resolution barrier imposed by the diffraction of light. These techniques are based on acquiring hundreds or thousands of images of single molecules, locating them and reconstructing a higher-resolution image from the high-precision localizations. These methods generally imply a considerable trade-off between imaging speed and resolution, limiting their applicability to high-throughput workflows. Recent advancements in scientific Complementary Metal-Oxide Semiconductor (sCMOS) camera sensors and localization algorithms reduce the temporal requirements for SMLM, pushing it toward high-throughput microscopy. Here we outline the decisions researchers face when considering how to adapt hardware on a new system for sCMOS sensors with high-throughput in mind. PMID:26079924

  2. High speed civil transport

    NASA Technical Reports Server (NTRS)

    Bogardus, Scott; Loper, Brent; Nauman, Chris; Page, Jeff; Parris, Rusty; Steinbach, Greg

    1990-01-01

    The design process of the High Speed Civil Transport (HSCT) combines existing technology with the expectation of future technology to create a Mach 3.0 transport. The HSCT was designed to have a range in excess of 6000 nautical miles and carry up to 300 passengers. This range will allow the HSCT to service the economically expanding Pacific Basin region. Effort was made in the design to enable the aircraft to use conventional airports with standard 12,000 foot runways. With a takeoff thrust of 250,000 pounds, the four supersonic through-flow engines will accelerate the HSCT to a cruise speed of Mach 3.0. The 679,000 pound (at takeoff) HSCT is designed to cruise at an altitude of 70,000 feet, flying above most atmospheric disturbances.

  3. High speed flywheel

    DOEpatents

    McGrath, Stephen V.

    1991-01-01

    A flywheel for operation at high speeds utilizes two or more ringlike coments arranged in a spaced concentric relationship for rotation about an axis and an expansion device interposed between the components for accommodating radial growth of the components resulting from flywheel operation. The expansion device engages both of the ringlike components, and the structure of the expansion device ensures that it maintains its engagement with the components. In addition to its expansion-accommodating capacity, the expansion device also maintains flywheel stiffness during flywheel operation.

  4. Mechanically Flexible and High-Performance CMOS Logic Circuits

    PubMed Central

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-01-01

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

  5. Mechanically Flexible and High-Performance CMOS Logic Circuits.

    PubMed

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-01-01

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

  6. High speed transient sampler

    DOEpatents

    McEwan, Thomas E.

    1995-01-01

    A high speed sampler comprises a meandered sample transmission line for transmitting an input signal, a straight strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates along the transmission lines. The sampling gates comprise a four terminal diode bridge having a first strobe resistor connected from a first terminal of the bridge to the positive strobe line, a second strobe resistor coupled from the third terminal of the bridge to the negative strobe line, a tap connected to the second terminal of the bridge and to the sample transmission line, and a sample holding capacitor connected to the fourth terminal of the bridge. The resistance of the first and second strobe resistors is much higher than the signal transmission line impedance in the preferred system. This results in a sampling gate which applies a very small load on the sample transmission line and on the strobe generator. The sample holding capacitor is implemented using a smaller capacitor and a larger capacitor isolated from the smaller capacitor by resistance. The high speed sampler of the present invention is also characterized by other optimizations, including transmission line tap compensation, stepped impedance strobe line, a multi-layer physical layout, and unique strobe generator design. A plurality of banks of such samplers are controlled for concatenated or interleaved sample intervals to achieve long sample lengths or short sample spacing.

  7. High speed transient sampler

    DOEpatents

    McEwan, T.E.

    1995-11-28

    A high speed sampler comprises a meandered sample transmission line for transmitting an input signal, a straight strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates along the transmission lines. The sampling gates comprise a four terminal diode bridge having a first strobe resistor connected from a first terminal of the bridge to the positive strobe line, a second strobe resistor coupled from the third terminal of the bridge to the negative strobe line, a tap connected to the second terminal of the bridge and to the sample transmission line, and a sample holding capacitor connected to the fourth terminal of the bridge. The resistance of the first and second strobe resistors is much higher than the signal transmission line impedance in the preferred system. This results in a sampling gate which applies a very small load on the sample transmission line and on the strobe generator. The sample holding capacitor is implemented using a smaller capacitor and a larger capacitor isolated from the smaller capacitor by resistance. The high speed sampler of the present invention is also characterized by other optimizations, including transmission line tap compensation, stepped impedance strobe line, a multi-layer physical layout, and unique strobe generator design. A plurality of banks of such samplers are controlled for concatenated or interleaved sample intervals to achieve long sample lengths or short sample spacing. 17 figs.

  8. High-Voltage-Input Level Translator Using Standard CMOS

    NASA Technical Reports Server (NTRS)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  9. HIGH SPEED CAMERA

    DOEpatents

    Rogers, B.T. Jr.; Davis, W.C.

    1957-12-17

    This patent relates to high speed cameras having resolution times of less than one-tenth microseconds suitable for filming distinct sequences of a very fast event such as an explosion. This camera consists of a rotating mirror with reflecting surfaces on both sides, a narrow mirror acting as a slit in a focal plane shutter, various other mirror and lens systems as well as an innage recording surface. The combination of the rotating mirrors and the slit mirror causes discrete, narrow, separate pictures to fall upon the film plane, thereby forming a moving image increment of the photographed event. Placing a reflecting surface on each side of the rotating mirror cancels the image velocity that one side of the rotating mirror would impart, so as a camera having this short a resolution time is thereby possible.

  10. High speed nozzles task

    NASA Technical Reports Server (NTRS)

    Hamed, Awatef

    1995-01-01

    Supersonic cruise exhaust nozzles for advanced applications are optimized for a high nozzle pressure ratio (NPR) at design supersonic cruise Mach number and altitude. The performance of these nozzles with large expansion ratios are severely degraded for operations at subsonic speeds near sea level for NPR significantly less than the design values. The prediction of over-expanded 2DCD nozzles performance is critical to evaluating the internal losses and to the optimization of the integrated vehicle and propulsion system performance. The reported research work was aimed at validating and assessing existing computational methods and turbulence models for predicting the flow characteristics and nozzle performance at over-expanded conditions. Flow simulations in 2DCD nozzles were performed using five different turbulence models. The results are compared with the experimental data for the wall pressure distribution and thrust and flow coefficients at over-expanded static conditions.

  11. High speed packet switching

    NASA Technical Reports Server (NTRS)

    1991-01-01

    This document constitutes the final report prepared by Proteon, Inc. of Westborough, Massachusetts under contract NAS 5-30629 entitled High-Speed Packet Switching (SBIR 87-1, Phase 2) prepared for NASA-Greenbelt, Maryland. The primary goal of this research project is to use the results of the SBIR Phase 1 effort to develop a sound, expandable hardware and software router architecture capable of forwarding 25,000 packets per second through the router and passing 300 megabits per second on the router's internal busses. The work being delivered under this contract received its funding from three different sources: the SNIPE/RIG contract (Contract Number F30602-89-C-0014, CDRL Sequence Number A002), the SBIR contract, and Proteon. The SNIPE/RIG and SBIR contracts had many overlapping requirements, which allowed the research done under SNIPE/RIG to be applied to SBIR. Proteon funded all of the work to develop new router interfaces other than FDDI, in addition to funding the productization of the router itself. The router being delivered under SBIR will be a fully product-quality machine. The work done during this contract produced many significant findings and results, summarized here and explained in detail in later sections of this report. The SNIPE/RIG contract was completed. That contract had many overlapping requirements with the SBIR contract, and resulted in the successful demonstration and delivery of a high speed router. The development that took place during the SNIPE/RIG contract produced findings that included the choice of processor and an understanding of the issues surrounding inter processor communications in a multiprocessor environment. Many significant speed enhancements to the router software were made during that time. Under the SBIR contract (and with help from Proteon-funded work), it was found that a single processor router achieved a throughput significantly higher than originally anticipated. For this reason, a single processor router was

  12. A 1-V TSPC Dual Modulus Prescaler with Speed Scalability Using Forward Body Biasing in 0.18µm CMOS

    NASA Astrophysics Data System (ADS)

    Shin, Hyunchol

    The operating speed scalability is demonstrated by using the forward body biasing method for a 1-V 0.18-µm CMOS true single-phase clocking (TSPC) dual-modulus prescaler. With the forward body bias voltage varying between 0 and 0.4V, the maximum operating speed changes by about 40-50% and the maximum input sensitivity frequency changes by about 400%. This speed scalability is achieved with less than 0.5-dB phase noise degradation. This demonstration indicates that the forward body biasing method is instrumental to build a cost-saving power-efficient 1-V 0.18-µm CMOS radio for low-power WBAN and WSN applications.

  13. A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

    NASA Technical Reports Server (NTRS)

    Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

    1993-01-01

    A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

  14. Monolithic CMOS-MEMS integration for high-g accelerometers

    NASA Astrophysics Data System (ADS)

    Narasimhan, Vinayak; Li, Holden; Tan, Chuan Seng

    2014-10-01

    This paper highlights work-in-progress towards the conceptualization, simulation, fabrication and initial testing of a silicon-germanium (SiGe) integrated CMOS-MEMS high-g accelerometer for military, munition, fuze and shock measurement applications. Developed on IMEC's SiGe MEMS platform, the MEMS offers a dynamic range of 5,000 g and a bandwidth of 12 kHz. The low noise readout circuit adopts a chopper-stabilization technique implementing the CMOS through the TSMC 0.18 µm process. The device structure employs a fully differential split comb-drive set up with two sets of stators and a rotor all driven separately. Dummy structures acting as protective over-range stops were designed to protect the active components when under impacts well above the designed dynamic range.

  15. Fully depleted, thick, monolithic CMOS pixels with high quantum efficiency

    NASA Astrophysics Data System (ADS)

    Clarke, A.; Stefanov, K.; Johnston, N.; Holland, A.

    2015-04-01

    The Centre for Electronic Imaging (CEI) has an active programme of evaluating and designing Complementary Metal-Oxide Semiconductor (CMOS) image sensors with high quantum efficiency, for applications in near-infrared and X-ray photon detection. This paper describes the performance characterisation of CMOS devices made on a high resistivity 50 μ m thick p-type substrate with a particular focus on determining the depletion depth and the quantum efficiency. The test devices contain 8 × 8 pixel arrays using CCD-style charge collection, which are manufactured in a low voltage CMOS process by ESPROS Photonics Corporation (EPC). Measurements include determining under which operating conditions the devices become fully depleted. By projecting a spot using a microscope optic and a LED and biasing the devices over a range of voltages, the depletion depth will change, causing the amount of charge collected in the projected spot to change. We determine if the device is fully depleted by measuring the signal collected from the projected spot. The analysis of spot size and shape is still under development.

  16. High speed civil transport

    NASA Technical Reports Server (NTRS)

    1991-01-01

    This report discusses the design and marketability of a next generation supersonic transport. Apogee Aeronautics Corporation has designated its High Speed Civil Transport (HSCT): Supercruiser HS-8. Since the beginning of the Concorde era, the general consensus has been that the proper time for the introduction of a next generation Supersonic Transport (SST) would depend upon the technical advances made in the areas of propulsion (reduction in emissions) and material composites (stronger, lighter materials). It is believed by many in the aerospace industry that these beforementioned technical advances lie on the horizon. With this being the case, this is the proper time to begin the design phase for the next generation HSCT. The design objective for a HSCT was to develop an aircraft that would be capable of transporting at least 250 passengers with baggage at a distance of 5500 nmi. The supersonic Mach number is currently unspecified. In addition, the design had to be marketable, cost effective, and certifiable. To achieve this goal, technical advances in the current SST's must be made, especially in the areas of aerodynamics and propulsion. As a result of these required aerodynamic advances, several different supersonic design concepts were reviewed.

  17. High resolution, high bandwidth global shutter CMOS area scan sensors

    NASA Astrophysics Data System (ADS)

    Faramarzpour, Naser; Sonder, Matthias; Li, Binqiao

    2013-10-01

    Global shuttering, sometimes also known as electronic shuttering, enables the use of CMOS sensors in a vast range of applications. Teledyne DALSA Global shutter sensors are able to integrate light synchronously across millions of pixels with microsecond accuracy. Teledyne DALSA offers 5 transistor global shutter pixels in variety of resolutions, pitches and noise and full-well combinations. One of the recent generations of these pixels is implemented in 12 mega pixel area scan device at 6 um pitch and that images up to 70 frames per second with 58 dB dynamic range. These square pixels include microlens and optional color filters. These sensors also offer exposure control, anti-blooming and high dynamic range operation by introduction of a drain and a PPD reset gate to the pixel. The state of the art sense node design of Teledyne DALSA's 5T pixel offers exceptional shutter rejection ratio. The architecture is consistent with the requirements to use stitching to achieve very large area scan devices. Parallel or serial digital output is provided on these sensors using on-chip, column-wise analog to digital converters. Flexible ADC bit depth combined with windowing (adjustable region of interest, ROI) allows these sensors to run with variety of resolution/bandwidth combinations. The low power, state of the art LVDS I/O technology allows for overall power consumptions of less than 2W at full performance conditions.

  18. Ultra-fast high-resolution hybrid and monolithic CMOS imagers in multi-frame radiography

    NASA Astrophysics Data System (ADS)

    Kwiatkowski, Kris; Douence, Vincent; Bai, Yibin; Nedrow, Paul; Mariam, Fesseha; Merrill, Frank; Morris, Christopher L.; Saunders, Andy

    2014-09-01

    A new burst-mode, 10-frame, hybrid Si-sensor/CMOS-ROIC FPA chip has been recently fabricated at Teledyne Imaging Sensors. The intended primary use of the sensor is in the multi-frame 800 MeV proton radiography at LANL. The basic part of the hybrid is a large (48×49 mm2) stitched CMOS chip of 1100×1100 pixel count, with a minimum shutter speed of 50 ns. The performance parameters of this chip are compared to the first generation 3-frame 0.5-Mpixel custom hybrid imager. The 3-frame cameras have been in continuous use for many years, in a variety of static and dynamic experiments at LANSCE. The cameras can operate with a per-frame adjustable integration time of ~ 120ns-to- 1s, and inter-frame time of 250ns to 2s. Given the 80 ms total readout time, the original and the new imagers can be externally synchronized to 0.1-to-5 Hz, 50-ns wide proton beam pulses, and record up to ~1000-frame radiographic movies typ. of 3-to-30 minute duration. The performance of the global electronic shutter is discussed and compared to that of a high-resolution commercial front-illuminated monolithic CMOS imager.

  19. High total dose effects on CMOS/SOI technology

    SciTech Connect

    Flament, O.; Dupont-Nivet, E.; Leray, J.L.; Pere, J.F.; Delagnes, E. ); Auberton-Herve, A.J.; Giffard, B. ); Borel, G.; Ouisse, T. )

    1992-06-01

    This paper reports that, CMOS silicon on insulator technology has shown its ability to process hardened components which remain functional after irradiation with a total dose of several tens of Megarads. New tests on elementary transistors and 29101 microprocessor have been made at doses up to 100 Mrad (SiO{sub 2}) and above. Results of irradiation at these total doses are presented for different biases, together with the post-irradiation behavior of the components. All the observations show that new parameters must be taken into account for hardness insurance at a high level of total dose.

  20. A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager

    PubMed Central

    Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

    2012-01-01

    Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm2. Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624

  1. High-Speed Electrochemical Imaging.

    PubMed

    Momotenko, Dmitry; Byers, Joshua C; McKelvey, Kim; Kang, Minkyung; Unwin, Patrick R

    2015-09-22

    The design, development, and application of high-speed scanning electrochemical probe microscopy is reported. The approach allows the acquisition of a series of high-resolution images (typically 1000 pixels μm(-2)) at rates approaching 4 seconds per frame, while collecting up to 8000 image pixels per second, about 1000 times faster than typical imaging speeds used up to now. The focus is on scanning electrochemical cell microscopy (SECCM), but the principles and practicalities are applicable to many electrochemical imaging methods. The versatility of the high-speed scan concept is demonstrated at a variety of substrates, including imaging the electroactivity of a patterned self-assembled monolayer on gold, visualization of chemical reactions occurring at single wall carbon nanotubes, and probing nanoscale electrocatalysts for water splitting. These studies provide movies of spatial variations of electrochemical fluxes as a function of potential and a platform for the further development of high speed scanning with other electrochemical imaging techniques. PMID:26267455

  2. SEAL FOR HIGH SPEED CENTRIFUGE

    DOEpatents

    Skarstrom, C.W.

    1957-12-17

    A seal is described for a high speed centrifuge wherein the centrifugal force of rotation acts on the gasket to form a tight seal. The cylindrical rotating bowl of the centrifuge contains a closure member resting on a shoulder in the bowl wall having a lower surface containing bands of gasket material, parallel and adjacent to the cylinder wall. As the centrifuge speed increases, centrifugal force acts on the bands of gasket material forcing them in to a sealing contact against the cylinder wall. This arrangememt forms a simple and effective seal for high speed centrifuges, replacing more costly methods such as welding a closure in place.

  3. Gated high speed optical detector

    NASA Technical Reports Server (NTRS)

    Green, S. I.; Carson, L. M.; Neal, G. W.

    1973-01-01

    The design, fabrication, and test of two gated, high speed optical detectors for use in high speed digital laser communication links are discussed. The optical detectors used a dynamic crossed field photomultiplier and electronics including dc bias and RF drive circuits, automatic remote synchronization circuits, automatic gain control circuits, and threshold detection circuits. The equipment is used to detect binary encoded signals from a mode locked neodynium laser.

  4. A high-speed, high fan-in dynamic comparator with low transistor count

    NASA Astrophysics Data System (ADS)

    Wey, I.-Chyn; He, Tz-Cheng; Chow, Hwang-Cherng; Sun, Pie-Hsien; Peng, Chien-Chang

    2014-05-01

    In this article, we proposed a high-speed, high fan-in dynamic CMOS comparator with low transistor count. Our approach is to construct the dynamic comparator based on the prior superiority of dynamic CMOS comparator and to further enhance its operating speed. Constructing the comparator with dynamic CMOS architecture, we can save 63.2% transistor count as compared with the conventional static CMOS design. The main contribution to accelerate the speed of dynamic comparator is to solve the problem of 'weak 0' existing in the PMOS of pull-down network. Instead, as an alternate to PMOS in the pull-down network, we use NMOS combined with an additional inverter in the front of the NMOS input gate. In this way, we can perform the same function as PMOS, but transmitting with both 'good 1' and 'good 0'. As a result, the proposed dynamic comparator can operate with lower propagation delay in the pull-down network. Finally, the proposed 64-bit dynamic comparator circuit can operate correctly under a clock frequency of 450 MHz with 0.18 µm technology while the prior circuit can only operate under 250 MHz at the same time.

  5. High responsivity CMOS imager pixel implemented in SOI technology

    NASA Technical Reports Server (NTRS)

    Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

    2000-01-01

    Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

  6. High speed optical networks

    NASA Astrophysics Data System (ADS)

    Frankel, Michael Y.; Livas, Jeff

    2005-02-01

    This overview will discuss core network technology and cost trade-offs inherent in choosing between "analog" architectures with high optical transparency, and ones heavily dependent on frequent "digital" signal regeneration. The exact balance will be related to the specific technology choices in each area outlined above, as well as the network needs such as node geographic spread, physical connectivity patterns, and demand loading. Over the course of a decade, optical networks have evolved from simple single-channel SONET regenerator-based links to multi-span multi-channel optically amplified ultra-long haul systems, fueled by high demand for bandwidth at reduced cost. In general, the cost of a well-designed high capacity system is dominated by the number of optical to electrical (OE) and electrical to optical (EO) conversions required. As the reach and channel capacity of the transport systems continued to increase, it became necessary to improve the granularity of the demand connections by introducing (optical add/drop multiplexers) OADMs. Thus, if a node requires only small demand connectivity, most of the optical channels are expressed through without regeneration (OEO). The network costs are correspondingly reduced, partially balanced by the increased cost of the OADM nodes. Lately, the industry has been aggressively pursuing a natural extension of this philosophy towards all-optical "analog" core networks, with each demand touching electrical digital circuitry only at the in/egress nodes. This is expected to produce a substantial elimination of OEO costs, increase in network capacity, and a notionally simpler operation and service turn-up. At the same time, such optical "analog" network requires a large amount of complicated hardware and software for monitoring and manipulating high bit rate optical signals. New and more complex modulation formats that provide resiliency to both optical noise and nonlinear propagation effects are important for extended

  7. Superplane! High Speed Civil Transport

    NASA Technical Reports Server (NTRS)

    1998-01-01

    The High Speed Civil Transport (HSCT). This light-hearted promotional piece explains what the HSCT 'Superplane' is and what advantages it will have over current aircraft. As envisioned, the HSCT is a next-generation supersonic (faster than the speed of sound) passenger jet that would fly 300 passengers at more than 1,500 miles per hour -- more than twice the speed of sound. It will cross the Pacific or Atlantic in less than half the time of modern subsonic jets, and at a ticket price less than 20 percent above comparable, slower flights

  8. Flexible high speed CODEC

    NASA Technical Reports Server (NTRS)

    Wernlund, James V.

    1993-01-01

    HARRIS, under contract with NASA Lewis, has developed a hard decision BCH (Bose-Chaudhuri-Hocquenghem) triple error correcting block CODEC ASIC, that can be used in either a bursted or continuous mode. the ASIC contains both encoder and decoder functions, programmable lock thresholds, and PSK related functions. The CODEC provides up to 4 dB of coding gain for data rates up to 300 Mbps. The overhead is selectable from 7/8 to 15/16 resulting in minimal band spreading, for a given BER. Many of the internal calculations are brought out enabling the CODEC to be incorporated in more complex designs. The ASIC has been tested in BPSK, QPSK and 16-ary PSK link simulators and found to perform to within 0.1 dB of theory for BER's of 10(exp -2) to 10(exp -9). The ASIC itself, being a hard decision CODEC, is not limited to PSK modulation formats. Unlike most hard decision CODEC's, the HARRIS CODEC doesn't upgrade BER performance significantly at high BER's but rather becomes transparent.

  9. Flexible high speed CODEC

    NASA Astrophysics Data System (ADS)

    Wernlund, James V.

    1993-02-01

    HARRIS, under contract with NASA Lewis, has developed a hard decision BCH (Bose-Chaudhuri-Hocquenghem) triple error correcting block CODEC ASIC, that can be used in either a bursted or continuous mode. the ASIC contains both encoder and decoder functions, programmable lock thresholds, and PSK related functions. The CODEC provides up to 4 dB of coding gain for data rates up to 300 Mbps. The overhead is selectable from 7/8 to 15/16 resulting in minimal band spreading, for a given BER. Many of the internal calculations are brought out enabling the CODEC to be incorporated in more complex designs. The ASIC has been tested in BPSK, QPSK and 16-ary PSK link simulators and found to perform to within 0.1 dB of theory for BER's of 10(exp -2) to 10(exp -9). The ASIC itself, being a hard decision CODEC, is not limited to PSK modulation formats. Unlike most hard decision CODEC's, the HARRIS CODEC doesn't upgrade BER performance significantly at high BER's but rather becomes transparent.

  10. A 4MP high-dynamic-range, low-noise CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Ma, Cheng; Liu, Yang; Li, Jing; Zhou, Quan; Chang, Yuchun; Wang, Xinyang

    2015-03-01

    In this paper we present a 4 Megapixel high dynamic range, low dark noise and dark current CMOS image sensor, which is ideal for high-end scientific and surveillance applications. The pixel design is based on a 4-T PPD structure. During the readout of the pixel array, signals are first amplified, and then feed to a low- power column-parallel ADC array which is already presented in [1]. Measurement results show that the sensor achieves a dynamic range of 96dB, a dark noise of 1.47e- at 24fps speed. The dark current is 0.15e-/pixel/s at -20oC.

  11. Nonlinear optical signal processing in high figure of merit CMOS compatible platforms

    NASA Astrophysics Data System (ADS)

    Moss, D. J.; Morandotti, R.

    2015-05-01

    Photonic integrated circuits that exploit nonlinear optics in order to generate and process signals all-optically have achieved performance far superior to that possible electronically - particularly with respect to speed. Although silicon-on-insulator has been the leading platform for nonlinear optics for some time, its high two-photon absorption at telecommunications wavelengths poses a fundamental limitation. We review the recent achievements based in new CMOS-compatible platforms that are better suited than SOI for nonlinear optics, focusing on amorphous silicon and Hydex glass. We highlight their potential as well as the challenges to achieving practical solutions for many key applications. These material systems have opened up many new capabilities such as on-chip optical frequency comb generation and ultrafast optical pulse generation and measurement.

  12. Design of a high performance CMOS charge pump for phase-locked loop synthesizers

    NASA Astrophysics Data System (ADS)

    Zhiqun, Li; Shuangshuang, Zheng; Ningbing, Hou

    2011-07-01

    A new high performance charge pump circuit is designed and realized in 0.18 μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range. Furthermore, a method of adding a precharging current source is proposed to increase the initial charge current, which will speed up the settling time of CPPLLs. Test results show that the current mismatching can be less than 0.4% in the output voltage range of 0.4 to 1.7 V, with a charge pump current of 100 μA and a precharging current of 70 μA. The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.

  13. High-speed stereoscopy of aurora

    NASA Astrophysics Data System (ADS)

    Kataoka, R.; Fukuda, Y.; Uchida, H. A.; Yamada, H.; Miyoshi, Y.; Ebihara, Y.; Dahlgren, H.; Hampton, D.

    2016-01-01

    We performed 100 fps stereoscopic imaging of aurora for the first time. Two identical sCMOS cameras equipped with narrow field-of-view lenses (15° by 15°) were directed at magnetic zenith with the north-south base distance of 8.1 km. Here we show the best example that a rapidly pulsating diffuse patch and a streaming discrete arc were observed at the same time with different parallaxes, and the emission altitudes were estimated as 85-95 km and > 100 km, respectively. The estimated emission altitudes are consistent with those estimated in previous studies, and it is suggested that high-speed stereoscopy is useful to directly measure the emission altitudes of various types of rapidly varying aurora. It is also found that variation of emission altitude is gradual (e.g., 10 km increase over 5 s) for pulsating patches and is fast (e.g., 10 km increase within 0.5 s) for streaming arcs.

  14. High speed multiwire photon camera

    NASA Technical Reports Server (NTRS)

    Lacy, Jeffrey L. (Inventor)

    1991-01-01

    An improved multiwire proportional counter camera having particular utility in the field of clinical nuclear medicine imaging. The detector utilizes direct coupled, low impedance, high speed delay lines, the segments of which are capacitor-inductor networks. A pile-up rejection test is provided to reject confused events otherwise caused by multiple ionization events occuring during the readout window.

  15. High speed multiwire photon camera

    NASA Technical Reports Server (NTRS)

    Lacy, Jeffrey L. (Inventor)

    1989-01-01

    An improved multiwire proportional counter camera having particular utility in the field of clinical nuclear medicine imaging. The detector utilizes direct coupled, low impedance, high speed delay lines, the segments of which are capacitor-inductor networks. A pile-up rejection test is provided to reject confused events otherwise caused by multiple ionization events occurring during the readout window.

  16. High speed laser tomography system.

    PubMed

    Samsonov, D; Elsaesser, A; Edwards, A; Thomas, H M; Morfill, G E

    2008-03-01

    A high speed laser tomography system was developed capable of acquiring three-dimensional (3D) images of optically thin clouds of moving micron-sized particles. It operates by parallel-shifting an illuminating laser sheet with a pair of galvanometer-driven mirrors and synchronously recording two-dimensional (2D) images of thin slices of the imaged volume. The maximum scanning speed achieved was 120,000 slices/s, sequences of 24 volume scans (up to 256 slices each) have been obtained. The 2D slices were stacked to form 3D images of the volume, then the positions of the particles were identified and followed in the consecutive scans. The system was used to image a complex plasma with particles moving at speeds up to cm/s. PMID:18377040

  17. Integrated, nonvolatile, high-speed analog random access memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor)

    1994-01-01

    This invention provides an integrated, non-volatile, high-speed random access memory. A magnetically switchable ferromagnetic or ferrimagnetic layer is sandwiched between an electrical conductor which provides the ability to magnetize the magnetically switchable layer and a magneto resistive or Hall effect material which allows sensing the magnetic field which emanates from the magnetization of the magnetically switchable layer. By using this integrated three-layer form, the writing process, which is controlled by the conductor, is separated from the storage medium in the magnetic layer and from the readback process which is controlled by the magnetoresistive layer. A circuit for implementing the memory in CMOS or the like is disclosed.

  18. Correct CMOS IC defect models for quality testing

    NASA Technical Reports Server (NTRS)

    Soden, Jerry M.; Hawkins, Charles F.

    1993-01-01

    Leading edge, high reliability, and low escape CMOS IC test practices have now virtually removed the stuck-at fault model and replaced it with more defect-orientated models. Quiescent power supply current testing (I(sub DDQ)) combined with strategic use of high speed test patterns is the recommended approach to zero defect and high reliability testing goals. This paper reviews the reasons for the change in CMOS IC test practices and outlines an improved CMOS IC test methodology.

  19. Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

    NASA Astrophysics Data System (ADS)

    Benoit, M.; Bilbao de Mendizabal, J.; Casse, G.; Chen, H.; Chen, K.; Di Bello, F. A.; Ferrere, D.; Golling, T.; Gonzalez-Sevilla, S.; Iacobucci, G.; Lanni, F.; Liu, H.; Meloni, F.; Meng, L.; Miucci, A.; Muenstermann, D.; Nessi, M.; Perić, I.; Rimoldi, M.; Ristic, B.; Barrero Pinto, M. Vicente; Vossebeld, J.; Weber, M.; Wu, W.; Xu, L.

    2016-07-01

    Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. This paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. Results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

  20. High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

    PubMed

    Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

    2010-12-15

    A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. PMID:20728336

  1. Hardware-based image processing for high-speed inspection of grains

    Technology Transfer Automated Retrieval System (TEKTRAN)

    A high-speed, low-cost, image-based sorting device was developed to detect and separate grains with slight color differences and small defects on grains The device directly combines a complementary metal–oxide–semiconductor (CMOS) color image sensor with a field-programmable gate array (FPGA) which...

  2. High-speed sorting of grains by color and surface texture

    Technology Transfer Automated Retrieval System (TEKTRAN)

    A high-speed, low-cost, image-based sorting device was developed to detect and separate grains with different colors/textures. The device directly combines a complementary metal–oxide–semiconductor (CMOS) color image sensor with a field-programmable gate array (FPGA) that was programmed to execute ...

  3. High speed COMS image acquisition and transmission system based on USB

    NASA Astrophysics Data System (ADS)

    Cui, Yundong; Jiang, Jie; Zhang, Guangjun

    2008-10-01

    A high speed CMOS image acquisition and transmission system, which is composed of CMOS image sensor IBIS5-A-1300, USB 2.0 interface chip EZ-USB FX2 and FPGA (Field Programmable Gate Array), is designed and developed. The design of IBIS5-A-1300 driving timing, USB interface chip timing, firmware and application program are introduced. Experiments show that the system possesses the advantage of high resolution and high frame rate, supports single frame acquisition and video preview and fits the criterion of USB2.0 and the demand of real-time data transmission.

  4. Design considerations for a new high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS)

    NASA Astrophysics Data System (ADS)

    Loughran, Brendan; Swetadri Vasan, S. N.; Singh, Vivek; Ionita, Ciprian N.; Jain, Amit; Bednarek, Daniel R.; Titus, Albert H.; Rudin, Stephen

    2013-03-01

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

  5. Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS).

    PubMed

    Loughran, Brendan; Swetadri Vasan, S N; Singh, Vivek; Ionita, Ciprian N; Jain, Amit; Bednarek, Daniel R; Titus, Albert; Rudin, Stephen

    2013-03-01

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems. PMID:24353389

  6. Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS)

    PubMed Central

    Loughran, Brendan; Swetadri Vasan, S. N.; Singh, Vivek; Ionita, Ciprian N.; Jain, Amit; Bednarek, Daniel R.; Titus, Albert; Rudin, Stephen

    2013-01-01

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50–1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems. PMID:24353389

  7. Small Scale High Speed Turbomachinery

    NASA Technical Reports Server (NTRS)

    London, Adam P. (Inventor); Droppers, Lloyd J. (Inventor); Lehman, Matthew K. (Inventor); Mehra, Amitav (Inventor)

    2015-01-01

    A small scale, high speed turbomachine is described, as well as a process for manufacturing the turbomachine. The turbomachine is manufactured by diffusion bonding stacked sheets of metal foil, each of which has been pre-formed to correspond to a cross section of the turbomachine structure. The turbomachines include rotating elements as well as static structures. Using this process, turbomachines may be manufactured with rotating elements that have outer diameters of less than four inches in size, and/or blading heights of less than 0.1 inches. The rotating elements of the turbomachines are capable of rotating at speeds in excess of 150 feet per second. In addition, cooling features may be added internally to blading to facilitate cooling in high temperature operations.

  8. Experiments on high speed ejectors

    NASA Technical Reports Server (NTRS)

    Wu, J. J.

    1986-01-01

    Experimental studies were conducted to investigate the flow and the performance of thrust augmenting ejectors for flight Mach numbers in the range of 0.5 to 0.8, primary air stagnation pressures up to 107 psig (738 kPa), and primary air stagnation temperatures up to 1250 F (677 C). The experiment verified the existence of the second solution ejector flow, where the flow after complete mixing is supersonic. Thrust augmentation in excess of 1.2 was demonstrated for both hot and cold primary jets. The experimental ejector performed better than the corresponding theoretical optimal first solution ejector, where the mixed flow is subsonic. Further studies are required to realize the full potential of the second solution ejector. The research program was started by the Flight Dynamics Research Corporation (FDRC) to investigate the characteristic of a high speed ejector which augments thrust of a jet at high flight speeds.

  9. Faster Is Better: High-Speed Modems.

    ERIC Educational Resources Information Center

    Roth, Cliff

    1995-01-01

    Discusses using high-speed modems to access the Internet. Examines internal and external modems, data speeds, compression and error reduction, faxing and voice capabilities, and software features. Considers ISDN (Integrated Services Digital Network) as the future replacement of high-speed modems. Sidebars present high-speed modem product…

  10. High-Speed TCP Testing

    NASA Technical Reports Server (NTRS)

    Brooks, David E.; Gassman, Holly; Beering, Dave R.; Welch, Arun; Hoder, Douglas J.; Ivancic, William D.

    1999-01-01

    Transmission Control Protocol (TCP) is the underlying protocol used within the Internet for reliable information transfer. As such, there is great interest to have all implementations of TCP efficiently interoperate. This is particularly important for links exhibiting long bandwidth-delay products. The tools exist to perform TCP analysis at low rates and low delays. However, for extremely high-rate and lone-delay links such as 622 Mbps over geosynchronous satellites, new tools and testing techniques are required. This paper describes the tools and techniques used to analyze and debug various TCP implementations over high-speed, long-delay links.

  11. A single shot TDC with 4.8 ps resolution in 40 nm CMOS for high energy physics applications

    NASA Astrophysics Data System (ADS)

    Prinzie, J.; Steyaert, M.; Leroux, P.

    2015-01-01

    A robust TDC with 4.8 ps bin width has been designed for harsh environments and high energy physics applications. The circuit uses resistive interpolation DLL with a novel dual phase detector architecture. This architecture improves startup- and recovery speed from single event strikes without control voltage ripple trade-off and requires no off-line calibrations. A 0.43 LSB DNL has been measured at a power consumption of 4.2 mW with an extended frequency range from 0.8 GHz to 2.4 GHz. The TDC has been processed in 40 nm CMOS technology.

  12. Quiet High-Speed Fan

    NASA Technical Reports Server (NTRS)

    Lieber, Lysbeth; Repp, Russ; Weir, Donald S.

    1996-01-01

    A calibration of the acoustic and aerodynamic prediction methods was performed and a baseline fan definition was established and evaluated to support the quiet high speed fan program. A computational fluid dynamic analysis of the NASA QF-12 Fan rotor, using the DAWES flow simulation program was performed to demonstrate and verify the causes of the relatively poor aerodynamic performance observed during the fan test. In addition, the rotor flowfield characteristics were qualitatively compared to the acoustic measurements to identify the key acoustic characteristics of the flow. The V072 turbofan source noise prediction code was used to generate noise predictions for the TFE731-60 fan at three operating conditions and compared to experimental data. V072 results were also used in the Acoustic Radiation Code to generate far field noise for the TFE731-60 nacelle at three speed points for the blade passage tone. A full 3-D viscous flow simulation of the current production TFE731-60 fan rotor was performed with the DAWES flow analysis program. The DAWES analysis was used to estimate the onset of multiple pure tone noise, based on predictions of inlet shock position as a function of the rotor tip speed. Finally, the TFE731-60 fan rotor wake structure predicted by the DAWES program was used to define a redesigned stator with the leading edge configured to minimize the acoustic effects of rotor wake / stator interaction, without appreciably degrading performance.

  13. High-speed phosphor thermometry.

    PubMed

    Fuhrmann, N; Baum, E; Brübach, J; Dreizler, A

    2011-10-01

    Phosphor thermometry is a semi-invasive surface temperature measurement technique utilising the luminescence properties of doped ceramic materials. Typically, these phosphor materials are coated onto the object of interest and are excited by a short UV laser pulse. Up to now, primarily Q-switched laser systems with repetition rates of 10 Hz were employed for excitation. Accordingly, this diagnostic tool was not applicable to resolve correlated temperature transients at time scales shorter than 100 ms. This contribution reports on the first realisation of a high-speed phosphor thermometry system employing a highly repetitive laser in the kHz regime and a fast decaying phosphor. A suitable material was characterised regarding its temperature lifetime characteristic and its measurement precision. Additionally, the influence of laser power on the phosphor coating was investigated in terms of heating effects. A demonstration of this high-speed technique has been conducted inside the thermally highly transient system of an optically accessible internal combustion engine. Temperatures have been measured with a repetition rate of 6 kHz corresponding to one sample per crank angle degree at 1000 rpm. PMID:22047319

  14. Flexible high-speed CODEC

    NASA Technical Reports Server (NTRS)

    Segallis, Greg P.; Wernlund, Jim V.; Corry, Glen

    1993-01-01

    This report is prepared by Harris Government Communication Systems Division for NASA Lewis Research Center under contract NAS3-25087. It is written in accordance with SOW section 4.0 (d) as detailed in section 2.6. The purpose of this document is to provide a summary of the program, performance results and analysis, and a technical assessment. The purpose of this program was to develop a flexible, high-speed CODEC that provides substantial coding gain while maintaining bandwidth efficiency for use in both continuous and bursted data environments for a variety of applications.

  15. High speed quantitative digital microscopy

    NASA Technical Reports Server (NTRS)

    Castleman, K. R.; Price, K. H.; Eskenazi, R.; Ovadya, M. M.; Navon, M. A.

    1984-01-01

    Modern digital image processing hardware makes possible quantitative analysis of microscope images at high speed. This paper describes an application to automatic screening for cervical cancer. The system uses twelve MC6809 microprocessors arranged in a pipeline multiprocessor configuration. Each processor executes one part of the algorithm on each cell image as it passes through the pipeline. Each processor communicates with its upstream and downstream neighbors via shared two-port memory. Thus no time is devoted to input-output operations as such. This configuration is expected to be at least ten times faster than previous systems.

  16. A high speed sequential decoder

    NASA Technical Reports Server (NTRS)

    Lum, H., Jr.

    1972-01-01

    The performance and theory of operation for the High Speed Hard Decision Sequential Decoder are delineated. The decoder is a forward error correction system which is capable of accepting data from binary-phase-shift-keyed and quadriphase-shift-keyed modems at input data rates up to 30 megabits per second. Test results show that the decoder is capable of maintaining a composite error rate of 0.00001 at an input E sub b/N sub o of 5.6 db. This performance has been obtained with minimum circuit complexity.

  17. Towards a 10 μs, thin and high resolution pixelated CMOS sensor system for future vertex detectors

    NASA Astrophysics Data System (ADS)

    De Masi, R.; Amar-Youcef, S.; Baudot, J.; Bertolone, G.; Brogna, A.; Chon-Sen, N.; Claus, G.; Colledani, C.; Degerli, Y.; Deveaux, M.; Dorokhov, A.; Doziére, G.; Dulinski, W.; Gelin, M.; Goffe, M.; Fontaine, J. C.; Hu-Guo, Ch.; Himmi, A.; Jaaskelainen, K.; Koziel, M.; Morel, F.; Müntz, C.; Orsini, F.; Santos, C.; Schrader, C.; Specht, M.; Stroth, J.; Valin, I.; Voutsinas, G.; Wagner, F. M.; Winter, M.

    2011-02-01

    The physics goals of many high energy experiments require a precise determination of decay vertices, imposing severe constraints on vertex detectors (readout speed, granularity, material budget,…). The IPHC-IRFU collaboration developed a sensor architecture to comply with these requirements. The first full scale CMOS sensor was realised and equips the reference planes of the EUDET beam telescope. Its architecture is being adapted to the needs of the STAR (RHIC) and CBM (FAIR) experiments. It is a promising candidate for the ILC experiments and the ALICE detector upgrade (LHC). A substantial improvement to the CMOS sensor performances, especially in terms of radiation hardness, should come from a new fabrication technology with depleted sensitive volume. A prototype sensor was fabricated to explore the benefits of the technology. The crucial system integration issue is also currently being addressed. In 2009 the PLUME collaboration was set up to investigate the feasibility and performances of a light double sided ladder equipped with CMOS sensors, aimed primarily for the ILC vertex detector but also of interest for other applications such as the CBM vertex detector.

  18. Development of High Speed Digital Camera: EXILIM EX-F1

    NASA Astrophysics Data System (ADS)

    Nojima, Osamu

    The EX-F1 is a high speed digital camera featuring a revolutionary improvement in burst shooting speed that is expected to create entirely new markets. This model incorporates a high speed CMOS sensor and a high speed LSI processor. With this model, CASIO has achieved an ultra-high speed 60 frames per second (fps) burst rate for still images, together with 1,200 fps high speed movie that captures movements which cannot even be seen by human eyes. Moreover, this model can record movies at full High-Definition. After launching it into the market, it was able to get a lot of high appraisals as an innovation camera. We will introduce the concept, features and technologies about the EX-F1.

  19. Remote Transmission at High Speed

    NASA Technical Reports Server (NTRS)

    2003-01-01

    Omni and NASA Test Operations at Stennis entered a Dual-Use Agreement to develop the FOTR-125, a 125 megabit-per-second fiber-optic transceiver that allows accurate digital recordings over a great distance. The transceiver s fiber-optic link can be as long as 25 kilometers. This makes it much longer than the standard coaxial link, which can be no longer than 50 meters.The FOTR-125 utilizes laser diode transmitter modules and integrated receivers for the optical interface. Two transmitters and two receivers are employed at each end of the link with automatic or manual switchover to maximize the reliability of the communications link. NASA uses the transceiver in Stennis High-Speed Data Acquisition System (HSDAS). The HSDAS consists of several identical systems installed on the Center s test stands to process all high-speed data related to its propulsion test programs. These transceivers allow the recorder and HSDAS controls to be located in the Test Control Center in a remote location while the digitizer is located on the test stand.

  20. High speed hybrid active system

    NASA Astrophysics Data System (ADS)

    Gonzalez, Ignacio F.; Chang, Fu-Kuo; Qing, Peter X.; Kumar, Amrita; Zhang, David

    2005-05-01

    A novel piezoelectric/fiber-optic system is developed for long-term health monitoring of aerospace vehicles and structures. The hybrid diagnostic system uses the piezoelectric actuators to input a controlled excitation to the structure and the fiber optic sensors to capture the corresponding structural response. The aim of the system is to detect changes in structures such as those found in aerospace applications (damage, cracks, aging, etc.). This system involves the use of fiber Bragg gratings, which may be either bonded to the surface of the material or embedded within it in order to detect the linear strain component produced by the excitation waves generate by an arbitrary waveform generator. Interrogation of the Bragg gratings is carried out using a high speed fiber grating demodulation unit and a high speed data acquisition card to provide actuation input. With data collection and information processing; is able to determine the condition of the structure. The demands on a system suitable for detecting ultrasonic acoustic waves are different than for the more common strain and temperature systems. On the one hand, the frequency is much higher, with typical values for ultrasonic frequencies used in non-destructive testing ranging from 100 kHz up to several MHz. On the other hand, the related strain levels are much lower, normally in the μstrain range. Fiber-optic solutions for this problem do exist and are particularly attractive for ultrasonic sensing as the sensors offer broadband detection capability.

  1. A Synchronization Algorithm and Implementation for High-Speed Block Codes Applications. Part 4

    NASA Technical Reports Server (NTRS)

    Lin, Shu; Zhang, Yu; Nakamura, Eric B.; Uehara, Gregory T.

    1998-01-01

    Block codes have trellis structures and decoders amenable to high speed CMOS VLSI implementation. For a given CMOS technology, these structures enable operating speeds higher than those achievable using convolutional codes for only modest reductions in coding gain. As a result, block codes have tremendous potential for satellite trunk and other future high-speed communication applications. This paper describes a new approach for implementation of the synchronization function for block codes. The approach utilizes the output of the Viterbi decoder and therefore employs the strength of the decoder. Its operation requires no knowledge of the signal-to-noise ratio of the received signal, has a simple implementation, adds no overhead to the transmitted data, and has been shown to be effective in simulation for received SNR greater than 2 dB.

  2. High-Speed Schlieren Movies of Decelerators at Supersonic Speeds

    NASA Technical Reports Server (NTRS)

    1960-01-01

    High-Speed Schlieren Movies of Decelerators at Supersonic Speeds. Tests were conducted on several types of porous parachutes, a paraglider, and a simulated retrorocket. Mach numbers ranged from 1.8-3.0, porosity from 20-80 percent, and camera speeds from 1680-3000 feet per second (fps) in trials with porous parachutes. Trials of reefed parachutes were conducted at Mach number 2.0 and reefing of 12-33 percent at camera speeds of 600 fps. A flexible parachute with an inflatable ring in the periphery of the canopy was tested at Reynolds number 750,000 per foot, Mach number 2.85, porosity of 28 percent, and camera speed of 36oo fps. A vortex-ring parachute was tested at Mach number 2.2 and camera speed of 3000 fps. The paraglider, with a sweepback of 45 degrees at an angle of attack of 45 degrees was tested at Mach number 2.65, drag coefficient of 0.200, and lift coefficient of 0.278 at a camera speed of 600 fps. A cold air jet exhausting upstream from the center of a bluff body was used to simulate a retrorocket. The free-stream Mach number was 2.0, free-stream dynamic pressure was 620 lb/sq ft, jet-exit static pressure ratio was 10.9, and camera speed was 600 fps. [Entire movie available on DVD from CASI as Doc ID 20070030973. Contact help@sti.nasa.gov

  3. High-Speed Optical Spectroscopy

    NASA Astrophysics Data System (ADS)

    Marsh, T. R.

    The large surveys and sensitive instruments of modern astronomy are turning ever more examples of variable objects, many of which are extending the parameter space to testing theories of stellar evolution and accretion. Future projects such as the Laser Interferometer Space Antenna (LISA) and the Large Synoptic Survey Telescope (LSST) will only add more challenging candidates to this list. Understanding such objects often requires fast spectroscopy, but the trend for ever larger detectors makes this difficult. In this contribution I outline the science made possible by high-speed spectroscopy, and consider how a combination of the well-known progress in computer technology combined with recent advances in CCD detectors may finally enable it to become a standard tool of astrophysics.

  4. High-speed data search

    NASA Technical Reports Server (NTRS)

    Driscoll, James N.

    1994-01-01

    The high-speed data search system developed for KSC incorporates existing and emerging information retrieval technology to help a user intelligently and rapidly locate information found in large textual databases. This technology includes: natural language input; statistical ranking of retrieved information; an artificial intelligence concept called semantics, where 'surface level' knowledge found in text is used to improve the ranking of retrieved information; and relevance feedback, where user judgements about viewed information are used to automatically modify the search for further information. Semantics and relevance feedback are features of the system which are not available commercially. The system further demonstrates focus on paragraphs of information to decide relevance; and it can be used (without modification) to intelligently search all kinds of document collections, such as collections of legal documents medical documents, news stories, patents, and so forth. The purpose of this paper is to demonstrate the usefulness of statistical ranking, our semantic improvement, and relevance feedback.

  5. Flexible High Speed Codec (FHSC)

    NASA Technical Reports Server (NTRS)

    Segallis, G. P.; Wernlund, J. V.

    1991-01-01

    The ongoing NASA/Harris Flexible High Speed Codec (FHSC) program is described. The program objectives are to design and build an encoder decoder that allows operation in either burst or continuous modes at data rates of up to 300 megabits per second. The decoder handles both hard and soft decision decoding and can switch between modes on a burst by burst basis. Bandspreading is low since the code rate is greater than or equal to 7/8. The encoder and a hard decision decoder fit on a single application specific integrated circuit (ASIC) chip. A soft decision applique is implemented using 300 K emitter coupled logic (ECL) which can be easily translated to an ECL gate array.

  6. Preliminary study of high-speed machining

    SciTech Connect

    Jordan, R.E.

    1980-07-01

    The feasibility of a high speed machining process has been established for application to Bendix aluminum products, based upon information gained through visits to existing high speed machining facilities and by the completion of a representative Bendix part using this process. The need for an experimental high speed machining capability at Bendix for further process evaluation is established.

  7. High speed sampler and demultiplexer

    DOEpatents

    McEwan, Thomas E.

    1995-01-01

    A high speed sampling demultiplexer based on a plurality of sampler banks, each bank comprising a sample transmission line for transmitting an input signal, a strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates at respective positions along the sample transmission line for sampling the input signal in response to the strobe signal. Strobe control circuitry is coupled to the plurality of banks, and supplies a sequence of bank strobe signals to the strobe transmission lines in each of the plurality of banks, and includes circuits for controlling the timing of the bank strobe signals among the banks of samplers. Input circuitry is included for supplying the input signal to be sampled to the plurality of sample transmission lines in the respective banks. The strobe control circuitry can repetitively strobe the plurality of banks of samplers such that the banks of samplers are cycled to create a long sample length. Second tier demultiplexing circuitry is coupled to each of the samplers in the plurality of banks. The second tier demultiplexing circuitry senses the sample taken by the corresponding sampler each time the bank in which the sampler is found is strobed. A plurality of such samples can be stored by the second tier demultiplexing circuitry for later processing. Repetitive sampling with the high speed transient sampler induces an effect known as "strobe kickout". The sample transmission lines include structures which reduce strobe kickout to acceptable levels, generally 60 dB below the signal, by absorbing the kickout pulses before the next sampling repetition.

  8. High speed sampler and demultiplexer

    DOEpatents

    McEwan, T.E.

    1995-12-26

    A high speed sampling demultiplexer based on a plurality of sampler banks, each bank comprising a sample transmission line for transmitting an input signal, a strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates at respective positions along the sample transmission line for sampling the input signal in response to the strobe signal. Strobe control circuitry is coupled to the plurality of banks, and supplies a sequence of bank strobe signals to the strobe transmission lines in each of the plurality of banks, and includes circuits for controlling the timing of the bank strobe signals among the banks of samplers. Input circuitry is included for supplying the input signal to be sampled to the plurality of sample transmission lines in the respective banks. The strobe control circuitry can repetitively strobe the plurality of banks of samplers such that the banks of samplers are cycled to create a long sample length. Second tier demultiplexing circuitry is coupled to each of the samplers in the plurality of banks. The second tier demultiplexing circuitry senses the sample taken by the corresponding sampler each time the bank in which the sampler is found is strobed. A plurality of such samples can be stored by the second tier demultiplexing circuitry for later processing. Repetitive sampling with the high speed transient sampler induces an effect known as ``strobe kickout``. The sample transmission lines include structures which reduce strobe kickout to acceptable levels, generally 60 dB below the signal, by absorbing the kickout pulses before the next sampling repetition. 16 figs.

  9. CMOS compatible high-Q photonic crystal nanocavity fabricated with photolithography on silicon photonic platform

    PubMed Central

    Ooka, Yuta; Tetsumoto, Tomohiro; Fushimi, Akihiro; Yoshiki, Wataru; Tanabe, Takasumi

    2015-01-01

    Progress on the fabrication of ultrahigh-Q photonic-crystal nanocavities (PhC-NCs) has revealed the prospect for new applications including silicon Raman lasers that require a strong confinement of light. Among various PhC-NCs, the highest Q has been recorded with silicon. On the other hand, microcavity is one of the basic building blocks in silicon photonics. However, the fusion between PhC-NCs and silicon photonics has yet to be exploited, since PhC-NCs are usually fabricated with electron-beam lithography and require an air-bridge structure. Here we show that a 2D-PhC-NC fabricated with deep-UV photolithography on a silica-clad silicon-on-insulator (SOI) structure will exhibit a high-Q of 2.2 × 105 with a mode-volume of ~1.7(λ/n)3. This is the highest Q demonstrated with photolithography. We also show that this device exhibits an efficient thermal diffusion and enables high-speed switching. The demonstration of the photolithographic fabrication of high-Q silica-clad PhC-NCs will open possibility for mass-manufacturing and boost the fusion between silicon photonics and CMOS devices. PMID:26086849

  10. CMOS compatible high-Q photonic crystal nanocavity fabricated with photolithography on silicon photonic platform.

    PubMed

    Ooka, Yuta; Tetsumoto, Tomohiro; Fushimi, Akihiro; Yoshiki, Wataru; Tanabe, Takasumi

    2015-01-01

    Progress on the fabrication of ultrahigh-Q photonic-crystal nanocavities (PhC-NCs) has revealed the prospect for new applications including silicon Raman lasers that require a strong confinement of light. Among various PhC-NCs, the highest Q has been recorded with silicon. On the other hand, microcavity is one of the basic building blocks in silicon photonics. However, the fusion between PhC-NCs and silicon photonics has yet to be exploited, since PhC-NCs are usually fabricated with electron-beam lithography and require an air-bridge structure. Here we show that a 2D-PhC-NC fabricated with deep-UV photolithography on a silica-clad silicon-on-insulator (SOI) structure will exhibit a high-Q of 2.2 × 10(5) with a mode-volume of ~ 1.7(λ/n)(3). This is the highest Q demonstrated with photolithography. We also show that this device exhibits an efficient thermal diffusion and enables high-speed switching. The demonstration of the photolithographic fabrication of high-Q silica-clad PhC-NCs will open possibility for mass-manufacturing and boost the fusion between silicon photonics and CMOS devices. PMID:26086849

  11. Development of low read noise high conversion gain CMOS image sensor for photon counting level imaging

    NASA Astrophysics Data System (ADS)

    Seo, Min-Woong; Kawahito, Shoji; Kagawa, Keiichiro; Yasutomi, Keita

    2016-05-01

    A CMOS image sensor with deep sub-electron read noise and high pixel conversion gain has been developed. Its performance is recognized through image outputs from an area image sensor, confirming the capability of photoelectroncounting- level imaging. To achieve high conversion gain, the proposed pixel has special structures to reduce the parasitic capacitances around FD node. As a result, the pixel conversion gain is increased due to the optimized FD node capacitance, and the noise performance is also improved by removing two noise sources from power supply. For the first time, high contrast images from the reset-gate-less CMOS image sensor, with less than 0.3e- rms noise level, have been generated at an extremely low light level of a few electrons per pixel. In addition, the photon-counting capability of the developed CMOS imager is demonstrated by a measurement, photoelectron-counting histogram (PCH).

  12. Prototyping of an HV-CMOS demonstrator for the High Luminosity-LHC upgrade

    NASA Astrophysics Data System (ADS)

    Vilella, E.; Benoit, M.; Casanova, R.; Casse, G.; Ferrere, D.; Iacobucci, G.; Peric, I.; Vossebeld, J.

    2016-01-01

    HV-CMOS sensors can offer important advantages in terms of material budget, granularity and cost for large area tracking systems in high energy physics experiments. This article presents the design and simulated results of an HV-CMOS pixel demonstrator for the High Luminosity-LHC. The pixel demonstrator has been designed in the 0.35 μm HV-CMOS process from ams AG and submitted for fabrication through an engineering run. To improve the response of the sensor, different wafers with moderate to high substrate resistivities are used to fabricate the design. The prototype consists of four large analog and standalone matrices with several pixel flavours, which are all compatible for readout with the FE-I4 ASIC. Details about the matrices and the pixel flavours are provided in this article.

  13. ADVANCED HIGH SPEED PROGRAMMABLE PREFORMING

    SciTech Connect

    Norris Jr, Robert E; Lomax, Ronny D; Xiong, Fue; Dahl, Jeffrey S; Blanchard, Patrick J

    2010-01-01

    Polymer-matrix composites offer greater stiffness and strength per unit weight than conventional materials resulting in new opportunities for lightweighting of automotive and heavy vehicles. Other benefits include design flexibility, less corrosion susceptibility, and the ability to tailor properties to specific load requirements. However, widespread implementation of structural composites requires lower-cost manufacturing processes than those that are currently available. Advanced, directed-fiber preforming processes have demonstrated exceptional value for rapid preforming of large, glass-reinforced, automotive composite structures. This is due to process flexibility and inherently low material scrap rate. Hence directed fiber performing processes offer a low cost manufacturing methodology for producing preforms for a variety of structural automotive components. This paper describes work conducted at the Oak Ridge National Laboratory (ORNL), focused on the development and demonstration of a high speed chopper gun to enhance throughput capabilities. ORNL and the Automotive Composites Consortium (ACC) revised the design of a standard chopper gun to expand the operational envelope, enabling delivery of up to 20kg/min. A prototype unit was fabricated and used to demonstrate continuous chopping of multiple roving at high output over extended periods. In addition fiber handling system modifications were completed to sustain the high output the modified chopper affords. These hardware upgrades are documented along with results of process characterization and capabilities assessment.

  14. Use of CMOS imagers to measure high fluxes of charged particles

    NASA Astrophysics Data System (ADS)

    Servoli, L.; Tucceri, P.

    2016-03-01

    The measurement of high flux charged particle beams, specifically at medical accelerators and with small fields, poses several challenges. In this work we propose a single particle counting method based on CMOS imagers optimized for visible light collection, exploiting their very high spatial segmentation (> 3 106 pixels/cm2) and almost full efficiency detection capability. An algorithm to measure the charged particle flux with a precision of ~ 1% for fluxes up to 40 MHz/cm2 has been developed, using a non-linear calibration algorithm, and several CMOS imagers with different characteristics have been compared to find their limits on flux measurement.

  15. High-stage analog accumulator for TDI CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Jianxin, Li; Fujun, Huang; Yong, Zong; Jing, Gao

    2016-02-01

    The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is employed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature (PVT) variations. The post layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 dB, while an ideal value is 21.072 dB. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. Furthermore, it is promising to design a higher stage accumulator based on the proposed structure. Project supported by the National Natural Science Foundation of China (Nos. 61404090, 61434004).

  16. High speed imager test station

    DOEpatents

    Yates, George J.; Albright, Kevin L.; Turko, Bojan T.

    1995-01-01

    A test station enables the performance of a solid state imager (herein called a focal plane array or FPA) to be determined at high image frame rates. A programmable waveform generator is adapted to generate clock pulses at determinable rates for clock light-induced charges from a FPA. The FPA is mounted on an imager header board for placing the imager in operable proximity to level shifters for receiving the clock pulses and outputting pulses effective to clock charge from the pixels forming the FPA. Each of the clock level shifters is driven by leading and trailing edge portions of the clock pulses to reduce power dissipation in the FPA. Analog circuits receive output charge pulses clocked from the FPA pixels. The analog circuits condition the charge pulses to cancel noise in the pulses and to determine and hold a peak value of the charge for digitizing. A high speed digitizer receives the peak signal value and outputs a digital representation of each one of the charge pulses. A video system then displays an image associated with the digital representation of the output charge pulses clocked from the FPA. In one embodiment, the FPA image is formatted to a standard video format for display on conventional video equipment.

  17. High speed imager test station

    DOEpatents

    Yates, G.J.; Albright, K.L.; Turko, B.T.

    1995-11-14

    A test station enables the performance of a solid state imager (herein called a focal plane array or FPA) to be determined at high image frame rates. A programmable waveform generator is adapted to generate clock pulses at determinable rates for clock light-induced charges from a FPA. The FPA is mounted on an imager header board for placing the imager in operable proximity to level shifters for receiving the clock pulses and outputting pulses effective to clock charge from the pixels forming the FPA. Each of the clock level shifters is driven by leading and trailing edge portions of the clock pulses to reduce power dissipation in the FPA. Analog circuits receive output charge pulses clocked from the FPA pixels. The analog circuits condition the charge pulses to cancel noise in the pulses and to determine and hold a peak value of the charge for digitizing. A high speed digitizer receives the peak signal value and outputs a digital representation of each one of the charge pulses. A video system then displays an image associated with the digital representation of the output charge pulses clocked from the FPA. In one embodiment, the FPA image is formatted to a standard video format for display on conventional video equipment. 12 figs.

  18. A high frame rate, 16 million pixels, radiation hard CMOS sensor

    NASA Astrophysics Data System (ADS)

    Guerrini, N.; Turchetta, R.; Van Hoften, G.; Henderson, R.; McMullan, G.; Faruqi, A. R.

    2011-03-01

    CMOS sensors provide the possibility of designing detectors for a large variety of applications with all the benefits and flexibility of the widely used CMOS process. In this paper we describe a novel CMOS sensor designed for transmission electron microscopy. The overall design consists of a large 61 × 63 mm2 silicon area containing 16 million pixels arranged in a 4K × 4K array, with radiation hard geometry. All this is combined with a very fast readout, the possibility of region of interest (ROI) readout, pixel binning with consequent frame rate increase and a dynamic range close to 12 bits. The high frame rate has been achieved using 32 parallel analogue outputs each one operating at up to 20 MHz. Binning of pixels can be controlled externally and the flexibility of the design allows several possibilities, such as 2 × 2 or 4 × 4 binning. Other binning configurations where the number of rows and the number of columns are not equal, such as 2 × 1 or 2 × 4, are also possible. Having control of the CMOS design allowed us to optimise the pixel design, in particular with regard to its radiation hardness, and to make optimum choices in the design of other regions of the final sensor. An early prototype was also designed with a variety of geometries in order to optimise the readout structure and these are presented. The sensor was manufactured in a 0.35 μm standard CMOS process.

  19. High-speed, electronically shuttered solid-state imager technology (invited)

    NASA Astrophysics Data System (ADS)

    Reich, R. K.; Rathman, D. D.; O'Mara, D. M.; Young, D. J.; Loomis, A. H.; Kohler, E. J.; Osgood, R. M.; Murphy, R. A.; Rose, M.; Berger, R.; Watson, S. A.; Ulibarri, M. D.; Perry, T.; Kosicki, B. B.

    2003-03-01

    Electronically shuttered solid-state imagers are being developed for high-speed imaging applications. A 5 cm×5 cm, 512×512-element, multiframe charge-coupled device (CCD) imager has been fabricated for the Los Alamos National Laboratory DARHT facility that collects four sequential image frames at megahertz rates. To operate at fast frame rates with high sensitivity, the imager uses an electronic shutter technology designed for back-illuminated CCDs. The design concept and test results are described for the burst-frame-rate imager. Also discussed is an evolving solid-state imager technology that has interesting characteristics for creating large-format x-ray detectors with short integration times (100 ps to 1 ns). Proposed device architectures use CMOS technology for high speed sampling (tens of picoseconds transistor switching times). Techniques for parallel clock distribution, that triggers the sampling of x-ray photoelectrons, will be described that exploit features of CMOS technology.

  20. High-speed pressure clamp.

    PubMed

    Besch, Stephen R; Suchyna, Thomas; Sachs, Frederick

    2002-10-01

    We built a high-speed, pneumatic pressure clamp to stimulate patch-clamped membranes mechanically. The key control element is a newly designed differential valve that uses a single, nickel-plated piezoelectric bending element to control both pressure and vacuum. To minimize response time, the valve body was designed with minimum dead volume. The result is improved response time and stability with a threefold decrease in actuation latency. Tight valve clearances minimize the steady-state air flow, permitting us to use small resonant-piston pumps to supply pressure and vacuum. To protect the valve from water contamination in the event of a broken pipette, an optical sensor detects water entering the valve and increases pressure rapidly to clear the system. The open-loop time constant for pressure is 2.5 ms for a 100-mmHg step, and the closed-loop settling time is 500-600 micros. Valve actuation latency is 120 micros. The system performance is illustrated for mechanically induced changes in patch capacitance. PMID:12397401

  1. High speed all optical networks

    NASA Technical Reports Server (NTRS)

    Chlamtac, Imrich; Ganz, Aura

    1990-01-01

    An inherent problem of conventional point-to-point wide area network (WAN) architectures is that they cannot translate optical transmission bandwidth into comparable user available throughput due to the limiting electronic processing speed of the switching nodes. The first solution to wavelength division multiplexing (WDM) based WAN networks that overcomes this limitation is presented. The proposed Lightnet architecture takes into account the idiosyncrasies of WDM switching/transmission leading to an efficient and pragmatic solution. The Lightnet architecture trades the ample WDM bandwidth for a reduction in the number of processing stages and a simplification of each switching stage, leading to drastically increased effective network throughputs. The principle of the Lightnet architecture is the construction and use of virtual topology networks, embedded in the original network in the wavelength domain. For this construction Lightnets utilize the new concept of lightpaths which constitute the links of the virtual topology. Lightpaths are all-optical, multihop, paths in the network that allow data to be switched through intermediate nodes using high throughput passive optical switches. The use of the virtual topologies and the associated switching design introduce a number of new ideas, which are discussed in detail.

  2. High-speed Wind Tunnels

    NASA Technical Reports Server (NTRS)

    Ackeret, J

    1936-01-01

    Wind tunnel construction and design is discussed especially in relation to subsonic and supersonic speeds. Reynolds Numbers and the theory of compressible flows are also taken into consideration in designing new tunnels.

  3. A very high speed lossless compression/decompression chip set

    NASA Technical Reports Server (NTRS)

    Venbrux, Jack; Liu, Norley; Liu, Kathy; Vincent, Peter; Merrell, Randy

    1991-01-01

    A chip is described that will perform lossless compression and decompression using the Rice Algorithm. The chip set is designed to compress and decompress source data in real time for many applications. The encoder is designed to code at 20 M samples/second at MIL specifications. That corresponds to 280 Mbits/second at maximum quantization or approximately 500 Mbits/second under nominal conditions. The decoder is designed to decode at 10 M samples/second at industrial specifications. A wide range of quantization levels is allowed (4...14 bits) and both nearest neighbor prediction and external prediction are supported. When the pre and post processors are bypassed, the chip set performs high speed entropy coding and decoding. This frees the chip set from being tied to one modeling technique or specific application. Both the encoder and decoder are being fabricated in a 1.0 micron CMOS process that has been tested to survive 1 megarad of total radiation dosage. The CMOS chips are small, only 5 mm on a side, and both are estimated to consume less than 1/4 of a Watt of power while operating at maximum frequency.

  4. Lincoln Laboratory high-speed solid-state imager technology

    NASA Astrophysics Data System (ADS)

    Reich, R. K.; Rathman, D. D.; O'Mara, D. M.; Young, D. J.; Loomis, A. H.; Osgood, R. M.; Murphy, R. A.; Rose, M.; Berger, R.; Tyrrell, B. M.; Watson, S. A.; Ulibarri, M. D.; Perry, T.; Weber, F.; Robey, H.

    2007-01-01

    Massachusetts Institute of Technology, Lincoln Laboratory (MIT LL) has been developing both continuous and burst solid-state focal-plane-array technology for a variety of high-speed imaging applications. For continuous imaging, a 128 × 128-pixel charge coupled device (CCD) has been fabricated with multiple output ports for operating rates greater than 10,000 frames per second with readout noise of less than 10 e- rms. An electronic shutter has been integrated into the pixels of the back-illuminated (BI) CCD imagers that give snapshot exposure times of less than 10 ns. For burst imaging, a 5 cm × 5 cm, 512 × 512-element, multi-frame CCD imager that collects four sequential image frames at megahertz rates has been developed for the Los Alamos National Laboratory Dual Axis Radiographic Hydrodynamic Test (DARHT) facility. To operate at fast frame rates with high sensitivity, the imager uses the same electronic shutter technology as the continuously framing 128 × 128 CCD imager. The design concept and test results are described for the burst-frame-rate imager. Also discussed is an evolving solid-state imager technology that has interesting characteristics for creating large-format x-ray detectors with ultra-short exposure times (100 to 300 ps). The detector will consist of CMOS readouts for high speed sampling (tens of picoseconds transistor switching times) that are bump bonded to deep-depletion silicon photodiodes. A 64 × 64-pixel CMOS test chip has been designed, fabricated and characterized to investigate the feasibility of making large-format detectors with short, simultaneous exposure times.

  5. High-Q CMOS-integrated photonic crystal microcavity devices

    PubMed Central

    Mehta, Karan K.; Orcutt, Jason S.; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J.

    2014-01-01

    Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300–9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems. PMID:24518161

  6. High-speed detection of DNA translocation in nanopipettes.

    PubMed

    Fraccari, Raquel L; Ciccarella, Pietro; Bahrami, Azadeh; Carminati, Marco; Ferrari, Giorgio; Albrecht, Tim

    2016-04-14

    We present a high-speed electrical detection scheme based on a custom-designed CMOS amplifier which allows the analysis of DNA translocation in glass nanopipettes on a microsecond timescale. Translocation of different DNA lengths in KCl electrolyte provides a scaling factor of the DNA translocation time equal to p = 1.22, which is different from values observed previously with nanopipettes in LiCl electrolyte or with nanopores. Based on a theoretical model involving electrophoresis, hydrodynamics and surface friction, we show that the experimentally observed range of p-values may be the result of, or at least be affected by DNA adsorption and friction between the DNA and the substrate surface. PMID:26985713

  7. High-speed camera with internal real-time image processing

    NASA Astrophysics Data System (ADS)

    Paindavoine, M.; Mosqueron, R.; Dubois, J.; Clerc, C.; Grapin, J. C.; Tomasini, F.

    2005-08-01

    High-speed video cameras are powerful tools for investigating for instance the dynamics of fluids or the movements of mechanical parts in manufacturing processes. In the past years, the use of CMOS sensors instead of CCDs have made possible the development of high-speed video cameras offering digital outputs, readout flexibility and lower manufacturing costs. In this field, we designed a new fast CMOS camera with a 1280×1024 pixels resolution at 500 fps. In order to transmit from the camera only useful information from the fast images, we studied some specific algorithms like edge detection, wavelet analysis, image compression and object tracking. These image processing algorithms have been implemented into a FPGA embedded inside the camera. This FPGA technology allows us to process fast images in real time.

  8. High-speed detection of DNA translocation in nanopipettes

    NASA Astrophysics Data System (ADS)

    Fraccari, Raquel L.; Ciccarella, Pietro; Bahrami, Azadeh; Carminati, Marco; Ferrari, Giorgio; Albrecht, Tim

    2016-03-01

    We present a high-speed electrical detection scheme based on a custom-designed CMOS amplifier which allows the analysis of DNA translocation in glass nanopipettes on a microsecond timescale. Translocation of different DNA lengths in KCl electrolyte provides a scaling factor of the DNA translocation time equal to p = 1.22, which is different from values observed previously with nanopipettes in LiCl electrolyte or with nanopores. Based on a theoretical model involving electrophoresis, hydrodynamics and surface friction, we show that the experimentally observed range of p-values may be the result of, or at least be affected by DNA adsorption and friction between the DNA and the substrate surface.We present a high-speed electrical detection scheme based on a custom-designed CMOS amplifier which allows the analysis of DNA translocation in glass nanopipettes on a microsecond timescale. Translocation of different DNA lengths in KCl electrolyte provides a scaling factor of the DNA translocation time equal to p = 1.22, which is different from values observed previously with nanopipettes in LiCl electrolyte or with nanopores. Based on a theoretical model involving electrophoresis, hydrodynamics and surface friction, we show that the experimentally observed range of p-values may be the result of, or at least be affected by DNA adsorption and friction between the DNA and the substrate surface. Electronic supplementary information (ESI) available: Gel electrophoresis confirming lengths and purity of DNA samples, comparison between Axopatch 200B and custom-built setup, comprehensive low-noise amplifier characterization, representative I-V curves of nanopipettes used, typical scatter plots of τ vs. peak amplitude for the four LDNA's used, table of most probable τ values, a comparison between different fitting models for the DNA translocation time distribution, further details on the stochastic numerical simulation of the scaling statistics and the derivation of the extended

  9. Review of high speed communications photomultiplier detectors

    NASA Technical Reports Server (NTRS)

    Enck, R. S.; Abraham, W. G.

    1978-01-01

    Four types of newly developed high speed photomultipliers are discussed: all electrostatic; static crossed field; dynamic crossed field; and hybrid (EBS). Design, construction, and performance parameters of each class are presented along with limitations of each class of device and prognosis for its future in high speed light detection. The particular advantage of these devices lies in high speed applications using low photon flux, large cathode areas, and broadband optical detection.

  10. High speed imaging - An important industrial tool

    NASA Technical Reports Server (NTRS)

    Moore, Alton; Pinelli, Thomas E.

    1986-01-01

    High-speed photography, which is a rapid sequence of photographs that allow an event to be analyzed through the stoppage of motion or the production of slow-motion effects, is examined. In high-speed photography 16, 35, and 70 mm film and framing rates between 64-12,000 frames per second are utilized to measure such factors as angles, velocities, failure points, and deflections. The use of dual timing lamps in high-speed photography and the difficulties encountered with exposure and programming the camera and event are discussed. The application of video cameras to the recording of high-speed events is described.

  11. High speed imaging - An important industrial tool

    NASA Astrophysics Data System (ADS)

    Moore, Alton; Pinelli, Thomas E.

    1986-05-01

    High-speed photography, which is a rapid sequence of photographs that allow an event to be analyzed through the stoppage of motion or the production of slow-motion effects, is examined. In high-speed photography 16, 35, and 70 mm film and framing rates between 64-12,000 frames per second are utilized to measure such factors as angles, velocities, failure points, and deflections. The use of dual timing lamps in high-speed photography and the difficulties encountered with exposure and programming the camera and event are discussed. The application of video cameras to the recording of high-speed events is described.

  12. A High Frequency Active Voltage Doubler in Standard CMOS Using Offset-Controlled Comparators for Inductive Power Transmission

    PubMed Central

    Lee, Hyung-Min; Ghovanloo, Maysam

    2014-01-01

    In this paper, we present a fully integrated active voltage doubler in CMOS technology using offset-controlled high speed comparators for extending the range of inductive power transmission to implantable microelectronic devices (IMD) and radio-frequency identification (RFID) tags. This active voltage doubler provides considerably higher power conversion efficiency (PCE) and lower dropout voltage compared to its passive counterpart and requires lower input voltage than active rectifiers, leading to reliable and efficient operation with weakly coupled inductive links. The offset-controlled functions in the comparators compensate for turn-on and turn-off delays to not only maximize the forward charging current to the load but also minimize the back current, optimizing PCE in the high frequency (HF) band. We fabricated the active voltage doubler in a 0.5-μm 3M2P std. CMOS process, occupying 0.144 mm2 of chip area. With 1.46 V peak AC input at 13.56 MHz, the active voltage doubler provides 2.4 V DC output across a 1 kΩ load, achieving the highest PCE = 79% ever reported at this frequency. In addition, the built-in start-up circuit ensures a reliable operation at lower voltages. PMID:23853321

  13. A high frequency active voltage doubler in standard CMOS using offset-controlled comparators for inductive power transmission.

    PubMed

    Lee, Hyung-Min; Ghovanloo, Maysam

    2013-06-01

    In this paper, we present a fully integrated active voltage doubler in CMOS technology using offset-controlled high speed comparators for extending the range of inductive power transmission to implantable microelectronic devices (IMD) and radio-frequency identification (RFID) tags. This active voltage doubler provides considerably higher power conversion efficiency (PCE) and lower dropout voltage compared to its passive counterpart and requires lower input voltage than active rectifiers, leading to reliable and efficient operation with weakly coupled inductive links. The offset-controlled functions in the comparators compensate for turn-on and turn-off delays to not only maximize the forward charging current to the load but also minimize the back current, optimizing PCE in the high frequency (HF) band. We fabricated the active voltage doubler in a 0.5-μm 3M2P std . CMOS process, occupying 0.144 mm(2) of chip area. With 1.46 V peak AC input at 13.56 MHz, the active voltage doubler provides 2.4 V DC output across a 1 kΩ load, achieving the highest PCE = 79% ever reported at this frequency. In addition, the built-in start-up circuit ensures a reliable operation at lower voltages. PMID:23853321

  14. High-Speed Ring Bus

    NASA Technical Reports Server (NTRS)

    Wysocky, Terry; Kopf, Edward, Jr.; Katanyoutananti, Sunant; Steiner, Carl; Balian, Harry

    2010-01-01

    The high-speed ring bus at the Jet Propulsion Laboratory (JPL) allows for future growth trends in spacecraft seen with future scientific missions. This innovation constitutes an enhancement of the 1393 bus as documented in the Institute of Electrical and Electronics Engineers (IEEE) 1393-1999 standard for a spaceborne fiber-optic data bus. It allows for high-bandwidth and time synchronization of all nodes on the ring. The JPL ring bus allows for interconnection of active units with autonomous operation and increased fault handling at high bandwidths. It minimizes the flight software interface with an intelligent physical layer design that has few states to manage as well as simplified testability. The design will soon be documented in the AS-1393 standard (Serial Hi-Rel Ring Network for Aerospace Applications). The framework is designed for "Class A" spacecraft operation and provides redundant data paths. It is based on "fault containment regions" and "redundant functional regions (RFR)" and has a method for allocating cables that completely supports the redundancy in spacecraft design, allowing for a complete RFR to fail. This design reduces the mass of the bus by incorporating both the Control Unit and the Data Unit in the same hardware. The standard uses ATM (asynchronous transfer mode) packets, standardized by ITU-T, ANSI, ETSI, and the ATM Forum. The IEEE-1393 standard uses the UNI form of the packet and provides no protection for the data portion of the cell. The JPL design adds optional formatting to this data portion. This design extends fault protection beyond that of the interconnect. This includes adding protection to the data portion that is contained within the Bus Interface Units (BIUs) and by adding to the signal interface between the Data Host and the JPL 1393 Ring Bus. Data transfer on the ring bus does not involve a master or initiator. Following bus protocol, any BIU may transmit data on the ring whenever it has data received from its host. There

  15. A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

    PubMed

    Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

    2016-01-01

    A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented. PMID:27104122

  16. High speed nano-metrology

    SciTech Connect

    Humphris, Andrew D. L.; Zhao Bin; Catto, David; Kohli, Priyanka; Howard-Knight, Jeremy P.; Hobbs, Jamie K.

    2011-04-15

    For manufacturing at the nanometre scale a method for rapid and accurate measurement of the resultant functional devices is required. Although atomic force microscopy (AFM) has the requisite spatial resolution, it is severely limited in scan speed, the resolution and repeatability of vertical and lateral measurements being degraded when speed is increased. Here we present a new approach to AFM that makes a direct and feedback-independent measurement of surface height using a laser interferometer focused onto the back of the AFM tip. Combining this direct height measurement with a passive, feedback-free method for maintaining tip-sample contact removes the constraint on scan speed that comes from the bandwidth of the z-feedback loop. Conventional laser reflection detection is used for feedback control, which now plays the role of minimising tip-sample forces, rather than producing the sample topography. Using the system in conjunction with a rapid scanner, true height images are obtained with areas up to (36 x 36) {mu}m{sup 2} at 1 image/second, suitable for in-line applications.

  17. Design and Fabrication of High-Efficiency CMOS/CCD Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2007-01-01

    An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the

  18. Aerodynamic Characteristics of Airfoils at High Speeds

    NASA Technical Reports Server (NTRS)

    Briggs, L J; Hull, G F; Dryden, H L

    1925-01-01

    This report deals with an experimental investigation of the aerodynamical characteristics of airfoils at high speeds. Lift, drag, and center of pressure measurements were made on six airfoils of the type used by the air service in propeller design, at speeds ranging from 550 to 1,000 feet per second. The results show a definite limit to the speed at which airfoils may efficiently be used to produce lift, the lift coefficient decreasing and the drag coefficient increasing as the speed approaches the speed of sound. The change in lift coefficient is large for thick airfoil sections (camber ratio 0.14 to 0.20) and for high angles of attack. The change is not marked for thin sections (camber ratio 0.10) at low angles of attack, for the speed range employed. At high speeds the center of pressure moves back toward the trailing edge of the airfoil as the speed increases. The results indicate that the use of tip speeds approaching the speed of sound for propellers of customary design involves a serious loss in efficiency.

  19. X-ray characterization of CMOS imaging detector with high resolution for fluoroscopic imaging application

    NASA Astrophysics Data System (ADS)

    Cha, Bo Kyung; Kim, Cho Rong; Jeon, Seongchae; Kim, Ryun Kyung; Seo, Chang-Woo; Yang, Keedong; Heo, Duchang; Lee, Tae-Bum; Shin, Min-Seok; Kim, Jong-Boo; Kwon, Oh-Kyung

    2013-12-01

    This paper introduces complementary metal-oxide semiconductor (CMOS) active pixel sensor (APS)-based X-ray imaging detectors with high spatial resolution for medical imaging application. In this study, our proposed X-ray CMOS imaging sensor has been fabricated by using a 0.35 μm 1 Poly 4 Metal CMOS process. The pixel size is 100 μm×100 μm and the pixel array format is 24×96 pixels, which provide a field-of-view (FOV) of 9.6 mm×2.4 mm. The 14.3-bit extend counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. Both thallium-doped CsI (CsI:Tl) and Gd2O2S:Tb scintillator screens were used as converters for incident X-rays to visible light photons. The optical property and X-ray imaging characterization such as X-ray to light response as a function of incident X-ray exposure dose, spatial resolution and X-ray images of objects were measured under different X-ray energy conditions. The measured results suggest that our developed CMOS-based X-ray imaging detector has the potential for fluoroscopic imaging and cone-beam computed tomography (CBCT) imaging applications.

  20. High-Speed Photography with Computer Control.

    ERIC Educational Resources Information Center

    Winters, Loren M.

    1991-01-01

    Describes the use of a microcomputer as an intervalometer for the control and timing of several flash units to photograph high-speed events. Applies this technology to study the oscillations of a stretched rubber band, the deceleration of high-speed projectiles in water, the splashes of milk drops, and the bursts of popcorn kernels. (MDH)

  1. High Speed Video for Airborne Instrumentation Application

    NASA Technical Reports Server (NTRS)

    Tseng, Ting; Reaves, Matthew; Mauldin, Kendall

    2006-01-01

    A flight-worthy high speed color video system has been developed. Extensive system development and ground and environmental. testing hes yielded a flight qualified High Speed Video System (HSVS), This HSVS was initially used on the F-15B #836 for the Lifting Insulating Foam Trajectory (LIFT) project.

  2. Reducing Heating In High-Speed Cinematography

    NASA Technical Reports Server (NTRS)

    Slater, Howard A.

    1989-01-01

    Infrared-absorbing and infrared-reflecting glass filters simple and effective means for reducing rise in temperature during high-speed motion-picture photography. "Hot-mirror" and "cold-mirror" configurations, employed in projection of images, helps prevent excessive heating of scenes by powerful lamps used in high-speed photography.

  3. High speed flow past wings

    NASA Technical Reports Server (NTRS)

    Norstrud, H.

    1973-01-01

    The analytical solution to the transonic small perturbation equation which describes steady compressible flow past finite wings at subsonic speeds can be expressed as a nonlinear integral equation with the perturbation velocity potential as the unknown function. This known formulation is substituted by a system of nonlinear algebraic equations to which various methods are applicable for its solution. Due to the presence of mathematical discontinuities in the flow solutions, however, a main computational difficulty was to ensure uniqueness of the solutions when local velocities on the wing exceeded the speed of sound. For continuous solutions this was achieved by embedding the algebraic system in an one-parameter operator homotopy in order to apply the method of parametric differentiation. The solution to the initial system of equations appears then as a solution to a Cauchy problem where the initial condition is related to the accompanying incompressible flow solution. In using this technique, however, a continuous dependence of the solution development on the initial data is lost when the solution reaches the minimum bifurcation point. A steepest descent iteration technique was therefore, added to the computational scheme for the calculation of discontinuous flow solutions. Results for purely subsonic flows and supersonic flows with and without compression shocks are given and compared with other available theoretical solutions.

  4. Region-of-interest cone beam computed tomography (ROI CBCT) with a high resolution CMOS detector

    NASA Astrophysics Data System (ADS)

    Jain, A.; Takemoto, H.; Silver, M. D.; Nagesh, S. V. S.; Ionita, C. N.; Bednarek, D. R.; Rudin, S.

    2015-03-01

    Cone beam computed tomography (CBCT) systems with rotational gantries that have standard flat panel detectors (FPD) are widely used for the 3D rendering of vascular structures using Feldkamp cone beam reconstruction algorithms. One of the inherent limitations of these systems is limited resolution (<3 lp/mm). There are systems available with higher resolution but their small FOV limits them to small animal imaging only. In this work, we report on region-of-interest (ROI) CBCT with a high resolution CMOS detector (75 μm pixels, 600 μm HR-CsI) mounted with motorized detector changer on a commercial FPD-based C-arm angiography gantry (194 μm pixels, 600 μm HL-CsI). A cylindrical CT phantom and neuro stents were imaged with both detectors. For each detector a total of 209 images were acquired in a rotational protocol. The technique parameters chosen for the FPD by the imaging system were used for the CMOS detector. The anti-scatter grid was removed and the incident scatter was kept the same for both detectors with identical collimator settings. The FPD images were reconstructed for the 10 cm x10 cm FOV and the CMOS images were reconstructed for a 3.84 cm x 3.84 cm FOV. Although the reconstructed images from the CMOS detector demonstrated comparable contrast to the FPD images, the reconstructed 3D images of the neuro stent clearly showed that the CMOS detector improved delineation of smaller objects such as the stent struts (~70 μm) compared to the FPD. Further development and the potential for substantial clinical impact are suggested.

  5. High Precision Bright-Star Astrometry with the USNO Astrometric CMOS Hybrid Camera System

    NASA Astrophysics Data System (ADS)

    Secrest, Nathan; Dudik, Rachel; Berghea, Ciprian; Hennessy, Greg; Dorland, Bryan

    2015-08-01

    While GAIA will provide excellent positional measurements of hundreds of millions of stars between 5 < mag < 20, an ongoing challenge in the field of high-precision differential astrometry is the positional accuracy of very bright stars (mag < 5), due to the enormous dynamic range between bright stars of interest, such as those in the Hipparcos catalog, and their background field stars, which are especially important for differential astrometry. Over the past few years, we have been testing the USNO Astrometric CMOS Hybrid Camera System (UAHC), which utilizes an H4RG-10 detector in windowing mode, as a possible solution to the NOFS USNO Bright Star Astrometric Database (UBAD). In this work, we discuss the results of an astrometric analysis of single-epoch Hipparcos data taken with the UAHC from the 1.55m Kaj Strand Astrometric Reflector at NOFS from June 27-30, 2014. We discuss the calibration of this data, as well as an astrometric analysis pipeline we developed that will enable multi-epoch differential and absolute astrometry with the UAHC. We find that while the overall differential astrometric stability of data taken with the UAHC is good (5-10 mas single-measurement precision) and comparable to other ground-based astrometric camera systems, bright stars in the detector window suffer from several systematic effects, such as insufficient window geometry and centroiding failures due to read-out artifacts—both of which can be significantly improved with modifications to the electronics, read-out speed and microcode.

  6. Active control system for high speed windmills

    DOEpatents

    Avery, D.E.

    1988-01-12

    A pump stroke is matched to the operating speed of a high speed windmill. The windmill drives a hydraulic pump for a control. Changes in speed of a wind driven shaft open supply and exhaust valves to opposite ends of a hydraulic actuator to lengthen and shorten an oscillating arm thereby lengthening and shortening the stroke of an output pump. Diminishing wind to a stall speed causes the valves to operate the hydraulic cylinder to shorten the oscillating arm to zero. A pressure accumulator in the hydraulic system provides the force necessary to supply the hydraulic fluid under pressure to drive the actuator into and out of the zero position in response to the windmill shaft speed approaching and exceeding windmill stall speed. 4 figs.

  7. Active control system for high speed windmills

    DOEpatents

    Avery, Don E.

    1988-01-01

    A pump stroke is matched to the operating speed of a high speed windmill. The windmill drives a hydraulic pump for a control. Changes in speed of a wind driven shaft open supply and exhaust valves to opposite ends of a hydraulic actuator to lengthen and shorten an oscillating arm thereby lengthening and shortening the stroke of an output pump. Diminishing wind to a stall speed causes the valves to operate the hydraulic cylinder to shorten the oscillating arm to zero. A pressure accumulator in the hydraulic system provides the force necessary to supply the hydraulic fluid under pressure to drive the actuator into and out of the zero position in response to the windmill shaft speed approaching and exceeding windmill stall speed.

  8. Design of high speed LVDS transceiver ICs

    NASA Astrophysics Data System (ADS)

    Jian, Xu; Zhigong, Wang; Xiaokang, Niu

    2010-07-01

    The design of low-power LVDS (low voltage differential signaling) transceiver ICs is presented. The LVDS transmitter integrates a common-mode feedback control on chip, while a specially designed pre-charge circuit is proposed to improve the speed of the circuit, making the highest data rate up to 622 Mb/s. For the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS receivers. In addition, the LVDS receiver also supports the failsafe function. The transceiver chips were verified with the CSMC 0.5-μm CMOS process. The measured results showed that, for the LVDS transmitter with the pre-charge technique proposed, the maximum data rate is higher than 622 Mb/s. The power consumption is 6 mA with a 5-V power supply. The LVDS receiver can work properly with a larger input common mode voltage (0.1-2.4 V) but a differential input voltage as low as 100 mV. The power consumption is only 1.2 mA with a 5-V supply at the highest data rate of 400 Mb/s. The chip set meets the TIA/EIA-644-A standards and shows its potential prospects in LVDS transmission systems.

  9. High-performance CMOS image sensors at BAE SYSTEMS Imaging Solutions

    NASA Astrophysics Data System (ADS)

    Vu, Paul; Fowler, Boyd; Liu, Chiao; Mims, Steve; Balicki, Janusz; Bartkovjak, Peter; Do, Hung; Li, Wang

    2012-07-01

    In this paper, we present an overview of high-performance CMOS image sensor products developed at BAE SYSTEMS Imaging Solutions designed to satisfy the increasingly challenging technical requirements for image sensors used in advanced scientific, industrial, and low light imaging applications. We discuss the design and present the test results of a family of image sensors tailored for high imaging performance and capable of delivering sub-electron readout noise, high dynamic range, low power, high frame rates, and high sensitivity. We briefly review the performance of the CIS2051, a 5.5-Mpixel image sensor, which represents our first commercial CMOS image sensor product that demonstrates the potential of our technology, then we present the performance characteristics of the CIS1021, a full HD format CMOS image sensor capable of delivering sub-electron read noise performance at 50 fps frame rate at full HD resolution. We also review the performance of the CIS1042, a 4-Mpixel image sensor which offers better than 70% QE @ 600nm combined with better than 91dB intra scene dynamic range and about 1 e- read noise at 100 fps frame rate at full resolution.

  10. Lubrication and cooling for high speed gears

    NASA Technical Reports Server (NTRS)

    Townsend, D. P.

    1985-01-01

    The problems and failures occurring with the operation of high speed gears are discussed. The gearing losses associated with high speed gearing such as tooth mesh friction, bearing friction, churning, and windage are discussed with various ways shown to help reduce these losses and thereby improve efficiency. Several different methods of oil jet lubrication for high speed gearing are given such as into mesh, out of mesh, and radial jet lubrication. The experiments and analytical results for the various methods of oil jet lubrication are shown with the strengths and weaknesses of each method discussed. The analytical and experimental results of gear lubrication and cooling at various test conditions are presented. These results show the very definite need of improved methods of gear cooling at high speed and high load conditions.

  11. Speed control with end cushion for high speed air cylinder

    DOEpatents

    Stevens, Wayne W.; Solbrig, Charles W.

    1991-01-01

    A high speed air cylinder in which the longitudinal movement of the piston within the air cylinder tube is controlled by pressurizing the air cylinder tube on the accelerating side of the piston and releasing pressure at a controlled rate on the decelerating side of the piston. The invention also includes a method for determining the pressure required on both the accelerating and decelerating sides of the piston to move the piston with a given load through a predetermined distance at the desired velocity, bringing the piston to rest safely without piston bounce at the end of its complete stroke.

  12. Damping Bearings In High-Speed Turbomachines

    NASA Technical Reports Server (NTRS)

    Von Pragenau, George L.

    1994-01-01

    Paper presents comparison of damping bearings with traditional ball, roller, and hydrostatic bearings in high-speed cryogenic turbopumps. Concept of damping bearings described in "Damping Seals and Bearings for a Turbomachine" (MFS-28345).

  13. Study of high speed photography measuring instrument

    NASA Astrophysics Data System (ADS)

    Zhang, Zhijun; Sun, Jiyu; Wu, Keyong

    2007-01-01

    High speed photograph measuring instrument is mainly used to measure and track the exterior ballistics, which can measure the flying position of the missile in the initial phase and trajectory. A new high speed photograph measuring instrument is presented in this paper. High speed photography measuring system records the parameters of object real-time, and then acquires the flying position and trajectory data of the missile in the initial phase. The detection distance of high speed photography is more than 4.5km, and the least detection distance is 450m, under the condition of well-balanced angular velocity and angular acceleration, program pilot track error less than 5'. This instrument also can measure and record the flying trail and trajectory parameters of plane's aero naval missile.

  14. Emulation of high-frequency substrate noise generation in CMOS digital circuits

    NASA Astrophysics Data System (ADS)

    Shimazaki, Shunsuke; Taga, Shota; Makita, Tetsuya; Azuma, Naoya; Miura, Noriyuki; Nagata, Makoto

    2014-01-01

    A noise emulator is based on the capacitor charging modeling and generates power and substrate noises expected in a CMOS digital integrated circuit. An off-chip near-magnetic-field sensor indirectly characterizes the distribution of clock timing and the adjustability of skews within on-chip digital circuits. An on-chip noise monitor captures power and substrate noise waveforms and evaluates noise frequency components in a wide frequency bandwidth. A 65 nm CMOS prototype demonstrated power and substrate noise generation in a variety of operating scenarios of digital integrated circuits. Power noise generation emulated at 125 MHz exhibits the enhancements of high-order harmonic components after deskewing at a timing resolution of 37.8 ps, as is specifically seen in more than 10 dB enlargement of the substrate noise component at 2.1 GHz.

  15. Analysis of neuronal cells of dissociated primary culture on high-density CMOS electrode array.

    PubMed

    Matsuda, Eiko; Mita, Takeshi; Hubert, Julien; Bakkum, Douglas; Frey, Urs; Hierlemann, Andreas; Takahashi, Hirokazu; Ikegami, Takashi

    2013-01-01

    Spontaneous development of neuronal cells was recorded around 4-34 days in vitro (DIV) with high-density CMOS array, which enables detailed study of the spatio-temporal activity of neuronal culture. We used the CMOS array to characterize the evolution of the inter-spike interval (ISI) distribution from putative single neurons, and estimate the network structure based on transfer entropy analysis, where each node corresponds to a single neuron. We observed that the ISI distributions gradually obeyed the power law with maturation of the network. The amount of information transferred between neurons increased at the early stage of development, but decreased as the network matured. These results suggest that both ISI and transfer entropy were very useful for characterizing the dynamic development of cultured neural cells over a few weeks. PMID:24109870

  16. Mixed material integration for high-speed applications

    NASA Astrophysics Data System (ADS)

    Krishnamurthy, Nicole Andrea

    A great demand for portable and highly integrated high speed electronic components and systems has recently surfaced as a result of the vast expansion of personal communications and other wireless applications. As more and more applications in personal communications require frequencies between 1 and 100 GHz, a reduction in the cost of III-V technology is necessary for a wide distribution of wireless products in the consumer market. III-V technology provides improved and unique functionality compared with silicon CMOS integrated circuit (IC) technology, yet current III-V technologies cannot meet all the demands of low cost, high levels of integration, low power, and performance because of high material costs and low yield compared with the current silicon technology. In this thesis, thin film mixed material integration is investigated as a method to increase functionality at lower cost. InP active devices are removed from the growth substrate and integrated onto other host substrates such as silicon via substrate removal. Characterization of these devices is performed. Also, thin film passive components via deposition on free standing polyimide are evaluated for lower cost and increased design freedom. By optimizing the passives and III-V active components separately and then integrating the two opens a new realm in mixed material integration.

  17. A High Vacuum High Speed Ion Pump

    DOE R&D Accomplishments Database

    Foster, J. S. Jr.; Lawrence, E. O.; Lofgren, E. J.

    1952-08-27

    A vacuum pump based on the properties of a magnetically collimated electric discharge is described. It has a speed in the range 3000 to 7000 liters a second and a base pressure in the order of 10{sup -6} mm. (auth)

  18. Superplane!High Speed Civil Transport

    NASA Technical Reports Server (NTRS)

    1998-01-01

    The High Speed Civil Transport (HSCT). This light-hearted promotional piece explains what the HSCT 'Superplane' is and what advantages it will have over current aircraft. As envisioned, the HSCT is a next-generation supersonic (faster than the speed of sound) passenger jet that would fly 300 passengers at more than 1,500 miles per hour -- more than twice the speed of sound. It will cross the Pacific or Atlantic in less than half the time of modern subsonic jets, and at a ticket price less than 20 percent above comparable, slower flights

  19. Propulsion concepts for high speed aircraft

    NASA Technical Reports Server (NTRS)

    Stull, F. D.; Jones, R. A.; Zima, W. P.

    1975-01-01

    A wide variety of potentially useful and effective airbreathing aircraft have been postulated to operate at speeds in excess of Mach 3.0 by NASA and the USAF. These systems include hydrogen-fueled transports of interest for very long ranges and airbreathing launch vehicles which are aircraft-type first stage candidates for future space shuttle systems. Other high speed airbreathing systems for possible future military applications include advanced reconnaissance and fighter/interceptor type aircraft and strategic systems. This paper presents (1) a chronology of Air Force technical activity on future propulsion concepts, (2) a status report on NASA research on scramjet technology for future systems which may require speeds above Mach 5, and (3) a description of a research vehicle by which advanced propulsion technology and other technologies related to high speed can be demonstrated.

  20. High speed switching in gases

    SciTech Connect

    Cassell, R.E.; Villa, F.

    1989-02-01

    A fast, efficient and reliable switch is the basic ingredient of a pulse power accelerator. Two switches have been proposed so far: the solid state switch, and the vacuum photodiode switch. The solid state version has been tested to some extent, albeit at low (few kilovolts) level, with risetime around 10 ps in the radial line transformer configuration. The vacuum photodiode is being investigated by Fisher and Rao at Brookhaven National Laboratory. Common to both switches is the need of a short laser pulse; near infrared for the solid state switch, and ultraviolet for the vacuum photodiode switch. Another common feature is the poor energy gain of these switches: the gain being the ratio between the electrical energy switched and the laser energy needed to drive the switch. For the solid state switch, calculations and experimental data show that the energy gain cannot exceed a value between 5 and 10. For the vacuum photodiode, the situation is somewhat similar, unless very high quantum efficiency, rugged photocathodes can be found. A closing switch also can be used to produce short pulses of rf at frequencies related to its closing time, using a well-known device called the frozen wave generator. For a risetime of the order of 30 ps, one could produce several Gigawatts of rf at Xband at very low cost. 12 refs., 12 figs.

  1. A high speed direct digital frequency synthesizer based on multi-channel structure

    NASA Astrophysics Data System (ADS)

    Ling, Yuan; Qiang, Zhang; Yin, Shi

    2015-06-01

    This paper presents a direct digital frequency synthesizer (DDFS) for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear digital-to-analog converter is implemented. The chip is fabricated in TSMC 130 nm CMOS technology with active area of 0.89 × 0.98 mm2 and total power consumption of 300 mW at a single 1.2 V supply voltage. The maximum operating speed is up to 2.0 GHz at room temperature.

  2. Speckle noise reduction in high speed polarization sensitive spectral domain optical coherence tomography

    NASA Astrophysics Data System (ADS)

    Götzinger, Erich; Pircher, Michael; Baumann, Bernhard; Schmoll, Tilman; Sattmann, Harald; Leitgeb, Rainer A.; Hitzenberger, Christoph K.

    2011-07-01

    We present a high speed polarization sensitive spectral domain optical coherence tomography system based on polarization maintaining fibers and two high speed CMOS line scan cameras capable of retinal imaging with up to 128 k A-lines/s. This high imaging speed strongly reduces motion artifacts and therefore averaging of several B-scans is possible, which strongly reduces speckle noise and improves image quality. We present several methods for averaging retardation and optic axis orientation, the best one providing a 5 fold noise reduction. Furthermore, a novel scheme of calculating images of degree of polarization uniformity is presented. We quantitatively compare the noise reduction depending on the number of averaged frames and discuss the limits of frame numbers that can usefully be averaged.

  3. Machine Vision Techniques For High Speed Videography

    NASA Astrophysics Data System (ADS)

    Hunter, David B.

    1984-11-01

    The priority associated with U.S. efforts to increase productivity has led to, among other things, the development of Machine Vision systems for use in manufacturing automation requirements. Many such systems combine solid state television cameras and data processing equipment to facilitate high speed, on-line inspection and real time dimensional measurement of parts and assemblies. These parts are often randomly oriented and spaced on a conveyor belt under continuous motion. Television imagery of high speed events has historically been achieved by use of pulsed (strobe) illumination or high speed shutter techniques synchronized with a camera's vertical blanking to separate write and read cycle operation. Lack of synchronization between part position and camera scanning in most on-line applications precludes use of this vertical interval illumination technique. Alternatively, many Machine Vision cameras incorporate special techniques for asynchronous, stop-motion imaging. Such cameras are capable of imaging parts asynchronously at rates approaching 60 hertz while remaining compatible with standard video recording units. Techniques for asynchronous, stop-motion imaging have not been incorporated in cameras used for High Speed Videography. Imaging of these events has alternatively been obtained through the utilization of special, high frame rate cameras to minimize motion during the frame interval. High frame rate cameras must undoubtedly be utilized for recording of high speed events occurring at high repetition rates. However, such cameras require very specialized, and often expensive, video recording equipment. It seems, therefore, that Machine Vision cameras with capability for asynchronous, stop-motion imaging represent a viable approach for cost effective video recording of high speed events occurring at repetition rates up to 60 hertz.

  4. Aerodynamic design on high-speed trains

    NASA Astrophysics Data System (ADS)

    Ding, San-San; Li, Qiang; Tian, Ai-Qin; Du, Jian; Liu, Jia-Li

    2016-04-01

    Compared with the traditional train, the operational speed of the high-speed train has largely improved, and the dynamic environment of the train has changed from one of mechanical domination to one of aerodynamic domination. The aerodynamic problem has become the key technological challenge of high-speed trains and significantly affects the economy, environment, safety, and comfort. In this paper, the relationships among the aerodynamic design principle, aerodynamic performance indexes, and design variables are first studied, and the research methods of train aerodynamics are proposed, including numerical simulation, a reduced-scale test, and a full-scale test. Technological schemes of train aerodynamics involve the optimization design of the streamlined head and the smooth design of the body surface. Optimization design of the streamlined head includes conception design, project design, numerical simulation, and a reduced-scale test. Smooth design of the body surface is mainly used for the key parts, such as electric-current collecting system, wheel truck compartment, and windshield. The aerodynamic design method established in this paper has been successfully applied to various high-speed trains (CRH380A, CRH380AM, CRH6, CRH2G, and the Standard electric multiple unit (EMU)) that have met expected design objectives. The research results can provide an effective guideline for the aerodynamic design of high-speed trains.

  5. Aerodynamic design on high-speed trains

    NASA Astrophysics Data System (ADS)

    Ding, San-San; Li, Qiang; Tian, Ai-Qin; Du, Jian; Liu, Jia-Li

    2016-01-01

    Compared with the traditional train, the operational speed of the high-speed train has largely improved, and the dynamic environment of the train has changed from one of mechanical domination to one of aerodynamic domination. The aerodynamic problem has become the key technological challenge of high-speed trains and significantly affects the economy, environment, safety, and comfort. In this paper, the relationships among the aerodynamic design principle, aerodynamic performance indexes, and design variables are first studied, and the research methods of train aerodynamics are proposed, including numerical simulation, a reduced-scale test, and a full-scale test. Technological schemes of train aerodynamics involve the optimization design of the streamlined head and the smooth design of the body surface. Optimization design of the streamlined head includes conception design, project design, numerical simulation, and a reduced-scale test. Smooth design of the body surface is mainly used for the key parts, such as electric-current collecting system, wheel truck compartment, and windshield. The aerodynamic design method established in this paper has been successfully applied to various high-speed trains (CRH380A, CRH380AM, CRH6, CRH2G, and the Standard electric multiple unit (EMU)) that have met expected design objectives. The research results can provide an effective guideline for the aerodynamic design of high-speed trains.

  6. High speed hydrogen/graphite interaction

    NASA Technical Reports Server (NTRS)

    Kelly, A. J.; Hamman, R.; Sharma, O. P.; Harrje, D. T.

    1974-01-01

    Various aspects of a research program on high speed hydrogen/graphite interaction are presented. Major areas discussed are: (1) theoretical predictions of hydrogen/graphite erosion rates; (2) high temperature, nonequilibrium hydrogen flow in a nozzle; and (3) molecular beam studies of hydrogen/graphite erosion.

  7. High Speed Digital Camera Technology Review

    NASA Technical Reports Server (NTRS)

    Clements, Sandra D.

    2009-01-01

    A High Speed Digital Camera Technology Review (HSD Review) is being conducted to evaluate the state-of-the-shelf in this rapidly progressing industry. Five HSD cameras supplied by four camera manufacturers participated in a Field Test during the Space Shuttle Discovery STS-128 launch. Each camera was also subjected to Bench Tests in the ASRC Imaging Development Laboratory. Evaluation of the data from the Field and Bench Tests is underway. Representatives from the imaging communities at NASA / KSC and the Optical Systems Group are participating as reviewers. A High Speed Digital Video Camera Draft Specification was updated to address Shuttle engineering imagery requirements based on findings from this HSD Review. This draft specification will serve as the template for a High Speed Digital Video Camera Specification to be developed for the wider OSG imaging community under OSG Task OS-33.

  8. CMOS solid-state photomultipliers for high energy resolution calorimeters

    NASA Astrophysics Data System (ADS)

    Johnson, Erik B.; Stapels, Christopher J.; Chen, Xiao Jie; Whitney, Chad; Chapman, Eric C.; Alberghini, Guy; Rines, Rich; Augustine, Frank; Miskimen, Rory; Lydon, Don; Christian, James

    2011-09-01

    High-energy, gamma-ray calorimetry typically employs large scintillation crystals coupled to photomultiplier tubes. These calorimeters are segmented to the limits associated with the costs of the crystals, photomultiplier tubes, and support electronics. A cost-effective means for construction of a calorimeter system is to use solid-state photomultipliers (SSPM) with front-end electronics, which is at least half the cost, but the SSPM must provide the necessary energy resolution defined by the physics goals. One experiment with plans to exploit this advantage is an upgrade to the PRIMEX experiment at Jefferson Laboratories. We have developed a large-area SSPM (1 cm × 1 cm) for readout of large scintillation crystals. As PbWO4 has excellent properties (small Molière radius and radiation hard) for high-energy gamma-rays (>1 GeV) but low light yields (~150 photons/MeV at 0 °C), evaluation of the SSPM and support readout electronics with LaBr3 provides a measure of the device performance. Using the known detection efficiency and dark current of the SSPM, an excess noise factor associated with after pulsing and cross talk is determined. The contribution to the energy resolution from the detector module is calculated as <1% for gamma rays greater than ~2.5 GeV (0.7% at 4.5 GeV).

  9. Architecture for High Speed Learning of Neural Network using Genetic Algorithm

    NASA Astrophysics Data System (ADS)

    Yoshikawa, Masaya; Terai, Hidekazu

    This paper discusses the architecture for high speed learning of Neural Network (NN) using Genetic Algorithm (GA). The proposed architecture prevents local minimum by using the GA characteristic of holding several individual populations for a population-based search and achieves high speed processing adopting dedicated hardware. To keep general purpose equal software processing, the proposed architecture can be flexible genetic operations on GA and is introduced both Sigmoid function and Heaviside function on NN. Furthermore, the proposed architecture is not optimized only the pipeline at evaluation phase on NN, but also optimized hierarchic pipelines on the whole at evolutionary phase. We have done the simulation, verification and logic synthesis using library of 0.35μm CMOS standard cell. Simulation results evaluating the proposed architecture show to achieve 22 times speed on average compared with software processing.

  10. Aerodynamics of High-Speed Trains

    NASA Astrophysics Data System (ADS)

    Schetz, Joseph A.

    This review highlights the differences between the aerodynamics of high-speed trains and other types of transportation vehicles. The emphasis is on modern, high-speed trains, including magnetic levitation (Maglev) trains. Some of the key differences are derived from the fact that trains operate near the ground or a track, have much greater length-to-diameter ratios than other vehicles, pass close to each other and to trackside structures, are more subject to crosswinds, and operate in tunnels with entry and exit events. The coverage includes experimental techniques and results and analytical and numerical methods, concentrating on the most recent information available.

  11. Congestion control of high-speed networks

    NASA Astrophysics Data System (ADS)

    1993-06-01

    We report on four areas of activity in the past six months. These areas include the following: (1) work on the control of integrated video and image traffic, both at the access to a network and within a high-speed network; (2) more general/game theoretic models for flow control in networks; (3) work on fault management for high-speed heterogeneous networks to improve survivability; and (4) work on all-optical (lightwave) networks of the future, designed to take advantage of the enormous bandwidth capability available at optical frequencies.

  12. Small, high-speed dataflow processor

    SciTech Connect

    Leler, W.

    1983-01-01

    Dataflow processors show much promise for high-speed computation at reasonable cost, but they are not without problems. The author discusses a processor design which combines ideas from dynamic dataflow architecture with those from reduced instruction set computers and proven large computers with parallel internal structures. The resulting processor includes a number of innovations, including operand destinations, killer tokens, I/O streams and closed-loop computation, which result in a small, relatively inexpensive processor capable of high-speed computation. The expected application areas of the processor include interactive computer graphics, signal processing, and artificial intelligence. 6 references.

  13. Spectrum acquisition of detonation based on CMOS

    NASA Astrophysics Data System (ADS)

    Li, Yan; Bai, Yonglin; Wang, Bo; Liu, Baiyu; Xue, Yingdong; Zhang, Wei; Gou, Yongsheng; Bai, Xiaohong; Qin, Junjun; Xian, Ouyang

    2010-10-01

    The detection of high-speed dynamic spectrum is the main method to acquire transient information. In order to obtain the large amount spectral data in real-time during the process of detonation, a CMOS-based system with high-speed spectrum data acquisition is designed. The hardware platform of the system is based on FPGA, and the unique characteristic of CMOS image sensors in the rolling shutter model is used simultaneously. Using FPGA as the master control chip of the system, not only provides the time sequence for CIS, but also controls the storage and transmission of the spectral data. In the experiment of spectral data acquisition, the acquired information is transmitted to the host computer through the CameraLink bus. The dynamic spectral curve is obtained after the subsequent processing. The experimental results demonstrate that this system is feasible in the acquisition and storage of high-speed dynamic spectrum information during the process of detonation.

  14. DAC 22 High Speed Civil Transport Model

    NASA Technical Reports Server (NTRS)

    1992-01-01

    Between tests, NASA research engineer Dave Hahne inspects a tenth-scale model of a supersonic transport model in the 30- by 60-Foot Tunnel at NASA Langley Research Center, Hampton, Virginia. The model is being used in support of NASA's High-Speed Research (HSR) program. Langley researchers are applying advance aerodynamic design methods to develop a wing leading-edge flap system which significantly improves low-speed fuel efficiency and reduces noise generated during takeoff operation. Langley is NASA's lead center for the agency's HSR program, aimed at developing technology to help U.S. industry compete in the rapidly expanding trans-oceanic transport market. A U.S. high-speed civil transport is expected to fly in about the year 2010. As envisioned, it would fly 300 passengers across the Pacific in about four hours at Mach 2.4 (approximately 1,600 mph/1950 kph) for a modest increase over business class fares.

  15. High-speed optical packet processing technologies based on novel optoelectronic devices

    NASA Astrophysics Data System (ADS)

    Takenouchi, Hirokazu; Takahashi, Ryo; Takahata, Kiyoto; Nakahara, Tatsushi; Suzuki, Hiroyuki

    2004-10-01

    To cope with the explosive growth of IP traffic, we must increase both the link capacity between nodes and the node throughput. These requirements have stimulated research on photonic networks that use optical technologies. Optical packet switching (OPS) is an attractive solution because it maximizes the use of the network bandwidth. The key functions in achieving such networks include synchronization, label processing, compression/decompression, regeneration, and buffering for high-speed asynchronous optical packets. However, it is impractical to implement such functions by using all-optical approaches. We have proposed a new optoelectronic system composed of a packet-by-packet optical clock-pulse generator (OCG), an all-optical serial-to-parallel converter (SPC), a photonic parallel-to-serial converter (PSC), and CMOS circuitry. The OCG provides a single optical pulse synchronized with the incoming packet, and the SPC carries out a parallel conversion of the incoming packet. The parallel converted data are processed in the smart CMOS circuit, and reconstructed into an optical packet by the photonic PSC. Our system makes it possible to carry out various functions for high-speed asynchronous optical packets. This paper reviews our recent work on high-speed optical packet processing technologies such as buffering, packet compression/decompression, and label swapping, which are key technologies for constructing future OPS networks.

  16. High Speed and Slow Motion: The Technology of Modern High Speed Cameras

    ERIC Educational Resources Information Center

    Vollmer, Michael; Mollmann, Klaus-Peter

    2011-01-01

    The enormous progress in the fields of microsystem technology, microelectronics and computer science has led to the development of powerful high speed cameras. Recently a number of such cameras became available as low cost consumer products which can also be used for the teaching of physics. The technology of high speed cameras is discussed,…

  17. High-Speed Schlieren Movies of Decelerators at Supersonic Speeds

    NASA Technical Reports Server (NTRS)

    1960-01-01

    Tests were conducted on several types of porous parachutes, a paraglider, and a simulated retrorocket. Mach numbers ranged from 1.8-3.0, porosity from 20-80 percent, and camera speeds from 1680-3000 feet per second (fps) in trials with porous parachutes. Trials of reefed parachutes were conducted at Mach number 2.0 and reefing of 12-33 percent at camera speeds of 600 fps. A flexible parachute with an inflatable ring in the periphery of the canopy was tested at Reynolds number 750,000 per foot, Mach number 2.85, porosity of 28 percent, and camera speed of 36oo fps. A vortex-ring parachute was tested at Mach number 2.2 and camera speed of 3000 fps. The paraglider, with a sweepback of 45 degrees at an angle of attack of 45 degrees was tested at Mach number 2.65, drag coefficient of 0.200, and lift coefficient of 0.278 at a camera speed of 600 fps. A cold air jet exhausting upstream from the center of a bluff body was used to simulate a retrorocket. The free-stream Mach number was 2.0, free-stream dynamic pressure was 620 lb/sq ft, jet-exit static pressure ratio was 10.9, and camera speed was 600 fps.

  18. Post-CMOS compatible high-throughput fabrication of AlN-based piezoelectric microcantilevers

    NASA Astrophysics Data System (ADS)

    Pérez-Campos, A.; Iriarte, G. F.; Hernando-Garcia, J.; Calle, F.

    2015-02-01

    A post-complementary metal oxide semiconductor (CMOS) compatible microfabrication process of piezoelectric cantilevers has been developed. The fabrication process is suitable for standard silicon technology and provides low-cost and high-throughput manufacturing. This work reports design, fabrication and characterization of piezoelectric cantilevers based on aluminum nitride (AlN) thin films synthesized at room temperature. The proposed microcantilever system is a sandwich structure composed of chromium (Cr) electrodes and a sputtered AlN film. The key issue for cantilever fabrication is the growth at room temperature of the AlN layer by reactive sputtering, making possible the innovative compatibility of piezoelectric MEMS devices with CMOS circuits already processed. AlN and Cr have been etched by inductively coupled plasma (ICP) dry etching using a BCl3-Cl2-Ar plasma chemistry. As part of the novelty of the post-CMOS micromachining process presented here, a silicon Si (1 0 0) wafer has been used as substrate as well as the sacrificial layer used to release the microcantilevers. In order to achieve this, the Si surface underneath the structure has been wet etched using an HNA (hydrofluoric acid + nitric acid + acetic acid) based solution. X-ray diffraction (XRD) characterization indicated the high crystalline quality of the AlN film. An atomic force microscope (AFM) has been used to determine the Cr electrode surface roughness. The morphology of the fabricated devices has been studied by scanning electron microscope (SEM). The cantilevers have been piezoelectrically actuated and their out-of-plane vibration modes were detected by vibrometry.

  19. High-speed data word monitor

    NASA Technical Reports Server (NTRS)

    Wirth, M. N.

    1975-01-01

    Small, portable, self-contained device provides high-speed display of bit pattern or any selected portion of transmission, can suppress filler patterns so that display is not updated, and can freeze display so that specific event may be observed in detail.

  20. Italian High-speed Airplane Engines

    NASA Technical Reports Server (NTRS)

    Bona, C F

    1940-01-01

    This paper presents an account of Italian high-speed engine designs. The tests were performed on the Fiat AS6 engine, and all components of that engine are discussed from cylinders to superchargers as well as the test set-up. The results of the bench tests are given along with the performance of the engines in various races.

  1. High-speed fiber grating pressure sensors

    NASA Astrophysics Data System (ADS)

    Udd, Eric; Rodriguez, George; Sandberg, Richard L.

    2014-06-01

    Fiber grating pressure sensors have been used to support pressure measurements associated with burn, deflagration and detonation of energetic materials. This paper provides an overview of this technology and serves as a companion paper to the application of this technology to measuring pressure during high speed impacts.

  2. Some problems of high speed travel

    PubMed Central

    Reader, D. C.

    1975-01-01

    Some aspects of high speed flight are examined to investigate whether increase in speed implies any lowering of safety standards. The problem of circadian dysrhythmia is discussed and methods of attenuating its effects are explained and some new hypnotic drugs are mentioned. The risk of decompression has been quantified and predictions have been made for risks in commercial service. Cosmic radiation in supersonic aircraft is unlikely to limit commercial operation or significantly increase risks to passengers and crew. The supersonic boom is likely to limit the terrain over which supersonic aircraft can operate and regulations covering engine noise on the ground could restrict some flights. PMID:1208294

  3. High Speed SPM of Functional Materials

    SciTech Connect

    Huey, Bryan D.

    2015-08-14

    The development and optimization of applications comprising functional materials necessitates a thorough understanding of their static and dynamic properties and performance at the nanoscale. Leveraging High Speed SPM and concepts enabled by it, efficient measurements and maps with nanoscale and nanosecond temporal resolution are uniquely feasible. This includes recent enhancements for topographic, conductivity, ferroelectric, and piezoelectric properties as originally proposed, as well as newly developed methods or improvements to AFM-based mechanical, friction, thermal, and photoconductivity measurements. The results of this work reveal fundamental mechanisms of operation, and suggest new approaches for improving the ultimate speed and/or efficiency, of data storage systems, magnetic-electric sensors, and solar cells.

  4. Sensor study for high speed autonomous operations

    NASA Astrophysics Data System (ADS)

    Schneider, Anne; La Celle, Zachary; Lacaze, Alberto; Murphy, Karl; Del Giorno, Mark; Close, Ryan

    2015-06-01

    As robotic ground systems advance in capabilities and begin to fulfill new roles in both civilian and military life, the limitation of slow operational speed has become a hindrance to the wide-spread adoption of these systems. For example, military convoys are reluctant to employ autonomous vehicles when these systems slow their movement from 60 miles per hour down to 40. However, these autonomous systems must operate at these lower speeds due to the limitations of the sensors they employ. Robotic Research, with its extensive experience in ground autonomy and associated problems therein, in conjunction with CERDEC/Night Vision and Electronic Sensors Directorate (NVESD), has performed a study to specify system and detection requirements; determined how current autonomy sensors perform in various scenarios; and analyzed how sensors should be employed to increase operational speeds of ground vehicles. The sensors evaluated in this study include the state of the art in LADAR/LIDAR, Radar, Electro-Optical, and Infrared sensors, and have been analyzed at high speeds to study their effectiveness in detecting and accounting for obstacles and other perception challenges. By creating a common set of testing benchmarks, and by testing in a wide range of real-world conditions, Robotic Research has evaluated where sensors can be successfully employed today; where sensors fall short; and which technologies should be examined and developed further. This study is the first step to achieve the overarching goal of doubling ground vehicle speeds on any given terrain.

  5. Technology needs for high speed rotorcraft (2)

    NASA Technical Reports Server (NTRS)

    Scott, Mark W.

    1991-01-01

    An analytical study was conducted to identify rotorcraft concepts best capable of combining a cruise speed of 350 to 450 knots with helicopter-like low speed attributes, and to define the technology advancements needed to make them viable by the year 2000. A systematic approach was used to compare the relative attributes and mission gross weights for a wide range of concepts, resulting in a downselect to the most promising concept/mission pairs. For transport missions, tilt-wing and variable diameter tilt-rotor (VDTR) concepts were found to be superior. For a military scout/attack role, the VDTR was best, although a shrouded rotor concept could provide a highly agile, low observable alternative if its weight empty fraction could be reduced. A design speed of 375 to 425 knots was found to be the maximum desirable for transport missions, with higher speed producing rapidly diminishing benefits in productivity. The key technologies that require advancement to make the tilt-wing and VDTR concepts viable are in the areas of wing and proprotor aerodynamics, efficient structural design, flight controls, refinement of the geared flap pitch control system, expansion of the speed/descent envelope, and the structural and aerodynamic tradeoffs of wing thickness and forward sweep. For the shrouded rotor, weight reduction is essential, particularly with respect to the mechanism for covering the rotor in cruise.

  6. Safety issues in high speed machining

    NASA Astrophysics Data System (ADS)

    1994-05-01

    There are several risks related to High-Speed Milling, but they have not been systematically determined or studied so far. Increased loads by high centrifugal forces may result in dramatic hazards. Flying tools or fragments from a tool with high kinetic energy may damage surrounding people, machines and devices. In the project, mechanical risks were evaluated, theoretic values for kinetic energies of rotating tools were calculated, possible damages of the flying objects were determined and terms to eliminate the risks were considered. The noise levels of the High-Speed Machining center owned by the Helsinki University of Technology (HUT) and the Technical Research Center of Finland (VTT) in practical machining situation were measured and the results were compared to those after basic preventive measures were taken.

  7. High speed printing with polygon scan heads

    NASA Astrophysics Data System (ADS)

    Stutz, Glenn

    2016-03-01

    To reduce and in many cases eliminate the costs associated with high volume printing of consumer and industrial products, this paper investigates and validates the use of the new generation of high speed pulse on demand (POD) lasers in concert with high speed (HS) polygon scan heads (PSH). Associated costs include consumables such as printing ink and nozzles, provisioning labor, maintenance and repair expense as well as reduction of printing lines due to high through put. Targets that are applicable and investigated include direct printing on plastics, printing on paper/cardboard as well as printing on labels. Market segments would include consumer products (CPG), medical and pharmaceutical products, universal ID (UID), and industrial products. In regards to the POD lasers employed, the wavelengths include UV(355nm), Green (532nm) and IR (1064nm) operating within the repetition range of 180 to 250 KHz.

  8. CMOS Amperometric ADC With High Sensitivity, Dynamic Range and Power Efficiency for Air Quality Monitoring.

    PubMed

    Li, Haitao; Boling, C Sam; Mason, Andrew J

    2016-08-01

    Airborne pollutants are a leading cause of illness and mortality globally. Electrochemical gas sensors show great promise for personal air quality monitoring to address this worldwide health crisis. However, implementing miniaturized arrays of such sensors demands high performance instrumentation circuits that simultaneously meet challenging power, area, sensitivity, noise and dynamic range goals. This paper presents a new multi-channel CMOS amperometric ADC featuring pixel-level architecture for gas sensor arrays. The circuit combines digital modulation of input currents and an incremental Σ∆ ADC to achieve wide dynamic range and high sensitivity with very high power efficiency and compact size. Fabricated in 0.5 [Formula: see text] CMOS, the circuit was measured to have 164 dB cross-scale dynamic range, 100 fA sensitivity while consuming only 241 [Formula: see text] and 0.157 [Formula: see text] active area per channel. Electrochemical experiments with liquid and gas targets demonstrate the circuit's real-time response to a wide range of analyte concentrations. PMID:27352395

  9. Novel source follower transistor structure without lightly doped drain for high performance CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Song, Hyeong-Sub; Kwon, Sung-Kyu; Jeon, So-Ra; Oh, Dong-Jun; Lee, Ga-Won; Lee, Hi-Deok

    2016-08-01

    To realize high-resolution pixels in the CMOS image sensor, it is necessary to reduce low-frequency noise, particularly random telegraph signal (RTS) noise of the source-follower transistor (SFT). To achieve less relative variation of drain noise current, ΔI D/I D, a metal–oxide–semiconductor field-effect transistor structure without the lightly doped drain (LDD) for the SFT transistor is proposed. Then, a comparison of RTS noise characteristics between the proposed SFT structure without LDD and the conventional SFT structure with LDD was conducted. Although the RTS noise occurrence probability of the proposed SFT structure without LDD is somewhat greater than that of the conventional SFT structure with LDD, the amplitude of relative variation of drain noise current of the proposed SFT structure is significantly less than that of the conventional SFT. Despite changes in several factors in the proposed SFT, such as effective channel length, trap depth profile in gate oxide, and random dopant fluctuation (RDF), it is believed that the change of trap depth profile is a primary factor for the improved RTS characteristic. Therefore, the proposed SFT is highly desirable for the high-resolution CMOS image sensor.

  10. Data Capture Technique for High Speed Signaling

    DOEpatents

    Barrett, Wayne Melvin; Chen, Dong; Coteus, Paul William; Gara, Alan Gene; Jackson, Rory; Kopcsay, Gerard Vincent; Nathanson, Ben Jesse; Vranas, Paylos Michael; Takken, Todd E.

    2008-08-26

    A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.

  11. High-speed civil transport study. Summary

    NASA Technical Reports Server (NTRS)

    1989-01-01

    A system of study of the potential for a high speed commercial transport aircraft addressed technology, economic, and environmental constraints. Market projections indicated a need for fleets of transport with supersonic or greater cruise speeds by the years 2000 to 2005. The associated design requirements called for a vehicle to carry 250 to 300 passengers over a range of 5000 to 6000 nautical miles. The study was initially unconstrained in terms of vehicle characteristics, such as cruise speed, propulsion systems, fuels, or structural materials. Analyses led to a focus on the most promising vehicle concepts. These were concepts that used a kerosene type fuel and cruised at Mach numbers between 2.0 to 3.2. Further systems study identified the impact of environmental constraints (for community noise, sonic boom, and engine emissions) on economic attractiveness and technological needs. Results showed that current technology cannot produce a viable high speed civil transport. Significant advances are needed to take off gross weight and allow for both economic attractiveness and environment acceptability. Specific technological requirements were identified to meet these needs.

  12. High-speed civil transport study

    NASA Technical Reports Server (NTRS)

    1989-01-01

    A system study of the potential for a high-speed commercial transport has addressed technological, economic, and environmental constraints. Market projections indicate a need for fleets of transports with supersonic or greater cruise speeds by the year 2000 to 2005. The associated design requirements called for a vehicle to carry 250 to 300 passengers over a range of 5,000 to 6,000 nautical miles. The study was initially unconstrained in terms of vehicle characteristic, such as cruise speed, propulsion systems, fuels, or structural materials. Analyses led to a focus on the most promising vehicle concepts. These were concepts that used a kerosene-type fuel and cruised at Mach numbers between 2.0 to 3.2. Further systems study identified the impact of environmental constraints (for community noise, sonic boom, and engine emissions) on economic attractiveness and technological needs. Results showed that current technology cannot produce a viable high-speed civil transport; significant advances are required to reduce takeoff gross weight and allow for both economic attractiveness and environmental accepatability. Specific technological requirements were identified to meet these needs.

  13. High dynamic range CMOS image sensor with pixel level ADC and in-situ image enhancement

    NASA Astrophysics Data System (ADS)

    Harton, Austin V.; Ahmed, Mohamed I.; Beuhler, Allyson; Castro, Francisco; Dawson, Linda M.; Herold, Barry W.; Kujawa, Gregory; Lee, King F.; Mareachen, Russell D.; Scaminaci, Tony J.

    2005-03-01

    We describe a CMOS image sensor with pixel level analog to digital conversion (ADC) having high dynamic range (>100db) and the capability of performing many image processing functions at the pixel level during image capture. The sensor has a 102x98 pixel array and is implemented in a 0.18um CMOS process technology. Each pixel is 15.5um x15.5um with 15% fill factor and is comprised of a comparator, two 10 bit memory registers and control logic. A digital to analog converter and system processor are located off-chip. The photodetector produces a photocurrent yielding a photo-voltage proportional to the impinging light intensity. Once the photo-voltage is less than a predetermined global reference voltage; a global code value is latched into the pixel data buffer. This process prevents voltage saturation resulting in high dynamic range imaging. Upon completion of image capture, a digital representation of the image exists at the pixel array, thereby, allowing image data to be accessed in a parallel fashion from the focal plane array. It is demonstrated that by appropriate variation of the global reference voltage with time, it is possible to perform, during image capture, thresholding and image enhancement operations, such as, contrast stretching in a parallel manner.

  14. High Speed Research Program Sonic Fatigue

    NASA Technical Reports Server (NTRS)

    Rizzi, Stephen A. (Technical Monitor); Beier, Theodor H.; Heaton, Paul

    2005-01-01

    The objective of this sonic fatigue summary is to provide major findings and technical results of studies, initiated in 1994, to assess sonic fatigue behavior of structure that is being considered for the High Speed Civil Transport (HSCT). High Speed Research (HSR) program objectives in the area of sonic fatigue were to predict inlet, exhaust and boundary layer acoustic loads; measure high cycle fatigue data for materials developed during the HSR program; develop advanced sonic fatigue calculation methods to reduce required conservatism in airframe designs; develop damping techniques for sonic fatigue reduction where weight effective; develop wing and fuselage sonic fatigue design requirements; and perform sonic fatigue analyses on HSCT structural concepts to provide guidance to design teams. All goals were partially achieved, but none were completed due to the premature conclusion of the HSR program. A summary of major program findings and recommendations for continued effort are included in the report.

  15. CAOS-CMOS camera.

    PubMed

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems. PMID:27410361

  16. Architectures and applications of high-speed vision

    NASA Astrophysics Data System (ADS)

    Watanabe, Yoshihiro; Oku, Hiromasa; Ishikawa, Masatoshi

    2014-11-01

    With the progress made in high-speed imaging technology, image processing systems that can process images at high frame rates, as well as their applications, are expected. In this article, we examine architectures for high-speed vision systems, and also dynamic image control, which can realize high-speed active optical systems. In addition, we also give an overview of some applications in which high-speed vision is used, including man-machine interfaces, image sensing, interactive displays, high-speed three-dimensional sensing, high-speed digital archiving, microvisual feedback, and high-speed intelligent robots.

  17. An ASIC memory buffer controller for a high speed disk system

    NASA Technical Reports Server (NTRS)

    Hodson, Robert F.; Campbell, Steve

    1993-01-01

    The need for large capacity, high speed mass memory storage devices has become increasingly evident at NASA during the past decade. High performance mass storage systems are crucial to present and future NASA systems. Spaceborne data storage system requirements have grown in response to the increasing amounts of data generated and processed by orbiting scientific experiments. Predictions indicate increases in the volume of data by orders of magnitude during the next decade. Current predictions are for storage capacities on the order of terabits (Tb), with data rates exceeding one gigabit per second (Gbps). As part of the design effort for a state of the art mass storage system, NASA Langley has designed a 144 CMOS ASIC to support high speed data transfers. This paper discusses the system architecture, ASIC design and some of the lessons learned in the development process.

  18. High-speed broadband tunable lasers

    NASA Astrophysics Data System (ADS)

    Adams, Laura E.; Nykolak, Gerald; Bethea, Clyde G.; Tanbun-Ek, Tawee; People, Roosevelt; Sergent, A. M.; Sciortino, Paul F., Jr.; Fullowan, Thomas R.

    1997-12-01

    New enabling technologies are needed for optical communication systems to accommodate rapidly growing traffic demands. Wavelength conversion and high-speed optical packet switching/routing will be key technology components for realizing more flexible and efficient optical networks. Lasers capable of wide-band, high-speed wavelength tuning will be essential to support these advanced functions. Also, many applications will require high launch powers in order to access an increasing number of users, nodes, or base stations. Hence, laser transmitters capable of suppressing stimulated Brillouin scattering (SBS) would be highly desirable. We have developed an ultrafast, broadband tunable laser, based on an electroabsorption modulator laser (EML), which exhibits wavelength switching speeds as fast as 56 ps. Here, we report system performance results on wavelength conversion high-speed optical packet switching, and SBS suppression using this device. We have tested multiple wavelength conversion sequences and demonstrated penalty-free transmission through two cascaded wavelength conversion stages including 200 km of standard non-DS fiber. When used to perform packet switching at 2.5 Gb/s, the tunable laser allows switching between optical packets on 4 wavelength channels in less than 1 bit period, thereby requiring no significant guardband. The modulated data packets have been transmitted through 200 km of non-DSF and yield open eye diagrams. The tunable laser has also been used to perform SBS suppression. We have measured SBS thresholds of approximately 25 dBm on 4 separate WDM channels. The required modulation signal is very small, 95 mVpp, and the residual AM is only approximately 1%.

  19. Survey Of High Speed Test Techniques

    NASA Astrophysics Data System (ADS)

    Gheewala, Tushar

    1988-02-01

    The emerging technologies for the characterization and production testing of high-speed devices and integrated circuits are reviewed. The continuing progress in the field of semiconductor technologies will, in the near future, demand test techniques to test 10ps to lOOps gate delays, 10 GHz to 100 GHz analog functions and 10,000 to 100,000 gates on a single chip. Clearly, no single test technique would provide a cost-effective answer to all the above demands. A divide-and-conquer approach based on a judicial selection of parametric, functional and high-speed tests will be required. In addition, design-for-test methods need to be pursued which will include on-chip test electronics as well as circuit techniques that minimize the circuit performance sensitivity to allowable process variations. The electron and laser beam based test technologies look very promising and may provide the much needed solutions to not only the high-speed test problem but also to the need for high levels of fault coverage during functional testing.

  20. High-speed massively parallel scanning

    DOEpatents

    Decker, Derek E.

    2010-07-06

    A new technique for recording a series of images of a high-speed event (such as, but not limited to: ballistics, explosives, laser induced changes in materials, etc.) is presented. Such technique(s) makes use of a lenslet array to take image picture elements (pixels) and concentrate light from each pixel into a spot that is much smaller than the pixel. This array of spots illuminates a detector region (e.g., film, as one embodiment) which is scanned transverse to the light, creating tracks of exposed regions. Each track is a time history of the light intensity for a single pixel. By appropriately configuring the array of concentrated spots with respect to the scanning direction of the detection material, different tracks fit between pixels and sufficient lengths are possible which can be of interest in several high-speed imaging applications.

  1. Pulse Detonation Engines for High Speed Flight

    NASA Technical Reports Server (NTRS)

    Povinelli, Louis A.

    2002-01-01

    Revolutionary concepts in propulsion are required in order to achieve high-speed cruise capability in the atmosphere and for low cost reliable systems for earth to orbit missions. One of the advanced concepts under study is the air-breathing pulse detonation engine. Additional work remains in order to establish the role and performance of a PDE in flight applications, either as a stand-alone device or as part of a combined cycle system. In this paper, we shall offer a few remarks on some of these remaining issues, i.e., combined cycle systems, nozzles and exhaust systems and thrust per unit frontal area limitations. Currently, an intensive experimental and numerical effort is underway in order to quantify the propulsion performance characteristics of this device. In this paper, we shall highlight our recent efforts to elucidate the propulsion potential of pulse detonation engines and their possible application to high-speed or hypersonic systems.

  2. The NASA High-Speed Research Program

    NASA Technical Reports Server (NTRS)

    Beam, Sherilee F.

    1992-01-01

    Since its inception, one of NASA's commitments has been to develop the technology to advance aeronautics. As such, a new High-Speed Research Program was activated to develop the technology for industry to build a High-Speed Civil Transport - a second generation Supersonic Transport (SST). The baseline for this program is the British Concorde, a major technological achievement for its time, but an aircraft which is now both technologically and economically outdated. Therefore, a second generation SST must satisfy environmental concerns and still be economically viable. In order to do this, it must have no significant effect on the ozone layer, meet Federal Air Regulation 36, Stage 3 for community noise, and have no perceptible sonic boom over populated areas. These three concerns are the focus of the research efforts in Phase 1 of the program and are the specific areas covered in the technical video report.

  3. High-speed tensile test instrument

    NASA Astrophysics Data System (ADS)

    Mott, P. H.; Twigg, J. N.; Roland, D. F.; Schrader, H. S.; Pathak, J. A.; Roland, C. M.

    2007-04-01

    A novel high-speed tensile test instrument is described, capable of measuring the mechanical response of elastomers at strain rates ranging from 10 to 1600 s-1 for strains through failure. The device employs a drop weight that engages levers to stretch a sample on a horizontal track. To improve dynamic equilibrium, a common problem in high speed testing, equal and opposite loading was applied to each end of the sample. Demonstrative results are reported for two elastomers at strain rates to 588 s-1 with maximum strains of 4.3. At the higher strain rates, there is a substantial inertial contribution to the measured force, an effect unaccounted for in prior works using the drop weight technique. The strain rates were essentially constant over most of the strain range and fill a three-decade gap in the data from existing methods.

  4. Manufacture and characterization of high Q-factor inductors based on CMOS-MEMS techniques.

    PubMed

    Yang, Ming-Zhi; Dai, Ching-Liang; Hong, Jin-Yu

    2011-01-01

    A high Q-factor (quality-factor) spiral inductor fabricated by the CMOS (complementary metal oxide semiconductor) process and a post-process was investigated. The spiral inductor is manufactured on a silicon substrate. A post-process is used to remove the underlying silicon substrate in order to reduce the substrate loss and to enhance the Q-factor of the inductor. The post-process adopts RIE (reactive ion etching) to etch the sacrificial oxide layer, and then TMAH (tetramethylammonium hydroxide) is employed to remove the silicon substrate for obtaining the suspended spiral inductor. The advantage of this post-processing method is its compatibility with the CMOS process. The performance of the spiral inductor is measured by an Agilent 8510C network analyzer and a Cascade probe station. Experimental results show that the Q-factor and inductance of the spiral inductor are 15 at 15 GHz and 1.8 nH at 1 GHz, respectively. PMID:22163726

  5. Manufacture and Characterization of High Q-Factor Inductors Based on CMOS-MEMS Techniques

    PubMed Central

    Yang, Ming-Zhi; Dai, Ching-Liang; Hong, Jin-Yu

    2011-01-01

    A high Q-factor (quality-factor) spiral inductor fabricated by the CMOS (complementary metal oxide semiconductor) process and a post-process was investigated. The spiral inductor is manufactured on a silicon substrate. A post-process is used to remove the underlying silicon substrate in order to reduce the substrate loss and to enhance the Q-factor of the inductor. The post-process adopts RIE (reactive ion etching) to etch the sacrificial oxide layer, and then TMAH (tetramethylammonium hydroxide) is employed to remove the silicon substrate for obtaining the suspended spiral inductor. The advantage of this post-processing method is its compatibility with the CMOS process. The performance of the spiral inductor is measured by an Agilent 8510C network analyzer and a Cascade probe station. Experimental results show that the Q-factor and inductance of the spiral inductor are 15 at 15 GHz and 1.8 nH at 1 GHz, respectively. PMID:22163726

  6. A high efficiency PWM CMOS class-D audio power amplifier

    NASA Astrophysics Data System (ADS)

    Zhangming, Zhu; Lianxi, Liu; Yintang, Yang; Han, Lei

    2009-02-01

    Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.

  7. Turbulence modeling for high speed compressible flows

    NASA Technical Reports Server (NTRS)

    Chandra, Suresh

    1993-01-01

    The following grant objectives were delineated in the proposal to NASA: to offer course work in computational fluid dynamics (CFD) and related areas to enable mechanical engineering students at North Carolina A&T State University (N.C. A&TSU) to pursue M.S. studies in CFD, and to enable students and faculty to engage in research in high speed compressible flows. Since no CFD-related activity existed at N.C. A&TSU before the start of the NASA grant period, training of students in the CFD area and initiation of research in high speed compressible flows were proposed as the key aspects of the project. To that end, graduate level courses in CFD, boundary layer theory, and fluid dynamics were offered. This effort included initiating a CFD course for graduate students. Also, research work was performed on studying compressibility effects in high speed flows. Specifically, a modified compressible dissipation model, which included a fourth order turbulent Mach number term, was incorporated into the SPARK code and verified for the air-air mixing layer case. The results obtained for this case were compared with a wide variety of experimental data to discern the trends in the mixing layer growth rates with varying convective Mach numbers. Comparison of the predictions of the study with the results of several analytical models was also carried out. The details of the research study are described in the publication entitled 'Compressibility Effects in Modeling Turbulent High Speed Mixing Layers,' which is attached to this report.

  8. Turbulence modeling for high speed compressible flows

    NASA Astrophysics Data System (ADS)

    Chandra, Suresh

    1993-08-01

    The following grant objectives were delineated in the proposal to NASA: to offer course work in computational fluid dynamics (CFD) and related areas to enable mechanical engineering students at North Carolina A&T State University (N.C. A&TSU) to pursue M.S. studies in CFD, and to enable students and faculty to engage in research in high speed compressible flows. Since no CFD-related activity existed at N.C. A&TSU before the start of the NASA grant period, training of students in the CFD area and initiation of research in high speed compressible flows were proposed as the key aspects of the project. To that end, graduate level courses in CFD, boundary layer theory, and fluid dynamics were offered. This effort included initiating a CFD course for graduate students. Also, research work was performed on studying compressibility effects in high speed flows. Specifically, a modified compressible dissipation model, which included a fourth order turbulent Mach number term, was incorporated into the SPARK code and verified for the air-air mixing layer case. The results obtained for this case were compared with a wide variety of experimental data to discern the trends in the mixing layer growth rates with varying convective Mach numbers. Comparison of the predictions of the study with the results of several analytical models was also carried out. The details of the research study are described in the publication entitled 'Compressibility Effects in Modeling Turbulent High Speed Mixing Layers,' which is attached to this report.

  9. Development of high-speed video cameras

    NASA Astrophysics Data System (ADS)

    Etoh, Takeharu G.; Takehara, Kohsei; Okinaka, Tomoo; Takano, Yasuhide; Ruckelshausen, Arno; Poggemann, Dirk

    2001-04-01

    Presented in this paper is an outline of the R and D activities on high-speed video cameras, which have been done in Kinki University since more than ten years ago, and are currently proceeded as an international cooperative project with University of Applied Sciences Osnabruck and other organizations. Extensive marketing researches have been done, (1) on user's requirements on high-speed multi-framing and video cameras by questionnaires and hearings, and (2) on current availability of the cameras of this sort by search of journals and websites. Both of them support necessity of development of a high-speed video camera of more than 1 million fps. A video camera of 4,500 fps with parallel readout was developed in 1991. A video camera with triple sensors was developed in 1996. The sensor is the same one as developed for the previous camera. The frame rate is 50 million fps for triple-framing and 4,500 fps for triple-light-wave framing, including color image capturing. Idea on a video camera of 1 million fps with an ISIS, In-situ Storage Image Sensor, was proposed in 1993 at first, and has been continuously improved. A test sensor was developed in early 2000, and successfully captured images at 62,500 fps. Currently, design of a prototype ISIS is going on, and, hopefully, will be fabricated in near future. Epoch-making cameras in history of development of high-speed video cameras by other persons are also briefly reviewed.

  10. High-speed pitch angle sorter

    NASA Technical Reports Server (NTRS)

    Keller, John W.; Torbert, R. B.; Vandiver, James

    1991-01-01

    A high-speed method was developed to compress the two-dimensional angular distribution of space particles gathered by space plasma instrumentation into the angle distribution, where the pitch angle is polar angle with respect to the ambient magnetic field. The pitch angle sorter can handle rates of up to 2 MHz and it is designed to accommodate high angular resolution plasma analyzers that are placed on a rotating spacecraft. This compression is achieved by relying on digitally encoded lookup tables to eliminate all arithmetic operations while applying the high symmetry of this compression to reduce the amount of digital memory.

  11. MM-122: High speed civil transport

    NASA Technical Reports Server (NTRS)

    Demarest, Bill; Anders, Kurt; Manchec, John; Yang, Eric; Overgaard, Dan; Kalkwarf, Mike

    1992-01-01

    The rapidly expanding Pacific Rim market along with other growing markets indicates that the future market potential for a high speed civil transport is great indeed. The MM-122 is the answer to the international market desire for a state of the art, long range, high speed civil transport. It will carry 250 passengers a distance of 5200 nm at over twice the speed of sound. The MM-122 is designed to incorporate the latest technologies in the areas of control systems, propulsions, aerodynamics, and materials. The MM-122 will accomplish these goals using the following design parameters. First, a double delta wing planform with highly swept canards and an appropriately area ruled fuselage will be incorporated to accomplish desired aerodynamic characteristics. Propulsion will be provided by four low bypass variable cycle turbofan engines. A quad-redundant fly-by-wire flight control system will be incorporated to provide appropriate static stability and level 1 handling qualities. Finally, the latest in conventional metallic and modern composite materials will be used to provide desired weight and performance characteristics. The MM-122 incorporates the latest in technology and cost minimization techniques to provide a viable solution to this future market potential.

  12. Testing of high speed network components

    SciTech Connect

    Wing, W.R.

    1997-06-30

    At the time of the start of this project, a battle was being fought between the computer networking technologies and telephone networking technologies. The telecommunications industry wanted to standardize on Asynchronous Transfer Mode (ATM) as the technology of choice for carrying all cross-country traffic. The computer industry wanted to use Packet Transfer Mode (PTM). The project had several goals, some unspoken. At the highest, most obvious level, the project goals were to test the high-speed components being developed by the computer technology industry. However, in addition, both industrial partners were having trouble finding markets for the high-speed networking technology they were developing and deploying. Thus, a part of the project was to demonstrate applications developed at Oak Ridge which would stretch the limits of the network, and thus demonstrate the utility of high-speed networks. Finally, an unspoken goal of the computer technology industry was to convince the telecommunications industry that packet switching was superior to cell switching. Conversely, the telecommunications industry hoped to see the computer technology industry`s packet switch fail to perform in a real-world test. Project was terminated early due to failure of one of the CRADA partners to deliver needed component.

  13. Technology needs for high speed rotorcraft (3)

    NASA Technical Reports Server (NTRS)

    Detore, Jack; Conway, Scott

    1991-01-01

    The spectrum of vertical takeoff and landing (VTOL) type aircraft is examined to determine which aircraft are most likely to achieve high subsonic cruise speeds and have hover qualities similar to a helicopter. Two civil mission profiles are considered: a 600-n.mi. mission for a 15- and a 30-passenger payload. Applying current technology, only the 15- and 30-passenger tiltfold aircraft are capable of attaining the 450-knot design goal. The two tiltfold aircraft at 450 knots and a 30-passenger tiltrotor at 375 knots were further developed for the Task II technology analysis. A program called High-Speed Total Envelope Proprotor (HI-STEP) is recommended to meet several of these issues based on the tiltrotor concept. A program called Tiltfold System (TFS) is recommended based on the tiltrotor concept. A task is identified to resolve the best design speed from productivity and demand considerations based on the technology that emerges from the recommended programs. HI-STEP's goals are to investigate propulsive efficiency, maneuver loads, and aeroelastic stability. Programs currently in progress that may meet the other technology needs include the Integrated High Performance Turbine Engine Technology (IHPTET) (NASA Lewis) and the Advanced Structural Concepts Program funded through NASA Langley.

  14. Large area CMOS bio-pixel array for compact high sensitive multiplex biosensing.

    PubMed

    Sandeau, Laure; Vuillaume, Cassandre; Contié, Sylvain; Grinenval, Eva; Belloni, Federico; Rigneault, Hervé; Owens, Roisin M; Fournet, Margaret Brennan

    2015-02-01

    A novel CMOS bio-pixel array which integrates assay substrate and assay readout is demonstrated for multiplex and multireplicate detection of a triplicate of cytokines with single digit pg ml(-1) sensitivities. Uniquely designed large area bio-pixels enable individual assays to be dedicated to and addressed by single pixels. A capability to simultaneously measure a large number of targets is provided by the 128 available pixels. Chemiluminescent assays are carried out directly on the pixel surface which also detects the emitted chemiluminescent photons, facilitating a highly compact sensor and reader format. The high sensitivity of the bio-pixel array is enabled by the high refractive index of silicon based pixels. This in turn generates a strong supercritical angle luminescence response significantly increasing the efficiency of the photon collection over conventional farfield modalities. PMID:25490928

  15. All aboard for high-speed rail

    SciTech Connect

    Herman, D.

    1996-09-01

    A sleek, bullet-nosed train whizzing across the countryside is a fairly common sight in many nations. Since the Train a Grande Vitesse (TGV)--the record-setting ``train with great speed``--was introduced in France in 1981, Germany, Japan, and other countries have joined the high-speed club. In addition, the Eurostar passenger train, which travels between Great Britain and France through the Channel Tunnel, can move at 186 miles per hour once it reaches French tracks. Despite the technology`s growth elsewhere, rapid rail travel has not been seen on US shores beyond a few test runs by various manufacturers. Before the end of the century, however, American train spotters will finally be able to see some very fast trains here too. In March, Washington, DC-based Amtrak announced the purchase of 18 American Flyer high-speed train sets for the Northeast Corridor, which stretches from Boston through new York to the nation`s capital. Furthermore, Florida will get its own system by 2004, and other states are now taking a look at the technology. The American Flyer--designed by Montreal-based Bombardier and TGV manufacturer GEC Alsthom Transport in Paris--should venture onto US rails by 1999. Traveling at up to 150 miles per hour, the American Flyer will cut the New York-Boston run from 4 1/2 hours to 3 hours and reduce New York-Washington trip time from 3 hours to less than 2 3/4. Amtrak hopes the new trains and better times will earn it a greater share of travelers from air shuttles and perhaps from Interstate 95. This article describes how technologies that tilt railcars and propel the world`s fastest trains will be merged into one train set for the American Flyer, Amtrak`s first trip along high-speed rails.

  16. High dynamic range CMOS-based mammography detector for FFDM and DBT

    NASA Astrophysics Data System (ADS)

    Peters, Inge M.; Smit, Chiel; Miller, James J.; Lomako, Andrey

    2016-03-01

    Digital Breast Tomosynthesis (DBT) requires excellent image quality in a dynamic mode at very low dose levels while Full Field Digital Mammography (FFDM) is a static imaging modality that requires high saturation dose levels. These opposing requirements can only be met by a dynamic detector with a high dynamic range. This paper will discuss a wafer-scale CMOS-based mammography detector with 49.5 μm pixels and a CsI scintillator. Excellent image quality is obtained for FFDM as well as DBT applications, comparing favorably with a-Se detectors that dominate the X-ray mammography market today. The typical dynamic range of a mammography detector is not high enough to accommodate both the low noise and the high saturation dose requirements for DBT and FFDM applications, respectively. An approach based on gain switching does not provide the signal-to-noise benefits in the low-dose DBT conditions. The solution to this is to add frame summing functionality to the detector. In one X-ray pulse several image frames will be acquired and summed. The requirements to implement this into a detector are low noise levels, high frame rates and low lag performance, all of which are unique characteristics of CMOS detectors. Results are presented to prove that excellent image quality is achieved, using a single detector for both DBT as well as FFDM dose conditions. This method of frame summing gave the opportunity to optimize the detector noise and saturation level for DBT applications, to achieve high DQE level at low dose, without compromising the FFDM performance.

  17. Cryogenic, high speed, turbopump bearing cooling requirements

    NASA Technical Reports Server (NTRS)

    Dolan, Fred J.; Gibson, Howard G.; Cannon, James L.; Cody, Joe C.

    1988-01-01

    Although the Space Shuttle Main Engine (SSME) has repeatedly demonstrated the capability to perform during launch, the High Pressure Oxidizer Turbopump (HPOTP) main shaft bearings have not met their 7.5 hour life requirement. A tester is being employed to provide the capability of subjecting full scale bearings and seals to speeds, loads, propellants, temperatures, and pressures which simulate engine operating conditions. The tester design permits much more elaborate instrumentation and diagnostics than could be accommodated in an SSME turbopump. Tests were made to demonstrate the facilities; and the devices' capabilities, to verify the instruments in its operating environment and to establish a performance baseline for the flight type SSME HPOTP Turbine Bearing design. Bearing performance data from tests are being utilized to generate: (1) a high speed, cryogenic turbopump bearing computer mechanical model, and (2) a much improved, very detailed thermal model to better understand bearing internal operating conditions. Parametric tests were also made to determine the effects of speed, axial loads, coolant flow rate, and surface finish degradation on bearing performance.

  18. Pressure Distribution Over Airfoils at High Speeds

    NASA Technical Reports Server (NTRS)

    Briggs, L J; Dryden, H L

    1927-01-01

    This report deals with the pressure distribution over airfoils at high speeds, and describes an extension of an investigation of the aerodynamic characteristics of certain airfoils which was presented in NACA Technical Report no. 207. The results presented in report no. 207 have been confirmed and extended to higher speeds through a more extensive and systematic series of tests. Observations were also made of the air flow near the surface of the airfoils, and the large changes in lift coefficients were shown to be associated with a sudden breaking away of the flow from the upper surface. The tests were made on models of 1-inch chord and comparison with the earlier measurements on models of 3-inch chord shows that the sudden change in the lift coefficient is due to compressibility and not to a change in the Reynolds number. The Reynolds number still has a large effect, however, on the drag coefficient. The pressure distribution observations furnish the propeller designer with data on the load distribution at high speeds, and also give a better picture of the air-flow changes.

  19. High-speed rolling deflectometer data evaluation

    NASA Astrophysics Data System (ADS)

    Andren, Peter

    1999-01-01

    The high-speed rolling deflectometer is one of the result of almost twenty year of research in pavement condition using laser technique. The latest research vehicle is the laser Road Deflection Tester, built in the mid-nineties using experiences from a prototype truck from the early nineties. Apart from the laser range finders used for finding used for finding the deflection, the truck is also equipped with optical speedometers for both longitudinal and transversal speed, accelerometers and force transducers on the rear wheel axle and a gyro for assessing the deviation. Presently, only the laser range finders are being used as the rest of the sensors has not been calibrated in a satisfying way. During the spring and summer of 1998 a first test program was carried out, and about twenty different roads were studied as a first step towards a more thorough investigation on a road network level. The results from this first major test with the high-speed rolling deflectometer are very promising and, even though many questions remains to be answered, the method has most certainly a strong potential. A general view of some different ways to evaluate the data, as well as more thorough evaluation of some specific roads, will be presented in this paper.

  20. A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders

    NASA Astrophysics Data System (ADS)

    Lee, Seungbeom; Lee, Hanho

    This paper presents a novel high-speed low-complexity pipelined degree-computationless modified Euclidean (pDCME) algorithm architecture for high-speed RS decoders. The pDCME algorithm allows elimination of the degree-computation so as to reduce hardware complexity and obtain high-speed processing. A high-speed RS decoder based on the pDCME algorithm has been designed and implemented with 0.13-μm CMOS standard cell technology in a supply voltage of 1.1V. The proposed RS decoder operates at a clock frequency of 660MHz and has a throughput of 5.3Gb/s. The proposed architecture requires approximately 15% fewer gate counts and a simpler control logic than architectures based on the popular modified Euclidean algorithm.

  1. Charged particle detection performances of CMOS pixel sensors produced in a 0.18 μm process with a high resistivity epitaxial layer

    NASA Astrophysics Data System (ADS)

    Senyukov, S.; Baudot, J.; Besson, A.; Claus, G.; Cousin, L.; Dorokhov, A.; Dulinski, W.; Goffe, M.; Hu-Guo, C.; Winter, M.

    2013-12-01

    The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50 μm thin CMOS Pixel Sensors (CPS) covering either the three innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35 μm CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJazz 0.18 μm CMOS process were studied with the help of the first prototype chip MIMOSA 32. The beam tests performed with negative pions of 120 GeV/c at the CERN-SPS allowed to measure a signal-to-noise ratio (SNR) for the non-irradiated chip in the range between 22 and 32 depending on the pixel design. The chip irradiated with the combined dose of 1 MRad and 1013neq /cm2 was observed to yield an SNR ranging between 11 and 23 for coolant temperatures varying from 15 °C to 30 °C. These SNR values were measured to result in particle detection efficiencies above 99.5% and 98% before and after irradiation, respectively. These satisfactory results allow to validate the TowerJazz 0.18 μm CMOS process for the ALICE ITS upgrade.

  2. Experimental Studies on High Speed Air Intakes

    NASA Astrophysics Data System (ADS)

    Panigrahy, Amit Kumar; Muruganandam, T. M.

    All high speed air breathing engines require an inlet to decelerate air from free stream velocity to a lower velocity conducive to combustion. The inlet is designed to capture and deliver the required mass flow to combustion chamber with minimum pressure loss, along with minimum flow distortion. Inlet buzz can occur due to several reasons, such as large internal area contraction ratio, serious shock-boundary layer interactions, and high back pressure. Inlet buzz is detrimental to thrust and can even cause structural damage. Thus a detailed back pressure and over contraction based study of inlet behavior is needed.

  3. An Analog Gamma Correction Scheme for High Dynamic Range CMOS Logarithmic Image Sensors

    PubMed Central

    Cao, Yuan; Pan, Xiaofang; Zhao, Xiaojin; Wu, Huisi

    2014-01-01

    In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO) based analog-to-digital converter (ADC) to perform the gamma correction during the analog-to-digital conversion. As a result, the quantization noise does not increase while the same high dynamic range of logarithmic image sensor is preserved. Moreover, by combining the gamma correction with the analog-to-digital conversion, the silicon area and overall power consumption can be greatly reduced. The proposed gamma correction scheme is validated by the reported simulation results and the experimental results measured for our designed test structure, which is fabricated with 0.35 μm standard complementary-metal-oxide-semiconductor (CMOS) process. PMID:25517692

  4. An analog gamma correction scheme for high dynamic range CMOS logarithmic image sensors.

    PubMed

    Cao, Yuan; Pan, Xiaofang; Zhao, Xiaojin; Wu, Huisi

    2014-01-01

    In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO) based analog-to-digital converter (ADC) to perform the gamma correction during the analog-to-digital conversion. As a result, the quantization noise does not increase while the same high dynamic range of logarithmic image sensor is preserved. Moreover, by combining the gamma correction with the analog-to-digital conversion, the silicon area and overall power consumption can be greatly reduced. The proposed gamma correction scheme is validated by the reported simulation results and the experimental results measured for our designed test structure, which is fabricated with 0.35 μm standard complementary-metal-oxide-semiconductor (CMOS) process. PMID:25517692

  5. A low-power CMOS WIA-PA transceiver with a high sensitivity GFSK demodulator

    NASA Astrophysics Data System (ADS)

    Tao, Yang; Yu, Jiang; Shengyou, Liu; Guiliang, Guo; Yuepeng, Yan

    2015-06-01

    This paper presents a low power, high sensitivity Gaussian frequency shift keying (GFSK) demodulator with a flexible frequency offset canceling method for wireless networks for industrial automation process automation (WIA-PA) transceiver fabricated in 0.18 μm CMOS technology. The receiver uses a low-IF (1.5 MHz) architecture, and the transmitter uses a sigma delta PLL based modulation with Gaussian low-pass filter for low power consumption. The active area of the demodulator is 0.14 mm2. Measurement results show that the proposed demodulator operates without harmonic distortion, deals with ± 180 kHz frequency offset, needs SNR only 18.5 dB at 0.1% bit-error rate (BER), and consumes no more than 0.26 mA from a 1.8 V power supply. Project supported by the National High Technology Research and Development Program of China (No. 2011AA040102).

  6. High speed SLVS transmitter and receiver

    NASA Astrophysics Data System (ADS)

    Bulbakov, I. S.; Atkin, E. V.; Voronin, A. G.

    2016-02-01

    Design of SLVS chip-to-chip communication transmitter/receiver IP block in 180 nm UMC MMRF CMOS process is presented. This block has been developed for study a data transmission over PCBs and/or electrical cables (lines) of few meters length at rates up to 320 Mb/s. Schematic for on-chip tests is also presented. This blocks are used for communication between front-end ASICs and DAQ system.

  7. High-Speed, High-Resolution Time-to-Digital Conversion

    NASA Technical Reports Server (NTRS)

    Katz, Richard; Kleyner, Igor; Garcia, Rafael

    2013-01-01

    This innovation is a series of time-tag pulses from a photomultiplier tube, featuring short time interval between pulses (e.g., 2.5 ns). Using the previous art, dead time between pulses is too long, or too much hardware is required, including a very-high-speed demultiplexer. A faster method is needed. The goal of this work is to provide circuits to time-tag pulses that arrive at a high rate using the hardwired logic in an FPGA - specifically the carry chain - to create what is (in effect) an analog delay line. High-speed pulses travel down the chain in a "wave." For instance, a pulse train has been demonstrated from a 1- GHz source reliably traveling down the carry chain. The size of the carry chain is over 10 ns in the time domain. Thus, multiple pulses will travel down the carry chain in a wave simultaneously. A register clocked by a low-skew clock takes a "snapshot" of the wave. Relatively simple logic can extract the pulses from the snapshot picture by detecting the transitions between logic states. The propagation delay of CMOS (complementary metal oxide semiconductor) logic circuits will differ and/or change as a result of temperature, voltage, age, radiation, and manufacturing variances. The time-to-digital conversion circuits can be calibrated with test signals, or the changes can be nulled by a separate on-die calibration channel, in a closed loop circuit.

  8. High speed GaN micro-light-emitting diode arrays for data communications

    NASA Astrophysics Data System (ADS)

    Watson, Scott; McKendry, Jonathan J. D.; Zhang, Shuailong; Massoubre, David; Rae, Bruce R.; Green, Richard P.; Gu, Erdan; Henderson, Robert K.; Kelly, A. E.; Dawson, Martin D.

    2012-10-01

    Micro light-emitting diode (micro-LED) arrays based on an AlInGaN structure have attracted much interest recently as light sources for data communications. Visible light communication (VLC), over free space or plastic optical fibre (POF), has become a very important technique in the role of data transmission. The micro-LEDs which are reported here contain pixels ranging in diameter from 14 to 84μm and can be driven directly using a high speed probe or via complementary metal-oxide semiconductor (CMOS) technology. The CMOS arrays allow for easy, computer control of individual pixels within arrays containing up to 16×16 elements. The micro-LEDs best suited for data transmission have peak emissions of 450nm or 520nm, however various other wavelengths across the visible spectrum can also be used. Optical modulation bandwidths of over 400MHz have been achieved as well as error-free (defined as an error rate of <1x10-10) data transmission using on-off keying (OOK) non-return-to-zero (NRZ) modulation at data rates of over 500Mbit/s over free space. Also, as a step towards a more practical multi-emitter data transmitter, the frequency response of a micro-LED integrated with CMOS circuitry was measured and found to be up to 185MHz. Despite the reduction in bandwidth compared to the bare measurements using a high speed probe, a good compromise is achieved from the additional control available to select each pixel. It has been shown that modulating more than one pixel simultaneously can increase the data rate. As work continues in this area, the aim will be to further increase the data transmission rate by modulating more pixels on a single device to transmit multiple parallel data channels simultaneously.

  9. High-Speed, high-power, switching transistor

    NASA Technical Reports Server (NTRS)

    Carnahan, D.; Ohu, C. K.; Hower, P. L.

    1979-01-01

    Silicon transistor rate for 200 angstroms at 400 to 600 volts combines switching speed of transistors with ruggedness, power capacity of thyristor. Transistor introduces unique combination of increased power-handling capability, unusally low saturation and switching losses, and submicrosecond switching speeds. Potential applications include high power switching regulators, linear amplifiers, chopper controls for high frequency electrical vehicle drives, VLF transmitters, RF induction heaters, kitchen cooking ranges, and electronic scalpels for medical surgery.

  10. High-speed Civil Transport Aircraft Emissions

    NASA Technical Reports Server (NTRS)

    Miake-Lye, Richard C.; Matulaitis, J. A.; Krause, F. H.; Dodds, Willard J.; Albers, Martin; Hourmouziadis, J.; Hasel, K. L.; Lohmann, R. P.; Stander, C.; Gerstle, John H.

    1992-01-01

    Estimates are given for the emissions from a proposed high speed civil transport (HSCT). This advanced technology supersonic aircraft would fly in the lower stratosphere at a speed of roughly Mach 1.6 to 3.2 (470 to 950 m/sec or 920 to 1850 knots). Because it would fly in the stratosphere at an altitude in the range of 15 to 23 km commensurate with its design speed, its exhaust effluents could perturb the chemical balance in the upper atmosphere. The first step in determining the nature and magnitude of any chemical changes in the atmosphere resulting from these proposed aircraft is to identify and quantify the chemically important species they emit. Relevant earlier work is summarized, dating back to the Climatic Impact Assessment Program of the early 1970s and current propulsion research efforts. Estimates are provided of the chemical composition of an HSCT's exhaust, and these emission indices are presented. Other aircraft emissions that are not due to combustion processes are also summarized; these emissions are found to be much smaller than the exhaust emissions. Future advances in propulsion technology, in experimental measurement techniques, and in understanding upper atmospheric chemistry may affect these estimates of the amounts of trace exhaust species or their relative importance.